`include "defines.svh"

module div_signed(
  input  logic        aclk,
  input  logic        s_axis_dividend_tvalid,
  input  logic [31:0] s_axis_dividend_tdata,
  input  logic        s_axis_divisor_tvalid,
  input  logic [31:0] s_axis_divisor_tdata,
  output logic        m_axis_dout_tvalid,
  output logic [63:0] m_axis_dout_tdata
);

  always_ff @(posedge aclk)
    if (s_axis_dividend_tvalid & s_axis_divisor_tvalid) begin
      m_axis_dout_tvalid <= 1'b1;
      m_axis_dout_tdata[63:32]  <= $signed(s_axis_dividend_tdata) / $signed(s_axis_divisor_tdata);
      m_axis_dout_tdata[31: 0]  <= $signed(s_axis_dividend_tdata) % $signed(s_axis_divisor_tdata);
    end else begin
      m_axis_dout_tvalid <= 0;
      m_axis_dout_tdata  <= 0;
    end


endmodule