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archive/bu
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5d61df40a6 | ||
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1e1725f436 | ||
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013104d616 | ||
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7835d63b0e | ||
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4e54a0a26b | ||
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5de9158326 |
3
.gitignore
vendored
3
.gitignore
vendored
@ -2,4 +2,5 @@ vivado.log
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vivado.jou
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.library_mapping.xml
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.project
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.settings
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.settings
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.vscode
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104
src/CP0/CP0.sv
104
src/CP0/CP0.sv
@ -13,6 +13,7 @@ module CP0 (
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// exception
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input EXCEPTION_t exception,
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output word_t EPC,
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output logic [3:0] CU,
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output logic Bev,
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output logic [19:0] EBase,
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@ -56,12 +57,14 @@ module CP0 (
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assign rf_cp0.Cause.IP[7:2] = {rf_cp0.Cause.TI | ext_int[5], ext_int[4:0]};
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assign rf_cp0.Cause.zero2 = 1'b0;
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assign rf_cp0.Cause.zero3 = 2'b00;
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assign rf_cp0.Status.zero1 = 9'b0;
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assign rf_cp0.Status.CU[3:1] = 3'b0;
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assign rf_cp0.Status.zero1 = 5'b0;
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assign rf_cp0.Status.zero2 = 6'b0;
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assign rf_cp0.Status.zero3 = 3'b0;
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assign rf_cp0.Status.zero4 = 2'b0;
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assign rf_cp0.EntryHi.zero = 5'b0;
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assign rf_cp0.Wired.zero = 29'b0;
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assign rf_cp0.Context.zero = 4'b0;
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assign rf_cp0.EntryLo1.zero = 6'b0;
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assign rf_cp0.EntryLo0.zero = 6'b0;
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assign rf_cp0.Random.zero = 29'b0;
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@ -87,45 +90,50 @@ module CP0 (
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always_ff @(posedge clk)
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if (rst) begin
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rf_cp0.Config.K0 = 3'b011;
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rf_cp0.EPC = 32'h0;
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rf_cp0.Cause.BD = 1'b0;
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rf_cp0.Cause.TI = 1'b0;
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rf_cp0.Cause.IP[1:0] = 2'b0;
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rf_cp0.Cause.ExcCode = 5'b0;
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rf_cp0.Status.Bev = 1'b1;
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rf_cp0.Status.IM = 8'b0;
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rf_cp0.Status.UM = 1'b0;
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rf_cp0.Status.EXL = 1'b0;
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rf_cp0.Status.IE = 1'b0;
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rf_cp0.Compare = 32'hFFFF_FFFF;
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rf_cp0.EntryHi.VPN2 = 19'b0;
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rf_cp0.EntryHi.ASID = 8'b0;
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rf_cp0.Count = 32'h0;
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rf_cp0.BadVAddr = 32'h0;
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rf_cp0.Wired.Wired = 3'b0;
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rf_cp0.EntryLo1.PFN = 20'b0;
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rf_cp0.EntryLo1.C = 3'b0;
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rf_cp0.EntryLo1.D = 1'b0;
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rf_cp0.EntryLo1.V = 1'b0;
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rf_cp0.EntryLo1.G = 1'b0;
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rf_cp0.EntryLo0.PFN = 20'b0;
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rf_cp0.EntryLo0.C = 3'b0;
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rf_cp0.EntryLo0.D = 1'b0;
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rf_cp0.EntryLo0.V = 1'b0;
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rf_cp0.EntryLo0.G = 1'b0;
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rf_cp0.Index.P = 1'b0;
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rf_cp0.Index.Index = 3'b0;
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rf_cp0.Random.Random = 3'b111;
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rf_cp0.Config.K0 = 3'b011;
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rf_cp0.EPC = 32'h0;
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rf_cp0.Cause.BD = 1'b0;
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rf_cp0.Cause.TI = 1'b0;
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rf_cp0.Cause.CE = 2'b0;
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rf_cp0.Cause.IP[1:0] = 2'b0;
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rf_cp0.Cause.ExcCode = 5'b0;
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rf_cp0.Status.CU[0] = 1'b1;
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rf_cp0.Status.Bev = 1'b1;
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rf_cp0.Status.IM = 8'b0;
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rf_cp0.Status.UM = 1'b0;
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rf_cp0.Status.EXL = 1'b0;
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rf_cp0.Status.IE = 1'b0;
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rf_cp0.Compare = 32'hFFFF_FFFF;
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rf_cp0.EntryHi.VPN2 = 19'b0;
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rf_cp0.EntryHi.ASID = 8'b0;
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rf_cp0.Count = 32'h0;
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rf_cp0.BadVAddr = 32'h0;
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rf_cp0.Wired.Wired = 3'b0;
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rf_cp0.Context.PTEBase = 9'b0;
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rf_cp0.Context.BadVPN2 = 19'b0;
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rf_cp0.EntryLo1.PFN = 20'b0;
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rf_cp0.EntryLo1.C = 3'b0;
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rf_cp0.EntryLo1.D = 1'b0;
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rf_cp0.EntryLo1.V = 1'b0;
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rf_cp0.EntryLo1.G = 1'b0;
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rf_cp0.EntryLo0.PFN = 20'b0;
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rf_cp0.EntryLo0.C = 3'b0;
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rf_cp0.EntryLo0.D = 1'b0;
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rf_cp0.EntryLo0.V = 1'b0;
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rf_cp0.EntryLo0.G = 1'b0;
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rf_cp0.Index.P = 1'b0;
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rf_cp0.Index.Index = 3'b0;
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rf_cp0.Random.Random = 3'b111;
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rf_cp0.EBase.EBase = 18'b0;
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rf_cp0.EBase.EBase = 18'b0;
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count_lo = 0;
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count_lo = 0;
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end else begin
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// count
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count_lo = ~count_lo;
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if (count_lo == 1) rf_cp0.Count = rf_cp0.Count + 1;
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rf_cp0.Random.Random = &rf_cp0.Random.Random ? rf_cp0.Wired.Wired
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: rf_cp0.Random.Random + 1'b1;
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if (en) begin
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case (addr)
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// 31: rf_cp0.DESAVE = wdata;
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@ -149,11 +157,12 @@ module CP0 (
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14: rf_cp0.EPC = wdata;
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13: rf_cp0.Cause.IP[1:0] = wdata[9:8];
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12: begin
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rf_cp0.Status.Bev = wdata[22];
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rf_cp0.Status.IM = wdata[15:8];
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rf_cp0.Status.UM = wdata[4];
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rf_cp0.Status.EXL = wdata[1];
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rf_cp0.Status.IE = wdata[0];
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rf_cp0.Status.CU[0] = wdata[28];
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rf_cp0.Status.Bev = wdata[22];
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rf_cp0.Status.IM = wdata[15:8];
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rf_cp0.Status.UM = wdata[4];
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rf_cp0.Status.EXL = wdata[1];
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rf_cp0.Status.IE = wdata[0];
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end
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11: begin
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rf_cp0.Cause.TI = 0;
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@ -166,9 +175,12 @@ module CP0 (
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9: rf_cp0.Count = wdata;
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8: rf_cp0.BadVAddr = wdata;
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// 7: rf_cp0.HWREna = wdata;
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6: rf_cp0.Wired.Wired = wdata[2:0];
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6: begin
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rf_cp0.Wired.Wired = wdata[2:0];
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rf_cp0.Random.Random = 3'b111;
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end
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// 5: rf_cp0.PageMask.Mask = wdata[24:13];
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// 4: rf_cp0.Context = wdata;
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4: rf_cp0.Context.PTEBase = wdata[31:23];
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3: begin
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rf_cp0.EntryLo1.PFN = wdata[25:6];
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rf_cp0.EntryLo1.C = wdata[5:3];
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@ -213,9 +225,6 @@ module CP0 (
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rf_cp0.Index.Index = tlb_Index.Index;
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end
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rf_cp0.Random.Random = &rf_cp0.Random.Random ? rf_cp0.Wired.Wired
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: rf_cp0.Random.Random + 1'b1;
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if (rf_cp0.Count == rf_cp0.Compare) rf_cp0.Cause.TI = 1;
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if (exception.ERET) rf_cp0.Status.EXL = 1'b0;
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@ -223,6 +232,7 @@ module CP0 (
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if (exception.ExcValid && rf_cp0.Status.EXL == 1'b0) begin
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rf_cp0.EPC = exception.Delay ? exception.EPC - 4 : exception.EPC;
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rf_cp0.Cause.BD = exception.Delay;
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rf_cp0.Cause.CE = exception.CE;
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rf_cp0.Cause.ExcCode = exception.ExcCode;
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rf_cp0.Status.EXL = 1'b1;
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@ -237,7 +247,8 @@ module CP0 (
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if ( exception.ExcCode == `EXCCODE_MOD
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| exception.ExcCode == `EXCCODE_TLBL
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| exception.ExcCode == `EXCCODE_TLBS) begin
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rf_cp0.EntryHi.VPN2 = exception.BadVAddr[31:13];
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rf_cp0.Context.BadVPN2 = exception.BadVAddr[31:13];
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rf_cp0.EntryHi.VPN2 = exception.BadVAddr[31:13];
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end
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end
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@ -275,7 +286,7 @@ module CP0 (
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6: rdata = rf_cp0.Wired;
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// 5: rdata = rf_cp0.PageMask;
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5: rdata = 32'h0;
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// 4: rdata = rf_cp0.Context;
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4: rdata = rf_cp0.Context;
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3: rdata = rf_cp0.EntryLo1;
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2: rdata = rf_cp0.EntryLo0;
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1: rdata = rf_cp0.Random;
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@ -284,6 +295,7 @@ module CP0 (
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endcase
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assign EPC = rf_cp0.EPC;
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assign CU = rf_cp0.Status.CU;
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assign Bev = rf_cp0.Status.Bev;
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assign EBase = rf_cp0.EBase[31:12];
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@ -267,60 +267,15 @@ module DCache (
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wdata2[i] = port.rdata;
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if (port.wvalid) begin
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case (port.sel1)
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2'b11: begin
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if (port.wstrb[3]) wdata1[i][127:120] = port.wdata[31:24];
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if (port.wstrb[2]) wdata1[i][119:112] = port.wdata[23:16];
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if (port.wstrb[1]) wdata1[i][111:104] = port.wdata[15: 8];
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if (port.wstrb[0]) wdata1[i][103: 96] = port.wdata[ 7: 0];
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end
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2'b10: begin
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if (port.wstrb[3]) wdata1[i][95:88] = port.wdata[31:24];
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if (port.wstrb[2]) wdata1[i][87:80] = port.wdata[23:16];
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if (port.wstrb[1]) wdata1[i][79:72] = port.wdata[15: 8];
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if (port.wstrb[0]) wdata1[i][71:64] = port.wdata[ 7: 0];
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end
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2'b01: begin
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if (port.wstrb[3]) wdata1[i][63:56] = port.wdata[31:24];
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if (port.wstrb[2]) wdata1[i][55:48] = port.wdata[23:16];
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if (port.wstrb[1]) wdata1[i][47:40] = port.wdata[15: 8];
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if (port.wstrb[0]) wdata1[i][39:32] = port.wdata[ 7: 0];
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end
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2'b00: begin
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if (port.wstrb[3]) wdata1[i][31:24] = port.wdata[31:24];
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if (port.wstrb[2]) wdata1[i][23:16] = port.wdata[23:16];
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if (port.wstrb[1]) wdata1[i][15: 8] = port.wdata[15: 8];
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if (port.wstrb[0]) wdata1[i][ 7: 0] = port.wdata[ 7: 0];
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end
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default: begin end
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endcase
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case (port.sel1)
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2'b11: begin
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if (port.wstrb[3]) wdata2[i][127:120] = port.wdata[31:24];
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if (port.wstrb[2]) wdata2[i][119:112] = port.wdata[23:16];
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if (port.wstrb[1]) wdata2[i][111:104] = port.wdata[15: 8];
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if (port.wstrb[0]) wdata2[i][103: 96] = port.wdata[ 7: 0];
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end
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2'b10: begin
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if (port.wstrb[3]) wdata2[i][95:88] = port.wdata[31:24];
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if (port.wstrb[2]) wdata2[i][87:80] = port.wdata[23:16];
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if (port.wstrb[1]) wdata2[i][79:72] = port.wdata[15: 8];
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if (port.wstrb[0]) wdata2[i][71:64] = port.wdata[ 7: 0];
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end
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2'b01: begin
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if (port.wstrb[3]) wdata2[i][63:56] = port.wdata[31:24];
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if (port.wstrb[2]) wdata2[i][55:48] = port.wdata[23:16];
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if (port.wstrb[1]) wdata2[i][47:40] = port.wdata[15: 8];
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if (port.wstrb[0]) wdata2[i][39:32] = port.wdata[ 7: 0];
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end
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2'b00: begin
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if (port.wstrb[3]) wdata2[i][31:24] = port.wdata[31:24];
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if (port.wstrb[2]) wdata2[i][23:16] = port.wdata[23:16];
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if (port.wstrb[1]) wdata2[i][15: 8] = port.wdata[15: 8];
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if (port.wstrb[0]) wdata2[i][ 7: 0] = port.wdata[ 7: 0];
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end
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default: begin end
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endcase
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if (port.wstrb[3]) wdata1[i][{port.sel1, 5'd24}+:8] = port.wdata[24+:8];
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if (port.wstrb[2]) wdata1[i][{port.sel1, 5'd16}+:8] = port.wdata[16+:8];
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if (port.wstrb[1]) wdata1[i][{port.sel1, 5'd08}+:8] = port.wdata[08+:8];
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if (port.wstrb[0]) wdata1[i][{port.sel1, 5'd00}+:8] = port.wdata[00+:8];
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if (port.wstrb[3]) wdata2[i][{port.sel1, 5'd24}+:8] = port.wdata[24+:8];
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if (port.wstrb[2]) wdata2[i][{port.sel1, 5'd16}+:8] = port.wdata[16+:8];
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if (port.wstrb[1]) wdata2[i][{port.sel1, 5'd08}+:8] = port.wdata[08+:8];
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if (port.wstrb[0]) wdata2[i][{port.sel1, 5'd00}+:8] = port.wdata[00+:8];
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end
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end
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end
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@ -84,7 +84,7 @@ module Controller (
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assign ctrl.MCtrl1.TLBP = ~inst[31] & inst[30] & ~inst[4] & inst[3];
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assign ctrl.MCtrl1.CACHE_OP = CacheOp_t'({inst[29] & inst[28] & inst[26] & inst[16], inst[29] & inst[28] & inst[26] & ~inst[20], inst[29] & inst[28] & inst[26] & ~inst[18] & (inst[20] | inst[19] | ~inst[16])});
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assign ctrl.Trap.TEN = ~inst[30] & ~inst[27] & (~inst[26] & ~inst[31] & ~inst[29] & ~inst[28] & inst[4] & inst[5] | inst[26] & ~inst[31] & ~inst[29] & ~inst[28] & inst[19]) | inst[30] & ~inst[29] & ~inst[31];
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assign ctrl.Trap.TEN = ~inst[29] & (~inst[26] & ~inst[30] & ~inst[31] & ~inst[28] & ~inst[27] & inst[4] & inst[5] | inst[26] & ~inst[31] & ~inst[28] & ~inst[27] & inst[19]);
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assign ctrl.Trap.TP = TrapOp_t'({~inst[26] & inst[2] | inst[26] & inst[18], ~inst[26] & inst[1] | inst[26] & inst[17]});
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|
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logic mov, rw, eqz;
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|
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@ -33,6 +33,7 @@ module Datapath (
|
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output word_t C0_wdata,
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output EXCEPTION_t C0_exception,
|
||||
input word_t C0_ERETPC,
|
||||
input logic [3:0] C0_CU,
|
||||
input logic C0_Bev,
|
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input logic [19:0] C0_EBase,
|
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input logic C0_kernel,
|
||||
@ -124,8 +125,8 @@ module Datapath (
|
||||
|
||||
logic D_IA_valid;
|
||||
logic D_IB_valid;
|
||||
logic D_IA_iv;
|
||||
logic D_IB_iv;
|
||||
logic D_IA_ri;
|
||||
logic D_IB_ri;
|
||||
|
||||
logic D_IA_TLBRefill;
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logic D_IA_TLBInvalid;
|
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@ -228,7 +229,7 @@ module Datapath (
|
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word_t M_I0_DIVUHB;
|
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word_t M_I0_DIVULB;
|
||||
|
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logic [5:0] M_I0_MULT_CNTR;
|
||||
logic M_I0_MULT_CNTR;
|
||||
|
||||
word_t M_I0_MULTH;
|
||||
word_t M_I0_MULTL;
|
||||
@ -448,51 +449,61 @@ module Datapath (
|
||||
);
|
||||
|
||||
// D.Exc
|
||||
instr_valid D_IA_instr_valid (
|
||||
decoder2 D_IA_decoder2 (
|
||||
D.IA_inst,
|
||||
D_IA_iv
|
||||
C0_CU,
|
||||
C0_kernel,
|
||||
D_IA_ri,
|
||||
D_IA_cpu,
|
||||
D.IA_CE
|
||||
);
|
||||
instr_valid D_IB_instr_valid (
|
||||
decoder2 D_IB_decoder2 (
|
||||
D.IB_inst,
|
||||
D_IB_iv
|
||||
C0_CU,
|
||||
C0_kernel,
|
||||
D_IB_ri,
|
||||
D_IB_cpu,
|
||||
D.IB_CE
|
||||
);
|
||||
|
||||
// INFO: Merge "pc[1:0] != 2'b00" into AddressError
|
||||
assign D.IA_ExcValid = D_IA_valid & ( D.IA_pc[1:0] != 2'b00
|
||||
| ~D_IA_iv
|
||||
| D_IA_ri | D_IA_cpu
|
||||
| D_IA_TLBRefill | D_IA_TLBInvalid
|
||||
| D_IA_AddressError
|
||||
| D.IA.SYSCALL | D.IA.BREAK | D.IA.ERET
|
||||
| D.IA.PRV & ~C0_kernel);
|
||||
assign D.IA_ERET = D_IA_valid & D.IA_pc[1:0] == 2'b00 & ~D_IA_TLBRefill & ~D_IA_TLBInvalid & ~D_IA_AddressError & D_IA_iv & D.IA.ERET;
|
||||
assign D.IA_ERET = D_IA_valid & D.IA_pc[1:0] == 2'b00 & ~D_IA_TLBRefill & ~D_IA_TLBInvalid & ~D_IA_AddressError & ~D_IA_ri & ~D_IA_cpu & D.IA.ERET;
|
||||
assign D.IA_REFILL = D_IA_valid & D.IB_pc[1:0] == 2'b00 & D_IA_TLBRefill;
|
||||
assign D.IA_ExcCode = D.IA_pc[1:0] != 2'b00 | D_IA_AddressError ? `EXCCODE_ADEL
|
||||
: D_IA_TLBRefill ? `EXCCODE_TLBL
|
||||
: D_IA_TLBInvalid ? `EXCCODE_TLBL
|
||||
: ~D_IA_iv ? `EXCCODE_RI
|
||||
: D_IA_cpu ? `EXCCODE_CPU
|
||||
: D_IA_ri ? `EXCCODE_RI
|
||||
: ~D.IA_inst[30] & D.IA_inst[0] ? `EXCCODE_BP
|
||||
: ~D.IA_inst[30] & ~D.IA_inst[0] ? `EXCCODE_SYS
|
||||
: `EXCCODE_CPU;
|
||||
: `EXCCODE_RI;
|
||||
|
||||
assign D.IB_ExcValid = D_IB_valid & ( D.IB_pc[1:0] != 2'b00
|
||||
| ~D_IB_iv
|
||||
| D_IB_ri | D_IB_cpu
|
||||
| D_IB_TLBRefill | D_IB_TLBInvalid
|
||||
| D_IB_AddressError
|
||||
| D.IB.SYSCALL | D.IB.BREAK | D.IB.ERET
|
||||
| D.IB_Delay & D.IB.BJRJ
|
||||
| D.IB.PRV & ~C0_kernel);
|
||||
assign D.IB_ERET = D_IB_valid & D.IB_pc[1:0] == 2'b00 & ~D_IB_TLBRefill & ~D_IB_TLBInvalid & ~D_IB_AddressError & D_IB_iv & D.IB.ERET & ~D.IB_Delay;
|
||||
assign D.IB_ERET = D_IB_valid & D.IB_pc[1:0] == 2'b00 & ~D_IB_TLBRefill & ~D_IB_TLBInvalid & ~D_IB_AddressError & ~D_IB_ri & ~D_IB_cpu & D.IB.ERET & ~D.IB_Delay;
|
||||
assign D.IB_REFILL = D_IB_valid & D.IB_pc[1:0] == 2'b00 & D_IB_TLBRefill;
|
||||
// EXCCODE_BP and EXCCODE_SYSCALL -> exc.txt
|
||||
assign D.IB_ExcCode = D.IB_pc[1:0] != 2'b00 | D_IB_AddressError ? `EXCCODE_ADEL
|
||||
: D_IB_TLBRefill ? `EXCCODE_TLBL
|
||||
: D_IB_TLBInvalid ? `EXCCODE_TLBL
|
||||
: ~D_IB_iv ? `EXCCODE_RI
|
||||
: D_IB_cpu ? `EXCCODE_CPU
|
||||
: D_IB_ri ? `EXCCODE_RI
|
||||
: D.IB.ERET ? `EXCCODE_RI
|
||||
: D.IB_Delay & D.IB.BJRJ ? `EXCCODE_RI
|
||||
: ~D.IB_inst[30] & D.IB_inst[0] ? `EXCCODE_BP
|
||||
: ~D.IB_inst[30] & ~D.IB_inst[0] ? `EXCCODE_SYS
|
||||
: `EXCCODE_CPU;
|
||||
: `EXCCODE_RI;
|
||||
assign D.IB_Delay = D.IA.BJRJ;
|
||||
|
||||
// D.Dispatch
|
||||
@ -535,6 +546,15 @@ module Datapath (
|
||||
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl1.MWR & ~D.IA.DP1
|
||||
// Not Arith -> LWL/LWR
|
||||
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & |D.IB.MCtrl1.ALR & ~D.IA.DP1
|
||||
// Any -> MOVN/MOVZ
|
||||
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.DT
|
||||
// Arith -> MOVN/MOVZ
|
||||
| E.I0.WCtrl.RW & D.IB.RT == E.I0.RD & D.IB.DT
|
||||
| E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & D.IB.DT
|
||||
// Not Arith -> MOVN/MOVZ
|
||||
| M.I0.WCtrl.RW & D.IB.RT == M.I0.RD & D.IB.DT & ~M.I0.MCtrl.RS0[2]
|
||||
// Load -> MOVN/MOVZ
|
||||
| M.I1.WCtrl.RW & D.IB.RT == M.I1.RD & D.IB.DT & M.I1.MCtrl.MR
|
||||
// CP0 Execution Hazards
|
||||
// Hazards Related to the TLB
|
||||
| D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBR & D.IA.MCtrl0.C0D == C0_INDEX
|
||||
@ -579,6 +599,7 @@ module Datapath (
|
||||
assign D.I0.ERET = D.A ? D.IB_ERET : D.IA_ERET;
|
||||
assign D.I0.REFILL = D.A ? D.IB_REFILL : D.IA_REFILL;
|
||||
assign D.I0.ExcCode = D.A ? D.IB_ExcCode : D.IA_ExcCode;
|
||||
assign D.I0.CE = D.A ? D.IB_CE : D.IA_CE;
|
||||
assign D.I0.Delay = D.A ? D.IB_Delay : D.IA_Delay;
|
||||
assign D.I0.OFA = D.A ? D.IB.OFA : D.IA.OFA;
|
||||
assign D.I0.RS = D.A ? D.IB.RS : D.IA.RS;
|
||||
@ -595,6 +616,7 @@ module Datapath (
|
||||
assign D_I1_go = D.A ? D_IA_go : D_IB_go;
|
||||
assign D.I1.pc = D.A ? D.IA_pc : D.IB_pc;
|
||||
assign D.I1.ExcValid = D.A ? D.IA_ExcValid : D.IB_ExcValid;
|
||||
assign D.I1.CE = D.A ? D.IA_CE : D.IB_CE;
|
||||
assign D.I1.ERET = D.A ? D.IA_ERET : D.IB_ERET;
|
||||
assign D.I1.REFILL = D.A ? D.IA_REFILL : D.IB_REFILL;
|
||||
assign D.I1.ExcCode = D.A ? D.IA_ExcCode : D.IB_ExcCode;
|
||||
@ -612,6 +634,22 @@ module Datapath (
|
||||
assign D.I1.RD = D.A ? D.IA.RD : D.IB.RD;
|
||||
assign D.I1.WCtrl = D.A ? D.IA.WCtrl : D.IB.WCtrl;
|
||||
|
||||
int fd;
|
||||
initial begin
|
||||
fd = $fopen("my_trace.txt", "w");
|
||||
if (!fd) $finish;
|
||||
end
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (~rst)
|
||||
$fdisplay(fd, "%d %d %d 0x%h 0x%h", D_go, D_I0_go, D_I1_go, D.I0.pc, D.I1.pc);
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (~rst)
|
||||
if (debug_wb_pc == 32'hbfc00100 || debug_wb1_pc == 32'hbfc00100)
|
||||
$fclose(fd);
|
||||
|
||||
|
||||
// D.Forwarding
|
||||
assign D_IA_FS_M_I0 = M.I0.WCtrl.RW & D.IA.RS == M.I0.RD;
|
||||
assign D_IA_FS_M_I1 = M.I1.WCtrl.RW & D.IA.RS == M.I1.RD;
|
||||
@ -685,13 +723,13 @@ module Datapath (
|
||||
E.en,
|
||||
E.I0.pc
|
||||
);
|
||||
ffenrc #(1 + 1 + 1 + 5 + 1) E_I0_Exc_ff (
|
||||
ffenrc #(1 + 1 + 1 + 5 + 2 + 1) E_I0_Exc_ff (
|
||||
clk,
|
||||
rst | rstM,
|
||||
{D.I0.ExcValid, D.I0.ERET, D.I0.REFILL, D.I0.ExcCode, D.I0.Delay},
|
||||
{D.I0.ExcValid, D.I0.ERET, D.I0.REFILL, D.I0.ExcCode, D.I0.CE, D.I0.Delay},
|
||||
E.en,
|
||||
~D_go,
|
||||
{E_I0_PrevExcValid, E_I0_PrevERET, E_I0_PrevREFILL, E_I0_PrevExcCode, E.I0.Delay}
|
||||
{E_I0_PrevExcValid, E_I0_PrevERET, E_I0_PrevREFILL, E_I0_PrevExcCode, E.I0.CE, E.I0.Delay}
|
||||
);
|
||||
ffenrc #(1) E_I0_ExcCtrl_ff (
|
||||
clk,
|
||||
@ -748,13 +786,13 @@ module Datapath (
|
||||
E.en,
|
||||
E.I1.pc
|
||||
);
|
||||
ffenrc #(1 + 1 + 1 + 5 + 1) E_I1_Exc_ff (
|
||||
ffenrc #(1 + 1 + 1 + 5 + 2 + 1) E_I1_Exc_ff (
|
||||
clk,
|
||||
rst | rstM,
|
||||
{D.I1.ExcValid, D.I1.ERET, D.I1.REFILL, D.I1.ExcCode, D.I1.Delay},
|
||||
{D.I1.ExcValid, D.I1.ERET, D.I1.REFILL, D.I1.ExcCode, D.I1.CE, D.I1.Delay},
|
||||
E.en,
|
||||
~D_go,
|
||||
{E_I1_PrevExcValid, E_I1_PrevERET, E_I1_PrevREFILL, E_I1_PrevExcCode, E.I1.Delay}
|
||||
{E_I1_PrevExcValid, E_I1_PrevERET, E_I1_PrevREFILL, E_I1_PrevExcCode, E.I1.CE, E.I1.Delay}
|
||||
);
|
||||
ffenrc #(1) E_I1_ExcCtrl_ff (
|
||||
clk,
|
||||
@ -1007,13 +1045,13 @@ module Datapath (
|
||||
M.en,
|
||||
M.I0.pc
|
||||
);
|
||||
ffenrc #(1 + 1 + 1 + 5 + 1) M_I0_Exc_ff (
|
||||
ffenrc #(1 + 1 + 1 + 5 + 2 + 1) M_I0_Exc_ff (
|
||||
clk,
|
||||
rst | rstM,
|
||||
{E.I0.ExcValid, E.I0.ERET, E.I0.REFILL, E.I0.ExcCode, E.I0.Delay},
|
||||
{E.I0.ExcValid, E.I0.ERET, E.I0.REFILL, E.I0.ExcCode, E.I0.CE, E.I0.Delay},
|
||||
M.en,
|
||||
~E_go,
|
||||
{M.I0.ExcValid, M.I0.ERET, M.I0.REFILL, M.I0.ExcCode, M.I0.Delay}
|
||||
{M.I0.ExcValid, M.I0.ERET, M.I0.REFILL, M.I0.ExcCode, M.I0.CE, M.I0.Delay}
|
||||
);
|
||||
ffen #(5 + 5) M_I0_RST_ff (
|
||||
clk,
|
||||
@ -1049,10 +1087,10 @@ module Datapath (
|
||||
~E_go | ~E_I0_go,
|
||||
{M.I0.RD, M.I0.WCtrl}
|
||||
);
|
||||
ffenr #(6) M_I0_MULT_CNTR_ff (
|
||||
ffenr #(1) M_I0_MULT_CNTR_ff (
|
||||
clk,
|
||||
rst | rstM,
|
||||
{E.I0.MCtrl.HLS[2:1] == 2'b10 & E_go & M.en, M_I0_MULT_CNTR[5:1]},
|
||||
{E.I0.MCtrl.HLS[2:1] == 2'b10 & E_go & M.en},
|
||||
1'b1,
|
||||
M_I0_MULT_CNTR
|
||||
);
|
||||
@ -1062,13 +1100,13 @@ module Datapath (
|
||||
M.en,
|
||||
M.I1.pc
|
||||
);
|
||||
ffenrc #(1 + 1 + 1 + 5 + 32 + 1) M_I1_Exc_ff (
|
||||
ffenrc #(1 + 1 + 1 + 5 + 2 + 32 + 1) M_I1_Exc_ff (
|
||||
clk,
|
||||
rst | rstM,
|
||||
{E.I1.ExcValid, E.I1.ERET, E.I1.REFILL, E.I1.ExcCode, E.I1.BadVAddr, E.I1.Delay},
|
||||
{E.I1.ExcValid, E.I1.ERET, E.I1.REFILL, E.I1.ExcCode, E.I1.CE, E.I1.BadVAddr, E.I1.Delay},
|
||||
M.en,
|
||||
~E_go,
|
||||
{M_I1_PrevExcValid, M.I1.ERET, M_I1_PrevREFILL, M_I1_PrevExcCode, M.I1.BadVAddr, M.I1.Delay}
|
||||
{M_I1_PrevExcValid, M.I1.ERET, M_I1_PrevREFILL, M_I1_PrevExcCode, M.I1.CE, M.I1.BadVAddr, M.I1.Delay}
|
||||
);
|
||||
ffen #(5) M_I1_RT_ff (
|
||||
clk,
|
||||
@ -1144,12 +1182,13 @@ module Datapath (
|
||||
|
||||
assign {M_exception, M_exception_REFILL} = {
|
||||
M.I1.ExcValid | M.I0.ExcValid,
|
||||
~M.I0.ExcValid | M.I1.ExcValid & M.A ? {M.I1.Delay, M.I1.ExcCode, M.I1.BadVAddr, M.I1.pc, M.I1.ERET, M.I1.REFILL}
|
||||
: {M.I0.Delay, M.I0.ExcCode, M.I0.BadVAddr, M.I0.pc, M.I0.ERET, M.I0.REFILL}
|
||||
~M.I0.ExcValid | M.I1.ExcValid & M.A ? {M.I1.Delay, M.I1.CE, M.I1.ExcCode, M.I1.BadVAddr, M.I1.pc, M.I1.ERET, M.I1.REFILL}
|
||||
: {M.I0.Delay, M.I0.CE, M.I0.ExcCode, M.I0.BadVAddr, M.I0.pc, M.I0.ERET, M.I0.REFILL}
|
||||
};
|
||||
assign C0_exception = {
|
||||
M_exception.ExcValid & M.en,
|
||||
M_exception.Delay,
|
||||
M_exception.CE,
|
||||
M_exception.ExcCode,
|
||||
M_exception.BadVAddr,
|
||||
M_exception.EPC,
|
||||
@ -1159,7 +1198,7 @@ module Datapath (
|
||||
// M.I0.MUL
|
||||
ffenr #(97) M_I0_MAS_ff (
|
||||
clk,rst,
|
||||
{M_I0_MULTL, M_I0_MULTH, M_I0_MULTUH, M_I0_MULT_CNTR[0]},
|
||||
{M_I0_MULTL, M_I0_MULTH, M_I0_MULTUH, M_I0_MULT_CNTR},
|
||||
1'b1,
|
||||
{M_I0_MULTLF, M_I0_MULTHF, M_I0_MULTUHF, M_I0_MAS_bvalid}
|
||||
);
|
||||
@ -1172,7 +1211,7 @@ module Datapath (
|
||||
|
||||
myBuffer #(96) M_I0_MULT_buffer (
|
||||
clk, rst,
|
||||
M_I0_MULT_CNTR[0] & M.I0.MCtrl.MAS == 2'b00 | M_I0_MAS_bvalid & |M.I0.MCtrl.MAS,
|
||||
M_I0_MULT_CNTR & M.I0.MCtrl.MAS == 2'b00 | M_I0_MAS_bvalid & |M.I0.MCtrl.MAS,
|
||||
M.I0.MCtrl.MAS == 2'b00 ? {M_I0_MULTL, M_I0_MULTH, M_I0_MULTUH}
|
||||
: {M_I0_MASL, M_I0_MASH, M_I0_MUASH},
|
||||
M.en,
|
||||
|
||||
123
src/Core/Gadgets/decoder2.sv
Normal file
123
src/Core/Gadgets/decoder2.sv
Normal file
@ -0,0 +1,123 @@
|
||||
`include "defines.svh"
|
||||
|
||||
module decoder2 (
|
||||
input word_t instr,
|
||||
input logic [3:0] CU,
|
||||
input logic kernel,
|
||||
output logic ri,
|
||||
output logic cpu,
|
||||
output logic [1:0] ce
|
||||
);
|
||||
|
||||
logic [3:0] CU2;
|
||||
assign CU2 = {CU[3:1], CU[0] | kernel};
|
||||
always_comb begin
|
||||
ri = 1'b1;
|
||||
ce = instr[27:26];
|
||||
cpu = ce != 2'b11
|
||||
& ~CU2[ce] & ( instr[31:28] == 4'b0100 // COPx
|
||||
| instr[31:28] == 4'b1100 // LWCx
|
||||
| instr[31:28] == 4'b1101 // LDCx
|
||||
| instr[31:28] == 4'b1110 // SWCx
|
||||
| instr[31:28] == 4'b1111 // SDCx
|
||||
); // TODO: Cache instruction
|
||||
casez (instr)
|
||||
32'b00000000000???????????????000000: ri = 1'b0; // SLL
|
||||
32'b00000000000???????????????000010: ri = 1'b0; // SRL
|
||||
32'b00000000000???????????????000011: ri = 1'b0; // SRA
|
||||
32'b000000???????????????00000000100: ri = 1'b0; // SLLV
|
||||
32'b000000???????????????00000000110: ri = 1'b0; // SRLV
|
||||
32'b000000???????????????00000000111: ri = 1'b0; // SRAV
|
||||
32'b000000?????0000000000?????001000: ri = 1'b0; // JR
|
||||
32'b000000?????00000??????????001001: ri = 1'b0; // JALR
|
||||
32'b000000???????????????00000001010: ri = 1'b0; // MOVZ
|
||||
32'b000000???????????????00000001011: ri = 1'b0; // MOVN
|
||||
32'b000000????????????????????001100: ri = 1'b0; // SYSCALL
|
||||
32'b000000????????????????????001101: ri = 1'b0; // BREAK
|
||||
32'b000000000000000000000?????001111: ri = 1'b0; // SYNC (NOP)
|
||||
32'b0000000000000000?????00000010000: ri = 1'b0; // MFHI
|
||||
32'b000000?????000000000000000010001: ri = 1'b0; // MTHI
|
||||
32'b0000000000000000?????00000010010: ri = 1'b0; // MFLO
|
||||
32'b000000?????000000000000000010011: ri = 1'b0; // MTLO
|
||||
32'b000000??????????0000000000011000: ri = 1'b0; // MULT
|
||||
32'b000000??????????0000000000011001: ri = 1'b0; // MULTU
|
||||
32'b000000??????????0000000000011010: ri = 1'b0; // DIV
|
||||
32'b000000??????????0000000000011011: ri = 1'b0; // DIVU
|
||||
32'b000000???????????????00000100000: ri = 1'b0; // ADD
|
||||
32'b000000???????????????00000100001: ri = 1'b0; // ADDU
|
||||
32'b000000???????????????00000100010: ri = 1'b0; // SUB
|
||||
32'b000000???????????????00000100011: ri = 1'b0; // SUBU
|
||||
32'b000000???????????????00000100100: ri = 1'b0; // AND
|
||||
32'b000000???????????????00000100101: ri = 1'b0; // OR
|
||||
32'b000000???????????????00000100110: ri = 1'b0; // XOR
|
||||
32'b000000???????????????00000100111: ri = 1'b0; // NOR
|
||||
32'b000000???????????????00000101010: ri = 1'b0; // SLT
|
||||
32'b000000???????????????00000101011: ri = 1'b0; // SLTU
|
||||
32'b000000????????????????????110000: ri = 1'b0; // TGE
|
||||
32'b000000????????????????????110001: ri = 1'b0; // TGEU
|
||||
32'b000000????????????????????110010: ri = 1'b0; // TLT
|
||||
32'b000000????????????????????110011: ri = 1'b0; // TLTU
|
||||
32'b000000????????????????????110100: ri = 1'b0; // TEQ
|
||||
32'b000000????????????????????110110: ri = 1'b0; // TNE
|
||||
32'b000001?????00000????????????????: ri = 1'b0; // BLTZ
|
||||
32'b000001?????00001????????????????: ri = 1'b0; // BGEZ
|
||||
32'b000001?????01000????????????????: ri = 1'b0; // TGEI
|
||||
32'b000001?????01001????????????????: ri = 1'b0; // TGEIU
|
||||
32'b000001?????01010????????????????: ri = 1'b0; // TLTI
|
||||
32'b000001?????01011????????????????: ri = 1'b0; // TLTIU
|
||||
32'b000001?????01110????????????????: ri = 1'b0; // TNEI
|
||||
32'b000001?????01100????????????????: ri = 1'b0; // TEQI
|
||||
32'b000001?????10000????????????????: ri = 1'b0; // BLTZAL
|
||||
32'b000001?????10001????????????????: ri = 1'b0; // BGEZAL
|
||||
32'b000010??????????????????????????: ri = 1'b0; // J
|
||||
32'b000011??????????????????????????: ri = 1'b0; // JAL
|
||||
32'b000100??????????????????????????: ri = 1'b0; // BEQ
|
||||
32'b000101??????????????????????????: ri = 1'b0; // BNE
|
||||
32'b000110?????00000????????????????: ri = 1'b0; // BLEZ
|
||||
32'b000111?????00000????????????????: ri = 1'b0; // BGTZ
|
||||
32'b001000??????????????????????????: ri = 1'b0; // ADDI
|
||||
32'b001001??????????????????????????: ri = 1'b0; // ADDIU
|
||||
32'b001010??????????????????????????: ri = 1'b0; // SLTI
|
||||
32'b001011??????????????????????????: ri = 1'b0; // SLTIU
|
||||
32'b001100??????????????????????????: ri = 1'b0; // ANDI
|
||||
32'b001101??????????????????????????: ri = 1'b0; // ORI
|
||||
32'b001110??????????????????????????: ri = 1'b0; // XORI
|
||||
32'b00111100000?????????????????????: ri = 1'b0; // LUI
|
||||
32'b01000000000??????????00000000???: ri = 1'b0; // MFC0
|
||||
32'b01000000100??????????00000000???: ri = 1'b0; // MTC0
|
||||
32'b01000010000000000000000000000001: ri = 1'b0; // TLBR
|
||||
32'b01000010000000000000000000000010: ri = 1'b0; // TLBWI
|
||||
32'b01000010000000000000000000000110: ri = 1'b0; // TLBWR
|
||||
32'b01000010000000000000000000001000: ri = 1'b0; // TLBP
|
||||
32'b01000010000000000000000000011000: ri = 1'b0; // ERET
|
||||
32'b011100??????????0000000000000000: ri = 1'b0; // MADD
|
||||
32'b011100??????????0000000000000001: ri = 1'b0; // MADDU
|
||||
32'b011100??????????0000000000000100: ri = 1'b0; // MSUB
|
||||
32'b011100??????????0000000000000101: ri = 1'b0; // MSUBU
|
||||
32'b011100???????????????00000000010: ri = 1'b0; // MUL
|
||||
// 32'b01111100000??????????00000111011: begin cpu = 1'b1; ce = 2'b0; end // RDHWR (CpU)
|
||||
32'b100000??????????????????????????: ri = 1'b0; // LB
|
||||
32'b100001??????????????????????????: ri = 1'b0; // LH
|
||||
32'b100010??????????????????????????: ri = 1'b0; // LWL
|
||||
32'b100011??????????????????????????: ri = 1'b0; // LW
|
||||
32'b100100??????????????????????????: ri = 1'b0; // LBU
|
||||
32'b100101??????????????????????????: ri = 1'b0; // LHU
|
||||
32'b100110??????????????????????????: ri = 1'b0; // LWR
|
||||
32'b101000??????????????????????????: ri = 1'b0; // SB
|
||||
32'b101001??????????????????????????: ri = 1'b0; // SH
|
||||
32'b101010??????????????????????????: ri = 1'b0; // SWL
|
||||
32'b101011??????????????????????????: ri = 1'b0; // SW
|
||||
32'b101110??????????????????????????: ri = 1'b0; // SWR
|
||||
32'b101111?????00000????????????????: ri = 1'b0; // I-Cache Index Invalid
|
||||
32'b101111?????01000????????????????: ri = 1'b0; // I-Cache Index Store Tag
|
||||
32'b101111?????10000????????????????: ri = 1'b0; // I-Cache Hit Invalid
|
||||
32'b101111?????00001????????????????: ri = 1'b0; // D-Cache Index Writeback Invalid
|
||||
32'b101111?????01001????????????????: ri = 1'b0; // D-Cache Index Store Tag
|
||||
32'b101111?????10001????????????????: ri = 1'b0; // D-Cache Hit Invalid
|
||||
32'b101111?????10101????????????????: ri = 1'b0; // D-Cache Hit Writeback Invalid
|
||||
// 32'b110000??????????????????????????: begin cpu = 1'b1; ce = 2'b0; end // LL (CpU)
|
||||
32'b110011??????????????????????????: ri = 1'b0; // PREF (NOP)
|
||||
// 32'b111000??????????????????????????: begin cpu = 1'b1; ce = 2'b0; end // SC (CpU)
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
@ -1,105 +0,0 @@
|
||||
`include "defines.svh"
|
||||
|
||||
module instr_valid (
|
||||
input word_t instr,
|
||||
output logic valid
|
||||
);
|
||||
|
||||
always_comb
|
||||
casez (instr)
|
||||
32'b000000000000000000000?????001111: valid = 1'b1; // SYNC (NOP)
|
||||
32'b00000000000???????????????000000: valid = 1'b1; // SLL
|
||||
32'b00000000000???????????????000010: valid = 1'b1; // SRL
|
||||
32'b00000000000???????????????000011: valid = 1'b1; // SRA
|
||||
32'b000000???????????????00000000100: valid = 1'b1; // SLLV
|
||||
32'b000000???????????????00000000110: valid = 1'b1; // SRLV
|
||||
32'b000000???????????????00000000111: valid = 1'b1; // SRAV
|
||||
32'b000000???????????????00000001010: valid = 1'b1; // MOVZ
|
||||
32'b000000???????????????00000001011: valid = 1'b1; // MOVN
|
||||
32'b000000?????000000000000000001000: valid = 1'b1; // JR
|
||||
32'b000000?????00000?????00000001001: valid = 1'b1; // JALR
|
||||
32'b000000????????????????????001100: valid = 1'b1; // SYSCALL
|
||||
32'b000000????????????????????001101: valid = 1'b1; // BREAK
|
||||
32'b0000000000000000?????00000010000: valid = 1'b1; // MFHI
|
||||
32'b000000?????000000000000000010001: valid = 1'b1; // MTHI
|
||||
32'b0000000000000000?????00000010010: valid = 1'b1; // MFLO
|
||||
32'b000000?????000000000000000010011: valid = 1'b1; // MTLO
|
||||
32'b000000??????????0000000000011000: valid = 1'b1; // MULT
|
||||
32'b000000??????????0000000000011001: valid = 1'b1; // MULTU
|
||||
32'b000000??????????0000000000011010: valid = 1'b1; // DIV
|
||||
32'b000000??????????0000000000011011: valid = 1'b1; // DIVU
|
||||
32'b000000???????????????00000100000: valid = 1'b1; // ADD
|
||||
32'b000000???????????????00000100001: valid = 1'b1; // ADDU
|
||||
32'b000000???????????????00000100010: valid = 1'b1; // SUB
|
||||
32'b000000???????????????00000100011: valid = 1'b1; // SUBU
|
||||
32'b000000???????????????00000100100: valid = 1'b1; // AND
|
||||
32'b000000???????????????00000100101: valid = 1'b1; // OR
|
||||
32'b000000???????????????00000100110: valid = 1'b1; // XOR
|
||||
32'b000000???????????????00000100111: valid = 1'b1; // NOR
|
||||
32'b000000???????????????00000101010: valid = 1'b1; // SLT
|
||||
32'b000000???????????????00000101011: valid = 1'b1; // SLTU
|
||||
32'b000000????????????????????110000: valid = 1'b1; // TGE
|
||||
32'b000000????????????????????110001: valid = 1'b1; // TGEU
|
||||
32'b000000????????????????????110010: valid = 1'b1; // TLT
|
||||
32'b000000????????????????????110011: valid = 1'b1; // TLTU
|
||||
32'b000000????????????????????110100: valid = 1'b1; // TEQ
|
||||
32'b000000????????????????????110110: valid = 1'b1; // TNE
|
||||
32'b000001?????00000????????????????: valid = 1'b1; // BLTZ
|
||||
32'b000001?????00001????????????????: valid = 1'b1; // BGEZ
|
||||
32'b000001?????01000????????????????: valid = 1'b1; // TGEI
|
||||
32'b000001?????01001????????????????: valid = 1'b1; // TGEIU
|
||||
32'b000001?????01010????????????????: valid = 1'b1; // TLTI
|
||||
32'b000001?????01011????????????????: valid = 1'b1; // TLTIU
|
||||
32'b000001?????01110????????????????: valid = 1'b1; // TNEI
|
||||
32'b000001?????01100????????????????: valid = 1'b1; // TEQI
|
||||
32'b000001?????10000????????????????: valid = 1'b1; // BLTZAL
|
||||
32'b000001?????10001????????????????: valid = 1'b1; // BGEZAL
|
||||
32'b000010??????????????????????????: valid = 1'b1; // J
|
||||
32'b000011??????????????????????????: valid = 1'b1; // JAL
|
||||
32'b000100??????????????????????????: valid = 1'b1; // BEQ
|
||||
32'b000101??????????????????????????: valid = 1'b1; // BNE
|
||||
32'b000110?????00000????????????????: valid = 1'b1; // BLEZ
|
||||
32'b000111?????00000????????????????: valid = 1'b1; // BGTZ
|
||||
32'b001000??????????????????????????: valid = 1'b1; // ADDI
|
||||
32'b001001??????????????????????????: valid = 1'b1; // ADDIU
|
||||
32'b001010??????????????????????????: valid = 1'b1; // SLTI
|
||||
32'b001011??????????????????????????: valid = 1'b1; // SLTIU
|
||||
32'b001100??????????????????????????: valid = 1'b1; // ANDI
|
||||
32'b001101??????????????????????????: valid = 1'b1; // ORI
|
||||
32'b001110??????????????????????????: valid = 1'b1; // XORI
|
||||
32'b00111100000?????????????????????: valid = 1'b1; // LUI
|
||||
32'b01000000000??????????00000000???: valid = 1'b1; // MFC0
|
||||
32'b01000000100??????????00000000???: valid = 1'b1; // MTC0
|
||||
32'b01000010000000000000000000000001: valid = 1'b1; // TLBR
|
||||
32'b01000010000000000000000000000010: valid = 1'b1; // TLBWI
|
||||
32'b01000010000000000000000000000110: valid = 1'b1; // TLBWR
|
||||
32'b01000010000000000000000000001000: valid = 1'b1; // TLBP
|
||||
32'b01000010000000000000000000011000: valid = 1'b1; // ERET
|
||||
32'b011100??????????0000000000000000: valid = 1'b1; // MADD
|
||||
32'b011100??????????0000000000000001: valid = 1'b1; // MADDU
|
||||
32'b011100??????????0000000000000100: valid = 1'b1; // MSUB
|
||||
32'b011100??????????0000000000000101: valid = 1'b1; // MSUBU
|
||||
32'b011100???????????????00000000010: valid = 1'b1; // MUL
|
||||
32'b100000??????????????????????????: valid = 1'b1; // LB
|
||||
32'b100001??????????????????????????: valid = 1'b1; // LH
|
||||
32'b100010??????????????????????????: valid = 1'b1; // LWL
|
||||
32'b100011??????????????????????????: valid = 1'b1; // LW
|
||||
32'b100100??????????????????????????: valid = 1'b1; // LBU
|
||||
32'b100101??????????????????????????: valid = 1'b1; // LHU
|
||||
32'b100110??????????????????????????: valid = 1'b1; // LWR
|
||||
32'b101000??????????????????????????: valid = 1'b1; // SB
|
||||
32'b101001??????????????????????????: valid = 1'b1; // SH
|
||||
32'b101010??????????????????????????: valid = 1'b1; // SWL
|
||||
32'b101011??????????????????????????: valid = 1'b1; // SW
|
||||
32'b101110??????????????????????????: valid = 1'b1; // SWR
|
||||
32'b101111?????00000????????????????: valid = 1'b1; // I-Cache Index Invalid
|
||||
32'b101111?????01000????????????????: valid = 1'b1; // I-Cache Index Store Tag
|
||||
32'b101111?????10000????????????????: valid = 1'b1; // I-Cache Hit Invalid
|
||||
32'b101111?????00001????????????????: valid = 1'b1; // D-Cache Index Writeback Invalid
|
||||
32'b101111?????01001????????????????: valid = 1'b1; // D-Cache Index Store Tag
|
||||
32'b101111?????10001????????????????: valid = 1'b1; // D-Cache Hit Invalid
|
||||
32'b101111?????10101????????????????: valid = 1'b1; // D-Cache Hit Writeback Invalid
|
||||
32'b110011??????????????????????????: valid = 1'b1; // PREF (NOP)
|
||||
default: valid = 1'b0;
|
||||
endcase
|
||||
endmodule
|
||||
@ -61,7 +61,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVIDEND_TUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVISOR_TLAST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVISOR_TUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">36</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">14</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TDATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DIVIDEND_TDATA_WIDTH">32</spirit:configurableElementValue>
|
||||
@ -96,8 +96,8 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_tuser_width">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_width">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.fractional_width">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.latency">36</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.latency_configuration">Automatic</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.latency">14</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.latency_configuration">Manual</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.operand_sign">Signed</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.remainder_type">Remainder</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
|
||||
|
||||
@ -61,7 +61,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVIDEND_TUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVISOR_TLAST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVISOR_TUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">34</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">14</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TDATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DIVIDEND_TDATA_WIDTH">32</spirit:configurableElementValue>
|
||||
@ -96,8 +96,8 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_tuser_width">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_width">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.fractional_width">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.latency">34</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.latency_configuration">Automatic</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.latency">14</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.latency_configuration">Manual</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.operand_sign">Unsigned</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.remainder_type">Remainder</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
|
||||
|
||||
@ -27,7 +27,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SCLR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ZERO_DETECT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MODEL_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MULT_TYPE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZE_GOAL">1</spirit:configurableElementValue>
|
||||
@ -47,7 +47,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OptGoal">Speed</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OutputWidthHigh">63</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OutputWidthLow">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PipeStages">6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PipeStages">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PortAType">Signed</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PortAWidth">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PortBType">Signed</spirit:configurableElementValue>
|
||||
|
||||
@ -27,7 +27,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SCLR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ZERO_DETECT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MODEL_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MULT_TYPE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZE_GOAL">1</spirit:configurableElementValue>
|
||||
@ -47,7 +47,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OptGoal">Speed</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OutputWidthHigh">63</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OutputWidthLow">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PipeStages">6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PipeStages">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PortAType">Unsigned</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PortAWidth">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PortBType">Unsigned</spirit:configurableElementValue>
|
||||
|
||||
@ -419,10 +419,10 @@ module MMU (
|
||||
if (rdata_axi.addr_ok) begin
|
||||
if (~rdata_axi.rvalid) drNextState = DR_WD1;
|
||||
else begin
|
||||
data.data_ok = 1;
|
||||
if (dCached2) drNextState = DR_WD2;
|
||||
else begin
|
||||
dEn = 1;
|
||||
data.data_ok = 1;
|
||||
drNextState = DR_IDLE;
|
||||
end
|
||||
end
|
||||
|
||||
@ -42,6 +42,7 @@ typedef enum bit [4:0] {
|
||||
typedef struct packed {
|
||||
logic ExcValid;
|
||||
logic Delay;
|
||||
logic [1:0] CE;
|
||||
logic [4:0] ExcCode;
|
||||
word_t BadVAddr;
|
||||
word_t EPC;
|
||||
@ -60,7 +61,19 @@ typedef struct packed {
|
||||
} CP0_REGS_CONFIG_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic [8:0] zero1;
|
||||
logic BD;
|
||||
logic TI;
|
||||
logic [1:0] CE;
|
||||
logic [11:0] zero1;
|
||||
logic [7:0] IP;
|
||||
logic zero2;
|
||||
logic [4:0] ExcCode;
|
||||
logic [1:0] zero3;
|
||||
} CP0_REGS_CAUSE_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic [3:0] CU;
|
||||
logic [4:0] zero1;
|
||||
logic Bev;
|
||||
logic [5:0] zero2;
|
||||
logic [7:0] IM;
|
||||
@ -71,16 +84,6 @@ typedef struct packed {
|
||||
logic IE;
|
||||
} CP0_REGS_STATUS_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic BD;
|
||||
logic TI;
|
||||
logic [13:0] zero1;
|
||||
logic [7:0] IP;
|
||||
logic zero2;
|
||||
logic [4:0] ExcCode;
|
||||
logic [1:0] zero3;
|
||||
} CP0_REGS_CAUSE_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic one;
|
||||
logic zero1;
|
||||
@ -118,8 +121,8 @@ typedef struct packed {
|
||||
word_t BadVAddr;
|
||||
// HWREna
|
||||
Wired_t Wired;
|
||||
// Context,
|
||||
// word_t PageMask;
|
||||
Context_t Context;
|
||||
// word_t PageMask;
|
||||
EntryLo_t EntryLo1;
|
||||
EntryLo_t EntryLo0;
|
||||
Random_t Random;
|
||||
|
||||
@ -12,6 +12,11 @@ typedef struct packed {
|
||||
// logic [11:0] Mask;
|
||||
// logic [12:0] zero2;
|
||||
// } PageMask_t;
|
||||
typedef struct packed {
|
||||
logic [ 8:0] PTEBase;
|
||||
logic [18:0] BadVPN2;
|
||||
logic [ 3:0] zero;
|
||||
} Context_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic [ 5:0] zero;
|
||||
@ -22,6 +27,7 @@ typedef struct packed {
|
||||
logic G;
|
||||
} EntryLo_t;
|
||||
|
||||
|
||||
typedef struct packed {
|
||||
logic P;
|
||||
logic [27:0] zero;
|
||||
|
||||
@ -193,6 +193,7 @@ typedef struct packed {
|
||||
logic IA_ERET;
|
||||
logic IA_REFILL;
|
||||
logic [4:0] IA_ExcCode;
|
||||
logic [1:0] IA_CE;
|
||||
logic IA_Delay;
|
||||
word_t IA_S;
|
||||
word_t IA_T;
|
||||
@ -205,6 +206,7 @@ typedef struct packed {
|
||||
logic IB_ERET;
|
||||
logic IB_REFILL;
|
||||
logic [4:0] IB_ExcCode;
|
||||
logic [1:0] IB_CE;
|
||||
logic IB_Delay;
|
||||
word_t IB_S;
|
||||
word_t IB_T;
|
||||
@ -218,6 +220,7 @@ typedef struct packed {
|
||||
logic ERET;
|
||||
logic REFILL;
|
||||
logic [4:0] ExcCode;
|
||||
logic [1:0] CE;
|
||||
logic Delay;
|
||||
logic OFA;
|
||||
|
||||
@ -244,6 +247,7 @@ typedef struct packed {
|
||||
logic ERET;
|
||||
logic REFILL;
|
||||
logic [4:0] ExcCode;
|
||||
logic [1:0] CE;
|
||||
logic Delay;
|
||||
logic OFA;
|
||||
|
||||
@ -276,6 +280,7 @@ typedef struct packed {
|
||||
logic ERET;
|
||||
logic REFILL;
|
||||
logic [4:0] ExcCode;
|
||||
logic [1:0] CE;
|
||||
logic Delay;
|
||||
logic OFA;
|
||||
|
||||
@ -303,6 +308,7 @@ typedef struct packed {
|
||||
logic ERET;
|
||||
logic REFILL;
|
||||
logic [4:0] ExcCode;
|
||||
logic [1:0] CE;
|
||||
word_t BadVAddr;
|
||||
logic Delay;
|
||||
logic OFA;
|
||||
@ -337,6 +343,7 @@ typedef struct packed {
|
||||
logic ERET;
|
||||
logic REFILL;
|
||||
logic [4:0] ExcCode;
|
||||
logic [1:0] CE;
|
||||
word_t BadVAddr;
|
||||
logic Delay;
|
||||
|
||||
@ -361,6 +368,7 @@ typedef struct packed {
|
||||
logic ERET;
|
||||
logic REFILL;
|
||||
logic [4:0] ExcCode;
|
||||
logic [1:0] CE;
|
||||
word_t BadVAddr;
|
||||
logic Delay;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user