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archive/2a
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1
.gitignore
vendored
1
.gitignore
vendored
@ -3,3 +3,4 @@ vivado.jou
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||||
.library_mapping.xml
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||||
.project
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||||
.settings
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||||
.vscode
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81
resources/top/mycpu_block.xdc
Normal file
81
resources/top/mycpu_block.xdc
Normal file
@ -0,0 +1,81 @@
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||||
#set_property SEVERITY {Warning} [get_drc_checks RTSTAT-2]
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#时钟信号连接
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#create_clock -period 10.000 [get_ports clk]
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set_property PACKAGE_PIN AC19 [get_ports clk]
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set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk]
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create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk]
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#reset
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set_property PACKAGE_PIN Y3 [get_ports resetn_rtl_0]
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#SPI flash
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set_property PACKAGE_PIN P20 [get_ports spi_rtl_0_sck_io]
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set_property PACKAGE_PIN R20 [get_ports {spi_rtl_0_ss_io[0]}]
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set_property PACKAGE_PIN P19 [get_ports spi_rtl_0_io1_io]
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set_property PACKAGE_PIN N18 [get_ports spi_rtl_0_io0_io]
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#mac phy connect
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set_property PACKAGE_PIN AB21 [get_ports mii_rtl_0_tx_clk]
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set_property PACKAGE_PIN AA19 [get_ports mii_rtl_0_rx_clk]
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set_property PACKAGE_PIN AA15 [get_ports mii_rtl_0_tx_en]
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set_property PACKAGE_PIN AF18 [get_ports {mii_rtl_0_txd[0]}]
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set_property PACKAGE_PIN AE18 [get_ports {mii_rtl_0_txd[1]}]
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set_property PACKAGE_PIN W15 [get_ports {mii_rtl_0_txd[2]}]
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set_property PACKAGE_PIN W14 [get_ports {mii_rtl_0_txd[3]}]
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set_property PACKAGE_PIN AE22 [get_ports mii_rtl_0_rx_dv]
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set_property PACKAGE_PIN V1 [get_ports {mii_rtl_0_rxd[0]}]
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set_property PACKAGE_PIN V4 [get_ports {mii_rtl_0_rxd[1]}]
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set_property PACKAGE_PIN V2 [get_ports {mii_rtl_0_rxd[2]}]
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set_property PACKAGE_PIN V3 [get_ports {mii_rtl_0_rxd[3]}]
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set_property PACKAGE_PIN W16 [get_ports mii_rtl_0_rx_er]
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set_property PACKAGE_PIN Y15 [get_ports mii_rtl_0_col]
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set_property PACKAGE_PIN AF20 [get_ports mii_rtl_0_crs]
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set_property PACKAGE_PIN W3 [get_ports mdio_rtl_0_mdc]
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set_property PACKAGE_PIN W1 [get_ports mdio_rtl_0_mdio_io]
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set_property PACKAGE_PIN AE26 [get_ports mii_rtl_0_rst_n]
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#uart
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set_property PACKAGE_PIN F23 [get_ports uart_rtl_0_rxd]
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set_property PACKAGE_PIN H19 [get_ports uart_rtl_0_txd]
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set_property PACKAGE_PIN E23 [get_ports uart_rtl_0_cts]
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set_property PACKAGE_PIN G20 [get_ports uart_rtl_0_dcd]
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set_property PACKAGE_PIN K6 [get_ports uart_rtl_0_dsr]
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set_property PACKAGE_PIN F25 [get_ports uart_rtl_0_dtr]
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set_property PACKAGE_PIN K7 [get_ports uart_rtl_0_ri]
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set_property PACKAGE_PIN F24 [get_ports uart_rtl_0_rts]
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set_property IOSTANDARD LVCMOS33 [get_ports clk]
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set_property IOSTANDARD LVCMOS33 [get_ports resetn_rtl_0]
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set_property IOSTANDARD LVCMOS33 [get_ports spi_rtl_0_io0_io]
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set_property IOSTANDARD LVCMOS33 [get_ports spi_rtl_0_io1_io]
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set_property IOSTANDARD LVCMOS33 [get_ports {spi_rtl_0_ss_io[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports spi_rtl_0_sck_io]
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set_property IOSTANDARD LVCMOS33 [get_ports {mii_rtl_0_rxd[*]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {mii_rtl_0_txd[*]}]
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set_property IOSTANDARD LVCMOS33 [get_ports mii_rtl_0_rst_n]
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set_property IOSTANDARD LVCMOS33 [get_ports mii_rtl_0_tx_en]
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set_property IOSTANDARD LVCMOS33 [get_ports mii_rtl_0_tx_clk]
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set_property IOSTANDARD LVCMOS33 [get_ports mii_rtl_0_rx_er]
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set_property IOSTANDARD LVCMOS33 [get_ports mii_rtl_0_col]
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set_property IOSTANDARD LVCMOS33 [get_ports mii_rtl_0_crs]
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set_property IOSTANDARD LVCMOS33 [get_ports mdio_rtl_0_mdc]
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set_property IOSTANDARD LVCMOS33 [get_ports mdio_rtl_0_mdio_io]
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set_property IOSTANDARD LVCMOS33 [get_ports mii_rtl_0_rx_clk]
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set_property IOSTANDARD LVCMOS33 [get_ports mii_rtl_0_rx_dv]
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set_property IOSTANDARD LVCMOS33 [get_ports uart_rtl_0_rxd]
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set_property IOSTANDARD LVCMOS33 [get_ports uart_rtl_0_txd]
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set_property IOSTANDARD LVCMOS33 [get_ports uart_rtl_0_cts]
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set_property IOSTANDARD LVCMOS33 [get_ports uart_rtl_0_dcd]
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set_property IOSTANDARD LVCMOS33 [get_ports uart_rtl_0_dsr]
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set_property IOSTANDARD LVCMOS33 [get_ports uart_rtl_0_dtr]
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set_property IOSTANDARD LVCMOS33 [get_ports uart_rtl_0_ri]
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set_property IOSTANDARD LVCMOS33 [get_ports uart_rtl_0_rts]
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create_clock -period 40.000 -name mii_rtl_0_rx_clk -waveform {0.000 20.000} [get_ports mii_rtl_0_rx_clk]
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create_clock -period 40.000 -name mii_rtl_0_tx_clk -waveform {0.000 20.000} [get_ports mii_rtl_0_tx_clk]
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91
resources/top/mycpu_top_verilog.v
Normal file
91
resources/top/mycpu_top_verilog.v
Normal file
@ -0,0 +1,91 @@
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module mycpu_top_verilog (
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input wire [5:0] ext_int, //high active
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input wire aclk,
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input wire aresetn, //low active
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output wire [ 3:0] arid,
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output wire [31:0] araddr,
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output wire [ 3:0] arlen,
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output wire [ 2:0] arsize,
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output wire [ 1:0] arburst,
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output wire [ 1:0] arlock,
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output wire [ 3:0] arcache,
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output wire [ 2:0] arprot,
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output wire arvalid,
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input wire arready,
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input wire [ 3:0] rid,
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input wire [31:0] rdata,
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input wire [ 1:0] rresp,
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input wire rlast,
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input wire rvalid,
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output wire rready,
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output wire [ 3:0] awid,
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output wire [31:0] awaddr,
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output wire [ 3:0] awlen,
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output wire [ 2:0] awsize,
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output wire [ 1:0] awburst,
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output wire [ 1:0] awlock,
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output wire [ 3:0] awcache,
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output wire [ 2:0] awprot,
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output wire awvalid,
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input wire awready,
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output wire [ 3:0] wid,
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output wire [31:0] wdata,
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output wire [ 3:0] wstrb,
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output wire wlast,
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output wire wvalid,
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input wire wready,
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input wire [3:0] bid,
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input wire [1:0] bresp,
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input wire bvalid,
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output wire bready
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);
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mycpu_top cpu(
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.ext_int(ext_int),
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.aclk (aclk),
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.aresetn(aresetn),
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.arid (arid),
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.araddr (araddr),
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.arlen (arlen),
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.arsize (arsize),
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.arburst(arburst),
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.arlock (arlock),
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.arcache(arcache),
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.arprot (arprot),
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.arvalid(arvalid),
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.arready(arready),
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.rid (rid),
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.rdata (rdata),
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.rresp (rresp),
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.rlast (rlast),
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.rvalid (rvalid),
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.rready (rready),
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.awid (awid),
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.awaddr (awaddr),
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.awlen (awlen),
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.awsize (awsize),
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.awburst(awburst),
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.awlock (awlock),
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.awcache(awcache),
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.awprot (awprot),
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.awvalid(awvalid),
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.awready(awready),
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.wid (wid),
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.wdata (wdata),
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.wstrb (wstrb),
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.wlast (wlast),
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.wvalid (wvalid),
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.wready (wready),
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.bid (bid),
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.bresp (bresp),
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.bvalid (bvalid),
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.bready (bready)
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);
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endmodule
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@ -13,8 +13,11 @@ module CP0 (
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// exception
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input EXCEPTION_t exception,
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output word_t EPC,
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output logic EXL,
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output logic Bev,
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output logic [19:0] EBase,
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output logic [3:0] CU,
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output logic in_kernel,
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// int
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input logic [5:0] ext_int,
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@ -24,7 +27,6 @@ module CP0 (
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input logic tlbr,
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input logic tlbp,
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output logic [2:0] K0,
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output logic in_kernel,
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output Random_t Random,
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output Index_t Index,
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output EntryHi_t EntryHi,
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@ -38,6 +40,14 @@ module CP0 (
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CP0_REGS_t rf_cp0;
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logic count_lo;
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word_t ila_cp0_count;
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word_t ila_cp0_compare;
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word_t ila_cp0_cause;
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word_t ila_cp0_status;
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assign ila_cp0_count = rf_cp0.Count;
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assign ila_cp0_compare = rf_cp0.Compare;
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assign ila_cp0_cause = rf_cp0.Cause;
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assign ila_cp0_status = rf_cp0.Status;
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// int comb logic
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assign interrupt = (rf_cp0.Status.EXL == 1'b0)
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@ -56,12 +66,14 @@ module CP0 (
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assign rf_cp0.Cause.IP[7:2] = {rf_cp0.Cause.TI | ext_int[5], ext_int[4:0]};
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assign rf_cp0.Cause.zero2 = 1'b0;
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assign rf_cp0.Cause.zero3 = 2'b00;
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assign rf_cp0.Status.zero1 = 9'b0;
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assign rf_cp0.Status.CU[3:1] = 3'b0;
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assign rf_cp0.Status.zero1 = 5'b0;
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assign rf_cp0.Status.zero2 = 6'b0;
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assign rf_cp0.Status.zero3 = 3'b0;
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assign rf_cp0.Status.zero4 = 2'b0;
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assign rf_cp0.EntryHi.zero = 5'b0;
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assign rf_cp0.Wired.zero = 29'b0;
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assign rf_cp0.Context.zero = 4'b0;
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assign rf_cp0.EntryLo1.zero = 6'b0;
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assign rf_cp0.EntryLo0.zero = 6'b0;
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assign rf_cp0.Random.zero = 29'b0;
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@ -85,25 +97,53 @@ module CP0 (
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assign rf_cp0.EBase.CPUNum = 10'b0;
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assign rf_cp0.PRId = 32'h00004220;
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`ifndef TLB_ENABLE
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assign rf_cp0.EntryHi.VPN2 = 19'b0;
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assign rf_cp0.EntryHi.ASID = 8'b0;
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assign rf_cp0.Wired.Wired = 3'b0;
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assign rf_cp0.Context.PTEBase = 9'b0;
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assign rf_cp0.Context.BadVPN2 = 19'b0;
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assign rf_cp0.EntryLo1.PFN = 20'b0;
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assign rf_cp0.EntryLo1.C = 3'b0;
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assign rf_cp0.EntryLo1.D = 1'b0;
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assign rf_cp0.EntryLo1.V = 1'b0;
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assign rf_cp0.EntryLo1.G = 1'b0;
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assign rf_cp0.EntryLo0.PFN = 20'b0;
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assign rf_cp0.EntryLo0.C = 3'b0;
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assign rf_cp0.EntryLo0.D = 1'b0;
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assign rf_cp0.EntryLo0.V = 1'b0;
|
||||
assign rf_cp0.EntryLo0.G = 1'b0;
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assign rf_cp0.Index.P = 1'b0;
|
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assign rf_cp0.Index.Index = 3'b0;
|
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assign rf_cp0.Random.Random = 3'b111;
|
||||
`endif
|
||||
|
||||
always_ff @(posedge clk)
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||||
if (rst) begin
|
||||
rf_cp0.Config.K0 = 3'b011;
|
||||
rf_cp0.EPC = 32'h0;
|
||||
rf_cp0.Cause.BD = 1'b0;
|
||||
rf_cp0.Cause.TI = 1'b0;
|
||||
rf_cp0.Cause.CE = 2'b0;
|
||||
rf_cp0.Cause.IP[1:0] = 2'b0;
|
||||
rf_cp0.Cause.ExcCode = 5'b0;
|
||||
rf_cp0.Status.CU[0] = 1'b1;
|
||||
rf_cp0.Status.Bev = 1'b1;
|
||||
rf_cp0.Status.IM = 8'b0;
|
||||
rf_cp0.Status.UM = 1'b0;
|
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rf_cp0.Status.EXL = 1'b0;
|
||||
rf_cp0.Status.IE = 1'b0;
|
||||
rf_cp0.Compare = 32'hFFFF_FFFF;
|
||||
rf_cp0.Compare = 32'h0;
|
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`ifdef TLB_ENABLE
|
||||
rf_cp0.EntryHi.VPN2 = 19'b0;
|
||||
rf_cp0.EntryHi.ASID = 8'b0;
|
||||
`endif
|
||||
rf_cp0.Count = 32'h0;
|
||||
rf_cp0.BadVAddr = 32'h0;
|
||||
`ifdef TLB_ENABLE
|
||||
rf_cp0.Wired.Wired = 3'b0;
|
||||
rf_cp0.Context.PTEBase = 9'b0;
|
||||
rf_cp0.Context.BadVPN2 = 19'b0;
|
||||
rf_cp0.EntryLo1.PFN = 20'b0;
|
||||
rf_cp0.EntryLo1.C = 3'b0;
|
||||
rf_cp0.EntryLo1.D = 1'b0;
|
||||
@ -117,6 +157,7 @@ module CP0 (
|
||||
rf_cp0.Index.P = 1'b0;
|
||||
rf_cp0.Index.Index = 3'b0;
|
||||
rf_cp0.Random.Random = 3'b111;
|
||||
`endif
|
||||
|
||||
rf_cp0.EBase.EBase = 18'b0;
|
||||
|
||||
@ -125,7 +166,8 @@ module CP0 (
|
||||
// count
|
||||
count_lo = ~count_lo;
|
||||
if (count_lo == 1) rf_cp0.Count = rf_cp0.Count + 1;
|
||||
|
||||
rf_cp0.Random.Random = &rf_cp0.Random.Random ? rf_cp0.Wired.Wired
|
||||
: rf_cp0.Random.Random + 1'b1;
|
||||
if (en) begin
|
||||
case (addr)
|
||||
// 31: rf_cp0.DESAVE = wdata;
|
||||
@ -149,6 +191,7 @@ module CP0 (
|
||||
14: rf_cp0.EPC = wdata;
|
||||
13: rf_cp0.Cause.IP[1:0] = wdata[9:8];
|
||||
12: begin
|
||||
rf_cp0.Status.CU[0] = wdata[28];
|
||||
rf_cp0.Status.Bev = wdata[22];
|
||||
rf_cp0.Status.IM = wdata[15:8];
|
||||
rf_cp0.Status.UM = wdata[4];
|
||||
@ -160,38 +203,56 @@ module CP0 (
|
||||
rf_cp0.Compare = wdata;
|
||||
end
|
||||
10: begin
|
||||
`ifdef TLB_ENABLE
|
||||
rf_cp0.EntryHi.VPN2 = wdata[31:13];
|
||||
rf_cp0.EntryHi.ASID = wdata[7:0];
|
||||
`endif
|
||||
end
|
||||
9: rf_cp0.Count = wdata;
|
||||
8: rf_cp0.BadVAddr = wdata;
|
||||
// 7: rf_cp0.HWREna = wdata;
|
||||
6: rf_cp0.Wired.Wired = wdata[2:0];
|
||||
6: begin
|
||||
`ifdef TLB_ENABLE
|
||||
rf_cp0.Wired.Wired = wdata[2:0];
|
||||
rf_cp0.Random.Random = 3'b111;
|
||||
`endif
|
||||
end
|
||||
// 5: rf_cp0.PageMask.Mask = wdata[24:13];
|
||||
// 4: rf_cp0.Context = wdata;
|
||||
4: begin
|
||||
`ifdef TLB_ENABLE
|
||||
rf_cp0.Context.PTEBase = wdata[31:23];
|
||||
`endif
|
||||
end
|
||||
3: begin
|
||||
`ifdef TLB_ENABLE
|
||||
rf_cp0.EntryLo1.PFN = wdata[25:6];
|
||||
rf_cp0.EntryLo1.C = wdata[5:3];
|
||||
rf_cp0.EntryLo1.D = wdata[2];
|
||||
rf_cp0.EntryLo1.V = wdata[1];
|
||||
rf_cp0.EntryLo1.G = wdata[0];
|
||||
`endif
|
||||
end
|
||||
2: begin
|
||||
`ifdef TLB_ENABLE
|
||||
rf_cp0.EntryLo0.PFN = wdata[25:6];
|
||||
rf_cp0.EntryLo0.C = wdata[5:3];
|
||||
rf_cp0.EntryLo0.D = wdata[2];
|
||||
rf_cp0.EntryLo0.V = wdata[1];
|
||||
rf_cp0.EntryLo0.G = wdata[0];
|
||||
`endif
|
||||
end
|
||||
// 1: rf_cp0.Random = wdata;
|
||||
0: begin
|
||||
`ifdef TLB_ENABLE
|
||||
rf_cp0.Index.Index = wdata[2:0];
|
||||
`endif
|
||||
end
|
||||
default: begin
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
`ifdef TLB_ENABLE
|
||||
if (tlbr) begin
|
||||
rf_cp0.EntryHi.VPN2 = tlb_EntryHi.VPN2;
|
||||
rf_cp0.EntryHi.ASID = tlb_EntryHi.ASID;
|
||||
@ -212,19 +273,20 @@ module CP0 (
|
||||
rf_cp0.Index.P = tlb_Index.P;
|
||||
rf_cp0.Index.Index = tlb_Index.Index;
|
||||
end
|
||||
|
||||
rf_cp0.Random.Random = &rf_cp0.Random.Random ? rf_cp0.Wired.Wired
|
||||
: rf_cp0.Random.Random + 1'b1;
|
||||
`endif
|
||||
|
||||
if (rf_cp0.Count == rf_cp0.Compare) rf_cp0.Cause.TI = 1;
|
||||
|
||||
if (exception.ERET) rf_cp0.Status.EXL = 1'b0;
|
||||
else begin
|
||||
if (exception.ExcValid && rf_cp0.Status.EXL == 1'b0) begin
|
||||
if (exception.ExcValid) begin
|
||||
if (rf_cp0.Status.EXL == 1'b0) begin
|
||||
rf_cp0.EPC = exception.Delay ? exception.EPC - 4 : exception.EPC;
|
||||
rf_cp0.Cause.BD = exception.Delay;
|
||||
rf_cp0.Cause.ExcCode = exception.ExcCode;
|
||||
rf_cp0.Status.EXL = 1'b1;
|
||||
end
|
||||
rf_cp0.Cause.CE = exception.CE;
|
||||
rf_cp0.Cause.ExcCode = exception.ExcCode;
|
||||
|
||||
if ( exception.ExcCode == `EXCCODE_MOD
|
||||
| exception.ExcCode == `EXCCODE_TLBL
|
||||
@ -234,11 +296,14 @@ module CP0 (
|
||||
rf_cp0.BadVAddr = exception.BadVAddr;
|
||||
end
|
||||
|
||||
`ifdef TLB_ENABLE
|
||||
if ( exception.ExcCode == `EXCCODE_MOD
|
||||
| exception.ExcCode == `EXCCODE_TLBL
|
||||
| exception.ExcCode == `EXCCODE_TLBS) begin
|
||||
rf_cp0.Context.BadVPN2 = exception.BadVAddr[31:13];
|
||||
rf_cp0.EntryHi.VPN2 = exception.BadVAddr[31:13];
|
||||
end
|
||||
`endif
|
||||
|
||||
end
|
||||
end
|
||||
@ -275,7 +340,7 @@ module CP0 (
|
||||
6: rdata = rf_cp0.Wired;
|
||||
// 5: rdata = rf_cp0.PageMask;
|
||||
5: rdata = 32'h0;
|
||||
// 4: rdata = rf_cp0.Context;
|
||||
4: rdata = rf_cp0.Context;
|
||||
3: rdata = rf_cp0.EntryLo1;
|
||||
2: rdata = rf_cp0.EntryLo0;
|
||||
1: rdata = rf_cp0.Random;
|
||||
@ -284,6 +349,7 @@ module CP0 (
|
||||
endcase
|
||||
|
||||
assign EPC = rf_cp0.EPC;
|
||||
assign CU = rf_cp0.Status.CU;
|
||||
assign Bev = rf_cp0.Status.Bev;
|
||||
assign EBase = rf_cp0.EBase[31:12];
|
||||
|
||||
@ -296,5 +362,6 @@ module CP0 (
|
||||
assign EntryLo0 = rf_cp0.EntryLo0;
|
||||
|
||||
assign in_kernel = ~rf_cp0.Status.UM | rf_cp0.Status.EXL; // currently no ERL
|
||||
assign EXL = rf_cp0.Status.EXL;
|
||||
|
||||
endmodule
|
||||
|
||||
@ -214,8 +214,8 @@ module DCache (
|
||||
end else begin
|
||||
if (port.req) begin
|
||||
if (state != IDLE)
|
||||
LRU[index1] <= nextLRU;
|
||||
nowLRU <= LRU[port.index];
|
||||
LRU[index1] = nextLRU;
|
||||
nowLRU = LRU[port.index];
|
||||
end
|
||||
end
|
||||
end
|
||||
@ -267,60 +267,15 @@ module DCache (
|
||||
wdata2[i] = port.rdata;
|
||||
|
||||
if (port.wvalid) begin
|
||||
case (port.sel1)
|
||||
2'b11: begin
|
||||
if (port.wstrb[3]) wdata1[i][127:120] = port.wdata[31:24];
|
||||
if (port.wstrb[2]) wdata1[i][119:112] = port.wdata[23:16];
|
||||
if (port.wstrb[1]) wdata1[i][111:104] = port.wdata[15: 8];
|
||||
if (port.wstrb[0]) wdata1[i][103: 96] = port.wdata[ 7: 0];
|
||||
end
|
||||
2'b10: begin
|
||||
if (port.wstrb[3]) wdata1[i][95:88] = port.wdata[31:24];
|
||||
if (port.wstrb[2]) wdata1[i][87:80] = port.wdata[23:16];
|
||||
if (port.wstrb[1]) wdata1[i][79:72] = port.wdata[15: 8];
|
||||
if (port.wstrb[0]) wdata1[i][71:64] = port.wdata[ 7: 0];
|
||||
end
|
||||
2'b01: begin
|
||||
if (port.wstrb[3]) wdata1[i][63:56] = port.wdata[31:24];
|
||||
if (port.wstrb[2]) wdata1[i][55:48] = port.wdata[23:16];
|
||||
if (port.wstrb[1]) wdata1[i][47:40] = port.wdata[15: 8];
|
||||
if (port.wstrb[0]) wdata1[i][39:32] = port.wdata[ 7: 0];
|
||||
end
|
||||
2'b00: begin
|
||||
if (port.wstrb[3]) wdata1[i][31:24] = port.wdata[31:24];
|
||||
if (port.wstrb[2]) wdata1[i][23:16] = port.wdata[23:16];
|
||||
if (port.wstrb[1]) wdata1[i][15: 8] = port.wdata[15: 8];
|
||||
if (port.wstrb[0]) wdata1[i][ 7: 0] = port.wdata[ 7: 0];
|
||||
end
|
||||
default: begin end
|
||||
endcase
|
||||
case (port.sel1)
|
||||
2'b11: begin
|
||||
if (port.wstrb[3]) wdata2[i][127:120] = port.wdata[31:24];
|
||||
if (port.wstrb[2]) wdata2[i][119:112] = port.wdata[23:16];
|
||||
if (port.wstrb[1]) wdata2[i][111:104] = port.wdata[15: 8];
|
||||
if (port.wstrb[0]) wdata2[i][103: 96] = port.wdata[ 7: 0];
|
||||
end
|
||||
2'b10: begin
|
||||
if (port.wstrb[3]) wdata2[i][95:88] = port.wdata[31:24];
|
||||
if (port.wstrb[2]) wdata2[i][87:80] = port.wdata[23:16];
|
||||
if (port.wstrb[1]) wdata2[i][79:72] = port.wdata[15: 8];
|
||||
if (port.wstrb[0]) wdata2[i][71:64] = port.wdata[ 7: 0];
|
||||
end
|
||||
2'b01: begin
|
||||
if (port.wstrb[3]) wdata2[i][63:56] = port.wdata[31:24];
|
||||
if (port.wstrb[2]) wdata2[i][55:48] = port.wdata[23:16];
|
||||
if (port.wstrb[1]) wdata2[i][47:40] = port.wdata[15: 8];
|
||||
if (port.wstrb[0]) wdata2[i][39:32] = port.wdata[ 7: 0];
|
||||
end
|
||||
2'b00: begin
|
||||
if (port.wstrb[3]) wdata2[i][31:24] = port.wdata[31:24];
|
||||
if (port.wstrb[2]) wdata2[i][23:16] = port.wdata[23:16];
|
||||
if (port.wstrb[1]) wdata2[i][15: 8] = port.wdata[15: 8];
|
||||
if (port.wstrb[0]) wdata2[i][ 7: 0] = port.wdata[ 7: 0];
|
||||
end
|
||||
default: begin end
|
||||
endcase
|
||||
if (port.wstrb[3]) wdata1[i][{port.sel1, 5'd24}+:8] = port.wdata[24+:8];
|
||||
if (port.wstrb[2]) wdata1[i][{port.sel1, 5'd16}+:8] = port.wdata[16+:8];
|
||||
if (port.wstrb[1]) wdata1[i][{port.sel1, 5'd08}+:8] = port.wdata[08+:8];
|
||||
if (port.wstrb[0]) wdata1[i][{port.sel1, 5'd00}+:8] = port.wdata[00+:8];
|
||||
|
||||
if (port.wstrb[3]) wdata2[i][{port.sel1, 5'd24}+:8] = port.wdata[24+:8];
|
||||
if (port.wstrb[2]) wdata2[i][{port.sel1, 5'd16}+:8] = port.wdata[16+:8];
|
||||
if (port.wstrb[1]) wdata2[i][{port.sel1, 5'd08}+:8] = port.wdata[08+:8];
|
||||
if (port.wstrb[0]) wdata2[i][{port.sel1, 5'd00}+:8] = port.wdata[00+:8];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
@ -149,8 +149,8 @@ module ICache (
|
||||
always_ff @(posedge clk) begin
|
||||
if (port.req) begin
|
||||
if (state != IDLE)
|
||||
LRU[index1] <= nextLRU;
|
||||
nowLRU <= LRU[port.index];
|
||||
LRU[index1] = nextLRU;
|
||||
nowLRU = LRU[port.index];
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
@ -2,34 +2,39 @@
|
||||
|
||||
module ALU(
|
||||
input word_t a, b,
|
||||
input aluctrl_t aluctrl,
|
||||
input ALUCtrl_t aluctrl,
|
||||
output word_t aluout,
|
||||
output logic overflow);
|
||||
output logic valid,
|
||||
output logic overflow
|
||||
);
|
||||
|
||||
wire logic alt = aluctrl.alt;
|
||||
logic alt;
|
||||
logic [4:0] sa;
|
||||
logic ex;
|
||||
word_t sl, sr;
|
||||
word_t b2;
|
||||
word_t sum;
|
||||
logic lt, ltu;
|
||||
|
||||
wire logic [4:0] sa = a[4:0];
|
||||
wire logic ex = alt & b[31];
|
||||
wire word_t sl = b << sa;
|
||||
/* verilator lint_off WIDTH */
|
||||
wire word_t sr = {{31{ex}}, b} >> sa;
|
||||
/* verilator lint_on WIDTH */
|
||||
assign alt = aluctrl.alt;
|
||||
|
||||
wire word_t b2 = alt ? ~b : b;
|
||||
wire word_t sum;
|
||||
wire logic lt, ltu;
|
||||
assign sa = a[4:0];
|
||||
assign ex = alt & b[31];
|
||||
assign sl = b << sa;
|
||||
assign sr = {{31{ex}}, b} >> sa;
|
||||
|
||||
/* verilator lint_off WIDTH */
|
||||
assign b2 = alt ? ~b : b;
|
||||
assign {lt, ltu, sum} = {a[31], 1'b0, a} + {b2[31], 1'b1, b2} + alt; // alt for cin(CARRY4) at synthesis
|
||||
/* verilator lint_on WIDTH */
|
||||
assign aluout = (aluctrl.f_sl ? sl : 32'b0)
|
||||
| (aluctrl.f_sr ? sr : 32'b0)
|
||||
| (aluctrl.f_add ? sum : 32'b0)
|
||||
| (aluctrl.f_and ? a & b : 32'b0)
|
||||
| (aluctrl.f_or ? alt ? ~(a | b) : a | b : 32'b0)
|
||||
| (aluctrl.f_xor ? a ^ b : 32'b0)
|
||||
| (aluctrl.f_slt ? {31'b0, lt } : 32'b0)
|
||||
| (aluctrl.f_sltu ? {31'b0, ltu} : 32'b0)
|
||||
| (aluctrl.f_mova ? a : 32'b0);
|
||||
|
||||
assign valid = ~aluctrl.f_mov | b == 32'h0 ^ alt;
|
||||
assign aluout = (aluctrl.f_sl ? sl : 32'h0)
|
||||
| (aluctrl.f_sr ? sr : 32'h0)
|
||||
| (aluctrl.f_add ? sum : 32'h0)
|
||||
| (aluctrl.f_and ? a & b : 32'h0)
|
||||
| (aluctrl.f_or ? alt ? ~(a | b) : a | b : 32'h0)
|
||||
| (aluctrl.f_xor ? a ^ b : 32'h0)
|
||||
| (aluctrl.f_slt ? {31'b0, lt } : 32'h0)
|
||||
| (aluctrl.f_sltu ? {31'b0, ltu} : 32'h0)
|
||||
| (aluctrl.f_mov ? a : 32'h0);
|
||||
assign overflow = lt ^ sum[31];
|
||||
endmodule
|
||||
|
||||
@ -36,16 +36,17 @@ module Controller (
|
||||
// Take Care of BGO
|
||||
assign ctrl.BGO = ~inst[26] & (eq | inst[27] & ltz) | inst[26] & (~inst[27] & (~inst[28] & (inst[16] & ~ltz | ~inst[16] & ltz) | inst[28] & ~eq) | inst[27] & ~eq & ~ltz);
|
||||
|
||||
assign ctrl.PRV = ~inst[31] & inst[30] & ~inst[29];
|
||||
assign ctrl.SYSCALL = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[3] & inst[2] & ~inst[0];
|
||||
assign ctrl.BREAK = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[3] & inst[2] & ~inst[1] & inst[0];
|
||||
assign ctrl.ERET = ~inst[31] & inst[30] & inst[4];
|
||||
assign ctrl.OFA = ~inst[26] & ~inst[30] & (~inst[29] & ~inst[31] & ~inst[28] & ~inst[27] & inst[5] & ~inst[0] & ~inst[4] & ~inst[2] & ~inst[3] | inst[29] & ~inst[27] & ~inst[31] & ~inst[28]);
|
||||
|
||||
assign ctrl.ES = ~inst[30] & (~inst[28] & ~inst[27] & (~inst[26] & (~inst[3] & inst[2] | inst[3] & (inst[1] | inst[4]) | inst[5]) | inst[26] & inst[19]) | inst[31]) | inst[29];
|
||||
assign ctrl.ET = ~inst[26] & ~inst[27] & ~inst[31] & (~inst[30] & ~inst[29] & ~inst[28] & (~inst[3] & ~inst[4] | inst[3] & inst[4] | inst[5]) | inst[30] & inst[29]);
|
||||
assign ctrl.DS = ~inst[26] & (~inst[28] & ~inst[30] & ~inst[31] & ~inst[29] & ~inst[27] & inst[3] & ~inst[1] & ~inst[4] & ~inst[2] | inst[28] & ~inst[29] & ~inst[31]) | inst[26] & ~inst[31] & ~inst[29] & (~inst[27] & ~inst[19] | inst[28]);
|
||||
assign ctrl.DT = ~inst[28] & ~inst[26] & ~inst[30] & ~inst[31] & ~inst[29] & ~inst[27] & inst[3] & inst[1] & ~inst[5] & ~inst[4] | inst[28] & ~inst[29] & ~inst[31] & ~inst[27];
|
||||
assign ctrl.ES = ~inst[31] & ~inst[27] & (~inst[30] & ~inst[29] & ~inst[28] & (~inst[26] & (~inst[4] & ~inst[2] & (~inst[5] & inst[3] & inst[1] | inst[5] & ~inst[3] & ~inst[0]) | inst[4] & (inst[5] | inst[3])) | inst[26] & inst[19]) | inst[29] & (inst[30] | ~inst[28] & ~inst[26])) | inst[31] & ~inst[30];
|
||||
assign ctrl.ET = ~inst[27] & ~inst[26] & (~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & (~inst[4] & ~inst[2] & (~inst[5] & inst[3] & inst[1] | inst[5] & ~inst[3] & ~inst[0]) | inst[4] & (inst[5] | inst[3])) | inst[30] & inst[29]);
|
||||
assign ctrl.ES2 = ~inst[30] & ~inst[28] & ~inst[27] & ~inst[26] & (inst[5] | ~inst[3] & inst[2]) | inst[29];
|
||||
assign ctrl.ET2 = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & (inst[5] | ~inst[4] & ~inst[3]);
|
||||
assign ctrl.DS = ~inst[26] & (~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[4] & inst[3] & ~inst[2] & ~inst[1] | ~inst[31] & ~inst[29] & inst[28]) | ~inst[31] & ~inst[29] & inst[26] & (inst[28] | ~inst[27] & ~inst[19]);
|
||||
assign ctrl.DT = ~inst[31] & ~inst[29] & inst[28] & ~inst[27];
|
||||
|
||||
assign ctrl.DP0 = ~inst[31] & (~inst[30] & (~inst[26] & (~inst[4] | ~inst[5] | inst[27] | inst[28]) | inst[26] & (~inst[19] | inst[27] | inst[28])) | inst[30] & (~inst[25] | inst[4]) | inst[29]) | inst[31] & inst[30];
|
||||
assign ctrl.DP1 = ~inst[30] & (~inst[4] | inst[5] | inst[28] | inst[29] | inst[31] | inst[27] | inst[26]) | inst[30] & ~inst[29] & (inst[25] | inst[31]);
|
||||
@ -58,11 +59,11 @@ module Controller (
|
||||
assign ctrl.ECtrl.OP.f_xor = ~inst[31] & (~inst[28] & ~inst[26] & ~inst[27] & ~inst[29] & inst[5] & ~inst[0] & inst[2] & ~inst[4] & inst[1] | inst[28] & inst[27]);
|
||||
assign ctrl.ECtrl.OP.f_slt = ~inst[31] & ~inst[28] & (~inst[26] & (~inst[29] & inst[5] & ~inst[0] & ~inst[2] & (inst[3] | inst[4]) | inst[27]) | inst[26] & ~inst[29] & ~inst[27] & ~inst[16] & ~inst[18] & ~inst[20]);
|
||||
assign ctrl.ECtrl.OP.f_sltu = ~inst[31] & ~inst[28] & (~inst[26] & ~inst[27] & ~inst[29] & inst[5] & inst[0] & ~inst[2] & (inst[3] | inst[4]) | inst[26] & (~inst[29] & ~inst[27] & inst[16] & ~inst[20] | inst[29] & inst[27]));
|
||||
assign ctrl.ECtrl.OP.f_mova = ~inst[31] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[5] & inst[3] & inst[1];
|
||||
assign ctrl.ECtrl.OP.alt = ~inst[31] & ~inst[28] & (~inst[29] & ~inst[27] & (~inst[26] & (inst[1] & (inst[0] | inst[5]) | inst[4]) | inst[26] & ~inst[20]) | inst[29] & inst[27]);
|
||||
assign ctrl.ECtrl.OP.f_mov = ~inst[31] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[5] & inst[3] & inst[1];
|
||||
assign ctrl.ECtrl.OP.alt = ~inst[31] & ~inst[28] & (~inst[29] & ~inst[27] & (~inst[26] & (inst[4] | inst[1] & (inst[5] | inst[0])) | inst[26] & ~inst[20]) | inst[29] & inst[27]);
|
||||
|
||||
assign ctrl.ECtrl.SA = SA_t'({(~inst[27] & (~inst[26] & ((inst[3] & inst[1] | inst[2]) | inst[5]) | inst[26] & ~inst[20]) | inst[31]) | inst[29], (~inst[28] & (inst[2] | inst[3] | inst[5] | inst[29] | inst[26]) | inst[28] & (~inst[27] | ~inst[26])) | inst[31]});
|
||||
assign ctrl.ECtrl.SB = SB_t'({(inst[26] & ~inst[27] & ~inst[20] | inst[31]) | inst[29], inst[3] & ~inst[5] | inst[26]});
|
||||
assign ctrl.ECtrl.SB = SB_t'({inst[31] | inst[29] | ~inst[27] & inst[26] & ~inst[20], inst[26] | inst[3] & ~inst[1]});
|
||||
|
||||
assign ctrl.MCtrl0.HW = ~inst[30] & ~inst[26] & ~inst[29] & ~inst[28] & ~inst[27] & inst[4] & (~inst[5] & ~inst[1] & inst[0] | inst[3]) | inst[30] & inst[29] & ~inst[1];
|
||||
assign ctrl.MCtrl0.LW = ~inst[30] & ~inst[26] & ~inst[29] & ~inst[28] & ~inst[27] & inst[4] & (~inst[5] & inst[1] & inst[0] | inst[3]) | inst[30] & inst[29] & ~inst[1];
|
||||
@ -73,24 +74,29 @@ module Controller (
|
||||
assign ctrl.MCtrl0.SEL = inst[2:0];
|
||||
assign ctrl.MCtrl0.RS0 = RS0_t'({~inst[30] & (~inst[4] | inst[5] | inst[29] | inst[26]), inst[30], ~inst[29] & (~inst[1] | inst[30])});
|
||||
|
||||
assign ctrl.MCtrl1.MR = inst[31] & ~inst[30];
|
||||
assign ctrl.MCtrl1.MR = inst[31] & (~inst[26] | inst[26] & (~inst[27] | inst[27] & ~inst[28] & ~inst[30]));
|
||||
assign ctrl.MCtrl1.MWR = inst[29];
|
||||
assign ctrl.MCtrl1.MX = ~inst[28];
|
||||
assign ctrl.MCtrl1.ALR = ALR_t'({inst[28] & inst[27] & ~inst[26], ~inst[28] & inst[27] & ~inst[26]});
|
||||
assign ctrl.MCtrl1.SZ = inst[27:26];
|
||||
|
||||
`ifdef TLB_ENABLE
|
||||
assign ctrl.MCtrl1.TLBR = ~inst[31] & inst[30] & ~inst[29] & inst[25] & ~inst[3] & ~inst[1];
|
||||
assign ctrl.MCtrl1.TLBWI = ~inst[31] & inst[30] & ~inst[29] & inst[25] & ~inst[3] & inst[1];
|
||||
assign ctrl.MCtrl1.TLBWR = ~inst[31] & inst[30] & ~inst[29] & inst[25] & ~inst[3] & (inst[2] | ~inst[1]);
|
||||
assign ctrl.MCtrl1.TLBP = ~inst[31] & inst[30] & ~inst[4] & inst[3];
|
||||
`else
|
||||
assign ctrl.MCtrl1.TLBR = 1'b0;
|
||||
assign ctrl.MCtrl1.TLBWI = 1'b0;
|
||||
assign ctrl.MCtrl1.TLBWR = 1'b0;
|
||||
assign ctrl.MCtrl1.TLBP = 1'b0;
|
||||
`endif
|
||||
|
||||
assign ctrl.MCtrl1.CACHE_OP = CacheOp_t'({inst[29] & inst[28] & inst[26] & inst[16], inst[29] & inst[28] & inst[26] & ~inst[20], inst[29] & inst[28] & inst[26] & ~inst[18] & (inst[20] | inst[19] | ~inst[16])});
|
||||
|
||||
assign ctrl.Trap.TEN = ~inst[30] & ~inst[27] & (~inst[26] & ~inst[31] & ~inst[29] & ~inst[28] & inst[4] & inst[5] | inst[26] & ~inst[31] & ~inst[29] & ~inst[28] & inst[19]) | inst[30] & ~inst[29] & ~inst[31];
|
||||
assign ctrl.Trap.TEN = ~inst[31] & ~inst[29] & ~inst[28] & ~inst[27] & (~inst[30] & ~inst[26] & inst[5] & inst[4] | inst[26] & inst[19]);
|
||||
assign ctrl.Trap.TP = TrapOp_t'({~inst[26] & inst[2] | inst[26] & inst[18], ~inst[26] & inst[1] | inst[26] & inst[17]});
|
||||
|
||||
logic mov, rw, eqz;
|
||||
assign mov = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[5] & ~inst[4] & inst[3] & ~inst[2] & inst[1];
|
||||
assign rw = ~inst[30] & (~inst[26] & (~inst[27] & (~inst[31] & (~inst[28] & (~inst[4] & (~inst[3] | ~inst[2] & (inst[0] | inst[1])) | inst[4] & ~inst[5] & ~inst[3] & ~inst[0]) | inst[29]) | inst[31] & ~inst[29]) | inst[27] & (~inst[31] & inst[29] | inst[31] & ~inst[29])) | inst[26] & (~inst[29] & (~inst[27] & ~inst[28] & inst[20] | inst[27] & ~inst[28] | inst[31]) | inst[29] & ~inst[31])) | inst[30] & ~inst[31] & ~inst[3] & (~inst[29] & ~inst[25] & ~inst[23] | inst[29] & inst[1]);
|
||||
assign eqz = rt == 32'h0;
|
||||
assign ctrl.WCtrl.RW = ctrl.RD != 5'b00000 & (~mov | ~inst[0] & eqz | inst[0] & ~eqz) & rw;
|
||||
assign ctrl.WCtrl.RW = ctrl.RD != 5'b00000 & (~inst[30] & (~inst[26] & (~inst[27] & (~inst[31] & (~inst[28] & (~inst[4] & (~inst[3] | ~inst[2] & (inst[0] | inst[1])) | inst[4] & ~inst[5] & ~inst[3] & ~inst[0]) | inst[29]) | inst[31] & ~inst[29]) | inst[27] & (~inst[31] & inst[29] | inst[31] & ~inst[29])) | inst[26] & (~inst[29] & (~inst[27] & ~inst[28] & inst[20] | inst[27] & ~inst[28] | inst[31]) | inst[29] & ~inst[31])) | inst[30] & ~inst[31] & ~inst[3] & (~inst[29] & ~inst[25] & ~inst[23] | inst[29] & inst[1]));
|
||||
|
||||
endmodule
|
||||
|
||||
@ -33,8 +33,10 @@ module Datapath (
|
||||
output word_t C0_wdata,
|
||||
output EXCEPTION_t C0_exception,
|
||||
input word_t C0_ERETPC,
|
||||
input logic C0_EXL,
|
||||
input logic C0_Bev,
|
||||
input logic [19:0] C0_EBase,
|
||||
input logic [3:0] C0_CU,
|
||||
input logic C0_kernel,
|
||||
|
||||
//debug interface
|
||||
@ -124,8 +126,10 @@ module Datapath (
|
||||
|
||||
logic D_IA_valid;
|
||||
logic D_IB_valid;
|
||||
logic D_IA_iv;
|
||||
logic D_IB_iv;
|
||||
logic D_IA_ri;
|
||||
logic D_IB_ri;
|
||||
logic D_IA_cpu;
|
||||
logic D_IB_cpu;
|
||||
|
||||
logic D_IA_TLBRefill;
|
||||
logic D_IA_TLBInvalid;
|
||||
@ -134,6 +138,8 @@ module Datapath (
|
||||
logic D_IB_TLBInvalid;
|
||||
logic D_IB_AddressError;
|
||||
|
||||
logic D_IA_HazardALU2;
|
||||
logic D_IB_HazardALU2;
|
||||
logic D_IA_Hazard;
|
||||
logic D_IB_Hazard;
|
||||
|
||||
@ -146,7 +152,9 @@ module Datapath (
|
||||
|
||||
word_t E_I0_A;
|
||||
word_t E_I0_B;
|
||||
logic E_I0_ALUvalid;
|
||||
logic E_I0_Overflow;
|
||||
WCtrl_t E_I0_NowWCtrl;
|
||||
logic E_I0_NowExcValid;
|
||||
logic E_I0_NowExcValidWithoutOF;
|
||||
logic E_I0_PrevExcValid;
|
||||
@ -158,7 +166,9 @@ module Datapath (
|
||||
word_t E_I1_A;
|
||||
word_t E_I1_B;
|
||||
word_t E_I1_ADDR;
|
||||
logic E_I1_ALUvalid;
|
||||
logic E_I1_Overflow;
|
||||
WCtrl_t E_I1_NowWCtrl;
|
||||
logic E_I1_STRBERROR;
|
||||
logic E_I1_NowExcValid;
|
||||
logic E_I1_NowExcValidWithoutOF;
|
||||
@ -214,6 +224,11 @@ module Datapath (
|
||||
word_t M_I1_MDataUR;
|
||||
word_t M_I1_MData;
|
||||
|
||||
word_t M_I0_A;
|
||||
word_t M_I0_B;
|
||||
logic M_I0_ALUvalid;
|
||||
logic M_I0_Overflow;
|
||||
|
||||
logic M_I0_DIV_valid;
|
||||
word_t M_I0_DIVH;
|
||||
word_t M_I0_DIVL;
|
||||
@ -228,7 +243,7 @@ module Datapath (
|
||||
word_t M_I0_DIVUHB;
|
||||
word_t M_I0_DIVULB;
|
||||
|
||||
logic [5:0] M_I0_MULT_CNTR;
|
||||
logic M_I0_MULT_CNTR;
|
||||
|
||||
word_t M_I0_MULTH;
|
||||
word_t M_I0_MULTL;
|
||||
@ -280,6 +295,7 @@ module Datapath (
|
||||
word_t HI;
|
||||
word_t LO;
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------//
|
||||
// Pre Fetch //
|
||||
//---------------------------------------------------------------------------//
|
||||
@ -297,7 +313,7 @@ module Datapath (
|
||||
{C0_Bev ? 23'h5fe001 : {C0_EBase, 3'h0}, `Off_GExc},
|
||||
{C0_Bev ? 23'h5fe001 : {C0_EBase, 3'h0}, `Off_TRef},
|
||||
C0_ERETPC,
|
||||
{M_exception.ERET, M_exception_REFILL, M_exception.ExcValid, ~D_IB_valid | ~D.IA.BJRJ | D.IA.B & ~D.IA.BGO},
|
||||
{M_exception.ERET, M_exception_REFILL & ~C0_EXL, M_exception.ExcValid, ~D_IB_valid | ~D.IA.BJRJ | D.IA.B & ~D.IA.BGO},
|
||||
PF.pc
|
||||
);
|
||||
|
||||
@ -448,57 +464,87 @@ module Datapath (
|
||||
);
|
||||
|
||||
// D.Exc
|
||||
instr_valid D_IA_instr_valid (
|
||||
decoder2 D_IA_decoder2 (
|
||||
D.IA_inst,
|
||||
D_IA_iv
|
||||
C0_CU,
|
||||
C0_kernel,
|
||||
D_IA_ri,
|
||||
D_IA_cpu,
|
||||
D.IA_CE
|
||||
);
|
||||
instr_valid D_IB_instr_valid (
|
||||
decoder2 D_IB_decoder2 (
|
||||
D.IB_inst,
|
||||
D_IB_iv
|
||||
C0_CU,
|
||||
C0_kernel,
|
||||
D_IB_ri,
|
||||
D_IB_cpu,
|
||||
D.IB_CE
|
||||
);
|
||||
|
||||
// INFO: Merge "pc[1:0] != 2'b00" into AddressError
|
||||
assign D.IA_ExcValid = D_IA_valid & ( D.IA_pc[1:0] != 2'b00
|
||||
| ~D_IA_iv
|
||||
| D_IA_ri | D_IA_cpu
|
||||
| D_IA_TLBRefill | D_IA_TLBInvalid
|
||||
| D_IA_AddressError
|
||||
| D.IA.SYSCALL | D.IA.BREAK | D.IA.ERET
|
||||
| D.IA.PRV & ~C0_kernel);
|
||||
assign D.IA_ERET = D_IA_valid & D.IA_pc[1:0] == 2'b00 & ~D_IA_TLBRefill & ~D_IA_TLBInvalid & ~D_IA_AddressError & D_IA_iv & D.IA.ERET;
|
||||
| D.IA.SYSCALL | D.IA.BREAK | D.IA.ERET);
|
||||
assign D.IA_ERET = D_IA_valid & D.IA_pc[1:0] == 2'b00 & ~D_IA_TLBRefill & ~D_IA_TLBInvalid & ~D_IA_AddressError & ~D_IA_ri & ~D_IA_cpu & D.IA.ERET;
|
||||
assign D.IA_REFILL = D_IA_valid & D.IB_pc[1:0] == 2'b00 & D_IA_TLBRefill;
|
||||
assign D.IA_ExcCode = D.IA_pc[1:0] != 2'b00 | D_IA_AddressError ? `EXCCODE_ADEL
|
||||
: D_IA_TLBRefill ? `EXCCODE_TLBL
|
||||
: D_IA_TLBInvalid ? `EXCCODE_TLBL
|
||||
: ~D_IA_iv ? `EXCCODE_RI
|
||||
: D_IA_cpu ? `EXCCODE_CPU
|
||||
: D_IA_ri ? `EXCCODE_RI
|
||||
: ~D.IA_inst[30] & D.IA_inst[0] ? `EXCCODE_BP
|
||||
: ~D.IA_inst[30] & ~D.IA_inst[0] ? `EXCCODE_SYS
|
||||
: `EXCCODE_CPU;
|
||||
: `EXCCODE_RI;
|
||||
|
||||
assign D.IB_ExcValid = D_IB_valid & ( D.IB_pc[1:0] != 2'b00
|
||||
| ~D_IB_iv
|
||||
| D_IB_ri | D_IB_cpu
|
||||
| D_IB_TLBRefill | D_IB_TLBInvalid
|
||||
| D_IB_AddressError
|
||||
| D.IB.SYSCALL | D.IB.BREAK | D.IB.ERET
|
||||
| D.IB_Delay & D.IB.BJRJ
|
||||
| D.IB.PRV & ~C0_kernel);
|
||||
assign D.IB_ERET = D_IB_valid & D.IB_pc[1:0] == 2'b00 & ~D_IB_TLBRefill & ~D_IB_TLBInvalid & ~D_IB_AddressError & D_IB_iv & D.IB.ERET & ~D.IB_Delay;
|
||||
| D.IB_Delay & D.IB.BJRJ);
|
||||
assign D.IB_ERET = D_IB_valid & D.IB_pc[1:0] == 2'b00 & ~D_IB_TLBRefill & ~D_IB_TLBInvalid & ~D_IB_AddressError & ~D_IB_ri & ~D_IB_cpu & D.IB.ERET & ~D.IB_Delay;
|
||||
assign D.IB_REFILL = D_IB_valid & D.IB_pc[1:0] == 2'b00 & D_IB_TLBRefill;
|
||||
// EXCCODE_BP and EXCCODE_SYSCALL -> exc.txt
|
||||
assign D.IB_ExcCode = D.IB_pc[1:0] != 2'b00 | D_IB_AddressError ? `EXCCODE_ADEL
|
||||
: D_IB_TLBRefill ? `EXCCODE_TLBL
|
||||
: D_IB_TLBInvalid ? `EXCCODE_TLBL
|
||||
: ~D_IB_iv ? `EXCCODE_RI
|
||||
: D_IB_cpu ? `EXCCODE_CPU
|
||||
: D_IB_ri ? `EXCCODE_RI
|
||||
: D.IB.ERET ? `EXCCODE_RI
|
||||
: D.IB_Delay & D.IB.BJRJ ? `EXCCODE_RI
|
||||
: ~D.IB_inst[30] & D.IB_inst[0] ? `EXCCODE_BP
|
||||
: ~D.IB_inst[30] & ~D.IB_inst[0] ? `EXCCODE_SYS
|
||||
: `EXCCODE_CPU;
|
||||
: `EXCCODE_RI;
|
||||
assign D.IB_Delay = D.IA.BJRJ;
|
||||
|
||||
// D.Dispatch
|
||||
// Not Arith -> Arith
|
||||
assign D_IA_Hazard = E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.ES & ~E.I0.MCtrl.RS0[2]
|
||||
| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.ET & ~E.I0.MCtrl.RS0[2]
|
||||
assign D_IA_HazardALU2 = E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.ES2 & ~E.I0.MCtrl_ALU1
|
||||
| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.ET2 & ~E.I0.MCtrl_ALU1
|
||||
// Load -> Arith
|
||||
| E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.ES2 & E.I1.MCtrl.MR
|
||||
| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.ET2 & E.I1.MCtrl.MR
|
||||
;
|
||||
|
||||
// Not Arith -> Arith
|
||||
assign D_IB_HazardALU2 = E.I0.WCtrl.RW & D.IB.RS == E.I0.RD & D.IB.ES2 & ~E.I0.MCtrl_ALU1
|
||||
| E.I0.WCtrl.RW & D.IB.RT == E.I0.RD & D.IB.ET2 & ~E.I0.MCtrl_ALU1
|
||||
// Load -> Arith
|
||||
| E.I1.WCtrl.RW & D.IB.RS == E.I1.RD & D.IB.ES2 & E.I1.MCtrl.MR
|
||||
| E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & D.IB.ET2 & E.I1.MCtrl.MR
|
||||
// Arith -> Arith
|
||||
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ES2
|
||||
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ET2
|
||||
;
|
||||
|
||||
assign D.A = ~(D.IA.DP0 & D.IA.DP1 | D.IA_ExcValid) ? D.IA.DP1 : D.IB.DP0 & ~D_IA_HazardALU2;
|
||||
|
||||
// D.Dispatch
|
||||
assign D_IA_Hazard = D_IA_HazardALU2 & D.A
|
||||
// Not Arith -> Arith
|
||||
| E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.ES & ~E.I0.MCtrl_ALU1
|
||||
| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.ET & ~E.I0.MCtrl_ALU1
|
||||
// Load -> Arith
|
||||
| E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.ES & E.I1.MCtrl.MR
|
||||
| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.ET & E.I1.MCtrl.MR
|
||||
@ -508,8 +554,8 @@ module Datapath (
|
||||
| E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.DS
|
||||
| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.DT
|
||||
// Not Arith -> B / JR
|
||||
| M.I0.WCtrl.RW & D.IA.RS == M.I0.RD & D.IA.DS & ~M.I0.MCtrl.RS0[2]
|
||||
| M.I0.WCtrl.RW & D.IA.RT == M.I0.RD & D.IA.DT & ~M.I0.MCtrl.RS0[2]
|
||||
| M.I0.WCtrl.RW & D.IA.RS == M.I0.RD & D.IA.DS & ~M.I0.MCtrl_ALU1
|
||||
| M.I0.WCtrl.RW & D.IA.RT == M.I0.RD & D.IA.DT & ~M.I0.MCtrl_ALU1
|
||||
// Load -> B / JR
|
||||
| M.I1.WCtrl.RW & D.IA.RS == M.I1.RD & D.IA.DS & M.I1.MCtrl.MR
|
||||
| M.I1.WCtrl.RW & D.IA.RT == M.I1.RD & D.IA.DT & M.I1.MCtrl.MR
|
||||
@ -518,23 +564,27 @@ module Datapath (
|
||||
| E.I0.MCtrl.C0W & D.IA.MCtrl1.TLBP & E.I0.MCtrl.C0D == C0_ENTRYHI
|
||||
;
|
||||
|
||||
assign D_IB_Hazard = D_IB_HazardALU2 & ~D.A
|
||||
// Not Arith -> Arith
|
||||
assign D_IB_Hazard = E.I0.WCtrl.RW & D.IB.RS == E.I0.RD & D.IB.ES & ~E.I0.MCtrl.RS0[2]
|
||||
| E.I0.WCtrl.RW & D.IB.RT == E.I0.RD & D.IB.ET & ~E.I0.MCtrl.RS0[2]
|
||||
| E.I0.WCtrl.RW & D.IB.RS == E.I0.RD & D.IB.ES & ~E.I0.MCtrl_ALU1
|
||||
| E.I0.WCtrl.RW & D.IB.RT == E.I0.RD & D.IB.ET & ~E.I0.MCtrl_ALU1
|
||||
// Load -> Arith
|
||||
| E.I1.WCtrl.RW & D.IB.RS == E.I1.RD & D.IB.ES & E.I1.MCtrl.MR
|
||||
| E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & D.IB.ET & E.I1.MCtrl.MR
|
||||
// Arith -> Arith
|
||||
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ES
|
||||
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ET
|
||||
// Load -> Arith2
|
||||
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ES2 & ~D.IA.DP0
|
||||
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ET2 & ~D.IA.DP0
|
||||
// Load -> MulDiv
|
||||
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.MCtrl0.HLS[2] & ~D.IA.DP0
|
||||
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & ~D.IB.MCtrl0.HLS[2] & (D.IB.MCtrl0.HW | D.IB.MCtrl0.LW) & ~D.IA.DP0
|
||||
// Load -> C0
|
||||
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl0.C0W & ~D.IA.DP0
|
||||
// Not Arith -> Store
|
||||
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl1.MWR & ~D.IA.DP1
|
||||
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl1.MWR & (~D.IA.DP1 | D_IA_HazardALU2)
|
||||
// Not Arith -> LWL/LWR
|
||||
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & |D.IB.MCtrl1.ALR & ~D.IA.DP1
|
||||
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & |D.IB.MCtrl1.ALR & (~D.IA.DP1 | D_IA_HazardALU2)
|
||||
// CP0 Execution Hazards
|
||||
// Hazards Related to the TLB
|
||||
| D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBR & D.IA.MCtrl0.C0D == C0_INDEX
|
||||
@ -558,8 +608,6 @@ module Datapath (
|
||||
| D.IA.MCtrl0.C0W & D.IB.ERET & D.IA.MCtrl0.C0D == C0_EPC
|
||||
;
|
||||
|
||||
assign D.A = (D.IA.DP0 & D.IA.DP1 | D.IA_ExcValid) ? D.IB.DP0 : D.IA.DP1;
|
||||
|
||||
assign D_IA_can_dispatch = ~D_IA_valid | D.IA_ExcValid | ~D_IA_Hazard & (~D.IA.BJRJ | D_IB_valid);
|
||||
assign D_IB_can_dispatch = ~D_IB_valid | D.IB_ExcValid & ~(D.IB.ERET & ~D.IB_Delay) | ~D_IB_Hazard & ~D.IB.BJRJ & (D.A ? D.IB.DP0 : D.IB.DP1);
|
||||
|
||||
@ -579,6 +627,7 @@ module Datapath (
|
||||
assign D.I0.ERET = D.A ? D.IB_ERET : D.IA_ERET;
|
||||
assign D.I0.REFILL = D.A ? D.IB_REFILL : D.IA_REFILL;
|
||||
assign D.I0.ExcCode = D.A ? D.IB_ExcCode : D.IA_ExcCode;
|
||||
assign D.I0.CE = D.A ? D.IB_CE : D.IA_CE;
|
||||
assign D.I0.Delay = D.A ? D.IB_Delay : D.IA_Delay;
|
||||
assign D.I0.OFA = D.A ? D.IB.OFA : D.IA.OFA;
|
||||
assign D.I0.RS = D.A ? D.IB.RS : D.IA.RS;
|
||||
@ -589,12 +638,14 @@ module Datapath (
|
||||
assign D.I0.sa = D.A ? D.IB_sa : D.IA_sa;
|
||||
assign D.I0.ECtrl = D.A ? D.IB.ECtrl : D.IA.ECtrl;
|
||||
assign D.I0.MCtrl = D.A ? D.IB.MCtrl0 : D.IA.MCtrl0;
|
||||
assign D.I0.MCtrl_ALU1 = D.I0.MCtrl.RS0[2] & (D.A ? ~D_IB_HazardALU2 : ~D_IA_HazardALU2);
|
||||
assign D.I0.RD = D.A ? D.IB.RD : D.IA.RD;
|
||||
assign D.I0.WCtrl = D.A ? D.IB.WCtrl : D.IA.WCtrl;
|
||||
|
||||
assign D_I1_go = D.A ? D_IA_go : D_IB_go;
|
||||
assign D.I1.pc = D.A ? D.IA_pc : D.IB_pc;
|
||||
assign D.I1.ExcValid = D.A ? D.IA_ExcValid : D.IB_ExcValid;
|
||||
assign D.I1.CE = D.A ? D.IA_CE : D.IB_CE;
|
||||
assign D.I1.ERET = D.A ? D.IA_ERET : D.IB_ERET;
|
||||
assign D.I1.REFILL = D.A ? D.IA_REFILL : D.IB_REFILL;
|
||||
assign D.I1.ExcCode = D.A ? D.IA_ExcCode : D.IB_ExcCode;
|
||||
@ -685,13 +736,13 @@ module Datapath (
|
||||
E.en,
|
||||
E.I0.pc
|
||||
);
|
||||
ffenrc #(1 + 1 + 1 + 5 + 1) E_I0_Exc_ff (
|
||||
ffenrc #(1 + 1 + 1 + 5 + 2 + 1) E_I0_Exc_ff (
|
||||
clk,
|
||||
rst | rstM,
|
||||
{D.I0.ExcValid, D.I0.ERET, D.I0.REFILL, D.I0.ExcCode, D.I0.Delay},
|
||||
{D.I0.ExcValid, D.I0.ERET, D.I0.REFILL, D.I0.ExcCode, D.I0.CE, D.I0.Delay},
|
||||
E.en,
|
||||
~D_go,
|
||||
{E_I0_PrevExcValid, E_I0_PrevERET, E_I0_PrevREFILL, E_I0_PrevExcCode, E.I0.Delay}
|
||||
{E_I0_PrevExcValid, E_I0_PrevERET, E_I0_PrevREFILL, E_I0_PrevExcCode, E.I0.CE, E.I0.Delay}
|
||||
);
|
||||
ffenrc #(1) E_I0_ExcCtrl_ff (
|
||||
clk,
|
||||
@ -725,13 +776,13 @@ module Datapath (
|
||||
E.en,
|
||||
E.I0.ECtrl
|
||||
);
|
||||
ffenrc #(19) E_I0_MCtrl_ff (
|
||||
ffenrc #(20) E_I0_MCtrl_ff (
|
||||
clk,
|
||||
rst | rstM,
|
||||
D.I0.MCtrl,
|
||||
{D.I0.MCtrl, D.I0.MCtrl_ALU1},
|
||||
E.en,
|
||||
~D_go | ~D_I0_go,
|
||||
E.I0.MCtrl
|
||||
{E.I0.MCtrl, E.I0.MCtrl_ALU1}
|
||||
);
|
||||
ffenrc #(5 + 1) E_I0_WCtrl_ff (
|
||||
clk,
|
||||
@ -748,13 +799,13 @@ module Datapath (
|
||||
E.en,
|
||||
E.I1.pc
|
||||
);
|
||||
ffenrc #(1 + 1 + 1 + 5 + 1) E_I1_Exc_ff (
|
||||
ffenrc #(1 + 1 + 1 + 5 + 2 + 1) E_I1_Exc_ff (
|
||||
clk,
|
||||
rst | rstM,
|
||||
{D.I1.ExcValid, D.I1.ERET, D.I1.REFILL, D.I1.ExcCode, D.I1.Delay},
|
||||
{D.I1.ExcValid, D.I1.ERET, D.I1.REFILL, D.I1.ExcCode, D.I1.CE, D.I1.Delay},
|
||||
E.en,
|
||||
~D_go,
|
||||
{E_I1_PrevExcValid, E_I1_PrevERET, E_I1_PrevREFILL, E_I1_PrevExcCode, E.I1.Delay}
|
||||
{E_I1_PrevExcValid, E_I1_PrevERET, E_I1_PrevREFILL, E_I1_PrevExcCode, E.I1.CE, E.I1.Delay}
|
||||
);
|
||||
ffenrc #(1) E_I1_ExcCtrl_ff (
|
||||
clk,
|
||||
@ -788,7 +839,7 @@ module Datapath (
|
||||
E.en,
|
||||
E.I1.ECtrl
|
||||
);
|
||||
ffenrc #(14) E_I1_MCtrl_ff (
|
||||
ffenrc #(15) E_I1_MCtrl_ff (
|
||||
clk,
|
||||
rst | rstM,
|
||||
D.I1.MCtrl,
|
||||
@ -860,8 +911,10 @@ module Datapath (
|
||||
E_I0_B,
|
||||
E.I0.ECtrl.OP,
|
||||
E.I0.ALUOut,
|
||||
E_I0_ALUvalid,
|
||||
E_I0_Overflow
|
||||
);
|
||||
assign E_I0_NowWCtrl.RW = E.I0.WCtrl.RW & (~E.I0.MCtrl_ALU1 | E_I0_ALUvalid);
|
||||
|
||||
// E.I0.MUL
|
||||
mul_signed E_I0_MULT_mul (
|
||||
@ -918,8 +971,10 @@ module Datapath (
|
||||
E_I1_B,
|
||||
E.I1.ECtrl.OP,
|
||||
E.I1.ALUOut,
|
||||
E_I1_ALUvalid,
|
||||
E_I1_Overflow
|
||||
);
|
||||
assign E_I1_NowWCtrl.RW = E.I1.WCtrl.RW & (E.I1.MCtrl.MR | E_I1_ALUvalid);
|
||||
|
||||
// E.I1.MEM
|
||||
memerror E_I1_memerror (
|
||||
@ -1007,13 +1062,13 @@ module Datapath (
|
||||
M.en,
|
||||
M.I0.pc
|
||||
);
|
||||
ffenrc #(1 + 1 + 1 + 5 + 1) M_I0_Exc_ff (
|
||||
ffenrc #(1 + 1 + 1 + 5 + 2 + 1) M_I0_Exc_ff (
|
||||
clk,
|
||||
rst | rstM,
|
||||
{E.I0.ExcValid, E.I0.ERET, E.I0.REFILL, E.I0.ExcCode, E.I0.Delay},
|
||||
{E.I0.ExcValid, E.I0.ERET, E.I0.REFILL, E.I0.ExcCode, E.I0.CE, E.I0.Delay},
|
||||
M.en,
|
||||
~E_go,
|
||||
{M.I0.ExcValid, M.I0.ERET, M.I0.REFILL, M.I0.ExcCode, M.I0.Delay}
|
||||
{M.I0.ExcValid, M.I0.ERET, M.I0.REFILL, M.I0.ExcCode, M.I0.CE, M.I0.Delay}
|
||||
);
|
||||
ffen #(5 + 5) M_I0_RST_ff (
|
||||
clk,
|
||||
@ -1033,26 +1088,38 @@ module Datapath (
|
||||
M.en,
|
||||
M.I0.ALUOut
|
||||
);
|
||||
ffenrc #(19) M_I0_MCtrl_ff (
|
||||
ffen #(32 + 5) M_I0_IS_ff (
|
||||
clk,
|
||||
{E.I0.imm, E.I0.sa},
|
||||
M.en,
|
||||
{M.I0.imm, M.I0.sa}
|
||||
);
|
||||
ffen #(14) M_I0_ECtrl_ff (
|
||||
clk,
|
||||
E.I0.ECtrl,
|
||||
M.en,
|
||||
M.I0.ECtrl
|
||||
);
|
||||
ffenrc #(20) M_I0_MCtrl_ff (
|
||||
clk,
|
||||
rst | rstM,
|
||||
E.I0.MCtrl,
|
||||
{E.I0.MCtrl, E.I0.MCtrl_ALU1},
|
||||
M.en,
|
||||
~E_go | ~E_I0_go,
|
||||
M.I0.MCtrl
|
||||
{M.I0.MCtrl, M.I0.MCtrl_ALU1}
|
||||
);
|
||||
ffenrc #(5 + 1) M_I0_WCtrl_ff (
|
||||
clk,
|
||||
rst | rstM,
|
||||
{E.I0.RD, E.I0.WCtrl},
|
||||
{E.I0.RD, E_I0_NowWCtrl},
|
||||
M.en,
|
||||
~E_go | ~E_I0_go,
|
||||
{M.I0.RD, M.I0.WCtrl}
|
||||
);
|
||||
ffenr #(6) M_I0_MULT_CNTR_ff (
|
||||
ffenr #(1) M_I0_MULT_CNTR_ff (
|
||||
clk,
|
||||
rst | rstM,
|
||||
{E.I0.MCtrl.HLS[2:1] == 2'b10 & E_go & M.en, M_I0_MULT_CNTR[5:1]},
|
||||
{E.I0.MCtrl.HLS[2:1] == 2'b10 & E_go & M.en},
|
||||
1'b1,
|
||||
M_I0_MULT_CNTR
|
||||
);
|
||||
@ -1062,13 +1129,13 @@ module Datapath (
|
||||
M.en,
|
||||
M.I1.pc
|
||||
);
|
||||
ffenrc #(1 + 1 + 1 + 5 + 32 + 1) M_I1_Exc_ff (
|
||||
ffenrc #(1 + 1 + 1 + 5 + 2 + 32 + 1) M_I1_Exc_ff (
|
||||
clk,
|
||||
rst | rstM,
|
||||
{E.I1.ExcValid, E.I1.ERET, E.I1.REFILL, E.I1.ExcCode, E.I1.BadVAddr, E.I1.Delay},
|
||||
{E.I1.ExcValid, E.I1.ERET, E.I1.REFILL, E.I1.ExcCode, E.I1.CE, E.I1.BadVAddr, E.I1.Delay},
|
||||
M.en,
|
||||
~E_go,
|
||||
{M_I1_PrevExcValid, M.I1.ERET, M_I1_PrevREFILL, M_I1_PrevExcCode, M.I1.BadVAddr, M.I1.Delay}
|
||||
{M_I1_PrevExcValid, M.I1.ERET, M_I1_PrevREFILL, M_I1_PrevExcCode, M.I1.CE, M.I1.BadVAddr, M.I1.Delay}
|
||||
);
|
||||
ffen #(5) M_I1_RT_ff (
|
||||
clk,
|
||||
@ -1088,7 +1155,7 @@ module Datapath (
|
||||
M.en,
|
||||
M.I1.ALUOut
|
||||
);
|
||||
ffenrc #(14) M_I1_MCtrl_ff (
|
||||
ffenrc #(15) M_I1_MCtrl_ff (
|
||||
clk,
|
||||
rst | rstM,
|
||||
E.I1.MCtrl,
|
||||
@ -1107,7 +1174,7 @@ module Datapath (
|
||||
ffenrc #(5 + 1) M_I1_WCtrl_ff (
|
||||
clk,
|
||||
rst | rstM,
|
||||
{E.I1.RD, E.I1.WCtrl},
|
||||
{E.I1.RD, E_I1_NowWCtrl},
|
||||
M.en,
|
||||
~E_go | ~E_I1_go,
|
||||
{M.I1.RD, M.I1.WCtrl}
|
||||
@ -1129,12 +1196,13 @@ module Datapath (
|
||||
dTLBExcValid,
|
||||
{dTLBRefillB, dTLBInvalidB, dTLBModifiedB, dAddressErrorB}
|
||||
);
|
||||
|
||||
assign M_I1_NowExcValid = dTLBRefillB | dTLBInvalidB | dTLBModifiedB | dAddressErrorB | M_I1_Trap;
|
||||
assign M.I1.ExcValid = M_I1_PrevExcValid | M_I1_NowExcValid;
|
||||
assign M.I1.REFILL = M_I1_PrevREFILL | dTLBRefillB;
|
||||
assign M.I1.ExcCode = M_I1_PrevExcValid ? M_I1_PrevExcCode
|
||||
: M_I1_Trap ? `EXCCODE_TR
|
||||
: dAddressErrorB ? M.I1.MCtrl.MWR ? `EXCCODE_ADES : `EXCCODE_ADES
|
||||
: dAddressErrorB ? M.I1.MCtrl.MWR ? `EXCCODE_ADES : `EXCCODE_ADEL
|
||||
: dTLBRefillB ? M.I1.MCtrl.MWR ? `EXCCODE_TLBS : `EXCCODE_TLBL
|
||||
: dTLBInvalidB ? M.I1.MCtrl.MWR ? `EXCCODE_TLBS : `EXCCODE_TLBL
|
||||
: `EXCCODE_MOD;
|
||||
@ -1144,22 +1212,48 @@ module Datapath (
|
||||
|
||||
assign {M_exception, M_exception_REFILL} = {
|
||||
M.I1.ExcValid | M.I0.ExcValid,
|
||||
~M.I0.ExcValid | M.I1.ExcValid & M.A ? {M.I1.Delay, M.I1.ExcCode, M.I1.BadVAddr, M.I1.pc, M.I1.ERET, M.I1.REFILL}
|
||||
: {M.I0.Delay, M.I0.ExcCode, M.I0.BadVAddr, M.I0.pc, M.I0.ERET, M.I0.REFILL}
|
||||
~M.I0.ExcValid | M.I1.ExcValid & M.A ? {M.I1.Delay, M.I1.CE, M.I1.ExcCode, M.I1.BadVAddr, M.I1.pc, M.I1.ERET, M.I1.REFILL}
|
||||
: {M.I0.Delay, M.I0.CE, M.I0.ExcCode, M.I0.BadVAddr, M.I0.pc, M.I0.ERET, M.I0.REFILL}
|
||||
};
|
||||
assign C0_exception = {
|
||||
M_exception.ExcValid & M.en,
|
||||
M_exception.Delay,
|
||||
M_exception.CE,
|
||||
M_exception.ExcCode,
|
||||
M_exception.BadVAddr,
|
||||
M_exception.EPC,
|
||||
M_exception.ERET & M.en
|
||||
};
|
||||
|
||||
// M.I0.ALU
|
||||
mux4 #(32) M_I0_A_mux (
|
||||
{27'b0, M.I0.sa},
|
||||
M.I0.pc,
|
||||
32'd0,
|
||||
M_I0_ForwardS,
|
||||
M.I0.ECtrl.SA,
|
||||
M_I0_A
|
||||
);
|
||||
mux3 #(32) M_I0_B_mux (
|
||||
M_I0_ForwardT,
|
||||
32'd8,
|
||||
M.I0.imm,
|
||||
M.I0.ECtrl.SB,
|
||||
M_I0_B
|
||||
);
|
||||
ALU M_I0_ALU (
|
||||
M_I0_A,
|
||||
M_I0_B,
|
||||
M.I0.ECtrl.OP,
|
||||
M.I0.ALUOut2,
|
||||
M_I0_ALUvalid,
|
||||
M_I0_Overflow
|
||||
);
|
||||
|
||||
// M.I0.MUL
|
||||
ffenr #(97) M_I0_MAS_ff (
|
||||
clk,rst,
|
||||
{M_I0_MULTL, M_I0_MULTH, M_I0_MULTUH, M_I0_MULT_CNTR[0]},
|
||||
{M_I0_MULTL, M_I0_MULTH, M_I0_MULTUH, M_I0_MULT_CNTR},
|
||||
1'b1,
|
||||
{M_I0_MULTLF, M_I0_MULTHF, M_I0_MULTUHF, M_I0_MAS_bvalid}
|
||||
);
|
||||
@ -1172,7 +1266,7 @@ module Datapath (
|
||||
|
||||
myBuffer #(96) M_I0_MULT_buffer (
|
||||
clk, rst,
|
||||
M_I0_MULT_CNTR[0] & M.I0.MCtrl.MAS == 2'b00 | M_I0_MAS_bvalid & |M.I0.MCtrl.MAS,
|
||||
M_I0_MULT_CNTR & M.I0.MCtrl.MAS == 2'b00 | M_I0_MAS_bvalid & |M.I0.MCtrl.MAS,
|
||||
M.I0.MCtrl.MAS == 2'b00 ? {M_I0_MULTL, M_I0_MULTH, M_I0_MULTUH}
|
||||
: {M_I0_MASL, M_I0_MASH, M_I0_MUASH},
|
||||
M.en,
|
||||
@ -1204,7 +1298,7 @@ module Datapath (
|
||||
HI,
|
||||
M_I0_MULTLB,
|
||||
C0_rdata,
|
||||
M.I0.ALUOut,
|
||||
M.I0.ALUOut2,
|
||||
M.I0.MCtrl.RS0,
|
||||
M.I0.RDataW
|
||||
);
|
||||
@ -1220,19 +1314,19 @@ module Datapath (
|
||||
ffen #(32) HI_ff (
|
||||
clk,
|
||||
M_I0_HI,
|
||||
M.I0.MCtrl.HW & M_go,
|
||||
M.I0.MCtrl.HW & M_I0_go & M.en,
|
||||
HI
|
||||
);
|
||||
ffen #(32) LO_ff (
|
||||
clk,
|
||||
M_I0_LO,
|
||||
M.I0.MCtrl.LW & M_go,
|
||||
M.I0.MCtrl.LW & M_I0_go & M.en,
|
||||
LO
|
||||
);
|
||||
|
||||
assign C0_addr = M.I0.MCtrl.C0D;
|
||||
assign C0_sel = M.I0.MCtrl.SEL;
|
||||
assign C0_we = M.I0.MCtrl.C0W & M_I0_go;
|
||||
assign C0_we = M.I0.MCtrl.C0W & M_I0_go & M.en;
|
||||
assign C0_wdata = M_I0_ForwardT;
|
||||
|
||||
// M.I1.MEM
|
||||
@ -1418,4 +1512,5 @@ module Datapath (
|
||||
|
||||
assign W.en = 1'b1;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
126
src/Core/Gadgets/decoder2.sv
Normal file
126
src/Core/Gadgets/decoder2.sv
Normal file
@ -0,0 +1,126 @@
|
||||
`include "defines.svh"
|
||||
|
||||
module decoder2 (
|
||||
input word_t instr,
|
||||
input logic [3:0] CU,
|
||||
input logic kernel,
|
||||
output logic ri,
|
||||
output logic cpu,
|
||||
output logic [1:0] ce
|
||||
);
|
||||
|
||||
logic [3:0] CU2;
|
||||
assign CU2 = {CU[3:1], CU[0] | kernel};
|
||||
always_comb begin
|
||||
ri = 1'b1;
|
||||
ce = {instr[27] & ~instr[26], instr[26]};
|
||||
cpu = ~CU2[ce] & ( instr[31:28] == 4'b0100 // COPx
|
||||
| instr[31:26] == 6'b110001 // LWC1
|
||||
| instr[31:26] == 6'b110010 // LWC2
|
||||
| instr[31:26] == 6'b110101 // LDC1
|
||||
| instr[31:26] == 6'b110110 // LDC2
|
||||
| instr[31:26] == 6'b111001 // SWC1
|
||||
| instr[31:26] == 6'b111010 // SWC2
|
||||
| instr[31:26] == 6'b111101 // SDC1
|
||||
| instr[31:26] == 6'b111110 // SDC2
|
||||
); // TODO: Cache instruction
|
||||
casez (instr)
|
||||
32'b00000000000???????????????000000: ri = 1'b0; // SLL
|
||||
32'b00000000000???????????????000010: ri = 1'b0; // SRL
|
||||
32'b00000000000???????????????000011: ri = 1'b0; // SRA
|
||||
32'b000000???????????????00000000100: ri = 1'b0; // SLLV
|
||||
32'b000000???????????????00000000110: ri = 1'b0; // SRLV
|
||||
32'b000000???????????????00000000111: ri = 1'b0; // SRAV
|
||||
32'b000000?????0000000000?????001000: ri = 1'b0; // JR
|
||||
32'b000000?????00000??????????001001: ri = 1'b0; // JALR
|
||||
32'b000000???????????????00000001010: ri = 1'b0; // MOVZ
|
||||
32'b000000???????????????00000001011: ri = 1'b0; // MOVN
|
||||
32'b000000????????????????????001100: ri = 1'b0; // SYSCALL
|
||||
32'b000000????????????????????001101: ri = 1'b0; // BREAK
|
||||
32'b000000000000000000000?????001111: ri = 1'b0; // SYNC (NOP)
|
||||
32'b0000000000000000?????00000010000: ri = 1'b0; // MFHI
|
||||
32'b000000?????000000000000000010001: ri = 1'b0; // MTHI
|
||||
32'b0000000000000000?????00000010010: ri = 1'b0; // MFLO
|
||||
32'b000000?????000000000000000010011: ri = 1'b0; // MTLO
|
||||
32'b000000??????????0000000000011000: ri = 1'b0; // MULT
|
||||
32'b000000??????????0000000000011001: ri = 1'b0; // MULTU
|
||||
32'b000000??????????0000000000011010: ri = 1'b0; // DIV
|
||||
32'b000000??????????0000000000011011: ri = 1'b0; // DIVU
|
||||
32'b000000???????????????00000100000: ri = 1'b0; // ADD
|
||||
32'b000000???????????????00000100001: ri = 1'b0; // ADDU
|
||||
32'b000000???????????????00000100010: ri = 1'b0; // SUB
|
||||
32'b000000???????????????00000100011: ri = 1'b0; // SUBU
|
||||
32'b000000???????????????00000100100: ri = 1'b0; // AND
|
||||
32'b000000???????????????00000100101: ri = 1'b0; // OR
|
||||
32'b000000???????????????00000100110: ri = 1'b0; // XOR
|
||||
32'b000000???????????????00000100111: ri = 1'b0; // NOR
|
||||
32'b000000???????????????00000101010: ri = 1'b0; // SLT
|
||||
32'b000000???????????????00000101011: ri = 1'b0; // SLTU
|
||||
32'b000000????????????????????110000: ri = 1'b0; // TGE
|
||||
32'b000000????????????????????110001: ri = 1'b0; // TGEU
|
||||
32'b000000????????????????????110010: ri = 1'b0; // TLT
|
||||
32'b000000????????????????????110011: ri = 1'b0; // TLTU
|
||||
32'b000000????????????????????110100: ri = 1'b0; // TEQ
|
||||
32'b000000????????????????????110110: ri = 1'b0; // TNE
|
||||
32'b000001?????00000????????????????: ri = 1'b0; // BLTZ
|
||||
32'b000001?????00001????????????????: ri = 1'b0; // BGEZ
|
||||
32'b000001?????01000????????????????: ri = 1'b0; // TGEI
|
||||
32'b000001?????01001????????????????: ri = 1'b0; // TGEIU
|
||||
32'b000001?????01010????????????????: ri = 1'b0; // TLTI
|
||||
32'b000001?????01011????????????????: ri = 1'b0; // TLTIU
|
||||
32'b000001?????01110????????????????: ri = 1'b0; // TNEI
|
||||
32'b000001?????01100????????????????: ri = 1'b0; // TEQI
|
||||
32'b000001?????10000????????????????: ri = 1'b0; // BLTZAL
|
||||
32'b000001?????10001????????????????: ri = 1'b0; // BGEZAL
|
||||
32'b000010??????????????????????????: ri = 1'b0; // J
|
||||
32'b000011??????????????????????????: ri = 1'b0; // JAL
|
||||
32'b000100??????????????????????????: ri = 1'b0; // BEQ
|
||||
32'b000101??????????????????????????: ri = 1'b0; // BNE
|
||||
32'b000110?????00000????????????????: ri = 1'b0; // BLEZ
|
||||
32'b000111?????00000????????????????: ri = 1'b0; // BGTZ
|
||||
32'b001000??????????????????????????: ri = 1'b0; // ADDI
|
||||
32'b001001??????????????????????????: ri = 1'b0; // ADDIU
|
||||
32'b001010??????????????????????????: ri = 1'b0; // SLTI
|
||||
32'b001011??????????????????????????: ri = 1'b0; // SLTIU
|
||||
32'b001100??????????????????????????: ri = 1'b0; // ANDI
|
||||
32'b001101??????????????????????????: ri = 1'b0; // ORI
|
||||
32'b001110??????????????????????????: ri = 1'b0; // XORI
|
||||
32'b00111100000?????????????????????: ri = 1'b0; // LUI
|
||||
32'b01000000000??????????00000000???: ri = 1'b0; // MFC0
|
||||
32'b01000000100??????????00000000???: ri = 1'b0; // MTC0
|
||||
32'b01000010000000000000000000000001: ri = 1'b0; // TLBR
|
||||
32'b01000010000000000000000000000010: ri = 1'b0; // TLBWI
|
||||
32'b01000010000000000000000000000110: ri = 1'b0; // TLBWR
|
||||
32'b01000010000000000000000000001000: ri = 1'b0; // TLBP
|
||||
32'b01000010000000000000000000011000: ri = 1'b0; // ERET
|
||||
32'b011100??????????0000000000000000: ri = 1'b0; // MADD
|
||||
32'b011100??????????0000000000000001: ri = 1'b0; // MADDU
|
||||
32'b011100??????????0000000000000100: ri = 1'b0; // MSUB
|
||||
32'b011100??????????0000000000000101: ri = 1'b0; // MSUBU
|
||||
32'b011100???????????????00000000010: ri = 1'b0; // MUL
|
||||
// 32'b01111100000??????????00000111011: begin cpu = 1'b1; ce = 2'b0; end // RDHWR (CpU)
|
||||
32'b100000??????????????????????????: ri = 1'b0; // LB
|
||||
32'b100001??????????????????????????: ri = 1'b0; // LH
|
||||
32'b100010??????????????????????????: ri = 1'b0; // LWL
|
||||
32'b100011??????????????????????????: ri = 1'b0; // LW
|
||||
32'b100100??????????????????????????: ri = 1'b0; // LBU
|
||||
32'b100101??????????????????????????: ri = 1'b0; // LHU
|
||||
32'b100110??????????????????????????: ri = 1'b0; // LWR
|
||||
32'b101000??????????????????????????: ri = 1'b0; // SB
|
||||
32'b101001??????????????????????????: ri = 1'b0; // SH
|
||||
32'b101010??????????????????????????: ri = 1'b0; // SWL
|
||||
32'b101011??????????????????????????: ri = 1'b0; // SW
|
||||
32'b101110??????????????????????????: ri = 1'b0; // SWR
|
||||
32'b101111?????00000????????????????: ri = 1'b0; // I-Cache Index Invalid
|
||||
32'b101111?????01000????????????????: ri = 1'b0; // I-Cache Index Store Tag
|
||||
32'b101111?????10000????????????????: ri = 1'b0; // I-Cache Hit Invalid
|
||||
32'b101111?????00001????????????????: ri = 1'b0; // D-Cache Index Writeback Invalid
|
||||
32'b101111?????01001????????????????: ri = 1'b0; // D-Cache Index Store Tag
|
||||
32'b101111?????10001????????????????: ri = 1'b0; // D-Cache Hit Invalid
|
||||
32'b101111?????10101????????????????: ri = 1'b0; // D-Cache Hit Writeback Invalid
|
||||
// 32'b110000??????????????????????????: begin cpu = 1'b1; ce = 2'b0; end // LL (CpU)
|
||||
32'b110011??????????????????????????: ri = 1'b0; // PREF (NOP)
|
||||
// 32'b111000??????????????????????????: begin cpu = 1'b1; ce = 2'b0; end // SC (CpU)
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
@ -1,105 +0,0 @@
|
||||
`include "defines.svh"
|
||||
|
||||
module instr_valid (
|
||||
input word_t instr,
|
||||
output logic valid
|
||||
);
|
||||
|
||||
always_comb
|
||||
casez (instr)
|
||||
32'b000000000000000000000?????001111: valid = 1'b1; // SYNC (NOP)
|
||||
32'b00000000000???????????????000000: valid = 1'b1; // SLL
|
||||
32'b00000000000???????????????000010: valid = 1'b1; // SRL
|
||||
32'b00000000000???????????????000011: valid = 1'b1; // SRA
|
||||
32'b000000???????????????00000000100: valid = 1'b1; // SLLV
|
||||
32'b000000???????????????00000000110: valid = 1'b1; // SRLV
|
||||
32'b000000???????????????00000000111: valid = 1'b1; // SRAV
|
||||
32'b000000???????????????00000001010: valid = 1'b1; // MOVZ
|
||||
32'b000000???????????????00000001011: valid = 1'b1; // MOVN
|
||||
32'b000000?????000000000000000001000: valid = 1'b1; // JR
|
||||
32'b000000?????00000?????00000001001: valid = 1'b1; // JALR
|
||||
32'b000000????????????????????001100: valid = 1'b1; // SYSCALL
|
||||
32'b000000????????????????????001101: valid = 1'b1; // BREAK
|
||||
32'b0000000000000000?????00000010000: valid = 1'b1; // MFHI
|
||||
32'b000000?????000000000000000010001: valid = 1'b1; // MTHI
|
||||
32'b0000000000000000?????00000010010: valid = 1'b1; // MFLO
|
||||
32'b000000?????000000000000000010011: valid = 1'b1; // MTLO
|
||||
32'b000000??????????0000000000011000: valid = 1'b1; // MULT
|
||||
32'b000000??????????0000000000011001: valid = 1'b1; // MULTU
|
||||
32'b000000??????????0000000000011010: valid = 1'b1; // DIV
|
||||
32'b000000??????????0000000000011011: valid = 1'b1; // DIVU
|
||||
32'b000000???????????????00000100000: valid = 1'b1; // ADD
|
||||
32'b000000???????????????00000100001: valid = 1'b1; // ADDU
|
||||
32'b000000???????????????00000100010: valid = 1'b1; // SUB
|
||||
32'b000000???????????????00000100011: valid = 1'b1; // SUBU
|
||||
32'b000000???????????????00000100100: valid = 1'b1; // AND
|
||||
32'b000000???????????????00000100101: valid = 1'b1; // OR
|
||||
32'b000000???????????????00000100110: valid = 1'b1; // XOR
|
||||
32'b000000???????????????00000100111: valid = 1'b1; // NOR
|
||||
32'b000000???????????????00000101010: valid = 1'b1; // SLT
|
||||
32'b000000???????????????00000101011: valid = 1'b1; // SLTU
|
||||
32'b000000????????????????????110000: valid = 1'b1; // TGE
|
||||
32'b000000????????????????????110001: valid = 1'b1; // TGEU
|
||||
32'b000000????????????????????110010: valid = 1'b1; // TLT
|
||||
32'b000000????????????????????110011: valid = 1'b1; // TLTU
|
||||
32'b000000????????????????????110100: valid = 1'b1; // TEQ
|
||||
32'b000000????????????????????110110: valid = 1'b1; // TNE
|
||||
32'b000001?????00000????????????????: valid = 1'b1; // BLTZ
|
||||
32'b000001?????00001????????????????: valid = 1'b1; // BGEZ
|
||||
32'b000001?????01000????????????????: valid = 1'b1; // TGEI
|
||||
32'b000001?????01001????????????????: valid = 1'b1; // TGEIU
|
||||
32'b000001?????01010????????????????: valid = 1'b1; // TLTI
|
||||
32'b000001?????01011????????????????: valid = 1'b1; // TLTIU
|
||||
32'b000001?????01110????????????????: valid = 1'b1; // TNEI
|
||||
32'b000001?????01100????????????????: valid = 1'b1; // TEQI
|
||||
32'b000001?????10000????????????????: valid = 1'b1; // BLTZAL
|
||||
32'b000001?????10001????????????????: valid = 1'b1; // BGEZAL
|
||||
32'b000010??????????????????????????: valid = 1'b1; // J
|
||||
32'b000011??????????????????????????: valid = 1'b1; // JAL
|
||||
32'b000100??????????????????????????: valid = 1'b1; // BEQ
|
||||
32'b000101??????????????????????????: valid = 1'b1; // BNE
|
||||
32'b000110?????00000????????????????: valid = 1'b1; // BLEZ
|
||||
32'b000111?????00000????????????????: valid = 1'b1; // BGTZ
|
||||
32'b001000??????????????????????????: valid = 1'b1; // ADDI
|
||||
32'b001001??????????????????????????: valid = 1'b1; // ADDIU
|
||||
32'b001010??????????????????????????: valid = 1'b1; // SLTI
|
||||
32'b001011??????????????????????????: valid = 1'b1; // SLTIU
|
||||
32'b001100??????????????????????????: valid = 1'b1; // ANDI
|
||||
32'b001101??????????????????????????: valid = 1'b1; // ORI
|
||||
32'b001110??????????????????????????: valid = 1'b1; // XORI
|
||||
32'b00111100000?????????????????????: valid = 1'b1; // LUI
|
||||
32'b01000000000??????????00000000???: valid = 1'b1; // MFC0
|
||||
32'b01000000100??????????00000000???: valid = 1'b1; // MTC0
|
||||
32'b01000010000000000000000000000001: valid = 1'b1; // TLBR
|
||||
32'b01000010000000000000000000000010: valid = 1'b1; // TLBWI
|
||||
32'b01000010000000000000000000000110: valid = 1'b1; // TLBWR
|
||||
32'b01000010000000000000000000001000: valid = 1'b1; // TLBP
|
||||
32'b01000010000000000000000000011000: valid = 1'b1; // ERET
|
||||
32'b011100??????????0000000000000000: valid = 1'b1; // MADD
|
||||
32'b011100??????????0000000000000001: valid = 1'b1; // MADDU
|
||||
32'b011100??????????0000000000000100: valid = 1'b1; // MSUB
|
||||
32'b011100??????????0000000000000101: valid = 1'b1; // MSUBU
|
||||
32'b011100???????????????00000000010: valid = 1'b1; // MUL
|
||||
32'b100000??????????????????????????: valid = 1'b1; // LB
|
||||
32'b100001??????????????????????????: valid = 1'b1; // LH
|
||||
32'b100010??????????????????????????: valid = 1'b1; // LWL
|
||||
32'b100011??????????????????????????: valid = 1'b1; // LW
|
||||
32'b100100??????????????????????????: valid = 1'b1; // LBU
|
||||
32'b100101??????????????????????????: valid = 1'b1; // LHU
|
||||
32'b100110??????????????????????????: valid = 1'b1; // LWR
|
||||
32'b101000??????????????????????????: valid = 1'b1; // SB
|
||||
32'b101001??????????????????????????: valid = 1'b1; // SH
|
||||
32'b101010??????????????????????????: valid = 1'b1; // SWL
|
||||
32'b101011??????????????????????????: valid = 1'b1; // SW
|
||||
32'b101110??????????????????????????: valid = 1'b1; // SWR
|
||||
32'b101111?????00000????????????????: valid = 1'b1; // I-Cache Index Invalid
|
||||
32'b101111?????01000????????????????: valid = 1'b1; // I-Cache Index Store Tag
|
||||
32'b101111?????10000????????????????: valid = 1'b1; // I-Cache Hit Invalid
|
||||
32'b101111?????00001????????????????: valid = 1'b1; // D-Cache Index Writeback Invalid
|
||||
32'b101111?????01001????????????????: valid = 1'b1; // D-Cache Index Store Tag
|
||||
32'b101111?????10001????????????????: valid = 1'b1; // D-Cache Hit Invalid
|
||||
32'b101111?????10101????????????????: valid = 1'b1; // D-Cache Hit Writeback Invalid
|
||||
32'b110011??????????????????????????: valid = 1'b1; // PREF (NOP)
|
||||
default: valid = 1'b0;
|
||||
endcase
|
||||
endmodule
|
||||
@ -33,7 +33,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
@ -64,7 +64,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
@ -84,10 +84,12 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_PORT"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">7</spirit:configurableElementValue>
|
||||
@ -250,12 +252,12 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
@ -304,6 +306,82 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
<xilinx:boundaryDescriptionInfo>
|
||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{
|
||||
"schema": "xilinx.com:schema:json_boundary:1.0",
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clka": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"wea": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"addra": [ { "direction": "in", "size_left": "6", "size_right": "0", "driver_value": "0" } ],
|
||||
"dina": [ { "direction": "in", "size_left": "127", "size_right": "0", "driver_value": "0" } ],
|
||||
"douta": [ { "direction": "out", "size_left": "127", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"CLK.ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"RST.ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"BRAM_PORTA": {
|
||||
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "addra" } ],
|
||||
"CLK": [ { "physical_name": "clka" } ],
|
||||
"DIN": [ { "physical_name": "dina" } ],
|
||||
"DOUT": [ { "physical_name": "douta" } ],
|
||||
"WE": [ { "physical_name": "wea" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_1": {
|
||||
"address_blocks": {
|
||||
"Mem0": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"usage": "memory",
|
||||
"access": "read-write",
|
||||
"parameters": {
|
||||
"OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
|
||||
"OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
|
||||
@ -33,7 +33,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
@ -64,7 +64,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
@ -84,10 +84,12 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_PORT"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">7</spirit:configurableElementValue>
|
||||
@ -250,12 +252,12 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
@ -304,6 +306,82 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
<xilinx:boundaryDescriptionInfo>
|
||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{
|
||||
"schema": "xilinx.com:schema:json_boundary:1.0",
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clka": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"wea": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"addra": [ { "direction": "in", "size_left": "6", "size_right": "0", "driver_value": "0" } ],
|
||||
"dina": [ { "direction": "in", "size_left": "22", "size_right": "0", "driver_value": "0" } ],
|
||||
"douta": [ { "direction": "out", "size_left": "22", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"CLK.ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"RST.ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"BRAM_PORTA": {
|
||||
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "addra" } ],
|
||||
"CLK": [ { "physical_name": "clka" } ],
|
||||
"DIN": [ { "physical_name": "dina" } ],
|
||||
"DOUT": [ { "physical_name": "douta" } ],
|
||||
"WE": [ { "physical_name": "wea" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_1": {
|
||||
"address_blocks": {
|
||||
"Mem0": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"usage": "memory",
|
||||
"access": "read-write",
|
||||
"parameters": {
|
||||
"OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
|
||||
"OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
|
||||
@ -33,7 +33,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
@ -64,7 +64,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
@ -84,10 +84,12 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_PORT"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">6</spirit:configurableElementValue>
|
||||
@ -250,12 +252,12 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
@ -304,6 +306,82 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
<xilinx:boundaryDescriptionInfo>
|
||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{
|
||||
"schema": "xilinx.com:schema:json_boundary:1.0",
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clka": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"wea": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"addra": [ { "direction": "in", "size_left": "5", "size_right": "0", "driver_value": "0" } ],
|
||||
"dina": [ { "direction": "in", "size_left": "255", "size_right": "0", "driver_value": "0" } ],
|
||||
"douta": [ { "direction": "out", "size_left": "255", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"CLK.ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"RST.ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"BRAM_PORTA": {
|
||||
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "addra" } ],
|
||||
"CLK": [ { "physical_name": "clka" } ],
|
||||
"DIN": [ { "physical_name": "dina" } ],
|
||||
"DOUT": [ { "physical_name": "douta" } ],
|
||||
"WE": [ { "physical_name": "wea" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_1": {
|
||||
"address_blocks": {
|
||||
"Mem0": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"usage": "memory",
|
||||
"access": "read-write",
|
||||
"parameters": {
|
||||
"OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
|
||||
"OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
|
||||
@ -33,7 +33,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
@ -64,7 +64,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
@ -84,10 +84,12 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_PORT"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">6</spirit:configurableElementValue>
|
||||
@ -250,12 +252,12 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
@ -304,6 +306,82 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
<xilinx:boundaryDescriptionInfo>
|
||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{
|
||||
"schema": "xilinx.com:schema:json_boundary:1.0",
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clka": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"wea": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"addra": [ { "direction": "in", "size_left": "5", "size_right": "0", "driver_value": "0" } ],
|
||||
"dina": [ { "direction": "in", "size_left": "21", "size_right": "0", "driver_value": "0" } ],
|
||||
"douta": [ { "direction": "out", "size_left": "21", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"CLK.ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"RST.ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"BRAM_PORTA": {
|
||||
"vlnv": "xilinx.com:interface:bram:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "addra" } ],
|
||||
"CLK": [ { "physical_name": "clka" } ],
|
||||
"DIN": [ { "physical_name": "dina" } ],
|
||||
"DOUT": [ { "physical_name": "douta" } ],
|
||||
"WE": [ { "physical_name": "wea" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_1": {
|
||||
"address_blocks": {
|
||||
"Mem0": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"usage": "memory",
|
||||
"access": "read-write",
|
||||
"parameters": {
|
||||
"OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
|
||||
"OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
|
||||
@ -9,10 +9,12 @@
|
||||
<spirit:instanceName>div_signed</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="div_gen" spirit:version="5.1"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.ASSOCIATED_PORT"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">1000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN_INTF.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
@ -22,7 +24,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@ -35,7 +37,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@ -48,7 +50,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@ -61,7 +63,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVIDEND_TUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVISOR_TLAST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVISOR_TUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">36</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">14</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TDATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DIVIDEND_TDATA_WIDTH">32</spirit:configurableElementValue>
|
||||
@ -96,8 +98,8 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_tuser_width">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_width">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.fractional_width">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.latency">36</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.latency_configuration">Automatic</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.latency">14</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.latency_configuration">Manual</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.operand_sign">Signed</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.remainder_type">Remainder</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
|
||||
@ -114,12 +116,12 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">19</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
@ -154,6 +156,132 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.latency_configuration" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.remainder_type" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
<xilinx:boundaryDescriptionInfo>
|
||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{
|
||||
"schema": "xilinx.com:schema:json_boundary:1.0",
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"s_axis_divisor_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_divisor_tdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axis_dividend_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_dividend_tdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axis_dout_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"m_axis_dout_tdata": [ { "direction": "out", "size_left": "63", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"M_AXIS_DOUT": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_dout_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_dout_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"aclk_intf": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS_DIVIDEND:S_AXIS_DIVISOR:M_AXIS_DOUT", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "1000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"aresetn_intf": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"aclken_intf": {
|
||||
"vlnv": "xilinx.com:signal:clockenable:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS_DIVISOR": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_divisor_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_divisor_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS_DIVIDEND": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_dividend_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_dividend_tvalid" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
|
||||
@ -9,10 +9,12 @@
|
||||
<spirit:instanceName>div_unsigned</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="div_gen" spirit:version="5.1"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.ASSOCIATED_PORT"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">1000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN_INTF.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
@ -22,7 +24,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@ -35,7 +37,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@ -48,7 +50,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@ -61,7 +63,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVIDEND_TUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVISOR_TLAST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVISOR_TUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">34</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">14</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TDATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DIVIDEND_TDATA_WIDTH">32</spirit:configurableElementValue>
|
||||
@ -96,8 +98,8 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_tuser_width">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_width">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.fractional_width">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.latency">34</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.latency_configuration">Automatic</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.latency">14</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.latency_configuration">Manual</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.operand_sign">Unsigned</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.remainder_type">Remainder</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
|
||||
@ -114,12 +116,12 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">19</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
@ -151,6 +153,132 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.latency_configuration" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.operand_sign" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
<xilinx:boundaryDescriptionInfo>
|
||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{
|
||||
"schema": "xilinx.com:schema:json_boundary:1.0",
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"s_axis_divisor_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_divisor_tdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axis_dividend_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_dividend_tdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"m_axis_dout_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"m_axis_dout_tdata": [ { "direction": "out", "size_left": "63", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"M_AXIS_DOUT": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_dout_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_dout_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"aclk_intf": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS_DIVIDEND:S_AXIS_DIVISOR:M_AXIS_DOUT", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "1000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"aresetn_intf": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"aclken_intf": {
|
||||
"vlnv": "xilinx.com:signal:clockenable:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS_DIVISOR": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_divisor_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_divisor_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS_DIVIDEND": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_dividend_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_dividend_tvalid" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
|
||||
@ -11,10 +11,12 @@
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.A_INTF.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.B_INTF.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_INTF.ASSOCIATED_PORT"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_INTF.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_INTF.FREQ_HZ">10000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_INTF.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_INTF.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_INTF.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_INTF.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.P_INTF.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SCLR_INTF.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_A_TYPE">0</spirit:configurableElementValue>
|
||||
@ -27,7 +29,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SCLR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ZERO_DETECT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MODEL_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MULT_TYPE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZE_GOAL">1</spirit:configurableElementValue>
|
||||
@ -47,7 +49,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OptGoal">Speed</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OutputWidthHigh">63</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OutputWidthLow">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PipeStages">6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PipeStages">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PortAType">Signed</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PortAWidth">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PortBType">Signed</spirit:configurableElementValue>
|
||||
@ -72,12 +74,12 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">18</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
@ -89,6 +91,90 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PortAWidth" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PortBWidth" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
<xilinx:boundaryDescriptionInfo>
|
||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{
|
||||
"schema": "xilinx.com:schema:json_boundary:1.0",
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"CLK": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"A": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"B": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"P": [ { "direction": "out", "size_left": "63", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"a_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "A" } ]
|
||||
}
|
||||
},
|
||||
"clk_intf": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "p_intf:b_intf:a_intf", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "sclr", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "ce", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "CLK" } ]
|
||||
}
|
||||
},
|
||||
"sclr_intf": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"ce_intf": {
|
||||
"vlnv": "xilinx.com:signal:clockenable:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
|
||||
}
|
||||
},
|
||||
"b_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "B" } ]
|
||||
}
|
||||
},
|
||||
"p_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "P" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
|
||||
@ -11,10 +11,12 @@
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.A_INTF.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.B_INTF.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_INTF.ASSOCIATED_PORT"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_INTF.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_INTF.FREQ_HZ">10000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_INTF.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_INTF.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_INTF.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_INTF.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.P_INTF.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SCLR_INTF.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_A_TYPE">1</spirit:configurableElementValue>
|
||||
@ -27,7 +29,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SCLR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ZERO_DETECT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MODEL_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MULT_TYPE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZE_GOAL">1</spirit:configurableElementValue>
|
||||
@ -47,7 +49,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OptGoal">Speed</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OutputWidthHigh">63</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OutputWidthLow">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PipeStages">6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PipeStages">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PortAType">Unsigned</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PortAWidth">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PortBType">Unsigned</spirit:configurableElementValue>
|
||||
@ -72,12 +74,12 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">18</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
@ -91,6 +93,90 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PortBType" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PortBWidth" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
<xilinx:boundaryDescriptionInfo>
|
||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{
|
||||
"schema": "xilinx.com:schema:json_boundary:1.0",
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"CLK": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"A": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"B": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"P": [ { "direction": "out", "size_left": "63", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"a_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "A" } ]
|
||||
}
|
||||
},
|
||||
"clk_intf": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "p_intf:b_intf:a_intf", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "sclr", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "ce", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "CLK" } ]
|
||||
}
|
||||
},
|
||||
"sclr_intf": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"ce_intf": {
|
||||
"vlnv": "xilinx.com:signal:clockenable:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
|
||||
}
|
||||
},
|
||||
"b_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "B" } ]
|
||||
}
|
||||
},
|
||||
"p_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "P" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
|
||||
@ -419,10 +419,10 @@ module MMU (
|
||||
if (rdata_axi.addr_ok) begin
|
||||
if (~rdata_axi.rvalid) drNextState = DR_WD1;
|
||||
else begin
|
||||
data.data_ok = 1;
|
||||
if (dCached2) drNextState = DR_WD2;
|
||||
else begin
|
||||
dEn = 1;
|
||||
data.data_ok = 1;
|
||||
drNextState = DR_IDLE;
|
||||
end
|
||||
end
|
||||
|
||||
117
src/MMU/TLB.sv
117
src/MMU/TLB.sv
@ -1,6 +1,8 @@
|
||||
`include "defines.svh"
|
||||
`include "TLB.svh"
|
||||
|
||||
`ifdef TLB_ENABLE
|
||||
|
||||
module TLB (
|
||||
input clk,
|
||||
input rst,
|
||||
@ -200,3 +202,118 @@ module TLB (
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`else
|
||||
|
||||
module TLB (
|
||||
input clk,
|
||||
input rst,
|
||||
|
||||
// CP0
|
||||
input logic [2:0] K0,
|
||||
input logic tlbw, // TLBWI + TLBWR
|
||||
input logic tlbp, // TLBP
|
||||
input logic [2:0] c0_Index, // TLBWR + TLBWI + TLBR
|
||||
|
||||
input EntryHi_t c0_EntryHi, // TLBWI + F/M(ASID)
|
||||
// input PageMask_t c0_PageMask, // TLBWI
|
||||
input EntryLo_t c0_EntryLo1, // TLBWI
|
||||
input EntryLo_t c0_EntryLo0, // TLBWI
|
||||
|
||||
output EntryHi_t EntryHi, // TLBR
|
||||
// output PageMask_t PageMask, // TLBR
|
||||
output EntryLo_t EntryLo1, // TLBR
|
||||
output EntryLo_t EntryLo0, // TLBR
|
||||
output Index_t Index, // TLBP
|
||||
|
||||
// MMU
|
||||
input word_t iVAddr,
|
||||
output word_t iPAddr,
|
||||
output logic iHit, // TLB Refill
|
||||
output logic iCached,
|
||||
output logic iValid, // TLB Invalid
|
||||
output logic iUser, // Privilege
|
||||
|
||||
input word_t dVAddr,
|
||||
output word_t dPAddr,
|
||||
output logic dHit, // TLB Refill
|
||||
output logic dCached,
|
||||
output logic dDirty, // TLB Modified
|
||||
output logic dValid, // TLB Invalid
|
||||
output logic dUser // Privilege
|
||||
);
|
||||
|
||||
word_t fVAddr, fVAddr1;
|
||||
word_t mVAddr, mVAddr1;
|
||||
|
||||
assign fVAddr = iVAddr;
|
||||
// Output
|
||||
ffenr #(32) inst_ff(
|
||||
clk, rst,
|
||||
fVAddr,
|
||||
1'b1,
|
||||
fVAddr1
|
||||
);
|
||||
always_comb begin
|
||||
if (fVAddr1 > 32'hBFFF_FFFF || fVAddr1 <= 32'h7FFF_FFFF) begin
|
||||
// kseg2 + kseg3 + kuseg -> tlb
|
||||
iPAddr = fVAddr1 & 32'h1FFF_FFFF;
|
||||
iHit = 1'b1;
|
||||
iCached = K0[0];
|
||||
iValid = 1'b1;
|
||||
iUser = 1'b1;
|
||||
end else if (fVAddr1 > 32'h9FFF_FFFF) begin
|
||||
// kseg1 uncached
|
||||
iPAddr = fVAddr1 & 32'h1FFF_FFFF;
|
||||
iHit = 1'b1;
|
||||
iCached = 1'b0;
|
||||
iValid = 1'b1;
|
||||
iUser = 1'b0;
|
||||
end else begin
|
||||
// kseg0 -> CP0.K0
|
||||
iPAddr = fVAddr1 & 32'h1FFF_FFFF;
|
||||
iHit = 1'b1;
|
||||
iCached = K0[0];
|
||||
iValid = 1'b1;
|
||||
iUser = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
assign mVAddr = dVAddr;
|
||||
ffenr #(32) data_ff (
|
||||
clk, rst,
|
||||
mVAddr,
|
||||
1'b1,
|
||||
mVAddr1
|
||||
);
|
||||
always_comb begin
|
||||
if (mVAddr1 > 32'hBFFF_FFFF || mVAddr1 <= 32'h7FFF_FFFF) begin
|
||||
// kseg2 + kseg3 + kuseg -> tlb
|
||||
dPAddr = mVAddr1 & 32'h1FFF_FFFF;
|
||||
dHit = 1'b1;
|
||||
dCached = K0[0];
|
||||
dDirty = 1'b1;
|
||||
dValid = 1'b1;
|
||||
dUser = 1'b1;
|
||||
end else if (mVAddr1 > 32'h9FFF_FFFF) begin
|
||||
// kseg1 uncached
|
||||
dPAddr = mVAddr1 & 32'h1FFF_FFFF;
|
||||
dHit = 1'b1;
|
||||
dCached = 1'b0;
|
||||
dDirty = 1'b1;
|
||||
dValid = 1'b1;
|
||||
dUser = 1'b0;
|
||||
end else begin
|
||||
// kseg0 -> CP0.K0
|
||||
dPAddr = mVAddr1 & 32'h1FFF_FFFF;
|
||||
dHit = 1'b1;
|
||||
dCached = K0[0];
|
||||
dDirty = 1'b1;
|
||||
dValid = 1'b1;
|
||||
dUser = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`endif
|
||||
@ -42,6 +42,7 @@ typedef enum bit [4:0] {
|
||||
typedef struct packed {
|
||||
logic ExcValid;
|
||||
logic Delay;
|
||||
logic [1:0] CE;
|
||||
logic [4:0] ExcCode;
|
||||
word_t BadVAddr;
|
||||
word_t EPC;
|
||||
@ -60,7 +61,19 @@ typedef struct packed {
|
||||
} CP0_REGS_CONFIG_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic [8:0] zero1;
|
||||
logic BD;
|
||||
logic TI;
|
||||
logic [1:0] CE;
|
||||
logic [11:0] zero1;
|
||||
logic [7:0] IP;
|
||||
logic zero2;
|
||||
logic [4:0] ExcCode;
|
||||
logic [1:0] zero3;
|
||||
} CP0_REGS_CAUSE_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic [3:0] CU;
|
||||
logic [4:0] zero1;
|
||||
logic Bev;
|
||||
logic [5:0] zero2;
|
||||
logic [7:0] IM;
|
||||
@ -71,16 +84,6 @@ typedef struct packed {
|
||||
logic IE;
|
||||
} CP0_REGS_STATUS_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic BD;
|
||||
logic TI;
|
||||
logic [13:0] zero1;
|
||||
logic [7:0] IP;
|
||||
logic zero2;
|
||||
logic [4:0] ExcCode;
|
||||
logic [1:0] zero3;
|
||||
} CP0_REGS_CAUSE_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic one;
|
||||
logic zero1;
|
||||
@ -118,7 +121,7 @@ typedef struct packed {
|
||||
word_t BadVAddr;
|
||||
// HWREna
|
||||
Wired_t Wired;
|
||||
// Context,
|
||||
Context_t Context;
|
||||
// word_t PageMask;
|
||||
EntryLo_t EntryLo1;
|
||||
EntryLo_t EntryLo0;
|
||||
|
||||
@ -12,6 +12,11 @@ typedef struct packed {
|
||||
// logic [11:0] Mask;
|
||||
// logic [12:0] zero2;
|
||||
// } PageMask_t;
|
||||
typedef struct packed {
|
||||
logic [ 8:0] PTEBase;
|
||||
logic [18:0] BadVPN2;
|
||||
logic [ 3:0] zero;
|
||||
} Context_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic [ 5:0] zero;
|
||||
@ -22,6 +27,7 @@ typedef struct packed {
|
||||
logic G;
|
||||
} EntryLo_t;
|
||||
|
||||
|
||||
typedef struct packed {
|
||||
logic P;
|
||||
logic [27:0] zero;
|
||||
|
||||
@ -5,11 +5,13 @@
|
||||
`define Off_TRef 9'h000
|
||||
`define Off_GExc 9'h180
|
||||
|
||||
`define TLB_ENABLE
|
||||
|
||||
// prio: int
|
||||
// fetch_addr
|
||||
// fetch_tlb_refill
|
||||
// fetch_tlb_invalid
|
||||
// ri
|
||||
// ri, cpu
|
||||
// syscall, break, overflow, trap
|
||||
// mem_addr
|
||||
// mem_tlb_refill
|
||||
@ -39,9 +41,9 @@ typedef struct packed {
|
||||
logic f_xor;
|
||||
logic f_slt;
|
||||
logic f_sltu;
|
||||
logic f_mova;
|
||||
logic f_mov;
|
||||
logic alt;
|
||||
} aluctrl_t;
|
||||
} ALUCtrl_t;
|
||||
|
||||
typedef enum logic [1:0] {
|
||||
SA = 2'b00,
|
||||
@ -104,7 +106,7 @@ typedef enum logic [1:0] {
|
||||
typedef struct packed {
|
||||
SA_t SA;
|
||||
SB_t SB;
|
||||
aluctrl_t OP;
|
||||
ALUCtrl_t OP;
|
||||
} ECtrl_t;
|
||||
|
||||
typedef struct packed {
|
||||
@ -141,8 +143,6 @@ typedef struct packed {
|
||||
} WCtrl_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic PRV;
|
||||
|
||||
logic SYSCALL;
|
||||
logic BREAK;
|
||||
logic ERET;
|
||||
@ -162,6 +162,8 @@ typedef struct packed {
|
||||
logic DT;
|
||||
logic ES;
|
||||
logic ET;
|
||||
logic ES2;
|
||||
logic ET2;
|
||||
|
||||
ECtrl_t ECtrl;
|
||||
|
||||
@ -193,6 +195,7 @@ typedef struct packed {
|
||||
logic IA_ERET;
|
||||
logic IA_REFILL;
|
||||
logic [4:0] IA_ExcCode;
|
||||
logic [1:0] IA_CE;
|
||||
logic IA_Delay;
|
||||
word_t IA_S;
|
||||
word_t IA_T;
|
||||
@ -205,6 +208,7 @@ typedef struct packed {
|
||||
logic IB_ERET;
|
||||
logic IB_REFILL;
|
||||
logic [4:0] IB_ExcCode;
|
||||
logic [1:0] IB_CE;
|
||||
logic IB_Delay;
|
||||
word_t IB_S;
|
||||
word_t IB_T;
|
||||
@ -218,6 +222,7 @@ typedef struct packed {
|
||||
logic ERET;
|
||||
logic REFILL;
|
||||
logic [4:0] ExcCode;
|
||||
logic [1:0] CE;
|
||||
logic Delay;
|
||||
logic OFA;
|
||||
|
||||
@ -232,6 +237,7 @@ typedef struct packed {
|
||||
ECtrl_t ECtrl;
|
||||
|
||||
MCtrl0_t MCtrl;
|
||||
logic MCtrl_ALU1; // critical
|
||||
|
||||
logic [4:0] RD;
|
||||
WCtrl_t WCtrl;
|
||||
@ -244,6 +250,7 @@ typedef struct packed {
|
||||
logic ERET;
|
||||
logic REFILL;
|
||||
logic [4:0] ExcCode;
|
||||
logic [1:0] CE;
|
||||
logic Delay;
|
||||
logic OFA;
|
||||
|
||||
@ -276,6 +283,7 @@ typedef struct packed {
|
||||
logic ERET;
|
||||
logic REFILL;
|
||||
logic [4:0] ExcCode;
|
||||
logic [1:0] CE;
|
||||
logic Delay;
|
||||
logic OFA;
|
||||
|
||||
@ -291,6 +299,7 @@ typedef struct packed {
|
||||
word_t ALUOut;
|
||||
|
||||
MCtrl0_t MCtrl;
|
||||
logic MCtrl_ALU1; // critical
|
||||
|
||||
logic [4:0] RD;
|
||||
WCtrl_t WCtrl;
|
||||
@ -303,6 +312,7 @@ typedef struct packed {
|
||||
logic ERET;
|
||||
logic REFILL;
|
||||
logic [4:0] ExcCode;
|
||||
logic [1:0] CE;
|
||||
word_t BadVAddr;
|
||||
logic Delay;
|
||||
logic OFA;
|
||||
@ -337,6 +347,7 @@ typedef struct packed {
|
||||
logic ERET;
|
||||
logic REFILL;
|
||||
logic [4:0] ExcCode;
|
||||
logic [1:0] CE;
|
||||
word_t BadVAddr;
|
||||
logic Delay;
|
||||
|
||||
@ -347,7 +358,14 @@ typedef struct packed {
|
||||
|
||||
word_t ALUOut;
|
||||
|
||||
word_t imm;
|
||||
logic [4:0] sa;
|
||||
|
||||
ECtrl_t ECtrl;
|
||||
word_t ALUOut2;
|
||||
|
||||
MCtrl0_t MCtrl;
|
||||
logic MCtrl_ALU1; // critical
|
||||
word_t RDataW;
|
||||
|
||||
logic [4:0] RD;
|
||||
@ -361,6 +379,7 @@ typedef struct packed {
|
||||
logic ERET;
|
||||
logic REFILL;
|
||||
logic [4:0] ExcCode;
|
||||
logic [1:0] CE;
|
||||
word_t BadVAddr;
|
||||
logic Delay;
|
||||
|
||||
|
||||
@ -89,10 +89,12 @@ module mycpu_top (
|
||||
word_t C0_wdata;
|
||||
EXCEPTION_t C0_exception;
|
||||
word_t C0_ERETPC;
|
||||
logic C0_EXL;
|
||||
logic C0_Bev;
|
||||
logic [19:0] C0_EBase;
|
||||
logic [2:0] K0;
|
||||
logic [3:0] C0_CU;
|
||||
logic in_kernel;
|
||||
logic [2:0] K0;
|
||||
Random_t c0_Random;
|
||||
Index_t c0_Index;
|
||||
EntryHi_t c0_EntryHi;
|
||||
@ -117,6 +119,11 @@ module mycpu_top (
|
||||
logic tlb_tlbp;
|
||||
logic c0_tlbr;
|
||||
logic c0_tlbp;
|
||||
logic [5:0] ext_intb;
|
||||
always_ff @(posedge aclk) begin
|
||||
if (~aresetn) ext_intb = 5'b0;
|
||||
else ext_intb = ext_int;
|
||||
end
|
||||
|
||||
|
||||
AXI axi (
|
||||
@ -187,14 +194,16 @@ module mycpu_top (
|
||||
.wdata (C0_wdata),
|
||||
.exception (C0_exception),
|
||||
.EPC (C0_ERETPC),
|
||||
.EXL (C0_EXL),
|
||||
.Bev (C0_Bev),
|
||||
.EBase (C0_EBase),
|
||||
.ext_int (ext_int),
|
||||
.CU (C0_CU),
|
||||
.in_kernel (in_kernel),
|
||||
.ext_int (ext_intb),
|
||||
.interrupt (C0_int),
|
||||
.tlbr (c0_tlbr),
|
||||
.tlbp (c0_tlbp),
|
||||
.K0 (K0),
|
||||
.in_kernel (in_kernel),
|
||||
.Random (c0_Random),
|
||||
.Index (c0_Index),
|
||||
.EntryHi (c0_EntryHi),
|
||||
@ -236,8 +245,10 @@ module mycpu_top (
|
||||
.C0_wdata (C0_wdata),
|
||||
.C0_exception(C0_exception),
|
||||
.C0_ERETPC (C0_ERETPC),
|
||||
.C0_EXL (C0_EXL),
|
||||
.C0_Bev (C0_Bev),
|
||||
.C0_EBase (C0_EBase),
|
||||
.C0_CU (C0_CU),
|
||||
.C0_kernel (in_kernel),
|
||||
|
||||
.debug_wb_pc (debug_wb_pc),
|
||||
|
||||
@ -6,8 +6,8 @@
|
||||
32'b000000???????????????00000000100 SL ? RS 1 1 RT 0 0 ? ? ? // SLLV
|
||||
32'b000000???????????????00000000110 SR 0 RS 1 1 RT 0 0 ? ? ? // SRLV
|
||||
32'b000000???????????????00000000111 SR 1 RS 1 1 RT 0 0 ? ? ? // SRAV
|
||||
32'b000000???????????????00000001010 MOVA ? RS 1 1 ? ? ? ? ? ? // MOVZ
|
||||
32'b000000???????????????00000001011 MOVA ? RS 1 1 ? ? ? ? ? ? // MOVN
|
||||
32'b000000???????????????00000001010 MOV 0 RS 1 1 RT 0 0 ? ? ? // MOVZ
|
||||
32'b000000???????????????00000001011 MOV 1 RS 1 1 RT 0 0 ? ? ? // MOVN
|
||||
32'b000000?????000000000000000001000 ? ? ? ? ? ? ? ? ? ? ? // JR
|
||||
32'b000000?????00000?????00000001001 ADD 0 PC 0 1 EIGHT 0 1 ? ? ? // JALR
|
||||
32'b000000????????????????????001100 ? ? ? ? ? ? ? ? ? ? ? // SYSCALL
|
||||
@ -74,11 +74,11 @@
|
||||
32'b011100???????????????00000000010 ? ? ? ? ? ? ? ? ? ? ? // MUL
|
||||
32'b100000?????????????????????????? ADD 0 RS 1 1 IMM 1 ? IX 0 1 // LB
|
||||
32'b100001?????????????????????????? ADD 0 RS 1 1 IMM 1 ? IX 0 1 // LH
|
||||
32'h100010?????????????????????????? ADD 0 RS 1 1 IMM 1 ? IX 0 1 // LWL
|
||||
32'b100010?????????????????????????? ADD 0 RS 1 1 IMM 1 ? IX 0 1 // LWL
|
||||
32'b100011?????????????????????????? ADD 0 RS 1 1 IMM 1 ? IX 0 1 // LW
|
||||
32'b100100?????????????????????????? ADD 0 RS 1 1 IMM 1 ? IX 0 1 // LBU
|
||||
32'b100101?????????????????????????? ADD 0 RS 1 1 IMM 1 ? IX 0 1 // LHU
|
||||
32'h100110?????????????????????????? ADD 0 RS 1 1 IMM 1 ? IX 0 1 // LWR
|
||||
32'b100110?????????????????????????? ADD 0 RS 1 1 IMM 1 ? IX 0 1 // LWR
|
||||
32'b101000?????????????????????????? ADD 0 RS 1 1 IMM 1 ? IX 0 1 // SB
|
||||
32'b101001?????????????????????????? ADD 0 RS 1 1 IMM 1 ? IX 0 1 // SH
|
||||
32'b101010?????????????????????????? ADD 0 RS 1 1 IMM 1 ? IX 0 1 // SWL
|
||||
|
||||
176
tools/global.txt
176
tools/global.txt
@ -1,88 +1,88 @@
|
||||
////-------------------------------- SYSCALL BREAK ERET OFA ES ET DS DT DP0 DP1
|
||||
32'b000000000000000000000?????001111 0 0 0 0 ? ? ? ? 1 1 // SYNC (NOP)
|
||||
32'b00000000000???????????????000000 0 0 0 0 0 1 0 0 1 1 // SLL
|
||||
32'b00000000000???????????????000010 0 0 0 0 0 1 0 0 1 1 // SRL
|
||||
32'b00000000000???????????????000011 0 0 0 0 0 1 0 0 1 1 // SRA
|
||||
32'b000000???????????????00000000100 0 0 0 0 1 1 0 0 1 1 // SLLV
|
||||
32'b000000???????????????00000000110 0 0 0 0 1 1 0 0 1 1 // SRLV
|
||||
32'b000000???????????????00000000111 0 0 0 0 1 1 0 0 1 1 // SRAV
|
||||
32'b000000???????????????00000001010 0 0 0 0 1 0 0 1 1 1 // MOVZ
|
||||
32'b000000???????????????00000001011 0 0 0 0 1 0 0 1 1 1 // MOVN
|
||||
32'b000000?????000000000000000001000 0 0 0 0 0 0 1 0 1 1 // JR
|
||||
32'b000000?????00000?????00000001001 0 0 0 0 0 0 1 0 1 1 // JALR
|
||||
32'b000000????????????????????001100 1 0 0 0 0 0 0 0 1 1 // SYSCALL
|
||||
32'b000000????????????????????001101 0 1 0 0 0 0 0 0 1 1 // BREAK
|
||||
32'b0000000000000000?????00000010000 0 0 0 0 0 0 0 0 1 0 // MFHI
|
||||
32'b000000?????000000000000000010001 0 0 0 0 0 0 0 0 1 0 // MTHI
|
||||
32'b0000000000000000?????00000010010 0 0 0 0 0 0 0 0 1 0 // MFLO
|
||||
32'b000000?????000000000000000010011 0 0 0 0 0 0 0 0 1 0 // MTLO
|
||||
32'b000000??????????0000000000011000 0 0 0 0 1 1 0 0 1 0 // MULT
|
||||
32'b000000??????????0000000000011001 0 0 0 0 1 1 0 0 1 0 // MULTU
|
||||
32'b000000??????????0000000000011010 0 0 0 0 1 1 0 0 1 0 // DIV
|
||||
32'b000000??????????0000000000011011 0 0 0 0 1 1 0 0 1 0 // DIVU
|
||||
32'b000000???????????????00000100000 0 0 0 1 1 1 0 0 1 1 // ADD
|
||||
32'b000000???????????????00000100001 0 0 0 0 1 1 0 0 1 1 // ADDU
|
||||
32'b000000???????????????00000100010 0 0 0 1 1 1 0 0 1 1 // SUB
|
||||
32'b000000???????????????00000100011 0 0 0 0 1 1 0 0 1 1 // SUBU
|
||||
32'b000000???????????????00000100100 0 0 0 0 1 1 0 0 1 1 // AND
|
||||
32'b000000???????????????00000100101 0 0 0 0 1 1 0 0 1 1 // OR
|
||||
32'b000000???????????????00000100110 0 0 0 0 1 1 0 0 1 1 // XOR
|
||||
32'b000000???????????????00000100111 0 0 0 0 1 1 0 0 1 1 // NOR
|
||||
32'b000000???????????????00000101010 0 0 0 0 1 1 0 0 1 1 // SLT
|
||||
32'b000000???????????????00000101011 0 0 0 0 1 1 0 0 1 1 // SLTU
|
||||
32'b000000????????????????????110000 0 0 0 0 1 1 0 0 0 1 // TGE
|
||||
32'b000000????????????????????110001 0 0 0 0 1 1 0 0 0 1 // TGEU
|
||||
32'b000000????????????????????110010 0 0 0 0 1 1 0 0 0 1 // TLT
|
||||
32'b000000????????????????????110011 0 0 0 0 1 1 0 0 0 1 // TLTU
|
||||
32'b000000????????????????????110100 0 0 0 0 1 1 0 0 0 1 // TEQ
|
||||
32'b000000????????????????????110110 0 0 0 0 1 1 0 0 0 1 // TNE
|
||||
32'b000001?????00000???????????????? 0 0 0 0 0 0 1 0 1 1 // BLTZ
|
||||
32'b000001?????00001???????????????? 0 0 0 0 0 0 1 0 1 1 // BGEZ
|
||||
32'b000001?????01000???????????????? 0 0 0 0 1 0 0 0 0 1 // TGEI
|
||||
32'b000001?????01001???????????????? 0 0 0 0 1 0 0 0 0 1 // TGEIU
|
||||
32'b000001?????01010???????????????? 0 0 0 0 1 0 0 0 0 1 // TLTI
|
||||
32'b000001?????01011???????????????? 0 0 0 0 1 0 0 0 0 1 // TLTIU
|
||||
32'b000001?????01110???????????????? 0 0 0 0 1 0 0 0 0 1 // TNEI
|
||||
32'b000001?????01100???????????????? 0 0 0 0 1 0 0 0 0 1 // TEQI
|
||||
32'b000001?????10000???????????????? 0 0 0 0 0 0 1 0 1 1 // BLTZAL
|
||||
32'b000001?????10001???????????????? 0 0 0 0 0 0 1 0 1 1 // BGEZAL
|
||||
32'b000010?????????????????????????? 0 0 0 0 0 0 0 0 1 1 // J
|
||||
32'b000011?????????????????????????? 0 0 0 0 0 0 0 0 1 1 // JAL
|
||||
32'b000100?????????????????????????? 0 0 0 0 0 0 1 1 1 1 // BEQ
|
||||
32'b000101?????????????????????????? 0 0 0 0 0 0 1 1 1 1 // BNE
|
||||
32'b000110?????00000???????????????? 0 0 0 0 0 0 1 0 1 1 // BLEZ
|
||||
32'b000111?????00000???????????????? 0 0 0 0 0 0 1 0 1 1 // BGTZ
|
||||
32'b001000?????????????????????????? 0 0 0 1 1 0 0 0 1 1 // ADDI
|
||||
32'b001001?????????????????????????? 0 0 0 0 1 0 0 0 1 1 // ADDIU
|
||||
32'b001010?????????????????????????? 0 0 0 0 1 0 0 0 1 1 // SLTI
|
||||
32'b001011?????????????????????????? 0 0 0 0 1 0 0 0 1 1 // SLTIU
|
||||
32'b001100?????????????????????????? 0 0 0 0 1 0 0 0 1 1 // ANDI
|
||||
32'b001101?????????????????????????? 0 0 0 0 1 0 0 0 1 1 // ORI
|
||||
32'b001110?????????????????????????? 0 0 0 0 1 0 0 0 1 1 // XORI
|
||||
32'b00111100000????????????????????? 0 0 0 0 1 0 0 0 1 1 // LUI
|
||||
32'b01000000000??????????00000000??? 0 0 0 0 0 0 0 0 1 0 // MFC0
|
||||
32'b01000000100??????????00000000??? 0 0 0 0 0 0 0 0 1 0 // MTC0
|
||||
32'b01000010000000000000000000000001 0 0 0 0 0 0 0 0 0 1 // TLBR
|
||||
32'b01000010000000000000000000000010 0 0 0 0 0 0 0 0 0 1 // TLBWI
|
||||
32'b01000010000000000000000000000110 0 0 0 0 0 0 0 0 0 1 // TLBWR
|
||||
32'b01000010000000000000000000001000 0 0 0 0 0 0 0 0 0 1 // TLBP
|
||||
32'b01000010000000000000000000011000 0 0 1 0 0 0 0 0 1 1 // ERET
|
||||
32'b011100??????????0000000000000000 0 0 0 0 1 1 0 0 1 0 // MADD
|
||||
32'b011100??????????0000000000000001 0 0 0 0 1 1 0 0 1 0 // MADDU
|
||||
32'b011100??????????0000000000000100 0 0 0 0 1 1 0 0 1 0 // MSUB
|
||||
32'b011100??????????0000000000000101 0 0 0 0 1 1 0 0 1 0 // MSUBU
|
||||
32'b011100???????????????00000000010 0 0 0 0 1 1 0 0 1 0 // MUL
|
||||
32'b100000?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // LB
|
||||
32'b100001?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // LH
|
||||
32'h100010?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // LWL
|
||||
32'b100011?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // LW
|
||||
32'b100100?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // LBU
|
||||
32'b100101?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // LHU
|
||||
32'h100110?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // LWR
|
||||
32'b101000?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // SB
|
||||
32'b101001?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // SH
|
||||
32'b101010?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // SWL
|
||||
32'b101011?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // SW
|
||||
32'b101110?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // SWR
|
||||
32'b101111?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // CACHE
|
||||
32'b110011?????????????????????????? 0 0 0 0 0 0 0 0 1 1 // PREF (NOP)
|
||||
////-------------------------------- SYSCALL BREAK ERET OFA ES ET ES2 ET2 DS DT DP0 DP1
|
||||
32'b000000000000000000000?????001111 0 0 0 0 0 0 0 0 0 0 1 1 // SYNC (NOP)
|
||||
32'b00000000000???????????????000000 0 0 0 0 0 0 0 1 0 0 1 1 // SLL
|
||||
32'b00000000000???????????????000010 0 0 0 0 0 0 0 1 0 0 1 1 // SRL
|
||||
32'b00000000000???????????????000011 0 0 0 0 0 0 0 1 0 0 1 1 // SRA
|
||||
32'b000000???????????????00000000100 0 0 0 0 0 0 1 1 0 0 1 1 // SLLV
|
||||
32'b000000???????????????00000000110 0 0 0 0 0 0 1 1 0 0 1 1 // SRLV
|
||||
32'b000000???????????????00000000111 0 0 0 0 0 0 1 1 0 0 1 1 // SRAV
|
||||
32'b000000???????????????00000001010 0 0 0 0 1 1 ? ? 0 0 1 1 // MOVZ
|
||||
32'b000000???????????????00000001011 0 0 0 0 1 1 ? ? 0 0 1 1 // MOVN
|
||||
32'b000000?????000000000000000001000 0 0 0 0 0 0 0 0 1 0 1 1 // JR
|
||||
32'b000000?????00000?????00000001001 0 0 0 0 0 0 0 0 1 0 1 1 // JALR
|
||||
32'b000000????????????????????001100 1 0 0 0 0 0 0 0 0 0 1 1 // SYSCALL
|
||||
32'b000000????????????????????001101 0 1 0 0 0 0 0 0 0 0 1 1 // BREAK
|
||||
32'b0000000000000000?????00000010000 0 0 0 0 0 0 0 0 0 0 1 0 // MFHI
|
||||
32'b000000?????000000000000000010001 0 0 0 0 0 0 0 0 0 0 1 0 // MTHI
|
||||
32'b0000000000000000?????00000010010 0 0 0 0 0 0 0 0 0 0 1 0 // MFLO
|
||||
32'b000000?????000000000000000010011 0 0 0 0 0 0 0 0 0 0 1 0 // MTLO
|
||||
32'b000000??????????0000000000011000 0 0 0 0 1 1 ? ? 0 0 1 0 // MULT
|
||||
32'b000000??????????0000000000011001 0 0 0 0 1 1 ? ? 0 0 1 0 // MULTU
|
||||
32'b000000??????????0000000000011010 0 0 0 0 1 1 ? ? 0 0 1 0 // DIV
|
||||
32'b000000??????????0000000000011011 0 0 0 0 1 1 ? ? 0 0 1 0 // DIVU
|
||||
32'b000000???????????????00000100000 0 0 0 1 1 1 ? ? 0 0 1 1 // ADD
|
||||
32'b000000???????????????00000100001 0 0 0 0 0 0 1 1 0 0 1 1 // ADDU
|
||||
32'b000000???????????????00000100010 0 0 0 1 1 1 ? ? 0 0 1 1 // SUB
|
||||
32'b000000???????????????00000100011 0 0 0 0 0 0 1 1 0 0 1 1 // SUBU
|
||||
32'b000000???????????????00000100100 0 0 0 0 0 0 1 1 0 0 1 1 // AND
|
||||
32'b000000???????????????00000100101 0 0 0 0 0 0 1 1 0 0 1 1 // OR
|
||||
32'b000000???????????????00000100110 0 0 0 0 0 0 1 1 0 0 1 1 // XOR
|
||||
32'b000000???????????????00000100111 0 0 0 0 0 0 1 1 0 0 1 1 // NOR
|
||||
32'b000000???????????????00000101010 0 0 0 0 0 0 1 1 0 0 1 1 // SLT
|
||||
32'b000000???????????????00000101011 0 0 0 0 0 0 1 1 0 0 1 1 // SLTU
|
||||
32'b000000????????????????????110000 0 0 0 0 1 1 ? ? 0 0 0 1 // TGE
|
||||
32'b000000????????????????????110001 0 0 0 0 1 1 ? ? 0 0 0 1 // TGEU
|
||||
32'b000000????????????????????110010 0 0 0 0 1 1 ? ? 0 0 0 1 // TLT
|
||||
32'b000000????????????????????110011 0 0 0 0 1 1 ? ? 0 0 0 1 // TLTU
|
||||
32'b000000????????????????????110100 0 0 0 0 1 1 ? ? 0 0 0 1 // TEQ
|
||||
32'b000000????????????????????110110 0 0 0 0 1 1 ? ? 0 0 0 1 // TNE
|
||||
32'b000001?????00000???????????????? 0 0 0 0 0 0 0 0 1 0 1 1 // BLTZ
|
||||
32'b000001?????00001???????????????? 0 0 0 0 0 0 0 0 1 0 1 1 // BGEZ
|
||||
32'b000001?????01000???????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // TGEI
|
||||
32'b000001?????01001???????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // TGEIU
|
||||
32'b000001?????01010???????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // TLTI
|
||||
32'b000001?????01011???????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // TLTIU
|
||||
32'b000001?????01110???????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // TNEI
|
||||
32'b000001?????01100???????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // TEQI
|
||||
32'b000001?????10000???????????????? 0 0 0 0 0 0 0 0 1 0 1 1 // BLTZAL
|
||||
32'b000001?????10001???????????????? 0 0 0 0 0 0 0 0 1 0 1 1 // BGEZAL
|
||||
32'b000010?????????????????????????? 0 0 0 0 0 0 0 0 0 0 1 1 // J
|
||||
32'b000011?????????????????????????? 0 0 0 0 0 0 0 0 0 0 1 1 // JAL
|
||||
32'b000100?????????????????????????? 0 0 0 0 0 0 0 0 1 1 1 1 // BEQ
|
||||
32'b000101?????????????????????????? 0 0 0 0 0 0 0 0 1 1 1 1 // BNE
|
||||
32'b000110?????00000???????????????? 0 0 0 0 0 0 0 0 1 0 1 1 // BLEZ
|
||||
32'b000111?????00000???????????????? 0 0 0 0 0 0 0 0 1 0 1 1 // BGTZ
|
||||
32'b001000?????????????????????????? 0 0 0 1 1 0 ? 0 0 0 1 1 // ADDI
|
||||
32'b001001?????????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // ADDIU
|
||||
32'b001010?????????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // SLTI
|
||||
32'b001011?????????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // SLTIU
|
||||
32'b001100?????????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // ANDI
|
||||
32'b001101?????????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // ORI
|
||||
32'b001110?????????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // XORI
|
||||
32'b00111100000????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // LUI
|
||||
32'b01000000000??????????00000000??? 0 0 0 0 0 0 0 0 0 0 1 0 // MFC0
|
||||
32'b01000000100??????????00000000??? 0 0 0 0 0 0 0 0 0 0 1 0 // MTC0
|
||||
32'b01000010000000000000000000000001 0 0 0 0 0 0 0 0 0 0 0 1 // TLBR
|
||||
32'b01000010000000000000000000000010 0 0 0 0 0 0 0 0 0 0 0 1 // TLBWI
|
||||
32'b01000010000000000000000000000110 0 0 0 0 0 0 0 0 0 0 0 1 // TLBWR
|
||||
32'b01000010000000000000000000001000 0 0 0 0 0 0 0 0 0 0 0 1 // TLBP
|
||||
32'b01000010000000000000000000011000 0 0 1 0 0 0 0 0 0 0 1 1 // ERET
|
||||
32'b011100??????????0000000000000000 0 0 0 0 1 1 ? ? 0 0 1 0 // MADD
|
||||
32'b011100??????????0000000000000001 0 0 0 0 1 1 ? ? 0 0 1 0 // MADDU
|
||||
32'b011100??????????0000000000000100 0 0 0 0 1 1 ? ? 0 0 1 0 // MSUB
|
||||
32'b011100??????????0000000000000101 0 0 0 0 1 1 ? ? 0 0 1 0 // MSUBU
|
||||
32'b011100???????????????00000000010 0 0 0 0 1 1 ? ? 0 0 1 0 // MUL
|
||||
32'b100000?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // LB
|
||||
32'b100001?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // LH
|
||||
32'b100010?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // LWL
|
||||
32'b100011?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // LW
|
||||
32'b100100?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // LBU
|
||||
32'b100101?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // LHU
|
||||
32'b100110?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // LWR
|
||||
32'b101000?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // SB
|
||||
32'b101001?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // SH
|
||||
32'b101010?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // SWL
|
||||
32'b101011?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // SW
|
||||
32'b101110?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // SWR
|
||||
32'b101111?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // CACHE
|
||||
32'b110011?????????????????????????? 0 0 0 0 0 0 0 0 0 0 1 1 // PREF (NOP)
|
||||
@ -74,11 +74,11 @@
|
||||
32'b011100???????????????00000000010 0 0 MUL? 1 0 ? PASST 0 0 0 MUL 0 1 0 // MUL
|
||||
32'b100000?????????????????????????? ? ? ? 0 ? ? ? ? ? 0 ? ? ? ? // LB
|
||||
32'b100001?????????????????????????? ? ? ? 0 ? ? ? ? ? 0 ? ? ? ? // LH
|
||||
32'h100010?????????????????????????? ? ? ? 0 ? ? ? ? ? 0 ? ? ? ? // LWL
|
||||
32'b100010?????????????????????????? ? ? ? 0 ? ? ? ? ? 0 ? ? ? ? // LWL
|
||||
32'b100011?????????????????????????? ? ? ? 0 ? ? ? ? ? 0 ? ? ? ? // LW
|
||||
32'b100100?????????????????????????? ? ? ? 0 ? ? ? ? ? 0 ? ? ? ? // LBU
|
||||
32'b100101?????????????????????????? ? ? ? 0 ? ? ? ? ? 0 ? ? ? ? // LHU
|
||||
32'h100110?????????????????????????? ? ? ? 0 ? ? ? ? ? 0 ? ? ? ? // LWR
|
||||
32'b100110?????????????????????????? ? ? ? 0 ? ? ? ? ? 0 ? ? ? ? // LWR
|
||||
32'b101000?????????????????????????? ? ? ? 0 ? ? ? ? ? 0 ? ? ? ? // SB
|
||||
32'b101001?????????????????????????? ? ? ? 0 ? ? ? ? ? 0 ? ? ? ? // SH
|
||||
32'b101010?????????????????????????? ? ? ? 0 ? ? ? ? ? 0 ? ? ? ? // SWL
|
||||
|
||||
188
tools/mctrl1.txt
188
tools/mctrl1.txt
@ -1,94 +1,94 @@
|
||||
////-------------------------------- TLBR TLBWI TLBWR TLBP MR MWR MX ALR ALR1 ALR0 CACHEOP CO2 CO1 CO0
|
||||
32'b000000000000000000000?????001111 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // SYNC (NOP)
|
||||
32'b00000000000???????????????000000 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // SLL
|
||||
32'b00000000000???????????????000010 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // SRL
|
||||
32'b00000000000???????????????000011 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // SRA
|
||||
32'b000000???????????????00000000100 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // SLLV
|
||||
32'b000000???????????????00000000110 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // SRLV
|
||||
32'b000000???????????????00000000111 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // SRAV
|
||||
32'b000000???????????????00000001010 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // MOVZ
|
||||
32'b000000???????????????00000001011 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // MOVN
|
||||
32'b000000?????000000000000000001000 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // JR
|
||||
32'b000000?????00000?????00000001001 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // JALR
|
||||
32'b000000????????????????????001100 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // SYSCALL
|
||||
32'b000000????????????????????001101 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // BREAK
|
||||
32'b0000000000000000?????00000010000 0 0 0 0 ? ? ? ? ? ? ? ? ? ? // MFHI
|
||||
32'b000000?????000000000000000010001 0 0 0 0 ? ? ? ? ? ? ? ? ? ? // MTHI
|
||||
32'b0000000000000000?????00000010010 0 0 0 0 ? ? ? ? ? ? ? ? ? ? // MFLO
|
||||
32'b000000?????000000000000000010011 0 0 0 0 ? ? ? ? ? ? ? ? ? ? // MTLO
|
||||
32'b000000??????????0000000000011000 0 0 0 0 ? ? ? ? ? ? ? ? ? ? // MULT
|
||||
32'b000000??????????0000000000011001 0 0 0 0 ? ? ? ? ? ? ? ? ? ? // MULTU
|
||||
32'b000000??????????0000000000011010 0 0 0 0 ? ? ? ? ? ? ? ? ? ? // DIV
|
||||
32'b000000??????????0000000000011011 0 0 0 0 ? ? ? ? ? ? ? ? ? ? // DIVU
|
||||
32'b000000???????????????00000100000 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // ADD
|
||||
32'b000000???????????????00000100001 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // ADDU
|
||||
32'b000000???????????????00000100010 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // SUB
|
||||
32'b000000???????????????00000100011 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // SUBU
|
||||
32'b000000???????????????00000100100 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // AND
|
||||
32'b000000???????????????00000100101 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // OR
|
||||
32'b000000???????????????00000100110 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // XOR
|
||||
32'b000000???????????????00000100111 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // NOR
|
||||
32'b000000???????????????00000101010 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // SLT
|
||||
32'b000000???????????????00000101011 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // SLTU
|
||||
32'b000000????????????????????110000 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // TGE
|
||||
32'b000000????????????????????110001 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // TGEU
|
||||
32'b000000????????????????????110010 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // TLT
|
||||
32'b000000????????????????????110011 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // TLTU
|
||||
32'b000000????????????????????110100 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // TEQ
|
||||
32'b000000????????????????????110110 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // TNE
|
||||
32'b000001?????00000???????????????? 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // BLTZ
|
||||
32'b000001?????00001???????????????? 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // BGEZ
|
||||
32'b000001?????01000???????????????? 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // TGEI
|
||||
32'b000001?????01001???????????????? 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // TGEIU
|
||||
32'b000001?????01010???????????????? 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // TLTI
|
||||
32'b000001?????01011???????????????? 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // TLTIU
|
||||
32'b000001?????01110???????????????? 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // TNEI
|
||||
32'b000001?????01100???????????????? 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // TEQI
|
||||
32'b000001?????10000???????????????? 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // BLTZAL
|
||||
32'b000001?????10001???????????????? 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // BGEZAL
|
||||
32'b000010?????????????????????????? 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // J
|
||||
32'b000011?????????????????????????? 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // JAL
|
||||
32'b000100?????????????????????????? 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // BEQ
|
||||
32'b000101?????????????????????????? 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // BNE
|
||||
32'b000110?????00000???????????????? 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // BLEZ
|
||||
32'b000111?????00000???????????????? 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // BGTZ
|
||||
32'b001000?????????????????????????? 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // ADDI
|
||||
32'b001001?????????????????????????? 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // ADDIU
|
||||
32'b001010?????????????????????????? 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // SLTI
|
||||
32'b001011?????????????????????????? 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // SLTIU
|
||||
32'b001100?????????????????????????? 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // ANDI
|
||||
32'b001101?????????????????????????? 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // ORI
|
||||
32'b001110?????????????????????????? 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // XORI
|
||||
32'b00111100000????????????????????? 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // LUI
|
||||
32'b01000000000??????????00000000??? 0 0 0 0 ? ? ? ? ? ? ? ? ? ? // MFC0
|
||||
32'b01000000100??????????00000000??? 0 0 0 0 ? ? ? ? ? ? ? ? ? ? // MTC0
|
||||
32'b01000010000000000000000000000001 1 0 1 0 0 ? ? ? ? ? ? ? ? ? // TLBR
|
||||
32'b01000010000000000000000000000010 0 1 0 0 0 ? ? ? ? ? ? ? ? ? // TLBWI
|
||||
32'b01000010000000000000000000000110 0 1 1 0 0 ? ? ? ? ? ? ? ? ? // TLBWR
|
||||
32'b01000010000000000000000000001000 0 0 0 1 0 ? ? ? ? ? ? ? ? ? // TLBP
|
||||
32'b01000010000000000000000000011000 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // ERET
|
||||
32'b011100??????????0000000000000000 0 0 0 0 ? ? ? ? ? ? ? ? ? ? // MADD
|
||||
32'b011100??????????0000000000000001 0 0 0 0 ? ? ? ? ? ? ? ? ? ? // MADDU
|
||||
32'b011100??????????0000000000000100 0 0 0 0 ? ? ? ? ? ? ? ? ? ? // MSUB
|
||||
32'b011100??????????0000000000000101 0 0 0 0 ? ? ? ? ? ? ? ? ? ? // MSUBU
|
||||
32'b011100???????????????00000000010 0 0 0 0 ? ? ? ? ? ? ? ? ? ? // MUL
|
||||
32'b100000?????????????????????????? 0 0 0 0 1 0 1 ALIGN 0 0 CNOP 0 0 0 // LB
|
||||
32'b100001?????????????????????????? 0 0 0 0 1 0 1 ALIGN 0 0 CNOP 0 0 0 // LH
|
||||
32'h100010?????????????????????????? 0 0 0 0 1 0 ? ULEFT 0 1 CNOP 0 0 0 // LWL
|
||||
32'b100011?????????????????????????? 0 0 0 0 1 0 ? ALIGN 0 0 CNOP 0 0 0 // LW
|
||||
32'b100100?????????????????????????? 0 0 0 0 1 0 0 ALIGN 0 0 CNOP 0 0 0 // LBU
|
||||
32'b100101?????????????????????????? 0 0 0 0 1 0 0 ALIGN 0 0 CNOP 0 0 0 // LHU
|
||||
32'h100110?????????????????????????? 0 0 0 0 1 0 ? URIGHT 1 0 CNOP 0 0 0 // LWR
|
||||
32'b101000?????????????????????????? 0 0 0 0 1 1 ? ALIGN 0 0 CNOP 0 0 0 // SB
|
||||
32'b101001?????????????????????????? 0 0 0 0 1 1 ? ALIGN 0 0 CNOP 0 0 0 // SH
|
||||
32'b101010?????????????????????????? 0 0 0 0 1 1 ? ULEFT 0 1 CNOP 0 0 0 // SWL
|
||||
32'b101011?????????????????????????? 0 0 0 0 1 1 ? ALIGN 0 0 CNOP 0 0 0 // SW
|
||||
32'b101110?????????????????????????? 0 0 0 0 1 1 ? URIGHT 1 0 CNOP 0 0 0 // SWR
|
||||
32'b101111?????00000???????????????? 0 0 0 0 1 1 ? ALIGN 0 0 IC_I 0 1 1 // I-Cache Index Invalid
|
||||
32'b101111?????01000???????????????? 0 0 0 0 1 1 ? ALIGN 0 0 IC_I 0 1 1 // I-Cache Index Store Tag
|
||||
32'b101111?????10000???????????????? 0 0 0 0 1 1 ? ALIGN 0 0 IC_L 0 0 1 // I-Cache Hit Invalid
|
||||
32'b101111?????00001???????????????? 0 0 0 0 1 1 ? ALIGN 0 0 DC_IB 1 1 0 // D-Cache Index Writeback Invalid
|
||||
32'b101111?????01001???????????????? 0 0 0 0 1 1 ? ALIGN 0 0 DC_IO 1 1 1 // D-Cache Index Store Tag
|
||||
32'b101111?????10001???????????????? 0 0 0 0 1 1 ? ALIGN 0 0 DC_LO 1 0 1 // D-Cache Hit Invalid
|
||||
32'b101111?????10101???????????????? 0 0 0 0 1 1 ? ALIGN 0 0 DC_LB 1 0 0 // D-Cache Hit Writeback Invalid
|
||||
32'b110011?????????????????????????? 0 0 0 0 0 ? ? ? ? ? ? ? ? ? // PREF (NOP)
|
||||
////-------------------------------- TLBR TLBWI TLBWR TLBP MR MWR MX ALR ALR1 ALR0 CACHEOP iop dop ioh wb
|
||||
32'b000000000000000000000?????001111 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // SYNC (NOP)
|
||||
32'b00000000000???????????????000000 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // SLL
|
||||
32'b00000000000???????????????000010 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // SRL
|
||||
32'b00000000000???????????????000011 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // SRA
|
||||
32'b000000???????????????00000000100 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // SLLV
|
||||
32'b000000???????????????00000000110 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // SRLV
|
||||
32'b000000???????????????00000000111 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // SRAV
|
||||
32'b000000???????????????00000001010 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // MOVZ
|
||||
32'b000000???????????????00000001011 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // MOVN
|
||||
32'b000000?????000000000000000001000 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // JR
|
||||
32'b000000?????00000?????00000001001 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // JALR
|
||||
32'b000000????????????????????001100 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // SYSCALL
|
||||
32'b000000????????????????????001101 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // BREAK
|
||||
32'b0000000000000000?????00000010000 0 0 0 0 ? ? ? ? ? ? CNOP 0 0 ? ? // MFHI
|
||||
32'b000000?????000000000000000010001 0 0 0 0 ? ? ? ? ? ? CNOP 0 0 ? ? // MTHI
|
||||
32'b0000000000000000?????00000010010 0 0 0 0 ? ? ? ? ? ? CNOP 0 0 ? ? // MFLO
|
||||
32'b000000?????000000000000000010011 0 0 0 0 ? ? ? ? ? ? CNOP 0 0 ? ? // MTLO
|
||||
32'b000000??????????0000000000011000 0 0 0 0 ? ? ? ? ? ? CNOP 0 0 ? ? // MULT
|
||||
32'b000000??????????0000000000011001 0 0 0 0 ? ? ? ? ? ? CNOP 0 0 ? ? // MULTU
|
||||
32'b000000??????????0000000000011010 0 0 0 0 ? ? ? ? ? ? CNOP 0 0 ? ? // DIV
|
||||
32'b000000??????????0000000000011011 0 0 0 0 ? ? ? ? ? ? CNOP 0 0 ? ? // DIVU
|
||||
32'b000000???????????????00000100000 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // ADD
|
||||
32'b000000???????????????00000100001 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // ADDU
|
||||
32'b000000???????????????00000100010 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // SUB
|
||||
32'b000000???????????????00000100011 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // SUBU
|
||||
32'b000000???????????????00000100100 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // AND
|
||||
32'b000000???????????????00000100101 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // OR
|
||||
32'b000000???????????????00000100110 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // XOR
|
||||
32'b000000???????????????00000100111 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // NOR
|
||||
32'b000000???????????????00000101010 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // SLT
|
||||
32'b000000???????????????00000101011 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // SLTU
|
||||
32'b000000????????????????????110000 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // TGE
|
||||
32'b000000????????????????????110001 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // TGEU
|
||||
32'b000000????????????????????110010 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // TLT
|
||||
32'b000000????????????????????110011 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // TLTU
|
||||
32'b000000????????????????????110100 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // TEQ
|
||||
32'b000000????????????????????110110 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // TNE
|
||||
32'b000001?????00000???????????????? 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // BLTZ
|
||||
32'b000001?????00001???????????????? 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // BGEZ
|
||||
32'b000001?????01000???????????????? 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // TGEI
|
||||
32'b000001?????01001???????????????? 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // TGEIU
|
||||
32'b000001?????01010???????????????? 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // TLTI
|
||||
32'b000001?????01011???????????????? 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // TLTIU
|
||||
32'b000001?????01110???????????????? 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // TNEI
|
||||
32'b000001?????01100???????????????? 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // TEQI
|
||||
32'b000001?????10000???????????????? 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // BLTZAL
|
||||
32'b000001?????10001???????????????? 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // BGEZAL
|
||||
32'b000010?????????????????????????? 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // J
|
||||
32'b000011?????????????????????????? 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // JAL
|
||||
32'b000100?????????????????????????? 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // BEQ
|
||||
32'b000101?????????????????????????? 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // BNE
|
||||
32'b000110?????00000???????????????? 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // BLEZ
|
||||
32'b000111?????00000???????????????? 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // BGTZ
|
||||
32'b001000?????????????????????????? 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // ADDI
|
||||
32'b001001?????????????????????????? 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // ADDIU
|
||||
32'b001010?????????????????????????? 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // SLTI
|
||||
32'b001011?????????????????????????? 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // SLTIU
|
||||
32'b001100?????????????????????????? 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // ANDI
|
||||
32'b001101?????????????????????????? 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // ORI
|
||||
32'b001110?????????????????????????? 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // XORI
|
||||
32'b00111100000????????????????????? 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // LUI
|
||||
32'b01000000000??????????00000000??? 0 0 0 0 ? ? ? ? ? ? CNOP 0 0 ? ? // MFC0
|
||||
32'b01000000100??????????00000000??? 0 0 0 0 ? ? ? ? ? ? CNOP 0 0 ? ? // MTC0
|
||||
32'b01000010000000000000000000000001 1 0 1 0 0 ? ? ? ? ? CNOP 0 0 ? ? // TLBR
|
||||
32'b01000010000000000000000000000010 0 1 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // TLBWI
|
||||
32'b01000010000000000000000000000110 0 1 1 0 0 ? ? ? ? ? CNOP 0 0 ? ? // TLBWR
|
||||
32'b01000010000000000000000000001000 0 0 0 1 0 ? ? ? ? ? CNOP 0 0 ? ? // TLBP
|
||||
32'b01000010000000000000000000011000 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // ERET
|
||||
32'b011100??????????0000000000000000 0 0 0 0 ? ? ? ? ? ? CNOP 0 0 ? ? // MADD
|
||||
32'b011100??????????0000000000000001 0 0 0 0 ? ? ? ? ? ? CNOP 0 0 ? ? // MADDU
|
||||
32'b011100??????????0000000000000100 0 0 0 0 ? ? ? ? ? ? CNOP 0 0 ? ? // MSUB
|
||||
32'b011100??????????0000000000000101 0 0 0 0 ? ? ? ? ? ? CNOP 0 0 ? ? // MSUBU
|
||||
32'b011100???????????????00000000010 0 0 0 0 ? ? ? ? ? ? CNOP 0 0 ? ? // MUL
|
||||
32'b100000?????????????????????????? 0 0 0 0 1 0 1 ALIGN 0 0 CNOP 0 0 ? ? // LB
|
||||
32'b100001?????????????????????????? 0 0 0 0 1 0 1 ALIGN 0 0 CNOP 0 0 ? ? // LH
|
||||
32'b100010?????????????????????????? 0 0 0 0 1 0 ? ULEFT 0 1 CNOP 0 0 ? ? // LWL
|
||||
32'b100011?????????????????????????? 0 0 0 0 1 0 ? ALIGN 0 0 CNOP 0 0 ? ? // LW
|
||||
32'b100100?????????????????????????? 0 0 0 0 1 0 0 ALIGN 0 0 CNOP 0 0 ? ? // LBU
|
||||
32'b100101?????????????????????????? 0 0 0 0 1 0 0 ALIGN 0 0 CNOP 0 0 ? ? // LHU
|
||||
32'b100110?????????????????????????? 0 0 0 0 1 0 ? URIGHT 1 0 CNOP 0 0 ? ? // LWR
|
||||
32'b101000?????????????????????????? 0 0 0 0 1 1 ? ALIGN 0 0 CNOP 0 0 ? ? // SB
|
||||
32'b101001?????????????????????????? 0 0 0 0 1 1 ? ALIGN 0 0 CNOP 0 0 ? ? // SH
|
||||
32'b101010?????????????????????????? 0 0 0 0 1 1 ? ULEFT 0 1 CNOP 0 0 ? ? // SWL
|
||||
32'b101011?????????????????????????? 0 0 0 0 1 1 ? ALIGN 0 0 CNOP 0 0 ? ? // SW
|
||||
32'b101110?????????????????????????? 0 0 0 0 1 1 ? URIGHT 1 0 CNOP 0 0 ? ? // SWR
|
||||
32'b101111?????00000???????????????? 0 0 0 0 0 ? ? ALIGN 0 0 IC_I 1 0 0 0 // I-Cache Index Invalid
|
||||
32'b101111?????01000???????????????? 0 0 0 0 0 ? ? ALIGN 0 0 IC_I 1 0 0 0 // I-Cache Index Store Tag
|
||||
32'b101111?????10000???????????????? 0 0 0 0 0 ? ? ALIGN 0 0 IC_L 1 0 1 0 // I-Cache Hit Invalid
|
||||
32'b101111?????00001???????????????? 0 0 0 0 0 ? ? ALIGN 0 0 DC_IB 0 1 0 1 // D-Cache Index Writeback Invalid
|
||||
32'b101111?????01001???????????????? 0 0 0 0 0 ? ? ALIGN 0 0 DC_IO 0 1 0 0 // D-Cache Index Store Tag
|
||||
32'b101111?????10001???????????????? 0 0 0 0 0 ? ? ALIGN 0 0 DC_LO 0 1 1 0 // D-Cache Hit Invalid
|
||||
32'b101111?????10101???????????????? 0 0 0 0 0 ? ? ALIGN 0 0 DC_LB 0 1 1 1 // D-Cache Hit Writeback Invalid
|
||||
32'b110011?????????????????????????? 0 0 0 0 0 ? ? ? ? ? CNOP 0 0 ? ? // PREF (NOP)
|
||||
@ -74,11 +74,11 @@
|
||||
32'b011100???????????????00000000010 0 0 0 0 // MUL
|
||||
32'b100000?????????????????????????? 0 0 0 0 // LB
|
||||
32'b100001?????????????????????????? 0 0 0 0 // LH
|
||||
32'h100010?????????????????????????? 0 0 0 0 // LWL
|
||||
32'b100010?????????????????????????? 0 0 0 0 // LWL
|
||||
32'b100011?????????????????????????? 0 0 0 0 // LW
|
||||
32'b100100?????????????????????????? 0 0 0 0 // LBU
|
||||
32'b100101?????????????????????????? 0 0 0 0 // LHU
|
||||
32'h100110?????????????????????????? 0 0 0 0 // LWR
|
||||
32'b100110?????????????????????????? 0 0 0 0 // LWR
|
||||
32'b101000?????????????????????????? 0 0 0 0 // SB
|
||||
32'b101001?????????????????????????? 0 0 0 0 // SH
|
||||
32'b101010?????????????????????????? 0 0 0 0 // SWL
|
||||
|
||||
@ -1,88 +0,0 @@
|
||||
////-------------------------------- PRV
|
||||
32'b000000000000000000000?????001111 0 // SYNC (NOP)
|
||||
32'b00000000000???????????????000000 0 // SLL
|
||||
32'b00000000000???????????????000010 0 // SRL
|
||||
32'b00000000000???????????????000011 0 // SRA
|
||||
32'b000000???????????????00000000100 0 // SLLV
|
||||
32'b000000???????????????00000000110 0 // SRLV
|
||||
32'b000000???????????????00000000111 0 // SRAV
|
||||
32'b000000???????????????00000001010 0 // MOVZ
|
||||
32'b000000???????????????00000001011 0 // MOVN
|
||||
32'b000000?????000000000000000001000 0 // JR
|
||||
32'b000000?????00000?????00000001001 0 // JALR
|
||||
32'b000000????????????????????001100 0 // SYSCALL
|
||||
32'b000000????????????????????001101 0 // BREAK
|
||||
32'b0000000000000000?????00000010000 0 // MFHI
|
||||
32'b000000?????000000000000000010001 0 // MTHI
|
||||
32'b0000000000000000?????00000010010 0 // MFLO
|
||||
32'b000000?????000000000000000010011 0 // MTLO
|
||||
32'b000000??????????0000000000011000 0 // MULT
|
||||
32'b000000??????????0000000000011001 0 // MULTU
|
||||
32'b000000??????????0000000000011010 0 // DIV
|
||||
32'b000000??????????0000000000011011 0 // DIVU
|
||||
32'b000000???????????????00000100000 0 // ADD
|
||||
32'b000000???????????????00000100001 0 // ADDU
|
||||
32'b000000???????????????00000100010 0 // SUB
|
||||
32'b000000???????????????00000100011 0 // SUBU
|
||||
32'b000000???????????????00000100100 0 // AND
|
||||
32'b000000???????????????00000100101 0 // OR
|
||||
32'b000000???????????????00000100110 0 // XOR
|
||||
32'b000000???????????????00000100111 0 // NOR
|
||||
32'b000000???????????????00000101010 0 // SLT
|
||||
32'b000000???????????????00000101011 0 // SLTU
|
||||
32'b000000????????????????????110000 0 // TGE
|
||||
32'b000000????????????????????110001 0 // TGEU
|
||||
32'b000000????????????????????110010 0 // TLT
|
||||
32'b000000????????????????????110011 0 // TLTU
|
||||
32'b000000????????????????????110100 0 // TEQ
|
||||
32'b000000????????????????????110110 0 // TNE
|
||||
32'b000001?????00000???????????????? 0 // BLTZ
|
||||
32'b000001?????00001???????????????? 0 // BGEZ
|
||||
32'b000001?????01000???????????????? 0 // TGEI
|
||||
32'b000001?????01001???????????????? 0 // TGEIU
|
||||
32'b000001?????01010???????????????? 0 // TLTI
|
||||
32'b000001?????01011???????????????? 0 // TLTIU
|
||||
32'b000001?????01110???????????????? 0 // TNEI
|
||||
32'b000001?????01100???????????????? 0 // TEQI
|
||||
32'b000001?????10000???????????????? 0 // BLTZAL
|
||||
32'b000001?????10001???????????????? 0 // BGEZAL
|
||||
32'b000010?????????????????????????? 0 // J
|
||||
32'b000011?????????????????????????? 0 // JAL
|
||||
32'b000100?????????????????????????? 0 // BEQ
|
||||
32'b000101?????????????????????????? 0 // BNE
|
||||
32'b000110?????00000???????????????? 0 // BLEZ
|
||||
32'b000111?????00000???????????????? 0 // BGTZ
|
||||
32'b001000?????????????????????????? 0 // ADDI
|
||||
32'b001001?????????????????????????? 0 // ADDIU
|
||||
32'b001010?????????????????????????? 0 // SLTI
|
||||
32'b001011?????????????????????????? 0 // SLTIU
|
||||
32'b001100?????????????????????????? 0 // ANDI
|
||||
32'b001101?????????????????????????? 0 // ORI
|
||||
32'b001110?????????????????????????? 0 // XORI
|
||||
32'b00111100000????????????????????? 0 // LUI
|
||||
32'b01000000000??????????00000000??? 1 // MFC0
|
||||
32'b01000000100??????????00000000??? 1 // MTC0
|
||||
32'b01000010000000000000000000000001 1 // TLBR
|
||||
32'b01000010000000000000000000000010 1 // TLBWI
|
||||
32'b01000010000000000000000000000110 1 // TLBWR
|
||||
32'b01000010000000000000000000001000 1 // TLBP
|
||||
32'b01000010000000000000000000011000 1 // ERET
|
||||
32'b011100??????????0000000000000000 0 // MADD
|
||||
32'b011100??????????0000000000000001 0 // MADDU
|
||||
32'b011100??????????0000000000000100 0 // MSUB
|
||||
32'b011100??????????0000000000000101 0 // MSUBU
|
||||
32'b011100???????????????00000000010 0 // MUL
|
||||
32'b100000?????????????????????????? 0 // LB
|
||||
32'b100001?????????????????????????? 0 // LH
|
||||
32'h100010?????????????????????????? 0 // LWL
|
||||
32'b100011?????????????????????????? 0 // LW
|
||||
32'b100100?????????????????????????? 0 // LBU
|
||||
32'b100101?????????????????????????? 0 // LHU
|
||||
32'h100110?????????????????????????? 0 // LWR
|
||||
32'b101000?????????????????????????? 0 // SB
|
||||
32'b101001?????????????????????????? 0 // SH
|
||||
32'b101010?????????????????????????? 0 // SWL
|
||||
32'b101011?????????????????????????? 0 // SW
|
||||
32'b101110?????????????????????????? 0 // SWR
|
||||
32'b101111?????????????????????????? 0 // CACHE
|
||||
32'b110011?????????????????????????? 0 // PREF (NOP)
|
||||
@ -60,13 +60,13 @@
|
||||
32'b001101?????????????????????????? 0 ? ? ? // ORI
|
||||
32'b001110?????????????????????????? 0 ? ? ? // XORI
|
||||
32'b00111100000????????????????????? 0 ? ? ? // LUI
|
||||
32'b01000000000??????????00000000??? 1 ? ? ? // MFC0
|
||||
32'b01000000100??????????00000000??? 1 ? ? ? // MTC0
|
||||
32'b01000010000000000000000000000001 1 ? ? ? // TLBR
|
||||
32'b01000010000000000000000000000010 1 ? ? ? // TLBWI
|
||||
32'b01000010000000000000000000000110 1 ? ? ? // TLBWR
|
||||
32'b01000010000000000000000000001000 1 ? ? ? // TLBP
|
||||
32'b01000010000000000000000000011000 1 ? ? ? // ERET
|
||||
32'b01000000000??????????00000000??? 0 ? ? ? // MFC0
|
||||
32'b01000000100??????????00000000??? 0 ? ? ? // MTC0
|
||||
32'b01000010000000000000000000000001 0 ? ? ? // TLBR
|
||||
32'b01000010000000000000000000000010 0 ? ? ? // TLBWI
|
||||
32'b01000010000000000000000000000110 0 ? ? ? // TLBWR
|
||||
32'b01000010000000000000000000001000 0 ? ? ? // TLBP
|
||||
32'b01000010000000000000000000011000 0 ? ? ? // ERET
|
||||
32'b011100??????????0000000000000000 0 ? ? ? // MADD
|
||||
32'b011100??????????0000000000000001 0 ? ? ? // MADDU
|
||||
32'b011100??????????0000000000000100 0 ? ? ? // MSUB
|
||||
@ -74,11 +74,11 @@
|
||||
32'b011100???????????????00000000010 0 ? ? ? // MUL
|
||||
32'b100000?????????????????????????? 0 ? ? ? // LB
|
||||
32'b100001?????????????????????????? 0 ? ? ? // LH
|
||||
32'h100010?????????????????????????? 0 ? ? ? // LWL
|
||||
32'b100010?????????????????????????? 0 ? ? ? // LWL
|
||||
32'b100011?????????????????????????? 0 ? ? ? // LW
|
||||
32'b100100?????????????????????????? 0 ? ? ? // LBU
|
||||
32'b100101?????????????????????????? 0 ? ? ? // LHU
|
||||
32'h100110?????????????????????????? 0 ? ? ? // LWR
|
||||
32'b100110?????????????????????????? 0 ? ? ? // LWR
|
||||
32'b101000?????????????????????????? 0 ? ? ? // SB
|
||||
32'b101001?????????????????????????? 0 ? ? ? // SH
|
||||
32'b101010?????????????????????????? 0 ? ? ? // SWL
|
||||
|
||||
176
tools/wctrl.txt
176
tools/wctrl.txt
@ -1,88 +1,88 @@
|
||||
////-------------------------------- MOV RW RD RD1 RD0
|
||||
32'b000000000000000000000?????001111 0 0 ? ? ? // SYNC (NOP)
|
||||
32'b00000000000???????????????000000 0 1 RD 0 0 // SLL
|
||||
32'b00000000000???????????????000010 0 1 RD 0 0 // SRL
|
||||
32'b00000000000???????????????000011 0 1 RD 0 0 // SRA
|
||||
32'b000000???????????????00000000100 0 1 RD 0 0 // SLLV
|
||||
32'b000000???????????????00000000110 0 1 RD 0 0 // SRLV
|
||||
32'b000000???????????????00000000111 0 1 RD 0 0 // SRAV
|
||||
32'b000000???????????????00000001010 1 1 RD 0 0 // MOVZ
|
||||
32'b000000???????????????00000001011 1 1 RD 0 0 // MOVN
|
||||
32'b000000?????000000000000000001000 0 0 ? ? ? // JR
|
||||
32'b000000?????00000?????00000001001 0 1 RD 0 0 // JALR
|
||||
32'b000000????????????????????001100 0 0 ? ? ? // SYSCALL
|
||||
32'b000000????????????????????001101 0 0 ? ? ? // BREAK
|
||||
32'b0000000000000000?????00000010000 0 1 RD 0 0 // MFHI
|
||||
32'b000000?????000000000000000010001 0 0 ? ? ? // MTHI
|
||||
32'b0000000000000000?????00000010010 0 1 RD 0 0 // MFLO
|
||||
32'b000000?????000000000000000010011 0 0 ? ? ? // MTLO
|
||||
32'b000000??????????0000000000011000 0 0 ? ? ? // MULT
|
||||
32'b000000??????????0000000000011001 0 0 ? ? ? // MULTU
|
||||
32'b000000??????????0000000000011010 0 0 ? ? ? // DIV
|
||||
32'b000000??????????0000000000011011 0 0 ? ? ? // DIVU
|
||||
32'b000000???????????????00000100000 0 1 RD 0 0 // ADD
|
||||
32'b000000???????????????00000100001 0 1 RD 0 0 // ADDU
|
||||
32'b000000???????????????00000100010 0 1 RD 0 0 // SUB
|
||||
32'b000000???????????????00000100011 0 1 RD 0 0 // SUBU
|
||||
32'b000000???????????????00000100100 0 1 RD 0 0 // AND
|
||||
32'b000000???????????????00000100101 0 1 RD 0 0 // OR
|
||||
32'b000000???????????????00000100110 0 1 RD 0 0 // XOR
|
||||
32'b000000???????????????00000100111 0 1 RD 0 0 // NOR
|
||||
32'b000000???????????????00000101010 0 1 RD 0 0 // SLT
|
||||
32'b000000???????????????00000101011 0 1 RD 0 0 // SLTU
|
||||
32'b000000????????????????????110000 0 0 ? ? ? // TGE
|
||||
32'b000000????????????????????110001 0 0 ? ? ? // TGEU
|
||||
32'b000000????????????????????110010 0 0 ? ? ? // TLT
|
||||
32'b000000????????????????????110011 0 0 ? ? ? // TLTU
|
||||
32'b000000????????????????????110100 0 0 ? ? ? // TEQ
|
||||
32'b000000????????????????????110110 0 0 ? ? ? // TNE
|
||||
32'b000001?????00000???????????????? 0 0 ? ? ? // BLTZ
|
||||
32'b000001?????00001???????????????? 0 0 ? ? ? // BGEZ
|
||||
32'b000001?????01000???????????????? 0 0 ? ? ? // TGEI
|
||||
32'b000001?????01001???????????????? 0 0 ? ? ? // TGEIU
|
||||
32'b000001?????01010???????????????? 0 0 ? ? ? // TLTI
|
||||
32'b000001?????01011???????????????? 0 0 ? ? ? // TLTIU
|
||||
32'b000001?????01110???????????????? 0 0 ? ? ? // TNEI
|
||||
32'b000001?????01100???????????????? 0 0 ? ? ? // TEQI
|
||||
32'b000001?????10000???????????????? 0 1 31 0 1 // BLTZAL
|
||||
32'b000001?????10001???????????????? 0 1 31 0 1 // BGEZAL
|
||||
32'b000010?????????????????????????? 0 0 ? ? ? // J
|
||||
32'b000011?????????????????????????? 0 1 31 0 1 // JAL
|
||||
32'b000100?????????????????????????? 0 0 ? ? ? // BEQ
|
||||
32'b000101?????????????????????????? 0 0 ? ? ? // BNE
|
||||
32'b000110?????00000???????????????? 0 0 ? ? ? // BLEZ
|
||||
32'b000111?????00000???????????????? 0 0 ? ? ? // BGTZ
|
||||
32'b001000?????????????????????????? 0 1 RT 1 ? // ADDI
|
||||
32'b001001?????????????????????????? 0 1 RT 1 ? // ADDIU
|
||||
32'b001010?????????????????????????? 0 1 RT 1 ? // SLTI
|
||||
32'b001011?????????????????????????? 0 1 RT 1 ? // SLTIU
|
||||
32'b001100?????????????????????????? 0 1 RT 1 ? // ANDI
|
||||
32'b001101?????????????????????????? 0 1 RT 1 ? // ORI
|
||||
32'b001110?????????????????????????? 0 1 RT 1 ? // XORI
|
||||
32'b00111100000????????????????????? 0 1 RT 1 ? // LUI
|
||||
32'b01000000000??????????00000000??? 0 1 RT 1 ? // MFC0
|
||||
32'b01000000100??????????00000000??? 0 0 ? ? ? // MTC0
|
||||
32'b01000010000000000000000000000001 0 0 ? ? ? // TLBR
|
||||
32'b01000010000000000000000000000010 0 0 ? ? ? // TLBWI
|
||||
32'b01000010000000000000000000000110 0 0 ? ? ? // TLBWR
|
||||
32'b01000010000000000000000000001000 0 0 ? ? ? // TLBP
|
||||
32'b01000010000000000000000000011000 0 0 ? ? ? // ERET
|
||||
32'b011100??????????0000000000000000 0 0 ? ? ? // MADD
|
||||
32'b011100??????????0000000000000001 0 0 ? ? ? // MADDU
|
||||
32'b011100??????????0000000000000100 0 0 ? ? ? // MSUB
|
||||
32'b011100??????????0000000000000101 0 0 ? ? ? // MSUBU
|
||||
32'b011100???????????????00000000010 0 1 RD 0 0 // MUL
|
||||
32'b100000?????????????????????????? 0 1 RT 1 ? // LB
|
||||
32'b100001?????????????????????????? 0 1 RT 1 ? // LH
|
||||
32'h100010?????????????????????????? 0 1 RT 1 ? // LWL
|
||||
32'b100011?????????????????????????? 0 1 RT 1 ? // LW
|
||||
32'b100100?????????????????????????? 0 1 RT 1 ? // LBU
|
||||
32'b100101?????????????????????????? 0 1 RT 1 ? // LHU
|
||||
32'h100110?????????????????????????? 0 1 RT 1 ? // LWR
|
||||
32'b101000?????????????????????????? 0 0 ? ? ? // SB
|
||||
32'b101001?????????????????????????? 0 0 ? ? ? // SH
|
||||
32'b101010?????????????????????????? 0 0 ? ? ? // SWL
|
||||
32'b101011?????????????????????????? 0 0 ? ? ? // SW
|
||||
32'b101110?????????????????????????? 0 0 ? ? ? // SWR
|
||||
32'b101111?????????????????????????? 0 0 ? ? ? // CACHE
|
||||
32'b110011?????????????????????????? 0 0 ? ? ? // PREF (NOP)
|
||||
////-------------------------------- RW RD RD1 RD0
|
||||
32'b000000000000000000000?????001111 0 ? ? ? // SYNC (NOP)
|
||||
32'b00000000000???????????????000000 1 RD 0 0 // SLL
|
||||
32'b00000000000???????????????000010 1 RD 0 0 // SRL
|
||||
32'b00000000000???????????????000011 1 RD 0 0 // SRA
|
||||
32'b000000???????????????00000000100 1 RD 0 0 // SLLV
|
||||
32'b000000???????????????00000000110 1 RD 0 0 // SRLV
|
||||
32'b000000???????????????00000000111 1 RD 0 0 // SRAV
|
||||
32'b000000???????????????00000001010 1 RD 0 0 // MOVZ
|
||||
32'b000000???????????????00000001011 1 RD 0 0 // MOVN
|
||||
32'b000000?????000000000000000001000 0 ? ? ? // JR
|
||||
32'b000000?????00000?????00000001001 1 RD 0 0 // JALR
|
||||
32'b000000????????????????????001100 0 ? ? ? // SYSCALL
|
||||
32'b000000????????????????????001101 0 ? ? ? // BREAK
|
||||
32'b0000000000000000?????00000010000 1 RD 0 0 // MFHI
|
||||
32'b000000?????000000000000000010001 0 ? ? ? // MTHI
|
||||
32'b0000000000000000?????00000010010 1 RD 0 0 // MFLO
|
||||
32'b000000?????000000000000000010011 0 ? ? ? // MTLO
|
||||
32'b000000??????????0000000000011000 0 ? ? ? // MULT
|
||||
32'b000000??????????0000000000011001 0 ? ? ? // MULTU
|
||||
32'b000000??????????0000000000011010 0 ? ? ? // DIV
|
||||
32'b000000??????????0000000000011011 0 ? ? ? // DIVU
|
||||
32'b000000???????????????00000100000 1 RD 0 0 // ADD
|
||||
32'b000000???????????????00000100001 1 RD 0 0 // ADDU
|
||||
32'b000000???????????????00000100010 1 RD 0 0 // SUB
|
||||
32'b000000???????????????00000100011 1 RD 0 0 // SUBU
|
||||
32'b000000???????????????00000100100 1 RD 0 0 // AND
|
||||
32'b000000???????????????00000100101 1 RD 0 0 // OR
|
||||
32'b000000???????????????00000100110 1 RD 0 0 // XOR
|
||||
32'b000000???????????????00000100111 1 RD 0 0 // NOR
|
||||
32'b000000???????????????00000101010 1 RD 0 0 // SLT
|
||||
32'b000000???????????????00000101011 1 RD 0 0 // SLTU
|
||||
32'b000000????????????????????110000 0 ? ? ? // TGE
|
||||
32'b000000????????????????????110001 0 ? ? ? // TGEU
|
||||
32'b000000????????????????????110010 0 ? ? ? // TLT
|
||||
32'b000000????????????????????110011 0 ? ? ? // TLTU
|
||||
32'b000000????????????????????110100 0 ? ? ? // TEQ
|
||||
32'b000000????????????????????110110 0 ? ? ? // TNE
|
||||
32'b000001?????00000???????????????? 0 ? ? ? // BLTZ
|
||||
32'b000001?????00001???????????????? 0 ? ? ? // BGEZ
|
||||
32'b000001?????01000???????????????? 0 ? ? ? // TGEI
|
||||
32'b000001?????01001???????????????? 0 ? ? ? // TGEIU
|
||||
32'b000001?????01010???????????????? 0 ? ? ? // TLTI
|
||||
32'b000001?????01011???????????????? 0 ? ? ? // TLTIU
|
||||
32'b000001?????01110???????????????? 0 ? ? ? // TNEI
|
||||
32'b000001?????01100???????????????? 0 ? ? ? // TEQI
|
||||
32'b000001?????10000???????????????? 1 31 0 1 // BLTZAL
|
||||
32'b000001?????10001???????????????? 1 31 0 1 // BGEZAL
|
||||
32'b000010?????????????????????????? 0 ? ? ? // J
|
||||
32'b000011?????????????????????????? 1 31 0 1 // JAL
|
||||
32'b000100?????????????????????????? 0 ? ? ? // BEQ
|
||||
32'b000101?????????????????????????? 0 ? ? ? // BNE
|
||||
32'b000110?????00000???????????????? 0 ? ? ? // BLEZ
|
||||
32'b000111?????00000???????????????? 0 ? ? ? // BGTZ
|
||||
32'b001000?????????????????????????? 1 RT 1 ? // ADDI
|
||||
32'b001001?????????????????????????? 1 RT 1 ? // ADDIU
|
||||
32'b001010?????????????????????????? 1 RT 1 ? // SLTI
|
||||
32'b001011?????????????????????????? 1 RT 1 ? // SLTIU
|
||||
32'b001100?????????????????????????? 1 RT 1 ? // ANDI
|
||||
32'b001101?????????????????????????? 1 RT 1 ? // ORI
|
||||
32'b001110?????????????????????????? 1 RT 1 ? // XORI
|
||||
32'b00111100000????????????????????? 1 RT 1 ? // LUI
|
||||
32'b01000000000??????????00000000??? 1 RT 1 ? // MFC0
|
||||
32'b01000000100??????????00000000??? 0 ? ? ? // MTC0
|
||||
32'b01000010000000000000000000000001 0 ? ? ? // TLBR
|
||||
32'b01000010000000000000000000000010 0 ? ? ? // TLBWI
|
||||
32'b01000010000000000000000000000110 0 ? ? ? // TLBWR
|
||||
32'b01000010000000000000000000001000 0 ? ? ? // TLBP
|
||||
32'b01000010000000000000000000011000 0 ? ? ? // ERET
|
||||
32'b011100??????????0000000000000000 0 ? ? ? // MADD
|
||||
32'b011100??????????0000000000000001 0 ? ? ? // MADDU
|
||||
32'b011100??????????0000000000000100 0 ? ? ? // MSUB
|
||||
32'b011100??????????0000000000000101 0 ? ? ? // MSUBU
|
||||
32'b011100???????????????00000000010 1 RD 0 0 // MUL
|
||||
32'b100000?????????????????????????? 1 RT 1 ? // LB
|
||||
32'b100001?????????????????????????? 1 RT 1 ? // LH
|
||||
32'b100010?????????????????????????? 1 RT 1 ? // LWL
|
||||
32'b100011?????????????????????????? 1 RT 1 ? // LW
|
||||
32'b100100?????????????????????????? 1 RT 1 ? // LBU
|
||||
32'b100101?????????????????????????? 1 RT 1 ? // LHU
|
||||
32'b100110?????????????????????????? 1 RT 1 ? // LWR
|
||||
32'b101000?????????????????????????? 0 ? ? ? // SB
|
||||
32'b101001?????????????????????????? 0 ? ? ? // SH
|
||||
32'b101010?????????????????????????? 0 ? ? ? // SWL
|
||||
32'b101011?????????????????????????? 0 ? ? ? // SW
|
||||
32'b101110?????????????????????????? 0 ? ? ? // SWR
|
||||
32'b101111?????????????????????????? 0 ? ? ? // CACHE
|
||||
32'b110011?????????????????????????? 0 ? ? ? // PREF (NOP)
|
||||
Loading…
Reference in New Issue
Block a user