4 Commits

Author	SHA1	Message	Date
Paul Pan	02f04a2bf3	Update MU and DCache	2022-08-03 14:26:44 +08:00
Paul Pan	a7793c6741	Another big update ... 1. refactor func test 2. fix CACHE inst 3. CP0 add Context Register 4. fix AXIWriter order	2022-08-01 22:01:24 +08:00
Paul Pan	b25fbb5ee1	fix: multiply model	2022-07-29 18:48:58 +08:00
Paul Pan	7b33e4213a	a big update ... 1. add test soft 2. modify verilator (TODO: crossbar need to replace) 3. fix CP0: now CU0 is always 1 4. Controller: cacheop 5. Controller: fix TEN 6. mycpu_top fix CP0_i 7. fix AXI.sv 8. fix AXIReader.sv 9. fix AXIWriter.sv: getting the correct data and length 10. MU: fix cache writeback, fix mem data mux, fix writer address, fix read request	2022-07-29 18:25:58 +08:00