|
|
966b7b6223
|
add control signals
|
2021-08-31 18:30:03 +08:00 |
|
|
|
0b872c9b7c
|
add sync pref as nop
|
2021-08-30 13:11:40 +08:00 |
|
|
|
1f94aebd9d
|
update control signals for swl/swr
|
2021-08-29 16:47:34 +08:00 |
|
|
|
54c6794a77
|
add LWL and LWR
|
2021-08-26 18:32:55 +08:00 |
|
|
|
1ad35234dc
|
txt add tlbwr
|
2021-08-26 17:04:09 +08:00 |
|
cxy004
|
67ccb57eda
|
RW & RS0 fix
tools update
|
2021-08-18 12:16:28 +08:00 |
|
|
|
22e469ceec
|
1. tlb: add soft
2. datapath OFA fix2
3. datapath C0 hazard
4. MMU buffer
Co-authored-by: cxy004 <cxy004@qq.com>
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
|
2021-08-12 21:38:30 +08:00 |
|
|
|
bc549d8bd4
|
1. tlb control signals
2. exccode rename
3. tlb datapath partial
Co-authored-by: cxy004 <cxy004@qq.com>
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
|
2021-08-11 12:58:02 +08:00 |
|
