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17f64e1f2f
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1. add cache (D-Cache Address) inst
2. fix bug in ALR
3. fix bug in MMU and DCache
4. Register File rst
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2021-09-02 19:20:19 +08:00 |
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f256abd248
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add control signals
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2021-09-02 19:05:23 +08:00 |
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53c0c018bb
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fix bug in decode
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2021-08-31 21:11:59 +08:00 |
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966b7b6223
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add control signals
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2021-08-31 18:30:03 +08:00 |
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0b872c9b7c
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add sync pref as nop
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2021-08-30 13:11:40 +08:00 |
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1f94aebd9d
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update control signals for swl/swr
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2021-08-29 16:47:34 +08:00 |
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54c6794a77
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add LWL and LWR
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2021-08-26 18:32:55 +08:00 |
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8d039f4327
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handle CpU exception
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2021-08-25 20:59:32 +08:00 |
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ba546d1d5f
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add tlbwr datapath
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2021-08-24 16:23:57 +08:00 |
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cxy004
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67ccb57eda
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RW & RS0 fix
tools update
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2021-08-18 12:16:28 +08:00 |
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cxy004
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9ac9b951fa
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decode tools
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2021-08-12 21:40:52 +08:00 |
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