|
|
75a62cfc37
|
try add trap
|
2021-09-22 13:41:09 +08:00 |
|
|
|
29c6e16682
|
try add MOVZ, MOVN
|
2021-09-07 19:24:34 +08:00 |
|
|
|
17f64e1f2f
|
1. add cache (D-Cache Address) inst
2. fix bug in ALR
3. fix bug in MMU and DCache
4. Register File rst
|
2021-09-02 19:20:19 +08:00 |
|
|
|
f256abd248
|
add control signals
|
2021-09-02 19:05:23 +08:00 |
|
|
|
966b7b6223
|
add control signals
|
2021-08-31 18:30:03 +08:00 |
|
|
|
0b872c9b7c
|
add sync pref as nop
|
2021-08-30 13:11:40 +08:00 |
|
|
|
eea7b6bbda
|
add lwl lwr swl swr test cases
|
2021-08-29 20:17:42 +08:00 |
|
|
|
1f94aebd9d
|
update control signals for swl/swr
|
2021-08-29 16:47:34 +08:00 |
|
|
|
54c6794a77
|
add LWL and LWR
|
2021-08-26 18:32:55 +08:00 |
|
|
|
ba546d1d5f
|
add tlbwr datapath
|
2021-08-24 16:23:57 +08:00 |
|
cxy004
|
67ccb57eda
|
RW & RS0 fix
tools update
|
2021-08-18 12:16:28 +08:00 |
|
