[happy]

.vscode/settings.json

@@ -62,5 +62,6 @@
     "cinttypes": "cpp",
     "typeinfo": "cpp",
     "iomanip": "cpp"
-    }
+  },
+  "editor.defaultFormatter": "bmpenuelas.systemverilog-formatter-vscode"
 }

src/Core/Issue.sv

@@ -1,6 +1,6 @@
 `include "sram.svh"
 
-module issue(
+module Issue(
         input  clk, rst,
         sramro_i.master fetch_i);
 

src/testbench/happy/happy.sv

@@ -7,23 +7,48 @@
 module happy ();
   logic clk, rst;
 
-  /* verilator lint_off UNOPTFLAT */
-  integer counter = 0;
-  /* verilator lint_on UNOPTFLAT */
+  wire [31:0] araddr;
+  wire [1:0] arburst;
+  wire [3:0] arid;
+  wire [7:0] arlen;
+  wire arready;
+  wire [2:0] arsize;
+  wire arvalid;
+  wire [31:0] awaddr;
+  wire [1:0] awburst;
+  wire [3:0] awid;
+  wire [7:0] awlen;
+  wire awready;
+  wire [2:0] awsize;
+  wire awvalid;
+  wire [3:0] bid;
+  wire bready;
+  wire [1:0] bresp;
+  wire bvalid;
+  wire [31:0] rdata;
+  wire [3:0] rid;
+  wire rlast;
+  wire rready;
+  wire [1:0] rresp;
+  wire rvalid;
+  wire [31:0] wdata;
+  wire wready;
+  wire [3:0] wstrb;
+  wire wvalid;
 
+  AXIRead_i fake_axi ();
+  sramro_i fake_sram ();
+  HandShake fake_hs ();
 
-  sramro_i fake ();
-  AXIRead_i fakeAR ();
-  HandShake fakeHS ();
   wire [31:0] ICacheAddress;
   wire ICacheLineOK;
   wire [`IC_DATA_LENGTH-1:0] ICacheLine;
 
-  ICache ICache (
+  ICache ic (
       .clk(clk),
       .rst(rst),
-      .sram(fake),
-      .AXIReq(fakeHS),
+      .sram(fake_sram.slave),
+      .AXIReq(fake_hs.next),
       .ICacheAddress(ICacheAddress),
       .ICacheLineOK(ICacheLineOK),
       .ICacheLine(ICacheLine)
@@ -32,29 +57,58 @@ module happy ();
   AXI AXI (
       .clk(clk),
       .rst(rst),
-      .AXIRead(fakeAR),
-      .ICReq(fakeHS),
+      .AXIRead(fake_axi.master),
+      .ICReq(fake_hs.prev),
       .ICacheAddress(ICacheAddress),
       .ICacheLineOK(ICacheLineOK),
       .ICacheLine(ICacheLine)
   );
 
-  initial begin
-    fake.req  = 1;
-    fake.addr = 32'b0100000;
-  end
+  assign fake_axi.AXIReadData.arready = arready;
+  assign fake_axi.AXIReadData.rid = rid;
+  assign fake_axi.AXIReadData.rdata = rdata;
+  assign fake_axi.AXIReadData.rresp = rresp;
+  assign fake_axi.AXIReadData.rlast = rlast;
+  assign fake_axi.AXIReadData.rvalid = rvalid;
 
-  integer i;
-  always_latch begin
-    clk = ~clk;
+  assign arid = fake_axi.AXIReadAddr.arid;
+  assign araddr = fake_axi.AXIReadAddr.araddr;
+  assign arlen[3:0] = fake_axi.AXIReadAddr.arlen;
+  assign arlen[7:4] = 0;
+  assign arsize = fake_axi.AXIReadAddr.arsize;
+  assign arburst = fake_axi.AXIReadAddr.arburst;
+  assign arvalid = fake_axi.AXIReadAddr.arvalid;
+  assign rready = fake_axi.AXIReadAddr.rready;
 
-    fake.addr = fake.addr + 1;
+  Issue issue (
+      .clk(clk),
+      .rst(rst),
+      .fetch_i(fake_sram)
+  );
 
+  HandShake fake_hs1 ();
+  HandShake fake_hs2 ();
+  word_t in1, in2;
+  word_t pin1, pin2;
+  word_t out1, out2;
+  word_t pout1, pout2;
 
-    if (clk == 1'b1) begin
-      counter = counter + 1;
-      if (counter >= 1024) $finish;
-    end
-  end
+  InstrQueue inst_queue (
+      .clk(clk),
+      .rst(rst),
+      .clear(),
+      .HandShake_in1(fake_hs1.prev),
+      .in1(in1),
+      .pin1(pin1),
+      .HandShake_in2(fake_hs2.prev),
+      .in2(in2),
+      .pin2(pin2),
+      .HandShake_out1(fake_hs1.next),
+      .out1(out1),
+      .pout1(pout1),
+      .HandShake_out2(fake_hs2.next),
+      .out2(out2),
+      .pout2(pout2)
+  );
 
 endmodule

src/testbench/happy/iq.sv

@@ -14,7 +14,7 @@ module iqhappy ();
   word_t pout1;
   word_t out2;
   word_t pout2;
-  issue issue (
+  Issue issue (
       .clk(clk),
       .rst(rst),
       .fetch_i(fake)