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[happy]

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This commit is contained in:
Paul Pan 2021-07-14 10:21:49 +08:00
parent 3b02d8670f
commit fd70b53964
4 changed files with 146 additions and 91 deletions
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129
.vscode/settings.json vendored
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@ -1,66 +1,67 @@
{ {
"files.associations": { "files.associations": {
"cctype": "cpp", "cctype": "cpp",
"clocale": "cpp", "clocale": "cpp",
"cmath": "cpp", "cmath": "cpp",
"cstdarg": "cpp", "cstdarg": "cpp",
"cstddef": "cpp", "cstddef": "cpp",
"cstdio": "cpp", "cstdio": "cpp",
"cstdlib": "cpp", "cstdlib": "cpp",
"cstring": "cpp", "cstring": "cpp",
"ctime": "cpp", "ctime": "cpp",
"cwchar": "cpp", "cwchar": "cpp",
"cwctype": "cpp", "cwctype": "cpp",
"array": "cpp", "array": "cpp",
"atomic": "cpp", "atomic": "cpp",
"bit": "cpp", "bit": "cpp",
"*.tcc": "cpp", "*.tcc": "cpp",
"bitset": "cpp", "bitset": "cpp",
"chrono": "cpp", "chrono": "cpp",
"compare": "cpp", "compare": "cpp",
"concepts": "cpp", "concepts": "cpp",
"condition_variable": "cpp", "condition_variable": "cpp",
"cstdint": "cpp", "cstdint": "cpp",
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"list": "cpp", "list": "cpp",
"map": "cpp", "map": "cpp",
"set": "cpp", "set": "cpp",
"string": "cpp", "string": "cpp",
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"unordered_set": "cpp", "unordered_set": "cpp",
"vector": "cpp", "vector": "cpp",
"exception": "cpp", "exception": "cpp",
"algorithm": "cpp", "algorithm": "cpp",
"functional": "cpp", "functional": "cpp",
"iterator": "cpp", "iterator": "cpp",
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"numeric": "cpp", "numeric": "cpp",
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} }

2
src/Core/Issue.sv
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@ -1,6 +1,6 @@
`include "sram.svh" `include "sram.svh"
module issue( module Issue(
input clk, rst, input clk, rst,
sramro_i.master fetch_i); sramro_i.master fetch_i);

102
src/testbench/happy/happy.sv
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@ -7,23 +7,48 @@
module happy (); module happy ();
logic clk, rst; logic clk, rst;
/* verilator lint_off UNOPTFLAT */ wire [31:0] araddr;
integer counter = 0; wire [1:0] arburst;
/* verilator lint_on UNOPTFLAT */ wire [3:0] arid;
wire [7:0] arlen;
wire arready;
wire [2:0] arsize;
wire arvalid;
wire [31:0] awaddr;
wire [1:0] awburst;
wire [3:0] awid;
wire [7:0] awlen;
wire awready;
wire [2:0] awsize;
wire awvalid;
wire [3:0] bid;
wire bready;
wire [1:0] bresp;
wire bvalid;
wire [31:0] rdata;
wire [3:0] rid;
wire rlast;
wire rready;
wire [1:0] rresp;
wire rvalid;
wire [31:0] wdata;
wire wready;
wire [3:0] wstrb;
wire wvalid;
AXIRead_i fake_axi ();
sramro_i fake_sram ();
HandShake fake_hs ();
sramro_i fake ();
AXIRead_i fakeAR ();
HandShake fakeHS ();
wire [31:0] ICacheAddress; wire [31:0] ICacheAddress;
wire ICacheLineOK; wire ICacheLineOK;
wire [`IC_DATA_LENGTH-1:0] ICacheLine; wire [`IC_DATA_LENGTH-1:0] ICacheLine;
ICache ICache ( ICache ic (
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
.sram(fake), .sram(fake_sram.slave),
.AXIReq(fakeHS), .AXIReq(fake_hs.next),
.ICacheAddress(ICacheAddress), .ICacheAddress(ICacheAddress),
.ICacheLineOK(ICacheLineOK), .ICacheLineOK(ICacheLineOK),
.ICacheLine(ICacheLine) .ICacheLine(ICacheLine)
@ -32,29 +57,58 @@ module happy ();
AXI AXI ( AXI AXI (
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
.AXIRead(fakeAR), .AXIRead(fake_axi.master),
.ICReq(fakeHS), .ICReq(fake_hs.prev),
.ICacheAddress(ICacheAddress), .ICacheAddress(ICacheAddress),
.ICacheLineOK(ICacheLineOK), .ICacheLineOK(ICacheLineOK),
.ICacheLine(ICacheLine) .ICacheLine(ICacheLine)
); );
initial begin assign fake_axi.AXIReadData.arready = arready;
fake.req = 1; assign fake_axi.AXIReadData.rid = rid;
fake.addr = 32'b0100000; assign fake_axi.AXIReadData.rdata = rdata;
end assign fake_axi.AXIReadData.rresp = rresp;
assign fake_axi.AXIReadData.rlast = rlast;
assign fake_axi.AXIReadData.rvalid = rvalid;
integer i; assign arid = fake_axi.AXIReadAddr.arid;
always_latch begin assign araddr = fake_axi.AXIReadAddr.araddr;
clk = ~clk; assign arlen[3:0] = fake_axi.AXIReadAddr.arlen;
assign arlen[7:4] = 0;
assign arsize = fake_axi.AXIReadAddr.arsize;
assign arburst = fake_axi.AXIReadAddr.arburst;
assign arvalid = fake_axi.AXIReadAddr.arvalid;
assign rready = fake_axi.AXIReadAddr.rready;
fake.addr = fake.addr + 1; Issue issue (
.clk(clk),
.rst(rst),
.fetch_i(fake_sram)
);
HandShake fake_hs1 ();
HandShake fake_hs2 ();
word_t in1, in2;
word_t pin1, pin2;
word_t out1, out2;
word_t pout1, pout2;
if (clk == 1'b1) begin InstrQueue inst_queue (
counter = counter + 1; .clk(clk),
if (counter >= 1024) $finish; .rst(rst),
end .clear(),
end .HandShake_in1(fake_hs1.prev),
.in1(in1),
.pin1(pin1),
.HandShake_in2(fake_hs2.prev),
.in2(in2),
.pin2(pin2),
.HandShake_out1(fake_hs1.next),
.out1(out1),
.pout1(pout1),
.HandShake_out2(fake_hs2.next),
.out2(out2),
.pout2(pout2)
);
endmodule endmodule

2
src/testbench/happy/iq.sv
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@ -14,7 +14,7 @@ module iqhappy ();
word_t pout1; word_t pout1;
word_t out2; word_t out2;
word_t pout2; word_t pout2;
issue issue ( Issue issue (
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
.fetch_i(fake) .fetch_i(fake)