[happy]
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.vscode/settings.json
vendored
3
.vscode/settings.json
vendored
@ -62,5 +62,6 @@
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"cinttypes": "cpp",
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"cinttypes": "cpp",
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"typeinfo": "cpp",
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"typeinfo": "cpp",
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"iomanip": "cpp"
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"iomanip": "cpp"
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}
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},
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"editor.defaultFormatter": "bmpenuelas.systemverilog-formatter-vscode"
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}
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}
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@ -1,6 +1,6 @@
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`include "sram.svh"
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`include "sram.svh"
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module issue(
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module Issue(
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input clk, rst,
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input clk, rst,
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sramro_i.master fetch_i);
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sramro_i.master fetch_i);
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@ -7,23 +7,48 @@
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module happy ();
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module happy ();
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logic clk, rst;
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logic clk, rst;
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/* verilator lint_off UNOPTFLAT */
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wire [31:0] araddr;
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integer counter = 0;
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wire [1:0] arburst;
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/* verilator lint_on UNOPTFLAT */
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wire [3:0] arid;
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wire [7:0] arlen;
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wire arready;
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wire [2:0] arsize;
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wire arvalid;
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wire [31:0] awaddr;
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wire [1:0] awburst;
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wire [3:0] awid;
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wire [7:0] awlen;
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wire awready;
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wire [2:0] awsize;
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wire awvalid;
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wire [3:0] bid;
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wire bready;
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wire [1:0] bresp;
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wire bvalid;
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wire [31:0] rdata;
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wire [3:0] rid;
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wire rlast;
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wire rready;
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wire [1:0] rresp;
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wire rvalid;
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wire [31:0] wdata;
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wire wready;
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wire [3:0] wstrb;
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wire wvalid;
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AXIRead_i fake_axi ();
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sramro_i fake_sram ();
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HandShake fake_hs ();
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sramro_i fake ();
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AXIRead_i fakeAR ();
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HandShake fakeHS ();
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wire [31:0] ICacheAddress;
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wire [31:0] ICacheAddress;
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wire ICacheLineOK;
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wire ICacheLineOK;
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wire [`IC_DATA_LENGTH-1:0] ICacheLine;
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wire [`IC_DATA_LENGTH-1:0] ICacheLine;
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ICache ICache (
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ICache ic (
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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.sram(fake),
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.sram(fake_sram.slave),
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.AXIReq(fakeHS),
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.AXIReq(fake_hs.next),
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.ICacheAddress(ICacheAddress),
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.ICacheAddress(ICacheAddress),
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.ICacheLineOK(ICacheLineOK),
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.ICacheLineOK(ICacheLineOK),
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.ICacheLine(ICacheLine)
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.ICacheLine(ICacheLine)
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@ -32,29 +57,58 @@ module happy ();
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AXI AXI (
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AXI AXI (
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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.AXIRead(fakeAR),
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.AXIRead(fake_axi.master),
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.ICReq(fakeHS),
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.ICReq(fake_hs.prev),
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.ICacheAddress(ICacheAddress),
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.ICacheAddress(ICacheAddress),
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.ICacheLineOK(ICacheLineOK),
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.ICacheLineOK(ICacheLineOK),
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.ICacheLine(ICacheLine)
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.ICacheLine(ICacheLine)
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);
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);
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initial begin
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assign fake_axi.AXIReadData.arready = arready;
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fake.req = 1;
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assign fake_axi.AXIReadData.rid = rid;
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fake.addr = 32'b0100000;
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assign fake_axi.AXIReadData.rdata = rdata;
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end
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assign fake_axi.AXIReadData.rresp = rresp;
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assign fake_axi.AXIReadData.rlast = rlast;
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assign fake_axi.AXIReadData.rvalid = rvalid;
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integer i;
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assign arid = fake_axi.AXIReadAddr.arid;
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always_latch begin
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assign araddr = fake_axi.AXIReadAddr.araddr;
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clk = ~clk;
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assign arlen[3:0] = fake_axi.AXIReadAddr.arlen;
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assign arlen[7:4] = 0;
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assign arsize = fake_axi.AXIReadAddr.arsize;
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assign arburst = fake_axi.AXIReadAddr.arburst;
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assign arvalid = fake_axi.AXIReadAddr.arvalid;
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assign rready = fake_axi.AXIReadAddr.rready;
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fake.addr = fake.addr + 1;
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Issue issue (
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.clk(clk),
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.rst(rst),
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.fetch_i(fake_sram)
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);
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HandShake fake_hs1 ();
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HandShake fake_hs2 ();
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word_t in1, in2;
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word_t pin1, pin2;
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word_t out1, out2;
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word_t pout1, pout2;
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if (clk == 1'b1) begin
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InstrQueue inst_queue (
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counter = counter + 1;
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.clk(clk),
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if (counter >= 1024) $finish;
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.rst(rst),
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end
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.clear(),
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end
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.HandShake_in1(fake_hs1.prev),
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.in1(in1),
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.pin1(pin1),
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.HandShake_in2(fake_hs2.prev),
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.in2(in2),
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.pin2(pin2),
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.HandShake_out1(fake_hs1.next),
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.out1(out1),
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.pout1(pout1),
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.HandShake_out2(fake_hs2.next),
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.out2(out2),
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.pout2(pout2)
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);
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endmodule
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endmodule
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@ -14,7 +14,7 @@ module iqhappy ();
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word_t pout1;
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word_t pout1;
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word_t out2;
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word_t out2;
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word_t pout2;
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word_t pout2;
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issue issue (
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Issue issue (
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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.fetch_i(fake)
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.fetch_i(fake)
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