From fd39e833f228a6509c3b802d5c1df71d7a4dc818 Mon Sep 17 00:00:00 2001
From: Hooo1941 <jiahao1941@outlook.com>
Date: Tue, 6 Jul 2021 12:16:15 +0800
Subject: [PATCH] [CP0] bugfix & config

---
 src/CP0/CP0.sv      | 38 +++++++++++++++++++++++---------------
 src/include/CP0.svh | 18 ++++++++++++++----
 2 files changed, 37 insertions(+), 19 deletions(-)

diff --git a/src/CP0/CP0.sv b/src/CP0/CP0.sv
index 22ea6ac..4c91d88 100644
--- a/src/CP0/CP0.sv
+++ b/src/CP0/CP0.sv
@@ -1,5 +1,8 @@
 `include "constants.svh"
 `include "CP0.svh"
+
+// TODO: Config1 reg
+
 module CP0 (
     input logic clk,
     input logic rst,
@@ -8,38 +11,37 @@ module CP0 (
     input logic en,
     input logic [4:0] waddr,
     output logic [31:0] wdata,
+
     // exception
     input EXCEPTION_t exception,
     input logic ERET,
     output logic [31:0] EPC,
     output logic [31:0] Status,
-    output logic [31:0] Cause
+    output logic [31:0] Cause,
+
+    output logic [2:0] K0
 );
 
   CP0_REGS_t rf_cp0;
   integer i;
   reg count_lo;
-  initial begin
-    count_lo = 0;
-    rf_cp0   = {617'b0, 1'b1, 406'b0};
-  end
   always_ff @(posedge rst or posedge clk)
     if (rst) begin
-      rf_cp0   = {617'b0, 1'b1, 406'b0};
+      rf_cp0   = {504'b0, 8'b10000010, 105'b0, 1'b1, 406'b0};
       count_lo = 0;
     end else if (clk) begin
-      if (ERET)
-        rf_cp0.Status.EXL = 1'b0;
+      if (ERET) rf_cp0.Status.EXL = 1'b0;
       if (exception.valid && rf_cp0.Status.EXL == 1'b0) begin
         rf_cp0.Cause.ExcCode = exception.ExcCode;
         rf_cp0.BadVAddr = exception.BadVAddr;
         rf_cp0.Status.EXL = 1'b1;
         if (~rf_cp0.Status.EXL) begin
           rf_cp0.EPC = exception.EPC;
-          if (exception.delay)
+          if (exception.delay) begin
             rf_cp0.Cause.BD = 1'b1;
-          else
-            rf_cp0.Cause.BD = 1'b0;
+            rf_cp0.EPC = rf_cp0.EPC - 4;
+          end
+          else rf_cp0.Cause.BD = 1'b0;
         end
       end
       // count
@@ -63,15 +65,18 @@ module CP0 (
           19: rf_cp0.WatchHi = wdata;
           18: rf_cp0.WatchLo = wdata;
           17: rf_cp0.LLAddr = wdata;
-          16: rf_cp0.Config = wdata;
+          16: rf_cp0.Config[2:0] = wdata[2:0];
           15: rf_cp0.PRId = wdata;
           14: rf_cp0.EPC = wdata;
-          13: rf_cp0.Cause = wdata;
-          12: rf_cp0.Status = wdata;
+          13: rf_cp0.Cause[9:8] = wdata[9:8];
+          12: begin
+            rf_cp0.Status[15:8] = wdata[15:8];
+            rf_cp0.Status[1:0] = wdata[1:0];
+          end
           11: rf_cp0.Compare = wdata;
           10: rf_cp0.EntryHi = wdata;
           9:  rf_cp0.Count = wdata;
-          8:  rf_cp0.BadVAddr = wdata;
+          //8:  rf_cp0.BadVAddr = wdata;
           7:  rf_cp0.HWREna = wdata;
           6:  rf_cp0.Wired = wdata;
           5:  rf_cp0.PageMask = wdata;
@@ -80,6 +85,8 @@ module CP0 (
           2:  rf_cp0.EntryLo0 = wdata;
           1:  rf_cp0.Random = wdata;
           0:  rf_cp0.Index = wdata;
+          default: begin
+          end
         endcase
     end
   always_comb
@@ -120,4 +127,5 @@ module CP0 (
   assign EPC = rf_cp0.EPC;
   assign Status = rf_cp0.Status;
   assign Cause = rf_cp0.Cause;
+  assign K0 = rf_cp0.Config.K0;
 endmodule
diff --git a/src/include/CP0.svh b/src/include/CP0.svh
index 8a65aa5..b22bef4 100644
--- a/src/include/CP0.svh
+++ b/src/include/CP0.svh
@@ -9,6 +9,17 @@ typedef struct packed {
   logic [31:0] EPC;
 } EXCEPTION_t;
 
+typedef struct packed {
+  logic M;
+  logic [14:0] zero;
+  logic BE;
+  logic [1:0] AT;
+  logic [2:0] AR;
+  logic [2:0] MT;
+  logic [3:0] zero1;
+  logic [2:0] K0;
+} CP0_REGS_CONFIG_t;
+
 typedef struct packed {
   logic [8:0] zero1;
   logic Bev;  // Constant 1
@@ -43,11 +54,10 @@ typedef struct packed {
       unused20,
       WatchHi,
       WatchLo,
-      LLAddr,
-      Config,
-      PRId,
-      EPC
+      LLAddr
   ;
+  CP0_REGS_CONFIG_t Config;
+  logic [31:0] PRId, EPC;
   CP0_REGS_CAUSE_t Cause;
   CP0_REGS_STATUS_t Status;
   logic [31:0] Compare,