BIG: fix dcache & fix HLS!!!
This commit is contained in:
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609908595f
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fd36f80bd6
@ -44,7 +44,7 @@ module DCache (
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logic [3:0] hitWay;
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DCData_t cacheLine;
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logic [1:0] victim;
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logic [3:0] victim;
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logic [3:0] wen;
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logic [3:0] replaceWen;
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@ -156,34 +156,39 @@ module DCache (
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assign port.hit = hit;
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assign port.row = cacheLine;
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assign nowLRU = LRU[index];
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// assign nowLRU = LRU[index];
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// ==============================
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// ========== Replace ===========
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// ==============================
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// Choose Victim
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assign victim = tagV[0] == 0 ? 2'b00 :
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tagV[1] == 0 ? 2'b01 :
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tagV[2] == 0 ? 2'b10 :
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tagV[3] == 0 ? 2'b11 :
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nowLRU[0] == 0 & ~tagOut[0].dirty ? 2'b00 :
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nowLRU[1] == 0 & ~tagOut[1].dirty ? 2'b01 :
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nowLRU[2] == 0 & ~tagOut[2].dirty ? 2'b10 :
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nowLRU[3] == 0 & ~tagOut[3].dirty ? 2'b11 :
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nowLRU[0] == 0 ? 2'b00 :
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nowLRU[1] == 0 ? 2'b01 :
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nowLRU[2] == 0 ? 2'b10 :
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nowLRU[3] == 0 ? 2'b11 :
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2'b11;
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assign wen[0] = hit ? hitWay[0] : (victim == 0);
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assign wen[1] = hit ? hitWay[1] : (victim == 1);
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assign wen[2] = hit ? hitWay[2] : (victim == 2);
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assign wen[3] = hit ? hitWay[3] : (victim == 3);
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assign victim = tagV[0] == 0 ? 4'b0001
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: tagV[1] == 0 ? 4'b0010
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: tagV[2] == 0 ? 4'b0100
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: tagV[3] == 0 ? 4'b1000
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: nowLRU[0] == 0 & ~tagOut[0].dirty ? 4'b0001
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: nowLRU[1] == 0 & ~tagOut[1].dirty ? 4'b0010
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: nowLRU[2] == 0 & ~tagOut[2].dirty ? 4'b0100
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: nowLRU[3] == 0 & ~tagOut[3].dirty ? 4'b1000
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: nowLRU[0] == 0 ? 4'b0001
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: nowLRU[1] == 0 ? 4'b0010
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: nowLRU[2] == 0 ? 4'b0100
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: 4'b1000;
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assign wen = hit ? hitWay : victim;
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assign port.dirt_valid = (state == LOOKUP) & tagV[victim] & tagOut[victim].dirty;
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assign port.dirt_addr = {tagOut[victim].tag, index, 4'b0};
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assign port.dirt_data = dataOut[victim];
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assign port.dirt_valid = (state == LOOKUP)
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& |{tagV & {tagOut[3].dirty, tagOut[2].dirty, tagOut[1].dirty, tagOut[0].dirty} & victim};
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assign port.dirt_addr = {
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(victim[0] ? tagOut[0].tag : {(32-`DC_TAGL){1'b0}})
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| (victim[1] ? tagOut[1].tag : {(32-`DC_TAGL){1'b0}})
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| (victim[2] ? tagOut[2].tag : {(32-`DC_TAGL){1'b0}})
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| (victim[3] ? tagOut[3].tag : {(32-`DC_TAGL){1'b0}}),
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index, 4'b0};
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assign port.dirt_data = (victim[0] ? dataOut[0] : `DC_DATA_LENGTH'b0)
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| (victim[1] ? dataOut[1] : `DC_DATA_LENGTH'b0)
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| (victim[2] ? dataOut[2] : `DC_DATA_LENGTH'b0)
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| (victim[3] ? dataOut[3] : `DC_DATA_LENGTH'b0);
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// Update LRU
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always_comb begin
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@ -213,8 +218,12 @@ module DCache (
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always_ff @(posedge clk) begin
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if (rst) begin
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for (integer i = 0; i < 64; i++) LRU[i] <= 4'b0;
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end else if (state == LOOKUP) LRU[index] <= nextLRU;
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for (integer i = 0; i < 128; i++) LRU[i] <= 4'b0;
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nowLRU = 4'b0;
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end else begin
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if (state == LOOKUP) LRU[index] = nextLRU;
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nowLRU = LRU[port.addr[`DC_TAGL-1:`DC_INDEXL]];
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end
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end
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// ==============================
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@ -33,6 +33,7 @@ module Controller (
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~inst[27] & (~inst[26] & inst[28] & eq | inst[26] & (~inst[28] & (inst[16] & ~ltz | ~inst[16] & ltz) | inst[28] & ~eq)) | inst[27] & (~inst[28] | (~inst[26] & (eq | ltz) | inst[26] & ~eq & ~ltz))
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});
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assign ctrl.BJRJ = ~inst[29] & (~inst[31] & (~inst[30] & ~inst[5] & ~inst[4] & inst[3] & ~inst[2] | inst[28] | inst[26]) | inst[27] & ~inst[26]);
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assign ctrl.JR = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[5] & ~inst[4] & inst[3] & ~inst[2];
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assign ctrl.SYSCALL = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[3] & inst[2] & ~inst[0];
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assign ctrl.BREAK = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[3] & inst[2] & inst[0];
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@ -62,7 +63,7 @@ module Controller (
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assign ctrl.MCtrl0.HW = ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[4] & (inst[3] | ~inst[1] & inst[0]);
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assign ctrl.MCtrl0.LW = ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[4] & (inst[3] | inst[1] & inst[0]);
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assign ctrl.MCtrl0.HLS = HLS_t'({~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & (~inst[4] | inst[3]), inst[1:0]});
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assign ctrl.MCtrl0.HLS = HLS_t'({~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[4] & inst[3], inst[1:0]});
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assign ctrl.MCtrl0.C0D = inst[15:11];
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assign ctrl.MCtrl0.C0W = inst[30] & inst[23];
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assign ctrl.MCtrl0.RS0 = RS0_t'({inst[29] | inst[26] | ~inst[4], inst[30] | ~inst[29] & ~inst[26] & inst[4] & ~inst[1]});
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@ -226,8 +226,8 @@ module Datapath (
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assign PF_pcp8 = {F.pc[31:3] + 1'b1, 3'b0};
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assign PF_pcb = {D.IB_pc[31:2] + {{14{D.IA_inst[15]}}, D.IA_inst[15:0]}, 2'b0};
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assign PF_pcj = {D.IB_pc[31:28], D.IA_inst[25:0], 2'b0};
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assign PF_pcjr = D_IA_ForwardS;
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assign PF_pcj = {D.IB_pc[31:28], D.IA_inst[25:0], 2'b0};
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mux4 #(32) PF_pc0_mux (
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PF_pcp8,
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PF_pcb,
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@ -249,7 +249,8 @@ module Datapath (
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assign rstD = D_IA_valid & D.IA.BJRJ & D.IA.PCS != PCP8 & D_IB_valid & D_readygo;
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assign rstM = C0_exception.ExcValid;
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assign PF_go = ~D.IA_ExcValid & ~D.IB_ExcValid & ~E_I0_ExcValidWithoutOF & ~E_I1_ExcValidWithoutOF & PF.pc[1:0] == 2'b00;
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assign PF_go = ~D.IA_ExcValid & ~D.IB_ExcValid & ~E_I0_ExcValidWithoutOF & ~E_I1_ExcValidWithoutOF
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& (~D_IB_valid | ~D.IA.JR | PF_pcjr[1:0] == 2'b00);
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assign fetch_i.req = ~F_valid | M_exception.ExcValid
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| PF_go & (~D_IB_valid & ~IQ_valids[0] | (~D.IA.BJRJ | D_readygo)
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& (rstD
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@ -893,7 +894,7 @@ module Datapath (
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ffenr #(6) M_I0_MULT_CNTR_ff (
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clk,
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rst | rstM,
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{E.I0.MCtrl.HLS[2:1] == 2'b10 & E_go & E_I0_go & M.en, M_I0_MULT_CNTR[5:1]},
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{E.I0.MCtrl.HLS[2:1] == 2'b10 & E_go & M.en, M_I0_MULT_CNTR[5:1]},
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1'b1,
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M_I0_MULT_CNTR
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);
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@ -110,6 +110,7 @@ typedef struct packed {
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PCS_t PCS;
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logic BJRJ;
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logic JR;
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logic DP0;
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logic DP1;
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logic DS;
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116
tools/ctrl.txt
116
tools/ctrl.txt
@ -1,58 +1,58 @@
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////-------------------------------- ERET SYSCALL BREAK PCS BJRJ BJR BE DP0 DP1 UI IX SA SB OP ALT OFA MR MWR MX RD RW RS0 HW LW C0W HLS
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32'b00000000000???????????????000000 0 0 0 ? 0 0 0 1 1 ? ? SA RT SL 0 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b00000000000???????????????000010 0 0 0 ? 0 0 0 1 1 ? ? SA RT SR 0 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b00000000000???????????????000011 0 0 0 ? 0 0 0 1 1 ? ? SA RT SR 1 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000000???????????????00000000100 0 0 0 ? 0 0 0 1 1 ? ? RS RT SL ? 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000000???????????????00000000110 0 0 0 ? 0 0 0 1 1 ? ? RS RT SR 0 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000000???????????????00000000111 0 0 0 ? 0 0 0 1 1 ? ? RS RT SR 1 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000000?????000000000000000001000 0 0 0 JR 1 1 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ?
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32'b000000?????00000?????00000001001 0 0 0 JR 1 1 0 1 1 ? ? PC 8 ADD 0 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000000????????????????????001100 0 1 0 ? 0 0 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ?
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32'b000000????????????????????001101 0 0 1 ? 0 0 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ?
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32'b0000000000000000?????00000010000 0 0 0 ? 0 0 0 1 0 ? ? PC 8 ? ? 0 ? ? ? RD 1 HI 0 0 0 ?
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32'b000000?????000000000000000010001 0 0 0 ? 0 0 0 1 0 ? ? PC 8 ? ? 0 ? ? ? ? 0 ? 1 0 0 RS
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32'b0000000000000000?????00000010010 0 0 0 ? 0 0 0 1 0 ? ? PC 8 ? ? 0 ? ? ? RD 1 LO 0 0 0 ?
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32'b000000?????000000000000000010011 0 0 0 ? 0 0 0 1 0 ? ? PC 8 ? ? 0 ? ? ? ? 0 ? 0 1 0 RS
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32'b000000??????????0000000000011000 0 0 0 ? 0 0 0 1 0 ? ? RS RT ? ? 0 ? ? ? ? 0 ? 1 1 0 MULT
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32'b000000??????????0000000000011001 0 0 0 ? 0 0 0 1 0 ? ? RS RT ? ? 0 ? ? ? ? 0 ? 1 1 0 MULTU
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32'b000000??????????0000000000011010 0 0 0 ? 0 0 0 1 0 ? ? RS RT ? ? 0 ? ? ? ? 0 ? 1 1 0 DIV
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32'b000000??????????0000000000011011 0 0 0 ? 0 0 0 1 0 ? ? RS RT ? ? 0 ? ? ? ? 0 ? 1 1 0 DIVU
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32'b000000???????????????00000100000 0 0 0 ? 0 0 0 1 1 ? ? RS RT ADD 0 1 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000000???????????????00000100001 0 0 0 ? 0 0 0 1 1 ? ? RS RT ADD 0 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000000???????????????00000100010 0 0 0 ? 0 0 0 1 1 ? ? RS RT ADD 1 1 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000000???????????????00000100011 0 0 0 ? 0 0 0 1 1 ? ? RS RT ADD 1 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000000???????????????00000100100 0 0 0 ? 0 0 0 1 1 ? ? RS RT AND ? 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000000???????????????00000100101 0 0 0 ? 0 0 0 1 1 ? ? RS RT OR 0 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000000???????????????00000100110 0 0 0 ? 0 0 0 1 1 ? ? RS RT XOR ? 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000000???????????????00000100111 0 0 0 ? 0 0 0 1 1 ? ? RS RT OR 1 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000000???????????????00000101010 0 0 0 ? 0 0 0 1 1 ? ? RS RT SLT 1 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000000???????????????00000101011 0 0 0 ? 0 0 0 1 1 ? ? RS RT SLTU 1 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000001?????00000???????????????? 0 0 0 B 1 1 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ?
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32'b000001?????10000???????????????? 0 0 0 B 1 1 0 1 1 ? ? PC 8 ADD 0 0 0 ? ? 31 1 ALUOut 0 0 0 ?
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32'b000001?????00001???????????????? 0 0 0 B 1 1 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ?
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32'b000001?????10001???????????????? 0 0 0 B 1 1 0 1 1 ? ? PC 8 ADD 0 0 0 ? ? 31 1 ALUOut 0 0 0 ?
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32'b000010?????????????????????????? 0 0 0 J 1 0 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ?
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32'b000011?????????????????????????? 0 0 0 J 1 0 0 1 1 ? ? PC 8 ADD 0 0 0 ? ? 31 1 ALUOut 0 0 0 ?
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32'b000100?????????????????????????? 0 0 0 B 1 1 1 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ?
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32'b000101?????????????????????????? 0 0 0 B 1 1 1 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ?
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32'b000110?????00000???????????????? 0 0 0 B 1 1 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ?
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32'b000111?????00000???????????????? 0 0 0 B 1 1 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ?
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32'b001000?????????????????????????? 0 0 0 ? 0 0 0 1 1 0 1 RS IMM ADD 0 1 0 ? ? RT 1 ALUOut 0 0 0 ?
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32'b001001?????????????????????????? 0 0 0 ? 0 0 0 1 1 0 1 RS IMM ADD 0 0 0 ? ? RT 1 ALUOut 0 0 0 ?
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32'b001010?????????????????????????? 0 0 0 ? 0 0 0 1 1 0 1 RS IMM SLT 1 0 0 ? ? RT 1 ALUOut 0 0 0 ?
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32'b001011?????????????????????????? 0 0 0 ? 0 0 0 1 1 0 1 RS IMM SLTU 1 0 0 ? ? RT 1 ALUOut 0 0 0 ?
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32'b001100?????????????????????????? 0 0 0 ? 0 0 0 1 1 0 0 RS IMM AND ? 0 0 ? ? RT 1 ALUOut 0 0 0 ?
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32'b001101?????????????????????????? 0 0 0 ? 0 0 0 1 1 0 0 RS IMM OR 0 0 0 ? ? RT 1 ALUOut 0 0 0 ?
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32'b001110?????????????????????????? 0 0 0 ? 0 0 0 1 1 0 0 RS IMM XOR ? 0 0 ? ? RT 1 ALUOut 0 0 0 ?
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32'b00111100000????????????????????? 0 0 0 ? 0 0 0 1 1 1 ? 0 IMM ADD 0 0 0 ? ? RT 1 ALUOut 0 0 0 ?
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32'b01000000000??????????00000000??? 0 0 0 ? 0 0 0 1 0 ? ? 0 IMM ? ? 0 ? ? ? RT 1 C0 0 0 0 ?
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32'b01000000100??????????00000000??? 0 0 0 ? 0 0 0 1 0 ? ? 0 IMM ? ? 0 ? ? ? ? 0 ? 0 0 1 ?
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32'b01000010000000000000000000011000 1 0 0 ? 0 0 0 1 1 ? ? 0 IMM ? ? 0 0 ? ? ? 0 ? 0 0 0 ?
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32'b100000?????????????????????????? 0 0 0 ? 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 0 1 RT 1 ? ? ? ? ?
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32'b100001?????????????????????????? 0 0 0 ? 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 0 1 RT 1 ? ? ? ? ?
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32'b100011?????????????????????????? 0 0 0 ? 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 0 ? RT 1 ? ? ? ? ?
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32'b100100?????????????????????????? 0 0 0 ? 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 0 0 RT 1 ? ? ? ? ?
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32'b100101?????????????????????????? 0 0 0 ? 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 0 0 RT 1 ? ? ? ? ?
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32'b101000?????????????????????????? 0 0 0 ? 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 1 ? ? 0 ? ? ? ? ?
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32'b101001?????????????????????????? 0 0 0 ? 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 1 ? ? 0 ? ? ? ? ?
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32'b101011?????????????????????????? 0 0 0 ? 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 1 ? ? 0 ? ? ? ? ?
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////-------------------------------- ERET SYSCALL BREAK PCS BJRJ JR BJR BE DP0 DP1 UI IX SA SB OP ALT OFA MR MWR MX RD RW RS0 HW LW C0W HLS
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32'b00000000000???????????????000000 0 0 0 ? 0 0 0 0 1 1 ? ? SA RT SL 0 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b00000000000???????????????000010 0 0 0 ? 0 0 0 0 1 1 ? ? SA RT SR 0 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b00000000000???????????????000011 0 0 0 ? 0 0 0 0 1 1 ? ? SA RT SR 1 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000000???????????????00000000100 0 0 0 ? 0 0 0 0 1 1 ? ? RS RT SL ? 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000000???????????????00000000110 0 0 0 ? 0 0 0 0 1 1 ? ? RS RT SR 0 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000000???????????????00000000111 0 0 0 ? 0 0 0 0 1 1 ? ? RS RT SR 1 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000000?????000000000000000001000 0 0 0 JR 1 1 1 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ?
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32'b000000?????00000?????00000001001 0 0 0 JR 1 1 1 0 1 1 ? ? PC 8 ADD 0 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000000????????????????????001100 0 1 0 ? 0 0 0 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ?
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32'b000000????????????????????001101 0 0 1 ? 0 0 0 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ?
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32'b0000000000000000?????00000010000 0 0 0 ? 0 0 0 0 1 0 ? ? PC 8 ? ? 0 ? ? ? RD 1 HI 0 0 0 ?
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32'b000000?????000000000000000010001 0 0 0 ? 0 0 0 0 1 0 ? ? PC 8 ? ? 0 ? ? ? ? 0 ? 1 0 0 RS
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32'b0000000000000000?????00000010010 0 0 0 ? 0 0 0 0 1 0 ? ? PC 8 ? ? 0 ? ? ? RD 1 LO 0 0 0 ?
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32'b000000?????000000000000000010011 0 0 0 ? 0 0 0 0 1 0 ? ? PC 8 ? ? 0 ? ? ? ? 0 ? 0 1 0 RS
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32'b000000??????????0000000000011000 0 0 0 ? 0 0 0 0 1 0 ? ? RS RT ? ? 0 ? ? ? ? 0 ? 1 1 0 MULT
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32'b000000??????????0000000000011001 0 0 0 ? 0 0 0 0 1 0 ? ? RS RT ? ? 0 ? ? ? ? 0 ? 1 1 0 MULTU
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32'b000000??????????0000000000011010 0 0 0 ? 0 0 0 0 1 0 ? ? RS RT ? ? 0 ? ? ? ? 0 ? 1 1 0 DIV
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32'b000000??????????0000000000011011 0 0 0 ? 0 0 0 0 1 0 ? ? RS RT ? ? 0 ? ? ? ? 0 ? 1 1 0 DIVU
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32'b000000???????????????00000100000 0 0 0 ? 0 0 0 0 1 1 ? ? RS RT ADD 0 1 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000000???????????????00000100001 0 0 0 ? 0 0 0 0 1 1 ? ? RS RT ADD 0 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000000???????????????00000100010 0 0 0 ? 0 0 0 0 1 1 ? ? RS RT ADD 1 1 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000000???????????????00000100011 0 0 0 ? 0 0 0 0 1 1 ? ? RS RT ADD 1 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000000???????????????00000100100 0 0 0 ? 0 0 0 0 1 1 ? ? RS RT AND ? 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000000???????????????00000100101 0 0 0 ? 0 0 0 0 1 1 ? ? RS RT OR 0 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000000???????????????00000100110 0 0 0 ? 0 0 0 0 1 1 ? ? RS RT XOR ? 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000000???????????????00000100111 0 0 0 ? 0 0 0 0 1 1 ? ? RS RT OR 1 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000000???????????????00000101010 0 0 0 ? 0 0 0 0 1 1 ? ? RS RT SLT 1 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000000???????????????00000101011 0 0 0 ? 0 0 0 0 1 1 ? ? RS RT SLTU 1 0 0 ? ? RD 1 ALUOut 0 0 0 ?
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32'b000001?????00000???????????????? 0 0 0 B 1 0 1 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ?
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32'b000001?????10000???????????????? 0 0 0 B 1 0 1 0 1 1 ? ? PC 8 ADD 0 0 0 ? ? 31 1 ALUOut 0 0 0 ?
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32'b000001?????00001???????????????? 0 0 0 B 1 0 1 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ?
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32'b000001?????10001???????????????? 0 0 0 B 1 0 1 0 1 1 ? ? PC 8 ADD 0 0 0 ? ? 31 1 ALUOut 0 0 0 ?
|
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32'b000010?????????????????????????? 0 0 0 J 1 0 0 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ?
|
||||
32'b000011?????????????????????????? 0 0 0 J 1 0 0 0 1 1 ? ? PC 8 ADD 0 0 0 ? ? 31 1 ALUOut 0 0 0 ?
|
||||
32'b000100?????????????????????????? 0 0 0 B 1 0 1 1 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ?
|
||||
32'b000101?????????????????????????? 0 0 0 B 1 0 1 1 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ?
|
||||
32'b000110?????00000???????????????? 0 0 0 B 1 0 1 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ?
|
||||
32'b000111?????00000???????????????? 0 0 0 B 1 0 1 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ?
|
||||
32'b001000?????????????????????????? 0 0 0 ? 0 0 0 0 1 1 0 1 RS IMM ADD 0 1 0 ? ? RT 1 ALUOut 0 0 0 ?
|
||||
32'b001001?????????????????????????? 0 0 0 ? 0 0 0 0 1 1 0 1 RS IMM ADD 0 0 0 ? ? RT 1 ALUOut 0 0 0 ?
|
||||
32'b001010?????????????????????????? 0 0 0 ? 0 0 0 0 1 1 0 1 RS IMM SLT 1 0 0 ? ? RT 1 ALUOut 0 0 0 ?
|
||||
32'b001011?????????????????????????? 0 0 0 ? 0 0 0 0 1 1 0 1 RS IMM SLTU 1 0 0 ? ? RT 1 ALUOut 0 0 0 ?
|
||||
32'b001100?????????????????????????? 0 0 0 ? 0 0 0 0 1 1 0 0 RS IMM AND ? 0 0 ? ? RT 1 ALUOut 0 0 0 ?
|
||||
32'b001101?????????????????????????? 0 0 0 ? 0 0 0 0 1 1 0 0 RS IMM OR 0 0 0 ? ? RT 1 ALUOut 0 0 0 ?
|
||||
32'b001110?????????????????????????? 0 0 0 ? 0 0 0 0 1 1 0 0 RS IMM XOR ? 0 0 ? ? RT 1 ALUOut 0 0 0 ?
|
||||
32'b00111100000????????????????????? 0 0 0 ? 0 0 0 0 1 1 1 ? 0 IMM ADD 0 0 0 ? ? RT 1 ALUOut 0 0 0 ?
|
||||
32'b01000000000??????????00000000??? 0 0 0 ? 0 0 0 0 1 0 ? ? 0 IMM ? ? 0 ? ? ? RT 1 C0 0 0 0 ?
|
||||
32'b01000000100??????????00000000??? 0 0 0 ? 0 0 0 0 1 0 ? ? 0 IMM ? ? 0 ? ? ? ? 0 ? 0 0 1 ?
|
||||
32'b01000010000000000000000000011000 1 0 0 ? 0 0 0 0 1 1 ? ? 0 IMM ? ? 0 0 ? ? ? 0 ? 0 0 0 ?
|
||||
32'b100000?????????????????????????? 0 0 0 ? 0 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 0 1 RT 1 ? ? ? ? ?
|
||||
32'b100001?????????????????????????? 0 0 0 ? 0 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 0 1 RT 1 ? ? ? ? ?
|
||||
32'b100011?????????????????????????? 0 0 0 ? 0 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 0 ? RT 1 ? ? ? ? ?
|
||||
32'b100100?????????????????????????? 0 0 0 ? 0 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 0 0 RT 1 ? ? ? ? ?
|
||||
32'b100101?????????????????????????? 0 0 0 ? 0 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 0 0 RT 1 ? ? ? ? ?
|
||||
32'b101000?????????????????????????? 0 0 0 ? 0 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 1 ? ? 0 ? ? ? ? ?
|
||||
32'b101001?????????????????????????? 0 0 0 ? 0 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 1 ? ? 0 ? ? ? ? ?
|
||||
32'b101011?????????????????????????? 0 0 0 ? 0 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 1 ? ? 0 ? ? ? ? ?
|
||||
|
||||
Loading…
Reference in New Issue
Block a user