NSCSCC/MIPS
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Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
Co-authored-by: cxy004 <cxy004@qq.com>
This commit is contained in:
Paul Pan 2021-08-15 11:25:08 +08:00
parent 997f34c7e7
commit f8f732bb70
2 changed files with 8 additions and 7 deletions
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1
src/CP0/CP0.sv
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@ -41,6 +41,7 @@ module CP0 (
// int comb logic
assign interrupt = (rf_cp0.Status.EXL == 1'b0)
& ~rf_cp0.Status.IE
& |{rf_cp0.Cause.IP & rf_cp0.Status.IM,
rf_cp0.Cause.TI & rf_cp0.Status.IM[7]};

14
src/Core/Gadgets.sv
View File

@ -80,13 +80,13 @@ module instr_valid (
32'b101000??????????????????????????: valid = 1'b1; // SB
32'b101001??????????????????????????: valid = 1'b1; // SH
32'b101011??????????????????????????: valid = 1'b1; // SW
32'b101111?????00000????????????????: valid = 1'b1; // I-Cache Index Invalid
32'b101111?????01000????????????????: valid = 1'b1; // I-Cache Index Store Tag
32'b101111?????10000????????????????: valid = 1'b1; // I-Cache Hit Invalid
32'b101111?????00001????????????????: valid = 1'b1; // D-Cache Index Writeback Invalid
32'b101111?????01001????????????????: valid = 1'b1; // D-Cache Index Store Tag
32'b101111?????10001????????????????: valid = 1'b1; // D-Cache Hit Invalid
32'b101111?????10101????????????????: valid = 1'b1; // D-Cache Hit Writeback Invalid
// 32'b101111?????00000????????????????: valid = 1'b1; // I-Cache Index Invalid
// 32'b101111?????01000????????????????: valid = 1'b1; // I-Cache Index Store Tag
// 32'b101111?????10000????????????????: valid = 1'b1; // I-Cache Hit Invalid
// 32'b101111?????00001????????????????: valid = 1'b1; // D-Cache Index Writeback Invalid
// 32'b101111?????01001????????????????: valid = 1'b1; // D-Cache Index Store Tag
// 32'b101111?????10001????????????????: valid = 1'b1; // D-Cache Hit Invalid
// 32'b101111?????10101????????????????: valid = 1'b1; // D-Cache Hit Writeback Invalid
default: valid = 1'b0;
endcase
endmodule