diff --git a/.gitignore b/.gitignore index c3699a9..29972c4 100644 --- a/.gitignore +++ b/.gitignore @@ -1,4 +1,5 @@ vivado.log vivado.jou .library_mapping.xml -.project \ No newline at end of file +.project +.settings \ No newline at end of file diff --git a/src/CP0/CP0.sv b/src/CP0/CP0.sv index b90fa61..a604771 100644 --- a/src/CP0/CP0.sv +++ b/src/CP0/CP0.sv @@ -26,18 +26,16 @@ module CP0 ( output logic [2:0] K0, output Index_t Index, output EntryHi_t EntryHi, - output PageMask_t PageMask, output EntryLo_t EntryLo1, output EntryLo_t EntryLo0, input EntryHi_t tlb_EntryHi, - input PageMask_t tlb_PageMask, input EntryLo_t tlb_EntryLo1, input EntryLo_t tlb_EntryLo0, input Index_t tlb_Index ); CP0_REGS_t rf_cp0; - reg count_lo; + logic count_lo; // int comb logic assign interrupt = (rf_cp0.Status.EXL == 1'b0) @@ -61,13 +59,24 @@ module CP0 ( assign rf_cp0.Status.zero2 = 6'b0; assign rf_cp0.Status.zero3 = 6'b0; assign rf_cp0.EntryHi.zero = 5'b0; - assign rf_cp0.PageMask.zero1 = 7'b0; - assign rf_cp0.PageMask.zero2 = 13'b0; + assign rf_cp0.Wired.zero = 29'b0; assign rf_cp0.EntryLo1.zero = 6'b0; assign rf_cp0.EntryLo0.zero = 6'b0; - assign rf_cp0.Index.zero = 29'b0; + assign rf_cp0.Random.zero = 29'b0; + assign rf_cp0.Index.zero = 28'b0; - assign rf_cp0.Config1 = 32'b0_000011_000_100_011_001_011_011_0000000; + // Vol III Figure 9-1 + // | 31 | 30...25 | 24...22 | 21...19 | 18...16 | + // | Config2 | MMU SIZE | iCache sets per way | iCache line size | iCache associativity | + // | 15...13 | 12...10 | 9...7 | + // | dCache sets per way | dCache line size | dCache associativity | + // | 6 | 5 | 4 | + // | Coprocessor 2 implemented | MD | Performance Counter registers | + // | 3 | 2 | + // | Watch registers implemented | Code compression implemented | + // | 1 | 0 | + // | EJTAG implemented | FPU implemented | + assign rf_cp0.Config1 = 32'b0_000111_000_100_011_001_011_011_0_0_0_0_0_0_0; assign rf_cp0.EBase.one = 1'b1; assign rf_cp0.EBase.zero1 = 1'b0; assign rf_cp0.EBase.zero2 = 2'b0; @@ -76,7 +85,6 @@ module CP0 ( always_ff @(posedge clk) if (rst) begin - // rf_cp0 = {504'b0, 8'b10000011, 105'b0, 1'b1, 117'b0, 1'b1, 288'b0}; rf_cp0.TagLo.Tag = 21'b0; rf_cp0.TagLo.D = 1'b0; rf_cp0.TagLo.V = 1'b0; @@ -95,7 +103,7 @@ module CP0 ( rf_cp0.EntryHi.ASID = 8'b0; rf_cp0.Count = 32'h0; rf_cp0.BadVAddr = 32'h0; - rf_cp0.PageMask.Mask = 12'b0; + rf_cp0.Wired.Wired = 3'b0; rf_cp0.EntryLo1.PFN = 20'b0; rf_cp0.EntryLo1.C = 3'b0; rf_cp0.EntryLo1.D = 1'b0; @@ -108,6 +116,7 @@ module CP0 ( rf_cp0.EntryLo0.G = 1'b0; rf_cp0.Index.P = 1'b0; rf_cp0.Index.Index = 2'b0; + rf_cp0.Random.Random = 3'b111; rf_cp0.EBase.EBase = 18'b0; @@ -160,8 +169,8 @@ module CP0 ( 9: rf_cp0.Count = wdata; 8: rf_cp0.BadVAddr = wdata; // 7: rf_cp0.HWREna = wdata; - // 6: rf_cp0.Wired = wdata; - 5: rf_cp0.PageMask.Mask = wdata[24:13]; + 6: rf_cp0.Wired = wdata[2:0]; + // 5: rf_cp0.PageMask.Mask = wdata[24:13]; // 4: rf_cp0.Context = wdata; 3: begin rf_cp0.EntryLo1.PFN = wdata[25:6]; @@ -179,7 +188,7 @@ module CP0 ( end // 1: rf_cp0.Random = wdata; 0: begin - rf_cp0.Index.Index = wdata[1:0]; + rf_cp0.Index.Index = wdata[2:0]; end default: begin end @@ -189,7 +198,7 @@ module CP0 ( if (tlbr) begin rf_cp0.EntryHi.VPN2 = tlb_EntryHi.VPN2; rf_cp0.EntryHi.ASID = tlb_EntryHi.ASID; - rf_cp0.PageMask.Mask = tlb_PageMask.Mask; + // rf_cp0.PageMask.Mask = tlb_PageMask.Mask; rf_cp0.EntryLo0.PFN = tlb_EntryLo0.PFN; rf_cp0.EntryLo0.C = tlb_EntryLo0.C; rf_cp0.EntryLo0.D = tlb_EntryLo0.D; @@ -201,11 +210,15 @@ module CP0 ( rf_cp0.EntryLo1.V = tlb_EntryLo1.V; rf_cp0.EntryLo1.G = tlb_EntryLo1.G; end + if (tlbp) begin rf_cp0.Index.P = tlb_Index.P; rf_cp0.Index.Index = tlb_Index.Index; end + rf_cp0.Random.Random = &rf_cp0.Random.Random ? rf_cp0.Wired.Wired + : rf_cp0.Random.Random + 1'b1; + if (rf_cp0.Count == rf_cp0.Compare) rf_cp0.Cause.TI = 1; if (exception.ERET) rf_cp0.Status.EXL = 1'b0; @@ -262,12 +275,13 @@ module CP0 ( 9: rdata = rf_cp0.Count; 8: rdata = rf_cp0.BadVAddr; // 7: rdata = rf_cp0.HWREna; - // 6: rdata = rf_cp0.Wired; - 5: rdata = rf_cp0.PageMask; + 6: rdata = rf_cp0.Wired; + // 5: rdata = rf_cp0.PageMask; + 5: rdata = 32'h0; // 4: rdata = rf_cp0.Context; 3: rdata = rf_cp0.EntryLo1; 2: rdata = rf_cp0.EntryLo0; - // 1: rdata = rf_cp0.Random; + 1: rdata = rf_cp0.Random; 0: rdata = rf_cp0.Index; default: rdata = 32'h0; endcase @@ -279,7 +293,7 @@ module CP0 ( assign K0 = rf_cp0.Config.K0; assign Index = rf_cp0.Index; assign EntryHi = rf_cp0.EntryHi; - assign PageMask = rf_cp0.PageMask; + // assign PageMask = rf_cp0.PageMask; assign EntryLo1 = rf_cp0.EntryLo1; assign EntryLo0 = rf_cp0.EntryLo0; diff --git a/src/MMU/MMU.sv b/src/MMU/MMU.sv index 4495540..2fc208c 100644 --- a/src/MMU/MMU.sv +++ b/src/MMU/MMU.sv @@ -25,11 +25,11 @@ module MMU ( input logic tlbp, // TLBP -> Write CP0 Index input Index_t c0_Index, // TLBR input EntryHi_t c0_EntryHi, // TLBWI + F/M(ASID) - input PageMask_t c0_PageMask, // TLBWI + // input PageMask_t c0_PageMask, // TLBWI input EntryLo_t c0_EntryLo1, // TLBWI input EntryLo_t c0_EntryLo0, // TLBWI output EntryHi_t EntryHi, // TLBR - output PageMask_t PageMask, // TLBR + // output PageMask_t PageMask, // TLBR output EntryLo_t EntryLo1, // TLBR output EntryLo_t EntryLo0, // TLBR output Index_t Index, // TLBP @@ -42,6 +42,49 @@ module MMU ( output logic dTLBModified ); + // ====================== + // ======== Defs ======== + // ====================== + + typedef enum bit [3:0] { + I_IDLE, + I_WA, + I_WD1, + I_WD2, + I_WD3, + I_WD4, + I_WD5, + I_WD6, + I_WD7, + I_WD8, + I_REFILL + } istate_t; + + typedef enum bit [2:0] { + DR_IDLE, + DR_WA, + DR_WD1, + DR_WD2, + DR_WD3, + DR_WD4, + DR_REFILL + } drstate_t; + + typedef enum bit [2:0] { + DW_IDLE, + DW_WD1, + DW_WD2, + DW_WD3, + DW_WD4, + DW_WB, + DW_WAITR + } dwstate_t; + + typedef enum bit { + DWA_IDLE, + DWA_WA + } dwastate_t; + // ====================== // ======== iVar ======== // ====================== @@ -62,19 +105,6 @@ module MMU ( // ======== iState Machine ======== // ================================ - typedef enum bit [3:0] { - I_IDLE, - I_WA, - I_WD1, - I_WD2, - I_WD3, - I_WD4, - I_WD5, - I_WD6, - I_WD7, - I_WD8, - I_REFILL - } istate_t; istate_t iState; istate_t iNextState; @@ -331,30 +361,10 @@ module MMU ( dWdata1 ); - // ================================ - // ========== dFunction ========== - // ================================ - - assign dVA = data.addr; - assign dValid1 = dReq1 & dHit1 & dMValid1 & (~data.wr | dDirty1); - - assign dTLBRefill = (drState == DR_IDLE) & dReq1 & ~dHit1; - assign dTLBInvalid = (drState == DR_IDLE) & dReq1 & ~dMValid1; - assign dTLBModified = (drState == DR_IDLE) & dReq1 & data.wr & ~dDirty1; - // ================================= // ======== drState Machine ======== // ================================= - typedef enum bit [2:0] { - DR_IDLE, - DR_WA, - DR_WD1, - DR_WD2, - DR_WD3, - DR_WD4, - DR_REFILL - } drstate_t; drstate_t drState; drstate_t drNextState; @@ -428,6 +438,17 @@ module MMU ( endcase end + // ================================ + // ========== dFunction ========== + // ================================ + + assign dVA = data.addr; + assign dValid1 = dReq1 & dHit1 & dMValid1 & (~data.wr | dDirty1); + + assign dTLBRefill = (drState == DR_IDLE) & dReq1 & ~dHit1; + assign dTLBInvalid = (drState == DR_IDLE) & dReq1 & ~dMValid1; + assign dTLBModified = (drState == DR_IDLE) & dReq1 & data.wr & ~dDirty1; + // ============================= // ======== drFlip-Flop ======== // ============================= @@ -489,15 +510,6 @@ module MMU ( // ======== dwState Machine ======== // ================================= - typedef enum bit [2:0] { - DW_IDLE, - DW_WD1, - DW_WD2, - DW_WD3, - DW_WD4, - DW_WB, - DW_WAITR - } dwstate_t; dwstate_t dwState; dwstate_t dwNextState; @@ -611,10 +623,6 @@ module MMU ( assign wdata_ok = (dwNextState == DW_IDLE) | (dwNextState == DW_WAITR); - typedef enum bit { - DWA_IDLE, - DWA_WA - } dwastate_t; dwastate_t dwaState; dwastate_t dwaNextState; @@ -682,12 +690,12 @@ module MMU ( .tlbp (tlbp), .c0_Index (c0_Index), .c0_EntryHi (c0_EntryHi), - .c0_PageMask(c0_PageMask), + // .c0_PageMask(c0_PageMask), .c0_EntryLo1(c0_EntryLo1), .c0_EntryLo0(c0_EntryLo0), .EntryHi (EntryHi), - .PageMask(PageMask), + // .PageMask(PageMask), .EntryLo1(EntryLo1), .EntryLo0(EntryLo0), .Index (Index), diff --git a/src/MMU/TLB.sv b/src/MMU/TLB.sv index 6c35cfe..b4b5ca7 100644 --- a/src/MMU/TLB.sv +++ b/src/MMU/TLB.sv @@ -1,3 +1,4 @@ +`include "defines.svh" `include "TLB.svh" module TLB ( @@ -11,12 +12,12 @@ module TLB ( input Index_t c0_Index, // TLBR input EntryHi_t c0_EntryHi, // TLBWI + F/M(ASID) - input PageMask_t c0_PageMask, // TLBWI + // input PageMask_t c0_PageMask, // TLBWI input EntryLo_t c0_EntryLo1, // TLBWI input EntryLo_t c0_EntryLo0, // TLBWI output EntryHi_t EntryHi, // TLBR - output PageMask_t PageMask, // TLBR + // output PageMask_t PageMask, // TLBR output EntryLo_t EntryLo1, // TLBR output EntryLo_t EntryLo0, // TLBR output Index_t Index, // TLBP @@ -51,30 +52,30 @@ module TLB ( Index_t Index0; - TLB_t [3:0] TLB_entries; + TLB_t [7:0] TLB_entries; TLB_t entry; - // CP0(TLBWI) EntryHi PageMask EntryLo0 EntryLo1 -> TLB[Index] + // CP0(TLBWI) EntryHi /*PageMask*/ EntryLo0 EntryLo1 -> TLB[Index] always_ff @(posedge clk) begin if (rst) begin - TLB_entries <= 360'b0; + TLB_entries <= 624'b0; end else if (tlbwi) TLB_entries[c0_Index.Index] <= {c0_EntryHi.VPN2, c0_EntryHi.ASID, - c0_PageMask.Mask, + // c0_PageMask.Mask, c0_EntryLo0.G & c0_EntryLo1.G, c0_EntryLo0.PFN, c0_EntryLo0.C, c0_EntryLo0.D, c0_EntryLo0.V, c0_EntryLo1.PFN, c0_EntryLo1.C, c0_EntryLo1.D, c0_EntryLo1.V}; end - // CP0(TLBR) Index -> EntryHi PageMask EntryLo0 EntryLo1 + // CP0(TLBR) Index -> EntryHi /*PageMask*/ EntryLo0 EntryLo1 assign entry = TLB_entries[c0_Index.Index]; assign EntryHi.zero = 5'b0; assign EntryHi.VPN2 = entry.VPN2; assign EntryHi.ASID = entry.ASID; - assign PageMask.zero1 = 7'b0; - assign PageMask.Mask = entry.PageMask; - assign PageMask.zero2 = 13'b0; + // assign PageMask.zero1 = 7'b0; + // assign PageMask.Mask = entry.PageMask; + // assign PageMask.zero2 = 13'b0; assign EntryLo0.zero = 6'b0; assign EntryLo0.PFN = entry.PFN0; @@ -192,7 +193,7 @@ endmodule module TLB_Lookup ( - input TLB_t [ 3:0] TLB_entries, + input TLB_t [ 7:0] TLB_entries, input logic [19:0] VPN, input logic [ 7:0] ASID, @@ -204,40 +205,47 @@ module TLB_Lookup ( output Index_t index ); - logic [3:0] hitWay; - for (genvar i = 0; i < 4; i++) - assign hitWay[i] = ((TLB_entries[i].VPN2 & ~{7'b0, TLB_entries[i].PageMask}) - == (VPN[19:1] & ~{7'b0, TLB_entries[i].PageMask})) + logic [7:0] hitWay; + for (genvar i = 0; i < 8; i++) + // assign hitWay[i] = ((TLB_entries[i].VPN2 & ~{7'b0, TLB_entries[i].PageMask}) + // == (VPN[19:1] & ~{7'b0, TLB_entries[i].PageMask})) + // & (TLB_entries[i].G | TLB_entries[i].ASID == ASID); + assign hitWay[i] = (TLB_entries[i].VPN2 == VPN[19:1]) & (TLB_entries[i].G | TLB_entries[i].ASID == ASID); // assume: hit is unique assign hit = |{hitWay}; assign index.P = ~hit; assign index.zero = 0; - onehot_bin4 index_decoder(hitWay, index.Index); + onehot_bin8 index_decoder(hitWay, index.Index); // always_comb for (int i = 0; i < 32; i++) index.Index |= hitWay[i] ? i : 0; TLB_t found; - assign found = (hitWay[ 0] ? TLB_entries[ 0] : 90'b0) - | (hitWay[ 1] ? TLB_entries[ 1] : 90'b0) - | (hitWay[ 2] ? TLB_entries[ 2] : 90'b0) - | (hitWay[ 3] ? TLB_entries[ 3] : 90'b0); + assign found = (hitWay[ 0] ? TLB_entries[ 0] : 78'b0) + | (hitWay[ 1] ? TLB_entries[ 1] : 78'b0) + | (hitWay[ 2] ? TLB_entries[ 2] : 78'b0) + | (hitWay[ 3] ? TLB_entries[ 3] : 78'b0) + | (hitWay[ 4] ? TLB_entries[ 4] : 78'b0) + | (hitWay[ 5] ? TLB_entries[ 5] : 78'b0) + | (hitWay[ 6] ? TLB_entries[ 6] : 78'b0) + | (hitWay[ 7] ? TLB_entries[ 7] : 78'b0); logic parity; - assign parity = |{ - VPN[12] & found.PageMask[10], - VPN[10] & ~found.PageMask[10] & found.PageMask[ 8], - VPN[ 8] & ~found.PageMask[ 8] & found.PageMask[ 6], - VPN[ 6] & ~found.PageMask[ 6] & found.PageMask[ 4], - VPN[ 4] & ~found.PageMask[ 4] & found.PageMask[ 2], - VPN[ 2] & ~found.PageMask[ 2] & found.PageMask[ 0], - VPN[ 0] & ~found.PageMask[ 0] - }; + // assign parity = |{ + // VPN[12] & found.PageMask[10], + // VPN[10] & ~found.PageMask[10] & found.PageMask[ 8], + // VPN[ 8] & ~found.PageMask[ 8] & found.PageMask[ 6], + // VPN[ 6] & ~found.PageMask[ 6] & found.PageMask[ 4], + // VPN[ 4] & ~found.PageMask[ 4] & found.PageMask[ 2], + // VPN[ 2] & ~found.PageMask[ 2] & found.PageMask[ 0], + // VPN[ 0] & ~found.PageMask[ 0] + // }; // assign parity = |{VPN & {7'b0, found.PageMask + 1'b1}}; + assign parity = VPN[0]; logic [19:0] PFN; assign {PFN, cached, dirty, valid} = parity ? {found.PFN1, found.C1[0], found.D1, found.V1} : {found.PFN0, found.C0[0], found.D0, found.V0}; - assign PPN = (VPN & {8'b0, found.PageMask}) | (PFN & ~{8'b0, found.PageMask}); - + // assign PPN = (VPN & {8'b0, found.PageMask}) | (PFN & ~{8'b0, found.PageMask}); + assign PPN = PFN; endmodule diff --git a/src/MyCPU.sv b/src/MyCPU.sv index 12fd74e..544c86e 100644 --- a/src/MyCPU.sv +++ b/src/MyCPU.sv @@ -93,11 +93,11 @@ module mycpu_top ( logic [2:0] K0; Index_t c0_Index; EntryHi_t c0_EntryHi; - PageMask_t c0_PageMask; + // PageMask_t c0_PageMask; EntryLo_t c0_EntryLo1; EntryLo_t c0_EntryLo0; EntryHi_t tlb_EntryHi; - PageMask_t tlb_PageMask; + // PageMask_t tlb_PageMask; EntryLo_t tlb_EntryLo1; EntryLo_t tlb_EntryLo0; Index_t tlb_Index; @@ -138,11 +138,11 @@ module mycpu_top ( .tlbp (tlb_tlbp), .c0_Index (c0_Index), .c0_EntryHi (c0_EntryHi), - .c0_PageMask (c0_PageMask), + // .c0_PageMask (c0_PageMask), .c0_EntryLo1 (c0_EntryLo1), .c0_EntryLo0 (c0_EntryLo0), .EntryHi (tlb_EntryHi), - .PageMask (tlb_PageMask), + // .PageMask (tlb_PageMask), .EntryLo1 (tlb_EntryLo1), .EntryLo0 (tlb_EntryLo0), .Index (tlb_Index), @@ -184,11 +184,11 @@ module mycpu_top ( .K0 (K0), .Index (c0_Index), .EntryHi (c0_EntryHi), - .PageMask (c0_PageMask), + // .PageMask (c0_PageMask), .EntryLo1 (c0_EntryLo1), .EntryLo0 (c0_EntryLo0), .tlb_EntryHi (tlb_EntryHi), - .tlb_PageMask(tlb_PageMask), + // .tlb_PageMask(tlb_PageMask), .tlb_EntryLo1(tlb_EntryLo1), .tlb_EntryLo0(tlb_EntryLo0), .tlb_Index (tlb_Index) diff --git a/src/include/CP0.svh b/src/include/CP0.svh index d6fefcf..89b8c2c 100644 --- a/src/include/CP0.svh +++ b/src/include/CP0.svh @@ -115,11 +115,13 @@ typedef struct packed { EntryHi_t EntryHi; word_t Count; word_t BadVAddr; - // HWREna, Wired, Context, - PageMask_t PageMask; + // HWREna + Wired_t Wired; + // Context, + // word_t PageMask; EntryLo_t EntryLo1; EntryLo_t EntryLo0; - //Random + Random_t Random; Index_t Index; // ==== sel1 ==== diff --git a/src/include/TLB.svh b/src/include/TLB.svh index 89d241a..e54dc45 100644 --- a/src/include/TLB.svh +++ b/src/include/TLB.svh @@ -7,11 +7,11 @@ typedef struct packed { logic [ 7:0] ASID; } EntryHi_t; -typedef struct packed { - logic [ 6:0] zero1; - logic [11:0] Mask; - logic [12:0] zero2; -} PageMask_t; +// typedef struct packed { +// logic [ 6:0] zero1; +// logic [11:0] Mask; +// logic [12:0] zero2; +// } PageMask_t; typedef struct packed { logic [ 5:0] zero; @@ -24,14 +24,24 @@ typedef struct packed { typedef struct packed { logic P; - logic [28:0] zero; - logic [ 1:0] Index; + logic [27:0] zero; + logic [ 2:0] Index; } Index_t; +typedef struct packed { + logic [28:0] zero; + logic [ 2:0] Wired; +} Wired_t; + +typedef struct packed { + logic [28:0] zero; + logic [ 2:0] Random; +} Random_t; + typedef struct packed { logic [18:0] VPN2; logic [ 7:0] ASID; - logic [11:0] PageMask; + // logic [11:0] PageMask; logic G; logic [19:0] PFN0; logic [ 2:0] C0;