diff --git a/resources/block/mycpu_block.xdc b/resources/block/mycpu_block.xdc index 356d4df..51066ba 100644 --- a/resources/block/mycpu_block.xdc +++ b/resources/block/mycpu_block.xdc @@ -81,7 +81,7 @@ create_clock -period 40.000 -name mii_rtl_0_tx_clk -waveform {0.000 20.000} [get -connect_debug_port u_ila_0/probe2 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[31]}]] + create_debug_core u_ila_0 ila set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] @@ -96,211 +96,607 @@ set_property port_width 1 [get_debug_ports u_ila_0/clk] connect_debug_port u_ila_0/clk [get_nets [list mycpu_block_i/clk_wiz_0/inst/clk_cpu]] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] set_property port_width 32 [get_debug_ports u_ila_0/probe0] -connect_debug_port u_ila_0/probe0 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[31]}]] +connect_debug_port u_ila_0/probe0 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/HI[31]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] set_property port_width 32 [get_debug_ports u_ila_0/probe1] -connect_debug_port u_ila_0/probe1 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[31]}]] +connect_debug_port u_ila_0/probe1 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/rdata[31]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] set_property port_width 32 [get_debug_ports u_ila_0/probe2] -connect_debug_port u_ila_0/probe2 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[31]}]] +connect_debug_port u_ila_0/probe2 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_count[31]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] -set_property port_width 32 [get_debug_ports u_ila_0/probe3] -connect_debug_port u_ila_0/probe3 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[31]}]] +set_property port_width 5 [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/addr[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/addr[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/addr[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/addr[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/addr[4]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] set_property port_width 32 [get_debug_ports u_ila_0/probe4] -connect_debug_port u_ila_0/probe4 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[31]}]] +connect_debug_port u_ila_0/probe4 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/LO[31]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] -set_property port_width 4 [get_debug_ports u_ila_0/probe5] -connect_debug_port u_ila_0/probe5 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_ExcCode[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_ExcCode[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_ExcCode[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_ExcCode[3]}]] +set_property port_width 20 [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo0[PFN][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo0[PFN][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo0[PFN][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo0[PFN][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo0[PFN][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo0[PFN][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo0[PFN][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo0[PFN][7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo0[PFN][8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo0[PFN][9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo0[PFN][10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo0[PFN][11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo0[PFN][12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo0[PFN][13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo0[PFN][14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo0[PFN][15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo0[PFN][16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo0[PFN][17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo0[PFN][18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo0[PFN][19]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] -set_property port_width 32 [get_debug_ports u_ila_0/probe6] -connect_debug_port u_ila_0/probe6 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[31]}]] +set_property port_width 3 [get_debug_ports u_ila_0/probe6] +connect_debug_port u_ila_0/probe6 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_Index[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_Index[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_Index[2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] set_property port_width 32 [get_debug_ports u_ila_0/probe7] -connect_debug_port u_ila_0/probe7 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[31]}]] +connect_debug_port u_ila_0/probe7 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/wdata[31]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] set_property port_width 32 [get_debug_ports u_ila_0/probe8] -connect_debug_port u_ila_0/probe8 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[31]}]] +connect_debug_port u_ila_0/probe8 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[31]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] -set_property port_width 32 [get_debug_ports u_ila_0/probe9] -connect_debug_port u_ila_0/probe9 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[31]}]] +set_property port_width 4 [get_debug_ports u_ila_0/probe9] +connect_debug_port u_ila_0/probe9 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_ExcCode[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_ExcCode[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_ExcCode[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_ExcCode[3]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] -set_property port_width 4 [get_debug_ports u_ila_0/probe10] -connect_debug_port u_ila_0/probe10 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wstrb[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wstrb[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wstrb[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wstrb[3]}]] +set_property port_width 32 [get_debug_ports u_ila_0/probe10] +connect_debug_port u_ila_0/probe10 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[31]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] -set_property port_width 4 [get_debug_ports u_ila_0/probe11] -connect_debug_port u_ila_0/probe11 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_wstrb[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_wstrb[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_wstrb[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_wstrb[3]}]] +set_property port_width 3 [get_debug_ports u_ila_0/probe11] +connect_debug_port u_ila_0/probe11 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/sel[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/sel[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/sel[2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] set_property port_width 32 [get_debug_ports u_ila_0/probe12] -connect_debug_port u_ila_0/probe12 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[31]}]] +connect_debug_port u_ila_0/probe12 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/CP0_compare[31]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] -set_property port_width 2 [get_debug_ports u_ila_0/probe13] -connect_debug_port u_ila_0/probe13 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_size[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_size[1]}]] +set_property port_width 6 [get_debug_ports u_ila_0/probe13] +connect_debug_port u_ila_0/probe13 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/ext_int_sync[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/ext_int_sync[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/ext_int_sync[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/ext_int_sync[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/ext_int_sync[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/ext_int_sync[5]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] -set_property port_width 32 [get_debug_ports u_ila_0/probe14] -connect_debug_port u_ila_0/probe14 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[31]}]] +set_property port_width 19 [get_debug_ports u_ila_0/probe14] +connect_debug_port u_ila_0/probe14 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryHi[VPN2][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryHi[VPN2][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryHi[VPN2][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryHi[VPN2][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryHi[VPN2][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryHi[VPN2][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryHi[VPN2][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryHi[VPN2][7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryHi[VPN2][8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryHi[VPN2][9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryHi[VPN2][10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryHi[VPN2][11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryHi[VPN2][12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryHi[VPN2][13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryHi[VPN2][14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryHi[VPN2][15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryHi[VPN2][16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryHi[VPN2][17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryHi[VPN2][18]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] set_property port_width 3 [get_debug_ports u_ila_0/probe15] -connect_debug_port u_ila_0/probe15 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_size[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_size[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_size[2]}]] +connect_debug_port u_ila_0/probe15 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][C1][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][C1][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][C1][2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] -set_property port_width 29 [get_debug_ports u_ila_0/probe16] -connect_debug_port u_ila_0/probe16 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[31]}]] +set_property port_width 20 [get_debug_ports u_ila_0/probe16] +connect_debug_port u_ila_0/probe16 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN0][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN0][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN0][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN0][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN0][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN0][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN0][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN0][7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN0][8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN0][9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN0][10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN0][11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN0][12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN0][13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN0][14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN0][15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN0][16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN0][17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN0][18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN0][19]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] -set_property port_width 32 [get_debug_ports u_ila_0/probe17] -connect_debug_port u_ila_0/probe17 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[31]}]] +set_property port_width 20 [get_debug_ports u_ila_0/probe17] +connect_debug_port u_ila_0/probe17 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN1][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN1][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN1][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN1][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN1][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN1][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN1][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN1][7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN1][8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN1][9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN1][10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN1][11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN1][12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN1][13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN1][14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN1][15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN1][16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN1][17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN1][18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN1][19]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] set_property port_width 3 [get_debug_ports u_ila_0/probe18] -connect_debug_port u_ila_0/probe18 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_size[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_size[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_size[2]}]] +connect_debug_port u_ila_0/probe18 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][C0][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][C0][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][C0][2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] -set_property port_width 4 [get_debug_ports u_ila_0/probe19] -connect_debug_port u_ila_0/probe19 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_len[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_len[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_len[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_len[3]}]] +set_property port_width 19 [get_debug_ports u_ila_0/probe19] +connect_debug_port u_ila_0/probe19 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][VPN2][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][VPN2][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][VPN2][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][VPN2][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][VPN2][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][VPN2][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][VPN2][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][VPN2][7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][VPN2][8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][VPN2][9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][VPN2][10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][VPN2][11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][VPN2][12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][VPN2][13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][VPN2][14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][VPN2][15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][VPN2][16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][VPN2][17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][VPN2][18]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] -set_property port_width 4 [get_debug_ports u_ila_0/probe20] -connect_debug_port u_ila_0/probe20 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_len[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_len[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_len[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_len[3]}]] +set_property port_width 3 [get_debug_ports u_ila_0/probe20] +connect_debug_port u_ila_0/probe20 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][C0][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][C0][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][C0][2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] -set_property port_width 32 [get_debug_ports u_ila_0/probe21] -connect_debug_port u_ila_0/probe21 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[31]}]] +set_property port_width 8 [get_debug_ports u_ila_0/probe21] +connect_debug_port u_ila_0/probe21 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][ASID][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][ASID][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][ASID][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][ASID][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][ASID][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][ASID][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][ASID][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][ASID][7]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] -set_property port_width 32 [get_debug_ports u_ila_0/probe22] -connect_debug_port u_ila_0/probe22 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[31]}]] +set_property port_width 20 [get_debug_ports u_ila_0/probe22] +connect_debug_port u_ila_0/probe22 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN0][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN0][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN0][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN0][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN0][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN0][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN0][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN0][7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN0][8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN0][9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN0][10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN0][11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN0][12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN0][13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN0][14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN0][15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN0][16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN0][17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN0][18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN0][19]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] -set_property port_width 32 [get_debug_ports u_ila_0/probe23] -connect_debug_port u_ila_0/probe23 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[31]}]] +set_property port_width 3 [get_debug_ports u_ila_0/probe23] +connect_debug_port u_ila_0/probe23 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][C0][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][C0][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][C0][2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] -set_property port_width 6 [get_debug_ports u_ila_0/probe24] -connect_debug_port u_ila_0/probe24 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/ext_int_sync[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/ext_int_sync[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/ext_int_sync[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/ext_int_sync[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/ext_int_sync[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/ext_int_sync[5]}]] +set_property port_width 19 [get_debug_ports u_ila_0/probe24] +connect_debug_port u_ila_0/probe24 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][VPN2][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][VPN2][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][VPN2][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][VPN2][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][VPN2][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][VPN2][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][VPN2][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][VPN2][7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][VPN2][8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][VPN2][9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][VPN2][10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][VPN2][11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][VPN2][12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][VPN2][13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][VPN2][14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][VPN2][15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][VPN2][16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][VPN2][17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][VPN2][18]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25] -set_property port_width 5 [get_debug_ports u_ila_0/probe25] -connect_debug_port u_ila_0/probe25 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr2[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr2[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr2[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr2[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr2[4]}]] +set_property port_width 8 [get_debug_ports u_ila_0/probe25] +connect_debug_port u_ila_0/probe25 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][ASID][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][ASID][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][ASID][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][ASID][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][ASID][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][ASID][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][ASID][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][ASID][7]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26] -set_property port_width 5 [get_debug_ports u_ila_0/probe26] -connect_debug_port u_ila_0/probe26 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr1[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr1[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr1[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr1[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr1[4]}]] +set_property port_width 8 [get_debug_ports u_ila_0/probe26] +connect_debug_port u_ila_0/probe26 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][ASID][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][ASID][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][ASID][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][ASID][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][ASID][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][ASID][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][ASID][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][ASID][7]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27] -set_property port_width 1 [get_debug_ports u_ila_0/probe27] -connect_debug_port u_ila_0/probe27 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_call]] +set_property port_width 3 [get_debug_ports u_ila_0/probe27] +connect_debug_port u_ila_0/probe27 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo1[C][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo1[C][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo1[C][2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28] -set_property port_width 1 [get_debug_ports u_ila_0/probe28] -connect_debug_port u_ila_0/probe28 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_done]] +set_property port_width 19 [get_debug_ports u_ila_0/probe28] +connect_debug_port u_ila_0/probe28 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][VPN2][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][VPN2][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][VPN2][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][VPN2][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][VPN2][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][VPN2][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][VPN2][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][VPN2][7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][VPN2][8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][VPN2][9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][VPN2][10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][VPN2][11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][VPN2][12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][VPN2][13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][VPN2][14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][VPN2][15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][VPN2][16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][VPN2][17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][VPN2][18]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29] -set_property port_width 1 [get_debug_ports u_ila_0/probe29] -connect_debug_port u_ila_0/probe29 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_call]] +set_property port_width 3 [get_debug_ports u_ila_0/probe29] +connect_debug_port u_ila_0/probe29 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][C0][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][C0][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][C0][2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30] -set_property port_width 1 [get_debug_ports u_ila_0/probe30] -connect_debug_port u_ila_0/probe30 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_done]] +set_property port_width 3 [get_debug_ports u_ila_0/probe30] +connect_debug_port u_ila_0/probe30 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][C1][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][C1][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][C1][2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31] -set_property port_width 1 [get_debug_ports u_ila_0/probe31] -connect_debug_port u_ila_0/probe31 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_valid]] +set_property port_width 20 [get_debug_ports u_ila_0/probe31] +connect_debug_port u_ila_0/probe31 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN1][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN1][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN1][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN1][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN1][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN1][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN1][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN1][7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN1][8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN1][9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN1][10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN1][11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN1][12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN1][13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN1][14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN1][15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN1][16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN1][17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN1][18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][PFN1][19]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32] -set_property port_width 1 [get_debug_ports u_ila_0/probe32] -connect_debug_port u_ila_0/probe32 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_valid]] +set_property port_width 19 [get_debug_ports u_ila_0/probe32] +connect_debug_port u_ila_0/probe32 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][VPN2][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][VPN2][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][VPN2][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][VPN2][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][VPN2][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][VPN2][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][VPN2][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][VPN2][7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][VPN2][8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][VPN2][9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][VPN2][10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][VPN2][11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][VPN2][12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][VPN2][13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][VPN2][14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][VPN2][15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][VPN2][16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][VPN2][17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][VPN2][18]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33] -set_property port_width 1 [get_debug_ports u_ila_0/probe33] -connect_debug_port u_ila_0/probe33 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/dAddressError]] +set_property port_width 8 [get_debug_ports u_ila_0/probe33] +connect_debug_port u_ila_0/probe33 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][ASID][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][ASID][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][ASID][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][ASID][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][ASID][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][ASID][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][ASID][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][ASID][7]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34] -set_property port_width 1 [get_debug_ports u_ila_0/probe34] -connect_debug_port u_ila_0/probe34 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/dTLBInvalid]] +set_property port_width 20 [get_debug_ports u_ila_0/probe34] +connect_debug_port u_ila_0/probe34 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN0][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN0][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN0][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN0][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN0][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN0][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN0][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN0][7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN0][8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN0][9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN0][10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN0][11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN0][12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN0][13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN0][14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN0][15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN0][16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN0][17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN0][18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN0][19]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35] -set_property port_width 1 [get_debug_ports u_ila_0/probe35] -connect_debug_port u_ila_0/probe35 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/dTLBModified]] +set_property port_width 3 [get_debug_ports u_ila_0/probe35] +connect_debug_port u_ila_0/probe35 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][C0][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][C0][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][C0][2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36] -set_property port_width 1 [get_debug_ports u_ila_0/probe36] -connect_debug_port u_ila_0/probe36 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/dTLBRefill]] +set_property port_width 20 [get_debug_ports u_ila_0/probe36] +connect_debug_port u_ila_0/probe36 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN0][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN0][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN0][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN0][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN0][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN0][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN0][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN0][7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN0][8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN0][9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN0][10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN0][11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN0][12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN0][13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN0][14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN0][15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN0][16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN0][17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN0][18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][PFN0][19]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37] -set_property port_width 1 [get_debug_ports u_ila_0/probe37] -connect_debug_port u_ila_0/probe37 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_ERET]] +set_property port_width 20 [get_debug_ports u_ila_0/probe37] +connect_debug_port u_ila_0/probe37 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN0][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN0][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN0][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN0][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN0][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN0][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN0][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN0][7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN0][8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN0][9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN0][10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN0][11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN0][12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN0][13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN0][14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN0][15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN0][16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN0][17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN0][18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN0][19]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38] -set_property port_width 1 [get_debug_ports u_ila_0/probe38] -connect_debug_port u_ila_0/probe38 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_ExcValid]] +set_property port_width 3 [get_debug_ports u_ila_0/probe38] +connect_debug_port u_ila_0/probe38 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][C1][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][C1][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][C1][2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39] -set_property port_width 1 [get_debug_ports u_ila_0/probe39] -connect_debug_port u_ila_0/probe39 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/iAddressError]] +set_property port_width 20 [get_debug_ports u_ila_0/probe39] +connect_debug_port u_ila_0/probe39 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN0][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN0][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN0][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN0][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN0][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN0][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN0][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN0][7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN0][8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN0][9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN0][10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN0][11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN0][12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN0][13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN0][14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN0][15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN0][16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN0][17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN0][18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN0][19]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40] -set_property port_width 1 [get_debug_ports u_ila_0/probe40] -connect_debug_port u_ila_0/probe40 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr_ok]] +set_property port_width 8 [get_debug_ports u_ila_0/probe40] +connect_debug_port u_ila_0/probe40 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][ASID][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][ASID][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][ASID][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][ASID][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][ASID][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][ASID][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][ASID][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][ASID][7]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41] -set_property port_width 1 [get_debug_ports u_ila_0/probe41] -connect_debug_port u_ila_0/probe41 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_data_ok]] +set_property port_width 8 [get_debug_ports u_ila_0/probe41] +connect_debug_port u_ila_0/probe41 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryHi[ASID][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryHi[ASID][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryHi[ASID][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryHi[ASID][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryHi[ASID][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryHi[ASID][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryHi[ASID][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryHi[ASID][7]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42] -set_property port_width 1 [get_debug_ports u_ila_0/probe42] -connect_debug_port u_ila_0/probe42 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_req]] +set_property port_width 20 [get_debug_ports u_ila_0/probe42] +connect_debug_port u_ila_0/probe42 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN1][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN1][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN1][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN1][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN1][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN1][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN1][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN1][7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN1][8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN1][9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN1][10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN1][11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN1][12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN1][13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN1][14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN1][15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN1][16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN1][17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN1][18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN1][19]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43] -set_property port_width 1 [get_debug_ports u_ila_0/probe43] -connect_debug_port u_ila_0/probe43 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/iTLBInvalid]] +set_property port_width 3 [get_debug_ports u_ila_0/probe43] +connect_debug_port u_ila_0/probe43 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][C1][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][C1][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][C1][2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44] -set_property port_width 1 [get_debug_ports u_ila_0/probe44] -connect_debug_port u_ila_0/probe44 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/iTLBRefill]] +set_property port_width 19 [get_debug_ports u_ila_0/probe44] +connect_debug_port u_ila_0/probe44 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][VPN2][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][VPN2][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][VPN2][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][VPN2][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][VPN2][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][VPN2][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][VPN2][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][VPN2][7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][VPN2][8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][VPN2][9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][VPN2][10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][VPN2][11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][VPN2][12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][VPN2][13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][VPN2][14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][VPN2][15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][VPN2][16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][VPN2][17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][VPN2][18]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45] -set_property port_width 1 [get_debug_ports u_ila_0/probe45] -connect_debug_port u_ila_0/probe45 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr_ok]] +set_property port_width 3 [get_debug_ports u_ila_0/probe45] +connect_debug_port u_ila_0/probe45 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo0[C][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo0[C][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo0[C][2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46] -set_property port_width 1 [get_debug_ports u_ila_0/probe46] -connect_debug_port u_ila_0/probe46 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_data_ok]] +set_property port_width 8 [get_debug_ports u_ila_0/probe46] +connect_debug_port u_ila_0/probe46 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][ASID][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][ASID][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][ASID][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][ASID][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][ASID][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][ASID][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][ASID][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][ASID][7]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47] -set_property port_width 1 [get_debug_ports u_ila_0/probe47] -connect_debug_port u_ila_0/probe47 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_req]] +set_property port_width 20 [get_debug_ports u_ila_0/probe47] +connect_debug_port u_ila_0/probe47 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN1][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN1][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN1][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN1][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN1][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN1][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN1][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN1][7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN1][8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN1][9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN1][10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN1][11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN1][12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN1][13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN1][14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN1][15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN1][16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN1][17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN1][18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][PFN1][19]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48] -set_property port_width 1 [get_debug_ports u_ila_0/probe48] -connect_debug_port u_ila_0/probe48 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_req]] +set_property port_width 3 [get_debug_ports u_ila_0/probe48] +connect_debug_port u_ila_0/probe48 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][C0][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][C0][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][C0][2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49] -set_property port_width 1 [get_debug_ports u_ila_0/probe49] -connect_debug_port u_ila_0/probe49 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wr]] +set_property port_width 3 [get_debug_ports u_ila_0/probe49] +connect_debug_port u_ila_0/probe49 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][C1][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][C1][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][C1][2]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50] -set_property port_width 1 [get_debug_ports u_ila_0/probe50] -connect_debug_port u_ila_0/probe50 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/we1]] +set_property port_width 20 [get_debug_ports u_ila_0/probe50] +connect_debug_port u_ila_0/probe50 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN1][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN1][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN1][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN1][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN1][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN1][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN1][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN1][7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN1][8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN1][9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN1][10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN1][11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN1][12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN1][13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN1][14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN1][15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN1][16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN1][17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN1][18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][PFN1][19]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51] -set_property port_width 1 [get_debug_ports u_ila_0/probe51] -connect_debug_port u_ila_0/probe51 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/we2]] +set_property port_width 20 [get_debug_ports u_ila_0/probe51] +connect_debug_port u_ila_0/probe51 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN1][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN1][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN1][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN1][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN1][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN1][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN1][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN1][7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN1][8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN1][9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN1][10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN1][11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN1][12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN1][13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN1][14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN1][15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN1][16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN1][17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN1][18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][PFN1][19]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52] +set_property port_width 8 [get_debug_ports u_ila_0/probe52] +connect_debug_port u_ila_0/probe52 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][ASID][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][ASID][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][ASID][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][ASID][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][ASID][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][ASID][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][ASID][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][ASID][7]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53] +set_property port_width 3 [get_debug_ports u_ila_0/probe53] +connect_debug_port u_ila_0/probe53 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][C0][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][C0][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][C0][2]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54] +set_property port_width 3 [get_debug_ports u_ila_0/probe54] +connect_debug_port u_ila_0/probe54 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][C1][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][C1][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][C1][2]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55] +set_property port_width 19 [get_debug_ports u_ila_0/probe55] +connect_debug_port u_ila_0/probe55 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][VPN2][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][VPN2][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][VPN2][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][VPN2][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][VPN2][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][VPN2][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][VPN2][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][VPN2][7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][VPN2][8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][VPN2][9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][VPN2][10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][VPN2][11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][VPN2][12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][VPN2][13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][VPN2][14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][VPN2][15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][VPN2][16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][VPN2][17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][VPN2][18]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56] +set_property port_width 20 [get_debug_ports u_ila_0/probe56] +connect_debug_port u_ila_0/probe56 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN0][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN0][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN0][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN0][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN0][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN0][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN0][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN0][7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN0][8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN0][9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN0][10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN0][11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN0][12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN0][13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN0][14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN0][15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN0][16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN0][17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN0][18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][PFN0][19]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57] +set_property port_width 3 [get_debug_ports u_ila_0/probe57] +connect_debug_port u_ila_0/probe57 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][C1][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][C1][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][C1][2]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58] +set_property port_width 20 [get_debug_ports u_ila_0/probe58] +connect_debug_port u_ila_0/probe58 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN1][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN1][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN1][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN1][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN1][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN1][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN1][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN1][7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN1][8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN1][9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN1][10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN1][11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN1][12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN1][13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN1][14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN1][15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN1][16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN1][17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN1][18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][PFN1][19]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59] +set_property port_width 19 [get_debug_ports u_ila_0/probe59] +connect_debug_port u_ila_0/probe59 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][VPN2][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][VPN2][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][VPN2][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][VPN2][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][VPN2][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][VPN2][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][VPN2][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][VPN2][7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][VPN2][8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][VPN2][9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][VPN2][10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][VPN2][11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][VPN2][12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][VPN2][13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][VPN2][14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][VPN2][15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][VPN2][16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][VPN2][17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][VPN2][18]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60] +set_property port_width 3 [get_debug_ports u_ila_0/probe60] +connect_debug_port u_ila_0/probe60 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][C0][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][C0][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][C0][2]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61] +set_property port_width 3 [get_debug_ports u_ila_0/probe61] +connect_debug_port u_ila_0/probe61 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][C1][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][C1][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][C1][2]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62] +set_property port_width 20 [get_debug_ports u_ila_0/probe62] +connect_debug_port u_ila_0/probe62 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN1][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN1][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN1][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN1][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN1][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN1][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN1][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN1][7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN1][8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN1][9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN1][10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN1][11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN1][12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN1][13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN1][14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN1][15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN1][16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN1][17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN1][18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN1][19]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63] +set_property port_width 19 [get_debug_ports u_ila_0/probe63] +connect_debug_port u_ila_0/probe63 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][VPN2][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][VPN2][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][VPN2][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][VPN2][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][VPN2][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][VPN2][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][VPN2][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][VPN2][7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][VPN2][8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][VPN2][9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][VPN2][10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][VPN2][11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][VPN2][12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][VPN2][13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][VPN2][14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][VPN2][15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][VPN2][16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][VPN2][17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][VPN2][18]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64] +set_property port_width 8 [get_debug_ports u_ila_0/probe64] +connect_debug_port u_ila_0/probe64 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][ASID][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][ASID][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][ASID][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][ASID][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][ASID][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][ASID][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][ASID][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][ASID][7]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe65] +set_property port_width 20 [get_debug_ports u_ila_0/probe65] +connect_debug_port u_ila_0/probe65 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN0][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN0][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN0][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN0][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN0][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN0][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN0][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN0][7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN0][8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN0][9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN0][10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN0][11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN0][12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN0][13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN0][14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN0][15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN0][16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN0][17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN0][18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][PFN0][19]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66] +set_property port_width 3 [get_debug_ports u_ila_0/probe66] +connect_debug_port u_ila_0/probe66 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_size[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_size[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_size[2]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67] +set_property port_width 2 [get_debug_ports u_ila_0/probe67] +connect_debug_port u_ila_0/probe67 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_size[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_size[1]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe68] +set_property port_width 32 [get_debug_ports u_ila_0/probe68] +connect_debug_port u_ila_0/probe68 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[31]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe69] +set_property port_width 32 [get_debug_ports u_ila_0/probe69] +connect_debug_port u_ila_0/probe69 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[31]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe70] +set_property port_width 32 [get_debug_ports u_ila_0/probe70] +connect_debug_port u_ila_0/probe70 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[31]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe71] +set_property port_width 32 [get_debug_ports u_ila_0/probe71] +connect_debug_port u_ila_0/probe71 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[31]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe72] +set_property port_width 32 [get_debug_ports u_ila_0/probe72] +connect_debug_port u_ila_0/probe72 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[31]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe73] +set_property port_width 32 [get_debug_ports u_ila_0/probe73] +connect_debug_port u_ila_0/probe73 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[31]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe74] +set_property port_width 5 [get_debug_ports u_ila_0/probe74] +connect_debug_port u_ila_0/probe74 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr2[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr2[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr2[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr2[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr2[4]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe75] +set_property port_width 5 [get_debug_ports u_ila_0/probe75] +connect_debug_port u_ila_0/probe75 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr1[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr1[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr1[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr1[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr1[4]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe76] +set_property port_width 32 [get_debug_ports u_ila_0/probe76] +connect_debug_port u_ila_0/probe76 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[31]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe77] +set_property port_width 32 [get_debug_ports u_ila_0/probe77] +connect_debug_port u_ila_0/probe77 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[31]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe78] +set_property port_width 32 [get_debug_ports u_ila_0/probe78] +connect_debug_port u_ila_0/probe78 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[31]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe79] +set_property port_width 32 [get_debug_ports u_ila_0/probe79] +connect_debug_port u_ila_0/probe79 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[31]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe80] +set_property port_width 32 [get_debug_ports u_ila_0/probe80] +connect_debug_port u_ila_0/probe80 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[31]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe81] +set_property port_width 4 [get_debug_ports u_ila_0/probe81] +connect_debug_port u_ila_0/probe81 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_wstrb[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_wstrb[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_wstrb[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_wstrb[3]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe82] +set_property port_width 4 [get_debug_ports u_ila_0/probe82] +connect_debug_port u_ila_0/probe82 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_len[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_len[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_len[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_len[3]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe83] +set_property port_width 4 [get_debug_ports u_ila_0/probe83] +connect_debug_port u_ila_0/probe83 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wstrb[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wstrb[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wstrb[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wstrb[3]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe84] +set_property port_width 3 [get_debug_ports u_ila_0/probe84] +connect_debug_port u_ila_0/probe84 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_size[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_size[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_size[2]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe85] +set_property port_width 4 [get_debug_ports u_ila_0/probe85] +connect_debug_port u_ila_0/probe85 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_len[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_len[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_len[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_len[3]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe86] +set_property port_width 32 [get_debug_ports u_ila_0/probe86] +connect_debug_port u_ila_0/probe86 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[31]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe87] +set_property port_width 20 [get_debug_ports u_ila_0/probe87] +connect_debug_port u_ila_0/probe87 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo1[PFN][0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo1[PFN][1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo1[PFN][2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo1[PFN][3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo1[PFN][4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo1[PFN][5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo1[PFN][6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo1[PFN][7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo1[PFN][8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo1[PFN][9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo1[PFN][10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo1[PFN][11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo1[PFN][12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo1[PFN][13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo1[PFN][14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo1[PFN][15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo1[PFN][16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo1[PFN][17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo1[PFN][18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo1[PFN][19]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe88] +set_property port_width 1 [get_debug_ports u_ila_0/probe88] +connect_debug_port u_ila_0/probe88 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_call]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe89] +set_property port_width 1 [get_debug_ports u_ila_0/probe89] +connect_debug_port u_ila_0/probe89 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_done]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe90] +set_property port_width 1 [get_debug_ports u_ila_0/probe90] +connect_debug_port u_ila_0/probe90 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_call]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe91] +set_property port_width 1 [get_debug_ports u_ila_0/probe91] +connect_debug_port u_ila_0/probe91 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_done]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe92] +set_property port_width 1 [get_debug_ports u_ila_0/probe92] +connect_debug_port u_ila_0/probe92 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo0[D]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe93] +set_property port_width 1 [get_debug_ports u_ila_0/probe93] +connect_debug_port u_ila_0/probe93 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo0[G]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe94] +set_property port_width 1 [get_debug_ports u_ila_0/probe94] +connect_debug_port u_ila_0/probe94 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo0[V]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe95] +set_property port_width 1 [get_debug_ports u_ila_0/probe95] +connect_debug_port u_ila_0/probe95 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo1[D]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe96] +set_property port_width 1 [get_debug_ports u_ila_0/probe96] +connect_debug_port u_ila_0/probe96 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo1[G]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe97] +set_property port_width 1 [get_debug_ports u_ila_0/probe97] +connect_debug_port u_ila_0/probe97 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/c0_EntryLo1[V]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe98] +set_property port_width 1 [get_debug_ports u_ila_0/probe98] +connect_debug_port u_ila_0/probe98 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_valid]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe99] +set_property port_width 1 [get_debug_ports u_ila_0/probe99] +connect_debug_port u_ila_0/probe99 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_valid]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe100] +set_property port_width 1 [get_debug_ports u_ila_0/probe100] +connect_debug_port u_ila_0/probe100 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/cp0/en]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe101] +set_property port_width 1 [get_debug_ports u_ila_0/probe101] +connect_debug_port u_ila_0/probe101 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_ERET]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe102] +set_property port_width 1 [get_debug_ports u_ila_0/probe102] +connect_debug_port u_ila_0/probe102 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_ExcValid]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe103] +set_property port_width 1 [get_debug_ports u_ila_0/probe103] +connect_debug_port u_ila_0/probe103 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr_ok]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe104] +set_property port_width 1 [get_debug_ports u_ila_0/probe104] +connect_debug_port u_ila_0/probe104 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_data_ok]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe105] +set_property port_width 1 [get_debug_ports u_ila_0/probe105] +connect_debug_port u_ila_0/probe105 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_req]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe106] +set_property port_width 1 [get_debug_ports u_ila_0/probe106] +connect_debug_port u_ila_0/probe106 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_req]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe107] +set_property port_width 1 [get_debug_ports u_ila_0/probe107] +connect_debug_port u_ila_0/probe107 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wr]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe108] +set_property port_width 1 [get_debug_ports u_ila_0/probe108] +connect_debug_port u_ila_0/probe108 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][D0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe109] +set_property port_width 1 [get_debug_ports u_ila_0/probe109] +connect_debug_port u_ila_0/probe109 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][D1]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe110] +set_property port_width 1 [get_debug_ports u_ila_0/probe110] +connect_debug_port u_ila_0/probe110 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][G]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe111] +set_property port_width 1 [get_debug_ports u_ila_0/probe111] +connect_debug_port u_ila_0/probe111 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][V0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe112] +set_property port_width 1 [get_debug_ports u_ila_0/probe112] +connect_debug_port u_ila_0/probe112 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[0][V1]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe113] +set_property port_width 1 [get_debug_ports u_ila_0/probe113] +connect_debug_port u_ila_0/probe113 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][D0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe114] +set_property port_width 1 [get_debug_ports u_ila_0/probe114] +connect_debug_port u_ila_0/probe114 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][D1]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe115] +set_property port_width 1 [get_debug_ports u_ila_0/probe115] +connect_debug_port u_ila_0/probe115 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][G]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe116] +set_property port_width 1 [get_debug_ports u_ila_0/probe116] +connect_debug_port u_ila_0/probe116 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][V0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe117] +set_property port_width 1 [get_debug_ports u_ila_0/probe117] +connect_debug_port u_ila_0/probe117 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[1][V1]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe118] +set_property port_width 1 [get_debug_ports u_ila_0/probe118] +connect_debug_port u_ila_0/probe118 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][D0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe119] +set_property port_width 1 [get_debug_ports u_ila_0/probe119] +connect_debug_port u_ila_0/probe119 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][D1]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe120] +set_property port_width 1 [get_debug_ports u_ila_0/probe120] +connect_debug_port u_ila_0/probe120 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][G]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe121] +set_property port_width 1 [get_debug_ports u_ila_0/probe121] +connect_debug_port u_ila_0/probe121 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][V0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe122] +set_property port_width 1 [get_debug_ports u_ila_0/probe122] +connect_debug_port u_ila_0/probe122 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[2][V1]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe123] +set_property port_width 1 [get_debug_ports u_ila_0/probe123] +connect_debug_port u_ila_0/probe123 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][D0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe124] +set_property port_width 1 [get_debug_ports u_ila_0/probe124] +connect_debug_port u_ila_0/probe124 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][D1]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe125] +set_property port_width 1 [get_debug_ports u_ila_0/probe125] +connect_debug_port u_ila_0/probe125 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][G]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe126] +set_property port_width 1 [get_debug_ports u_ila_0/probe126] +connect_debug_port u_ila_0/probe126 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][V0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe127] +set_property port_width 1 [get_debug_ports u_ila_0/probe127] +connect_debug_port u_ila_0/probe127 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[3][V1]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe128] +set_property port_width 1 [get_debug_ports u_ila_0/probe128] +connect_debug_port u_ila_0/probe128 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][D0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe129] +set_property port_width 1 [get_debug_ports u_ila_0/probe129] +connect_debug_port u_ila_0/probe129 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][D1]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe130] +set_property port_width 1 [get_debug_ports u_ila_0/probe130] +connect_debug_port u_ila_0/probe130 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][G]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe131] +set_property port_width 1 [get_debug_ports u_ila_0/probe131] +connect_debug_port u_ila_0/probe131 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][V0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe132] +set_property port_width 1 [get_debug_ports u_ila_0/probe132] +connect_debug_port u_ila_0/probe132 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[4][V1]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe133] +set_property port_width 1 [get_debug_ports u_ila_0/probe133] +connect_debug_port u_ila_0/probe133 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][D0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe134] +set_property port_width 1 [get_debug_ports u_ila_0/probe134] +connect_debug_port u_ila_0/probe134 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][D1]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe135] +set_property port_width 1 [get_debug_ports u_ila_0/probe135] +connect_debug_port u_ila_0/probe135 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][G]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe136] +set_property port_width 1 [get_debug_ports u_ila_0/probe136] +connect_debug_port u_ila_0/probe136 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][V0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe137] +set_property port_width 1 [get_debug_ports u_ila_0/probe137] +connect_debug_port u_ila_0/probe137 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[5][V1]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe138] +set_property port_width 1 [get_debug_ports u_ila_0/probe138] +connect_debug_port u_ila_0/probe138 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][D0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe139] +set_property port_width 1 [get_debug_ports u_ila_0/probe139] +connect_debug_port u_ila_0/probe139 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][D1]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe140] +set_property port_width 1 [get_debug_ports u_ila_0/probe140] +connect_debug_port u_ila_0/probe140 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][G]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe141] +set_property port_width 1 [get_debug_ports u_ila_0/probe141] +connect_debug_port u_ila_0/probe141 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][V0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe142] +set_property port_width 1 [get_debug_ports u_ila_0/probe142] +connect_debug_port u_ila_0/probe142 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[6][V1]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe143] +set_property port_width 1 [get_debug_ports u_ila_0/probe143] +connect_debug_port u_ila_0/probe143 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][D0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe144] +set_property port_width 1 [get_debug_ports u_ila_0/probe144] +connect_debug_port u_ila_0/probe144 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][D1]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe145] +set_property port_width 1 [get_debug_ports u_ila_0/probe145] +connect_debug_port u_ila_0/probe145 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][G]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe146] +set_property port_width 1 [get_debug_ports u_ila_0/probe146] +connect_debug_port u_ila_0/probe146 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][V0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe147] +set_property port_width 1 [get_debug_ports u_ila_0/probe147] +connect_debug_port u_ila_0/probe147 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/TLB_entries[7][V1]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe148] +set_property port_width 1 [get_debug_ports u_ila_0/probe148] +connect_debug_port u_ila_0/probe148 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/TLB/tlbw]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe149] +set_property port_width 1 [get_debug_ports u_ila_0/probe149] +connect_debug_port u_ila_0/probe149 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/we1]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe150] +set_property port_width 1 [get_debug_ports u_ila_0/probe150] +connect_debug_port u_ila_0/probe150 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/we2]] set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] diff --git a/src/CP0/CP0.sv b/src/CP0/CP0.sv index b796508..8fe3895 100644 --- a/src/CP0/CP0.sv +++ b/src/CP0/CP0.sv @@ -5,11 +5,11 @@ module CP0 ( input logic clk, input logic rst, - input logic [4:0] addr, - input logic [2:0] sel, - output word_t rdata, - input logic en, - input word_t wdata, + (*mark_debug="true"*)input logic [4:0] addr, + (*mark_debug="true"*)input logic [2:0] sel, + (*mark_debug="true"*)output word_t rdata, + (*mark_debug="true"*)input logic en, + (*mark_debug="true"*)input word_t wdata, // int input logic [5:0] ext_int, @@ -78,6 +78,12 @@ module CP0 ( assign rf_cp0.EBase.CPUNum = 10'b0; assign rf_cp0.PRId = 32'h42424242; + (*mark_debug="true"*)word_t CP0_compare; + (*mark_debug="true"*)word_t CP0_count; + assign CP0_compare = rf_cp0.Compare; + assign CP0_count = rf_cp0.Count; + + always_ff @(posedge clk) if (rst) begin rf_cp0.Config.K0 = 3'b011; diff --git a/src/Core/Datapath.sv b/src/Core/Datapath.sv index 5245a60..a8cc8ac 100644 --- a/src/Core/Datapath.sv +++ b/src/Core/Datapath.sv @@ -105,8 +105,8 @@ module Datapath ( logic D_IB_FT_W_I1; word_t D_IB_ForwardT; - logic D_IA_valid; - logic D_IB_valid; + (*mark_debug="true"*)logic D_IA_valid; + (*mark_debug="true"*)logic D_IB_valid; logic D_IA_ri; logic D_IB_ri; logic D_IA_cpu; @@ -280,8 +280,8 @@ module Datapath ( word_t M_I1_DataR; logic M_I1_CACHE_REQ; - word_t HI; - word_t LO; + (*mark_debug="true"*)word_t HI; + (*mark_debug="true"*)word_t LO; //---------------------------------------------------------------------------// // Pre Fetch // @@ -629,6 +629,19 @@ module Datapath ( // end // `endif +`ifdef ILA_DEBUG + + (*mark_debug="true"*)word_t D_IA_pc; + (*mark_debug="true"*)word_t D_IB_pc; + (*mark_debug="true"*)word_t D_IA_inst; + (*mark_debug="true"*)word_t D_IB_inst; + assign D_IA_pc = D.IA_pc; + assign D_IB_pc = D.IB_pc; + assign D_IA_inst = D.IA_inst; + assign D_IB_inst = D.IB_inst; + +`endif + assign D_I0_go = D.A ? D_IB_go : D_IA_go; assign D.I0.pc = D.A ? D.IB_pc : D.IA_pc; assign D.I0.ExcValid = D.A ? D.IB_ExcValid : D.IA_ExcValid; @@ -1258,6 +1271,19 @@ module Datapath ( M_exception.ERET & M.en }; +`ifdef ILA_DEBUG + (*mark_debug="true"*)logic EXC_ExcValid; + (*mark_debug="true"*)logic [4:0] EXC_ExcCode; + (*mark_debug="true"*)word_t EXC_BadVAddr; + (*mark_debug="true"*)word_t EXC_EPC; + (*mark_debug="true"*)logic EXC_ERET; + assign EXC_ExcValid = M_exception.ExcValid & M.en; + assign EXC_ExcCode = M_exception.ExcCode; + assign EXC_BadVAddr = M_exception.BadVAddr; + assign EXC_EPC = M_exception.EPC; + assign EXC_ERET = M_exception.ERET & M.en; +`endif + // M.I0.ALU mux4 #(32) M_I0_A_mux ( {27'b0, M.I0.sa}, diff --git a/src/Core/RF.sv b/src/Core/RF.sv index 49b2ad4..1da7af4 100644 --- a/src/Core/RF.sv +++ b/src/Core/RF.sv @@ -7,12 +7,12 @@ module RF ( input logic [4:0] raddr2, input logic [4:0] raddr3, input logic [4:0] raddr4, - input logic we1, - input logic we2, - input logic [4:0] waddr1, - input logic [4:0] waddr2, - input word_t wdata1, - input word_t wdata2, + (*mark_debug="true"*)input logic we1, + (*mark_debug="true"*)input logic we2, + (*mark_debug="true"*)input logic [4:0] waddr1, + (*mark_debug="true"*)input logic [4:0] waddr2, + (*mark_debug="true"*)input word_t wdata1, + (*mark_debug="true"*)input word_t wdata2, output word_t rdata1, output word_t rdata2, output word_t rdata3, diff --git a/src/MU/MU.sv b/src/MU/MU.sv index a9d55d6..aa38ce0 100644 --- a/src/MU/MU.sv +++ b/src/MU/MU.sv @@ -16,6 +16,41 @@ module MU ( CP0_i.mu cp0 ); +`ifdef ILA_DEBUG + (*mark_debug="true"*) logic MEM_req; + (*mark_debug="true"*) logic MEM_wr; + (*mark_debug="true"*) word_t MEM_addr; + (*mark_debug="true"*) logic [1:0] MEM_size; + (*mark_debug="true"*) logic [3:0] MEM_wstrb; + (*mark_debug="true"*) word_t MEM_wdata; + (*mark_debug="true"*) logic MEM_addr_ok; + (*mark_debug="true"*) logic MEM_data_ok; + (*mark_debug="true"*) word_t MEM_rdata; + (*mark_debug="true"*) logic MEM_prv_req; + (*mark_debug="true"*) word_t MEM_prv_addr; + + assign MEM_req = memory.req; + assign MEM_wr = memory.wr; + assign MEM_addr = memory.addr; + assign MEM_size = memory.size; + assign MEM_wstrb = memory.wstrb; + assign MEM_wdata = memory.wdata; + assign MEM_addr_ok = memory.addr_ok; + assign MEM_data_ok = memory.data_ok; + assign MEM_rdata = memory.rdata; + + always_ff @(posedge clk) + if (rst) begin + MEM_prv_req <= 0; + MEM_prv_addr <= 0; + end else begin + MEM_prv_req <= memory.req & memory.addr_ok; + if (memory.req & memory.addr_ok) + MEM_prv_addr <= memory.addr; + end + +`endif + // ============= // == CacheOp == // ============= @@ -281,12 +316,12 @@ module MU ( // =============== // input - logic amr_call; - word_t amr_addr; - logic [3:0] amr_len; - logic [2:0] amr_size; + (*mark_debug="true"*)logic amr_call; + (*mark_debug="true"*)word_t amr_addr; + (*mark_debug="true"*)logic [3:0] amr_len; + (*mark_debug="true"*)logic [2:0] amr_size; // output - logic amr_done; + (*mark_debug="true"*)logic amr_done; DCData_t amr_buffer; AXIReader #(`DC_DATA_LENGTH) @@ -306,14 +341,14 @@ module MU ( // ================ // input - logic amw_call; - word_t amw_addr; - logic [3:0] amw_len; - logic [2:0] amw_size; - logic [3:0] amw_wstrb; + (*mark_debug="true"*)logic amw_call; + (*mark_debug="true"*)word_t amw_addr; + (*mark_debug="true"*)logic [3:0] amw_len; + (*mark_debug="true"*)logic [2:0] amw_size; + (*mark_debug="true"*)logic [3:0] amw_wstrb; DCData_t amw_data; // output - logic amw_done; + (*mark_debug="true"*)logic amw_done; AXIWriter #(`DC_DATA_LENGTH) mem_writer ( @@ -549,8 +584,9 @@ module MU ( end else begin // uncached read - in_mem_ready = 1'b1; - dcache.index_for_lookup = memory.addr[`DC_TAGL-1:`DC_INDEXL]; + // in_mem_ready = 1'b1; + // dcache.index_for_lookup = memory.addr[`DC_TAGL-1:`DC_INDEXL]; + mem_wait_cache = 1'b1; mem_rdata_select_direct = 1'b1; mem_rdata_source_data = amr_buffer; end @@ -587,8 +623,9 @@ module MU ( mem_nxt_state = MEM_LOOKUP; // to CPU out_mem_valid = 1'b1; - in_mem_ready = 1'b1; - dcache.index_for_lookup = memory.addr[`DC_TAGL-1:`DC_INDEXL]; + // in_mem_ready = 1'b1; + // dcache.index_for_lookup = memory.addr[`DC_TAGL-1:`DC_INDEXL]; + mem_wait_cache = 1'b1; end end diff --git a/src/MU/TLB.sv b/src/MU/TLB.sv index 696c67a..2e18cba 100644 --- a/src/MU/TLB.sv +++ b/src/MU/TLB.sv @@ -7,13 +7,13 @@ module TLB ( // CP0 input logic [2:0] K0, - input logic tlbw, // TLBWI + TLBWR + (*mark_debug="true"*)input logic tlbw, // TLBWI + TLBWR input logic tlbp, // TLBP - input logic [2:0] c0_Index, // TLBWR + TLBWI + TLBR + (*mark_debug="true"*)input logic [2:0] c0_Index, // TLBWR + TLBWI + TLBR - input EntryHi_t c0_EntryHi, // TLBWI + F/M(ASID) - input EntryLo_t c0_EntryLo1, // TLBWI - input EntryLo_t c0_EntryLo0, // TLBWI + (*mark_debug="true"*)input EntryHi_t c0_EntryHi, // TLBWI + F/M(ASID) + (*mark_debug="true"*)input EntryLo_t c0_EntryLo1, // TLBWI + (*mark_debug="true"*)input EntryLo_t c0_EntryLo0, // TLBWI output EntryHi_t EntryHi, // TLBR output EntryLo_t EntryLo1, // TLBR @@ -52,7 +52,7 @@ module TLB ( Index_t Index0; - TLB_t [7:0] TLB_entries; + (*mark_debug="true"*)TLB_t [7:0] TLB_entries; TLB_t entry; // CP0(TLBWI) EntryHi EntryLo0 EntryLo1 -> TLB[Index] diff --git a/src/mycpu_top.sv b/src/mycpu_top.sv index 12fe650..07d6d70 100644 --- a/src/mycpu_top.sv +++ b/src/mycpu_top.sv @@ -84,7 +84,7 @@ module mycpu_top ( logic C0_we; word_t C0_wdata; - logic [5:0] ext_int_sync; + (*mark_debug="true"*)logic [5:0] ext_int_sync; always_ff @(posedge aclk) if (~aresetn) ext_int_sync <= 0; else ext_int_sync <= ext_int;