Test Passed? maybe
1. fix timing loop 2. fix multi driven 3. fix CACHE I-Cache Index logic 4. fix testcase
This commit is contained in:
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fa0c8ece07
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e08ded2242
@ -8,22 +8,49 @@ LEAF(n99_cache_icache_test)
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li s2, 0x0
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li s2, 0x0
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###test inst
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###test inst
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.n99_1_prepare:
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addi a1, zero, 0
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.n99_1:
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.n99_1:
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addi a0, zero, 0
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.n99_1_replace:
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nop # will be replaced with "addi a0, a0, 1" -> 20840001
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bne a0, a1, inst_error
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nop
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bne a1, zero, .n99_2_prepare # jump out 2nd
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nop
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addi a1, a1, 1
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.n99_1_work:
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la v0, .n99_1_replace
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la v0, .n99_1_replace
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li v1, 0x20840001
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li v1, 0x20840001
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li t0, 0x20000000
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subu v0, v0, t0 # v0 <- 9fcxxxxx
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sw v1, 0(v0)
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sw v1, 0(v0)
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cache 21, 0(v0) # D-Cache Hit WriteBack Invalid
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cache 21, 0(v0) # D-Cache Hit WriteBack Invalid
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cache 16, 0(v0) # I-Cache Hit Invalid
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cache 16, 0(v0) # I-Cache Hit Invalid
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addi a0, zero, 0
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# TODO: clear Datapath on CACHE
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addi a1, zero, 1
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# using enough nop to stop prefetch
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.n99_1_replace:
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nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop
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nop # line will be replaced with "addi a0, a0, 1" -> 20840001
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nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop
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bne a0, a1, inst_error
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j .n99_1
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nop
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nop
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.n99_2_prepare:
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addi a1, zero, 0
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.n99_2:
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.n99_2:
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addi a0, zero, 0
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.n99_2_replace:
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nop # will be replaced with "addi a0, a0, 1" -> 20840001
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bne a0, a1, inst_error
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nop
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bne a1, zero, .n99_3_prepare # jump out 2nd
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nop
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addi a1, a1, 1
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.n99_2_work:
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la v0, .n99_2_replace
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la v0, .n99_2_replace
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li v1, 0x20840001
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li v1, 0x20840001
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li t0, 0x20000000
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subu v0, v0, t0
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sw v1, 0(v0)
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sw v1, 0(v0)
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cache 21, 0(v0) # D-Cache Hit WriteBack Invalid
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cache 21, 0(v0) # D-Cache Hit WriteBack Invalid
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addi t0, zero, 0
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addi t0, zero, 0
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@ -31,21 +58,35 @@ LEAF(n99_cache_icache_test)
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.n99_2_loop:
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.n99_2_loop:
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beq t0, t1, .n99_2_check
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beq t0, t1, .n99_2_check
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nop
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nop
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add v0, t0, zero
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cache 0, 0(t0) # I-Cache Index Invalid
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cache 0, 0(v0) # I-Cache Index Invalid
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addi t0, t0, 1
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addi t0, t0, 1
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j .n99_2_loop
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j .n99_2_loop
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nop
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.n99_2_check:
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.n99_2_check:
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addi a0, zero, 0
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# TODO: clear Datapath on CACHE
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addi a1, zero, 1
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# using enough nop to stop prefetch
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.n99_2_replace:
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nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop
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nop # line will be replaced with "addi a0, a0, 1" -> 20840001
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nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop
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bne a0, a1, inst_error
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j .n99_2
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nop
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nop
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.n99_3_prepare:
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addi a1, zero, 0
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.n99_3:
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.n99_3:
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addi a0, zero, 0
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.n99_3_replace:
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nop # will be replaced with "addi a0, a0, 1" -> 20840001
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bne a0, a1, inst_error
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nop
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bne a1, zero, .n99_success # jump out 2nd
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nop
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addi a1, a1, 1
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.n99_3_work:
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la v0, .n99_3_replace
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la v0, .n99_3_replace
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li v1, 0x20840001
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li v1, 0x20840001
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li t0, 0x20000000
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subu v0, v0, t0
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sw v1, 0(v0)
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sw v1, 0(v0)
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cache 21, 0(v0) # D-Cache Hit WriteBack Invalid
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cache 21, 0(v0) # D-Cache Hit WriteBack Invalid
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addi t0, zero, 0
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addi t0, zero, 0
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@ -53,16 +94,19 @@ LEAF(n99_cache_icache_test)
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.n99_3_loop:
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.n99_3_loop:
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beq t0, t1, .n99_3_check
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beq t0, t1, .n99_3_check
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nop
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nop
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add v0, t0, zero
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cache 0, 0(t0) # I-Cache Index Invalid
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cache 8, 0(v0) # I-Cache Index Store Tag
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addi t0, t0, 1
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addi t0, t0, 1
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j .n99_3_loop
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j .n99_3_loop
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nop
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.n99_3_check:
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.n99_3_check:
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addi a0, zero, 0
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# TODO: clear Datapath on CACHE
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addi a1, zero, 1
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# using enough nop to stop prefetch
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.n99_3_replace:
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nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop
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nop # line will be replaced with "addi a0, a0, 1" -> 20840001
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nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop
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bne a0, a1, inst_error
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j .n99_3
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nop
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.n99_success:
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nop
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nop
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###detect exception
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###detect exception
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@ -299,6 +299,26 @@ inst_test:
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nop #####
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nop #####
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kseg0_kseg1:
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kseg0_kseg1:
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jal n98_cache_dcache_test
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nop
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jal wait_1s
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nop
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la t1, n99_kseg1_kseg0
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li t2, 0x20000000
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subu t9, t1, t2
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jr t9
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nop
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n99_kseg1_kseg0:
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jal n99_cache_icache_test
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nop
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jal wait_1s
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nop
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la t9, n99_kseg0_kseg1
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jr t9
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nop
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n99_kseg0_kseg1:
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jal n2_addu_test #addu
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jal n2_addu_test #addu
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nop
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nop
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jal wait_1s
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jal wait_1s
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@ -683,25 +703,6 @@ kseg0_kseg1:
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nop
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nop
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jal wait_1s
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jal wait_1s
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nop
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nop
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jal n98_cache_dcache_test
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nop
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jal wait_1s
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nop
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la t1, n99_kseg1_kseg0
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li t2, 0x20000000
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subu t9, t1, t2
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jr t9
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nop
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n99_kseg1_kseg0:
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jal n99_cache_icache_test
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nop
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jal wait_1s
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nop
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la t9, n99_kseg0_kseg1
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jr t9
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nop
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n99_kseg0_kseg1:
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###check io access
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###check io access
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LI (a0, IO_SIMU_ADDR)
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LI (a0, IO_SIMU_ADDR)
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@ -115,7 +115,7 @@ module CP0 (
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rf_cp0.EntryLo0.V = 1'b0;
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rf_cp0.EntryLo0.V = 1'b0;
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rf_cp0.EntryLo0.G = 1'b0;
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rf_cp0.EntryLo0.G = 1'b0;
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rf_cp0.Index.P = 1'b0;
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rf_cp0.Index.P = 1'b0;
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rf_cp0.Index.Index = 2'b0;
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rf_cp0.Index.Index = 3'b0;
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rf_cp0.Random.Random = 3'b111;
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rf_cp0.Random.Random = 3'b111;
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rf_cp0.EBase.EBase = 18'b0;
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rf_cp0.EBase.EBase = 18'b0;
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@ -166,7 +166,7 @@ module CP0 (
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9: rf_cp0.Count = wdata;
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9: rf_cp0.Count = wdata;
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8: rf_cp0.BadVAddr = wdata;
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8: rf_cp0.BadVAddr = wdata;
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// 7: rf_cp0.HWREna = wdata;
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// 7: rf_cp0.HWREna = wdata;
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6: rf_cp0.Wired = wdata[2:0];
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6: rf_cp0.Wired = {29'b0, wdata[2:0]};
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// 5: rf_cp0.PageMask.Mask = wdata[24:13];
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// 5: rf_cp0.PageMask.Mask = wdata[24:13];
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// 4: rf_cp0.Context = wdata;
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// 4: rf_cp0.Context = wdata;
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3: begin
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3: begin
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@ -241,10 +241,10 @@ module DCache (
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assign DataRAM2.wen = (bwe1 & wen[2]) | (bwe2 & wen2[2]);
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assign DataRAM2.wen = (bwe1 & wen[2]) | (bwe2 & wen2[2]);
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assign DataRAM3.wen = (bwe1 & wen[3]) | (bwe2 & wen2[3]);
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assign DataRAM3.wen = (bwe1 & wen[3]) | (bwe2 & wen2[3]);
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// 写数据
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// 写数据
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assign TagRAM0.wdata = port.clear ? `DC_TAG_LENGTH'b0 : {port.tag1, port.wvalid, 1'b1};
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assign TagRAM0.wdata = {port.tag1, port.wvalid, ~port.clear};
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assign TagRAM1.wdata = port.clear ? `DC_TAG_LENGTH'b0 : {port.tag1, port.wvalid, 1'b1};
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assign TagRAM1.wdata = {port.tag1, port.wvalid, ~port.clear};
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assign TagRAM2.wdata = port.clear ? `DC_TAG_LENGTH'b0 : {port.tag1, port.wvalid, 1'b1};
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assign TagRAM2.wdata = {port.tag1, port.wvalid, ~port.clear};
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assign TagRAM3.wdata = port.clear ? `DC_TAG_LENGTH'b0 : {port.tag1, port.wvalid, 1'b1};
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assign TagRAM3.wdata = {port.tag1, port.wvalid, ~port.clear};
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assign DataRAM0.wdata = state == LOOKUP ? wdata1[0] : wdata2[0];
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assign DataRAM0.wdata = state == LOOKUP ? wdata1[0] : wdata2[0];
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assign DataRAM1.wdata = state == LOOKUP ? wdata1[1] : wdata2[1];
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assign DataRAM1.wdata = state == LOOKUP ? wdata1[1] : wdata2[1];
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@ -176,23 +176,23 @@ module ICache (
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assign DataRAM2.addr = baddr;
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assign DataRAM2.addr = baddr;
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assign DataRAM3.addr = baddr;
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assign DataRAM3.addr = baddr;
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// 写使能
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// 写使能
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assign TagRAM0.wen = bwe & wen2[0];
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assign TagRAM0.wen = bwe & wen2[0] | port.clear & wen[0];
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assign TagRAM1.wen = bwe & wen2[1];
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assign TagRAM1.wen = bwe & wen2[1] | port.clear & wen[1];
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assign TagRAM2.wen = bwe & wen2[2];
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assign TagRAM2.wen = bwe & wen2[2] | port.clear & wen[2];
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assign TagRAM3.wen = bwe & wen2[3];
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assign TagRAM3.wen = bwe & wen2[3] | port.clear & wen[3];
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assign DataRAM0.wen = bwe & wen2[0];
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assign DataRAM0.wen = bwe & wen2[0] | port.clear & wen[0];
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assign DataRAM1.wen = bwe & wen2[1];
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assign DataRAM1.wen = bwe & wen2[1] | port.clear & wen[1];
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assign DataRAM2.wen = bwe & wen2[2];
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assign DataRAM2.wen = bwe & wen2[2] | port.clear & wen[2];
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assign DataRAM3.wen = bwe & wen2[3];
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assign DataRAM3.wen = bwe & wen2[3] | port.clear & wen[3];
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// 写数据
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// 写数据
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assign TagRAM0.wdata = {port.tag1, 1'b1};
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assign TagRAM0.wdata = {port.tag1, ~port.clear};
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assign TagRAM1.wdata = {port.tag1, 1'b1};
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assign TagRAM1.wdata = {port.tag1, ~port.clear};
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assign TagRAM2.wdata = {port.tag1, 1'b1};
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assign TagRAM2.wdata = {port.tag1, ~port.clear};
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assign TagRAM3.wdata = {port.tag1, 1'b1};
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assign TagRAM3.wdata = {port.tag1, ~port.clear};
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assign DataRAM0.wdata = port.clear ? `IC_TAG_LENGTH'b0 : port.rdata;
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assign DataRAM0.wdata = port.rdata;
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assign DataRAM1.wdata = port.clear ? `IC_TAG_LENGTH'b0 : port.rdata;
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assign DataRAM1.wdata = port.rdata;
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assign DataRAM2.wdata = port.clear ? `IC_TAG_LENGTH'b0 : port.rdata;
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assign DataRAM2.wdata = port.rdata;
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assign DataRAM3.wdata = port.clear ? `IC_TAG_LENGTH'b0 : port.rdata;
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assign DataRAM3.wdata = port.rdata;
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ICTag_bram tag_ram0 (
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ICTag_bram tag_ram0 (
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.addra(TagRAM0.addr),
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.addra(TagRAM0.addr),
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@ -1,6 +1,8 @@
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`include "defines.svh"
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`include "defines.svh"
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`include "sram.svh"
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`include "sram.svh"
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`include "CP0.svh"
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`include "CP0.svh"
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`include "ICache.svh"
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`include "DCache.svh"
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module Datapath (
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module Datapath (
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input clk,
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input clk,
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@ -97,6 +97,10 @@ module MMU (
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word_t iD1, iD2, iD3, iD4, iD5, iD6, iD7;
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word_t iD1, iD2, iD3, iD4, iD5, iD6, iD7;
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logic diReq;
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CacheOp_t cacheOp1, cacheOp2;
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word_t dVA1;
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// ================================
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// ================================
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// ======== iState Machine ========
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// ======== iState Machine ========
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// ================================
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// ================================
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@ -183,7 +187,7 @@ module MMU (
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/*
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/*
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* I-Cache Cache指令实现备注:
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* I-Cache Cache指令实现备注:
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* 在进入 I_CACHE 状态时需确保 iEn == 0
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* 在进入 I_CACHE 状态时需确保 iEn == 0
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* 跳出 I_CACHE 状态时 iEn = 1
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* 跳出 I_CACHE 状态时 iEn = 0
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* 注意处理 Exceptions
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* 注意处理 Exceptions
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* TLB 转换请求在 iNextState == I_CACHE时发送
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* TLB 转换请求在 iNextState == I_CACHE时发送
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* I-Cache 查询请求在 iNextState == I_CACHE时发送
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* I-Cache 查询请求在 iNextState == I_CACHE时发送
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@ -192,8 +196,9 @@ module MMU (
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* drState 状态机同步
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* drState 状态机同步
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*/
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*/
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if (~iTLBRefill & ~iTLBInvalid & iCached1 & (ic.hit | cacheOp1[1])) ic.clear = 1;
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if (~iTLBRefill & ~iTLBInvalid & (iCached1 & ic.hit | cacheOp1[1])) ic.clear = 1;
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iEn = 1;
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iEn = 0;
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iEn2 = 1;
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iNextState = I_IDLE;
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iNextState = I_IDLE;
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end
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end
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endcase
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endcase
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@ -219,7 +224,7 @@ module MMU (
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// ========== iFunction ==========
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// ========== iFunction ==========
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// ===============================
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// ===============================
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assign iVA = iNextState == I_CACHE ? data.addr : inst.addr;
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assign iVA = iNextState == I_CACHE ? dVA1 : inst.addr;
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assign iValid1 = iReq1 & iHit1 & iMValid1 & (in_kernel | iUser1);
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assign iValid1 = iReq1 & iHit1 & iMValid1 & (in_kernel | iUser1);
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assign inst.addr_ok = iEn;
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assign inst.addr_ok = iEn;
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@ -234,12 +239,11 @@ module MMU (
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);
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);
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// I-Cache req on inst query or cache instruction
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// I-Cache req on inst query or cache instruction
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assign ic.req = iEn | iNextState == I_CACHE;
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assign ic.req = iEn & iState != I_CACHE | iNextState == I_CACHE;
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assign ic.valid = iValid1 & iCached1;
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assign ic.valid = iValid1 & iCached1;
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assign ic.index = iVA[`IC_TAGL-1:`IC_INDEXL];
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assign ic.index = iVA[`IC_TAGL-1:`IC_INDEXL];
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||||||
assign ic.tag1 = iEn2 ? iPA1[31:`IC_TAGL] : iPA2[31:`IC_TAGL];
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assign ic.tag1 = iEn2 ? iPA1[31:`IC_TAGL] : iPA2[31:`IC_TAGL];
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assign ic.rvalid = inst_axi.rvalid & inst_axi.data_ok;
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assign ic.rvalid = inst_axi.rvalid & inst_axi.data_ok;
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assign ic.clear = iState == I_CACHE & ~cacheOp1[2] & iCached1 & (ic.hit | cacheOp1[1]);
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||||||
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mux4 #(256) ic_rdata_mux (
|
mux4 #(256) ic_rdata_mux (
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{inst_axi.rdata, iD7, iD6, iD5, iD4, iD3, iD2, iD1},
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{inst_axi.rdata, iD7, iD6, iD5, iD4, iD3, iD2, iD1},
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@ -254,8 +258,8 @@ module MMU (
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assign inst_axi.len = (iEn2 ? iCached1 : iCached2) ? 4'b0111 : 4'b0001;
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assign inst_axi.len = (iEn2 ? iCached1 : iCached2) ? 4'b0111 : 4'b0001;
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assign inst_axi.size = 3'b010;
|
assign inst_axi.size = 3'b010;
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||||||
|
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||||||
assign iTLBRefill = (iState == I_IDLE & iReq1 | iState == I_CACHE & ~cacheOp[1]) & ~iHit1;
|
assign iTLBRefill = (iState == I_IDLE & iReq1 | iState == I_CACHE & ~cacheOp1[1]) & ~iHit1;
|
||||||
assign iTLBInvalid = (iState == I_IDLE & iReq1 | iState == I_CACHE & ~cacheOp[1]) & ~iMValid1;
|
assign iTLBInvalid = (iState == I_IDLE & iReq1 | iState == I_CACHE & ~cacheOp1[1]) & ~iMValid1;
|
||||||
assign iAddressError = (iState == I_IDLE) & iReq1 & ~in_kernel & ~iUser1;
|
assign iAddressError = (iState == I_IDLE) & iReq1 & ~in_kernel & ~iUser1;
|
||||||
|
|
||||||
// ======================
|
// ======================
|
||||||
@ -265,7 +269,7 @@ module MMU (
|
|||||||
word_t dVA;
|
word_t dVA;
|
||||||
|
|
||||||
logic dEn;
|
logic dEn;
|
||||||
logic dReq1, dcReq1, diReq;
|
logic dReq1, dcReq1;
|
||||||
logic dHit1;
|
logic dHit1;
|
||||||
logic dCached1, dCached2;
|
logic dCached1, dCached2;
|
||||||
logic dDirty1;
|
logic dDirty1;
|
||||||
@ -275,8 +279,6 @@ module MMU (
|
|||||||
word_t dPA1, dPA2;
|
word_t dPA1, dPA2;
|
||||||
logic [1:0] dSize1;
|
logic [1:0] dSize1;
|
||||||
|
|
||||||
CacheOp_t cacheOp1, cacheOp2;
|
|
||||||
|
|
||||||
logic dEn2;
|
logic dEn2;
|
||||||
logic dwr1;
|
logic dwr1;
|
||||||
logic [3:0] dWstrb1;
|
logic [3:0] dWstrb1;
|
||||||
@ -294,6 +296,7 @@ module MMU (
|
|||||||
|
|
||||||
ffenr #(1) dvalid_ff (clk, rst, data.req, dEn, dReq1);
|
ffenr #(1) dvalid_ff (clk, rst, data.req, dEn, dReq1);
|
||||||
ffen #(2) dsize_ff (clk, data.size, dEn, dSize1);
|
ffen #(2) dsize_ff (clk, data.size, dEn, dSize1);
|
||||||
|
ffen #(32) dVA1_ff (clk, data.addr, dEn, dVA1);
|
||||||
ffen #(32) dPA_ff (clk, dPA1, dEn2, dPA2);
|
ffen #(32) dPA_ff (clk, dPA1, dEn2, dPA2);
|
||||||
ffen #(1) dCached_ff (clk, dCached1, dEn2, dCached2);
|
ffen #(1) dCached_ff (clk, dCached1, dEn2, dCached2);
|
||||||
ffen #(1) dwr_ff (clk, data.wr, dEn2, dwr1);
|
ffen #(1) dwr_ff (clk, data.wr, dEn2, dwr1);
|
||||||
@ -322,8 +325,8 @@ module MMU (
|
|||||||
rdata_axi.req = 0;
|
rdata_axi.req = 0;
|
||||||
case (drState)
|
case (drState)
|
||||||
DR_IDLE: begin
|
DR_IDLE: begin
|
||||||
if (~dValid1) dEn = 1;
|
if (diReq) drNextState = DR_CACHE;
|
||||||
else if (~dcReq1) drNextState = DR_CACHE;
|
else if (~dValid1) dEn = 1;
|
||||||
else begin
|
else begin
|
||||||
dEn2 = 1;
|
dEn2 = 1;
|
||||||
if (data.wr) data.data_ok = 1;
|
if (data.wr) data.data_ok = 1;
|
||||||
@ -407,9 +410,8 @@ module MMU (
|
|||||||
*/
|
*/
|
||||||
|
|
||||||
assign dVA = data.addr;
|
assign dVA = data.addr;
|
||||||
assign diReq = dEn ? data.req & ~cacheOp[2] & |cacheOp[1:0]
|
assign diReq = dReq1 & ~cacheOp1[2] & |cacheOp1[1:0];
|
||||||
: dReq1 & ~cacheOp1[2] & |cacheOp1[1:0];
|
assign dcReq1 = dReq1 & (cacheOp1 == CNOP | cacheOp1[2]); // exclude I-Cache clear
|
||||||
assign dcReq1 = dReq1 & (cacheOp1 == CNOP | cacheOp[2]); // exclude I-Cache clear
|
|
||||||
assign dValid1 = dReq1 & dHit1 & dMValid1 & (~data.wr | dDirty1) & (in_kernel | dUser1);
|
assign dValid1 = dReq1 & dHit1 & dMValid1 & (~data.wr | dDirty1) & (in_kernel | dUser1);
|
||||||
|
|
||||||
assign dTLBRefill = drState == DR_IDLE & dcReq1 & (cacheOp1 == CNOP | ~cacheOp1[1]) & ~dHit1;
|
assign dTLBRefill = drState == DR_IDLE & dcReq1 & (cacheOp1 == CNOP | ~cacheOp1[1]) & ~dHit1;
|
||||||
@ -457,6 +459,8 @@ module MMU (
|
|||||||
|
|
||||||
// do not request when handling CACHE instruction on I-Cache
|
// do not request when handling CACHE instruction on I-Cache
|
||||||
assign dc.req = dEn & (cacheOp[2] | ~|cacheOp[1:0]);
|
assign dc.req = dEn & (cacheOp[2] | ~|cacheOp[1:0]);
|
||||||
|
// TODO: 在实现 CACHE 指令的 D-Cache Index 功能时应替换成下面注释的内容
|
||||||
|
// assign dc.valid = dValid1 & (dCached1 & (~cacheOp1[2] | dc.hit) | cacheOp1[1]);
|
||||||
assign dc.valid = dValid1 & dCached1 & (~cacheOp1[2] | cacheOp1[1] | dc.hit);
|
assign dc.valid = dValid1 & dCached1 & (~cacheOp1[2] | cacheOp1[1] | dc.hit);
|
||||||
assign dc.index = dVA[`DC_TAGL-1:`DC_INDEXL];
|
assign dc.index = dVA[`DC_TAGL-1:`DC_INDEXL];
|
||||||
assign dc.tag1 = dEn2 ? dPA1[31:`DC_TAGL] : dPA2[31:`DC_TAGL];
|
assign dc.tag1 = dEn2 ? dPA1[31:`DC_TAGL] : dPA2[31:`DC_TAGL];
|
||||||
|
@ -6,7 +6,7 @@
|
|||||||
// IC for I-Cache
|
// IC for I-Cache
|
||||||
`define IC_TAGL 11
|
`define IC_TAGL 11
|
||||||
`define IC_INDEXL 5
|
`define IC_INDEXL 5
|
||||||
`define IC_TAG_LENGTH (32-`IC_TAGL+1) // Tag + Valid
|
`define IC_TAG_LENGTH 22 // Tag + Valid
|
||||||
`define IC_DATA_LENGTH 256 // 32Bytes
|
`define IC_DATA_LENGTH 256 // 32Bytes
|
||||||
|
|
||||||
typedef logic [`IC_DATA_LENGTH-1:0] ICData_t;
|
typedef logic [`IC_DATA_LENGTH-1:0] ICData_t;
|
||||||
|
Loading…
Reference in New Issue
Block a user