Minimize CP0 when TLB is disabled
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baa2bb049f
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@ -44,6 +44,7 @@ module CP0 (
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assign rf_cp0.Status.zero2 = 6'b0;
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assign rf_cp0.Status.zero2 = 6'b0;
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assign rf_cp0.Status.zero3 = 3'b0;
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assign rf_cp0.Status.zero3 = 3'b0;
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assign rf_cp0.Status.zero4 = 2'b0;
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assign rf_cp0.Status.zero4 = 2'b0;
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`ifdef ENABLE_TLB
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assign rf_cp0.EntryHi.zero = 5'b0;
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assign rf_cp0.EntryHi.zero = 5'b0;
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assign rf_cp0.Wired.zero = 29'b0;
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assign rf_cp0.Wired.zero = 29'b0;
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assign rf_cp0.Context.zero = 4'b0;
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assign rf_cp0.Context.zero = 4'b0;
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@ -51,18 +52,7 @@ module CP0 (
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assign rf_cp0.EntryLo0.zero = 6'b0;
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assign rf_cp0.EntryLo0.zero = 6'b0;
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assign rf_cp0.Random.zero = 29'b0;
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assign rf_cp0.Random.zero = 29'b0;
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assign rf_cp0.Index.zero = 28'b0;
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assign rf_cp0.Index.zero = 28'b0;
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`endif
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// Vol III Figure 9-1
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// | 31 | 30...25 | 24...22 | 21...19 | 18...16 |
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// | Config2 | MMU SIZE | iCache sets per way | iCache line size | iCache associativity |
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// | 15...13 | 12...10 | 9...7 |
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// | dCache sets per way | dCache line size | dCache associativity |
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// | 6 | 5 | 4 |
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// | Coprocessor 2 implemented | MD | Performance Counter registers |
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// | 3 | 2 |
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// | Watch registers implemented | Code compression implemented |
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// | 1 | 0 |
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// | EJTAG implemented | FPU implemented |
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/*verilator lint_off WIDTH*/
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/*verilator lint_off WIDTH*/
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assign rf_cp0.Config1.Config2 = 1'b0;
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assign rf_cp0.Config1.Config2 = 1'b0;
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@ -104,10 +94,13 @@ module CP0 (
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rf_cp0.Status.EXL = 1'b0;
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rf_cp0.Status.EXL = 1'b0;
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rf_cp0.Status.IE = 1'b0;
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rf_cp0.Status.IE = 1'b0;
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rf_cp0.Compare = 32'h0;
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rf_cp0.Compare = 32'h0;
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`ifdef ENABLE_TLB
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rf_cp0.EntryHi.VPN2 = 19'b0;
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rf_cp0.EntryHi.VPN2 = 19'b0;
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rf_cp0.EntryHi.ASID = 8'b0;
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rf_cp0.EntryHi.ASID = 8'b0;
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`endif
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rf_cp0.Count = 32'h0;
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rf_cp0.Count = 32'h0;
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rf_cp0.BadVAddr = 32'h0;
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rf_cp0.BadVAddr = 32'h0;
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`ifdef ENABLE_TLB
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rf_cp0.Wired.Wired = 3'b0;
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rf_cp0.Wired.Wired = 3'b0;
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rf_cp0.Context.PTEBase = 9'b0;
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rf_cp0.Context.PTEBase = 9'b0;
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rf_cp0.Context.BadVPN2 = 19'b0;
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rf_cp0.Context.BadVPN2 = 19'b0;
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@ -124,6 +117,7 @@ module CP0 (
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rf_cp0.Index.P = 1'b0;
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rf_cp0.Index.P = 1'b0;
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rf_cp0.Index.Index = 3'b0;
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rf_cp0.Index.Index = 3'b0;
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rf_cp0.Random.Random = 3'b111;
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rf_cp0.Random.Random = 3'b111;
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`endif
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rf_cp0.EBase.EBase = 18'b0;
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rf_cp0.EBase.EBase = 18'b0;
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@ -133,8 +127,11 @@ module CP0 (
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count_lo = ~count_lo;
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count_lo = ~count_lo;
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if (count_lo == 1) rf_cp0.Count = rf_cp0.Count + 1;
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if (count_lo == 1) rf_cp0.Count = rf_cp0.Count + 1;
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`ifdef ENABLE_TLB
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rf_cp0.Random.Random = &rf_cp0.Random.Random ? rf_cp0.Wired.Wired
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rf_cp0.Random.Random = &rf_cp0.Random.Random ? rf_cp0.Wired.Wired
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: rf_cp0.Random.Random + 1'b1;
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: rf_cp0.Random.Random + 1'b1;
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`endif
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if (en) begin
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if (en) begin
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case (addr)
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case (addr)
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// 31: rf_cp0.DESAVE = wdata;
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// 31: rf_cp0.DESAVE = wdata;
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@ -169,13 +166,16 @@ module CP0 (
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rf_cp0.Cause.TI = 0;
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rf_cp0.Cause.TI = 0;
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rf_cp0.Compare = wdata;
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rf_cp0.Compare = wdata;
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end
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end
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`ifdef ENABLE_TLB
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10: begin
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10: begin
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rf_cp0.EntryHi.VPN2 = wdata[31:13];
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rf_cp0.EntryHi.VPN2 = wdata[31:13];
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rf_cp0.EntryHi.ASID = wdata[7:0];
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rf_cp0.EntryHi.ASID = wdata[7:0];
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end
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end
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`endif
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9: rf_cp0.Count = wdata;
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9: rf_cp0.Count = wdata;
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8: rf_cp0.BadVAddr = wdata;
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8: rf_cp0.BadVAddr = wdata;
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// 7: rf_cp0.HWREna = wdata;
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// 7: rf_cp0.HWREna = wdata;
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`ifdef ENABLE_TLB
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6: begin
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6: begin
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rf_cp0.Wired.Wired = wdata[2:0];
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rf_cp0.Wired.Wired = wdata[2:0];
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rf_cp0.Random.Random = 3'b111;
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rf_cp0.Random.Random = 3'b111;
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@ -202,11 +202,13 @@ module CP0 (
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0: begin
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0: begin
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rf_cp0.Index.Index = wdata[2:0];
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rf_cp0.Index.Index = wdata[2:0];
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end
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end
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`endif
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default: begin
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default: begin
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end
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end
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endcase
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endcase
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end
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end
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`ifdef ENABLE_TLB
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if (c0.cpu_tlbr) begin
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if (c0.cpu_tlbr) begin
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rf_cp0.EntryHi.VPN2 = c0.tlb_EntryHi.VPN2;
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rf_cp0.EntryHi.VPN2 = c0.tlb_EntryHi.VPN2;
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rf_cp0.EntryHi.ASID = c0.tlb_EntryHi.ASID;
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rf_cp0.EntryHi.ASID = c0.tlb_EntryHi.ASID;
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@ -227,6 +229,7 @@ module CP0 (
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rf_cp0.Index.P = c0.tlb_Index.P;
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rf_cp0.Index.P = c0.tlb_Index.P;
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rf_cp0.Index.Index = c0.tlb_Index.Index;
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rf_cp0.Index.Index = c0.tlb_Index.Index;
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end
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end
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`endif
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if (rf_cp0.Count == rf_cp0.Compare) rf_cp0.Cause.TI = 1;
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if (rf_cp0.Count == rf_cp0.Compare) rf_cp0.Cause.TI = 1;
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@ -247,12 +250,14 @@ module CP0 (
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rf_cp0.BadVAddr = c0.cpu_exception.BadVAddr;
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rf_cp0.BadVAddr = c0.cpu_exception.BadVAddr;
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end
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end
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`ifdef ENABLE_TLB
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if ( c0.cpu_exception.ExcCode == `EXCCODE_MOD
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if ( c0.cpu_exception.ExcCode == `EXCCODE_MOD
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| c0.cpu_exception.ExcCode == `EXCCODE_TLBL
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| c0.cpu_exception.ExcCode == `EXCCODE_TLBL
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| c0.cpu_exception.ExcCode == `EXCCODE_TLBS) begin
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| c0.cpu_exception.ExcCode == `EXCCODE_TLBS) begin
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rf_cp0.Context.BadVPN2 = c0.cpu_exception.BadVAddr[31:13];
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rf_cp0.Context.BadVPN2 = c0.cpu_exception.BadVAddr[31:13];
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rf_cp0.EntryHi.VPN2 = c0.cpu_exception.BadVAddr[31:13];
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rf_cp0.EntryHi.VPN2 = c0.cpu_exception.BadVAddr[31:13];
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end
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end
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`endif
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end
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end
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end
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end
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@ -282,10 +287,13 @@ module CP0 (
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13: rdata = rf_cp0.Cause;
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13: rdata = rf_cp0.Cause;
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12: rdata = rf_cp0.Status;
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12: rdata = rf_cp0.Status;
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11: rdata = rf_cp0.Compare;
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11: rdata = rf_cp0.Compare;
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`ifdef ENABLE_TLB
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10: rdata = rf_cp0.EntryHi;
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10: rdata = rf_cp0.EntryHi;
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`endif
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9: rdata = rf_cp0.Count;
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9: rdata = rf_cp0.Count;
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8: rdata = rf_cp0.BadVAddr;
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8: rdata = rf_cp0.BadVAddr;
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// 7: rdata = rf_cp0.HWREna;
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// 7: rdata = rf_cp0.HWREna;
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`ifdef ENABLE_TLB
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6: rdata = rf_cp0.Wired;
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6: rdata = rf_cp0.Wired;
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// 5: rdata = rf_cp0.PageMask;
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// 5: rdata = rf_cp0.PageMask;
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5: rdata = 32'h0;
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5: rdata = 32'h0;
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@ -294,6 +302,7 @@ module CP0 (
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2: rdata = rf_cp0.EntryLo0;
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2: rdata = rf_cp0.EntryLo0;
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1: rdata = rf_cp0.Random;
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1: rdata = rf_cp0.Random;
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0: rdata = rf_cp0.Index;
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0: rdata = rf_cp0.Index;
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`endif
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default: rdata = 32'h0;
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default: rdata = 32'h0;
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endcase
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endcase
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@ -303,12 +312,19 @@ module CP0 (
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assign c0.cp0_K0 = rf_cp0.Config.K0;
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assign c0.cp0_K0 = rf_cp0.Config.K0;
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assign c0.cp0_CU = rf_cp0.Status.CU;
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assign c0.cp0_CU = rf_cp0.Status.CU;
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`ifdef ENABLE_TLB
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assign c0.cp0_Random = rf_cp0.Random;
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assign c0.cp0_Random = rf_cp0.Random;
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assign c0.cp0_Index = rf_cp0.Index;
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assign c0.cp0_Index = rf_cp0.Index;
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assign c0.cp0_EntryHi = rf_cp0.EntryHi;
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assign c0.cp0_EntryHi = rf_cp0.EntryHi;
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// assign PageMask = rf_cp0.PageMask;
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assign c0.cp0_EntryLo1 = rf_cp0.EntryLo1;
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assign c0.cp0_EntryLo1 = rf_cp0.EntryLo1;
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assign c0.cp0_EntryLo0 = rf_cp0.EntryLo0;
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assign c0.cp0_EntryLo0 = rf_cp0.EntryLo0;
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`else
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assign c0.cp0_Random = 0;
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assign c0.cp0_Index = 0;
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assign c0.cp0_EntryHi = 0;
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assign c0.cp0_EntryLo1 = 0;
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assign c0.cp0_EntryLo0 = 0;
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`endif
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assign c0.cp0_in_kernel = ~rf_cp0.Status.UM | rf_cp0.Status.EXL; // currently no ERL
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assign c0.cp0_in_kernel = ~rf_cp0.Status.UM | rf_cp0.Status.EXL; // currently no ERL
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@ -134,17 +134,19 @@ typedef struct packed {
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CP0_REGS_CAUSE_t Cause;
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CP0_REGS_CAUSE_t Cause;
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CP0_REGS_STATUS_t Status;
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CP0_REGS_STATUS_t Status;
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word_t Compare;
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word_t Compare;
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`ifdef ENABLE_TLB
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EntryHi_t EntryHi;
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EntryHi_t EntryHi;
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`endif
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word_t Count;
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word_t Count;
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word_t BadVAddr;
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word_t BadVAddr;
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// HWREna
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`ifdef ENABLE_TLB
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Wired_t Wired;
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Wired_t Wired;
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Context_t Context;
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Context_t Context;
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// word_t PageMask;
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EntryLo_t EntryLo1;
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EntryLo_t EntryLo1;
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EntryLo_t EntryLo0;
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EntryLo_t EntryLo0;
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Random_t Random;
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Random_t Random;
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Index_t Index;
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Index_t Index;
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`endif
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// ==== sel1 ====
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// ==== sel1 ====
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CP0_REGS_CONFIG1_t Config1;
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CP0_REGS_CONFIG1_t Config1;
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@ -3,6 +3,9 @@
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`include "defines.svh"
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`include "defines.svh"
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// TAGL <= 12
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// INDEXL <= 6
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// IC for I-Cache
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// IC for I-Cache
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`define IC_TAGL 12
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`define IC_TAGL 12
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`define IC_INDEXL 6
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`define IC_INDEXL 6
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@ -3,11 +3,11 @@
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// `define ILA_DEBUG
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// `define ILA_DEBUG
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`define ENABLE_CACHEOP
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// `define ENABLE_CACHEOP
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`define ENABLE_TLB
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// `define ENABLE_TLB
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`define ENABLE_CpU
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// `define ENABLE_CpU
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`define ENABLE_TRAP
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// `define ENABLE_TRAP
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`define ENABLE_MADD
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// `define ENABLE_MADD
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`ifdef SIMULATION_VERILATOR
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`ifdef SIMULATION_VERILATOR
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`undef ENABLE_CpU
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`undef ENABLE_CpU
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