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cxy004 2021-07-16 15:26:47 +08:00
commit dbd82fe117
2 changed files with 181 additions and 97 deletions
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141
src/Core/InstrQueue.sv
View File

@ -72,12 +72,13 @@ readygo to valid
logic a1, a2;
// logic [5:0] judge;
// always_ff @(negedge clk) judge = {qv4, qv3, qv2, qv1, HandShake_out1.allowin, HandShake_out2.allowin};
ffen #(2) a (
clk,
{HandShake_out1.allowin, HandShake_out2.allowin},
1'b1,
{a1, a2}
);
// ffen #(2) a (
// clk,
// {HandShake_out1.allowin, HandShake_out2.allowin},
// 1'b1,
// {a1, a2}
// );
assign {a1, a2} = {HandShake_out1.allowin, HandShake_out2.allowin};
assign judge = {qv4, qv3, qv2, qv1, a1, a2};
// assign out1 = qi1;
// assign out2 = qi2;
@ -128,30 +129,106 @@ readygo to valid
dp4 = (judge[4] & ~judge[0] & (~judge[1] | judge[5])) ? pin1 : pin2;
end
always_ff @(posedge clk) begin
if (rst | clear) begin
{qv1, qv2, qv3, qv4} <= 4'b0;
end else begin
if (en1) begin
qi1 <= di1;
qv1 <= dv1;
qp1 <= dp1;
end
if (en2) begin
qi2 <= di2;
qv2 <= dv2;
qp2 <= dp2;
end
if (en3) begin
qi3 <= di3;
qv3 <= dv3;
qp3 <= dp3;
end
if (en4) begin
qi4 <= di4;
qv4 <= dv4;
qp4 <= dp4;
end
end
end
// always_ff @(posedge clk) begin
// if (rst | clear) begin
// {qv1, qv2, qv3, qv4} <= 4'b0;
// end else begin
// if (en1) begin
// qi1 <= di1;
// qv1 <= dv1;
// qp1 <= dp1;
// end
// if (en2) begin
// qi2 <= di2;
// qv2 <= dv2;
// qp2 <= dp2;
// end
// if (en3) begin
// qi3 <= di3;
// qv3 <= dv3;
// qp3 <= dp3;
// end
// if (en4) begin
// qi4 <= di4;
// qv4 <= dv4;
// qp4 <= dp4;
// end
// end
// end
ffen #(32) pc1 (
clk,
dp1,
en1,
qp1
);
ffen #(32) pc2 (
clk,
dp2,
en2,
qp2
);
ffen #(32) pc3 (
clk,
dp3,
en3,
qp3
);
ffen #(32) pc4 (
clk,
dp4,
en4,
qp4
);
ffen #(32) instr1 (
clk,
di1,
en1,
qi1
);
ffen #(32) instr2 (
clk,
di2,
en2,
qi2
);
ffen #(32) instr3 (
clk,
di3,
en3,
qi3
);
ffen #(32) instr4 (
clk,
di4,
en4,
qi4
);
ffenr #(1) valid1 (
clk,
rst | clear,
dv1,
en1,
qv1
);
ffenr #(1) valid2 (
clk,
rst | clear,
dv2,
en2,
qv2
);
ffenr #(1) valid3 (
clk,
rst | clear,
dv3,
en3,
qv3
);
ffenr #(1) valid4 (
clk,
rst | clear,
dv4,
en4,
qv4
);
endmodule

137
src/testbench/instrqueue/testbench.sv
View File

@ -34,78 +34,85 @@ module testbench_iq();
clear
);
always begin
clk = 1; rst = 1; fakehso1.allowin = 0; fakehso2.allowin = 0;
fakehsi1.readygo = 1; fakehsi2.readygo = 1; clear = 0;
in1 = 0; in2 = 0; pin1 = 0; pin2 = 0; #50;
clk = 0; rst = 0; #50;
clk = 1;
in1 = 1; in2 = 2; pin1 = 1; pin2 = 2; #50;
clk = 0; #50;
clk = 1;
in1 = 3; in2 = 4; pin1 = 3; pin2 = 4; clear = 1; #50;
clk = 0; #50;
clk = 1; clear = 0;fakehso1.allowin = 1; fakehso2.allowin = 1;
in1 = 5; in2 = 6 ; pin1 = 5; pin2 = 6; #50;
fakehsi1.readygo = 0; fakehsi2.readygo = 0;
clk = 0; #50; clk = 1; #50; clk = 0; #50; clk = 1; #50; clk = 0; #50;
// clk = 1; rst = 1; fakehso1.allowin = 0; fakehso2.allowin = 0;
// fakehsi1.readygo = 1; fakehsi2.readygo = 1; clear = 0;
// in1 = 0; in2 = 0; pin1 = 0; pin2 = 0; #50;
// clk = 0; rst = 0; #50;
// clk = 1;
// in1 = 1; in2 = 2; pin1 = 1; pin2 = 2; #50;
// clk = 0; #50;
// clk = 1;
// in1 = 3; in2 = 4; pin1 = 3; pin2 = 4; clear = 1; #50;
// clk = 0; #50;
// clk = 1; clear = 0;fakehso1.allowin = 1; fakehso2.allowin = 1;
// in1 = 5; in2 = 6 ; pin1 = 5; pin2 = 6; #50;
// fakehsi1.readygo = 0; fakehsi2.readygo = 0;
// clk = 0; #50; clk = 1; #50; clk = 0; #50; clk = 1; #50; clk = 0; #50;
clk = 1; rst = 1; fakehso1.allowin = 0; fakehso2.allowin = 0;
fakehsi1.readygo = 1; fakehsi2.readygo = 1; clear = 0;
in1 = 0; in2 = 0; pin1 = 0; pin2 = 0; #50;
clk = 0; rst = 0; #50;
clk = 1;
in1 = 1; in2 = 2; pin1 = 1; pin2 = 2; #50;
clk = 0; #50;
clk = 1;
in1 = 3; in2 = 4; pin1 = 3; pin2 = 4; #50;
clk = 0; #50;
clk = 1; fakehso1.allowin = 1; fakehso2.allowin = 1;
in1 = 5; in2 = 6; pin1 = 5; pin2 = 6; clear = 1; #50;
fakehsi1.readygo = 0; fakehsi2.readygo = 0;
clk = 0; #50; clear = 0; clk = 1; #50; clk = 0; #50; clk = 1; #50; clk = 0; #50;
clk = 1; rst = 1; fakehso1.allowin = 0; fakehso2.allowin = 0;
// clk = 1; rst = 1; fakehso1.allowin = 0; fakehso2.allowin = 0;
// fakehsi1.readygo = 1; fakehsi2.readygo = 1; clear = 0;
// in1 = 0; in2 = 0; pin1 = 0; pin2 = 0; #50;
// clk = 0; rst = 0; #50;
// clk = 1;
// in1 = 1; in2 = 2; pin1 = 1; pin2 = 2; #50;
// clk = 0; #50;
// clk = 1;
// in1 = 3; in2 = 4; pin1 = 3; pin2 = 4; #50;
// clk = 0; #50;
// clk = 1; fakehso1.allowin = 1; fakehso2.allowin = 1;
// in1 = 5; in2 = 6; pin1 = 5; pin2 = 6; clear = 1; #50;
// fakehsi1.readygo = 0; fakehsi2.readygo = 0;
// clk = 0; #50; clear = 0; clk = 1; #50; clk = 0; #50; clk = 1; #50; clk = 0; #50;
clk = 0;
fakehsi1.readygo = 1; fakehsi2.readygo = 1;
in1 = 0; in2 = 0; pin1 = 0; pin2 = 0; #50;
clk = 0; rst = 0; #50;
clk = 1;
in1 = 1; in2 = 2; pin1 = 1; pin2 = 2; #50;
fakehso1.allowin = 0; fakehso2.allowin = 0;
rst = 1;
in1 = 0; in2 = 0; pin1 = 0; pin2 = 0; #5;
clk = 1; #50;
rst = 0; #5;
clk = 0; #50;
in1 = 1; in2 = 2; pin1 = 1; pin2 = 2;
#5;
clk = 1;
in1 = 3; in2 = 4; pin1 = 3; pin2 = 4; #50;
#50;
clk = 0; #50;
clk = 1; fakehso1.allowin = 1; fakehso2.allowin = 1;
in1 = 5; in2 = 6; pin1 = 5; pin2 = 6; #50;
fakehsi1.readygo = 0; fakehsi2.readygo = 0;
clk = 0; #50; clk = 1; #50; clk = 0; #50; clk = 1; #50; clk = 0; #50;
clk = 1; rst = 1; fakehso1.allowin = 1; fakehso2.allowin = 1;
fakehsi1.readygo = 1; fakehsi2.readygo = 1;
in1 = 0; in2 = 0; pin1 = 0; pin2 = 0; #50;
clk = 0; rst = 0; #50;
clk = 1;
in1 = 1; in2 = 2; pin1 = 1; pin2 = 2; #50;
clk = 0; #50;
clk = 1;
in1 = 3; in2 = 4; pin1 = 3; pin2 = 4; #50;
clk = 0; #50;
clk = 1;
in1 = 5; in2 = 6; pin1 = 5; pin2 = 6; #50;
fakehsi1.readygo = 0; fakehsi2.readygo = 0;
clk = 0; #50; clk = 1; #50; clk = 0; #50; clk = 1; #50; clk = 0; #50;
clk = 1; rst = 1; fakehso1.allowin = 1; fakehso2.allowin = 0;
fakehsi1.readygo = 1; fakehsi2.readygo = 1;
in1 = 0; in2 = 0; pin1 = 0; pin2 = 0; #50;
clk = 0; rst = 0; #50;
clk = 1;
in1 = 1; in2 = 2; pin1 = 1; pin2 = 2; #50;
clk = 0; #50;
clk = 1;
in1 = 3; in2 = 4; pin1 = 3; pin2 = 4; #50;
clk = 0; #50;
clk = 1;
in1 = 5; in2 = 6; pin1 = 5; pin2 = 6; fakehso2.allowin = 1; #50;
in1 = 3; in2 = 4; pin1 = 3; pin2 = 4; #5;
clk = 1;
#50;
clk = 0; #50;
fakehso1.allowin = 1; fakehso2.allowin = 1;
in1 = 5; in2 = 6; pin1 = 5; pin2 = 6; #5;
clk = 1;#50;
fakehsi1.readygo = 0; fakehsi2.readygo = 0;
clk = 0; #50; clk = 1; #50; clk = 0; #50; clk = 1; #50; clk = 0; #50;
// clk = 1; rst = 1; fakehso1.allowin = 1; fakehso2.allowin = 1;
// fakehsi1.readygo = 1; fakehsi2.readygo = 1;
// in1 = 0; in2 = 0; pin1 = 0; pin2 = 0; #50;
// clk = 0; rst = 0; #50;
// clk = 1;
// in1 = 1; in2 = 2; pin1 = 1; pin2 = 2; #50;
// clk = 0; #50;
// clk = 1;
// in1 = 3; in2 = 4; pin1 = 3; pin2 = 4; #50;
// clk = 0; #50;
// clk = 1;
// in1 = 5; in2 = 6; pin1 = 5; pin2 = 6; #50;
// fakehsi1.readygo = 0; fakehsi2.readygo = 0;
// clk = 0; #50; clk = 1; #50; clk = 0; #50; clk = 1; #50; clk = 0; #50;
// clk = 1; rst = 1; fakehso1.allowin = 1; fakehso2.allowin = 0;
// fakehsi1.readygo = 1; fakehsi2.readygo = 1;
// in1 = 0; in2 = 0; pin1 = 0; pin2 = 0; #50;
// clk = 0; rst = 0; #50;
// clk = 1;
// in1 = 1; in2 = 2; pin1 = 1; pin2 = 2; #50;
// clk = 0; #50;
// clk = 1;
// in1 = 3; in2 = 4; pin1 = 3; pin2 = 4; #50;
// clk = 0; #50;
// clk = 1;
// in1 = 5; in2 = 6; pin1 = 5; pin2 = 6; fakehso2.allowin = 1; #50;
// fakehsi1.readygo = 0; fakehsi2.readygo = 0;
// clk = 0; #50; clk = 1; #50; clk = 0; #50; clk = 1; #50; clk = 0; #50;
$finish;
end
endmodule