From db1aa1d615f709c442519096b95499ba59b43f32 Mon Sep 17 00:00:00 2001 From: Paul Pan Date: Tue, 2 Aug 2022 11:29:23 +0800 Subject: [PATCH] Manual Merge Co-authored-by: cxy004 Co-authored-by: Hooo1941 --- sim/Makefile | 9 ++- sim/sim_main.cpp | 2 +- src/CP0/CP0.sv | 91 ++++++++++++----------- src/Core/Datapath.sv | 91 ++++++++++++----------- src/Core/Gadgets/decoder2.sv | 123 ++++++++++++++++++++++++++++++++ src/Core/Gadgets/instr_valid.sv | 105 --------------------------- src/MU/interface.sv | 63 +++++++++------- src/include/CP0.svh | 31 ++++---- src/include/defines.svh | 17 ++++- src/mycpu_top.sv | 39 ---------- 10 files changed, 297 insertions(+), 274 deletions(-) create mode 100644 src/Core/Gadgets/decoder2.sv delete mode 100644 src/Core/Gadgets/instr_valid.sv diff --git a/sim/Makefile b/sim/Makefile index 6d8959b..6d115db 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -24,7 +24,7 @@ VERILATOR_BUILD_FLAGS += --assert # Generate coverage analysis VERILATOR_BUILD_FLAGS += --coverage # Run make to compile model, with as many CPUs as are free -VERILATOR_BUILD_FLAGS += --compiler clang -CFLAGS "-Wno-parentheses-equality" --build -j +VERILATOR_BUILD_FLAGS += --compiler clang -CFLAGS "-Wno-parentheses-equality" -j # Simulation Defines VERILATOR_FLAGS += -sv -DSIMULATION_VERILATOR -DSIMULATION_PC @@ -50,16 +50,19 @@ FUNC_SOURCE = $(wildcard ../resources/tb.sv ../resources/func_test/*.v ../resour #################### # Targets # #################### -.phony: test func_test func_coverage func_run clean +.phony: lint verilate func_build func_coverage func_run clean default: func_run lint: $(VERILATOR) --lint-only $(VERILATOR_FLAGS) $(INCLUDE) $(SOURCE) -top mycpu_top -func_build: +verilate: $(VERILATOR) $(VERILATOR_FLAGS) $(VERILATOR_BUILD_FLAGS) $(INCLUDE) $(SOURCE) $(FUNC_SOURCE) $(VERILATOR_INPUT) +func_build: verilate + make -C obj_dir -f Vtestbench_top.mk -j + func_coverage: func_build @rm -rf logs/annotated $(VERILATOR_COVERAGE) $(VERILATOR_COV_FLAGS) diff --git a/sim/sim_main.cpp b/sim/sim_main.cpp index fd8dd6e..d0ba72a 100644 --- a/sim/sim_main.cpp +++ b/sim/sim_main.cpp @@ -30,7 +30,7 @@ int main(int argc, char **argv, char **env) { std::cout << "<<< Simulation Started >>>" << std::endl; auto time_start = std::chrono::high_resolution_clock::now(); top->clk = 0; - top->switch_sim = 0xff; + top->switch_sim = ~(0); while (!Verilated::gotFinish() && main_time < time_limit) { if (ctrl_c_hit) break; diff --git a/src/CP0/CP0.sv b/src/CP0/CP0.sv index a6fa3a1..8b21f7b 100644 --- a/src/CP0/CP0.sv +++ b/src/CP0/CP0.sv @@ -10,12 +10,6 @@ module CP0 ( input logic en, input word_t wdata, - // exception - input EXCEPTION_t exception, - output word_t EPC, - output logic Bev, - output logic [19:0] EBase, - // int input logic [5:0] ext_int, output logic interrupt, @@ -40,19 +34,17 @@ module CP0 ( assign rf_cp0.Config.AR = 3'b0; assign rf_cp0.Config.MT = 3'b001; assign rf_cp0.Config.zero1 = 4'b0; - assign rf_cp0.Cause.zero1 = 14'b0; + assign rf_cp0.Cause.zero1 = 12'b0; assign rf_cp0.Cause.IP[7:2] = {rf_cp0.Cause.TI | ext_int[5], ext_int[4:0]}; assign rf_cp0.Cause.zero2 = 1'b0; - assign rf_cp0.Cause.zero3 = 2'b00; - assign rf_cp0.Status.zero1 = 2'b0; - assign rf_cp0.Status.CU0 = 1'b1; + assign rf_cp0.Cause.zero3 = 2'b0; + assign rf_cp0.Status.CU[3:1] = 3'b0; + assign rf_cp0.Status.zero1 = 5'b0; assign rf_cp0.Status.zero2 = 6'b0; - assign rf_cp0.Status.zero3 = 6'b0; - assign rf_cp0.Status.zero4 = 3'b0; - assign rf_cp0.Status.zero5 = 2'b0; + assign rf_cp0.Status.zero3 = 3'b0; + assign rf_cp0.Status.zero4 = 2'b0; assign rf_cp0.EntryHi.zero = 5'b0; assign rf_cp0.Wired.zero = 29'b0; - assign rf_cp0.Context.BadVPN2= 19'b0; assign rf_cp0.Context.zero = 4'b0; assign rf_cp0.EntryLo1.zero = 6'b0; assign rf_cp0.EntryLo0.zero = 6'b0; @@ -70,12 +62,12 @@ module CP0 ( // | Watch registers implemented | Code compression implemented | // | 1 | 0 | // | EJTAG implemented | FPU implemented | - assign rf_cp0.Config1 = 32'b0_000111_000_100_011_001_011_011_0_0_0_0_0_0_0; - assign rf_cp0.EBase.one = 1'b1; - assign rf_cp0.EBase.zero1 = 1'b0; - assign rf_cp0.EBase.zero2 = 2'b0; - assign rf_cp0.EBase.CPUNum = 10'b0; - assign rf_cp0.PRId = 32'h00004220; + assign rf_cp0.Config1 = 32'b0_000111_000_100_011_001_011_011_0_0_0_0_0_0_0; + assign rf_cp0.EBase.one = 1'b1; + assign rf_cp0.EBase.zero1 = 1'b0; + assign rf_cp0.EBase.zero2 = 2'b0; + assign rf_cp0.EBase.CPUNum = 10'b0; + assign rf_cp0.PRId = 32'h00004220; always_ff @(posedge clk) if (rst) begin @@ -83,20 +75,23 @@ module CP0 ( rf_cp0.EPC = 32'h0; rf_cp0.Cause.BD = 1'b0; rf_cp0.Cause.TI = 1'b0; + rf_cp0.Cause.CE = 2'b0; rf_cp0.Cause.IP[1:0] = 2'b0; rf_cp0.Cause.ExcCode = 5'b0; + rf_cp0.Status.CU[0] = 1'b1; rf_cp0.Status.Bev = 1'b1; rf_cp0.Status.IM = 8'b0; rf_cp0.Status.UM = 1'b0; rf_cp0.Status.EXL = 1'b0; rf_cp0.Status.IE = 1'b0; - rf_cp0.Compare = 32'hFFFF_FFFF; + rf_cp0.Compare = 32'h0; rf_cp0.EntryHi.VPN2 = 19'b0; rf_cp0.EntryHi.ASID = 8'b0; rf_cp0.Count = 32'h0; rf_cp0.BadVAddr = 32'h0; rf_cp0.Wired.Wired = 3'b0; rf_cp0.Context.PTEBase = 9'b0; + rf_cp0.Context.BadVPN2 = 19'b0; rf_cp0.EntryLo1.PFN = 20'b0; rf_cp0.EntryLo1.C = 3'b0; rf_cp0.EntryLo1.D = 1'b0; @@ -111,9 +106,9 @@ module CP0 ( rf_cp0.Index.Index = 3'b0; rf_cp0.Random.Random = 3'b111; - rf_cp0.EBase.EBase = 18'b0; + rf_cp0.EBase.EBase = 18'b0; - count_lo = 0; + count_lo = 0; end else begin // count count_lo = ~count_lo; @@ -144,11 +139,12 @@ module CP0 ( 14: rf_cp0.EPC = wdata; 13: rf_cp0.Cause.IP[1:0] = wdata[9:8]; 12: begin - rf_cp0.Status.Bev = wdata[22]; - rf_cp0.Status.IM = wdata[15:8]; - rf_cp0.Status.UM = wdata[4]; - rf_cp0.Status.EXL = wdata[1]; - rf_cp0.Status.IE = wdata[0]; + rf_cp0.Status.CU[0] = wdata[28]; + rf_cp0.Status.Bev = wdata[22]; + rf_cp0.Status.IM = wdata[15:8]; + rf_cp0.Status.UM = wdata[4]; + rf_cp0.Status.EXL = wdata[1]; + rf_cp0.Status.IE = wdata[0]; end 11: begin rf_cp0.Cause.TI = 0; @@ -215,26 +211,28 @@ module CP0 ( if (rf_cp0.Count == rf_cp0.Compare) rf_cp0.Cause.TI = 1; - if (exception.ERET) rf_cp0.Status.EXL = 1'b0; + if (c0.cpu_exception.ERET) rf_cp0.Status.EXL = 1'b0; else begin - if (exception.ExcValid && rf_cp0.Status.EXL == 1'b0) begin - rf_cp0.EPC = exception.Delay ? exception.EPC - 4 : exception.EPC; - rf_cp0.Cause.BD = exception.Delay; - rf_cp0.Cause.ExcCode = exception.ExcCode; + if (c0.cpu_exception.ExcValid && rf_cp0.Status.EXL == 1'b0) begin + rf_cp0.EPC = c0.cpu_exception.Delay ? c0.cpu_exception.EPC - 4 : c0.cpu_exception.EPC; + rf_cp0.Cause.BD = c0.cpu_exception.Delay; + rf_cp0.Cause.CE = c0.cpu_exception.CE; + rf_cp0.Cause.ExcCode = c0.cpu_exception.ExcCode; rf_cp0.Status.EXL = 1'b1; - if ( exception.ExcCode == `EXCCODE_MOD - | exception.ExcCode == `EXCCODE_TLBL - | exception.ExcCode == `EXCCODE_TLBS - | exception.ExcCode == `EXCCODE_ADEL - | exception.ExcCode == `EXCCODE_ADES) begin - rf_cp0.BadVAddr = exception.BadVAddr; + if ( c0.cpu_exception.ExcCode == `EXCCODE_MOD + | c0.cpu_exception.ExcCode == `EXCCODE_TLBL + | c0.cpu_exception.ExcCode == `EXCCODE_TLBS + | c0.cpu_exception.ExcCode == `EXCCODE_ADEL + | c0.cpu_exception.ExcCode == `EXCCODE_ADES) begin + rf_cp0.BadVAddr = c0.cpu_exception.BadVAddr; end - if ( exception.ExcCode == `EXCCODE_MOD - | exception.ExcCode == `EXCCODE_TLBL - | exception.ExcCode == `EXCCODE_TLBS) begin - rf_cp0.EntryHi.VPN2 = exception.BadVAddr[31:13]; + if ( c0.cpu_exception.ExcCode == `EXCCODE_MOD + | c0.cpu_exception.ExcCode == `EXCCODE_TLBL + | c0.cpu_exception.ExcCode == `EXCCODE_TLBS) begin + rf_cp0.Context.BadVPN2 = c0.cpu_exception.BadVAddr[31:13]; + rf_cp0.EntryHi.VPN2 = c0.cpu_exception.BadVAddr[31:13]; end end @@ -280,11 +278,12 @@ module CP0 ( default: rdata = 32'h0; endcase - assign EPC = rf_cp0.EPC; - assign Bev = rf_cp0.Status.Bev; - assign EBase = rf_cp0.EBase[31:12]; + assign c0.cp0_EPC = rf_cp0.EPC; + assign c0.cp0_Bev = rf_cp0.Status.Bev; + assign c0.cp0_EBase = rf_cp0.EBase[31:12]; assign c0.cp0_K0 = rf_cp0.Config.K0; + assign c0.cp0_CU = rf_cp0.Status.CU; assign c0.cp0_Random = rf_cp0.Random; assign c0.cp0_Index = rf_cp0.Index; assign c0.cp0_EntryHi = rf_cp0.EntryHi; diff --git a/src/Core/Datapath.sv b/src/Core/Datapath.sv index 62871a3..0253405 100644 --- a/src/Core/Datapath.sv +++ b/src/Core/Datapath.sv @@ -19,10 +19,6 @@ module Datapath ( input word_t C0_rdata, output logic C0_we, output word_t C0_wdata, - output EXCEPTION_t C0_exception, - input word_t C0_ERETPC, - input logic C0_Bev, - input logic [19:0] C0_EBase, //debug interface output wire [31:0] debug_wb_pc, @@ -111,8 +107,10 @@ module Datapath ( logic D_IA_valid; logic D_IB_valid; - logic D_IA_iv; - logic D_IB_iv; + logic D_IA_ri; + logic D_IB_ri; + logic D_IA_cpu; + logic D_IB_cpu; logic D_IA_TLBRefill; logic D_IA_TLBInvalid; @@ -282,15 +280,15 @@ module Datapath ( prio_mux5 #(32) PF_pc_mux ( PF_pc0, PF_pcp8, - {C0_Bev ? 23'h5fe001 : {C0_EBase, 3'h0}, `Off_GExc}, - {C0_Bev ? 23'h5fe001 : {C0_EBase, 3'h0}, `Off_TRef}, - C0_ERETPC, + {C0.cp0_Bev ? 23'h5fe001 : {C0.cp0_EBase, 3'h0}, `Off_GExc}, + {C0.cp0_Bev ? 23'h5fe001 : {C0.cp0_EBase, 3'h0}, `Off_TRef}, + C0.cp0_EPC, {M_exception.ERET, M_exception_REFILL, M_exception.ExcValid, ~D_IB_valid | ~D.IA.BJRJ | D.IA.B & ~D.IA.BGO}, PF.pc ); assign rstD = D_IA_valid & (D.IA.B & D.IA.BGO | D.IA.JR | D.IA.J) & D_IB_valid & D_readygo; - assign rstM = C0_exception.ExcValid; + assign rstM = C0.cpu_exception.ExcValid; assign PF_go = ~D.IA_ExcValid & ~D.IB_ExcValid & ~E_I0_ExcValidWithoutOF & ~E_I1_ExcValidWithoutOF & (~D_IB_valid | ~D.IA.JR | PF_pcjr[1:0] == 2'b00); @@ -436,51 +434,61 @@ module Datapath ( ); // D.Exc - instr_valid D_IA_instr_valid ( - D.IA_inst, - D_IA_iv + decoder2 D_IA_decoder2 ( + D.IA_inst, + C0.cp0_CU, + C0.cp0_in_kernel, + D_IA_ri, + D_IA_cpu, + D.IA_CE ); - instr_valid D_IB_instr_valid ( - D.IB_inst, - D_IB_iv + decoder2 D_IB_decoder2 ( + D.IB_inst, + C0.cp0_CU, + C0.cp0_in_kernel, + D_IB_ri, + D_IB_cpu, + D.IB_CE ); // INFO: Merge "pc[1:0] != 2'b00" into AddressError assign D.IA_ExcValid = D_IA_valid & ( D.IA_pc[1:0] != 2'b00 - | ~D_IA_iv + | D_IA_ri | D_IA_cpu | D_IA_TLBRefill | D_IA_TLBInvalid | D_IA_AddressError | D.IA.SYSCALL | D.IA.BREAK | D.IA.ERET | D.IA.PRV & ~C0.cp0_in_kernel); - assign D.IA_ERET = D_IA_valid & D.IA_pc[1:0] == 2'b00 & ~D_IA_TLBRefill & ~D_IA_TLBInvalid & ~D_IA_AddressError & D_IA_iv & D.IA.ERET; + assign D.IA_ERET = D_IA_valid & D.IA_pc[1:0] == 2'b00 & ~D_IA_TLBRefill & ~D_IA_TLBInvalid & ~D_IA_AddressError & ~D_IA_ri & ~D_IA_cpu & D.IA.ERET; assign D.IA_REFILL = D_IA_valid & D.IB_pc[1:0] == 2'b00 & D_IA_TLBRefill; assign D.IA_ExcCode = D.IA_pc[1:0] != 2'b00 | D_IA_AddressError ? `EXCCODE_ADEL : D_IA_TLBRefill ? `EXCCODE_TLBL : D_IA_TLBInvalid ? `EXCCODE_TLBL - : ~D_IA_iv ? `EXCCODE_RI + : D_IA_cpu ? `EXCCODE_CPU + : D_IA_ri ? `EXCCODE_RI : ~D.IA_inst[30] & D.IA_inst[0] ? `EXCCODE_BP : ~D.IA_inst[30] & ~D.IA_inst[0] ? `EXCCODE_SYS - : `EXCCODE_CPU; + : `EXCCODE_RI; assign D.IB_ExcValid = D_IB_valid & ( D.IB_pc[1:0] != 2'b00 - | ~D_IB_iv + | D_IB_ri | D_IB_cpu | D_IB_TLBRefill | D_IB_TLBInvalid | D_IB_AddressError | D.IB.SYSCALL | D.IB.BREAK | D.IB.ERET | D.IB_Delay & D.IB.BJRJ | D.IB.PRV & ~C0.cp0_in_kernel); - assign D.IB_ERET = D_IB_valid & D.IB_pc[1:0] == 2'b00 & ~D_IB_TLBRefill & ~D_IB_TLBInvalid & ~D_IB_AddressError & D_IB_iv & D.IB.ERET & ~D.IB_Delay; + assign D.IB_ERET = D_IB_valid & D.IB_pc[1:0] == 2'b00 & ~D_IB_TLBRefill & ~D_IB_TLBInvalid & ~D_IB_AddressError & ~D_IB_ri & ~D_IB_cpu & D.IB.ERET & ~D.IB_Delay; assign D.IB_REFILL = D_IB_valid & D.IB_pc[1:0] == 2'b00 & D_IB_TLBRefill; // EXCCODE_BP and EXCCODE_SYSCALL -> exc.txt assign D.IB_ExcCode = D.IB_pc[1:0] != 2'b00 | D_IB_AddressError ? `EXCCODE_ADEL : D_IB_TLBRefill ? `EXCCODE_TLBL : D_IB_TLBInvalid ? `EXCCODE_TLBL - : ~D_IB_iv ? `EXCCODE_RI + : D_IB_cpu ? `EXCCODE_CPU + : D_IB_ri ? `EXCCODE_RI : D.IB.ERET ? `EXCCODE_RI : D.IB_Delay & D.IB.BJRJ ? `EXCCODE_RI : ~D.IB_inst[30] & D.IB_inst[0] ? `EXCCODE_BP : ~D.IB_inst[30] & ~D.IB_inst[0] ? `EXCCODE_SYS - : `EXCCODE_CPU; + : `EXCCODE_RI; assign D.IB_Delay = D.IA.BJRJ; // D.Dispatch @@ -523,7 +531,7 @@ module Datapath ( | D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl1.MWR & ~D.IA.DP1 // Not Arith -> LWL/LWR | D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & |D.IB.MCtrl1.ALR & ~D.IA.DP1 - // D.IA -> MOVN/MOVZ + // Any -> MOVN/MOVZ | D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.DT // Arith -> MOVN/MOVZ | E.I0.WCtrl.RW & D.IB.RT == E.I0.RD & D.IB.DT @@ -584,6 +592,7 @@ module Datapath ( assign D.I0.ERET = D.A ? D.IB_ERET : D.IA_ERET; assign D.I0.REFILL = D.A ? D.IB_REFILL : D.IA_REFILL; assign D.I0.ExcCode = D.A ? D.IB_ExcCode : D.IA_ExcCode; + assign D.I0.CE = D.A ? D.IB_CE : D.IA_CE; assign D.I0.Delay = D.A ? D.IB_Delay : D.IA_Delay; assign D.I0.OFA = D.A ? D.IB.OFA : D.IA.OFA; assign D.I0.RS = D.A ? D.IB.RS : D.IA.RS; @@ -600,6 +609,7 @@ module Datapath ( assign D_I1_go = D.A ? D_IA_go : D_IB_go; assign D.I1.pc = D.A ? D.IA_pc : D.IB_pc; assign D.I1.ExcValid = D.A ? D.IA_ExcValid : D.IB_ExcValid; + assign D.I1.CE = D.A ? D.IA_CE : D.IB_CE; assign D.I1.ERET = D.A ? D.IA_ERET : D.IB_ERET; assign D.I1.REFILL = D.A ? D.IA_REFILL : D.IB_REFILL; assign D.I1.ExcCode = D.A ? D.IA_ExcCode : D.IB_ExcCode; @@ -690,13 +700,13 @@ module Datapath ( E.en, E.I0.pc ); - ffenrc #(1 + 1 + 1 + 5 + 1) E_I0_Exc_ff ( + ffenrc #(1 + 1 + 1 + 5 + 2 + 1) E_I0_Exc_ff ( clk, rst | rstM, - {D.I0.ExcValid, D.I0.ERET, D.I0.REFILL, D.I0.ExcCode, D.I0.Delay}, + {D.I0.ExcValid, D.I0.ERET, D.I0.REFILL, D.I0.ExcCode, D.I0.CE, D.I0.Delay}, E.en, ~D_go, - {E_I0_PrevExcValid, E_I0_PrevERET, E_I0_PrevREFILL, E_I0_PrevExcCode, E.I0.Delay} + {E_I0_PrevExcValid, E_I0_PrevERET, E_I0_PrevREFILL, E_I0_PrevExcCode, E.I0.CE, E.I0.Delay} ); ffenrc #(1) E_I0_ExcCtrl_ff ( clk, @@ -753,13 +763,13 @@ module Datapath ( E.en, E.I1.pc ); - ffenrc #(1 + 1 + 1 + 5 + 1) E_I1_Exc_ff ( + ffenrc #(1 + 1 + 1 + 5 + 2 + 1) E_I1_Exc_ff ( clk, rst | rstM, - {D.I1.ExcValid, D.I1.ERET, D.I1.REFILL, D.I1.ExcCode, D.I1.Delay}, + {D.I1.ExcValid, D.I1.ERET, D.I1.REFILL, D.I1.ExcCode, D.I1.CE, D.I1.Delay}, E.en, ~D_go, - {E_I1_PrevExcValid, E_I1_PrevERET, E_I1_PrevREFILL, E_I1_PrevExcCode, E.I1.Delay} + {E_I1_PrevExcValid, E_I1_PrevERET, E_I1_PrevREFILL, E_I1_PrevExcCode, E.I1.CE, E.I1.Delay} ); ffenrc #(1) E_I1_ExcCtrl_ff ( clk, @@ -1014,13 +1024,13 @@ module Datapath ( M.en, M.I0.pc ); - ffenrc #(1 + 1 + 1 + 5 + 1) M_I0_Exc_ff ( + ffenrc #(1 + 1 + 1 + 5 + 2 + 1) M_I0_Exc_ff ( clk, rst | rstM, - {E.I0.ExcValid, E.I0.ERET, E.I0.REFILL, E.I0.ExcCode, E.I0.Delay}, + {E.I0.ExcValid, E.I0.ERET, E.I0.REFILL, E.I0.ExcCode, E.I0.CE, E.I0.Delay}, M.en, ~E_go, - {M.I0.ExcValid, M.I0.ERET, M.I0.REFILL, M.I0.ExcCode, M.I0.Delay} + {M.I0.ExcValid, M.I0.ERET, M.I0.REFILL, M.I0.ExcCode, M.I0.CE, M.I0.Delay} ); ffen #(5 + 5) M_I0_RST_ff ( clk, @@ -1069,13 +1079,13 @@ module Datapath ( M.en, M.I1.pc ); - ffenrc #(1 + 1 + 1 + 5 + 32 + 1) M_I1_Exc_ff ( + ffenrc #(1 + 1 + 1 + 5 + 2 + 32 + 1) M_I1_Exc_ff ( clk, rst | rstM, - {E.I1.ExcValid, E.I1.ERET, E.I1.REFILL, E.I1.ExcCode, E.I1.BadVAddr, E.I1.Delay}, + {E.I1.ExcValid, E.I1.ERET, E.I1.REFILL, E.I1.ExcCode, E.I1.CE, E.I1.BadVAddr, E.I1.Delay}, M.en, ~E_go, - {M_I1_PrevExcValid, M.I1.ERET, M_I1_PrevREFILL, M_I1_PrevExcCode, M.I1.BadVAddr, M.I1.Delay} + {M_I1_PrevExcValid, M.I1.ERET, M_I1_PrevREFILL, M_I1_PrevExcCode, M.I1.CE, M.I1.BadVAddr, M.I1.Delay} ); ffen #(5) M_I1_RT_ff ( clk, @@ -1151,12 +1161,13 @@ module Datapath ( assign {M_exception, M_exception_REFILL} = { M.I1.ExcValid | M.I0.ExcValid, - ~M.I0.ExcValid | M.I1.ExcValid & M.A ? {M.I1.Delay, M.I1.ExcCode, M.I1.BadVAddr, M.I1.pc, M.I1.ERET, M.I1.REFILL} - : {M.I0.Delay, M.I0.ExcCode, M.I0.BadVAddr, M.I0.pc, M.I0.ERET, M.I0.REFILL} + ~M.I0.ExcValid | M.I1.ExcValid & M.A ? {M.I1.Delay, M.I1.CE, M.I1.ExcCode, M.I1.BadVAddr, M.I1.pc, M.I1.ERET, M.I1.REFILL} + : {M.I0.Delay, M.I0.CE, M.I0.ExcCode, M.I0.BadVAddr, M.I0.pc, M.I0.ERET, M.I0.REFILL} }; - assign C0_exception = { + assign C0.cpu_exception = { M_exception.ExcValid & M.en, M_exception.Delay, + M_exception.CE, M_exception.ExcCode, M_exception.BadVAddr, M_exception.EPC, diff --git a/src/Core/Gadgets/decoder2.sv b/src/Core/Gadgets/decoder2.sv new file mode 100644 index 0000000..e3646cc --- /dev/null +++ b/src/Core/Gadgets/decoder2.sv @@ -0,0 +1,123 @@ +`include "defines.svh" + +module decoder2 ( + input word_t instr, + input logic [3:0] CU, + input logic kernel, + output logic ri, + output logic cpu, + output logic [1:0] ce +); + + logic [3:0] CU2; + assign CU2 = {CU[3:1], CU[0] | kernel}; + always_comb begin + ri = 1'b1; + ce = instr[27:26]; + cpu = ce != 2'b11 + & ~CU2[ce] & ( instr[31:28] == 4'b0100 // COPx + | instr[31:28] == 4'b1100 // LWCx + | instr[31:28] == 4'b1101 // LDCx + | instr[31:28] == 4'b1110 // SWCx + | instr[31:28] == 4'b1111 // SDCx + ); // TODO: Cache instruction + casez (instr) + 32'b00000000000???????????????000000: ri = 1'b0; // SLL + 32'b00000000000???????????????000010: ri = 1'b0; // SRL + 32'b00000000000???????????????000011: ri = 1'b0; // SRA + 32'b000000???????????????00000000100: ri = 1'b0; // SLLV + 32'b000000???????????????00000000110: ri = 1'b0; // SRLV + 32'b000000???????????????00000000111: ri = 1'b0; // SRAV + 32'b000000?????0000000000?????001000: ri = 1'b0; // JR + 32'b000000?????00000??????????001001: ri = 1'b0; // JALR + 32'b000000???????????????00000001010: ri = 1'b0; // MOVZ + 32'b000000???????????????00000001011: ri = 1'b0; // MOVN + 32'b000000????????????????????001100: ri = 1'b0; // SYSCALL + 32'b000000????????????????????001101: ri = 1'b0; // BREAK + 32'b000000000000000000000?????001111: ri = 1'b0; // SYNC (NOP) + 32'b0000000000000000?????00000010000: ri = 1'b0; // MFHI + 32'b000000?????000000000000000010001: ri = 1'b0; // MTHI + 32'b0000000000000000?????00000010010: ri = 1'b0; // MFLO + 32'b000000?????000000000000000010011: ri = 1'b0; // MTLO + 32'b000000??????????0000000000011000: ri = 1'b0; // MULT + 32'b000000??????????0000000000011001: ri = 1'b0; // MULTU + 32'b000000??????????0000000000011010: ri = 1'b0; // DIV + 32'b000000??????????0000000000011011: ri = 1'b0; // DIVU + 32'b000000???????????????00000100000: ri = 1'b0; // ADD + 32'b000000???????????????00000100001: ri = 1'b0; // ADDU + 32'b000000???????????????00000100010: ri = 1'b0; // SUB + 32'b000000???????????????00000100011: ri = 1'b0; // SUBU + 32'b000000???????????????00000100100: ri = 1'b0; // AND + 32'b000000???????????????00000100101: ri = 1'b0; // OR + 32'b000000???????????????00000100110: ri = 1'b0; // XOR + 32'b000000???????????????00000100111: ri = 1'b0; // NOR + 32'b000000???????????????00000101010: ri = 1'b0; // SLT + 32'b000000???????????????00000101011: ri = 1'b0; // SLTU + 32'b000000????????????????????110000: ri = 1'b0; // TGE + 32'b000000????????????????????110001: ri = 1'b0; // TGEU + 32'b000000????????????????????110010: ri = 1'b0; // TLT + 32'b000000????????????????????110011: ri = 1'b0; // TLTU + 32'b000000????????????????????110100: ri = 1'b0; // TEQ + 32'b000000????????????????????110110: ri = 1'b0; // TNE + 32'b000001?????00000????????????????: ri = 1'b0; // BLTZ + 32'b000001?????00001????????????????: ri = 1'b0; // BGEZ + 32'b000001?????01000????????????????: ri = 1'b0; // TGEI + 32'b000001?????01001????????????????: ri = 1'b0; // TGEIU + 32'b000001?????01010????????????????: ri = 1'b0; // TLTI + 32'b000001?????01011????????????????: ri = 1'b0; // TLTIU + 32'b000001?????01110????????????????: ri = 1'b0; // TNEI + 32'b000001?????01100????????????????: ri = 1'b0; // TEQI + 32'b000001?????10000????????????????: ri = 1'b0; // BLTZAL + 32'b000001?????10001????????????????: ri = 1'b0; // BGEZAL + 32'b000010??????????????????????????: ri = 1'b0; // J + 32'b000011??????????????????????????: ri = 1'b0; // JAL + 32'b000100??????????????????????????: ri = 1'b0; // BEQ + 32'b000101??????????????????????????: ri = 1'b0; // BNE + 32'b000110?????00000????????????????: ri = 1'b0; // BLEZ + 32'b000111?????00000????????????????: ri = 1'b0; // BGTZ + 32'b001000??????????????????????????: ri = 1'b0; // ADDI + 32'b001001??????????????????????????: ri = 1'b0; // ADDIU + 32'b001010??????????????????????????: ri = 1'b0; // SLTI + 32'b001011??????????????????????????: ri = 1'b0; // SLTIU + 32'b001100??????????????????????????: ri = 1'b0; // ANDI + 32'b001101??????????????????????????: ri = 1'b0; // ORI + 32'b001110??????????????????????????: ri = 1'b0; // XORI + 32'b00111100000?????????????????????: ri = 1'b0; // LUI + 32'b01000000000??????????00000000???: ri = 1'b0; // MFC0 + 32'b01000000100??????????00000000???: ri = 1'b0; // MTC0 + 32'b01000010000000000000000000000001: ri = 1'b0; // TLBR + 32'b01000010000000000000000000000010: ri = 1'b0; // TLBWI + 32'b01000010000000000000000000000110: ri = 1'b0; // TLBWR + 32'b01000010000000000000000000001000: ri = 1'b0; // TLBP + 32'b01000010000000000000000000011000: ri = 1'b0; // ERET + 32'b011100??????????0000000000000000: ri = 1'b0; // MADD + 32'b011100??????????0000000000000001: ri = 1'b0; // MADDU + 32'b011100??????????0000000000000100: ri = 1'b0; // MSUB + 32'b011100??????????0000000000000101: ri = 1'b0; // MSUBU + 32'b011100???????????????00000000010: ri = 1'b0; // MUL + // 32'b01111100000??????????00000111011: begin cpu = 1'b1; ce = 2'b0; end // RDHWR (CpU) + 32'b100000??????????????????????????: ri = 1'b0; // LB + 32'b100001??????????????????????????: ri = 1'b0; // LH + 32'b100010??????????????????????????: ri = 1'b0; // LWL + 32'b100011??????????????????????????: ri = 1'b0; // LW + 32'b100100??????????????????????????: ri = 1'b0; // LBU + 32'b100101??????????????????????????: ri = 1'b0; // LHU + 32'b100110??????????????????????????: ri = 1'b0; // LWR + 32'b101000??????????????????????????: ri = 1'b0; // SB + 32'b101001??????????????????????????: ri = 1'b0; // SH + 32'b101010??????????????????????????: ri = 1'b0; // SWL + 32'b101011??????????????????????????: ri = 1'b0; // SW + 32'b101110??????????????????????????: ri = 1'b0; // SWR + 32'b101111?????00000????????????????: ri = 1'b0; // I-Cache Index Invalid + 32'b101111?????01000????????????????: ri = 1'b0; // I-Cache Index Store Tag + 32'b101111?????10000????????????????: ri = 1'b0; // I-Cache Hit Invalid + 32'b101111?????00001????????????????: ri = 1'b0; // D-Cache Index Writeback Invalid + 32'b101111?????01001????????????????: ri = 1'b0; // D-Cache Index Store Tag + 32'b101111?????10001????????????????: ri = 1'b0; // D-Cache Hit Invalid + 32'b101111?????10101????????????????: ri = 1'b0; // D-Cache Hit Writeback Invalid + // 32'b110000??????????????????????????: begin cpu = 1'b1; ce = 2'b0; end // LL (CpU) + 32'b110011??????????????????????????: ri = 1'b0; // PREF (NOP) + // 32'b111000??????????????????????????: begin cpu = 1'b1; ce = 2'b0; end // SC (CpU) + endcase + end +endmodule diff --git a/src/Core/Gadgets/instr_valid.sv b/src/Core/Gadgets/instr_valid.sv deleted file mode 100644 index 656d4e8..0000000 --- a/src/Core/Gadgets/instr_valid.sv +++ /dev/null @@ -1,105 +0,0 @@ -`include "defines.svh" - -module instr_valid ( - input word_t instr, - output logic valid -); - - always_comb - casez (instr) - 32'b000000000000000000000?????001111: valid = 1'b1; // SYNC (NOP) - 32'b00000000000???????????????000000: valid = 1'b1; // SLL - 32'b00000000000???????????????000010: valid = 1'b1; // SRL - 32'b00000000000???????????????000011: valid = 1'b1; // SRA - 32'b000000???????????????00000000100: valid = 1'b1; // SLLV - 32'b000000???????????????00000000110: valid = 1'b1; // SRLV - 32'b000000???????????????00000000111: valid = 1'b1; // SRAV - 32'b000000???????????????00000001010: valid = 1'b1; // MOVZ - 32'b000000???????????????00000001011: valid = 1'b1; // MOVN - 32'b000000?????000000000000000001000: valid = 1'b1; // JR - 32'b000000?????00000?????00000001001: valid = 1'b1; // JALR - 32'b000000????????????????????001100: valid = 1'b1; // SYSCALL - 32'b000000????????????????????001101: valid = 1'b1; // BREAK - 32'b0000000000000000?????00000010000: valid = 1'b1; // MFHI - 32'b000000?????000000000000000010001: valid = 1'b1; // MTHI - 32'b0000000000000000?????00000010010: valid = 1'b1; // MFLO - 32'b000000?????000000000000000010011: valid = 1'b1; // MTLO - 32'b000000??????????0000000000011000: valid = 1'b1; // MULT - 32'b000000??????????0000000000011001: valid = 1'b1; // MULTU - 32'b000000??????????0000000000011010: valid = 1'b1; // DIV - 32'b000000??????????0000000000011011: valid = 1'b1; // DIVU - 32'b000000???????????????00000100000: valid = 1'b1; // ADD - 32'b000000???????????????00000100001: valid = 1'b1; // ADDU - 32'b000000???????????????00000100010: valid = 1'b1; // SUB - 32'b000000???????????????00000100011: valid = 1'b1; // SUBU - 32'b000000???????????????00000100100: valid = 1'b1; // AND - 32'b000000???????????????00000100101: valid = 1'b1; // OR - 32'b000000???????????????00000100110: valid = 1'b1; // XOR - 32'b000000???????????????00000100111: valid = 1'b1; // NOR - 32'b000000???????????????00000101010: valid = 1'b1; // SLT - 32'b000000???????????????00000101011: valid = 1'b1; // SLTU - 32'b000000????????????????????110000: valid = 1'b1; // TGE - 32'b000000????????????????????110001: valid = 1'b1; // TGEU - 32'b000000????????????????????110010: valid = 1'b1; // TLT - 32'b000000????????????????????110011: valid = 1'b1; // TLTU - 32'b000000????????????????????110100: valid = 1'b1; // TEQ - 32'b000000????????????????????110110: valid = 1'b1; // TNE - 32'b000001?????00000????????????????: valid = 1'b1; // BLTZ - 32'b000001?????00001????????????????: valid = 1'b1; // BGEZ - 32'b000001?????01000????????????????: valid = 1'b1; // TGEI - 32'b000001?????01001????????????????: valid = 1'b1; // TGEIU - 32'b000001?????01010????????????????: valid = 1'b1; // TLTI - 32'b000001?????01011????????????????: valid = 1'b1; // TLTIU - 32'b000001?????01110????????????????: valid = 1'b1; // TNEI - 32'b000001?????01100????????????????: valid = 1'b1; // TEQI - 32'b000001?????10000????????????????: valid = 1'b1; // BLTZAL - 32'b000001?????10001????????????????: valid = 1'b1; // BGEZAL - 32'b000010??????????????????????????: valid = 1'b1; // J - 32'b000011??????????????????????????: valid = 1'b1; // JAL - 32'b000100??????????????????????????: valid = 1'b1; // BEQ - 32'b000101??????????????????????????: valid = 1'b1; // BNE - 32'b000110?????00000????????????????: valid = 1'b1; // BLEZ - 32'b000111?????00000????????????????: valid = 1'b1; // BGTZ - 32'b001000??????????????????????????: valid = 1'b1; // ADDI - 32'b001001??????????????????????????: valid = 1'b1; // ADDIU - 32'b001010??????????????????????????: valid = 1'b1; // SLTI - 32'b001011??????????????????????????: valid = 1'b1; // SLTIU - 32'b001100??????????????????????????: valid = 1'b1; // ANDI - 32'b001101??????????????????????????: valid = 1'b1; // ORI - 32'b001110??????????????????????????: valid = 1'b1; // XORI - 32'b00111100000?????????????????????: valid = 1'b1; // LUI - 32'b01000000000??????????00000000???: valid = 1'b1; // MFC0 - 32'b01000000100??????????00000000???: valid = 1'b1; // MTC0 - 32'b01000010000000000000000000000001: valid = 1'b1; // TLBR - 32'b01000010000000000000000000000010: valid = 1'b1; // TLBWI - 32'b01000010000000000000000000000110: valid = 1'b1; // TLBWR - 32'b01000010000000000000000000001000: valid = 1'b1; // TLBP - 32'b01000010000000000000000000011000: valid = 1'b1; // ERET - 32'b011100??????????0000000000000000: valid = 1'b1; // MADD - 32'b011100??????????0000000000000001: valid = 1'b1; // MADDU - 32'b011100??????????0000000000000100: valid = 1'b1; // MSUB - 32'b011100??????????0000000000000101: valid = 1'b1; // MSUBU - 32'b011100???????????????00000000010: valid = 1'b1; // MUL - 32'b100000??????????????????????????: valid = 1'b1; // LB - 32'b100001??????????????????????????: valid = 1'b1; // LH - 32'b100010??????????????????????????: valid = 1'b1; // LWL - 32'b100011??????????????????????????: valid = 1'b1; // LW - 32'b100100??????????????????????????: valid = 1'b1; // LBU - 32'b100101??????????????????????????: valid = 1'b1; // LHU - 32'b100110??????????????????????????: valid = 1'b1; // LWR - 32'b101000??????????????????????????: valid = 1'b1; // SB - 32'b101001??????????????????????????: valid = 1'b1; // SH - 32'b101010??????????????????????????: valid = 1'b1; // SWL - 32'b101011??????????????????????????: valid = 1'b1; // SW - 32'b101110??????????????????????????: valid = 1'b1; // SWR - 32'b101111?????00000????????????????: valid = 1'b1; // I-Cache Index Invalid - 32'b101111?????01000????????????????: valid = 1'b1; // I-Cache Index Store Tag - 32'b101111?????10000????????????????: valid = 1'b1; // I-Cache Hit Invalid - 32'b101111?????00001????????????????: valid = 1'b1; // D-Cache Index Writeback Invalid - 32'b101111?????01001????????????????: valid = 1'b1; // D-Cache Index Store Tag - 32'b101111?????10001????????????????: valid = 1'b1; // D-Cache Hit Invalid - 32'b101111?????10101????????????????: valid = 1'b1; // D-Cache Hit Writeback Invalid - 32'b110011??????????????????????????: valid = 1'b1; // PREF (NOP) - default: valid = 1'b0; - endcase -endmodule diff --git a/src/MU/interface.sv b/src/MU/interface.sv index 6cfdb37..f0e97b3 100644 --- a/src/MU/interface.sv +++ b/src/MU/interface.sv @@ -122,29 +122,34 @@ interface AXIWrite_i; endinterface interface CP0_i; - logic [2:0] cp0_K0; - logic cp0_in_kernel; - logic cpu_tlbwi; - logic cpu_tlbwr; - logic cpu_c0_tlbp; - logic cpu_tlb_tlbp; - logic cpu_tlbr; - Random_t cp0_Random; // TLBWR - EntryHi_t cp0_EntryHi; // TLBWI + F/M(ASID) - EntryLo_t cp0_EntryLo1; // TLBWI - EntryLo_t cp0_EntryLo0; // TLBWI - Index_t cp0_Index; // TLBWI + TLBR - EntryHi_t tlb_EntryHi; - EntryLo_t tlb_EntryLo1; - EntryLo_t tlb_EntryLo0; - Index_t tlb_Index; // TLBP - logic tlb_iTLBRefill; - logic tlb_iTLBInvalid; - logic tlb_iAddressError; - logic tlb_dTLBRefill; - logic tlb_dTLBInvalid; - logic tlb_dTLBModified; - logic tlb_dAddressError; + logic [2:0] cp0_K0; + logic [3:0] cp0_CU; + logic cp0_in_kernel; + logic cpu_tlbwi; + logic cpu_tlbwr; + logic cpu_c0_tlbp; + logic cpu_tlb_tlbp; + logic cpu_tlbr; + EXCEPTION_t cpu_exception; + Random_t cp0_Random; // TLBWR + EntryHi_t cp0_EntryHi; // TLBWI + F/M(ASID) + EntryLo_t cp0_EntryLo1; // TLBWI + EntryLo_t cp0_EntryLo0; // TLBWI + Index_t cp0_Index; // TLBWI + TLBR + word_t cp0_EPC; + logic cp0_Bev; + logic [19:0] cp0_EBase; + EntryHi_t tlb_EntryHi; + EntryLo_t tlb_EntryLo1; + EntryLo_t tlb_EntryLo0; + Index_t tlb_Index; // TLBP + logic tlb_iTLBRefill; + logic tlb_iTLBInvalid; + logic tlb_iAddressError; + logic tlb_dTLBRefill; + logic tlb_dTLBInvalid; + logic tlb_dTLBModified; + logic tlb_dAddressError; modport mu( input cp0_K0, @@ -171,6 +176,7 @@ interface CP0_i; ); modport cp0( output cp0_K0, + output cp0_CU, output cp0_in_kernel, input cpu_c0_tlbp, input cpu_tlbr, @@ -180,11 +186,15 @@ interface CP0_i; // output cp0_PageMask, output cp0_EntryLo1, output cp0_EntryLo0, + output cp0_EPC, + output cp0_Bev, + output cp0_EBase, input tlb_EntryHi, // input tlb_PageMask, input tlb_EntryLo1, input tlb_EntryLo0, - input tlb_Index + input tlb_Index, + input cpu_exception ); modport cpu( output cpu_tlbwi, @@ -192,7 +202,12 @@ interface CP0_i; output cpu_c0_tlbp, output cpu_tlb_tlbp, output cpu_tlbr, + output cpu_exception, + input cp0_CU, input cp0_in_kernel, + input cp0_EPC, + input cp0_Bev, + input cp0_EBase, input tlb_iTLBRefill, input tlb_iTLBInvalid, input tlb_iAddressError, diff --git a/src/include/CP0.svh b/src/include/CP0.svh index 4c36723..e142c2f 100644 --- a/src/include/CP0.svh +++ b/src/include/CP0.svh @@ -42,6 +42,7 @@ typedef enum bit [4:0] { typedef struct packed { logic ExcValid; logic Delay; + logic [1:0] CE; logic [4:0] ExcCode; word_t BadVAddr; word_t EPC; @@ -59,30 +60,30 @@ typedef struct packed { logic [2:0] K0; } CP0_REGS_CONFIG_t; -typedef struct packed { - logic [1:0] zero1; - logic CU0; - logic [5:0] zero2; - logic Bev; - logic [5:0] zero3; - logic [7:0] IM; - logic [2:0] zero4; - logic UM; - logic [1:0] zero5; - logic EXL; - logic IE; -} CP0_REGS_STATUS_t; - typedef struct packed { logic BD; logic TI; - logic [13:0] zero1; + logic [1:0] CE; + logic [11:0] zero1; logic [7:0] IP; logic zero2; logic [4:0] ExcCode; logic [1:0] zero3; } CP0_REGS_CAUSE_t; +typedef struct packed { + logic [3:0] CU; + logic [4:0] zero1; + logic Bev; + logic [5:0] zero2; + logic [7:0] IM; + logic [2:0] zero3; + logic UM; + logic [1:0] zero4; + logic EXL; + logic IE; +} CP0_REGS_STATUS_t; + typedef struct packed { logic one; logic zero1; diff --git a/src/include/defines.svh b/src/include/defines.svh index ca33b55..f0a26fc 100644 --- a/src/include/defines.svh +++ b/src/include/defines.svh @@ -1,9 +1,10 @@ `ifndef DEFINES_SVH `define DEFINES_SVH -`define XLEN 32 `define ENABLE_TLB +`define ENABLE_CpU +`define XLEN 32 `define PCRST 32'hBFC00000 `define Off_TRef 9'h000 `define Off_GExc 9'h180 @@ -27,7 +28,13 @@ `define EXCCODE_SYS 5'h08 `define EXCCODE_BP 5'h09 `define EXCCODE_RI 5'h0A + +`ifdef ENABLE_CpU `define EXCCODE_CPU 5'h0B +`else +`define EXCCODE_CPU 5'h0A +`endif + `define EXCCODE_OV 5'h0C `define EXCCODE_TR 5'h0D @@ -195,6 +202,7 @@ typedef struct packed { logic IA_ERET; logic IA_REFILL; logic [4:0] IA_ExcCode; + logic [1:0] IA_CE; logic IA_Delay; word_t IA_S; word_t IA_T; @@ -207,6 +215,7 @@ typedef struct packed { logic IB_ERET; logic IB_REFILL; logic [4:0] IB_ExcCode; + logic [1:0] IB_CE; logic IB_Delay; word_t IB_S; word_t IB_T; @@ -220,6 +229,7 @@ typedef struct packed { logic ERET; logic REFILL; logic [4:0] ExcCode; + logic [1:0] CE; logic Delay; logic OFA; @@ -246,6 +256,7 @@ typedef struct packed { logic ERET; logic REFILL; logic [4:0] ExcCode; + logic [1:0] CE; logic Delay; logic OFA; @@ -278,6 +289,7 @@ typedef struct packed { logic ERET; logic REFILL; logic [4:0] ExcCode; + logic [1:0] CE; logic Delay; logic OFA; @@ -305,6 +317,7 @@ typedef struct packed { logic ERET; logic REFILL; logic [4:0] ExcCode; + logic [1:0] CE; word_t BadVAddr; logic Delay; logic OFA; @@ -339,6 +352,7 @@ typedef struct packed { logic ERET; logic REFILL; logic [4:0] ExcCode; + logic [1:0] CE; word_t BadVAddr; logic Delay; @@ -363,6 +377,7 @@ typedef struct packed { logic ERET; logic REFILL; logic [4:0] ExcCode; + logic [1:0] CE; word_t BadVAddr; logic Delay; diff --git a/src/mycpu_top.sv b/src/mycpu_top.sv index c4b851c..b21d612 100644 --- a/src/mycpu_top.sv +++ b/src/mycpu_top.sv @@ -83,37 +83,6 @@ module mycpu_top ( word_t C0_rdata; logic C0_we; word_t C0_wdata; - EXCEPTION_t C0_exception; - word_t C0_ERETPC; - logic C0_Bev; - logic [19:0] C0_EBase; - logic [2:0] K0; - logic in_kernel; - Random_t c0_Random; - Index_t c0_Index; - EntryHi_t c0_EntryHi; - // PageMask_t c0_PageMask; - EntryLo_t c0_EntryLo1; - EntryLo_t c0_EntryLo0; - EntryHi_t tlb_EntryHi; - // PageMask_t tlb_PageMask; - EntryLo_t tlb_EntryLo1; - EntryLo_t tlb_EntryLo0; - Index_t tlb_Index; - - logic iTLBRefill; - logic iTLBInvalid; - logic iAddressError; - logic dTLBRefill; - logic dTLBInvalid; - logic dTLBModified; - logic dAddressError; - logic tlb_tlbwi; - logic tlb_tlbwr; - logic tlb_tlbp; - logic c0_tlbr; - logic c0_tlbp; - AXI axi ( .arid (arid), @@ -196,10 +165,6 @@ module mycpu_top ( .rdata (C0_rdata), .en (C0_we), .wdata (C0_wdata), - .exception (C0_exception), - .EPC (C0_ERETPC), - .Bev (C0_Bev), - .EBase (C0_EBase), .ext_int (ext_int), .interrupt (C0_int), .c0 (c0.cp0) @@ -219,10 +184,6 @@ module mycpu_top ( .C0_rdata (C0_rdata), .C0_we (C0_we), .C0_wdata (C0_wdata), - .C0_exception(C0_exception), - .C0_ERETPC (C0_ERETPC), - .C0_Bev (C0_Bev), - .C0_EBase (C0_EBase), .debug_wb_pc (debug_wb_pc), .debug_wb_rf_wen (debug_wb_rf_wen),