Update ENABLE_TLB
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14
sim/Makefile
14
sim/Makefile
@ -50,7 +50,7 @@ FUNC_SOURCE = $(wildcard ../resources/tb.sv ../resources/func_test/*.v ../resour
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####################
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# Targets #
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####################
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.phony: lint verilate func_build func_coverage func_run clean
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.phony: lint verilate func_soft tlb_soft build coverage run clean
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default: func_run
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@ -60,14 +60,20 @@ lint:
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verilate:
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$(VERILATOR) $(VERILATOR_FLAGS) $(VERILATOR_BUILD_FLAGS) $(INCLUDE) $(SOURCE) $(FUNC_SOURCE) $(VERILATOR_INPUT)
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func_build: verilate
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func_soft:
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cd ../resources/soft/func && make clean && make && cp obj/axi_ram.mif ../../../sim && cd ../../../sim
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tlb_soft:
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cd ../resources/soft/tlb_func && make clean && make && cp obj/axi_ram.mif ../../../sim && cd ../../../sim
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build: verilate
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make -C obj_dir -f Vtestbench_top.mk -j
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func_coverage:
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coverage:
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@rm -rf logs/annotated
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$(VERILATOR_COVERAGE) $(VERILATOR_COV_FLAGS)
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func_run: func_build
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run: build
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@rm -rf logs
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obj_dir/Vtestbench_top
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gtkwave logs/trace.fst
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@ -511,7 +511,9 @@ module Datapath (
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| M.I1.WCtrl.RW & D.IA.RT == M.I1.RD & D.IA.DT & M.I1.MCtrl.MR
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// CP0 Execution Hazards
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// Hazards Related to the TLB
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`ifdef ENABLE_TLB
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| E.I0.MCtrl.C0W & D.IA.MCtrl1.TLBP & E.I0.MCtrl.C0D == C0_ENTRYHI
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`endif
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;
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// Not Arith -> Arith
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@ -542,6 +544,7 @@ module Datapath (
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| M.I1.WCtrl.RW & D.IB.RT == M.I1.RD & D.IB.DT & M.I1.MCtrl.MR
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// CP0 Execution Hazards
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// Hazards Related to the TLB
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`ifdef ENABLE_TLB
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| D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBR & D.IA.MCtrl0.C0D == C0_INDEX
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| D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBWI & D.IA.MCtrl0.C0D == C0_ENTRYHI
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| D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBWI & D.IA.MCtrl0.C0D == C0_ENTRYLO0
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@ -559,6 +562,7 @@ module Datapath (
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| D.IA.MCtrl1.TLBR & D.IB.WCtrl.RW & D.IB.MCtrl0.C0D == C0_ENTRYLO1 & D.IB.MCtrl0.RS0 == RS0_C0
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// | D.IA.MCtrl1.TLBR & D.IB.WCtrl.RW & D.IB.MCtrl0.C0D == C0_PAGEMASK & D.IB.MCtrl0.RS0 == RS0_C0
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| D.IA.MCtrl1.TLBP & D.IB.WCtrl.RW & D.IB.MCtrl0.C0D == C0_INDEX & D.IB.MCtrl0.RS0 == RS0_C0
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`endif
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// Hazards Related to Exceptions or Interrupts
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| D.IA.MCtrl0.C0W & D.IB.ERET & D.IA.MCtrl0.C0D == C0_EPC
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;
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@ -805,7 +809,12 @@ module Datapath (
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E.en,
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E.I1.ECtrl
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);
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ffenrc #(15) E_I1_MCtrl_ff (
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`ifdef ENABLE_TLB
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ffenrc #(15)
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`else
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ffenrc #(11)
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`endif
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E_I1_MCtrl_ff (
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clk,
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rst | rstM,
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D.I1.MCtrl,
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@ -947,7 +956,11 @@ module Datapath (
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E_I1_STRBERROR
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);
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`ifdef ENABLE_TLB
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assign C0.cpu_tlb_tlbp = E.I1.MCtrl.TLBP;
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`else
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assign C0.cpu_tlb_tlbp = 0;
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`endif
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assign mem.req = E.I1.MCtrl.MR & E_I1_goWithoutOF & M.en & ~rstM;
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assign E_I1_ADDR = E_I1_ForwardS + E.I1.imm;
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assign mem.addr = |E.I1.MCtrl.ALR ? {E_I1_ADDR[31:2], 2'b0} : E_I1_ADDR;
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@ -1109,7 +1122,12 @@ module Datapath (
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M.en,
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M.I1.ALUOut
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);
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ffenrc #(15) M_I1_MCtrl_ff (
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`ifdef ENABLE_TLB
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ffenrc #(15)
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`else
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ffenrc #(11)
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`endif
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M_I1_MCtrl_ff (
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clk,
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rst | rstM,
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E.I1.MCtrl,
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@ -1152,7 +1170,15 @@ module Datapath (
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dTLBExcValid,
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{dTLBRefillB, dTLBInvalidB, dTLBModifiedB, dAddressErrorB}
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);
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assign M_I1_NowExcValid = dTLBRefillB | dTLBInvalidB | dTLBModifiedB | dAddressErrorB | M_I1_Trap;
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assign M_I1_NowExcValid = 0
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`ifdef ENABLE_TLB
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| dTLBRefillB | dTLBInvalidB | dTLBModifiedB | dAddressErrorB
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`endif
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`ifdef ENABLE_TRAP
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| M_I1_Trap
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`endif
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;
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assign M.I1.ExcValid = M_I1_PrevExcValid | M_I1_NowExcValid;
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assign M.I1.REFILL = M_I1_PrevREFILL | dTLBRefillB;
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assign M.I1.ExcCode = M_I1_PrevExcValid ? M_I1_PrevExcCode
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@ -1260,10 +1286,18 @@ module Datapath (
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assign C0_wdata = M_I0_ForwardT;
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// M.I1.MEM
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`ifdef ENABLE_TLB
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assign C0.cpu_tlbwi = M.I1.MCtrl.TLBWI;
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assign C0.cpu_tlbwr = M.I1.MCtrl.TLBWR;
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assign C0.cpu_tlbr = M.I1.MCtrl.TLBR;
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assign C0.cpu_c0_tlbp = M.I1.MCtrl.TLBP & M.en;
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`else
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assign C0.cpu_tlbwi = 0;
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assign C0.cpu_tlbwr = 0;
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assign C0.cpu_tlbr = 0;
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assign C0.cpu_c0_tlbp = 0;
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`endif
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assign mem.wr = M.I1.MCtrl.MWR;
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memoutput M_I1_memoutput (
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.addr (M.I1.ALUOut[1:0]),
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