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Update ENABLE_TLB

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This commit is contained in:
Paul Pan 2022-08-04 11:53:11 +08:00
parent 02f04a2bf3
commit d487e8583d
2 changed files with 47 additions and 7 deletions
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14
sim/Makefile
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@ -50,7 +50,7 @@ FUNC_SOURCE = $(wildcard ../resources/tb.sv ../resources/func_test/*.v ../resour
####################
# Targets #
####################
.phony: lint verilate func_build func_coverage func_run clean
.phony: lint verilate func_soft tlb_soft build coverage run clean
default: func_run
@ -60,14 +60,20 @@ lint:
verilate:
$(VERILATOR) $(VERILATOR_FLAGS) $(VERILATOR_BUILD_FLAGS) $(INCLUDE) $(SOURCE) $(FUNC_SOURCE) $(VERILATOR_INPUT)
func_build: verilate
func_soft:
cd ../resources/soft/func && make clean && make && cp obj/axi_ram.mif ../../../sim && cd ../../../sim
tlb_soft:
cd ../resources/soft/tlb_func && make clean && make && cp obj/axi_ram.mif ../../../sim && cd ../../../sim
build: verilate
make -C obj_dir -f Vtestbench_top.mk -j
func_coverage:
coverage:
@rm -rf logs/annotated
$(VERILATOR_COVERAGE) $(VERILATOR_COV_FLAGS)
func_run: func_build
run: build
@rm -rf logs
obj_dir/Vtestbench_top
gtkwave logs/trace.fst

40
src/Core/Datapath.sv
View File

@ -511,7 +511,9 @@ module Datapath (
| M.I1.WCtrl.RW & D.IA.RT == M.I1.RD & D.IA.DT & M.I1.MCtrl.MR
// CP0 Execution Hazards
// Hazards Related to the TLB
`ifdef ENABLE_TLB
| E.I0.MCtrl.C0W & D.IA.MCtrl1.TLBP & E.I0.MCtrl.C0D == C0_ENTRYHI
`endif
;
// Not Arith -> Arith
@ -542,6 +544,7 @@ module Datapath (
| M.I1.WCtrl.RW & D.IB.RT == M.I1.RD & D.IB.DT & M.I1.MCtrl.MR
// CP0 Execution Hazards
// Hazards Related to the TLB
`ifdef ENABLE_TLB
| D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBR & D.IA.MCtrl0.C0D == C0_INDEX
| D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBWI & D.IA.MCtrl0.C0D == C0_ENTRYHI
| D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBWI & D.IA.MCtrl0.C0D == C0_ENTRYLO0
@ -559,6 +562,7 @@ module Datapath (
| D.IA.MCtrl1.TLBR & D.IB.WCtrl.RW & D.IB.MCtrl0.C0D == C0_ENTRYLO1 & D.IB.MCtrl0.RS0 == RS0_C0
// | D.IA.MCtrl1.TLBR & D.IB.WCtrl.RW & D.IB.MCtrl0.C0D == C0_PAGEMASK & D.IB.MCtrl0.RS0 == RS0_C0
| D.IA.MCtrl1.TLBP & D.IB.WCtrl.RW & D.IB.MCtrl0.C0D == C0_INDEX & D.IB.MCtrl0.RS0 == RS0_C0
`endif
// Hazards Related to Exceptions or Interrupts
| D.IA.MCtrl0.C0W & D.IB.ERET & D.IA.MCtrl0.C0D == C0_EPC
;
@ -805,7 +809,12 @@ module Datapath (
E.en,
E.I1.ECtrl
);
ffenrc #(15) E_I1_MCtrl_ff (
`ifdef ENABLE_TLB
ffenrc #(15)
`else
ffenrc #(11)
`endif
E_I1_MCtrl_ff (
clk,
rst | rstM,
D.I1.MCtrl,
@ -947,7 +956,11 @@ module Datapath (
E_I1_STRBERROR
);
`ifdef ENABLE_TLB
assign C0.cpu_tlb_tlbp = E.I1.MCtrl.TLBP;
`else
assign C0.cpu_tlb_tlbp = 0;
`endif
assign mem.req = E.I1.MCtrl.MR & E_I1_goWithoutOF & M.en & ~rstM;
assign E_I1_ADDR = E_I1_ForwardS + E.I1.imm;
assign mem.addr = |E.I1.MCtrl.ALR ? {E_I1_ADDR[31:2], 2'b0} : E_I1_ADDR;
@ -1109,7 +1122,12 @@ module Datapath (
M.en,
M.I1.ALUOut
);
ffenrc #(15) M_I1_MCtrl_ff (
`ifdef ENABLE_TLB
ffenrc #(15)
`else
ffenrc #(11)
`endif
M_I1_MCtrl_ff (
clk,
rst | rstM,
E.I1.MCtrl,
@ -1152,7 +1170,15 @@ module Datapath (
dTLBExcValid,
{dTLBRefillB, dTLBInvalidB, dTLBModifiedB, dAddressErrorB}
);
assign M_I1_NowExcValid = dTLBRefillB | dTLBInvalidB | dTLBModifiedB | dAddressErrorB | M_I1_Trap;
assign M_I1_NowExcValid = 0
`ifdef ENABLE_TLB
| dTLBRefillB | dTLBInvalidB | dTLBModifiedB | dAddressErrorB
`endif
`ifdef ENABLE_TRAP
| M_I1_Trap
`endif
;
assign M.I1.ExcValid = M_I1_PrevExcValid | M_I1_NowExcValid;
assign M.I1.REFILL = M_I1_PrevREFILL | dTLBRefillB;
assign M.I1.ExcCode = M_I1_PrevExcValid ? M_I1_PrevExcCode
@ -1260,10 +1286,18 @@ module Datapath (
assign C0_wdata = M_I0_ForwardT;
// M.I1.MEM
`ifdef ENABLE_TLB
assign C0.cpu_tlbwi = M.I1.MCtrl.TLBWI;
assign C0.cpu_tlbwr = M.I1.MCtrl.TLBWR;
assign C0.cpu_tlbr = M.I1.MCtrl.TLBR;
assign C0.cpu_c0_tlbp = M.I1.MCtrl.TLBP & M.en;
`else
assign C0.cpu_tlbwi = 0;
assign C0.cpu_tlbwr = 0;
assign C0.cpu_tlbr = 0;
assign C0.cpu_c0_tlbp = 0;
`endif
assign mem.wr = M.I1.MCtrl.MWR;
memoutput M_I1_memoutput (
.addr (M.I1.ALUOut[1:0]),