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[Cache] ICache fix bug

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This commit is contained in:
Paul Pan 2021-07-10 22:38:29 +08:00
parent e5dfdd27b5
commit d4521234b4
5 changed files with 96 additions and 54 deletions
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6
src/AXI/AXI.sv
View File

@ -18,10 +18,6 @@ module AXI (
AXIStatus_t status, nextStatus;
initial begin
status = ASIdle;
end
/*
----- ICache -----
ReadAddr:
@ -73,6 +69,7 @@ module AXI (
// read status switch
always_comb begin
IReadAllowReq = 1'b1;
IReadAddr = 32'b0;
IReadReqPending = 1'b0;
nextStatus = status;
@ -94,6 +91,7 @@ module AXI (
// 处理ICache读过程
ASReadInst: begin
IReadAllowReq = 1'b0;
if (IReadRespOK) begin
// 不和ICache握手, 直接返回
nextStatus = ASIdle;

70
src/Cache/ICache.sv
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@ -57,7 +57,7 @@ module ICache (
wire [`IC_DATA_LENGTH-1:0] cacheLine1; // Cache Line
wire [31:0] cacheLineData1[4]; // tmp: Map Cache Line into 4 Cache Data
logic cacheMiss;
wire cacheMiss;
// Miss
wire req2;
@ -122,34 +122,12 @@ module ICache (
.q (wen0)
);
ffenr #(637) pipelineReg1 (
ffenr #(33) pipelineReg1 (
.clk(clk),
.rst(rst | wen0),
.en(~cacheMiss),
.d({
sram.addr,
TagRAM0.rdata,
TagRAM1.rdata,
TagRAM2.rdata,
TagRAM3.rdata,
DataRAM0.rdata,
DataRAM1.rdata,
DataRAM2.rdata,
DataRAM3.rdata,
req0
}),
.q({
PC1, // sram.addr
tagOut1[0], // TagRAM
tagOut1[1],
tagOut1[2],
tagOut1[3],
dataOut1[0], // DataRAM
dataOut1[1],
dataOut1[2],
dataOut1[3],
req1 // req
})
.en (~cacheMiss),
.d ({sram.addr, req0}),
.q ({PC1, req1})
);
// ==============================
@ -165,10 +143,10 @@ module ICache (
assign hitWay1[3] = tagOut1[3][0] & tagOut1[3][`IC_TAG_LENGTH-1:1] == tag1;
assign hit1 = hitWay1[0] | hitWay1[1] | hitWay1[2] | hitWay1[3];
assign cacheLine1 = (hitWay1[0] ? dataOut1 : `IC_DATA_LENGTH'b0) |
(hitWay1[1] ? dataOut1 : `IC_DATA_LENGTH'b0) |
(hitWay1[2] ? dataOut1 : `IC_DATA_LENGTH'b0) |
(hitWay1[3] ? dataOut1 : `IC_DATA_LENGTH'b0);
assign cacheLine1 = (hitWay1[0] ? dataOut1[0] : `IC_DATA_LENGTH'b0) |
(hitWay1[1] ? dataOut1[1] : `IC_DATA_LENGTH'b0) |
(hitWay1[2] ? dataOut1[2] : `IC_DATA_LENGTH'b0) |
(hitWay1[3] ? dataOut1[3] : `IC_DATA_LENGTH'b0);
assign cacheLineData1[0] = cacheLine1[31:0];
assign cacheLineData1[1] = cacheLine1[63:32];
@ -176,10 +154,7 @@ module ICache (
assign cacheLineData1[3] = cacheLine1[127:96];
// Cache Miss
always_ff @(posedge clk) begin
if (rst) cacheMiss <= 1'b0;
else cacheMiss <= ~hit1 & ~wen0;
end
assign cacheMiss = ~hit1 & ~wen0 & req1;
// SRAM
// Lookup + Replace
@ -236,9 +211,9 @@ module ICache (
ffenr #(37) pipelineReg2 (
.clk(clk),
.rst(rst),
.en (AXIBlocker == Idle),
.d ({PC1, hitWay1, cacheMiss}),
.q ({PC2, hitWay2, req2}) // TODO: Req2的逻辑可能有误
.en ((AXIBlocker == Idle) & AXIReq.allowin), // TODO: 这里需要重新设计一下: AXI是否流水
.d({PC1, hitWay1, cacheMiss}),
.q({PC2, hitWay2, req2}) // TODO: Req2的逻辑可能有误
);
// ==============================
@ -246,25 +221,28 @@ module ICache (
// ==============================
assign hit2 = hitWay2[0] | hitWay2[1] | hitWay2[2] | hitWay2[3];
assign AXIReq.readygo = AXIReq.allowin & ~hit2 & req2;
assign AXIReq.readygo = ~hit2 & req2;
assign ICacheAddress = {PC2[31:4], 4'b0};
always_ff @(posedge clk) begin
always_comb begin
casez (AXIBlocker)
Idle: begin
if (req2) nextAXIBlocker <= Wait;
else nextAXIBlocker <= AXIBlocker;
if (req2) nextAXIBlocker = Wait;
else nextAXIBlocker = AXIBlocker;
end
Wait: begin
if (ICacheLineOK) nextAXIBlocker <= Idle;
else nextAXIBlocker <= AXIBlocker;
if (ICacheLineOK) nextAXIBlocker = Idle;
else nextAXIBlocker = AXIBlocker;
end
default: begin
nextAXIBlocker <= AXIBlocker;
nextAXIBlocker = Idle;
end
endcase
end
AXIBlocker <= nextAXIBlocker;
always_ff @(posedge clk) begin
if (rst) AXIBlocker <= Idle;
else AXIBlocker <= nextAXIBlocker;
end
// ==============================

2
src/IP/cache_data_bram/cache_data_bram.xci
View File

@ -244,7 +244,7 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>

2
src/IP/cache_tag_bram/cache_tag_bram.xci
View File

@ -244,7 +244,7 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>

66
src/testbench/tmp.coe Normal file
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@ -0,0 +1,66 @@
memory_initialization_radix=16;
memory_initialization_vector=
00000000,
00000001,
00000002,
00000003,
00000004,
00000005,
00000006,
00000007,
00000008,
00000009,
0000000A,
0000000B,
0000000C,
0000000D,
0000000E,
0000000F,
00000010,
00000011,
00000012,
00000013,
00000014,
00000015,
00000016,
00000017,
00000018,
00000019,
0000001A,
0000001B,
0000001C,
0000001D,
0000001E,
0000001F,
00000020,
00000021,
00000022,
00000023,
00000024,
00000025,
00000026,
00000027,
00000028,
00000029,
0000002A,
0000002B,
0000002C,
0000002D,
0000002E,
0000002F,
00000030,
00000031,
00000032,
00000033,
00000034,
00000035,
00000036,
00000037,
00000038,
00000039,
0000003A,
0000003B,
0000003C,
0000003D,
0000003E,
0000003F;