From d2b4570c9efdab379be99e23ddc5fe80364484a2 Mon Sep 17 00:00:00 2001 From: Paul Pan Date: Mon, 26 Jul 2021 22:29:59 +0800 Subject: [PATCH] controller + prefetch + iq Co-authored-by: Hooo1941 Co-authored-by: cxy004 --- src/Core/Controller.sv | 74 ++++++++--- src/Core/Datapath.sv | 242 +++++++++++++++++++++++++++++------ src/Core/InstrQueue.sv | 121 +++++++++--------- src/include/defines.svh | 45 ++++++- src/testbench/happy/happy.sv | 5 +- tools/ctrl.out.txt | 42 ++++++ tools/ctrl.txt | 58 +++++++++ tools/ctrl_maker.py | 2 +- tools/out1.txt | 19 +++ 9 files changed, 483 insertions(+), 125 deletions(-) create mode 100644 tools/ctrl.out.txt create mode 100644 tools/ctrl.txt create mode 100644 tools/out1.txt diff --git a/src/Core/Controller.sv b/src/Core/Controller.sv index 1e24dbd..ef5f232 100644 --- a/src/Core/Controller.sv +++ b/src/Core/Controller.sv @@ -1,25 +1,59 @@ `include "defines.svh" -module controller( - input word_t instr, - // fetch - output logic [1:0] pcsrc, - // decode - output logic [4:0] rs, rt, rd, - output word_t imm, - // execute - output logic [1:0] alusrca, alusrcb, - output aluctrl_t aluctrl, - // memory - output logic [1:0] size, - output logic lunsigned, memwrite, - // write-back - output logic memtorf, rfwrite, cp0write); +module Controller ( + input word_t inst, + output Ctrl_t ctrl, + output word_t imm, + output logic [4:0] sa +); + mux3 #(5) RD_mux ( + 5'b11111, + inst[15:11], + ctrl.RT, + {inst[31] | inst[29], inst[26]}, + ctrl.RD + ); + + mux3 #(32) imm_mux ( + {{16{inst[15]}}, inst[15:0]}, + {16'b0, inst[15:0]}, + {inst[15:0], 16'b0}, + {inst[28] & inst[27] & inst[26], inst[31] | ~inst[28]}, + imm + ); + + assign sa = inst[10:6]; + + assign ctrl.SYSCALL = ~inst[26] & ~inst[29] & ~inst[30] & ~inst[28] & ~inst[31] & ~inst[27] & inst[2] & inst[3] & ~inst[0]; + assign ctrl.BREAK = ~inst[26] & ~inst[29] & ~inst[30] & ~inst[28] & ~inst[31] & ~inst[27] & inst[2] & inst[3] & inst[0]; + assign ctrl.ERET = inst[30] & inst[25]; + assign ctrl.OFA = ~inst[26] & (~inst[29] & ~inst[30] & ~inst[28] & ~inst[31] & ~inst[27] & inst[5] & ~inst[0] & ~inst[2] & ~inst[3] | inst[29] & ~inst[28] & ~inst[31] & ~inst[27]); + + assign ctrl.RS = inst[25:21]; + assign ctrl.RT = inst[20:16]; + + assign ctrl.PFCtrl.BJJR = ~inst[26] & (~inst[27] & (~inst[28] & ~inst[30] & ~inst[31] & ~inst[29] & inst[3] & ~inst[4] & ~inst[5] & ~inst[2] | inst[28] & ~inst[31] & ~inst[29]) | inst[27] & ~inst[29]) | inst[26] & ~inst[29] & ~inst[31]; + assign ctrl.PFCtrl.BJR = ~inst[26] & (~inst[28] & ~inst[30] & ~inst[29] & ~inst[31] & ~inst[27] & inst[3] & ~inst[4] & ~inst[5] & ~inst[2] | inst[28] & ~inst[29] & ~inst[31]) | inst[26] & ~inst[29] & ~inst[31] & (~inst[27] | inst[27] & inst[28]); + assign ctrl.PFCtrl.BE = inst[28] & ~inst[29] & ~inst[31] & ~inst[27]; + + assign ctrl.DCtrl.DP0 = ~inst[31]; + assign ctrl.DCtrl.DP1 = ~inst[30] & (~inst[26] & (~inst[29] & (~inst[28] & (~inst[31] & (~inst[27] & ~inst[4] | inst[27]) | inst[31]) | inst[28]) | inst[29]) | inst[26]) | inst[30] & inst[25]; + assign ctrl.DCtrl.UI = inst[28] & inst[27] & inst[26]; + assign ctrl.DCtrl.IX = ~inst[28] | inst[28] & inst[31]; + + assign ctrl.ECtrl.OP.alt = ~inst[31] & (~inst[26] & (~inst[27] & ~inst[29] & inst[1] & (~inst[5] & inst[0] | inst[5]) | inst[27]) | inst[26] & inst[27] & inst[29] & ~inst[28]); + + assign ctrl.MCtrl0.HW = ~inst[26] & ~inst[29] & ~inst[30] & ~inst[28] & ~inst[27] & inst[4] & (~inst[3] & ~inst[1] & inst[0] | inst[3]); + assign ctrl.MCtrl0.LW = ~inst[26] & ~inst[29] & ~inst[30] & ~inst[28] & ~inst[27] & inst[4] & (~inst[3] & inst[1] & inst[0] | inst[3]); + assign ctrl.MCtrl0.C0D = inst[15:11]; + assign ctrl.MCtrl0.C0W = inst[30] & inst[23]; + + assign ctrl.MCtrl1.MR = inst[31]; + assign ctrl.MCtrl1.MWR = inst[29]; + assign ctrl.MCtrl1.MX = ~inst[28]; + assign ctrl.MCtrl1.SZ = inst[27:26]; + + assign ctrl.WCtrl.RW = ~inst[30] & (~inst[29] & (~inst[31] & ~inst[28] & (~inst[27] & (~inst[26] & (~inst[3] & (~inst[4] | inst[4] & ~inst[0]) | inst[3] & (~inst[5] & ~inst[4] & ~inst[2] & inst[0] | inst[5])) | inst[26] & inst[20]) | inst[27] & inst[26]) | inst[31]) | inst[29] & ~inst[31]) | inst[30] & ~inst[25] & ~inst[23]; - assign rs = instr[25:21]; - assign rt = instr[20:16]; - mux3#(5) rd_mux(5'b11111, instr[15:11], rt, {instr[31] | instr[29], instr[26]}, rd); - mux3#(32) imm_mux({{16{instr[15]}}, instr[15:0]}, {16'b0, instr[15:0]}, {instr[15:0], 16'b0}, - {instr[28] & instr[27] & instr[26], instr[31] | ~instr[28]}, imm); endmodule diff --git a/src/Core/Datapath.sv b/src/Core/Datapath.sv index 4a5ad69..914d725 100644 --- a/src/Core/Datapath.sv +++ b/src/Core/Datapath.sv @@ -5,8 +5,9 @@ module Datapath ( input clk, input rst, - // MMU D-MEM - sram_i.master mem_i, + // MMU + sramro_i.master fetch_i, + sram_i.master mem_i, // CP0 output logic [4:0] C0_addr, @@ -14,13 +15,48 @@ module Datapath ( output logic C0_we, output word_t C0_wdata, output EXCEPTION_t C0_exception, - input word_t C0_EPC + input word_t C0_EPC, + + // test RF + input logic [4:0] test_addr, + output word_t test_data ); + PF_t PF; + F_t F; + D_t D; E_t E; M_t M; W_t W; + // Pre Fetch + word_t PF_pcp8; + word_t PF_pcb; + word_t PF_pcj; + word_t PF_pcjr; + word_t PF_pc0; + + // Instr Queue + logic IQ_IA_valid; + word_t IQ_IA_inst; + word_t IQ_IA_pc; + + logic IQ_IB_valid; + word_t IQ_IB_inst; + word_t IQ_IB_pc; + + + // Decode + word_t D_IA_ForwardS; + + logic D_IA_valid; + logic D_IB_valid; + + logic D_IA_iv; + logic D_IB_iv; + + + // Execute logic E_go; logic E_I0_go; @@ -95,37 +131,171 @@ module Datapath ( word_t HI; word_t LO; - // Write Back - logic R_we1; - logic R_we2; - logic [4:0] R_waddr1; - logic [4:0] R_waddr2; - word_t R_wdata1; - word_t R_wdata2; + //---------------------------------------------------------------------------// + // Pre Fetch // + //---------------------------------------------------------------------------// + + assign PF_pcp8 = {F.pc[31:3] + 1'b1, 3'b0}; + assign PF_pcb = {D.IB_pc[31:2] + {{14{D.IA_inst[15]}}, D.IA_inst[15:0]}, 2'b0}; + assign PF_pcj = {D.IB_pc[31:28], D.IA_inst[25:0], 2'b0}; + assign PF_pcjr = D_IA_ForwardS; + mux4 #(32) PF_pc0_mux ( + PF_pcp8, + PF_pcb, + PF_pcj, + PF_pcjr, + D.IA.PCS, + PF_pc0 + ); + prio_mux4 #(32) PF_pc_mux ( + PF_pc0, + C0_EPC, + `PCEXC, + `PCRST, + {rst, C0_exception.ExcValid, C0_exception.ERET}, + PF.pc + ); + + // assign excPF = PF.pc[1:0] != 2'b00; + + // assign fetch_i.req = F.en & ~excPF; + assign fetch_i.addr = PF.pc; + + //---------------------------------------------------------------------------// + // Fetch Stage // + //---------------------------------------------------------------------------// + + // F.FF + ffenr #(32) F_pc_ff ( + clk, + rst, + PF.pc, + F.en, + F.pc + ); + + // assign F.en = fetch_i.data_ok; + + //---------------------------------------------------------------------------// + // Instr Queue // + //---------------------------------------------------------------------------// + + InstrQueue InstrQueue ( + .clk(clk), + .rst(rst), + + .vinA(fetch_i.data_ok), + .inA (F.pc[2] ? fetch_i.rdata1 : fetch_i.rdata0), + .pinA(F.pc), + + .vinB(fetch_i.data_ok & ~F.pc[2]), + .inB (fetch_i.rdata1), + .pinB({F.pc[31:3], 1'b1, F.pc[1:0]}), + + .enA (D.en0), + .voutA(IQ_IA_valid), + .outA (IQ_IA_inst), + .poutA(IQ_IA_pc), + + .enB (D.en1), + .voutB(IQ_IB_valid), + .outB (IQ_IB_inst), + .poutB(IQ_IB_pc), + + .valids(), + .clear (IQ_clear) + ); //---------------------------------------------------------------------------// // Decode Stage // //---------------------------------------------------------------------------// - RF RegisterFile( - .clk(clk), - .raddr1(R_raddr1), - .raddr2(R_raddr2), - .raddr3(R_raddr3), - .raddr4(R_raddr4), - .we1(R_we1), - .we2(R_we2), - .waddr1(R_waddr1), - .waddr2(R_waddr2), - .wdata1(R_wdata1), - .wdata2(R_wdata2), - .rdata1(R_rdata1), - .rdata2(R_rdata2), - .rdata3(R_rdata3), - .rdata4(R_rdata4), - .test_addr(R_test_addr), - .test_data(R_test_data) + // D.FF + + // IQ_IA -> D_IA IQ_IB -> D_IB en0 = 1 en1 = 1 + // D_IB -> D_IA IQ_IA -> D_IB en0 = 1 en1 = 0 + + ffenr #(1 + 32 + 32) D_IA_ff ( + clk, + rst, + D.en1 ? {IQ_IA_valid, IQ_IA_pc, IQ_IA_inst} : {D_IB_valid, D.IB_pc, D.IB_inst}, + D.en0, + {D_IA_valid, D.IA_pc, D.IA_instr} ); + ffenr #(1 + 32 + 32) D_IB_ff ( + clk, + rst, + D.en1 ? {IQ_IB_valid, IQ_IB_pc, IQ_IB_inst} : {IQ_IA_valid, IQ_IA_pc, IQ_IA_inst}, + D.en0, + {D_IB_valid, D.IB_pc, D.IB_inst} + ); + + // Register File + + RF RegisterFile ( + .clk(clk), + .raddr1(D.IA.RS), + .raddr2(D.IA.RT), + .raddr3(D.IB.RS), + .raddr4(D.IB.RT), + .we1(W.I0.WCtrl.RW), + .we2(W.I1.WCtrl.RW), + .waddr1(W.I0.RD), + .waddr2(W.I1.RD), + .wdata1(W.I0.RDataW), + .wdata2(W.I1.RDataW), + .rdata1(D.IA_S), + .rdata2(D.IA_T), + .rdata3(D.IB_S), + .rdata4(D.IB_T), + .test_addr(test_addr), + .test_data(test_data) + ); + + // D.Decode + + Controller D_IA_ctrl ( + D.IA_inst, + D.IA, + D.IA_imm, + D.IA_sa + ); + Controller D_IB_ctrl ( + D.IB_inst, + D.IB, + D.IB_imm, + D.IB_sa + ); + + + + + // D.Exc + + instr_valid D_IA_instr_valid ( + D.IA_inst, + D_IA_iv + ); + instr_valid D_IB_instr_valid ( + D.IB_inst, + D_IB_iv + ); + + assign D.IA_ExcValid = D_IA_valid & (ERET | SYSCALL | BREAK | D.IA_pc[1:0] != 2'b00 | ~D_IA_iv); + assign D.IA_ExcCode = D.IA_pc[1:0] != 2'b00 ? `EXCCODE_ADDRR : `EXCCODE_RI; + assign D.IA_Delay = 1'b0; + + assign D.IB_ExcValid = D_IB_valid & (ERET | SYSCALL | BREAK | D.IB_pc[1:0] != 2'b00 | ~D_IB_iv); + assign D.IB_ExcCode = D.IB_pc[1:0] != 2'b00 ? `EXCCODE_ADDRR : `EXCCODE_RI; + assign D.IB_Delay = (D_IB_DELAY); + + // D.Dispatch + + + + // D.BJJR + + //---------------------------------------------------------------------------// // Execute Stage // @@ -486,7 +656,8 @@ module Datapath ( (~M_I0_FS_W_I0 | M_I0_FS_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW, M.I1.ALUOut, {M_I0_FS_M_I1, M_I0_FS_W_I0 | M_I0_FS_W_I1}, - M_I0_ForwardS); + M_I0_ForwardS + ); assign M_I0_FT_M_I1 = M.A & M.I1.WCtrl.RW & M.I0.RT == M.I1.RD & ~M.I1.MCtrl.MR; assign M_I0_FT_W_I0 = W.I0.WCtrl.RW & M.I0.RT == W.I0.RD; @@ -496,7 +667,8 @@ module Datapath ( (~M_I0_FT_W_I0 | M_I0_FT_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW, M.I1.ALUOut, {M_I0_FT_M_I1, M_I0_FT_W_I0 | M_I0_FT_W_I1}, - M_I0_ForwardT); + M_I0_ForwardT + ); assign M_I1_FT_M_I0 = ~M.A & M.I0.WCtrl.RW & M.I1.RT == M.I0.RD; assign M_I1_FT_W_I0 = W.I0.WCtrl.RW & M.I1.RT == W.I0.RD; @@ -506,7 +678,8 @@ module Datapath ( (~M_I1_FT_W_I0 | M_I1_FT_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW, M.I0.RDataW, {M_I1_FT_M_I0, M_I1_FT_W_I0 | M_I1_FT_W_I1}, - M_I1_ForwardT); + M_I1_ForwardT + ); //----------------------------------------------------------------------------// // Write-Back Stage // @@ -550,11 +723,4 @@ module Datapath ( assign W.en = 1'b1; - assign R_we1 = W.I0.WCtrl.RW; - assign R_we2 = W.I1.WCtrl.RW; - assign R_waddr1 = W.I0.RD; - assign R_waddr2 = W.I1.RD; - assign R_wdata1 = W.I0.RDataW; - assign R_wdata2 = W.I1.RDataW; - endmodule diff --git a/src/Core/InstrQueue.sv b/src/Core/InstrQueue.sv index 93ebe7b..68ae4cf 100644 --- a/src/Core/InstrQueue.sv +++ b/src/Core/InstrQueue.sv @@ -2,21 +2,26 @@ module InstrQueue ( input logic clk, input logic rst, - // HandShake.prev HandShake_in1, - input logic vin1, - input logic vin2, + + input logic vinA, + input word_t inA, + input word_t pinA, + + input logic vinB, + input word_t inB, + input word_t pinB, + + input logic enA, + output logic voutA, + output word_t outA, + output word_t poutA, + + input logic enB, + output logic voutB, + output word_t outB, + output word_t poutB, + output logic [3:0] valids, - input word_t in1, - input word_t pin1, - // HandShake.prev HandShake_in2, - input word_t in2, - input word_t pin2, - HandShake.next HandShake_out1, - output word_t out1, - output word_t pout1, - HandShake.next HandShake_out2, - output word_t out2, - output word_t pout2, input logic clear ); @@ -25,46 +30,46 @@ instr: ffen valid: ffenr readygo to valid 0: -0out: instr1<-in1, instr2<-in2 -1out: out1<-in1, instr1<-in2 -2out: out1<-in1, out2<-in2 +0out: instr1<-inA, instr2<-inB +1out: outA<-inA, instr1<-inB +2out: outA<-inA, outB<-inB 1: -0out: instr2<-in1, instr3<-in2 -1out: out1<-instr1 instr1<-in1 instr2<-in2 -2out: out1<-instr1 out2<-in1 instr1<-in2 +0out: instr2<-inA, instr3<-inB +1out: outA<-instr1 instr1<-inA instr2<-inB +2out: outA<-instr1 outB<-inA instr1<-inB 2: -0out: instr4<-in1 -1out: out1<-instr1 instr1<-instr2 instr2<-in1 instr3<-in2 -2out: out1<-instr1 out2<-instr2 instr1<-in1 instr2<-in2 +0out: instr4<-inA +1out: outA<-instr1 instr1<-instr2 instr2<-inA instr3<-inB +2out: outA<-instr1 outB<-instr2 instr1<-inA instr2<-inB 3: -1out: out1<-instr1 instr1<-instr2 instr2<-in1 instr3<-in2 -2out: out1<-instr1 out2<-instr2 instr1<-instr3 instr2<-in1 instr3<-in2 +1out: outA<-instr1 instr1<-instr2 instr2<-inA instr3<-inB +2out: outA<-instr1 outB<-instr2 instr1<-instr3 instr2<-inA instr3<-inB 4: 0out: -1out: out1<-instr1 instr1<-instr2 instr2<-instr3 instr3<-in1 -2out: out1<-instr1 out2<-instr2 instr1<-instr3 instr3<-instr4 instr4<-in1 +1out: outA<-instr1 instr1<-instr2 instr2<-instr3 instr3<-inA +2out: outA<-instr1 outB<-instr2 instr1<-instr3 instr3<-instr4 instr4<-inA 无直通 0: -0out: instr1<-in1, instr2<-in2 -1out: instr1<-in1, instr2<-in2 -2out: instr1<-in1, instr2<-in2 +0out: instr1<-inA, instr2<-inB +1out: instr1<-inA, instr2<-inB +2out: instr1<-inA, instr2<-inB 1: -0out: instr2<-in1, instr3<-in2 -1out: out1<-instr1 instr1<-in1 instr2<-in2 -2out: out1<-instr1 instr1<-in1 instr2<-in2 +0out: instr2<-inA, instr3<-inB +1out: outA<-instr1 instr1<-inA instr2<-inB +2out: outA<-instr1 instr1<-inA instr2<-inB 2: -0out: instr3<-in1 instr4<-in2 -1out: out1<-instr1 instr1<-instr2 instr2<-in1 instr3<-in2 -2out: out1<-instr1 out2<-instr2 instr1<-in1 instr2<-in2 +0out: instr3<-inA instr4<-inB +1out: outA<-instr1 instr1<-instr2 instr2<-inA instr3<-inB +2out: outA<-instr1 outB<-instr2 instr1<-inA instr2<-inB 3: -0out: instr4<-in1 -1out: out1<-instr1 instr1<-instr2 instr2<-instr3 instr3<-in1 instr4<-in2 -2out: out1<-instr1 out2<-instr2 instr1<-instr3 instr2<-in1 instr3<-in2 +0out: instr4<-inA +1out: outA<-instr1 instr1<-instr2 instr2<-instr3 instr3<-inA instr4<-inB +2out: outA<-instr1 outB<-instr2 instr1<-instr3 instr2<-inA instr3<-inB 4: 0out: nop -1out: out1<-instr1 instr1<-instr2 instr2<-instr3 instr3<-instr4 instr4<-in1 -2out: out1<-instr1 out2<-instr2 instr1<-instr3 instr2<-instr4 instr3<-in1 instr4<-in2 +1out: outA<-instr1 instr1<-instr2 instr2<-instr3 instr3<-instr4 instr4<-inA +2out: outA<-instr1 outB<-instr2 instr1<-instr3 instr2<-instr4 instr3<-inA instr4<-inB */ word_t di1, di2, di3, di4, qi1, qi2, qi3, qi4; @@ -72,7 +77,7 @@ readygo to valid logic en1, en2, en3, en4; word_t dp1, dp2, dp3, dp4, qp1, qp2, qp3, qp4; logic [5:0] judge; - assign judge = {qv4, qv3, qv2, qv1, HandShake_out1.allowin, HandShake_out2.allowin}; + assign judge = {qv4, qv3, qv2, qv1, enA, enB}; assign valids = {qv4, qv3, qv2, qv1}; assign en1 = ~judge[2] | judge[1]; assign en2 = ~judge[3] | judge[1]; @@ -82,35 +87,35 @@ readygo to valid // 11 >= 4 // 10 == 3 // others:00 - // {HandShake_in1, HandShake_in2} - // assign HandShake_in1.allowin = (~judge[4] & (~judge[3] | judge[1]) | judge[4] & judge[0] & ~judge[5]); - // assign HandShake_in2.allowin = (~judge[3] & (~judge[2] | judge[1]) | judge[3] & ~judge[4] & judge[0]); - // assign HandShake_in1.allowin = ~judge[5] | judge[1]; - // assign HandShake_in2.allowin = (~judge[4] | judge[1] & (~judge[5] | judge[0])); + // {HandShake_inA, HandShake_inB} + // assign HandShake_inA.allowin = (~judge[4] & (~judge[3] | judge[1]) | judge[4] & judge[0] & ~judge[5]); + // assign HandShake_inB.allowin = (~judge[3] & (~judge[2] | judge[1]) | judge[3] & ~judge[4] & judge[0]); + // assign HandShake_inA.allowin = ~judge[5] | judge[1]; + // assign HandShake_inB.allowin = (~judge[4] | judge[1] & (~judge[5] | judge[0])); - assign {out1, out2, pout1, pout2} = {qi1, qi2, qp1, qp2}; - assign HandShake_out1.readygo = judge[2]; - assign HandShake_out2.readygo = judge[3]; + assign {outA, outB, poutA, poutB} = {qi1, qi2, qp1, qp2}; + assign voutA = judge[2]; + assign voutB = judge[3]; always_comb begin if (judge[3] & ~judge[0]) {di1, dv1, dp1} = {qi2, qv2, qp2}; else if (judge[3] & judge[0] & judge[4]) {di1, dv1, dp1} = {qi3, qv3, qp3}; - else {di1, dv1, dp1} = {in1, vin1, pin1}; + else {di1, dv1, dp1} = {inA, vinA, pinA}; if (judge[4] & ~judge[0]) {di2, dv2, dp2} = {qi3, qv3, qp3}; else if (judge[4] & judge[0] & judge[5]) {di2, dv2, dp2} = {qi4, qv4, qp4}; else if (~judge[4] & (~judge[2] | (~judge[3] & judge[1] | judge[0]))) - {di2, dv2, dp2} = {in2, vin2, pin2}; - else {di2, dv2, dp2} = {in1, vin1, pin1}; + {di2, dv2, dp2} = {inB, vinB, pinB}; + else {di2, dv2, dp2} = {inA, vinA, pinA}; if (judge[5] & ~judge[0]) {di3, dv3, dp3} = {qi4, qv4, qp4}; else if ((~judge[5] & judge[3] & ~judge[0] & (~judge[4] & ~judge[1] | judge[4]) | judge[5] & judge[0])) - {di3, dv3, dp3} = {in1, vin1, pin1}; - else {di3, dv3, dp3} = {in2, vin1, pin2}; + {di3, dv3, dp3} = {inA, vinA, pinA}; + else {di3, dv3, dp3} = {inB, vinA, pinB}; - di4 = (judge[4] & ~judge[0] & (~judge[1] | judge[5])) ? in1 : in2; - dv4 = ((judge[4] & ~judge[0] & (~judge[1] | judge[5])) ? vin1 : vin2); - dp4 = (judge[4] & ~judge[0] & (~judge[1] | judge[5])) ? pin1 : pin2; + di4 = (judge[4] & ~judge[0] & (~judge[1] | judge[5])) ? inA : inB; + dv4 = ((judge[4] & ~judge[0] & (~judge[1] | judge[5])) ? vinA : vinB); + dp4 = (judge[4] & ~judge[0] & (~judge[1] | judge[5])) ? pinA : pinB; end ffen #(32) pc1 ( clk, diff --git a/src/include/defines.svh b/src/include/defines.svh index 49ae21c..a7d5534 100644 --- a/src/include/defines.svh +++ b/src/include/defines.svh @@ -129,16 +129,13 @@ typedef struct packed { typedef struct packed {logic RW;} WCtrl_t; typedef struct packed { - logic ExcValid; - logic ERET; - logic [4:0] ExcCode; - logic Delay; - logic OFA; + logic SYSCALL; + logic BREAK; + logic ERET; + logic OFA; logic [4:0] RS; logic [4:0] RT; - word_t S; - word_t T; PFCtrl_t PFCtrl; @@ -153,6 +150,40 @@ typedef struct packed { WCtrl_t WCtrl; } Ctrl_t; +typedef struct packed {word_t pc;} PF_t; + +typedef struct packed { + logic en; + word_t pc; +} F_t; + +typedef struct packed { + logic en0, en1; + Ctrl_t IA, IB; + + word_t IA_pc; + word_t IA_inst; + logic IA_ExcValid; + logic IA_ERET; + logic [4:0] IA_ExcCode; + logic IA_Delay; + word_t IA_S; + word_t IA_T; + word_t IA_imm; + logic [4:0] IA_sa; + + word_t IB_pc; + word_t IB_inst; + logic IB_ExcValid; + logic IB_ERET; + logic [4:0] IB_ExcCode; + logic IB_Delay; + word_t IB_S; + word_t IB_T; + word_t IB_imm; + logic [4:0] IB_sa; +} D_t; + typedef struct packed { logic en; logic A; diff --git a/src/testbench/happy/happy.sv b/src/testbench/happy/happy.sv index c5f9ae9..a750d64 100644 --- a/src/testbench/happy/happy.sv +++ b/src/testbench/happy/happy.sv @@ -192,6 +192,9 @@ module happy (); .pout2(pout2) ); - Datapath dp (.mem_i(data.master)); + Datapath dp ( + .fetch_i(inst.master), + .mem_i (data.master) + ); endmodule diff --git a/tools/ctrl.out.txt b/tools/ctrl.out.txt new file mode 100644 index 0000000..b3b92d0 --- /dev/null +++ b/tools/ctrl.out.txt @@ -0,0 +1,42 @@ +ctrl.ERET = inst[30] & inst[25] +ctrl.SYSCALL = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[3] & inst[2] & ~inst[0] +ctrl.BREAK = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[3] & inst[2] & inst[0] + +ctrl.PFCtrl.BJJR = ~inst[26] & (~inst[27] & (~inst[28] & ~inst[30] & ~inst[31] & ~inst[29] & inst[3] & ~inst[4] & ~inst[5] & ~inst[2] | inst[28] & ~inst[31] & ~inst[29]) | inst[27] & ~inst[29]) | inst[26] & ~inst[29] & ~inst[31] +ctrl.PFCtrl.BJR = (~inst[26] & (~inst[28] & ~inst[30] & ~inst[29] & ~inst[31] & ~inst[27] & inst[3] & ~inst[4] & ~inst[5] & ~inst[2] | inst[28] & ~inst[29] & ~inst[31]) | inst[26] & ~inst[29] & ~inst[31] & (~inst[27] | inst[28])) +ctrl.PFCtrl.BE = ~inst[31] & ~inst[29] & inst[28] & ~inst[27] + +ctrl.DCtrl.DP0 = ~inst[31] +ctrl.DCtrl.DP1 = ~inst[30] & (~inst[26] & (~inst[29] & (~inst[28] & (~inst[31] & (~inst[27] & ~inst[4] | inst[27]) | inst[31]) | inst[28]) | inst[29]) | inst[26]) | inst[30] & inst[25] +ctrl.DCtrl.UI = inst[28] & inst[29] & inst[27] & inst[26] +ctrl.DCtrl.IX = ~inst[28] + +ctrl.ECtrl.SA +{'SA': '~inst[31] & ~inst[29] & ~inst[26] & ~inst[30] & ~inst[28] & ~inst[27] & ~inst[5] & ~inst[4] & ~inst[3] & ~inst[2]', 'RS': '(~inst[31] & (~inst[29] & ~inst[26] & ~inst[30] & ~inst[28] & ~inst[27] & (~inst[5] & (~inst[4] & ~inst[3] & inst[2] | inst[4] & inst[3]) | inst[5]) | inst[29] & (~inst[28] | inst[28] & (~inst[27] | inst[27] & ~inst[26]))) | inst[31])' + +ctrl.ECtrl.SB +{'RT': '~inst[29] & ~inst[31] & ~inst[26] & ~inst[30] & ~inst[28] & ~inst[27] & (~inst[5] & (~inst[1] & (~inst[0] & (~inst[3] & ~inst[4] | inst[3] & inst[4]) | inst[0] & inst[4] & inst[3]) | inst[1] & (~inst[4] | inst[4] & inst[3])) | inst[5])', '8': '~inst[29] & ~inst[31] & (~inst[26] & (~inst[30] & (~inst[28] & (~inst[27] & ~inst[5] & (~inst[1] & (~inst[0] & (~inst[3] & inst[4] | inst[3] & ~inst[4]) | inst[0] & (~inst[4] | inst[4] & ~inst[3])) | inst[1] & inst[4] & ~inst[3]) | inst[27]) | inst[28]) | inst[30]) | inst[26])', 'IMM': '(~inst[29] & inst[31] | inst[29])'} + +ctrl.ECtrl.OP[8:1] +{'SR': '~inst[31] & ~inst[26] & ~inst[28] & ~inst[27] & ~inst[30] & ~inst[29] & ~inst[5] & ~inst[3] & (~inst[1] & ~inst[2] | inst[1])', 'SL': '~inst[31] & ~inst[26] & ~inst[28] & ~inst[27] & ~inst[30] & ~inst[29] & ~inst[5] & ~inst[3] & ~inst[1] & inst[2]', 'ADD': '(~inst[31] & (~inst[26] & ~inst[28] & ~inst[27] & (~inst[30] & (~inst[29] & (~inst[5] & inst[3] | inst[5] & ~inst[2] & ~inst[3]) | inst[29]) | inst[30]) | inst[26] & (~inst[29] | inst[29] & (~inst[28] & ~inst[27] | inst[28] & inst[27]))) | inst[31])', 'SLT': '~inst[31] & ~inst[26] & ~inst[28] & (~inst[27] & ~inst[30] & ~inst[29] & inst[5] & ~inst[2] & inst[3] & ~inst[0] | inst[27])', 'SLTU': '~inst[31] & (~inst[26] & ~inst[28] & ~inst[27] & ~inst[30] & ~inst[29] & inst[5] & ~inst[2] & inst[3] & inst[0] | inst[26] & inst[29] & ~inst[28] & inst[27])', 'AND': '~inst[31] & ~inst[26] & (~inst[28] & ~inst[27] & ~inst[30] & ~inst[29] & inst[5] & inst[2] & ~inst[0] & ~inst[1] | inst[28] & ~inst[27])', 'XOR': '~inst[31] & ~inst[26] & (~inst[28] & ~inst[27] & ~inst[30] & ~inst[29] & inst[5] & inst[2] & ~inst[0] & inst[1] | inst[28] & inst[27])', 'OR': '~inst[31] & (~inst[26] & ~inst[28] & ~inst[27] & ~inst[30] & ~inst[29] & inst[5] & inst[2] & inst[0] | inst[26] & inst[29] & inst[28] & ~inst[27])'} + +ctrl.ECtrl.OP[0] = ~inst[31] & (~inst[26] & ~inst[30] & (~inst[27] & ~inst[29] & inst[1] & (~inst[5] & inst[0] | inst[5]) | inst[27]) | inst[26] & inst[27] & inst[29] & ~inst[28])' +ctrl.OFA = ~inst[26] & (~inst[29] & ~inst[30] & ~inst[28] & ~inst[31] & ~inst[27] & inst[5] & ~inst[0] & ~inst[2] & ~inst[3] | inst[29] & ~inst[28] & ~inst[31] & ~inst[27])' +ctrl.MCtrl1.MR = inst[31] +ctrl.MCtrl1.MWR = inst[29] +ctrl.MCtrl1.MX = ~inst[28] + +RD +{'RD': '~inst[29] & ~inst[31] & ~inst[26]', '31': '~inst[29] & ~inst[31] & inst[26]', 'RT': '(~inst[29] & inst[31] | inst[29])'} + +ctrl.WCtrl.RW = (~inst[30] & (~inst[29] & (~inst[31] & ~inst[28] & (~inst[27] & (~inst[26] & (~inst[3] & (~inst[4] | inst[4] & ~inst[0]) | inst[3] & (~inst[5] & ~inst[4] & ~inst[2] & inst[0] | inst[5])) | inst[26] & inst[20]) | inst[27] & inst[26]) | inst[31]) | inst[29] & ~inst[31]) | inst[30] & ~inst[25] & ~inst[23]) + +ctrl.MCtrl0.RS0 +{'ALUOut': '~inst[30] & (~inst[29] & (~inst[26] & ~inst[4] | inst[26]) | inst[29])', 'HI': '~inst[30] & ~inst[29] & ~inst[26] & inst[4] & ~inst[1]', 'LO': '~inst[30] & ~inst[29] & ~inst[26] & inst[4] & inst[1]', 'C0': 'inst[30]'} + +ctrl.MCtrl0.HW = ~inst[26] & ~inst[29] & ~inst[30] & ~inst[28] & ~inst[27] & inst[4] & (~inst[3] & ~inst[1] & inst[0] | inst[3]) +ctrl.MCtrl0.LW = ~inst[26] & ~inst[29] & ~inst[30] & ~inst[28] & ~inst[27] & inst[4] & (~inst[3] & inst[1] & inst[0] | inst[3])' +ctrl.MCtrl0.C0W = inst[30] & inst[23] + +ctrl.MCtrl0.HLS +{'RS': '~inst[3]', 'MULT': 'inst[3] & ~inst[1] & ~inst[0]', 'MULTU': 'inst[3] & ~inst[1] & inst[0]', 'DIV': 'inst[3] & inst[1] & ~inst[0]', 'DIVU': 'inst[3] & inst[1] & inst[0]'} diff --git a/tools/ctrl.txt b/tools/ctrl.txt new file mode 100644 index 0000000..c070a06 --- /dev/null +++ b/tools/ctrl.txt @@ -0,0 +1,58 @@ +////-------------------------------- ERET SYSCALL BREAK PCS BJJR BJR BE DP0 DP1 UI IX SA SB OP ALT OFA MR MWR MX RD RW RS0 HW LW C0W HLS +32'b00000000000???????????????000000 0 0 0 ? 0 0 0 1 1 ? ? SA RT SR 0 0 0 ? ? RD 1 ALUOut 0 0 0 ? +32'b00000000000???????????????000010 0 0 0 ? 0 0 0 1 1 ? ? SA RT SR 0 0 0 ? ? RD 1 ALUOut 0 0 0 ? +32'b00000000000???????????????000011 0 0 0 ? 0 0 0 1 1 ? ? SA RT SR 1 0 0 ? ? RD 1 ALUOut 0 0 0 ? +32'b000000???????????????00000000100 0 0 0 ? 0 0 0 1 1 ? ? RS RT SL ? 0 0 ? ? RD 1 ALUOut 0 0 0 ? +32'b000000???????????????00000000110 0 0 0 ? 0 0 0 1 1 ? ? RS RT SR 0 0 0 ? ? RD 1 ALUOut 0 0 0 ? +32'b000000???????????????00000000111 0 0 0 ? 0 0 0 1 1 ? ? RS RT SR 1 0 0 ? ? RD 1 ALUOut 0 0 0 ? +32'b000000?????000000000000000001000 0 0 0 JR 1 1 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ? +32'b000000?????00000?????00000001001 0 0 0 JR 1 1 0 1 1 ? ? PC 8 ADD 0 0 0 ? ? RD 1 ALUOut 0 0 0 ? +32'b000000????????????????????001100 0 1 0 ? 0 0 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ? +32'b000000????????????????????001101 0 0 1 ? 0 0 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ? +32'b0000000000000000?????00000010000 0 0 0 ? 0 0 0 1 0 ? ? PC 8 ? ? 0 ? ? ? RD 1 HI 0 0 0 ? +32'b000000?????000000000000000010001 0 0 0 ? 0 0 0 1 0 ? ? PC 8 ? ? 0 ? ? ? ? 0 ? 1 0 0 RS +32'b0000000000000000?????00000010010 0 0 0 ? 0 0 0 1 0 ? ? PC 8 ? ? 0 ? ? ? RD 1 LO 0 0 0 ? +32'b000000?????000000000000000010011 0 0 0 ? 0 0 0 1 0 ? ? PC 8 ? ? 0 ? ? ? ? 0 ? 0 1 0 RS +32'b000000??????????0000000000011000 0 0 0 ? 0 0 0 1 0 ? ? RS RT ? ? 0 ? ? ? ? 0 ? 1 1 0 MULT +32'b000000??????????0000000000011001 0 0 0 ? 0 0 0 1 0 ? ? RS RT ? ? 0 ? ? ? ? 0 ? 1 1 0 MULTU +32'b000000??????????0000000000011010 0 0 0 ? 0 0 0 1 0 ? ? RS RT ? ? 0 ? ? ? ? 0 ? 1 1 0 DIV +32'b000000??????????0000000000011011 0 0 0 ? 0 0 0 1 0 ? ? RS RT ? ? 0 ? ? ? ? 0 ? 1 1 0 DIVU +32'b000000???????????????00000100000 0 0 0 ? 0 0 0 1 1 ? ? RS RT ADD 0 1 0 ? ? RD 1 ALUOut 0 0 0 ? +32'b000000???????????????00000100001 0 0 0 ? 0 0 0 1 1 ? ? RS RT ADD 0 0 0 ? ? RD 1 ALUOut 0 0 0 ? +32'b000000???????????????00000100010 0 0 0 ? 0 0 0 1 1 ? ? RS RT ADD 1 1 0 ? ? RD 1 ALUOut 0 0 0 ? +32'b000000???????????????00000100011 0 0 0 ? 0 0 0 1 1 ? ? RS RT ADD 1 0 0 ? ? RD 1 ALUOut 0 0 0 ? +32'b000000???????????????00000100100 0 0 0 ? 0 0 0 1 1 ? ? RS RT AND ? 0 0 ? ? RD 1 ALUOut 0 0 0 ? +32'b000000???????????????00000100101 0 0 0 ? 0 0 0 1 1 ? ? RS RT OR 0 0 0 ? ? RD 1 ALUOut 0 0 0 ? +32'b000000???????????????00000100110 0 0 0 ? 0 0 0 1 1 ? ? RS RT XOR ? 0 0 ? ? RD 1 ALUOut 0 0 0 ? +32'b000000???????????????00000100111 0 0 0 ? 0 0 0 1 1 ? ? RS RT OR 1 0 0 ? ? RD 1 ALUOut 0 0 0 ? +32'b000000???????????????00000101010 0 0 0 ? 0 0 0 1 1 ? ? RS RT SLT 1 0 0 ? ? RD 1 ALUOut 0 0 0 ? +32'b000000???????????????00000101011 0 0 0 ? 0 0 0 1 1 ? ? RS RT SLTU 1 0 0 ? ? RD 1 ALUOut 0 0 0 ? +32'b000001?????00000???????????????? 0 0 0 B 1 1 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ? +32'b000001?????10000???????????????? 0 0 0 B 1 1 0 1 1 ? ? PC 8 ADD 0 0 0 ? ? 31 1 ALUOut 0 0 0 ? +32'b000001?????00001???????????????? 0 0 0 B 1 1 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ? +32'b000001?????10001???????????????? 0 0 0 B 1 1 0 1 1 ? ? PC 8 ADD 0 0 0 ? ? 31 1 ALUOut 0 0 0 ? +32'b000010?????????????????????????? 0 0 0 J 1 0 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ? +32'b000011?????????????????????????? 0 0 0 J 1 0 0 1 1 ? ? PC 8 ADD 0 0 0 ? ? 31 1 ALUOut 0 0 0 ? +32'b000100?????????????????????????? 0 0 0 B 1 1 1 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ? +32'b000101?????????????????????????? 0 0 0 B 1 1 1 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ? +32'b000110?????00000???????????????? 0 0 0 B 1 1 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ? +32'b000111?????00000???????????????? 0 0 0 B 1 1 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ? +32'b001000?????????????????????????? 0 0 0 ? 0 0 0 1 1 0 1 RS IMM ADD 0 1 0 ? ? RT 1 ALUOut 0 0 0 ? +32'b001001?????????????????????????? 0 0 0 ? 0 0 0 1 1 0 1 RS IMM ADD 0 0 0 ? ? RT 1 ALUOut 0 0 0 ? +32'b001010?????????????????????????? 0 0 0 ? 0 0 0 1 1 0 1 RS IMM SLT 1 0 0 ? ? RT 1 ALUOut 0 0 0 ? +32'b001011?????????????????????????? 0 0 0 ? 0 0 0 1 1 0 1 RS IMM SLTU 1 0 0 ? ? RT 1 ALUOut 0 0 0 ? +32'b001100?????????????????????????? 0 0 0 ? 0 0 0 1 1 0 0 RS IMM AND ? 0 0 ? ? RT 1 ALUOut 0 0 0 ? +32'b001101?????????????????????????? 0 0 0 ? 0 0 0 1 1 0 0 RS IMM OR 0 0 0 ? ? RT 1 ALUOut 0 0 0 ? +32'b001110?????????????????????????? 0 0 0 ? 0 0 0 1 1 0 0 RS IMM XOR ? 0 0 ? ? RT 1 ALUOut 0 0 0 ? +32'b00111100000????????????????????? 0 0 0 ? 0 0 0 1 1 1 ? 0 IMM ADD 0 0 0 ? ? RT 1 ALUOut 0 0 0 ? +32'b01000000000??????????00000000??? 0 0 0 ? 0 0 0 1 0 ? ? 0 IMM ? ? 0 ? ? ? RD 1 C0 0 0 0 ? +32'b01000000100??????????00000000??? 0 0 0 ? 0 0 0 1 0 ? ? 0 IMM ? ? 0 ? ? ? ? 0 ? 0 0 1 ? +32'b01000010000000000000000000011000 1 0 0 ? 0 0 0 1 1 ? ? 0 IMM ? ? 0 0 ? ? ? 0 ? 0 0 0 ? +32'b100000?????????????????????????? 0 0 0 ? 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 0 1 RT 1 ? ? ? ? ? +32'b100001?????????????????????????? 0 0 0 ? 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 0 1 RT 1 ? ? ? ? ? +32'b100011?????????????????????????? 0 0 0 ? 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 0 ? RT 1 ? ? ? ? ? +32'b100100?????????????????????????? 0 0 0 ? 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 0 0 RT 1 ? ? ? ? ? +32'b100101?????????????????????????? 0 0 0 ? 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 0 0 RT 1 ? ? ? ? ? +32'b101000?????????????????????????? 0 0 0 ? 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 1 ? ? 0 ? ? ? ? ? +32'b101001?????????????????????????? 0 0 0 ? 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 1 ? ? 0 ? ? ? ? ? +32'b101011?????????????????????????? 0 0 0 ? 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 1 ? ? 0 ? ? ? ? ? diff --git a/tools/ctrl_maker.py b/tools/ctrl_maker.py index f931bfb..ca0054e 100644 --- a/tools/ctrl_maker.py +++ b/tools/ctrl_maker.py @@ -1,4 +1,4 @@ -with open('instrqueue.sv') as f: +with open('ctrl.txt') as f: lines = f.readlines() title = lines[0].split() items = [x.split() for x in lines[1:]] diff --git a/tools/out1.txt b/tools/out1.txt new file mode 100644 index 0000000..ee35205 --- /dev/null +++ b/tools/out1.txt @@ -0,0 +1,19 @@ +assign ctrl.ERET = inst[30] & inst[25]; +assign ctrl.SYSCALL = ~inst[26] & ~inst[29] & ~inst[30] & ~inst[28] & ~inst[31] & ~inst[27] & inst[2] & inst[3] & ~inst[0]; +assign ctrl.BREAK = ~inst[26] & ~inst[29] & ~inst[30] & ~inst[28] & ~inst[31] & ~inst[27] & inst[2] & inst[3] & inst[0]; +assign ctrl.PFCtrl.BJJR = ~inst[26] & (~inst[27] & (~inst[28] & ~inst[30] & ~inst[31] & ~inst[29] & inst[3] & ~inst[4] & ~inst[5] & ~inst[2] | inst[28] & ~inst[31] & ~inst[29]) | inst[27] & ~inst[29]) | inst[26] & ~inst[29] & ~inst[31]; +assign ctrl.PFCtrl.BJR = ~inst[26] & (~inst[28] & ~inst[30] & ~inst[29] & ~inst[31] & ~inst[27] & inst[3] & ~inst[4] & ~inst[5] & ~inst[2] | inst[28] & ~inst[29] & ~inst[31]) | inst[26] & ~inst[29] & ~inst[31] & (~inst[27] | inst[27] & inst[28]); +assign ctrl.PFCtrl.BE = inst[28] & ~inst[29] & ~inst[31] & ~inst[27]; +assign ctrl.DCtrl.DP0 = ~inst[31]; +assign ctrl.DCtrl.DP1 = ~inst[30] & (~inst[26] & (~inst[29] & (~inst[28] & (~inst[31] & (~inst[27] & ~inst[4] | inst[27]) | inst[31]) | inst[28]) | inst[29]) | inst[26]) | inst[30] & inst[25]; +assign ctrl.DCtrl.UI = inst[28] & inst[27] & inst[26]; +assign ctrl.DCtrl.IX = ~inst[28] | inst[28] & inst[31]; +assign ctrl.ECtrl.ALT = ~inst[31] & (~inst[26] & (~inst[27] & ~inst[29] & inst[1] & (~inst[5] & inst[0] | inst[5]) | inst[27]) | inst[26] & inst[27] & inst[29] & ~inst[28]); +assign ctrl.OFA = ~inst[26] & (~inst[29] & ~inst[30] & ~inst[28] & ~inst[31] & ~inst[27] & inst[5] & ~inst[0] & ~inst[2] & ~inst[3] | inst[29] & ~inst[28] & ~inst[31] & ~inst[27]); +assign ctrl.MCtrl1.MR = inst[31]; +assign ctrl.MCtrl1.MWR = inst[29]; +assign ctrl.MCtrl1.MX = ~inst[28]; +assign ctrl.WCtrl.RW = ~inst[30] & (~inst[29] & (~inst[31] & ~inst[28] & (~inst[27] & (~inst[26] & (~inst[3] & (~inst[4] | inst[4] & ~inst[0]) | inst[3] & (~inst[5] & ~inst[4] & ~inst[2] & inst[0] | inst[5])) | inst[26] & inst[20]) | inst[27] & inst[26]) | inst[31]) | inst[29] & ~inst[31]) | inst[30] & ~inst[25] & ~inst[23]; +assign ctrl.MCtrl0.HW = ~inst[26] & ~inst[29] & ~inst[30] & ~inst[28] & ~inst[27] & inst[4] & (~inst[3] & ~inst[1] & inst[0] | inst[3]); +assign ctrl.MCtrl0.LW = ~inst[26] & ~inst[29] & ~inst[30] & ~inst[28] & ~inst[27] & inst[4] & (~inst[3] & inst[1] & inst[0] | inst[3]); +assign ctrl.MCtrl0.C0W = inst[30] & inst[23];