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2alu tryfix

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cxy004 2022-08-04 12:40:46 +08:00
parent 101230bd67
commit cc1988ceba
1 changed files with 7 additions and 7 deletions
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14
src/Core/Datapath.sv
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@ -554,20 +554,20 @@ module Datapath (
// Load -> Arith // Load -> Arith
| E.I1.WCtrl.RW & D.IB.RS == E.I1.RD & D.IB.ES & E.I1.MCtrl.MR | E.I1.WCtrl.RW & D.IB.RS == E.I1.RD & D.IB.ES & E.I1.MCtrl.MR
| E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & D.IB.ET & E.I1.MCtrl.MR | E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & D.IB.ET & E.I1.MCtrl.MR
// Load -> ALU2
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ES2 & ~D.IA.DP0
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ET2 & ~D.IA.DP0
// Arith -> Arith // Arith -> Arith
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ES | D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ES
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ET | D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ET
// Load -> Arith2
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ES2 & ~D.IA.DP0
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ET2 & ~D.IA.DP0
// Load -> MulDiv
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.MCtrl0.HLS[2] & ~D.IA.DP0
// Load -> C0 // Load -> C0
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl0.C0W & ~D.IA.DP0 | D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl0.C0W & ~D.IA.DP0
// Not Arith -> Store // Not Arith -> Store
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl1.MWR & ~D.IA.DP1 | D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl1.MWR & (~D.IA.DP1 | D_IA_HazardALU2)
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl1.MWR & D_IA_HazardALU2
// Not Arith -> LWL/LWR // Not Arith -> LWL/LWR
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & |D.IB.MCtrl1.ALR & ~D.IA.DP1 | D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & |D.IB.MCtrl1.ALR & (~D.IA.DP1 | D_IA_HazardALU2)
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & |D.IB.MCtrl1.ALR & D_IA_HazardALU2
// CP0 Execution Hazards // CP0 Execution Hazards
// Hazards Related to the TLB // Hazards Related to the TLB
| D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBR & D.IA.MCtrl0.C0D == C0_INDEX | D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBR & D.IA.MCtrl0.C0D == C0_INDEX