Fix TLB
This commit is contained in:
parent
7a506ba611
commit
caa2171996
20
src/MU/MU.sv
20
src/MU/MU.sv
@ -660,8 +660,8 @@ module MU (
|
||||
|
||||
word_t iVA, iPA1;
|
||||
word_t dVA, dPA1;
|
||||
logic iHit1, iCached1, iMValid1, iUser1;
|
||||
logic dHit1, dCached1, dMValid1, dUser1, dDirty1;
|
||||
logic iHit1, iCached1, iMValid1, iPrv1;
|
||||
logic dHit1, dCached1, dMValid1, dPrv1, dDirty1;
|
||||
|
||||
TLB TLB (
|
||||
.clk (clk),
|
||||
@ -683,14 +683,14 @@ module MU (
|
||||
.iHit (iHit1),
|
||||
.iCached (iCached1),
|
||||
.iValid (iMValid1),
|
||||
.iUser (iUser1),
|
||||
.iPrv (iPrv1),
|
||||
.dVAddr (dVA),
|
||||
.dPAddr (dPA1),
|
||||
.dHit (dHit1),
|
||||
.dCached (dCached1),
|
||||
.dDirty (dDirty1),
|
||||
.dValid (dMValid1),
|
||||
.dUser (dUser1)
|
||||
.dPrv (dPrv1)
|
||||
);
|
||||
|
||||
logic choose_cop_i, choose_cop_d;
|
||||
@ -706,23 +706,23 @@ module MU (
|
||||
// instfetch
|
||||
assign iVA = choose_cop_i ? cacheop.addr : (instfetch.req & instfetch.addr_ok & ~if_wait_cache ? instfetch.addr : stored_instfetch_addr);
|
||||
assign instfetch_phy_addr = iPA1;
|
||||
assign instfetch_valid = iHit1 & iMValid1 & (cp0.cp0_in_kernel | iUser1);
|
||||
assign instfetch_valid = iHit1 & iMValid1 & (cp0.cp0_in_kernel | ~iPrv1);
|
||||
assign instfetch_cached = iCached1;
|
||||
|
||||
assign cp0.tlb_iTLBRefill = if_req & ~iHit1;
|
||||
assign cp0.tlb_iTLBRefill = if_req & ~iHit1 & (cp0.cp0_in_kernel | ~iPrv1);
|
||||
assign cp0.tlb_iTLBInvalid = if_req & ~iMValid1;
|
||||
assign cp0.tlb_iAddressError = if_req & ~(cp0.cp0_in_kernel | iUser1);
|
||||
assign cp0.tlb_iAddressError = if_req & ~cp0.cp0_in_kernel & iPrv1;
|
||||
|
||||
// memory
|
||||
assign dVA = choose_cop_d ? cacheop.addr : (memory.req & memory.addr_ok & ~mem_wait_cache ? memory.addr : stored_memory_addr);
|
||||
assign memory_phy_addr = dPA1;
|
||||
assign memory_valid = dHit1 & dMValid1 & (cp0.cp0_in_kernel | dUser1) & (~memory.wr | dDirty1);
|
||||
assign memory_valid = dHit1 & dMValid1 & (cp0.cp0_in_kernel | ~dPrv1) & (~memory.wr | dDirty1);
|
||||
assign memory_cached = dCached1;
|
||||
|
||||
assign cp0.tlb_dTLBRefill = mem_req & ~dHit1;
|
||||
assign cp0.tlb_dTLBRefill = mem_req & ~dHit1 & (cp0.cp0_in_kernel | ~dPrv1);
|
||||
assign cp0.tlb_dTLBInvalid = mem_req & ~dMValid1;
|
||||
assign cp0.tlb_dTLBModified = mem_req & memory.wr & ~dDirty1;
|
||||
assign cp0.tlb_dAddressError = mem_req & ~(cp0.cp0_in_kernel | dUser1);
|
||||
assign cp0.tlb_dAddressError = mem_req & ~cp0.cp0_in_kernel & dPrv1;
|
||||
|
||||
`else
|
||||
|
||||
|
@ -26,7 +26,7 @@ module TLB (
|
||||
output logic iHit, // TLB Refill
|
||||
output logic iCached,
|
||||
output logic iValid, // TLB Invalid
|
||||
output logic iUser, // Privilege
|
||||
output logic iPrv, // Privilege
|
||||
|
||||
input word_t dVAddr,
|
||||
output word_t dPAddr,
|
||||
@ -34,7 +34,7 @@ module TLB (
|
||||
output logic dCached,
|
||||
output logic dDirty, // TLB Modified
|
||||
output logic dValid, // TLB Invalid
|
||||
output logic dUser // Privilege
|
||||
output logic dPrv // Privilege
|
||||
);
|
||||
|
||||
word_t fVAddr, fVAddr1;
|
||||
@ -149,7 +149,7 @@ module TLB (
|
||||
.cached (iCached),
|
||||
.dirty (),
|
||||
.valid (iValid),
|
||||
.privilege (iUser) // not
|
||||
.privilege (iPrv)
|
||||
);
|
||||
/* verilator lint_on PINCONNECTEMPTY */
|
||||
|
||||
@ -172,7 +172,7 @@ module TLB (
|
||||
.cached (dCached),
|
||||
.dirty (dDirty),
|
||||
.valid (dValid),
|
||||
.privilege (dUser) // not
|
||||
.privilege (dPrv)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
@ -1,5 +1,6 @@
|
||||
`include "defines.svh"
|
||||
`include "Cache.svh"
|
||||
`include "CP0.svh"
|
||||
|
||||
interface InstFetch_i;
|
||||
logic req;
|
||||
|
Loading…
Reference in New Issue
Block a user