[Cache] ICache fix LRU
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@ -50,6 +50,7 @@ module ICache (
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wire [`IC_TAG_LENGTH-1:0] tagOut1[4];
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wire [`IC_DATA_LENGTH-1:0] dataOut1[4];
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wire [3:0] tagV1;
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wire hit1; // Cache hit or not
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wire [3:0] hitWay1; // Cache Line hit or not
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@ -66,6 +67,7 @@ module ICache (
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wire hit2;
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wire [3:0] hitWay2;
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wire [3:0] tagV2;
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typedef enum logic [1:0] {
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Idle,
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@ -81,6 +83,7 @@ module ICache (
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wire [5:0] addr3;
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wire [`IC_TAG_LENGTH-2:0] tag3;
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wire [1:0] victim3;
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wire [3:0] tagV3;
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wire [3:0] wen3;
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@ -103,10 +106,11 @@ module ICache (
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end
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end
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mux2 #(6) ctrl0_mux (
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mux3 #(6) ctrl0_mux (
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sram.addr[9:4],
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PC1[9:4],
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wAddr4,
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ctrl0,
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{ctrl0, ~sram.addr_ok}, // TODO: 这里可能有问题,需要详细测试
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cacheAddress0
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);
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@ -135,7 +139,7 @@ module ICache (
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// =========== Lookup ===========
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// ==============================
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// TODO: 确保cacheMiss时tagOut1和dataOut1不变
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// 确保cacheMiss时tagOut1和dataOut1不变 -> L106 mux3解决?
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assign tagOut1[0] = TagRAM0.rdata;
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assign tagOut1[1] = TagRAM1.rdata;
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assign tagOut1[2] = TagRAM2.rdata;
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@ -146,14 +150,19 @@ module ICache (
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assign dataOut1[2] = DataRAM2.rdata;
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assign dataOut1[3] = DataRAM3.rdata;
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assign tagV1[0] = tagOut1[0][0];
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assign tagV1[1] = tagOut1[1][0];
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assign tagV1[2] = tagOut1[2][0];
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assign tagV1[3] = tagOut1[3][0];
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// Hit Check
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assign tag1 = PC1[31:10];
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assign addr1 = PC1[9:4];
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assign hitWay1[0] = tagOut1[0][0] & tagOut1[0][`IC_TAG_LENGTH-1:1] == tag1;
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assign hitWay1[1] = tagOut1[1][0] & tagOut1[1][`IC_TAG_LENGTH-1:1] == tag1;
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assign hitWay1[2] = tagOut1[2][0] & tagOut1[2][`IC_TAG_LENGTH-1:1] == tag1;
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assign hitWay1[3] = tagOut1[3][0] & tagOut1[3][`IC_TAG_LENGTH-1:1] == tag1;
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assign hitWay1[0] = tagV1[0] & tagOut1[0][`IC_TAG_LENGTH-1:1] == tag1;
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assign hitWay1[1] = tagV1[1] & tagOut1[1][`IC_TAG_LENGTH-1:1] == tag1;
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assign hitWay1[2] = tagV1[2] & tagOut1[2][`IC_TAG_LENGTH-1:1] == tag1;
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assign hitWay1[3] = tagV1[3] & tagOut1[3][`IC_TAG_LENGTH-1:1] == tag1;
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assign hit1 = hitWay1[0] | hitWay1[1] | hitWay1[2] | hitWay1[3];
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assign cacheLine1 = (hitWay1[0] ? dataOut1[0] : `IC_DATA_LENGTH'b0) |
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@ -221,12 +230,12 @@ module ICache (
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// ==== Pipeline Register 2 =====
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// ==============================
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ffenr #(37) pipelineReg2 (
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ffenr #(41) pipelineReg2 (
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.clk(clk),
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.rst(rst | AXIBlocker == Done),
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.en (AXIBlocker == Idle), // TODO: 这里需要重新设计一下: AXI是否流水
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.d ({PC1, hitWay1, cacheMiss}),
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.q ({PC2, hitWay2, req2}) // TODO: Req2的逻辑可能有误
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.d ({PC1, hitWay1, cacheMiss, tagV1}),
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.q ({PC2, hitWay2, req2, tagV2})
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);
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// ==============================
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@ -268,19 +277,23 @@ module ICache (
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// ==== Pipeline Register 3 =====
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// ==============================
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ffenr #(`IC_DATA_LENGTH + 1 + 6 + 22) pipelineReg3 (
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ffenr #(`IC_DATA_LENGTH + 1 + 6 + 22 + 4) pipelineReg3 (
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.clk(clk),
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.rst(rst),
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.en (1'b1),
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.d ({ICacheLine, ICacheLineOK, PC2[9:4], PC2[31:10]}),
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.q ({ICacheLine3, ICacheLineOK3, addr3, tag3})
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.d ({ICacheLine, ICacheLineOK, PC2[9:4], PC2[31:10], tagV2}),
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.q ({ICacheLine3, ICacheLineOK3, addr3, tag3, tagV3})
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);
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// ==============================
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// ========== Replace ===========
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// ==============================
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assign victim3 = LRU[addr3][0] == 0 ? 2'b00 :
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assign victim3 = tagV3[0] == 0 ? 2'b00 :
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tagV3[1] == 0 ? 2'b01 :
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tagV3[2] == 0 ? 2'b10 :
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tagV3[3] == 0 ? 2'b11 :
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LRU[addr3][0] == 0 ? 2'b00 :
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LRU[addr3][1] == 0 ? 2'b01 :
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LRU[addr3][2] == 0 ? 2'b10 :
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LRU[addr3][3] == 0 ? 2'b11 :
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@ -290,6 +303,13 @@ module ICache (
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assign wen3[2] = (victim3 == 2) & ICacheLineOK3;
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assign wen3[3] = (victim3 == 3) & ICacheLineOK3;
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always_ff @(posedge clk) begin
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if (wen3 != 0) begin
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$display("Victim Found: wen3=0x%b, addr3=0x%8h, tagV3=0x%b, LRU=0x%b", wen3, addr3, tagV3,
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LRU[addr3]);
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end
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end
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// ==============================
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// ==== Pipeline Register 4 =====
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// ==============================
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2
src/testbench/icache/.gitignore
vendored
2
src/testbench/icache/.gitignore
vendored
@ -1,3 +1 @@
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obj_dir
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logs
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coe
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@ -1,13 +0,0 @@
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verilator -I/home/paul/loongson/MIPS/src/AXI/ \
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-I/home/paul/loongson/MIPS/src/Cache/ \
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-I/home/paul/loongson/MIPS/src/Core/ \
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-I/home/paul/loongson/MIPS/src/CP0/ \
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-I/home/paul/loongson/MIPS/src/include/ \
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-I/home/paul/loongson/MIPS/src/testbench/happy/ \
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+1800-2017ext+sv \
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--cc --trace --exe --build \
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sim_main.cpp testbench.sv
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./obj_dir/Vtestbench +trace
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gtkwave ./logs/vlt_dump.vcd
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@ -1,90 +0,0 @@
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#include <memory>
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#include "Vtestbench.h"
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#include "verilated.h"
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int main(int argc, char **argv, char **env)
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{
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// Create logs/ directory in case we have traces to put under it
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Verilated::mkdir("logs");
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// Construct a VerilatedContext to hold simulation time, etc.
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// Multiple modules (made later below with Vtop) may share the same
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// context to share time, or modules may have different contexts if
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// they should be independent from each other.
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// Using unique_ptr is similar to
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// "VerilatedContext* contextp = new VerilatedContext" then deleting at end.
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const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
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// Set debug level, 0 is off, 9 is highest presently used
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// May be overridden by commandArgs argument parsing
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contextp->debug(0);
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// Randomization reset policy
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// May be overridden by commandArgs argument parsing
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contextp->randReset(2);
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// Verilator must compute traced signals
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contextp->traceEverOn(true);
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// Pass arguments so Verilated code can see them, e.g. $value$plusargs
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// This needs to be called before you create any model
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contextp->commandArgs(argc, argv);
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// Construct the Verilated model, from Vtop.h generated from Verilating "top.v".
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// Using unique_ptr is similar to "Vtop* top = new Vtop" then deleting at end.
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// "TOP" will be the hierarchical name of the module.
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const std::unique_ptr<Vtestbench> top{new Vtestbench{contextp.get(), "TESTBENCH"}};
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// Set Vtop's input signals
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top->clk = 0;
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top->rst = 0;
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// Simulate until $finish
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while (!contextp->gotFinish())
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{
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// Historical note, before Verilator 4.200 Verilated::gotFinish()
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// was used above in place of contextp->gotFinish().
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// Most of the contextp-> calls can use Verilated:: calls instead;
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// the Verilated:: versions simply assume there's a single context
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// being used (per thread). It's faster and clearer to use the
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// newer contextp-> versions.
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contextp->timeInc(1); // 1 timeprecision period passes...
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// Historical note, before Verilator 4.200 a sc_time_stamp()
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// function was required instead of using timeInc. Once timeInc()
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// is called (with non-zero), the Verilated libraries assume the
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// new API, and sc_time_stamp() will no longer work.
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// Toggle a fast (time/2 period) clock
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top->clk = !top->clk;
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// Evaluate model
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// (If you have multiple models being simulated in the same
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// timestep then instead of eval(), call eval_step() on each, then
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// eval_end_step() on each. See the manual.)
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top->eval();
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// Read outputs
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VL_PRINTF("[%" VL_PRI64 "d] clk=%x rst=%x -> "
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"req=%x "
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"addr=%" VL_PRI64 "x "
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"addr_ok=%x data_ok=%x "
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"rdata0=%" VL_PRI64 "x "
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"rdata1=%" VL_PRI64 "x "
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"\n",
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contextp->time(), top->clk, top->rst,
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top->req,
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top->addr,
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top->addr_ok, top->data_ok,
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top->rdata0,
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top->rdata1);
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}
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// Final model cleanup
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top->final();
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// Return good completion status
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// Don't use exit() or destructor won't get called
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return 0;
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}
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@ -114,7 +114,7 @@ module test ();
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assign rready = fake_axi.AXIReadAddr.rready;
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integer counter = 0;
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reg [31:0] addr;
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reg [11:0] addr;
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enum logic [1:0] {
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IDLE,
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REQ,
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@ -135,8 +135,8 @@ module test ();
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nextStatus = REQ;
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end else begin
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fake_sram.req = 1'b1;
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//fake_sram.addr = addr;
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fake_sram.addr = addrt[addrx];
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fake_sram.addr = {18'b0, addr, 2'b0};
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//fake_sram.addr = addrt[addrx];
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nextStatus = REQ;
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end
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end else nextStatus = IDLE;
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@ -148,8 +148,12 @@ module test ();
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end
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if (fake_sram.data_ok) begin
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nextStatus = IDLE;
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//addr = addr + 8;
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addrx = addrx + 1;
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if(fake_sram.rdata0 != (addr&'hFFE) && fake_sram.rdata1 != (addr&'hFFE) + 1)begin
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$display("ERROR OCCURED! addr=0x%8h, rdata0=0x%8h, rdata1=0x%8h",
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((addr-1)<<2), fake_sram.rdata0, fake_sram.rdata1);
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end
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addr = addr + 1;
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//addrx = addrx + 1;
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end else nextStatus = REQ;
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end else nextStatus = IDLE;
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end
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@ -190,7 +194,7 @@ module test ();
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$dumpvars();
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status = IDLE;
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addr = 20;
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addr = 0;
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addrx = 0;
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addrt[0] = 48;
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@ -1,45 +0,0 @@
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`include "ICache.svh"
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`include "sram.svh"
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module testbench (
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input clk,
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input rst,
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output req,
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output word_t addr,
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output addr_ok,
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output data_ok,
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output word_t rdata0,
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output word_t rdata1
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);
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sramro_i fake_sram ();
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ICache ic (
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.clk (clk),
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.rst (rst),
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.sram(fake_sram.slave)
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);
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assign req = fake_sram.req;
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assign addr = fake_sram.addr;
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assign addr_ok = fake_sram.addr_ok;
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assign data_ok = fake_sram.data_ok;
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assign rdata0 = fake_sram.rdata0;
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assign rdata1 = fake_sram.rdata1;
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initial begin
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$dumpfile("logs/vlt_dump.vcd");
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$dumpvars();
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fake_sram.req = 1;
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fake_sram.addr = 32'b0100000;
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end
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integer counter = 0;
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always_ff @(posedge clk) begin
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if (fake_sram.data_ok) fake_sram.addr = fake_sram.addr + 1;
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if (clk == 1'b1) begin
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counter = counter + 1;
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if (counter >= 16) $finish;
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end
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end
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endmodule
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