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resources/soc/rtl/AMBA/axi2apb.v
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542
resources/soc/rtl/AMBA/axi2apb.v
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/*------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Copyright (c) 2016, Loongson Technology Corporation Limited.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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3. Neither the name of Loongson Technology Corporation Limited nor the names of
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its contributors may be used to endorse or promote products derived from this
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software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
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TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--------------------------------------------------------------------------------
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------------------------------------------------------------------------------*/
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`include "config.h"
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module axi2apb_bridge(
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clk,
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rst_n,
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axi_s_awid,
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axi_s_awaddr,
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axi_s_awlen,
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axi_s_awsize,
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axi_s_awburst,
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axi_s_awlock,
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axi_s_awcache,
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axi_s_awprot,
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axi_s_awvalid,
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axi_s_awready,
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axi_s_wid,
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axi_s_wdata,
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axi_s_wstrb,
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axi_s_wlast,
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axi_s_wvalid,
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axi_s_wready,
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axi_s_bid,
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axi_s_bresp,
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axi_s_bvalid,
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axi_s_bready,
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axi_s_arid,
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axi_s_araddr,
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axi_s_arlen,
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axi_s_arsize,
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axi_s_arburst,
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axi_s_arlock,
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axi_s_arcache,
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axi_s_arprot,
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axi_s_arvalid,
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axi_s_arready,
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axi_s_rid,
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axi_s_rdata,
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axi_s_rresp,
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axi_s_rlast,
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axi_s_rvalid,
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axi_s_rready,
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apb_valid_cpu,
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cpu_grant,
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apb_word_trans,
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apb_high_24b_rd,
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apb_high_24b_wr,
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apb_clk,
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apb_reset_n,
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reg_psel,
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reg_enable,
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reg_rw,
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reg_addr,
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reg_datai,
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reg_ready_1,
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reg_datao
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);
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parameter L_ADDR_APB = 20;
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input clk;
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input rst_n;
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input [`LID -1 :0] axi_s_awid;
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input [`Lawaddr -1 :0] axi_s_awaddr;
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input [`Lawlen -1 :0] axi_s_awlen;
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input [`Lawsize -1 :0] axi_s_awsize;
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input [`Lawburst -1 :0] axi_s_awburst;
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input [`Lawlock -1 :0] axi_s_awlock;
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input [`Lawcache -1 :0] axi_s_awcache;
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input [`Lawprot -1 :0] axi_s_awprot;
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input axi_s_awvalid;
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output axi_s_awready;
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input [`LID -1 :0] axi_s_wid;
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input [`Lwdata -1 :0] axi_s_wdata;
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input [`Lwstrb -1 :0] axi_s_wstrb;
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input axi_s_wlast;
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input axi_s_wvalid;
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output axi_s_wready;
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output [`LID -1 :0] axi_s_bid;
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output [`Lbresp -1 :0] axi_s_bresp;
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output axi_s_bvalid;
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input axi_s_bready;
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input [`LID -1 :0] axi_s_arid;
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input [`Laraddr -1 :0] axi_s_araddr;
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input [`Larlen -1 :0] axi_s_arlen;
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input [`Larsize -1 :0] axi_s_arsize;
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input [`Larburst -1 :0] axi_s_arburst;
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input [`Larlock -1 :0] axi_s_arlock;
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input [`Larcache -1 :0] axi_s_arcache;
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input [`Larprot -1 :0] axi_s_arprot;
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input axi_s_arvalid;
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output axi_s_arready;
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output [`LID -1 :0] axi_s_rid;
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output [`Lrdata -1 :0] axi_s_rdata;
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output [`Lrresp -1 :0] axi_s_rresp;
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output axi_s_rlast;
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output axi_s_rvalid;
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input axi_s_rready;
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input apb_word_trans;
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input cpu_grant;
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output apb_valid_cpu;
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input [23:0] apb_high_24b_rd;
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output [23:0] apb_high_24b_wr;
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output apb_clk;
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output apb_reset_n;
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output reg_psel;
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output reg_enable;
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output reg_rw;
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output[L_ADDR_APB-1:0] reg_addr;
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output[7:0] reg_datai;
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input [7:0] reg_datao;
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input reg_ready_1;
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wire csr_rw_send_axi_rsp_done;
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wire reg_ready;
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parameter CSR_RW_SM_IDLE = 4'b0001,
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CSR_RW_SM_GET_AXI_ADDR = 4'b0010,
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CSR_RW_SM_SEND_AXI_RSP = 4'b1000;
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reg reg_psel;
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reg reg_enable;
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reg axi_s_sel_rd;
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reg axi_s_sel_wr;
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reg[3:0] csr_rw_sm;
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reg[3:0] csr_rw_sm_nxt;
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reg[L_ADDR_APB-1:0] axi_s_req_addr;
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reg[`LID-1:0] axi_s_w_id;
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reg[`LID-1:0] axi_s_r_id;
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reg[23:0] apb_high_24b_wr;
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assign apb_clk = clk;
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assign apb_reset_n = rst_n;
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assign reg_rw = axi_s_sel_wr;
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assign reg_addr = axi_s_req_addr;
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assign reg_ready = reg_enable & reg_ready_1;
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assign apb_valid_cpu = axi_s_sel_wr | axi_s_sel_rd | axi_s_awvalid | axi_s_arvalid;
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reg axi_s_rlast;
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reg axi_s_rvalid;
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reg axi_s_wready;
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reg axi_s_awready;
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reg axi_s_arready;
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reg [1:0]axi_s_rstrb;
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reg [3:0]apb_s_wstrb;
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reg [31:0]reg_datai_32;
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reg [31:0]reg_datao_32;
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reg [2:0] rd_count;
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reg [2:0] apb_rd_size;
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reg [2:0] apb_wr_size;
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reg [7:0] reg_datai;
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reg axi_s_bvalid;
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always@(posedge clk)
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begin
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if(!rst_n)
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begin
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reg_datai_32 <= 32'h0;
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reg_datao_32 <= 32'h0;
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axi_s_req_addr <= 20'h0;
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apb_s_wstrb <= 4'b0;
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axi_s_rstrb <= 2'b0;
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axi_s_wready <= 1'b0;
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reg_enable <= 1'b0;
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reg_psel <= 1'b0;
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rd_count <= 3'b0;
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apb_rd_size <= 3'b0;
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apb_wr_size <= 3'b0;
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axi_s_rlast <= 1'b0;
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axi_s_rvalid <= 1'b0;
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reg_datai <= 8'b0;
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axi_s_awready <= 1'b0;
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axi_s_arready <= 1'b0;
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axi_s_bvalid <= 1'b0;
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axi_s_sel_wr <= 1'b0;
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axi_s_sel_rd <= 1'b0;
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axi_s_w_id <= 'h0;
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axi_s_r_id <= 'h0;
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apb_high_24b_wr <= 24'h0;
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end
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else begin
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if(axi_s_awvalid & ~axi_s_bvalid & ~axi_s_sel_rd & (csr_rw_sm == CSR_RW_SM_IDLE) &cpu_grant) begin
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axi_s_req_addr <= axi_s_awaddr[L_ADDR_APB-1:0];
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axi_s_awready <= 1'b1;
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axi_s_sel_wr <= 1'b1;
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apb_wr_size <= axi_s_awsize;
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end
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else if(axi_s_sel_wr) begin
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axi_s_awready <= 1'b0;
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if(axi_s_wvalid && ~axi_s_wready) begin
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axi_s_req_addr <= (axi_s_wstrb[3:0]==4'h2)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h1):
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(axi_s_wstrb[3:0]==4'h4)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h2):
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(axi_s_wstrb[3:0]==4'h8)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h3):
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(axi_s_wstrb[3:0]==4'h6)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h1):
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(axi_s_wstrb[3:0]==4'hc)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h2): axi_s_req_addr ;
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axi_s_wready <= 1'b1;
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reg_psel <= 1'b0;
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reg_enable <= 1'b0;
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axi_s_w_id <= axi_s_wid;
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case({axi_s_req_addr[1:0]})
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2'b00: begin apb_s_wstrb <= axi_s_wstrb[3:0]; reg_datai_32 <=axi_s_wdata[31:0]; end
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2'b01: begin apb_s_wstrb <= {1'b0,axi_s_wstrb[3:1]}; reg_datai_32 <={8'h0,axi_s_wdata[31:8]}; end
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2'b10: begin apb_s_wstrb <= {2'b0,axi_s_wstrb[3:2]}; reg_datai_32 <={16'b0,axi_s_wdata[31:16]}; end
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2'b11: begin apb_s_wstrb <= {3'b0,axi_s_wstrb[3]}; reg_datai_32 <={24'b0,axi_s_wdata[31:24]}; end
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default: begin apb_s_wstrb <= 4'b0; reg_datai_32 <=32'h0; end
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endcase
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end
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else if((~reg_psel) && (apb_s_wstrb!=4'h0) ) begin
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reg_psel <= 1'b1;
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reg_enable <= 1'b0;
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reg_datai <= (apb_s_wstrb == 4'h1) ? reg_datai_32[7:0]:
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(apb_s_wstrb == 4'h2) ? reg_datai_32[15:8]:
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(apb_s_wstrb == 4'h6) ? reg_datai_32[15:8]:
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(apb_s_wstrb == 4'h4) ? reg_datai_32[23:16]:
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(apb_s_wstrb == 4'h8) ? reg_datai_32[31:24]: reg_datai_32[7:0];
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apb_high_24b_wr <= reg_datai_32[31:8];
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if(axi_s_bready) axi_s_bvalid <= 1'b0;
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end
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else if(apb_word_trans & apb_s_wstrb==4'hf ) begin
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if(~reg_ready)begin
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reg_psel <= 1'b1;
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reg_enable <= 1'b1;
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end
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else begin
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reg_psel <= 1'b0;
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reg_enable <= 1'b0;
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axi_s_sel_wr <= 1'b0;
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axi_s_bvalid <= 1'b1;
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apb_s_wstrb <= 4'b0;
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end
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reg_datai <= reg_datai_32[7:0];
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apb_high_24b_wr <= reg_datai_32[31:8];
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axi_s_wready <= 1'b0;
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end
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else if(apb_s_wstrb[0]) begin
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if(~reg_ready)begin
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reg_psel <= 1'b1;
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reg_enable <= 1'b1;
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reg_datai <= reg_datai_32[7:0];
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end
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else begin
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if(apb_s_wstrb[3:1] ==3'b0)
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begin
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reg_psel <= 1'b0;
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axi_s_sel_wr<= 1'b0;
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axi_s_bvalid <= 1'b1;
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end
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else
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reg_psel <= 1'b1;
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reg_enable <= 1'b0;
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apb_s_wstrb[0] <= 1'b0;
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axi_s_req_addr <= axi_s_req_addr +1'b1;
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reg_datai <= reg_datai_32[15:8];
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end
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axi_s_wready <= 1'b0;
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end
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else if (apb_s_wstrb[1]) begin
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if(~reg_ready)begin
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reg_psel <= 1'b1;
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reg_enable <= 1'b1;
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end
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else begin
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if(apb_s_wstrb[3:2] ==2'b0)
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begin
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reg_psel <= 1'b0;
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axi_s_sel_wr <= 1'b0;
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axi_s_bvalid <= 1'b1;
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end
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else
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reg_psel <= 1'b1;
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reg_enable <= 1'b0;
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apb_s_wstrb[1] <= 1'b0;
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axi_s_req_addr <= axi_s_req_addr +1'b1;
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reg_datai <= reg_datai_32[23:16];
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end
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axi_s_wready <= 1'b0;
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end
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else if (apb_s_wstrb[2]) begin
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if(~reg_ready)begin
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reg_psel <= 1'b1;
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reg_enable <= 1'b1;
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end
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else begin
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if(apb_s_wstrb[3] ==1'b0)
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begin
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reg_psel <= 1'b0;
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axi_s_sel_wr <= 1'b0;
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axi_s_bvalid <= 1'b1;
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end
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else
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reg_psel <= 1'b1;
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reg_enable <= 1'b0;
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apb_s_wstrb[2] <= 1'b0;
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axi_s_req_addr <= axi_s_req_addr +1'b1;
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reg_datai <= reg_datai_32[31:24];
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end
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axi_s_wready <= 1'b0;
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end
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else if (apb_s_wstrb[3]) begin
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if(~reg_ready)begin
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reg_psel <= 1'b1;
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reg_enable <= 1'b1;
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end
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else begin
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reg_psel <= 1'b0;
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reg_enable <= 1'b0;
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axi_s_sel_wr <= 1'b0;
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axi_s_bvalid <= 1'b1;
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apb_s_wstrb[3] <= 1'b0;
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end
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axi_s_wready <= 1'b0;
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end
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else begin
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reg_psel <= 1'b0;
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reg_enable <= 1'b0;
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reg_datai <= 8'h0;
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apb_s_wstrb <= 4'h0;
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axi_s_wready <= 1'b0;
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if(csr_rw_sm == CSR_RW_SM_IDLE) axi_s_sel_wr <= 1'b0;
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end
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end
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else if(axi_s_arvalid & ~axi_s_arready & ~axi_s_bvalid & (csr_rw_sm == CSR_RW_SM_IDLE)&cpu_grant)
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begin
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reg_enable <= 1'b0;
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reg_psel <= 1'b1;
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axi_s_arready <= 1'b1;
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axi_s_sel_rd <= 1'b1;
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axi_s_r_id <= axi_s_arid;
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apb_rd_size <= axi_s_arsize;
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axi_s_req_addr <= axi_s_araddr[L_ADDR_APB-1:0];
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axi_s_rstrb <= axi_s_araddr[1:0];
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if(axi_s_arsize==3'b010)
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rd_count<= 3'h4;
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else if(axi_s_arsize==3'b01)
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rd_count<= 3'h2;
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else if(axi_s_arsize==3'b0)
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rd_count<= 3'h1;
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end
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else if(axi_s_sel_rd)
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begin
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axi_s_arready <= 1'b0;
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if(apb_word_trans)
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begin
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if(reg_ready)
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begin
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reg_psel <= rd_count==3'b10;
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reg_enable <= 1'b0;
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rd_count <= rd_count-3'b1;
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axi_s_rlast <= apb_rd_size==3'h2|rd_count==2'b1;
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axi_s_rvalid <= apb_rd_size==3'h2|rd_count==2'b1;
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axi_s_sel_rd <= rd_count==3'b10;
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reg_datao_32 <= {apb_high_24b_rd,reg_datao};
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end
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else begin
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reg_psel <= 1'b1;
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reg_enable <= 1'b1;
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end
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end
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else if(rd_count==3'h4)
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begin
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if(reg_ready)
|
||||
begin
|
||||
reg_psel <= 1'b1;
|
||||
reg_enable <= 1'b0;
|
||||
rd_count <= rd_count-3'h1;
|
||||
reg_datao_32[7:0] <= reg_datao;
|
||||
axi_s_req_addr <= axi_s_req_addr +1'b1;
|
||||
end
|
||||
else begin
|
||||
reg_psel <= 1'b1;
|
||||
reg_enable <= 1'b1;
|
||||
end
|
||||
end
|
||||
else if(rd_count==3'h3)
|
||||
begin
|
||||
if(reg_ready)
|
||||
begin
|
||||
reg_psel <= 1'b1;
|
||||
reg_enable <= 1'b0;
|
||||
rd_count <= rd_count-3'h1;
|
||||
reg_datao_32[15:8] <= reg_datao;
|
||||
axi_s_req_addr <= axi_s_req_addr +1'b1;
|
||||
end
|
||||
else begin
|
||||
reg_psel <= 1'b1;
|
||||
reg_enable <= 1'b1;
|
||||
end
|
||||
end
|
||||
else if(rd_count==3'h2)
|
||||
begin
|
||||
if(reg_ready)
|
||||
begin
|
||||
reg_psel <= 1'b1;
|
||||
reg_enable <= 1'b0;
|
||||
rd_count <= rd_count-3'h1;
|
||||
axi_s_req_addr <= axi_s_req_addr +1'b1;
|
||||
if(apb_rd_size==3'h2 )
|
||||
reg_datao_32[23:16] <= reg_datao;
|
||||
else if(apb_rd_size==3'h1)
|
||||
reg_datao_32[7:0] <= reg_datao;
|
||||
end
|
||||
else begin
|
||||
reg_psel <= 1'b1;
|
||||
reg_enable <= 1'b1;
|
||||
end
|
||||
end
|
||||
else if(rd_count==3'h1)
|
||||
begin
|
||||
if(reg_ready)
|
||||
begin
|
||||
reg_psel <= 1'b0;
|
||||
reg_enable <= 1'b0;
|
||||
axi_s_rlast <= 1'b1;
|
||||
axi_s_rvalid <= 1'b1;
|
||||
axi_s_sel_rd <= 1'b0;
|
||||
if(apb_rd_size==3'h2 )
|
||||
reg_datao_32[31:24] <= reg_datao;
|
||||
else if(apb_rd_size==3'h1)
|
||||
reg_datao_32[15:8] <= reg_datao;
|
||||
else if(apb_rd_size==3'h0)
|
||||
reg_datao_32[7:0] <= reg_datao;
|
||||
end
|
||||
else begin
|
||||
reg_psel <= 1'b1;
|
||||
reg_enable <= 1'b1;
|
||||
end
|
||||
end// end if(rd_count)
|
||||
else begin
|
||||
axi_s_arready <= 1'b0;
|
||||
axi_s_rlast <= 1'b1;
|
||||
axi_s_rvalid <= 1'b1;
|
||||
reg_psel <= 1'b0;
|
||||
reg_enable <= 1'b0;
|
||||
if(axi_s_rvalid && axi_s_rready)
|
||||
begin
|
||||
reg_datao_32 <= 32'h0;
|
||||
axi_s_rlast <= 1'b0;
|
||||
axi_s_rvalid <= 1'b0;
|
||||
end
|
||||
if(csr_rw_sm == CSR_RW_SM_IDLE) axi_s_sel_rd <= 1'b0;
|
||||
if(axi_s_bready) axi_s_bvalid <= 1'b0;
|
||||
end
|
||||
end//end if(axi_s_sel_rd)
|
||||
else begin
|
||||
reg_psel <= 1'b0;
|
||||
reg_enable <= 1'b0;
|
||||
axi_s_sel_wr <= 1'b0;
|
||||
axi_s_sel_rd <= 1'b0;
|
||||
axi_s_wready <= 1'b0;
|
||||
axi_s_arready <= 1'b0;
|
||||
axi_s_req_addr <= 32'h0;
|
||||
reg_datai_32 <= 32'h0;
|
||||
if(axi_s_bready) axi_s_bvalid <= 1'b0;
|
||||
if(axi_s_rvalid && axi_s_rready)
|
||||
begin
|
||||
reg_datao_32 <= 32'h0;
|
||||
axi_s_rlast <= 1'b0;
|
||||
axi_s_rvalid <= 1'b0;
|
||||
end
|
||||
end
|
||||
end//end if(rst_n)
|
||||
end//end always
|
||||
|
||||
assign csr_rw_send_axi_rsp_done = csr_rw_sm == CSR_RW_SM_SEND_AXI_RSP && axi_s_rlast && axi_s_rready || axi_s_bvalid && axi_s_bready;
|
||||
|
||||
assign axi_s_bid = axi_s_w_id;
|
||||
assign axi_s_rid = axi_s_r_id;
|
||||
assign axi_s_bresp = 2'b00;
|
||||
assign axi_s_rresp = 2'b00;
|
||||
|
||||
assign axi_s_rdata= ( axi_s_rstrb == 2'h0) ? { reg_datao_32 } :
|
||||
( axi_s_rstrb == 2'h1) ? {reg_datao_32[23:0], 8'h0} :
|
||||
( axi_s_rstrb == 2'h2) ? {reg_datao_32[15:0],16'h0} :
|
||||
( axi_s_rstrb == 2'h3) ? {reg_datao_32[7:0], 24'h0} : 32'h0;
|
||||
|
||||
always@(csr_rw_sm or axi_s_awvalid or axi_s_arvalid or axi_s_sel_rd or axi_s_sel_wr or
|
||||
axi_s_wready or csr_rw_send_axi_rsp_done or cpu_grant) begin
|
||||
case(csr_rw_sm)
|
||||
CSR_RW_SM_IDLE:
|
||||
if((axi_s_awvalid || axi_s_arvalid)&&~(axi_s_sel_wr||axi_s_sel_rd)&cpu_grant)
|
||||
csr_rw_sm_nxt = CSR_RW_SM_GET_AXI_ADDR;
|
||||
else
|
||||
csr_rw_sm_nxt = CSR_RW_SM_IDLE;
|
||||
CSR_RW_SM_GET_AXI_ADDR:
|
||||
if(axi_s_sel_wr)
|
||||
csr_rw_sm_nxt = CSR_RW_SM_SEND_AXI_RSP;
|
||||
else if(axi_s_sel_rd)
|
||||
csr_rw_sm_nxt = CSR_RW_SM_SEND_AXI_RSP;
|
||||
else
|
||||
csr_rw_sm_nxt = CSR_RW_SM_GET_AXI_ADDR;
|
||||
CSR_RW_SM_SEND_AXI_RSP:
|
||||
if(csr_rw_send_axi_rsp_done)
|
||||
csr_rw_sm_nxt = CSR_RW_SM_IDLE;
|
||||
else
|
||||
csr_rw_sm_nxt = CSR_RW_SM_SEND_AXI_RSP;
|
||||
default:
|
||||
csr_rw_sm_nxt = CSR_RW_SM_IDLE;
|
||||
endcase
|
||||
end
|
||||
|
||||
always@(posedge clk) begin
|
||||
if(!rst_n)
|
||||
csr_rw_sm <= CSR_RW_SM_IDLE;
|
||||
else
|
||||
csr_rw_sm <= csr_rw_sm_nxt;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
1102
resources/soc/rtl/AMBA/axi_mux.v
Normal file
1102
resources/soc/rtl/AMBA/axi_mux.v
Normal file
File diff suppressed because it is too large
Load Diff
1430
resources/soc/rtl/APB_DEV/NAND/nand.v
Normal file
1430
resources/soc/rtl/APB_DEV/NAND/nand.v
Normal file
File diff suppressed because it is too large
Load Diff
62
resources/soc/rtl/APB_DEV/URT/raminfr.v
Normal file
62
resources/soc/rtl/APB_DEV/URT/raminfr.v
Normal file
@ -0,0 +1,62 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
module raminfr(clk, we, a, dpra, di, dpo);
|
||||
|
||||
parameter addr_width = 4;
|
||||
parameter data_width = 8;
|
||||
parameter depth = 16;
|
||||
|
||||
input clk;
|
||||
input we;
|
||||
input [addr_width-1:0] a;
|
||||
input [addr_width-1:0] dpra;
|
||||
input [data_width-1:0] di;
|
||||
output [data_width-1:0] dpo;
|
||||
reg [data_width-1:0] ram [depth-1:0];
|
||||
|
||||
wire [data_width-1:0] di;
|
||||
wire [addr_width-1:0] a;
|
||||
wire [addr_width-1:0] dpra;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (we)
|
||||
ram[a] <= di;
|
||||
end
|
||||
reg [data_width-1:0] dpo;
|
||||
|
||||
always @(posedge clk)
|
||||
dpo <= ram[dpra];
|
||||
|
||||
endmodule
|
||||
|
119
resources/soc/rtl/APB_DEV/URT/uart_defines.h
Normal file
119
resources/soc/rtl/APB_DEV/URT/uart_defines.h
Normal file
@ -0,0 +1,119 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
`define UART_ADDR_WIDTH 3
|
||||
`define UART_DATA_WIDTH 8
|
||||
|
||||
// Register addresses
|
||||
`define UART_REG_RB `UART_ADDR_WIDTH'd0 // receiver buffer
|
||||
`define UART_REG_TR `UART_ADDR_WIDTH'd0 // transmitter
|
||||
`define UART_REG_IE `UART_ADDR_WIDTH'd1 // Interrupt enable
|
||||
`define UART_REG_II `UART_ADDR_WIDTH'd2 // Interrupt identification
|
||||
`define UART_REG_FC `UART_ADDR_WIDTH'd2 // FIFO control
|
||||
`define UART_REG_LC `UART_ADDR_WIDTH'd3 // Line Control
|
||||
`define UART_REG_MC `UART_ADDR_WIDTH'd4 // Modem control
|
||||
`define UART_REG_LS `UART_ADDR_WIDTH'd5 // Line status
|
||||
`define UART_REG_MS `UART_ADDR_WIDTH'd6 // Modem status
|
||||
`define UART_REG_SR `UART_ADDR_WIDTH'd7 // Scratch register
|
||||
`define UART_REG_DL1 `UART_ADDR_WIDTH'd0 // Divisor latch bytes (1-2)
|
||||
`define UART_REG_DL2 `UART_ADDR_WIDTH'd1
|
||||
|
||||
// Interrupt Enable register bits
|
||||
`define UART_IE_RDA 0 // Received Data available interrupt
|
||||
`define UART_IE_THRE 1 // Transmitter Holding Register empty interrupt
|
||||
`define UART_IE_RLS 2 // Receiver Line Status Interrupt
|
||||
`define UART_IE_MS 3 // Modem Status Interrupt
|
||||
|
||||
// Interrupt Identification register bits
|
||||
`define UART_II_IP 0 // Interrupt pending when 0
|
||||
`define UART_II_II 3:1 // Interrupt identification
|
||||
|
||||
// Interrupt identification values for bits 3:1
|
||||
`define UART_II_RLS 3'b011 // Receiver Line Status
|
||||
`define UART_II_RDA 3'b010 // Receiver Data available
|
||||
`define UART_II_TI 3'b110 // Timeout Indication
|
||||
`define UART_II_THRE 3'b001 // Transmitter Holding Register empty
|
||||
`define UART_II_MS 3'b000 // Modem Status
|
||||
|
||||
// FIFO Control Register bits
|
||||
`define UART_FC_TL 1:0 // Trigger level
|
||||
|
||||
// FIFO trigger level values
|
||||
`define UART_FC_1 2'b00
|
||||
`define UART_FC_4 2'b01
|
||||
`define UART_FC_8 2'b10
|
||||
`define UART_FC_14 2'b11
|
||||
|
||||
// Line Control register bits
|
||||
`define UART_LC_BITS 1:0 // bits in character
|
||||
`define UART_LC_SB 2 // stop bits
|
||||
`define UART_LC_PE 3 // parity enable
|
||||
`define UART_LC_EP 4 // even parity
|
||||
`define UART_LC_SP 5 // stick parity
|
||||
`define UART_LC_BC 6 // Break control
|
||||
`define UART_LC_DL 7 // Divisor Latch access bit
|
||||
|
||||
// Modem Control register bits
|
||||
`define UART_MC_DTR 0
|
||||
`define UART_MC_RTS 1
|
||||
`define UART_MC_OUT1 2
|
||||
`define UART_MC_OUT2 3
|
||||
`define UART_MC_LB 4 // Loopback mode
|
||||
|
||||
// Line Status Register bits
|
||||
`define UART_LS_DR 0 // Data ready
|
||||
`define UART_LS_OE 1 // Overrun Error
|
||||
`define UART_LS_PE 2 // Parity Error
|
||||
`define UART_LS_FE 3 // Framing Error
|
||||
`define UART_LS_BI 4 // Break interrupt
|
||||
`define UART_LS_TFE 5 // Transmit FIFO is empty
|
||||
`define UART_LS_TE 6 // Transmitter Empty indicator
|
||||
`define UART_LS_EI 7 // Error indicator
|
||||
|
||||
// Modem Status Register bits
|
||||
`define UART_MS_DCTS 0 // Delta signals
|
||||
`define UART_MS_DDSR 1
|
||||
`define UART_MS_TERI 2
|
||||
`define UART_MS_DDCD 3
|
||||
`define UART_MS_CCTS 4 // Complement signals
|
||||
`define UART_MS_CDSR 5
|
||||
`define UART_MS_CRI 6
|
||||
`define UART_MS_CDCD 7
|
||||
|
||||
// FIFO parameter defines
|
||||
|
||||
`define UART_FIFO_WIDTH 8
|
||||
`define UART_FIFO_DEPTH 16
|
||||
`define UART_FIFO_POINTER_W 4
|
||||
`define UART_FIFO_COUNTER_W 5
|
||||
`define UART_FIFO_REC_WIDTH 11
|
288
resources/soc/rtl/APB_DEV/URT/uart_receiver.v
Normal file
288
resources/soc/rtl/APB_DEV/URT/uart_receiver.v
Normal file
@ -0,0 +1,288 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
`include "uart_defines.h"
|
||||
|
||||
module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable,
|
||||
counter_t, rf_count, rf_data_out, rf_error_bit,
|
||||
rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
|
||||
|
||||
input clk;
|
||||
input wb_rst_i;
|
||||
input [7:0] lcr;
|
||||
input rf_pop;
|
||||
input srx_pad_i;
|
||||
input enable;
|
||||
input rx_reset;
|
||||
input lsr_mask;
|
||||
|
||||
output [9:0] counter_t;
|
||||
output [`UART_FIFO_COUNTER_W-1:0] rf_count;
|
||||
output [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
|
||||
output rf_overrun;
|
||||
output rf_error_bit;
|
||||
output [3:0] rstate;
|
||||
output rf_push_pulse;
|
||||
|
||||
reg [3:0] rstate;
|
||||
reg [3:0] rcounter16;
|
||||
reg [2:0] rbit_counter;
|
||||
reg [7:0] rshift;
|
||||
reg rparity;
|
||||
reg rparity_error;
|
||||
reg rframing_error;
|
||||
reg rbit_in;
|
||||
reg rparity_xor;
|
||||
reg [7:0] counter_b;
|
||||
reg rf_push_q;
|
||||
|
||||
reg [`UART_FIFO_REC_WIDTH-1:0] rf_data_in;
|
||||
wire[`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
|
||||
wire rf_push_pulse;
|
||||
reg rf_push;
|
||||
wire rf_pop;
|
||||
wire rf_overrun;
|
||||
wire[`UART_FIFO_COUNTER_W-1:0] rf_count;
|
||||
wire rf_error_bit;
|
||||
wire break_error = (counter_b == 0);
|
||||
|
||||
uart_rfifo #(`UART_FIFO_REC_WIDTH) fifo_rx(
|
||||
.clk ( clk ),
|
||||
.wb_rst_i ( wb_rst_i ),
|
||||
.data_in ( rf_data_in ),
|
||||
.data_out ( rf_data_out ),
|
||||
.push ( rf_push_pulse),
|
||||
.pop ( rf_pop ),
|
||||
.overrun ( rf_overrun ),
|
||||
.count ( rf_count ),
|
||||
.error_bit ( rf_error_bit ),
|
||||
.fifo_reset ( rx_reset ),
|
||||
.reset_status( lsr_mask )
|
||||
);
|
||||
|
||||
wire rcounter16_eq_7 = (rcounter16 == 4'd7);
|
||||
wire rcounter16_eq_0 = (rcounter16 == 4'd0);
|
||||
wire rcounter16_eq_1 = (rcounter16 == 4'd1);
|
||||
|
||||
wire [3:0] rcounter16_minus_1 = rcounter16 - 1'b1;
|
||||
|
||||
parameter sr_idle = 4'd0;
|
||||
parameter sr_rec_start = 4'd1;
|
||||
parameter sr_rec_bit = 4'd2;
|
||||
parameter sr_rec_parity = 4'd3;
|
||||
parameter sr_rec_stop = 4'd4;
|
||||
parameter sr_check_parity = 4'd5;
|
||||
parameter sr_rec_prepare = 4'd6;
|
||||
parameter sr_end_bit = 4'd7;
|
||||
parameter sr_ca_lc_parity = 4'd8;
|
||||
parameter sr_wait1 = 4'd9;
|
||||
parameter sr_push = 4'd10;
|
||||
|
||||
|
||||
always @(posedge clk ) begin
|
||||
if (wb_rst_i) begin
|
||||
rstate <= sr_idle;
|
||||
rbit_in <= 1'b0;
|
||||
rcounter16 <= 0;
|
||||
rbit_counter <= 0;
|
||||
rparity_xor <= 1'b0;
|
||||
rframing_error <= 1'b0;
|
||||
rparity_error <= 1'b0;
|
||||
rparity <= 1'b0;
|
||||
rshift <= 0;
|
||||
rf_push <= 1'b0;
|
||||
rf_data_in <= 0;
|
||||
end
|
||||
else if (enable) begin
|
||||
case (rstate)
|
||||
sr_idle : begin
|
||||
rf_push <= 1'b0;
|
||||
rf_data_in <= 0;
|
||||
rcounter16 <= 4'b1110;
|
||||
if (srx_pad_i==1'b0 & ~break_error) begin
|
||||
rstate <= sr_rec_start;
|
||||
end
|
||||
end
|
||||
sr_rec_start : begin
|
||||
rf_push <= 1'b0;
|
||||
if (rcounter16_eq_7)
|
||||
if (srx_pad_i==1'b1)
|
||||
rstate <= sr_idle;
|
||||
else
|
||||
rstate <= sr_rec_prepare;
|
||||
else rstate<=rstate;
|
||||
rcounter16 <= rcounter16_minus_1;
|
||||
end
|
||||
sr_rec_prepare: begin
|
||||
case (lcr[1:0])
|
||||
2'b00 : rbit_counter <= 3'b100;
|
||||
2'b01 : rbit_counter <= 3'b101;
|
||||
2'b10 : rbit_counter <= 3'b110;
|
||||
2'b11 : rbit_counter <= 3'b111;
|
||||
endcase
|
||||
if (rcounter16_eq_0) begin
|
||||
rstate <= sr_rec_bit;
|
||||
rcounter16 <= 4'b1110;
|
||||
rshift <= 0;
|
||||
end
|
||||
else
|
||||
rstate <= sr_rec_prepare;
|
||||
rcounter16 <= rcounter16_minus_1;
|
||||
end
|
||||
sr_rec_bit : begin
|
||||
if (rcounter16_eq_0) rstate <= sr_end_bit;
|
||||
if (rcounter16_eq_7)
|
||||
case (lcr[1:0])
|
||||
2'b00 : rshift[4:0] <= {srx_pad_i, rshift[4:1]};
|
||||
2'b01 : rshift[5:0] <= {srx_pad_i, rshift[5:1]};
|
||||
2'b10 : rshift[6:0] <= {srx_pad_i, rshift[6:1]};
|
||||
2'b11 : rshift[7:0] <= {srx_pad_i, rshift[7:1]};
|
||||
endcase
|
||||
rcounter16 <= rcounter16_minus_1;
|
||||
end
|
||||
sr_end_bit : begin
|
||||
if (rbit_counter==3'b0)
|
||||
if (lcr[`UART_LC_PE])
|
||||
rstate <= sr_rec_parity;
|
||||
else begin
|
||||
rstate <= sr_rec_stop;
|
||||
rparity_error<= 1'b0;
|
||||
end
|
||||
else begin
|
||||
rstate <= sr_rec_bit;
|
||||
rbit_counter <= rbit_counter - 1'b1;
|
||||
end
|
||||
rcounter16 <= 4'b1110;
|
||||
end
|
||||
sr_rec_parity : begin
|
||||
if (rcounter16_eq_7) begin
|
||||
rparity <= srx_pad_i;
|
||||
rstate <= sr_ca_lc_parity;
|
||||
end
|
||||
rcounter16 <= rcounter16_minus_1;
|
||||
end
|
||||
sr_ca_lc_parity:begin
|
||||
rcounter16 <= rcounter16_minus_1;
|
||||
rparity_xor <= ^{rshift,rparity};
|
||||
rstate <= sr_check_parity;
|
||||
end
|
||||
sr_check_parity: begin
|
||||
case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
|
||||
2'b00: rparity_error <= rparity_xor == 0;
|
||||
2'b01: rparity_error <= ~rparity;
|
||||
2'b10: rparity_error <= rparity_xor == 1;
|
||||
2'b11: rparity_error <= rparity;
|
||||
endcase
|
||||
rcounter16 <= rcounter16_minus_1;
|
||||
rstate <= sr_wait1;
|
||||
end
|
||||
sr_wait1 :
|
||||
if (rcounter16_eq_0) begin
|
||||
rstate <= sr_rec_stop;
|
||||
rcounter16 <= 4'b1110;
|
||||
end
|
||||
else rcounter16 <= rcounter16_minus_1;
|
||||
sr_rec_stop : begin
|
||||
if (rcounter16_eq_7) begin
|
||||
rframing_error <= !srx_pad_i;
|
||||
rstate <= sr_push;
|
||||
end
|
||||
rcounter16 <= rcounter16_minus_1;
|
||||
end
|
||||
sr_push : begin
|
||||
if(srx_pad_i | break_error) begin
|
||||
if(break_error)
|
||||
rf_data_in <= {8'b0, 3'b100};
|
||||
else
|
||||
rf_data_in <= {rshift, 1'b0, rparity_error, rframing_error};
|
||||
rf_push <= 1'b1;
|
||||
rstate <= sr_idle;
|
||||
end
|
||||
else if(~rframing_error) begin
|
||||
rf_data_in <= {rshift, 1'b0, rparity_error, rframing_error};
|
||||
rf_push <= 1'b1;
|
||||
rcounter16 <= 4'b1110;
|
||||
rstate <= sr_rec_start;
|
||||
end
|
||||
|
||||
end
|
||||
default : rstate <= sr_idle;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @ (posedge clk ) begin
|
||||
if(wb_rst_i) rf_push_q <= 0;
|
||||
else rf_push_q <= rf_push;
|
||||
end
|
||||
|
||||
assign rf_push_pulse = rf_push & ~rf_push_q;
|
||||
|
||||
|
||||
reg [9:0] toc_value;
|
||||
|
||||
always @(lcr)
|
||||
case (lcr[3:0])
|
||||
4'b0000 : toc_value = 447;
|
||||
4'b0100 : toc_value = 479;
|
||||
4'b0001, 4'b1000 : toc_value = 511;
|
||||
4'b1100 : toc_value = 543;
|
||||
4'b0010, 4'b0101, 4'b1001 : toc_value = 575;
|
||||
4'b0011, 4'b0110, 4'b1010, 4'b1101 : toc_value = 639;
|
||||
4'b0111, 4'b1011, 4'b1110 : toc_value = 703;
|
||||
4'b1111 : toc_value = 767;
|
||||
endcase
|
||||
|
||||
wire [7:0] brc_value;
|
||||
assign brc_value = toc_value[9:2];
|
||||
|
||||
always @(posedge clk ) begin
|
||||
if (wb_rst_i) counter_b <= 8'd159;
|
||||
else if (srx_pad_i) counter_b <= brc_value;
|
||||
else if (enable & counter_b != 8'b0)
|
||||
counter_b <= counter_b - 1;
|
||||
end
|
||||
|
||||
|
||||
reg [9:0] counter_t;
|
||||
|
||||
always @(posedge clk ) begin
|
||||
if (wb_rst_i) counter_t <= 10'd639;
|
||||
else if(rf_push_pulse || rf_pop || rf_count == 0)
|
||||
counter_t <= toc_value;
|
||||
else if (enable && counter_t != 10'b0)
|
||||
counter_t <= counter_t - 1;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
711
resources/soc/rtl/APB_DEV/URT/uart_regs.v
Normal file
711
resources/soc/rtl/APB_DEV/URT/uart_regs.v
Normal file
@ -0,0 +1,711 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
`include "uart_defines.h"
|
||||
|
||||
`define UART_DL1 7:0
|
||||
`define UART_DL2 15:8
|
||||
`define UART_DL3 23:16
|
||||
module uart_regs (clk, rst, clk_carrier,
|
||||
addr, dat_i, dat_o, we, re,
|
||||
|
||||
modem_inputs,
|
||||
rts_pad_o, dtr_pad_o,
|
||||
stx_pad_o,TXD_i,srx_pad_i,RXD_o,
|
||||
int_o,
|
||||
usart_mode,
|
||||
rx_en,
|
||||
tx2rx_en
|
||||
);
|
||||
input clk;
|
||||
input rst ;
|
||||
input clk_carrier;
|
||||
input [2:0] addr;
|
||||
input [7:0] dat_i;
|
||||
output [7:0] dat_o;
|
||||
input we;
|
||||
input re;
|
||||
|
||||
output stx_pad_o;
|
||||
input srx_pad_i;
|
||||
input TXD_i;
|
||||
output RXD_o;
|
||||
|
||||
input [3:0] modem_inputs;
|
||||
output rts_pad_o;
|
||||
output dtr_pad_o;
|
||||
output int_o;
|
||||
|
||||
output usart_mode;
|
||||
output tx2rx_en;
|
||||
output rx_en;
|
||||
|
||||
wire [3:0] modem_inputs;
|
||||
reg enable;
|
||||
|
||||
wire stx_pad_o;
|
||||
wire srx_pad_i;
|
||||
wire srx_pad;
|
||||
|
||||
reg [7:0] dat_o;
|
||||
|
||||
wire [2:0] addr;
|
||||
wire [7:0] dat_i;
|
||||
|
||||
reg [3:0] ier;
|
||||
reg [3:0] iir;
|
||||
reg [1:0] fcr;
|
||||
reg [4:0] mcr;
|
||||
reg infrared;
|
||||
reg rx_pol;
|
||||
reg [7:0] lcr;
|
||||
reg [7:0] msr;
|
||||
reg [23:0] dl;
|
||||
reg start_dlc;
|
||||
reg lsr_mask_d;
|
||||
reg msi_reset;
|
||||
|
||||
reg [15:0] dlc;
|
||||
reg int_o;
|
||||
|
||||
reg [3:0] trigger_level;
|
||||
reg rx_reset;
|
||||
reg tx_reset;
|
||||
wire dlab;
|
||||
|
||||
wire usart_mode;
|
||||
wire usart_rx_en;
|
||||
wire usart_tx_en;
|
||||
wire tx2rx_en;
|
||||
reg sclk_reg;
|
||||
reg sclk_en_reg;
|
||||
reg [7:0] mode_reg;
|
||||
reg [7:0] fi_di_reg;
|
||||
reg [7:0] sclk_count;
|
||||
reg [2:0] repeat_reg;
|
||||
|
||||
wire usart_normal;
|
||||
wire usart_irda;
|
||||
wire usart_t0;
|
||||
wire usart_t1;
|
||||
wire rx_en;
|
||||
wire tx_en;
|
||||
wire sclk_por;
|
||||
|
||||
assign usart_normal = mode_reg[1:0]==2'h0;
|
||||
assign usart_irda = mode_reg[1:0]==2'h1;
|
||||
assign usart_t0 = mode_reg[1:0]==2'h2;
|
||||
assign usart_t1 = mode_reg[1:0]==2'h3;
|
||||
assign usart_tx_en = mode_reg[2]==1'b0;
|
||||
assign usart_rx_en = mode_reg[2]==1'b1;
|
||||
assign sclk_por = mode_reg[3];
|
||||
assign RXD_o = sclk_reg^sclk_por;
|
||||
|
||||
assign usart_mode = usart_t0 || usart_t1;
|
||||
assign rx_en = usart_normal || usart_irda || usart_mode && usart_rx_en;
|
||||
assign tx_en = usart_normal || usart_irda || usart_mode && usart_tx_en;
|
||||
|
||||
|
||||
always @(posedge clk )
|
||||
begin
|
||||
if (rst) begin
|
||||
mode_reg <= 8'h0;
|
||||
fi_di_reg <= 8'h0;
|
||||
repeat_reg<= 3'h4;
|
||||
sclk_en_reg<= 1'b0;
|
||||
end
|
||||
else if (we && addr==`UART_REG_SR)begin
|
||||
if(dlab)
|
||||
fi_di_reg <= dat_i;
|
||||
else
|
||||
mode_reg <= dat_i;
|
||||
end
|
||||
else begin
|
||||
if(enable) sclk_en_reg <= mode_reg[4];
|
||||
repeat_reg <= mode_reg[7:5];
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if(rst) begin
|
||||
sclk_count <= 8'b0;
|
||||
sclk_reg <=1'b0;
|
||||
end
|
||||
else if(usart_mode&&(fi_di_reg>8'h1)&&sclk_en_reg) begin
|
||||
if(sclk_count == fi_di_reg[7:1]) begin
|
||||
sclk_reg <= 1'b1;
|
||||
sclk_count <= sclk_count + 1'b1;
|
||||
end
|
||||
else if(sclk_count == fi_di_reg) begin
|
||||
sclk_reg <= 1'b0;
|
||||
sclk_count <= 8'b0;
|
||||
end
|
||||
else begin
|
||||
sclk_count <= sclk_count + 1'b1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
sclk_reg <=1'b0;
|
||||
sclk_count <= 8'b0;
|
||||
end
|
||||
end
|
||||
|
||||
wire cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i;
|
||||
wire loopback;
|
||||
wire cts, dsr, ri, dcd;
|
||||
wire cts_c, dsr_c, ri_c, dcd_c;
|
||||
wire rts_pad_o, dtr_pad_o;
|
||||
|
||||
wire [7:0] lsr;
|
||||
wire lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7;
|
||||
reg lsr0r, lsr1r, lsr2r, lsr3r, lsr4r, lsr5r, lsr6r, lsr7r;
|
||||
wire lsr_mask;
|
||||
|
||||
assign lsr[7:0] = { lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r };
|
||||
|
||||
assign {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs;
|
||||
assign {cts, dsr, ri, dcd} = ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
|
||||
|
||||
assign {cts_c, dsr_c, ri_c, dcd_c} = loopback ? {mcr[`UART_MC_RTS],mcr[`UART_MC_DTR],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]}
|
||||
: {cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
|
||||
|
||||
assign dlab = lcr[`UART_LC_DL];
|
||||
assign loopback = mcr[4];
|
||||
|
||||
assign rts_pad_o = mcr[`UART_MC_RTS];
|
||||
assign dtr_pad_o = mcr[`UART_MC_DTR];
|
||||
|
||||
wire rls_int;
|
||||
wire rda_int;
|
||||
wire ti_int;
|
||||
wire thre_int;
|
||||
wire ms_int;
|
||||
|
||||
wire tf_push;
|
||||
reg rf_pop;
|
||||
wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
|
||||
wire rf_error_bit;
|
||||
wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
|
||||
wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
|
||||
wire [2:0] tstate;
|
||||
wire [3:0] rstate;
|
||||
wire [9:0] counter_t;
|
||||
|
||||
wire thre_set_en;
|
||||
reg [7:0] block_cnt;
|
||||
reg [7:0] block_value;
|
||||
wire current_finish;
|
||||
wire max_repeat_time;
|
||||
|
||||
wire serial_out;
|
||||
wire serial_out_modulated = ~ (clk_carrier & serial_out);
|
||||
|
||||
uart_transmitter transmitter(.clk(clk), .wb_rst_i(rst), .lcr(lcr), .tf_push(tf_push), .wb_dat_i(dat_i),
|
||||
|
||||
.tx2rx_en (tx2rx_en),
|
||||
.usart_mode(usart_mode),
|
||||
.srx_pad_i(TXD_i),
|
||||
.enable (enable && tx_en),
|
||||
.usart_t0(usart_t0),
|
||||
.repeat_time(repeat_reg ),
|
||||
.current_finish(current_finish),
|
||||
.max_repeat_time(max_repeat_time),
|
||||
|
||||
.stx_pad_o(serial_out), .tstate(tstate), .tf_count(tf_count),
|
||||
.tx_reset(tx_reset), .lsr_mask(lsr_mask));
|
||||
wire rcv_pad_i;
|
||||
assign rcv_pad_i = ~usart_mode ? srx_pad_i : (rx_en ? TXD_i : 1'b1);
|
||||
|
||||
uart_sync_flops i_uart_sync_flops(
|
||||
.rst_i (rst),
|
||||
.clk_i (clk),
|
||||
.stage1_rst_i (1'b0),
|
||||
.stage1_clk_en_i (1'b1),
|
||||
.async_dat_i (rcv_pad_i),
|
||||
.sync_dat_o (srx_pad)
|
||||
);
|
||||
|
||||
defparam i_uart_sync_flops.width = 1;
|
||||
defparam i_uart_sync_flops.init_value = 1'b1;
|
||||
wire serial_in = loopback ? serial_out : rx_pol ? ~srx_pad : srx_pad;
|
||||
assign stx_pad_o = loopback ? 1'b1 : infrared ? serial_out_modulated : serial_out;
|
||||
|
||||
wire rf_overrun;
|
||||
wire rf_push_pulse;
|
||||
uart_receiver receiver(.clk(clk), .wb_rst_i(rst), .lcr(lcr), .rf_pop(rf_pop), .srx_pad_i(serial_in),
|
||||
.enable(enable && rx_en),
|
||||
.counter_t(counter_t), .rf_count(rf_count), .rf_data_out(rf_data_out), .rf_error_bit(rf_error_bit),
|
||||
.rf_overrun(rf_overrun), .rx_reset(rx_reset), .lsr_mask(lsr_mask), .rstate(rstate), .rf_push_pulse(rf_push_pulse));
|
||||
|
||||
|
||||
always @(dl or dlab or ier or iir or fi_di_reg or mode_reg
|
||||
or lcr or lsr or msr or rf_data_out or addr )
|
||||
begin
|
||||
case (addr)
|
||||
`UART_REG_RB : dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3];
|
||||
`UART_REG_IE : dat_o = dlab ? dl[`UART_DL2] : ier;
|
||||
`UART_REG_II : dat_o = dlab ? dl[`UART_DL3] : {4'b1100,iir};
|
||||
`UART_REG_LC : dat_o = lcr;
|
||||
`UART_REG_LS : dat_o = lsr;
|
||||
`UART_REG_MS : dat_o = msr;
|
||||
`UART_REG_SR : dat_o = dlab ? fi_di_reg : mode_reg;
|
||||
default : dat_o = 8'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk )
|
||||
begin
|
||||
if (rst)
|
||||
rf_pop <= 0;
|
||||
else
|
||||
if (rf_pop)
|
||||
rf_pop <= 0;
|
||||
else
|
||||
if (re && addr == `UART_REG_RB && !dlab)
|
||||
rf_pop <= 1;
|
||||
end
|
||||
|
||||
wire lsr_mask_condition;
|
||||
wire iir_read;
|
||||
wire msr_read;
|
||||
wire fifo_read;
|
||||
wire fifo_write;
|
||||
|
||||
assign lsr_mask_condition = (re && addr == `UART_REG_LS && !dlab);
|
||||
assign iir_read = (re && addr == `UART_REG_II && !dlab);
|
||||
assign msr_read = (re && addr == `UART_REG_MS && !dlab);
|
||||
assign fifo_read = (re && addr == `UART_REG_RB && !dlab);
|
||||
assign fifo_write = (we && addr == `UART_REG_TR && !dlab);
|
||||
|
||||
always @(posedge clk )
|
||||
begin
|
||||
if (rst)
|
||||
lsr_mask_d <= 0;
|
||||
else
|
||||
lsr_mask_d <= lsr_mask_condition;
|
||||
end
|
||||
|
||||
assign lsr_mask = lsr_mask_condition && ~lsr_mask_d;
|
||||
|
||||
always @(posedge clk )
|
||||
begin
|
||||
if (rst)
|
||||
msi_reset <= 1;
|
||||
else
|
||||
if (msi_reset)
|
||||
msi_reset <= 0;
|
||||
else
|
||||
if (msr_read)
|
||||
msi_reset <= 1;
|
||||
end
|
||||
|
||||
always @(posedge clk )
|
||||
if (rst)
|
||||
lcr <= 8'b00000011;
|
||||
else
|
||||
if (we && addr==`UART_REG_LC)
|
||||
lcr <= dat_i;
|
||||
|
||||
always @(posedge clk )
|
||||
if (rst)
|
||||
begin
|
||||
ier <= 4'b0000;
|
||||
dl[`UART_DL2] <= 8'b0;
|
||||
end
|
||||
else
|
||||
if (we && addr==`UART_REG_IE)
|
||||
if (dlab)
|
||||
begin
|
||||
dl[`UART_DL2] <= dat_i;
|
||||
end
|
||||
else
|
||||
ier <= dat_i[3:0];
|
||||
else
|
||||
ier<= ier;
|
||||
|
||||
always @(posedge clk )
|
||||
if (rst) begin
|
||||
fcr <= 2'b11;
|
||||
rx_reset <= 0;
|
||||
tx_reset <= 0;
|
||||
dl[`UART_DL3] <= 8'h0;
|
||||
end else
|
||||
if (we && addr==`UART_REG_FC) begin
|
||||
if(dlab) dl[`UART_DL3] <= dat_i;
|
||||
else begin
|
||||
fcr <= dat_i[7:6];
|
||||
rx_reset <= dat_i[1];
|
||||
tx_reset <= dat_i[2];
|
||||
end
|
||||
end else begin
|
||||
rx_reset <= 0;
|
||||
tx_reset <= 0;
|
||||
end
|
||||
|
||||
always @(posedge clk )
|
||||
if (rst) begin
|
||||
mcr <= 5'b0;
|
||||
infrared <= 1'b0;
|
||||
rx_pol <= 1'b0; end
|
||||
else
|
||||
if(we && addr==`UART_REG_MC) begin
|
||||
mcr <= dat_i[4:0];
|
||||
infrared <= dat_i[7];
|
||||
rx_pol <= dat_i[6]; end
|
||||
|
||||
assign tf_push = we & addr==`UART_REG_TR & !dlab;
|
||||
always @(posedge clk )
|
||||
if (rst)
|
||||
begin
|
||||
dl[`UART_DL1] <= 8'b0;
|
||||
start_dlc <= 1'b0;
|
||||
end
|
||||
else
|
||||
if (we && addr==`UART_REG_TR)
|
||||
if (dlab)
|
||||
begin
|
||||
dl[`UART_DL1] <= dat_i;
|
||||
start_dlc <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
start_dlc <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
start_dlc <= 1'b0;
|
||||
end
|
||||
|
||||
always @(fcr)
|
||||
case (fcr[`UART_FC_TL])
|
||||
2'b00 : trigger_level = 1;
|
||||
2'b01 : trigger_level = 4;
|
||||
2'b10 : trigger_level = 8;
|
||||
2'b11 : trigger_level = 14;
|
||||
endcase
|
||||
|
||||
reg [3:0] delayed_modem_signals;
|
||||
always @(posedge clk )
|
||||
begin
|
||||
if (rst)
|
||||
begin
|
||||
msr <= 0;
|
||||
delayed_modem_signals[3:0] <= 0;
|
||||
end
|
||||
else begin
|
||||
msr[`UART_MS_DDCD:`UART_MS_DCTS] <= msi_reset ? 4'b0 :
|
||||
msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ delayed_modem_signals[3:0]);
|
||||
msr[`UART_MS_CDCD:`UART_MS_CCTS] <= {dcd_c, ri_c, dsr_c, cts_c};
|
||||
delayed_modem_signals[3:0] <= {dcd, ri, dsr, cts};
|
||||
end
|
||||
end
|
||||
|
||||
assign lsr0 = (rf_count==0 && rf_push_pulse);
|
||||
assign lsr1 = rf_overrun;
|
||||
assign lsr2 = rf_data_out[1];
|
||||
assign lsr3 = rf_data_out[0];
|
||||
assign lsr4 = rf_data_out[2];
|
||||
assign lsr5 = current_finish && (tf_count==5'b0 && thre_set_en);
|
||||
assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == 3'd0));
|
||||
assign lsr7 = rf_error_bit | rf_overrun;
|
||||
|
||||
reg lsr0_d;
|
||||
|
||||
always @(posedge clk )
|
||||
if (rst) lsr0_d <= 0;
|
||||
else lsr0_d <= lsr0;
|
||||
|
||||
always @(posedge clk )
|
||||
if (rst) lsr0r <= 0;
|
||||
else lsr0r <= (rf_count==1 && rf_pop && !rf_push_pulse || rx_reset) ? 0 :
|
||||
lsr0r || (lsr0 && ~lsr0_d);
|
||||
|
||||
reg lsr1_d;
|
||||
|
||||
always @(posedge clk )
|
||||
if (rst) lsr1_d <= 0;
|
||||
else lsr1_d <= lsr1;
|
||||
|
||||
always @(posedge clk )
|
||||
if (rst) lsr1r <= 0;
|
||||
else lsr1r <= lsr_mask ? 0 : lsr1r || (lsr1 && ~lsr1_d);
|
||||
|
||||
reg lsr2_d;
|
||||
|
||||
always @(posedge clk )
|
||||
if (rst) lsr2_d <= 0;
|
||||
else lsr2_d <= lsr2;
|
||||
|
||||
always @(posedge clk )
|
||||
if (rst) lsr2r <= 0;
|
||||
else lsr2r <= lsr_mask ? 0 : lsr2r || (lsr2 && ~lsr2_d);
|
||||
|
||||
reg lsr3_d;
|
||||
|
||||
always @(posedge clk )
|
||||
if (rst) lsr3_d <= 0;
|
||||
else lsr3_d <= lsr3;
|
||||
|
||||
always @(posedge clk )
|
||||
if (rst) lsr3r <= 0;
|
||||
else lsr3r <= lsr_mask ? 0 : lsr3r || (lsr3 && ~lsr3_d);
|
||||
|
||||
reg lsr4_d;
|
||||
|
||||
always @(posedge clk )
|
||||
if (rst) lsr4_d <= 0;
|
||||
else lsr4_d <= lsr4;
|
||||
|
||||
always @(posedge clk )
|
||||
if (rst) lsr4r <= 0;
|
||||
else lsr4r <= lsr_mask ? 0 : lsr4r || (lsr4 && ~lsr4_d);
|
||||
|
||||
reg lsr5_d;
|
||||
always @(posedge clk )
|
||||
if (rst) lsr5_d <= 1;
|
||||
else lsr5_d <= lsr5;
|
||||
|
||||
always @(posedge clk )
|
||||
if (rst) lsr5r <= 1;
|
||||
else lsr5r <= (fifo_write) ? 0 : lsr5r || (lsr5 && ~lsr5_d);
|
||||
|
||||
reg lsr6_d;
|
||||
|
||||
always @(posedge clk )
|
||||
if (rst) lsr6_d <= 1;
|
||||
else lsr6_d <= lsr6;
|
||||
|
||||
always @(posedge clk )
|
||||
if (rst) lsr6r <= 1;
|
||||
else lsr6r <= (fifo_write) ? 0 : lsr6r || (lsr6 && ~lsr6_d);
|
||||
|
||||
reg lsr7_d;
|
||||
|
||||
always @(posedge clk )
|
||||
if (rst) lsr7_d <= 0;
|
||||
else lsr7_d <= lsr7;
|
||||
|
||||
always @(posedge clk )
|
||||
if (rst) lsr7r <= 0;
|
||||
else lsr7r <= lsr_mask ? 0 : lsr7r || (lsr7 && ~lsr7_d);
|
||||
|
||||
reg [8:0] M_cnt;
|
||||
wire [8:0] M_next = M_cnt + dl[`UART_DL3];
|
||||
wire M_toggle = M_cnt[8] ^ M_next[8];
|
||||
|
||||
always @(posedge clk )
|
||||
begin
|
||||
if (rst) begin
|
||||
dlc <= 0;
|
||||
M_cnt <= 8'h0;
|
||||
end
|
||||
else if (start_dlc | ~ (|dlc)) begin
|
||||
dlc <= dl - 1 + M_toggle;
|
||||
M_cnt <= M_next;
|
||||
end
|
||||
else
|
||||
dlc <= dlc - 1;
|
||||
end
|
||||
|
||||
always @(posedge clk )
|
||||
begin
|
||||
if (rst)
|
||||
enable <= 1'b0;
|
||||
else if (|dl & ~(|dlc))
|
||||
enable <= 1'b1;
|
||||
else
|
||||
enable <= 1'b0;
|
||||
end
|
||||
|
||||
always @(lcr)
|
||||
case (lcr[3:0])
|
||||
4'b0000 : block_value = 95;
|
||||
4'b0100 : block_value = 103;
|
||||
4'b0001, 4'b1000 : block_value = 111;
|
||||
4'b1100 : block_value = 119;
|
||||
4'b0010, 4'b0101, 4'b1001 : block_value = 127;
|
||||
4'b0011, 4'b0110, 4'b1010, 4'b1101 : block_value = 143;
|
||||
4'b0111, 4'b1011, 4'b1110 : block_value = 159;
|
||||
4'b1111 : block_value = 175;
|
||||
endcase
|
||||
|
||||
always @(posedge clk )
|
||||
begin
|
||||
if (rst)
|
||||
block_cnt <= 8'd0;
|
||||
else
|
||||
if(lsr5r & fifo_write)
|
||||
block_cnt <= usart_t0 ? (block_value + 8'h16) : block_value;
|
||||
else
|
||||
if (enable & block_cnt != 8'b0)
|
||||
block_cnt <= block_cnt - 1;
|
||||
end
|
||||
|
||||
assign thre_set_en = ~(|block_cnt);
|
||||
|
||||
assign rls_int = ier[`UART_IE_RLS] && (lsr[`UART_LS_OE] || lsr[`UART_LS_PE] || lsr[`UART_LS_FE] || lsr[`UART_LS_BI]);
|
||||
assign rda_int = ier[`UART_IE_RDA] && (rf_count >= {1'b0,trigger_level});
|
||||
assign thre_int = ier[`UART_IE_THRE]&& lsr[`UART_LS_TFE];
|
||||
assign ms_int = ier[`UART_IE_MS] && (usart_t0 ? max_repeat_time : (| msr[3:0]));
|
||||
assign ti_int = ier[`UART_IE_RDA] && (counter_t == 10'b0) && (|rf_count);
|
||||
|
||||
reg rls_int_d;
|
||||
reg thre_int_d;
|
||||
reg ms_int_d;
|
||||
reg ti_int_d;
|
||||
reg rda_int_d;
|
||||
|
||||
always @(posedge clk )
|
||||
if (rst) rls_int_d <= 0;
|
||||
else rls_int_d <= rls_int;
|
||||
|
||||
always @(posedge clk )
|
||||
if (rst) rda_int_d <= 0;
|
||||
else rda_int_d <= rda_int;
|
||||
|
||||
always @(posedge clk )
|
||||
if (rst) thre_int_d <= 0;
|
||||
else thre_int_d <= thre_int;
|
||||
|
||||
always @(posedge clk )
|
||||
if (rst) ms_int_d <= 0;
|
||||
else ms_int_d <= ms_int;
|
||||
|
||||
always @(posedge clk )
|
||||
if (rst) ti_int_d <= 0;
|
||||
else ti_int_d <= ti_int;
|
||||
|
||||
|
||||
wire rls_int_rise;
|
||||
wire thre_int_rise;
|
||||
wire ms_int_rise;
|
||||
wire ti_int_rise;
|
||||
wire rda_int_rise;
|
||||
|
||||
assign rda_int_rise = rda_int & ~rda_int_d;
|
||||
assign rls_int_rise = rls_int & ~rls_int_d;
|
||||
assign thre_int_rise = thre_int & ~thre_int_d;
|
||||
assign ms_int_rise = ms_int & ~ms_int_d;
|
||||
assign ti_int_rise = ti_int & ~ti_int_d;
|
||||
|
||||
reg rls_int_pnd;
|
||||
reg rda_int_pnd;
|
||||
reg thre_int_pnd;
|
||||
reg ms_int_pnd;
|
||||
reg ti_int_pnd;
|
||||
|
||||
always @(posedge clk )
|
||||
if (rst) rls_int_pnd <= 0;
|
||||
else
|
||||
rls_int_pnd <= lsr_mask ? 0 :
|
||||
rls_int_rise ? 1 :
|
||||
rls_int_pnd && ier[`UART_IE_RLS];
|
||||
|
||||
reg d1_fifo_read;
|
||||
always @( posedge clk ) d1_fifo_read <= fifo_read;
|
||||
|
||||
always @(posedge clk)
|
||||
if (rst) rda_int_pnd <= 0;
|
||||
else rda_int_pnd <= ((rf_count == {1'b0,trigger_level}) && d1_fifo_read) ? 0 :
|
||||
rda_int_rise ? 1 :
|
||||
rda_int_pnd && ier[`UART_IE_RDA];
|
||||
|
||||
always @(posedge clk )
|
||||
if (rst) thre_int_pnd <= 0;
|
||||
else
|
||||
thre_int_pnd <= fifo_write || (iir_read & ~iir[`UART_II_IP] & iir[`UART_II_II] == `UART_II_THRE)? 0 :
|
||||
thre_int_rise ? 1 :
|
||||
thre_int_pnd && ier[`UART_IE_THRE];
|
||||
|
||||
always @(posedge clk )
|
||||
if (rst) ms_int_pnd <= 0;
|
||||
else
|
||||
ms_int_pnd <= msr_read ? 0 : ms_int_rise ? 1 :
|
||||
ms_int_pnd && ier[`UART_IE_MS];
|
||||
|
||||
always @(posedge clk )
|
||||
if (rst) ti_int_pnd <= 0;
|
||||
else
|
||||
ti_int_pnd <= fifo_read ? 0 : ti_int_rise ? 1 :
|
||||
ti_int_pnd && ier[`UART_IE_RDA];
|
||||
|
||||
always @(posedge clk )
|
||||
begin
|
||||
if (rst) int_o <= 1'b0;
|
||||
else int_o <= rls_int_pnd ? ~lsr_mask :
|
||||
rda_int_pnd ? 1 :
|
||||
ti_int_pnd ? ~fifo_read:
|
||||
thre_int_pnd? !(fifo_write & iir_read) :
|
||||
ms_int_pnd ? ~msr_read :
|
||||
0;
|
||||
end
|
||||
|
||||
|
||||
always @(posedge clk )
|
||||
begin
|
||||
if (rst)
|
||||
iir <= 1;
|
||||
else
|
||||
if (rls_int_pnd)
|
||||
begin
|
||||
iir[`UART_II_II] <= `UART_II_RLS;
|
||||
iir[`UART_II_IP] <= 1'b0;
|
||||
end else
|
||||
if (rda_int_pnd)
|
||||
begin
|
||||
iir[`UART_II_II] <= `UART_II_RDA;
|
||||
iir[`UART_II_IP] <= 1'b0;
|
||||
end
|
||||
else if (ti_int_pnd)
|
||||
begin
|
||||
iir[`UART_II_II] <= `UART_II_TI;
|
||||
iir[`UART_II_IP] <= 1'b0;
|
||||
end
|
||||
else if (thre_int_pnd)
|
||||
begin
|
||||
iir[`UART_II_II] <= `UART_II_THRE;
|
||||
iir[`UART_II_IP] <= 1'b0;
|
||||
end
|
||||
else if (ms_int_pnd)
|
||||
begin
|
||||
iir[`UART_II_II] <= `UART_II_MS;
|
||||
iir[`UART_II_IP] <= 1'b0;
|
||||
end else
|
||||
begin
|
||||
iir[`UART_II_II] <= 0;
|
||||
iir[`UART_II_IP] <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
193
resources/soc/rtl/APB_DEV/URT/uart_rfifo.v
Normal file
193
resources/soc/rtl/APB_DEV/URT/uart_rfifo.v
Normal file
@ -0,0 +1,193 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
`include "uart_defines.h"
|
||||
|
||||
module uart_rfifo (clk,
|
||||
wb_rst_i, data_in, data_out,
|
||||
push,
|
||||
pop,
|
||||
overrun,
|
||||
count,
|
||||
error_bit,
|
||||
fifo_reset,
|
||||
reset_status
|
||||
);
|
||||
|
||||
parameter fifo_width = `UART_FIFO_WIDTH;
|
||||
parameter fifo_depth = `UART_FIFO_DEPTH;
|
||||
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
|
||||
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
|
||||
|
||||
input clk;
|
||||
input wb_rst_i;
|
||||
input push;
|
||||
input pop;
|
||||
input [fifo_width-1:0] data_in;
|
||||
input fifo_reset;
|
||||
input reset_status;
|
||||
|
||||
output [fifo_width-1:0] data_out;
|
||||
output overrun;
|
||||
output [fifo_counter_w-1:0] count;
|
||||
output error_bit;
|
||||
|
||||
wire [fifo_width-1:0] data_out;
|
||||
wire [7:0] data8_out;
|
||||
reg [2:0] fifo[fifo_depth-1:0];
|
||||
|
||||
reg [fifo_pointer_w-1:0] top;
|
||||
reg [fifo_pointer_w-1:0] bottom;
|
||||
|
||||
reg [fifo_counter_w-1:0] count;
|
||||
reg overrun;
|
||||
|
||||
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
|
||||
|
||||
raminfr #(fifo_pointer_w,8,fifo_depth) rfifo (.clk(clk),
|
||||
.we(push),
|
||||
.a(top),
|
||||
.dpra(bottom),
|
||||
.di(data_in[fifo_width-1:fifo_width-8]),
|
||||
.dpo(data8_out)
|
||||
);
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (wb_rst_i)
|
||||
begin
|
||||
top <= 0;
|
||||
bottom <= 1'b0;
|
||||
count <= 0;
|
||||
fifo[0] <= 0;
|
||||
fifo[1] <= 0;
|
||||
fifo[2] <= 0;
|
||||
fifo[3] <= 0;
|
||||
fifo[4] <= 0;
|
||||
fifo[5] <= 0;
|
||||
fifo[6] <= 0;
|
||||
fifo[7] <= 0;
|
||||
fifo[8] <= 0;
|
||||
fifo[9] <= 0;
|
||||
fifo[10]<= 0;
|
||||
fifo[11]<= 0;
|
||||
fifo[12]<= 0;
|
||||
fifo[13]<= 0;
|
||||
fifo[14]<= 0;
|
||||
fifo[15]<= 0;
|
||||
end
|
||||
else
|
||||
if (fifo_reset) begin
|
||||
top <= 0;
|
||||
bottom <= 1'b0;
|
||||
count <= 0;
|
||||
fifo[0] <= 0;
|
||||
fifo[1] <= 0;
|
||||
fifo[2] <= 0;
|
||||
fifo[3] <= 0;
|
||||
fifo[4] <= 0;
|
||||
fifo[5] <= 0;
|
||||
fifo[6] <= 0;
|
||||
fifo[7] <= 0;
|
||||
fifo[8] <= 0;
|
||||
fifo[9] <= 0;
|
||||
fifo[10]<= 0;
|
||||
fifo[11]<= 0;
|
||||
fifo[12]<= 0;
|
||||
fifo[13]<= 0;
|
||||
fifo[14]<= 0;
|
||||
fifo[15]<= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
case ({push, pop})
|
||||
2'b10 : if (count<fifo_depth)
|
||||
begin
|
||||
top <= top_plus_1;
|
||||
fifo[top] <= data_in[2:0];
|
||||
count <= count + 1'b1;
|
||||
end
|
||||
2'b01 : if(count>0)
|
||||
begin
|
||||
fifo[bottom] <= 0;
|
||||
bottom <= bottom + 1'b1;
|
||||
count <= count - 1'b1;
|
||||
end
|
||||
2'b11 : begin
|
||||
bottom <= bottom + 1'b1;
|
||||
top <= top_plus_1;
|
||||
fifo[top] <= data_in[2:0];
|
||||
end
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (wb_rst_i)
|
||||
overrun <= 1'b0;
|
||||
else
|
||||
if(fifo_reset | reset_status)
|
||||
overrun <= 1'b0;
|
||||
else
|
||||
if(push & ~pop & (count==fifo_depth))
|
||||
overrun <= 1'b1;
|
||||
end
|
||||
|
||||
assign data_out = {data8_out,fifo[bottom]};
|
||||
|
||||
wire [2:0] word0 = fifo[0];
|
||||
wire [2:0] word1 = fifo[1];
|
||||
wire [2:0] word2 = fifo[2];
|
||||
wire [2:0] word3 = fifo[3];
|
||||
wire [2:0] word4 = fifo[4];
|
||||
wire [2:0] word5 = fifo[5];
|
||||
wire [2:0] word6 = fifo[6];
|
||||
wire [2:0] word7 = fifo[7];
|
||||
|
||||
wire [2:0] word8 = fifo[8];
|
||||
wire [2:0] word9 = fifo[9];
|
||||
wire [2:0] word10 = fifo[10];
|
||||
wire [2:0] word11 = fifo[11];
|
||||
wire [2:0] word12 = fifo[12];
|
||||
wire [2:0] word13 = fifo[13];
|
||||
wire [2:0] word14 = fifo[14];
|
||||
wire [2:0] word15 = fifo[15];
|
||||
|
||||
assign error_bit = |(word0[2:0] | word1[2:0] | word2[2:0] | word3[2:0] |
|
||||
word4[2:0] | word5[2:0] | word6[2:0] | word7[2:0] |
|
||||
word8[2:0] | word9[2:0] | word10[2:0] | word11[2:0] |
|
||||
word12[2:0] | word13[2:0] | word14[2:0] | word15[2:0] );
|
||||
|
||||
endmodule
|
76
resources/soc/rtl/APB_DEV/URT/uart_sync_flops.v
Normal file
76
resources/soc/rtl/APB_DEV/URT/uart_sync_flops.v
Normal file
@ -0,0 +1,76 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
module uart_sync_flops
|
||||
(
|
||||
rst_i,
|
||||
clk_i,
|
||||
stage1_rst_i,
|
||||
stage1_clk_en_i,
|
||||
async_dat_i,
|
||||
sync_dat_o
|
||||
);
|
||||
|
||||
parameter Tp = 1;
|
||||
parameter width = 1;
|
||||
parameter init_value = 1'b0;
|
||||
|
||||
input rst_i;
|
||||
input clk_i;
|
||||
input stage1_rst_i;
|
||||
input stage1_clk_en_i;
|
||||
input [width-1:0] async_dat_i;
|
||||
output [width-1:0] sync_dat_o;
|
||||
|
||||
reg [width-1:0] sync_dat_o;
|
||||
reg [width-1:0] flop_0;
|
||||
|
||||
always @ (posedge clk_i)
|
||||
begin
|
||||
if (rst_i)
|
||||
flop_0 <= {width{init_value}};
|
||||
else
|
||||
flop_0 <= async_dat_i;
|
||||
end
|
||||
|
||||
always @ (posedge clk_i)
|
||||
begin
|
||||
if (rst_i)
|
||||
sync_dat_o <= {width{init_value}};
|
||||
else if (stage1_rst_i)
|
||||
sync_dat_o <= {width{init_value}};
|
||||
else if (stage1_clk_en_i)
|
||||
sync_dat_o <= flop_0;
|
||||
end
|
||||
|
||||
endmodule
|
129
resources/soc/rtl/APB_DEV/URT/uart_tfifo.v
Normal file
129
resources/soc/rtl/APB_DEV/URT/uart_tfifo.v
Normal file
@ -0,0 +1,129 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
`include "uart_defines.h"
|
||||
|
||||
module uart_tfifo (clk,
|
||||
wb_rst_i, data_in, data_out,
|
||||
push,
|
||||
pop,
|
||||
overrun,
|
||||
count,
|
||||
fifo_reset,
|
||||
reset_status
|
||||
);
|
||||
|
||||
parameter fifo_width = `UART_FIFO_WIDTH;
|
||||
parameter fifo_depth = `UART_FIFO_DEPTH;
|
||||
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
|
||||
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
|
||||
|
||||
input clk;
|
||||
input wb_rst_i;
|
||||
input push;
|
||||
input pop;
|
||||
input [fifo_width-1:0] data_in;
|
||||
input fifo_reset;
|
||||
input reset_status;
|
||||
|
||||
output [fifo_width-1:0] data_out;
|
||||
output overrun;
|
||||
output [fifo_counter_w-1:0] count;
|
||||
|
||||
wire [fifo_width-1:0] data_out;
|
||||
|
||||
reg [fifo_pointer_w-1:0] top;
|
||||
reg [fifo_pointer_w-1:0] bottom;
|
||||
|
||||
reg [fifo_counter_w-1:0] count;
|
||||
reg overrun;
|
||||
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
|
||||
|
||||
raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo (.clk(clk),
|
||||
.we(push),
|
||||
.a(top),
|
||||
.dpra(bottom),
|
||||
.di(data_in),
|
||||
.dpo(data_out)
|
||||
);
|
||||
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (wb_rst_i)
|
||||
begin
|
||||
top <= 0;
|
||||
bottom <= 1'b0;
|
||||
count <= 0;
|
||||
end
|
||||
else
|
||||
if (fifo_reset) begin
|
||||
top <= 0;
|
||||
bottom <= 1'b0;
|
||||
count <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
case ({push, pop})
|
||||
2'b10 : if (count<fifo_depth)
|
||||
begin
|
||||
top <= top_plus_1;
|
||||
count <= count + 1'b1;
|
||||
end
|
||||
2'b01 : if(count>0)
|
||||
begin
|
||||
bottom <= bottom + 1'b1;
|
||||
count <= count - 1'b1;
|
||||
end
|
||||
2'b11 : begin
|
||||
bottom <= bottom + 1'b1;
|
||||
top <= top_plus_1;
|
||||
end
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (wb_rst_i)
|
||||
overrun <= 1'b0;
|
||||
else
|
||||
if(fifo_reset | reset_status)
|
||||
overrun <= 1'b0;
|
||||
else
|
||||
if(push & (count==fifo_depth))
|
||||
overrun <= 1'b1;
|
||||
end
|
||||
|
||||
endmodule
|
107
resources/soc/rtl/APB_DEV/URT/uart_top.v
Normal file
107
resources/soc/rtl/APB_DEV/URT/uart_top.v
Normal file
@ -0,0 +1,107 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
`include "uart_defines.h"
|
||||
|
||||
module UART_TOP(
|
||||
PCLK, PRST_,
|
||||
PSEL, PENABLE, PADDR, PWRITE,
|
||||
PWDATA, URT_PRDATA,
|
||||
|
||||
INT, clk_carrier,
|
||||
|
||||
TXD_i, TXD_o, TXD_oe,
|
||||
RXD_i, RXD_o, RXD_oe,
|
||||
|
||||
RTS, CTS, DSR,
|
||||
DCD, DTR, RI
|
||||
);
|
||||
|
||||
input PCLK, PRST_;
|
||||
input PSEL, PENABLE, PWRITE;
|
||||
input [7:0] PADDR;
|
||||
input [7:0] PWDATA;
|
||||
output [7:0] URT_PRDATA;
|
||||
|
||||
output INT;
|
||||
input clk_carrier;
|
||||
|
||||
input TXD_i;
|
||||
output TXD_o;
|
||||
output TXD_oe;
|
||||
input RXD_i;
|
||||
output RXD_o;
|
||||
output RXD_oe;
|
||||
|
||||
output RTS;
|
||||
input CTS, DSR, DCD;
|
||||
output DTR;
|
||||
input RI;
|
||||
|
||||
wire prst = !PRST_;
|
||||
wire we = PSEL & PENABLE & PWRITE;
|
||||
wire re = PSEL & PENABLE & !PWRITE;
|
||||
|
||||
wire rx_en;
|
||||
wire tx2rx_en;
|
||||
wire isomode;
|
||||
|
||||
assign TXD_oe = isomode&&(rx_en||tx2rx_en) ? 1'b1:1'b0;
|
||||
assign RXD_oe =~isomode;
|
||||
|
||||
uart_regs regs(
|
||||
.clk (PCLK ),
|
||||
.rst (prst ),
|
||||
.clk_carrier (clk_carrier),
|
||||
.addr (PADDR[2:0] ),
|
||||
.dat_i (PWDATA ),
|
||||
.dat_o (URT_PRDATA ),
|
||||
.we (we ),
|
||||
.re (re ),
|
||||
|
||||
.modem_inputs({ CTS, DSR, RI, DCD } ),
|
||||
.rts_pad_o (RTS ),
|
||||
.dtr_pad_o (DTR ),
|
||||
.stx_pad_o (TXD_o ),
|
||||
.TXD_i (TXD_i ),
|
||||
.srx_pad_i (RXD_i ),
|
||||
.RXD_o (RXD_o ),
|
||||
.int_o ( INT ),
|
||||
.tx2rx_en (tx2rx_en ),
|
||||
.rx_en (rx_en ),
|
||||
.usart_mode (isomode )
|
||||
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
281
resources/soc/rtl/APB_DEV/URT/uart_transmitter.v
Normal file
281
resources/soc/rtl/APB_DEV/URT/uart_transmitter.v
Normal file
@ -0,0 +1,281 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
`include "uart_defines.h"
|
||||
|
||||
module uart_transmitter (clk, wb_rst_i, lcr, tf_push, wb_dat_i,
|
||||
enable,stx_pad_o, tstate, tf_count, tx_reset, lsr_mask,
|
||||
usart_t0,srx_pad_i,repeat_time,max_repeat_time,current_finish,
|
||||
usart_mode,tx2rx_en);
|
||||
|
||||
input clk;
|
||||
input wb_rst_i;
|
||||
input [7:0] lcr;
|
||||
input tf_push;
|
||||
input [7:0] wb_dat_i;
|
||||
input enable;
|
||||
input tx_reset;
|
||||
input lsr_mask;
|
||||
input usart_mode;
|
||||
input usart_t0,srx_pad_i;
|
||||
input [2:0] repeat_time;
|
||||
output current_finish;
|
||||
output max_repeat_time;
|
||||
|
||||
output tx2rx_en;
|
||||
reg tx2rx_en;
|
||||
output stx_pad_o;
|
||||
output [2:0] tstate;
|
||||
output [`UART_FIFO_COUNTER_W-1:0] tf_count;
|
||||
|
||||
reg [2:0] tstate;
|
||||
reg [4:0] counter;
|
||||
reg [2:0] bit_counter;
|
||||
reg [6:0] shift_out;
|
||||
reg stx_o_tmp;
|
||||
reg parity_xor;
|
||||
reg tf_pop;
|
||||
reg bit_out;
|
||||
reg tx_error;
|
||||
reg [2:0] error_time;
|
||||
|
||||
wire [`UART_FIFO_WIDTH-1:0] tf_data_in;
|
||||
wire [`UART_FIFO_WIDTH-1:0] tf_data_out;
|
||||
wire tf_push;
|
||||
wire tf_overrun;
|
||||
wire [`UART_FIFO_COUNTER_W-1:0]tf_count;
|
||||
|
||||
assign tf_data_in = wb_dat_i;
|
||||
|
||||
uart_tfifo fifo_tx(
|
||||
.clk ( clk ),
|
||||
.wb_rst_i( wb_rst_i ),
|
||||
.data_in ( tf_data_in ),
|
||||
.data_out( tf_data_out ),
|
||||
.push ( tf_push ),
|
||||
.pop ( tf_pop ),
|
||||
.overrun ( tf_overrun ),
|
||||
.count ( tf_count ),
|
||||
.fifo_reset ( tx_reset),
|
||||
.reset_status(lsr_mask )
|
||||
);
|
||||
|
||||
parameter s_idle = 3'd0;
|
||||
parameter s_send_start = 3'd1;
|
||||
parameter s_send_byte = 3'd2;
|
||||
parameter s_send_parity = 3'd3;
|
||||
parameter s_send_stop = 3'd4;
|
||||
parameter s_pop_byte = 3'd5;
|
||||
parameter s_send_guard1 = 3'd6;
|
||||
reg [7:0]tf_data_bak;
|
||||
|
||||
wire max_repeat_time = (error_time==(repeat_time+1'b1)) & usart_mode & usart_t0;
|
||||
|
||||
always @(posedge clk )
|
||||
begin
|
||||
if (wb_rst_i)
|
||||
begin
|
||||
tx_error <= 1'b0;
|
||||
error_time <= 3'b0;
|
||||
tstate <= s_idle;
|
||||
stx_o_tmp <= 1'b1;
|
||||
counter <= 5'b0;
|
||||
shift_out <= 7'b0;
|
||||
bit_out <= 1'b0;
|
||||
parity_xor <= 1'b0;
|
||||
tf_pop <= 1'b0;
|
||||
bit_counter <= 3'b0;
|
||||
tx2rx_en <= 1'b0;
|
||||
tf_data_bak <= 8'h0;
|
||||
end
|
||||
else
|
||||
if (enable)
|
||||
begin
|
||||
case (tstate)
|
||||
s_idle :if ((~|tf_count)&(error_time==(repeat_time+1'b1)||~tx_error||~usart_mode))
|
||||
begin
|
||||
tstate <= s_idle;
|
||||
stx_o_tmp <= 1'b1;
|
||||
tx_error <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
tf_pop <= 1'b0;
|
||||
stx_o_tmp <= 1'b1;
|
||||
tstate <= s_pop_byte;
|
||||
end
|
||||
s_pop_byte : begin
|
||||
|
||||
if(tx_error&(error_time !=(repeat_time+1'b1)))
|
||||
begin
|
||||
tf_pop <= 1'b0;
|
||||
case (lcr[1:0])
|
||||
2'b00 : begin
|
||||
bit_counter <= 3'b100;
|
||||
parity_xor <= ^tf_data_bak[4:0];
|
||||
end
|
||||
2'b01 : begin
|
||||
bit_counter <= 3'b101;
|
||||
parity_xor <= ^tf_data_bak[5:0];
|
||||
end
|
||||
2'b10 : begin
|
||||
bit_counter <= 3'b110;
|
||||
parity_xor <= ^tf_data_bak[6:0];
|
||||
end
|
||||
2'b11 : begin
|
||||
bit_counter <= 3'b111;
|
||||
parity_xor <= ^tf_data_bak[7:0];
|
||||
end
|
||||
endcase
|
||||
{shift_out[6:0], bit_out} <= tf_data_bak;
|
||||
end
|
||||
else begin
|
||||
tf_pop <= 1'b1;
|
||||
error_time <= 3'h0;
|
||||
case (lcr[1:0])
|
||||
2'b00 : begin
|
||||
bit_counter <= 3'b100;
|
||||
parity_xor <= ^tf_data_out[4:0];
|
||||
end
|
||||
2'b01 : begin
|
||||
bit_counter <= 3'b101;
|
||||
parity_xor <= ^tf_data_out[5:0];
|
||||
end
|
||||
2'b10 : begin
|
||||
bit_counter <= 3'b110;
|
||||
parity_xor <= ^tf_data_out[6:0];
|
||||
end
|
||||
2'b11 : begin
|
||||
bit_counter <= 3'b111;
|
||||
parity_xor <= ^tf_data_out[7:0];
|
||||
end
|
||||
endcase
|
||||
{shift_out[6:0], bit_out} <= tf_data_out;
|
||||
tf_data_bak <= tf_data_out;
|
||||
end
|
||||
tstate <= s_send_start;
|
||||
end
|
||||
s_send_start : begin
|
||||
tf_pop <= 1'b0;
|
||||
if (~|counter)
|
||||
counter <= 5'b01111;
|
||||
else if (counter == 5'b00001)
|
||||
begin
|
||||
counter <= 0;
|
||||
tstate <= s_send_byte;
|
||||
end
|
||||
else
|
||||
counter <= counter - 1'b1;
|
||||
stx_o_tmp <= 1'b0;
|
||||
end
|
||||
s_send_byte : begin
|
||||
if (~|counter)
|
||||
counter <= 5'b01111;
|
||||
else if (counter == 5'b00001)
|
||||
begin
|
||||
if (bit_counter > 3'b0) begin
|
||||
bit_counter <= bit_counter - 1'b1;
|
||||
{shift_out[5:0],bit_out } <= {shift_out[6:1], shift_out[0]};
|
||||
tstate <= s_send_byte;
|
||||
end
|
||||
else
|
||||
if (~lcr[`UART_LC_PE]) begin
|
||||
tstate <= s_send_stop;
|
||||
end
|
||||
else begin
|
||||
case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
|
||||
2'b00: bit_out <= ~parity_xor;
|
||||
2'b01: bit_out <= 1'b1;
|
||||
2'b10: bit_out <= parity_xor;
|
||||
2'b11: bit_out <= 1'b0;
|
||||
endcase
|
||||
tstate <= s_send_parity;
|
||||
end
|
||||
counter <= 0;
|
||||
end
|
||||
else counter <= counter - 1'b1;
|
||||
stx_o_tmp <= bit_out;
|
||||
end
|
||||
s_send_parity : begin
|
||||
if (~|counter) counter <= 5'b01111;
|
||||
else if (counter == 5'b00001) begin
|
||||
counter <= 4'b0;
|
||||
tstate <= usart_mode ? s_send_guard1 : s_send_stop;
|
||||
end
|
||||
else counter <= counter - 1'b1;
|
||||
stx_o_tmp <= bit_out;
|
||||
end
|
||||
s_send_stop : begin
|
||||
if (~|counter) begin
|
||||
if(usart_t0)
|
||||
counter <= tx_error ? 5'b11101 : 5'b01101;
|
||||
else
|
||||
casex ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
|
||||
3'b0xx: counter <= 5'b01101;
|
||||
3'b100: counter <= 5'b10101;
|
||||
default: counter <= 5'b11101;
|
||||
endcase
|
||||
end
|
||||
else if (counter == 5'b00001) begin
|
||||
counter <= 5'b0;
|
||||
tx2rx_en<= 1'b0;
|
||||
tstate <= s_idle;
|
||||
end
|
||||
else counter <= counter - 1'b1;
|
||||
stx_o_tmp <= 1'b1;
|
||||
end
|
||||
s_send_guard1:begin
|
||||
if (~|counter) begin
|
||||
tx2rx_en <= 1'b1;
|
||||
counter <= usart_t0 ? 5'b01111:5'b01101;
|
||||
end
|
||||
else if (counter == 5'b00001) begin
|
||||
counter <= 5'b0;
|
||||
tx_error <= !srx_pad_i;
|
||||
error_time<= error_time + !srx_pad_i;
|
||||
tx2rx_en <= usart_t0 ? 1'b1 : 1'b0;
|
||||
tstate <= usart_t0 ? s_send_stop : s_idle;
|
||||
end
|
||||
else counter <= counter - 1'b1;
|
||||
stx_o_tmp <= 1'b1;
|
||||
end
|
||||
default :
|
||||
tstate <= s_idle;
|
||||
endcase
|
||||
end
|
||||
else tf_pop <= 1'b0;
|
||||
end
|
||||
|
||||
assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp;
|
||||
assign current_finish = usart_mode ? ( (tstate==3'b0)&(tx_error & (error_time ==repeat_time+1'b1) |~tx_error) ) : 1'b1;
|
||||
|
||||
endmodule
|
416
resources/soc/rtl/APB_DEV/apb_dev_top.v
Normal file
416
resources/soc/rtl/APB_DEV/apb_dev_top.v
Normal file
@ -0,0 +1,416 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
`include "config.h"
|
||||
|
||||
module axi2apb_misc
|
||||
(
|
||||
clk,
|
||||
rst_n,
|
||||
|
||||
axi_s_awid,
|
||||
axi_s_awaddr,
|
||||
axi_s_awlen,
|
||||
axi_s_awsize,
|
||||
axi_s_awburst,
|
||||
axi_s_awlock,
|
||||
axi_s_awcache,
|
||||
axi_s_awprot,
|
||||
axi_s_awvalid,
|
||||
axi_s_awready,
|
||||
axi_s_wid,
|
||||
axi_s_wdata,
|
||||
axi_s_wstrb,
|
||||
axi_s_wlast,
|
||||
axi_s_wvalid,
|
||||
axi_s_wready,
|
||||
axi_s_bid,
|
||||
axi_s_bresp,
|
||||
axi_s_bvalid,
|
||||
axi_s_bready,
|
||||
axi_s_arid,
|
||||
axi_s_araddr,
|
||||
axi_s_arlen,
|
||||
axi_s_arsize,
|
||||
axi_s_arburst,
|
||||
axi_s_arlock,
|
||||
axi_s_arcache,
|
||||
axi_s_arprot,
|
||||
axi_s_arvalid,
|
||||
axi_s_arready,
|
||||
axi_s_rid,
|
||||
axi_s_rdata,
|
||||
axi_s_rresp,
|
||||
axi_s_rlast,
|
||||
axi_s_rvalid,
|
||||
axi_s_rready,
|
||||
|
||||
apb_rw_dma,
|
||||
apb_psel_dma,
|
||||
apb_enab_dma,
|
||||
apb_addr_dma,
|
||||
apb_valid_dma,
|
||||
apb_wdata_dma,
|
||||
apb_rdata_dma,
|
||||
apb_ready_dma,
|
||||
dma_grant,
|
||||
|
||||
dma_req_o,
|
||||
dma_ack_i,
|
||||
|
||||
uart0_txd_i,
|
||||
uart0_txd_o,
|
||||
uart0_txd_oe,
|
||||
uart0_rxd_i,
|
||||
uart0_rxd_o,
|
||||
uart0_rxd_oe,
|
||||
uart0_rts_o,
|
||||
uart0_dtr_o,
|
||||
uart0_cts_i,
|
||||
uart0_dsr_i,
|
||||
uart0_dcd_i,
|
||||
uart0_ri_i,
|
||||
|
||||
uart0_int,
|
||||
nand_int,
|
||||
|
||||
nand_type,
|
||||
nand_cle ,
|
||||
nand_ale ,
|
||||
nand_rdy ,
|
||||
nand_rd ,
|
||||
nand_ce,
|
||||
nand_wr ,
|
||||
nand_dat_i ,
|
||||
nand_dat_o ,
|
||||
nand_dat_oe
|
||||
);
|
||||
|
||||
parameter ADDR_APB = 20,
|
||||
DATA_APB = 8,
|
||||
L_ADDR = 64,
|
||||
L_ID = 8,
|
||||
L_DATA = 128,
|
||||
L_MASK = 16;
|
||||
|
||||
input clk;
|
||||
input rst_n;
|
||||
|
||||
input [`LID -1 :0] axi_s_awid;
|
||||
input [`Lawaddr -1 :0] axi_s_awaddr;
|
||||
input [`Lawlen -1 :0] axi_s_awlen;
|
||||
input [`Lawsize -1 :0] axi_s_awsize;
|
||||
input [`Lawburst -1 :0] axi_s_awburst;
|
||||
input [`Lawlock -1 :0] axi_s_awlock;
|
||||
input [`Lawcache -1 :0] axi_s_awcache;
|
||||
input [`Lawprot -1 :0] axi_s_awprot;
|
||||
input axi_s_awvalid;
|
||||
output axi_s_awready;
|
||||
input [`LID -1 :0] axi_s_wid;
|
||||
input [`Lwdata -1 :0] axi_s_wdata;
|
||||
input [`Lwstrb -1 :0] axi_s_wstrb;
|
||||
input axi_s_wlast;
|
||||
input axi_s_wvalid;
|
||||
output axi_s_wready;
|
||||
output [`LID -1 :0] axi_s_bid;
|
||||
output [`Lbresp -1 :0] axi_s_bresp;
|
||||
output axi_s_bvalid;
|
||||
input axi_s_bready;
|
||||
input [`LID -1 :0] axi_s_arid;
|
||||
input [`Laraddr -1 :0] axi_s_araddr;
|
||||
input [`Larlen -1 :0] axi_s_arlen;
|
||||
input [`Larsize -1 :0] axi_s_arsize;
|
||||
input [`Larburst -1 :0] axi_s_arburst;
|
||||
input [`Larlock -1 :0] axi_s_arlock;
|
||||
input [`Larcache -1 :0] axi_s_arcache;
|
||||
input [`Larprot -1 :0] axi_s_arprot;
|
||||
input axi_s_arvalid;
|
||||
output axi_s_arready;
|
||||
output [`LID -1 :0] axi_s_rid;
|
||||
output [`Lrdata -1 :0] axi_s_rdata;
|
||||
output [`Lrresp -1 :0] axi_s_rresp;
|
||||
output axi_s_rlast;
|
||||
output axi_s_rvalid;
|
||||
input axi_s_rready;
|
||||
|
||||
output apb_ready_dma;
|
||||
input apb_rw_dma;
|
||||
input apb_psel_dma;
|
||||
input apb_enab_dma;
|
||||
input [ADDR_APB-1:0] apb_addr_dma;
|
||||
input [31:0] apb_wdata_dma;
|
||||
output[31:0] apb_rdata_dma;
|
||||
input apb_valid_dma;
|
||||
output dma_grant;
|
||||
|
||||
output dma_req_o;
|
||||
input dma_ack_i;
|
||||
|
||||
input uart0_txd_i;
|
||||
output uart0_txd_o;
|
||||
output uart0_txd_oe;
|
||||
input uart0_rxd_i;
|
||||
output uart0_rxd_o;
|
||||
output uart0_rxd_oe;
|
||||
output uart0_rts_o;
|
||||
output uart0_dtr_o;
|
||||
input uart0_cts_i;
|
||||
input uart0_dsr_i;
|
||||
input uart0_dcd_i;
|
||||
input uart0_ri_i;
|
||||
|
||||
input [3:0]nand_rdy;
|
||||
output [3:0]nand_ce;
|
||||
output nand_cle;
|
||||
output nand_ale;
|
||||
output nand_rd;
|
||||
output nand_wr;
|
||||
output nand_dat_oe;
|
||||
input [7:0]nand_dat_i ;
|
||||
output [7:0]nand_dat_o ;
|
||||
|
||||
output uart0_int;
|
||||
output nand_int;
|
||||
input [1:0]nand_type;
|
||||
|
||||
wire nand_dma_req_o;
|
||||
assign dma_req_o = nand_dma_req_o;
|
||||
assign nand_dma_ack_i = dma_ack_i;
|
||||
|
||||
wire apb_ready_cpu;
|
||||
wire apb_rw_cpu;
|
||||
wire apb_psel_cpu;
|
||||
wire apb_enab_cpu;
|
||||
wire [ADDR_APB-1 :0] apb_addr_cpu;
|
||||
wire [DATA_APB-1:0] apb_datai_cpu;
|
||||
wire [DATA_APB-1:0] apb_datao_cpu;
|
||||
wire apb_clk_cpu;
|
||||
wire apb_reset_n_cpu;
|
||||
wire apb_word_trans_cpu;
|
||||
wire apb_valid_cpu;
|
||||
wire dma_grant;
|
||||
wire [23:0] apb_high_24b_rd;
|
||||
wire [23:0] apb_high_24b_wr;
|
||||
|
||||
wire apb_rw_dma;
|
||||
wire apb_psel_dma;
|
||||
wire apb_enab_dma;
|
||||
wire [31:0] apb_wdata_dma;
|
||||
wire [31:0] apb_rdata_dma;
|
||||
wire apb_clk_dma;
|
||||
wire apb_reset_n_dma;
|
||||
|
||||
wire apb_uart0_req;
|
||||
wire apb_uart0_ack;
|
||||
wire apb_uart0_rw;
|
||||
wire apb_uart0_enab;
|
||||
wire apb_uart0_psel;
|
||||
wire [ADDR_APB -1:0] apb_uart0_addr;
|
||||
wire [DATA_APB -1:0] apb_uart0_datai;
|
||||
wire [DATA_APB -1:0] apb_uart0_datao;
|
||||
|
||||
wire apb_nand_req;
|
||||
wire apb_nand_ack;
|
||||
wire apb_nand_rw;
|
||||
wire apb_nand_enab;
|
||||
wire apb_nand_psel;
|
||||
wire [ADDR_APB -1:0] apb_nand_addr;
|
||||
wire [31:0] apb_nand_datai;
|
||||
wire [31:0] apb_nand_datao;
|
||||
|
||||
axi2apb_bridge AA_axi2apb_bridge_cpu
|
||||
(
|
||||
.clk (clk ),
|
||||
.rst_n (rst_n ),
|
||||
.axi_s_awid (axi_s_awid ),
|
||||
.axi_s_awaddr (axi_s_awaddr ),
|
||||
.axi_s_awlen (axi_s_awlen ),
|
||||
.axi_s_awsize (axi_s_awsize ),
|
||||
.axi_s_awburst (axi_s_awburst ),
|
||||
.axi_s_awlock (axi_s_awlock ),
|
||||
.axi_s_awcache (axi_s_awcache ),
|
||||
.axi_s_awprot (axi_s_awprot ),
|
||||
.axi_s_awvalid (axi_s_awvalid ),
|
||||
.axi_s_awready (axi_s_awready ),
|
||||
.axi_s_wid (axi_s_wid ),
|
||||
.axi_s_wdata (axi_s_wdata ),
|
||||
.axi_s_wstrb (axi_s_wstrb ),
|
||||
.axi_s_wlast (axi_s_wlast ),
|
||||
.axi_s_wvalid (axi_s_wvalid ),
|
||||
.axi_s_wready (axi_s_wready ),
|
||||
.axi_s_bid (axi_s_bid ),
|
||||
.axi_s_bresp (axi_s_bresp ),
|
||||
.axi_s_bvalid (axi_s_bvalid ),
|
||||
.axi_s_bready (axi_s_bready ),
|
||||
.axi_s_arid (axi_s_arid ),
|
||||
.axi_s_araddr (axi_s_araddr ),
|
||||
.axi_s_arlen (axi_s_arlen ),
|
||||
.axi_s_arsize (axi_s_arsize ),
|
||||
.axi_s_arburst (axi_s_arburst ),
|
||||
.axi_s_arlock (axi_s_arlock ),
|
||||
.axi_s_arcache (axi_s_arcache ),
|
||||
.axi_s_arprot (axi_s_arprot ),
|
||||
.axi_s_arvalid (axi_s_arvalid ),
|
||||
.axi_s_arready (axi_s_arready ),
|
||||
.axi_s_rid (axi_s_rid ),
|
||||
.axi_s_rdata (axi_s_rdata ),
|
||||
.axi_s_rresp (axi_s_rresp ),
|
||||
.axi_s_rlast (axi_s_rlast ),
|
||||
.axi_s_rvalid (axi_s_rvalid ),
|
||||
.axi_s_rready (axi_s_rready ),
|
||||
|
||||
.apb_word_trans (apb_word_trans_cpu ),
|
||||
.apb_high_24b_rd (apb_high_24b_rd ),
|
||||
.apb_high_24b_wr (apb_high_24b_wr ),
|
||||
.apb_valid_cpu (apb_valid_cpu ),
|
||||
.cpu_grant (~dma_grant ),
|
||||
|
||||
.apb_clk (apb_clk_cpu ),
|
||||
.apb_reset_n (apb_reset_n_cpu ),
|
||||
.reg_psel (apb_psel_cpu ),
|
||||
.reg_enable (apb_enab_cpu ),
|
||||
.reg_rw (apb_rw_cpu ),
|
||||
.reg_addr (apb_addr_cpu ),
|
||||
.reg_datai (apb_datai_cpu ),
|
||||
.reg_datao (apb_datao_cpu ),
|
||||
.reg_ready_1 (apb_ready_cpu )
|
||||
);
|
||||
|
||||
apb_mux2 AA_apb_mux16
|
||||
(
|
||||
.clk (clk ),
|
||||
.rst_n (rst_n ),
|
||||
.apb_ready_dma (apb_ready_dma ),
|
||||
.apb_rw_dma (apb_rw_dma ),
|
||||
.apb_addr_dma (apb_addr_dma ),
|
||||
.apb_psel_dma (apb_psel_dma ),
|
||||
.apb_enab_dma (apb_enab_dma ),
|
||||
.apb_wdata_dma (apb_wdata_dma ),
|
||||
.apb_rdata_dma (apb_rdata_dma ),
|
||||
.apb_valid_dma (apb_valid_dma ),
|
||||
.apb_valid_cpu (apb_valid_cpu ),
|
||||
.dma_grant (dma_grant ),
|
||||
|
||||
.apb_ack_cpu (apb_ready_cpu ),
|
||||
.apb_rw_cpu (apb_rw_cpu ),
|
||||
.apb_addr_cpu (apb_addr_cpu ),
|
||||
.apb_psel_cpu (apb_psel_cpu ),
|
||||
.apb_enab_cpu (apb_enab_cpu ),
|
||||
.apb_datai_cpu (apb_datai_cpu ),
|
||||
.apb_datao_cpu (apb_datao_cpu ),
|
||||
.apb_high_24b_rd (apb_high_24b_rd),
|
||||
.apb_high_24b_wr (apb_high_24b_wr),
|
||||
.apb_word_trans_cpu (apb_word_trans_cpu ),
|
||||
|
||||
.apb0_req (apb_uart0_req ),
|
||||
.apb0_ack (apb_uart0_ack ),
|
||||
.apb0_rw (apb_uart0_rw ),
|
||||
.apb0_psel (apb_uart0_psel ),
|
||||
.apb0_enab (apb_uart0_enab ),
|
||||
.apb0_addr (apb_uart0_addr ),
|
||||
.apb0_datai (apb_uart0_datai ),
|
||||
.apb0_datao (apb_uart0_datao ),
|
||||
|
||||
.apb1_req (apb_nand_req ),
|
||||
.apb1_ack (apb_nand_ack ),
|
||||
.apb1_rw (apb_nand_rw ),
|
||||
.apb1_enab (apb_nand_enab ),
|
||||
.apb1_psel (apb_nand_psel ),
|
||||
.apb1_addr (apb_nand_addr ),
|
||||
.apb1_datai (apb_nand_datai ),
|
||||
.apb1_datao (apb_nand_datao )
|
||||
|
||||
);
|
||||
|
||||
//uart0
|
||||
assign apb_uart0_ack = apb_uart0_enab;
|
||||
UART_TOP uart0
|
||||
(
|
||||
.PCLK (clk ),
|
||||
.clk_carrier (1'b0 ),
|
||||
.PRST_ (rst_n ),
|
||||
.PSEL (apb_uart0_psel ),
|
||||
.PENABLE (apb_uart0_enab ),
|
||||
.PADDR (apb_uart0_addr[7:0] ),
|
||||
.PWRITE (apb_uart0_rw ),
|
||||
.PWDATA (apb_uart0_datai ),
|
||||
.URT_PRDATA (apb_uart0_datao ),
|
||||
.INT (uart0_int ),
|
||||
.TXD_o (uart0_txd_o ),
|
||||
.TXD_i (uart0_txd_i ),
|
||||
.TXD_oe (uart0_txd_oe ),
|
||||
.RXD_o (uart0_rxd_o ),
|
||||
.RXD_i (uart0_rxd_i ),
|
||||
.RXD_oe (uart0_rxd_oe ),
|
||||
.RTS (uart0_rts_o ),
|
||||
.CTS (uart0_cts_i ),
|
||||
.DSR (uart0_dsr_i ),
|
||||
.DCD (uart0_dcd_i ),
|
||||
.DTR (uart0_dtr_o ),
|
||||
.RI (uart0_ri_i )
|
||||
);
|
||||
|
||||
//NAND
|
||||
nand_module nand_module
|
||||
(
|
||||
.nand_type (nand_type ),
|
||||
|
||||
.clk (clk ),
|
||||
.rst_n (rst_n ),
|
||||
|
||||
.apb_psel (apb_nand_psel ),
|
||||
.apb_enab (apb_nand_enab ),
|
||||
.apb_rw (apb_nand_rw ),
|
||||
.apb_addr (apb_nand_addr ),
|
||||
.apb_datai (apb_nand_datai ),
|
||||
.apb_datao (apb_nand_datao ),
|
||||
.apb_ack (apb_nand_ack ),
|
||||
|
||||
.nand_dma_req_o (nand_dma_req_o ),
|
||||
.nand_dma_ack_i (nand_dma_ack_i ),
|
||||
|
||||
.nand_ce (nand_ce ),
|
||||
.nand_dat_i (nand_dat_i ),
|
||||
.nand_dat_o (nand_dat_o ),
|
||||
.nand_dat_oe (nand_dat_oe ),
|
||||
.nand_ale (nand_ale ),
|
||||
.nand_cle (nand_cle ),
|
||||
.nand_wr (nand_wr ),
|
||||
.nand_rd (nand_rd ),
|
||||
.nand_rdy (nand_rdy ),
|
||||
.nand_int (nand_int )
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
203
resources/soc/rtl/APB_DEV/apb_mux2.v
Normal file
203
resources/soc/rtl/APB_DEV/apb_mux2.v
Normal file
@ -0,0 +1,203 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
`define APB_DEV0 6'h10
|
||||
`define APB_DEV1 6'h1e
|
||||
module apb_mux2 (
|
||||
clk,
|
||||
rst_n,
|
||||
apb_ack_cpu,
|
||||
apb_rw_cpu,
|
||||
apb_psel_cpu,
|
||||
apb_enab_cpu,
|
||||
apb_addr_cpu,
|
||||
apb_datai_cpu,
|
||||
apb_datao_cpu,
|
||||
apb_high_24b_rd,
|
||||
apb_high_24b_wr,
|
||||
apb_word_trans_cpu,
|
||||
|
||||
apb_ready_dma,
|
||||
apb_rw_dma,
|
||||
apb_psel_dma,
|
||||
apb_enab_dma,
|
||||
apb_addr_dma,
|
||||
apb_wdata_dma,
|
||||
apb_rdata_dma,
|
||||
apb_valid_dma,
|
||||
apb_valid_cpu,
|
||||
dma_grant,
|
||||
|
||||
apb0_req,
|
||||
apb0_ack,
|
||||
apb0_rw,
|
||||
apb0_psel,
|
||||
apb0_enab,
|
||||
apb0_addr,
|
||||
apb0_datai,
|
||||
apb0_datao,
|
||||
|
||||
apb1_req,
|
||||
apb1_ack,
|
||||
apb1_rw,
|
||||
apb1_psel,
|
||||
apb1_enab,
|
||||
apb1_addr,
|
||||
apb1_datai,
|
||||
apb1_datao
|
||||
);
|
||||
|
||||
parameter ADDR_APB = 20,
|
||||
DATA_APB = 8,
|
||||
DATA_APB_32 = 32;
|
||||
input clk,rst_n;
|
||||
output apb_ready_dma;
|
||||
input apb_rw_dma;
|
||||
input apb_psel_dma;
|
||||
input apb_enab_dma;
|
||||
input [ADDR_APB-1:0] apb_addr_dma;
|
||||
input [31:0] apb_wdata_dma;
|
||||
output[31:0] apb_rdata_dma;
|
||||
output dma_grant;
|
||||
input apb_valid_dma;
|
||||
input apb_valid_cpu;
|
||||
|
||||
output apb_ack_cpu;
|
||||
input apb_rw_cpu;
|
||||
input apb_psel_cpu;
|
||||
input apb_enab_cpu;
|
||||
input [ADDR_APB-1:0] apb_addr_cpu;
|
||||
input [DATA_APB-1:0] apb_datai_cpu;
|
||||
output[DATA_APB-1:0] apb_datao_cpu;
|
||||
output [23:0] apb_high_24b_rd;
|
||||
input [23:0] apb_high_24b_wr;
|
||||
|
||||
output apb_word_trans_cpu;
|
||||
output apb0_req;
|
||||
input apb0_ack;
|
||||
output apb0_rw;
|
||||
output apb0_psel;
|
||||
output apb0_enab;
|
||||
output[ADDR_APB-1:0] apb0_addr;
|
||||
output[DATA_APB-1:0] apb0_datai;
|
||||
input [DATA_APB-1:0] apb0_datao;
|
||||
|
||||
output apb1_req;
|
||||
input apb1_ack;
|
||||
output apb1_rw;
|
||||
output apb1_psel;
|
||||
output apb1_enab;
|
||||
output[ADDR_APB-1:0] apb1_addr;
|
||||
output[31:0] apb1_datai;
|
||||
input [31:0] apb1_datao;
|
||||
|
||||
wire apb_ack;
|
||||
wire apb_rw;
|
||||
wire apb_psel;
|
||||
wire apb_enab;
|
||||
wire [ADDR_APB-1:0] apb_addr;
|
||||
wire [DATA_APB-1:0] apb_datai;
|
||||
wire [23:0]high_24b_wr;
|
||||
wire [23:0]high_24b_rd;
|
||||
wire [7:0]apb_datao ;
|
||||
wire dma_grant;
|
||||
|
||||
arb_2_1 arb_2_1(.clk(clk), .rst_n(rst_n), .valid0(apb_valid_cpu), .valid1(apb_valid_dma), .dma_grant(dma_grant));
|
||||
|
||||
assign apb_addr = dma_grant ? apb_addr_dma:apb_addr_cpu;
|
||||
assign apb_rw = dma_grant ? apb_rw_dma:apb_rw_cpu;
|
||||
assign apb_psel = dma_grant ? apb_psel_dma:apb_psel_cpu;
|
||||
assign apb_enab = dma_grant ? apb_enab_dma:apb_enab_cpu;
|
||||
assign apb_datai = dma_grant ? apb_wdata_dma[7:0]:apb_datai_cpu;
|
||||
assign high_24b_wr = dma_grant ? apb_wdata_dma[31:8]:apb_high_24b_wr;
|
||||
assign high_24b_rd = apb1_req ? apb1_datao[31:8] : 24'h0;
|
||||
|
||||
assign apb_word_trans_cpu = dma_grant ? 1'h0: apb1_req;
|
||||
|
||||
assign apb_high_24b_rd = dma_grant ? 24'h0: high_24b_rd;
|
||||
assign apb_datao_cpu = dma_grant ? 8'h0: apb_datao;
|
||||
assign apb_rdata_dma = dma_grant ? {high_24b_rd,apb_datao }:32'h0;
|
||||
assign apb_ack_cpu = ~dma_grant & apb_ack;
|
||||
assign apb_ready_dma = dma_grant & apb_ack;
|
||||
|
||||
assign apb0_req = (apb_addr[ADDR_APB-1:14] ==`APB_DEV0);
|
||||
assign apb1_req = (apb_addr[ADDR_APB-1:14] ==`APB_DEV1);
|
||||
|
||||
assign apb0_psel = apb_psel && apb0_req ;
|
||||
assign apb1_psel = apb_psel && apb1_req;
|
||||
|
||||
assign apb0_enab = apb_enab && apb0_req ;
|
||||
assign apb1_enab = apb_enab && apb1_req;
|
||||
|
||||
assign apb_ack = apb0_req ? apb0_ack :
|
||||
apb1_req ? apb1_ack :
|
||||
1'b0;
|
||||
|
||||
assign apb_datao = apb0_req ? apb0_datao :
|
||||
apb1_req ? apb1_datao[7:0] :
|
||||
8'b0;
|
||||
|
||||
|
||||
|
||||
assign apb0_addr = apb_addr;
|
||||
assign apb0_datai = apb_datai;
|
||||
assign apb0_rw = apb_rw;
|
||||
|
||||
assign apb1_addr = apb_addr;
|
||||
assign apb1_datai = {high_24b_wr,apb_datai};
|
||||
assign apb1_rw = apb_rw;
|
||||
|
||||
endmodule
|
||||
|
||||
module arb_2_1( clk, rst_n, valid0, valid1, dma_grant);
|
||||
input clk;
|
||||
input rst_n;
|
||||
input valid0;
|
||||
input valid1;
|
||||
output dma_grant;
|
||||
reg dma_grant;
|
||||
|
||||
always @(posedge clk)
|
||||
if(~rst_n)
|
||||
dma_grant<= 1'b0;
|
||||
else if(valid0&&~valid1)
|
||||
dma_grant<= 1'b0;
|
||||
else if(valid1&&~valid0)
|
||||
dma_grant<= 1'b1;
|
||||
else if(valid0&&valid1&&~dma_grant)
|
||||
dma_grant<= 1'b0;
|
||||
else if(valid0&&valid1&&dma_grant)
|
||||
dma_grant<= 1'b1;
|
||||
else dma_grant<= 1'b0;
|
||||
|
||||
endmodule
|
140
resources/soc/rtl/APB_DEV/nand_module.v
Normal file
140
resources/soc/rtl/APB_DEV/nand_module.v
Normal file
@ -0,0 +1,140 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
module nand_module
|
||||
(
|
||||
nand_type ,
|
||||
|
||||
clk,
|
||||
rst_n,
|
||||
|
||||
apb_psel,
|
||||
apb_enab,
|
||||
apb_rw,
|
||||
apb_addr,
|
||||
apb_datai,
|
||||
apb_datao,
|
||||
apb_ack,
|
||||
|
||||
nand_dma_req_o,
|
||||
nand_dma_ack_i,
|
||||
|
||||
nand_ce ,
|
||||
nand_dat_i ,
|
||||
nand_dat_o ,
|
||||
nand_dat_oe,
|
||||
nand_ale ,
|
||||
nand_cle ,
|
||||
nand_wr ,
|
||||
nand_rd ,
|
||||
nand_rdy ,
|
||||
|
||||
nand_int
|
||||
|
||||
);
|
||||
input [1:0]nand_type;
|
||||
input clk;
|
||||
input rst_n;
|
||||
input apb_psel;
|
||||
input apb_enab;
|
||||
input apb_rw;
|
||||
input [19:0] apb_addr;
|
||||
input [31:0] apb_datai;
|
||||
output[31:0] apb_datao;
|
||||
output apb_ack;
|
||||
|
||||
output nand_dma_req_o;
|
||||
input nand_dma_ack_i;
|
||||
|
||||
output [3:0] nand_ce;
|
||||
input [7:0] nand_dat_i ;
|
||||
output [7:0] nand_dat_o ;
|
||||
output nand_dat_oe;
|
||||
output nand_ale;
|
||||
output nand_cle;
|
||||
output nand_wr;
|
||||
output nand_rd;
|
||||
input [3:0] nand_rdy;
|
||||
output nand_int;
|
||||
|
||||
wire psel;
|
||||
wire penable;
|
||||
wire [10:0] paddr;
|
||||
wire pwr;
|
||||
assign apb_ack = apb_enab;
|
||||
assign psel = apb_psel;
|
||||
assign penable = apb_enab;
|
||||
assign paddr = apb_addr[10:0];
|
||||
assign pwr = apb_rw;
|
||||
|
||||
reg [3:0] nand_iordy_r0;
|
||||
reg [3:0] nand_iordy_r1;
|
||||
always @(posedge clk) begin
|
||||
nand_iordy_r0 <= nand_rdy;
|
||||
nand_iordy_r1 <= nand_iordy_r0;
|
||||
end
|
||||
reg [1:0] nand_type_r1;
|
||||
reg [1:0] nand_type_r2;
|
||||
|
||||
always @(posedge clk)
|
||||
if(~rst_n)begin
|
||||
nand_type_r1 <= nand_type;
|
||||
nand_type_r2 <= nand_type_r1;
|
||||
end
|
||||
|
||||
NAND_top NAND
|
||||
(
|
||||
.nand_type (nand_type_r2 ),
|
||||
.pclk (clk ),
|
||||
.prst_ (rst_n ),
|
||||
.psel (psel ),
|
||||
.penable (penable ),
|
||||
.pwrite (pwr ),
|
||||
.ADDR (paddr ),
|
||||
.DAT_I (apb_datai ),
|
||||
.DAT_O (apb_datao ),
|
||||
|
||||
.NAND_CE_o (nand_ce ),
|
||||
.NAND_REQ (nand_dma_req_o ),
|
||||
.NAND_I (nand_dat_i ),
|
||||
.NAND_O (nand_dat_o ),
|
||||
.NAND_EN_ (nand_dat_oe ),
|
||||
.NAND_ALE (nand_ale ),
|
||||
.NAND_CLE (nand_cle ),
|
||||
.NAND_RD_ (nand_rd ),
|
||||
.NAND_WR_ (nand_wr ),
|
||||
.NAND_IORDY_i (nand_iordy_r1 ),
|
||||
|
||||
.nand_int (nand_int )
|
||||
);
|
||||
endmodule
|
695
resources/soc/rtl/CONFREG/confreg.v
Normal file
695
resources/soc/rtl/CONFREG/confreg.v
Normal file
@ -0,0 +1,695 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
`define ORDER_REG_ADDR 16'h1160 //32'hbfd0_1160
|
||||
`define LED_ADDR 16'hf000 //32'hbfd0_f000
|
||||
`define LED_RG0_ADDR 16'hf004 //32'hbfd0_f004
|
||||
`define LED_RG1_ADDR 16'hf008 //32'hbfd0_f008
|
||||
`define NUM_ADDR 16'hf010 //32'hbfd0_f010
|
||||
`define SWITCH_ADDR 16'hf020 //32'hbfd0_f020
|
||||
`define BTN_KEY_ADDR 16'hf024 //32'hbfd0_f024
|
||||
`define BTN_STEP_ADDR 16'hf028 //32'hbfd0_f028
|
||||
`define TIMER_ADDR 16'he000 //32'hbfd0_e000
|
||||
module confreg(
|
||||
aclk,
|
||||
aresetn,
|
||||
|
||||
s_awid,
|
||||
s_awaddr,
|
||||
s_awlen,
|
||||
s_awsize,
|
||||
s_awburst,
|
||||
s_awlock,
|
||||
s_awcache,
|
||||
s_awprot,
|
||||
s_awvalid,
|
||||
s_awready,
|
||||
s_wid,
|
||||
s_wdata,
|
||||
s_wstrb,
|
||||
s_wlast,
|
||||
s_wvalid,
|
||||
s_wready,
|
||||
s_bid,
|
||||
s_bresp,
|
||||
s_bvalid,
|
||||
s_bready,
|
||||
s_arid,
|
||||
s_araddr,
|
||||
s_arlen,
|
||||
s_arsize,
|
||||
s_arburst,
|
||||
s_arlock,
|
||||
s_arcache,
|
||||
s_arprot,
|
||||
s_arvalid,
|
||||
s_arready,
|
||||
s_rid,
|
||||
s_rdata,
|
||||
s_rresp,
|
||||
s_rlast,
|
||||
s_rvalid,
|
||||
s_rready,
|
||||
|
||||
order_addr_reg,
|
||||
finish_read_order,
|
||||
write_dma_end,
|
||||
|
||||
cr00,
|
||||
cr01,
|
||||
cr02,
|
||||
cr03,
|
||||
cr04,
|
||||
cr05,
|
||||
cr06,
|
||||
cr07,
|
||||
|
||||
led,
|
||||
led_rg0,
|
||||
led_rg1,
|
||||
num_csn,
|
||||
num_a_g,
|
||||
switch,
|
||||
btn_key_col,
|
||||
btn_key_row,
|
||||
btn_step
|
||||
);
|
||||
input aclk;
|
||||
input aresetn;
|
||||
|
||||
input [3 :0] s_awid;
|
||||
input [31:0] s_awaddr;
|
||||
input [7 :0] s_awlen;
|
||||
input [2 :0] s_awsize;
|
||||
input [1 :0] s_awburst;
|
||||
input s_awlock;
|
||||
input [3 :0] s_awcache;
|
||||
input [2 :0] s_awprot;
|
||||
input s_awvalid;
|
||||
output s_awready;
|
||||
input [3 :0] s_wid;
|
||||
input [31:0] s_wdata;
|
||||
input [3 :0] s_wstrb;
|
||||
input s_wlast;
|
||||
input s_wvalid;
|
||||
output s_wready;
|
||||
output [3 :0] s_bid;
|
||||
output [1 :0] s_bresp;
|
||||
output s_bvalid;
|
||||
input s_bready;
|
||||
input [3 :0] s_arid;
|
||||
input [31:0] s_araddr;
|
||||
input [7 :0] s_arlen;
|
||||
input [2 :0] s_arsize;
|
||||
input [1 :0] s_arburst;
|
||||
input s_arlock;
|
||||
input [3 :0] s_arcache;
|
||||
input [2 :0] s_arprot;
|
||||
input s_arvalid;
|
||||
output s_arready;
|
||||
output [3 :0] s_rid;
|
||||
output [31:0] s_rdata;
|
||||
output [1 :0] s_rresp;
|
||||
output s_rlast;
|
||||
output s_rvalid;
|
||||
input s_rready;
|
||||
|
||||
output reg [31:0] order_addr_reg;
|
||||
input finish_read_order;
|
||||
input write_dma_end;
|
||||
|
||||
output [31:0] cr00;
|
||||
output [31:0] cr01;
|
||||
output [31:0] cr02;
|
||||
output [31:0] cr03;
|
||||
output [31:0] cr04;
|
||||
output [31:0] cr05;
|
||||
output [31:0] cr06;
|
||||
output [31:0] cr07;
|
||||
|
||||
output [15:0] led;
|
||||
output [1 :0] led_rg0;
|
||||
output [1 :0] led_rg1;
|
||||
output reg [7 :0] num_csn;
|
||||
output reg [6 :0] num_a_g;
|
||||
input [7 :0] switch;
|
||||
output [3 :0] btn_key_col;
|
||||
input [3 :0] btn_key_row;
|
||||
input [1 :0] btn_step;
|
||||
|
||||
//
|
||||
reg [31:0] led_data;
|
||||
reg [31:0] led_rg0_data;
|
||||
reg [31:0] led_rg1_data;
|
||||
reg [31:0] num_data;
|
||||
wire [31:0] switch_data;
|
||||
wire [31:0] btn_key_data;
|
||||
wire [31:0] btn_step_data;
|
||||
reg [31:0] timer;
|
||||
|
||||
reg [31:0] cr00,cr01,cr02,cr03,cr04,cr05,cr06,cr07;
|
||||
reg busy,write,R_or_W;
|
||||
reg s_wready;
|
||||
|
||||
wire ar_enter = s_arvalid & s_arready;
|
||||
wire r_retire = s_rvalid & s_rready & s_rlast;
|
||||
wire aw_enter = s_awvalid & s_awready;
|
||||
wire w_enter = s_wvalid & s_wready & s_wlast;
|
||||
wire b_retire = s_bvalid & s_bready;
|
||||
|
||||
wire s_arready = ~busy & (!R_or_W| !s_awvalid);
|
||||
wire s_awready = ~busy & ( R_or_W| !s_arvalid);
|
||||
|
||||
always@(posedge aclk)
|
||||
if(~aresetn) busy <= 1'b0;
|
||||
else if(ar_enter|aw_enter) busy <= 1'b1;
|
||||
else if(r_retire|b_retire) busy <= 1'b0;
|
||||
|
||||
reg [3 :0] buf_id;
|
||||
reg [31:0] buf_addr;
|
||||
reg [7 :0] buf_len;
|
||||
reg [2 :0] buf_size;
|
||||
reg [1 :0] buf_burst;
|
||||
reg buf_lock;
|
||||
reg [3 :0] buf_cache;
|
||||
reg [2 :0] buf_prot;
|
||||
|
||||
always@(posedge aclk)
|
||||
if(~aresetn) begin
|
||||
R_or_W <= 1'b0;
|
||||
buf_id <= 'b0;
|
||||
buf_addr <= 'b0;
|
||||
buf_len <= 'b0;
|
||||
buf_size <= 'b0;
|
||||
buf_burst <= 'b0;
|
||||
buf_lock <= 'b0;
|
||||
buf_cache <= 'b0;
|
||||
buf_prot <= 'b0;
|
||||
end
|
||||
else
|
||||
if(ar_enter | aw_enter) begin
|
||||
R_or_W <= ar_enter;
|
||||
buf_id <= ar_enter ? s_arid : s_awid ;
|
||||
buf_addr <= ar_enter ? s_araddr : s_awaddr ;
|
||||
buf_len <= ar_enter ? s_arlen : s_awlen ;
|
||||
buf_size <= ar_enter ? s_arsize : s_awsize ;
|
||||
buf_burst <= ar_enter ? s_arburst: s_awburst;
|
||||
buf_lock <= ar_enter ? s_arlock : s_awlock ;
|
||||
buf_cache <= ar_enter ? s_arcache: s_awcache;
|
||||
buf_prot <= ar_enter ? s_arprot : s_awprot ;
|
||||
end
|
||||
|
||||
always@(posedge aclk)
|
||||
if(~aresetn) write <= 1'b0;
|
||||
else if(aw_enter) write <= 1'b1;
|
||||
else if(ar_enter) write <= 1'b0;
|
||||
|
||||
always@(posedge aclk)
|
||||
if(~aresetn) s_wready <= 1'b0;
|
||||
else if(aw_enter) s_wready <= 1'b1;
|
||||
else if(w_enter & s_wlast) s_wready <= 1'b0;
|
||||
|
||||
always@(posedge aclk)
|
||||
if(~aresetn) begin
|
||||
cr00 <= 32'd0;
|
||||
cr01 <= 32'd0;
|
||||
cr02 <= 32'd0;
|
||||
cr03 <= 32'd0;
|
||||
cr04 <= 32'd0;
|
||||
cr05 <= 32'd0;
|
||||
cr06 <= 32'd0;
|
||||
cr07 <= 32'd0;
|
||||
end
|
||||
else if(w_enter) begin
|
||||
case (buf_addr[15:2])
|
||||
14'd0: cr00 <= s_wdata;
|
||||
14'd1: cr01 <= s_wdata;
|
||||
14'd2: cr02 <= s_wdata;
|
||||
14'd3: cr03 <= s_wdata;
|
||||
14'd4: cr04 <= s_wdata;
|
||||
14'd5: cr05 <= s_wdata;
|
||||
14'd6: cr06 <= s_wdata;
|
||||
14'd7: cr07 <= s_wdata;
|
||||
endcase
|
||||
end
|
||||
|
||||
reg [31:0] s_rdata;
|
||||
reg s_rvalid,s_rlast;
|
||||
wire [31:0] rdata_d = buf_addr[15:2] == 14'd0 ? cr00 :
|
||||
buf_addr[15:2] == 14'd1 ? cr01 :
|
||||
buf_addr[15:2] == 14'd2 ? cr02 :
|
||||
buf_addr[15:2] == 14'd3 ? cr03 :
|
||||
buf_addr[15:2] == 14'd4 ? cr04 :
|
||||
buf_addr[15:2] == 14'd5 ? cr05 :
|
||||
buf_addr[15:2] == 14'd6 ? cr06 :
|
||||
buf_addr[15:2] == 14'd7 ? cr07 :
|
||||
buf_addr[15:0] == `ORDER_REG_ADDR ? order_addr_reg :
|
||||
buf_addr[15:0] == `LED_ADDR ? led_data :
|
||||
buf_addr[15:0] == `LED_RG0_ADDR ? led_rg0_data :
|
||||
buf_addr[15:0] == `LED_RG1_ADDR ? led_rg1_data :
|
||||
buf_addr[15:0] == `NUM_ADDR ? num_data :
|
||||
buf_addr[15:0] == `SWITCH_ADDR ? switch_data :
|
||||
buf_addr[15:0] == `BTN_KEY_ADDR ? btn_key_data :
|
||||
buf_addr[15:0] == `BTN_STEP_ADDR ? btn_step_data :
|
||||
buf_addr[15:0] == `TIMER_ADDR ? timer : 32'd0;
|
||||
|
||||
always@(posedge aclk)
|
||||
if(~aresetn) begin
|
||||
s_rdata <= 'b0;
|
||||
s_rvalid <= 1'b0;
|
||||
s_rlast <= 1'b0;
|
||||
end
|
||||
else if(busy & !write & !r_retire)
|
||||
begin
|
||||
s_rdata <= rdata_d;
|
||||
s_rvalid <= 1'b1;
|
||||
s_rlast <= 1'b1;
|
||||
end
|
||||
else if(r_retire)
|
||||
begin
|
||||
s_rvalid <= 1'b0;
|
||||
end
|
||||
|
||||
reg s_bvalid;
|
||||
always@(posedge aclk)
|
||||
if(~aresetn) s_bvalid <= 1'b0;
|
||||
else if(w_enter) s_bvalid <= 1'b1;
|
||||
else if(b_retire) s_bvalid <= 1'b0;
|
||||
|
||||
assign s_rid = buf_id;
|
||||
assign s_bid = buf_id;
|
||||
assign s_bresp = 2'b0;
|
||||
assign s_rresp = 2'b0;
|
||||
|
||||
wire write_order_reg = w_enter & (buf_addr[15:0]==`ORDER_REG_ADDR);
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
order_addr_reg <= 32'h0;
|
||||
end
|
||||
else if(write_order_reg)
|
||||
begin
|
||||
order_addr_reg <= s_wdata[31:0];
|
||||
end
|
||||
else if(write_dma_end | finish_read_order)
|
||||
begin
|
||||
order_addr_reg[2] <= write_dma_end ? 1'b0 : order_addr_reg[2];
|
||||
order_addr_reg[3] <= finish_read_order ? 1'b0 : order_addr_reg[3];
|
||||
end
|
||||
end
|
||||
//-------------------------------{timer}begin----------------------------//
|
||||
wire write_timer = w_enter & (buf_addr[15:0]==`TIMER_ADDR);
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
timer <= 32'd0;
|
||||
end
|
||||
else if (write_timer)
|
||||
begin
|
||||
timer <= s_wdata[31:0];
|
||||
end
|
||||
else
|
||||
begin
|
||||
timer <= timer + 1'b1;
|
||||
end
|
||||
end
|
||||
//--------------------------------{timer}end-----------------------------//
|
||||
|
||||
//--------------------------------{led}begin-----------------------------//
|
||||
//led display
|
||||
//led_data[31:0]
|
||||
wire write_led = w_enter & (buf_addr[15:0]==`LED_ADDR);
|
||||
assign led = led_data[15:0];
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
led_data <= 32'h0;
|
||||
end
|
||||
else if(write_led)
|
||||
begin
|
||||
led_data <= s_wdata[31:0];
|
||||
end
|
||||
end
|
||||
//---------------------------------{led}end------------------------------//
|
||||
|
||||
//-------------------------------{switch}begin---------------------------//
|
||||
//switch data
|
||||
//switch_data[7:0]
|
||||
assign switch_data = {24'd0,switch};
|
||||
//--------------------------------{switch}end----------------------------//
|
||||
|
||||
//------------------------------{btn key}begin---------------------------//
|
||||
//btn key data
|
||||
reg [15:0] btn_key_r;
|
||||
assign btn_key_data = {16'd0,btn_key_r};
|
||||
|
||||
//state machine
|
||||
reg [2:0] state;
|
||||
wire [2:0] next_state;
|
||||
|
||||
//eliminate jitter
|
||||
reg key_flag;
|
||||
reg [19:0] key_count;
|
||||
reg [3:0] state_count;
|
||||
wire key_start = (state==3'b000) && !(&btn_key_row);
|
||||
wire key_end = (state==3'b111) && (&btn_key_row);
|
||||
wire key_sample= key_count[19];
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
key_flag <= 1'd0;
|
||||
end
|
||||
else if (key_sample && state_count[3])
|
||||
begin
|
||||
key_flag <= 1'b0;
|
||||
end
|
||||
else if( key_start || key_end )
|
||||
begin
|
||||
key_flag <= 1'b1;
|
||||
end
|
||||
|
||||
if(!aresetn || !key_flag)
|
||||
begin
|
||||
key_count <= 20'd0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
key_count <= key_count + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn || state_count[3])
|
||||
begin
|
||||
state_count <= 4'd0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
state_count <= state_count + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
state <= 3'b000;
|
||||
end
|
||||
else if (state_count[3])
|
||||
begin
|
||||
state <= next_state;
|
||||
end
|
||||
end
|
||||
|
||||
assign next_state = (state == 3'b000) ? ( (key_sample && !(&btn_key_row)) ? 3'b001 : 3'b000 ) :
|
||||
(state == 3'b001) ? ( !(&btn_key_row) ? 3'b111 : 3'b010 ) :
|
||||
(state == 3'b010) ? ( !(&btn_key_row) ? 3'b111 : 3'b011 ) :
|
||||
(state == 3'b011) ? ( !(&btn_key_row) ? 3'b111 : 3'b100 ) :
|
||||
(state == 3'b100) ? ( !(&btn_key_row) ? 3'b111 : 3'b000 ) :
|
||||
(state == 3'b111) ? ( (key_sample && (&btn_key_row)) ? 3'b000 : 3'b111 ) :
|
||||
3'b000;
|
||||
assign btn_key_col = (state == 3'b000) ? 4'b0000:
|
||||
(state == 3'b001) ? 4'b1110:
|
||||
(state == 3'b010) ? 4'b1101:
|
||||
(state == 3'b011) ? 4'b1011:
|
||||
(state == 3'b100) ? 4'b0111:
|
||||
4'b0000;
|
||||
wire [15:0] btn_key_tmp;
|
||||
always @(posedge aclk) begin
|
||||
if(!aresetn) begin
|
||||
btn_key_r <= 16'd0;
|
||||
end
|
||||
else if(next_state==3'b000)
|
||||
begin
|
||||
btn_key_r <=16'd0;
|
||||
end
|
||||
else if(next_state == 3'b111 && state != 3'b111) begin
|
||||
btn_key_r <= btn_key_tmp;
|
||||
end
|
||||
end
|
||||
|
||||
assign btn_key_tmp = (state == 3'b001)&(btn_key_row == 4'b1110) ? 16'h0001:
|
||||
(state == 3'b001)&(btn_key_row == 4'b1101) ? 16'h0010:
|
||||
(state == 3'b001)&(btn_key_row == 4'b1011) ? 16'h0100:
|
||||
(state == 3'b001)&(btn_key_row == 4'b0111) ? 16'h1000:
|
||||
(state == 3'b010)&(btn_key_row == 4'b1110) ? 16'h0002:
|
||||
(state == 3'b010)&(btn_key_row == 4'b1101) ? 16'h0020:
|
||||
(state == 3'b010)&(btn_key_row == 4'b1011) ? 16'h0200:
|
||||
(state == 3'b010)&(btn_key_row == 4'b0111) ? 16'h2000:
|
||||
(state == 3'b011)&(btn_key_row == 4'b1110) ? 16'h0004:
|
||||
(state == 3'b011)&(btn_key_row == 4'b1101) ? 16'h0040:
|
||||
(state == 3'b011)&(btn_key_row == 4'b1011) ? 16'h0400:
|
||||
(state == 3'b011)&(btn_key_row == 4'b0111) ? 16'h4000:
|
||||
(state == 3'b100)&(btn_key_row == 4'b1110) ? 16'h0008:
|
||||
(state == 3'b100)&(btn_key_row == 4'b1101) ? 16'h0080:
|
||||
(state == 3'b100)&(btn_key_row == 4'b1011) ? 16'h0800:
|
||||
(state == 3'b100)&(btn_key_row == 4'b0111) ? 16'h8000:16'h0000;
|
||||
//-------------------------------{btn key}end----------------------------//
|
||||
|
||||
//-----------------------------{btn step}begin---------------------------//
|
||||
//btn step data
|
||||
reg btn_step0_r; //0:press
|
||||
reg btn_step1_r; //0:press
|
||||
assign btn_step_data = {30'd0,~btn_step0_r,~btn_step1_r}; //1:press
|
||||
|
||||
//-----step0
|
||||
//eliminate jitter
|
||||
reg step0_flag;
|
||||
reg [19:0] step0_count;
|
||||
wire step0_start = btn_step0_r && !btn_step[0];
|
||||
wire step0_end = !btn_step0_r && btn_step[0];
|
||||
wire step0_sample= step0_count[19];
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
step0_flag <= 1'd0;
|
||||
end
|
||||
else if (step0_sample)
|
||||
begin
|
||||
step0_flag <= 1'b0;
|
||||
end
|
||||
else if( step0_start || step0_end )
|
||||
begin
|
||||
step0_flag <= 1'b1;
|
||||
end
|
||||
|
||||
if(!aresetn || !step0_flag)
|
||||
begin
|
||||
step0_count <= 20'd0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
step0_count <= step0_count + 1'b1;
|
||||
end
|
||||
|
||||
if(!aresetn)
|
||||
begin
|
||||
btn_step0_r <= 1'b1;
|
||||
end
|
||||
else if(step0_sample)
|
||||
begin
|
||||
btn_step0_r <= btn_step[0];
|
||||
end
|
||||
end
|
||||
|
||||
//-----step1
|
||||
//eliminate jitter
|
||||
reg step1_flag;
|
||||
reg [19:0] step1_count;
|
||||
wire step1_start = btn_step1_r && !btn_step[1];
|
||||
wire step1_end = !btn_step1_r && btn_step[1];
|
||||
wire step1_sample= step1_count[19];
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
step1_flag <= 1'd0;
|
||||
end
|
||||
else if (step1_sample)
|
||||
begin
|
||||
step1_flag <= 1'b0;
|
||||
end
|
||||
else if( step1_start || step1_end )
|
||||
begin
|
||||
step1_flag <= 1'b1;
|
||||
end
|
||||
|
||||
if(!aresetn || !step1_flag)
|
||||
begin
|
||||
step1_count <= 20'd0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
step1_count <= step1_count + 1'b1;
|
||||
end
|
||||
|
||||
if(!aresetn)
|
||||
begin
|
||||
btn_step1_r <= 1'b1;
|
||||
end
|
||||
else if(step1_sample)
|
||||
begin
|
||||
btn_step1_r <= btn_step[1];
|
||||
end
|
||||
end
|
||||
//------------------------------{btn step}end----------------------------//
|
||||
|
||||
//-------------------------------{led rg}begin---------------------------//
|
||||
//led_rg0_data[31:0] led_rg0_data[31:0]
|
||||
//bfd0_f010 bfd0_f014
|
||||
wire write_led_rg0 = w_enter & (buf_addr[15:0]==`LED_RG0_ADDR);
|
||||
wire write_led_rg1 = w_enter & (buf_addr[15:0]==`LED_RG1_ADDR);
|
||||
assign led_rg0 = led_rg0_data[1:0];
|
||||
assign led_rg1 = led_rg1_data[1:0];
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
led_rg0_data <= 32'h0;
|
||||
end
|
||||
else if(write_led_rg0)
|
||||
begin
|
||||
led_rg0_data <= s_wdata[31:0];
|
||||
end
|
||||
|
||||
if(!aresetn)
|
||||
begin
|
||||
led_rg1_data <= 32'h0;
|
||||
end
|
||||
else if(write_led_rg1)
|
||||
begin
|
||||
led_rg1_data <= s_wdata[31:0];
|
||||
end
|
||||
end
|
||||
//--------------------------------{led rg}end----------------------------//
|
||||
|
||||
//---------------------------{digital number}begin-----------------------//
|
||||
//digital number display
|
||||
//num_data[31:0]
|
||||
wire write_num = w_enter & (buf_addr[15:0]==`NUM_ADDR);
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
num_data <= 32'h0;
|
||||
end
|
||||
else if(write_num)
|
||||
begin
|
||||
num_data <= s_wdata[31:0];
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
reg [19:0] count;
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
count <= 20'd0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
count <= count + 1'b1;
|
||||
end
|
||||
end
|
||||
//scan data
|
||||
reg [3:0] scan_data;
|
||||
always @ ( posedge aclk )
|
||||
begin
|
||||
if ( !aresetn )
|
||||
begin
|
||||
scan_data <= 32'd0;
|
||||
num_csn <= 8'b1111_1111;
|
||||
end
|
||||
else
|
||||
begin
|
||||
case(count[19:17])
|
||||
3'b000 : scan_data <= num_data[31:28];
|
||||
3'b001 : scan_data <= num_data[27:24];
|
||||
3'b010 : scan_data <= num_data[23:20];
|
||||
3'b011 : scan_data <= num_data[19:16];
|
||||
3'b100 : scan_data <= num_data[15:12];
|
||||
3'b101 : scan_data <= num_data[11: 8];
|
||||
3'b110 : scan_data <= num_data[7 : 4];
|
||||
3'b111 : scan_data <= num_data[3 : 0];
|
||||
endcase
|
||||
|
||||
case(count[19:17])
|
||||
3'b000 : num_csn <= 8'b0111_1111;
|
||||
3'b001 : num_csn <= 8'b1011_1111;
|
||||
3'b010 : num_csn <= 8'b1101_1111;
|
||||
3'b011 : num_csn <= 8'b1110_1111;
|
||||
3'b100 : num_csn <= 8'b1111_0111;
|
||||
3'b101 : num_csn <= 8'b1111_1011;
|
||||
3'b110 : num_csn <= 8'b1111_1101;
|
||||
3'b111 : num_csn <= 8'b1111_1110;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if ( !aresetn )
|
||||
begin
|
||||
num_a_g <= 7'b0000000;
|
||||
end
|
||||
else
|
||||
begin
|
||||
case ( scan_data )
|
||||
4'd0 : num_a_g <= 7'b1111110; //0
|
||||
4'd1 : num_a_g <= 7'b0110000; //1
|
||||
4'd2 : num_a_g <= 7'b1101101; //2
|
||||
4'd3 : num_a_g <= 7'b1111001; //3
|
||||
4'd4 : num_a_g <= 7'b0110011; //4
|
||||
4'd5 : num_a_g <= 7'b1011011; //5
|
||||
4'd6 : num_a_g <= 7'b1011111; //6
|
||||
4'd7 : num_a_g <= 7'b1110000; //7
|
||||
4'd8 : num_a_g <= 7'b1111111; //8
|
||||
4'd9 : num_a_g <= 7'b1111011; //9
|
||||
4'd10: num_a_g <= 7'b1110111; //a
|
||||
4'd11: num_a_g <= 7'b0011111; //b
|
||||
4'd12: num_a_g <= 7'b1001110; //c
|
||||
4'd13: num_a_g <= 7'b0111101; //d
|
||||
4'd14: num_a_g <= 7'b1001111; //e
|
||||
4'd15: num_a_g <= 7'b1000111; //f
|
||||
endcase
|
||||
end
|
||||
end
|
||||
//----------------------------{digital number}end------------------------//
|
||||
endmodule
|
778
resources/soc/rtl/DMA/dma.v
Normal file
778
resources/soc/rtl/DMA/dma.v
Normal file
@ -0,0 +1,778 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
`define DMA_ORDERSIZE 32
|
||||
`define DMA_WORDSIZE 32
|
||||
`include "config.h"
|
||||
`define WRITE_LENGTH 16
|
||||
`define READ_LENGTH 16
|
||||
module dma_master(
|
||||
clk,
|
||||
rst_n,
|
||||
arid, araddr, arlen ,arsize, arburst, arlock, arcache, arprot, arvalid, arready,
|
||||
rid , rdata , rresp ,rlast , rvalid , rready,
|
||||
awid, awaddr, awlen ,awsize, awburst, awlock, awcache, awprot, awvalid, awready,
|
||||
wid , wdata , wstrb ,wlast , wvalid , wready,
|
||||
bid , bresp , bvalid,bready,
|
||||
dma_int, order_addr_in,dma_req_in,dma_ack_out,
|
||||
finish_read_order, write_dma_end,dma_gnt,
|
||||
apb_valid_req,apb_psel, apb_penable, apb_rw, apb_addr,apb_rdata,apb_wdata
|
||||
);
|
||||
input clk;
|
||||
input rst_n;
|
||||
input dma_gnt;
|
||||
|
||||
output [`LID -1 :0] awid;
|
||||
output [`Lawaddr -1 :0] awaddr;
|
||||
output [`Lawlen -1 :0] awlen;
|
||||
output [`Lawsize -1 :0] awsize;
|
||||
output [`Lawburst -1 :0] awburst;
|
||||
output [`Lawlock -1 :0] awlock;
|
||||
output [`Lawcache -1 :0] awcache;
|
||||
output [`Lawprot -1 :0] awprot;
|
||||
output awvalid;
|
||||
input awready;
|
||||
output [`LID -1 :0] wid;
|
||||
output [64 -1 :0] wdata;
|
||||
output [8 -1 :0] wstrb;
|
||||
output wlast;
|
||||
output wvalid;
|
||||
input wready;
|
||||
input [`LID -1 :0] bid;
|
||||
input [`Lbresp -1 :0] bresp;
|
||||
input bvalid;
|
||||
output bready;
|
||||
output [`LID -1 :0] arid;
|
||||
output [`Laraddr -1 :0] araddr;
|
||||
output [`Larlen -1 :0] arlen;
|
||||
output [`Larsize -1 :0] arsize;
|
||||
output [`Larburst -1 :0] arburst;
|
||||
output [`Larlock -1 :0] arlock;
|
||||
output [`Larcache -1 :0] arcache;
|
||||
output [`Larprot -1 :0] arprot;
|
||||
output arvalid;
|
||||
input arready;
|
||||
input [`LID -1 :0] rid;
|
||||
input [64 -1 :0] rdata;
|
||||
input [`Lrresp -1 :0] rresp;
|
||||
input rlast;
|
||||
input rvalid;
|
||||
output rready;
|
||||
|
||||
output dma_int;
|
||||
output dma_ack_out;
|
||||
input [31:0] order_addr_in;
|
||||
input dma_req_in;
|
||||
output finish_read_order;
|
||||
output write_dma_end;
|
||||
|
||||
output apb_psel;
|
||||
output apb_valid_req;
|
||||
output apb_penable;
|
||||
output apb_rw;
|
||||
output [31:0] apb_addr;
|
||||
input [31:0] apb_rdata;
|
||||
output [31:0] apb_wdata;
|
||||
|
||||
wire read_idle;
|
||||
wire read_ready;
|
||||
wire get_order;
|
||||
wire read_order;
|
||||
wire finish_read_order;
|
||||
wire r_ddr_wait;
|
||||
wire read_ddr;
|
||||
wire read_ddr_end;
|
||||
wire read_dev;
|
||||
wire read_dev_end;
|
||||
wire read_step_end;
|
||||
wire write_idle;
|
||||
wire write_ready;
|
||||
wire w_ddr_wait;
|
||||
wire write_ddr;
|
||||
wire write_ddr_end;
|
||||
wire w_dma_wait;
|
||||
wire write_dma;
|
||||
wire write_dma_end ;
|
||||
wire write_step_end;
|
||||
wire rresp_ok = (rresp==2'h0);
|
||||
wire bresp_ok = (bresp==2'h0);
|
||||
|
||||
wire dma_start;
|
||||
wire dma_stop;
|
||||
wire ask_valid;
|
||||
wire [31:0] ask_addr;
|
||||
wire [ 1:0] device_num_tmp;
|
||||
assign device_num_tmp = order_addr_in[1:0];
|
||||
assign ask_valid = order_addr_in[2] ;
|
||||
assign dma_start = order_addr_in[3] ;
|
||||
assign dma_stop = order_addr_in[4] &
|
||||
(read_ddr_end | read_dev_end | read_step_end | read_idle ) &
|
||||
(write_ddr_end | write_dma_end | write_step_end | write_idle);
|
||||
assign ask_addr = {order_addr_in[31:5], 5'h0};
|
||||
|
||||
reg [ 3:0] dma_read_state;
|
||||
reg [ 3:0] dma_write_state;
|
||||
reg [31:0] count_length;
|
||||
reg [ 4:0] count_fifo_r;
|
||||
reg [ 4:0] count_fifo_w;
|
||||
reg [ 5:0] count_fifo;
|
||||
reg [31:0] mem [31:0];
|
||||
reg dma_r_w;
|
||||
reg [31:0] dma_order_addr;
|
||||
reg [31:0] dma_mem_addr;
|
||||
reg [31:0] dma_dev_addr;
|
||||
reg [31:0] dma_length;
|
||||
reg [31:0] dma_step_length;
|
||||
reg [31:0] dma_step_times;
|
||||
reg [31:0] dma_state_reg;
|
||||
reg dma_get_order;
|
||||
|
||||
wire [31:0]mem0 = mem[0];
|
||||
wire [31:0]mem1 = mem[1];
|
||||
wire [31:0]mem2 = mem[2];
|
||||
wire [31:0]mem3 = mem[3];
|
||||
wire [31:0]mem4 = mem[4];
|
||||
wire [31:0]mem5 = mem[5];
|
||||
wire [31:0]mem6 = mem[6];
|
||||
wire [31:0]mem7 = mem[7];
|
||||
wire [31:0]mem8 = mem[8];
|
||||
wire [31:0]mem9 = mem[9];
|
||||
wire [31:0]mem10 = mem[10];
|
||||
wire [31:0]mem11 = mem[11];
|
||||
wire [31:0]mem12 = mem[12];
|
||||
wire [31:0]mem13 = mem[13];
|
||||
wire [31:0]mem14 = mem[14];
|
||||
wire [31:0]mem15 = mem[15];
|
||||
wire [31:0]mem16 = mem[16];
|
||||
wire [31:0]mem17 = mem[17];
|
||||
wire [31:0]mem18 = mem[18];
|
||||
wire [31:0]mem19 = mem[19];
|
||||
wire [31:0]mem20 = mem[20];
|
||||
wire [31:0]mem21 = mem[21];
|
||||
wire [31:0]mem22 = mem[22];
|
||||
wire [31:0]mem23 = mem[23];
|
||||
wire [31:0]mem24 = mem[24];
|
||||
wire [31:0]mem25 = mem[25];
|
||||
wire [31:0]mem26 = mem[26];
|
||||
wire [31:0]mem27 = mem[27];
|
||||
wire [31:0]mem28 = mem[28];
|
||||
wire [31:0]mem29 = mem[29];
|
||||
wire [31:0]mem30 = mem[30];
|
||||
wire [31:0]mem31 = mem[31];
|
||||
|
||||
wire dma_order_en;
|
||||
wire[ 3:0] dma_next_read_state;
|
||||
wire[ 3:0] dma_next_write_state;
|
||||
wire[31:0] count_obj;
|
||||
wire dma_single_trans_over;
|
||||
wire dma_trans_over;
|
||||
wire dma_state_change_en;
|
||||
wire dma_int_mask;
|
||||
|
||||
assign dma_int_mask = dma_state_reg[0];
|
||||
assign dma_int = dma_state_reg[1];
|
||||
assign dma_order_en = dma_order_addr[0];
|
||||
|
||||
reg dma_req_in_reg_1, dma_req_in_reg_2;
|
||||
reg dma_req_r;
|
||||
reg dma_req;
|
||||
always @(posedge clk)begin
|
||||
if (~rst_n) begin
|
||||
dma_req_in_reg_1 <= 1'b0;
|
||||
dma_req_in_reg_2 <= 1'b0;
|
||||
end else begin
|
||||
dma_req_in_reg_1 <= dma_req_in;
|
||||
dma_req_in_reg_2 <= dma_req_in_reg_1;
|
||||
end
|
||||
end
|
||||
always @(posedge clk)begin
|
||||
if (~rst_n)
|
||||
dma_req_r <= 1'b0;
|
||||
else
|
||||
dma_req_r <= dma_req_in_reg_2;
|
||||
end
|
||||
always @(posedge clk)begin
|
||||
if (~rst_n)
|
||||
dma_req <= 1'b0;
|
||||
else if (dma_ack_out | !dma_req_in_reg_2)
|
||||
dma_req <= 1'b0;
|
||||
else if (~dma_req_r & dma_req_in_reg_2)
|
||||
dma_req <= 1'b1;
|
||||
end
|
||||
|
||||
parameter READ_IDLE = 4'h0;
|
||||
parameter READ_READY = 4'h1;
|
||||
parameter GET_ORDER = 4'h2;
|
||||
parameter READ_ORDER = 4'h3;
|
||||
parameter FINISH_READ_ORDER = 4'h4;
|
||||
parameter R_DDR_WAIT = 4'h5;
|
||||
parameter READ_DDR = 4'h6;
|
||||
parameter READ_DDR_END = 4'h7;
|
||||
parameter READ_DEV = 4'h8;
|
||||
parameter READ_DEV_END = 4'h9;
|
||||
parameter READ_STEP_END = 4'ha;
|
||||
|
||||
assign read_idle = dma_read_state==READ_IDLE;
|
||||
assign read_ready = dma_read_state==READ_READY;
|
||||
assign get_order = dma_read_state==GET_ORDER;
|
||||
assign read_order = dma_read_state==READ_ORDER;
|
||||
assign finish_read_order = dma_read_state==FINISH_READ_ORDER;
|
||||
assign r_ddr_wait = dma_read_state==R_DDR_WAIT;
|
||||
assign read_ddr = dma_read_state==READ_DDR;
|
||||
assign read_ddr_end = dma_read_state==READ_DDR_END;
|
||||
assign read_dev = dma_read_state==READ_DEV;
|
||||
assign read_dev_end = dma_read_state==READ_DEV_END;
|
||||
assign read_step_end = dma_read_state==READ_STEP_END;
|
||||
|
||||
assign dma_single_trans_over = (write_step_end | read_step_end & (count_fifo==0)) & (count_length==32'b0) & (dma_step_times==32'b1) ? 1'b1 : 1'b0;
|
||||
assign dma_trans_over = dma_single_trans_over & !dma_order_en;
|
||||
reg dma_trans_over_reg;
|
||||
always @(posedge clk)begin
|
||||
if(!rst_n)
|
||||
dma_trans_over_reg <= 1'b0;
|
||||
else if(dma_trans_over)
|
||||
dma_trans_over_reg <= 1'b1;
|
||||
else if((read_idle & write_idle) & dma_start)
|
||||
dma_trans_over_reg <= 1'b0;
|
||||
end
|
||||
|
||||
wire [5:0] num_fifo;
|
||||
wire read_ddr_again = !dma_get_order & dma_r_w & (count_fifo <= `READ_LENGTH) & (count_length!=0) & (num_fifo >6'h0);
|
||||
wire read_dev_again = !dma_get_order & !dma_r_w & dma_req & (count_fifo < 6'h20);
|
||||
|
||||
assign dma_next_read_state = read_idle ? (dma_start ? READ_READY : READ_IDLE) :
|
||||
read_ready ? (dma_get_order ? GET_ORDER : read_ddr_again ? R_DDR_WAIT : read_dev_again ? READ_DEV : READ_READY) :
|
||||
get_order ? (arready ? READ_ORDER : GET_ORDER) :
|
||||
read_order ? (rvalid & rlast & rready & rresp_ok ? FINISH_READ_ORDER : READ_ORDER) :
|
||||
finish_read_order ? READ_READY :
|
||||
r_ddr_wait ? (arready ? READ_DDR : R_DDR_WAIT) :
|
||||
read_ddr ? (rvalid & rready & rlast & rresp_ok ? READ_DDR_END : READ_DDR) :
|
||||
read_ddr_end ? ((count_length==0) ? READ_STEP_END : read_ddr_again ? R_DDR_WAIT : READ_DDR_END) :
|
||||
read_step_end ? ((dma_trans_over | dma_stop) ? READ_IDLE : dma_get_order ? GET_ORDER : read_ddr_again ? R_DDR_WAIT : READ_STEP_END) :
|
||||
read_dev ? ((dma_trans_over | dma_stop) ? READ_IDLE : dma_get_order ? GET_ORDER : apb_penable ? READ_DEV_END : READ_DEV) :
|
||||
read_dev_end ? ((dma_trans_over | dma_stop) ? READ_IDLE : dma_get_order ? GET_ORDER : read_dev_again ? READ_DEV : READ_DEV_END) : READ_IDLE;
|
||||
|
||||
|
||||
reg [1:0]arb_write_op;
|
||||
wire aw_empty = (arb_write_op==2'b01) & write_ddr_end || (arb_write_op==2'b00) & write_dma_end || (arb_write_op==2'b11);
|
||||
wire write_ddr_ok = ((count_fifo >= `WRITE_LENGTH) | (count_fifo >= count_length)) & (count_length!=0);
|
||||
always @(posedge clk)begin
|
||||
if(!rst_n | dma_stop)
|
||||
arb_write_op <= 2'b11;
|
||||
else if(ask_valid & aw_empty & (arb_write_op!=0))
|
||||
arb_write_op <= 2'b00;
|
||||
else if(!dma_r_w & write_ddr_ok & aw_empty)
|
||||
arb_write_op <= 2'b01;
|
||||
else if(aw_empty)
|
||||
arb_write_op <= 2'b11;
|
||||
end
|
||||
|
||||
wire write_ddr_again = !dma_get_order & (arb_write_op==2'b01) & write_ddr_ok;
|
||||
wire write_dma_again = !dma_get_order & (arb_write_op==2'b00);
|
||||
|
||||
parameter WRITE_IDLE = 4'h0;
|
||||
parameter W_DDR_WAIT = 4'h1;
|
||||
parameter WRITE_DDR = 4'h2;
|
||||
parameter WRITE_DDR_END = 4'h3;
|
||||
parameter W_DMA_WAIT = 4'h4;
|
||||
parameter WRITE_DMA = 4'h5;
|
||||
parameter WRITE_DMA_END = 4'h6;
|
||||
parameter WRITE_STEP_END = 4'h7;
|
||||
assign write_idle = dma_write_state==WRITE_IDLE;
|
||||
assign w_ddr_wait = dma_write_state==W_DDR_WAIT;
|
||||
assign write_ddr = dma_write_state==WRITE_DDR;
|
||||
assign write_ddr_end = dma_write_state==WRITE_DDR_END;
|
||||
assign w_dma_wait = dma_write_state==W_DMA_WAIT;
|
||||
assign write_dma = dma_write_state==WRITE_DMA;
|
||||
assign write_dma_end = dma_write_state==WRITE_DMA_END;
|
||||
assign write_step_end = dma_write_state==WRITE_STEP_END;
|
||||
reg awvalid_dma;
|
||||
assign dma_next_write_state = write_idle ? (write_dma_again ? W_DMA_WAIT : write_ddr_again ? W_DDR_WAIT : WRITE_IDLE) :
|
||||
w_ddr_wait ? (awready ? WRITE_DDR : W_DDR_WAIT) :
|
||||
write_ddr ? (bvalid & bresp_ok & bready ? WRITE_DDR_END : WRITE_DDR) :
|
||||
write_ddr_end ? (write_dma_again ? W_DMA_WAIT : (count_length==0) ? WRITE_STEP_END : write_ddr_again ? W_DDR_WAIT : WRITE_DDR_END):
|
||||
w_dma_wait ? (awvalid_dma & awready ? WRITE_DMA : W_DMA_WAIT) :
|
||||
write_dma ? (bvalid & bresp_ok & bready ? WRITE_DMA_END : WRITE_DMA) :
|
||||
write_dma_end ? (dma_r_w ? WRITE_IDLE : (count_length==0) ? WRITE_STEP_END : write_ddr_again ? W_DDR_WAIT : WRITE_DMA_END) :
|
||||
write_step_end ? ((dma_trans_over | dma_stop | (count_length==0)&(dma_step_times==32'h1)) ? WRITE_IDLE :
|
||||
write_dma_again ? W_DMA_WAIT : write_ddr_again ? W_DDR_WAIT : WRITE_STEP_END) : WRITE_IDLE;
|
||||
|
||||
wire [1:0] ac97_mod = dma_dev_addr[29:28];
|
||||
wire byte_mod = (ac97_mod == 2'b00);
|
||||
wire half_mod = (ac97_mod == 2'b01);
|
||||
wire word_mod = (ac97_mod == 2'b10);
|
||||
wire [31:0] mem_0 = mem[count_fifo_w];
|
||||
wire [31:0] mem_1 = mem[count_fifo_w+1];
|
||||
wire [31:0] wdata_tmp0_tmp = byte_mod ? {mem_1[23:16], mem_1[7 :0], mem_0[23:16], mem_0[7 :0]} : half_mod ? {mem_1[15: 0], mem_0[15: 0]} : mem_0;
|
||||
wire [31:0] wdata_tmp1_tmp = byte_mod ? {mem_1[31:24], mem_1[15:8], mem_0[31:24], mem_0[15:8]} : half_mod ? {mem_1[31:16], mem_0[31:16]} : mem_1;
|
||||
wire [31:0] wdata_tmp0 = dma_dev_addr[30] ? wdata_tmp0_tmp : mem_0;
|
||||
wire [31:0] wdata_tmp1 = dma_dev_addr[30] ? wdata_tmp1_tmp : mem_0;
|
||||
reg [32:0] reg_ac97;
|
||||
wire write_dev_ok = ((dma_dev_addr[31:30]==2'b11) ? (reg_ac97[32] | (count_fifo>=6'h2)) : (count_fifo>=6'h1)) & dma_req & dma_r_w;
|
||||
always@(posedge clk)begin
|
||||
if(!rst_n)
|
||||
reg_ac97 <= 33'h0;
|
||||
else if(apb_penable & dma_dev_addr[31] & !reg_ac97[32])
|
||||
reg_ac97 <= {1'b1, wdata_tmp1};
|
||||
else if(apb_penable & reg_ac97[32])
|
||||
reg_ac97[32] <= 1'b0;
|
||||
end
|
||||
|
||||
reg arvalid_dev;
|
||||
always @(posedge clk)begin
|
||||
if(!rst_n)
|
||||
arvalid_dev <= 1'b0;
|
||||
else if(arvalid_dev & apb_penable)
|
||||
arvalid_dev <= 1'b0;
|
||||
else if((read_dev & !dma_get_order | read_dev_end) & read_dev_again)
|
||||
arvalid_dev <= 1'b1;
|
||||
end
|
||||
|
||||
reg awvalid_dev;
|
||||
always @(posedge clk)begin
|
||||
if(!rst_n)
|
||||
awvalid_dev <= 1'b0;
|
||||
else if(awvalid_dev & apb_penable)
|
||||
awvalid_dev <= 1'b0;
|
||||
else if(write_dev_ok)
|
||||
awvalid_dev <= 1'b1;
|
||||
end
|
||||
assign dma_ack_out = apb_psel;
|
||||
|
||||
assign dma_state_change_en = (dma_read_state !=dma_next_read_state) | (dma_write_state!=dma_next_write_state);
|
||||
always@(posedge clk)begin
|
||||
if(!rst_n | dma_trans_over | dma_stop)begin
|
||||
dma_read_state <= READ_IDLE;
|
||||
dma_write_state <= WRITE_IDLE;
|
||||
end else if(dma_state_change_en)begin
|
||||
dma_read_state <= dma_next_read_state;
|
||||
dma_write_state <= dma_next_write_state;
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge clk)begin
|
||||
if(~rst_n | finish_read_order | dma_stop)
|
||||
dma_get_order <= 1'b0;
|
||||
else if((read_idle & write_idle) & dma_start | dma_single_trans_over & dma_order_en)
|
||||
dma_get_order <= 1'b1;
|
||||
end
|
||||
|
||||
wire [2:0] size_tmp = read_ddr ? arsize : awsize;
|
||||
wire [1:0] read_size = read_dev ? 2'h1 : (arsize==3'h3) ? 2'h2 : 2'h1;
|
||||
wire [1:0] write_size = awvalid_dev ? (((dma_dev_addr[31:30]==2'b11) & (count_fifo>32'h1)) ? 2'h2 : 2'h1) : (awsize==3'h3) ? 2'h2 : 2'h1;
|
||||
|
||||
always@(posedge clk)begin
|
||||
if(~rst_n)
|
||||
count_length <= 32'b0;
|
||||
else if (dma_stop)
|
||||
count_length <= 32'b0;
|
||||
else if(finish_read_order)
|
||||
count_length <= dma_length;
|
||||
else if(dma_get_order)
|
||||
count_length <= `DMA_ORDERSIZE;
|
||||
else if(((read_ddr_end | write_ddr_end) & count_length==32'b0) & (dma_step_times > 32'h1))
|
||||
count_length <= dma_length;
|
||||
else if(read_ddr & rvalid & rready & rresp_ok | write_ddr & wvalid & wready)
|
||||
count_length <= count_length - ((size_tmp==3'h3) ? 2'h2 : 2'h1);
|
||||
end
|
||||
|
||||
reg [4:0] read_num;
|
||||
reg [4:0] write_num;
|
||||
always@(posedge clk)begin
|
||||
if(~rst_n | dma_single_trans_over | dma_stop)begin
|
||||
count_fifo_r <= 5'h0;
|
||||
read_num <= 5'h0;
|
||||
end else if(read_ddr & rvalid & rready & rresp_ok | read_dev & apb_penable)begin
|
||||
count_fifo_r <= count_fifo_r + read_size;
|
||||
read_num <= read_ddr ? (rlast ? 5'h0 : read_num + 1'b1) : read_num;
|
||||
end
|
||||
end
|
||||
always@(posedge clk)begin
|
||||
if(~rst_n | dma_single_trans_over | dma_stop)begin
|
||||
count_fifo_w <= 5'h0;
|
||||
write_num <= 5'h0;
|
||||
end else if(write_ddr & wvalid & wready | awvalid_dev & apb_penable & !reg_ac97[32])begin
|
||||
count_fifo_w <= count_fifo_w + write_size;
|
||||
write_num <= write_ddr ? (wlast ? 5'h0 : write_num + 1'b1) : write_num;
|
||||
end
|
||||
end
|
||||
|
||||
reg write_dma_to_ddr;
|
||||
reg [1:0]dma_num;
|
||||
|
||||
always@(posedge clk)begin
|
||||
if(~rst_n)begin
|
||||
dma_num <= 2'h0;
|
||||
write_dma_to_ddr <= 1'h0;
|
||||
end
|
||||
else if(write_dma & wvalid & wready)begin
|
||||
dma_num <= dma_num + 1'b1;
|
||||
write_dma_to_ddr <= !write_dma_to_ddr;
|
||||
end
|
||||
end
|
||||
|
||||
wire [1:0] fifo_read_add = {2{(read_ddr & rvalid & rready | read_dev & apb_penable)}} & read_size;
|
||||
wire [1:0] fifo_write_sum = {2{(write_ddr & wvalid & wready | awvalid_dev & apb_penable & !reg_ac97[32])}} & write_size;
|
||||
always@(posedge clk)begin
|
||||
if(~rst_n | dma_single_trans_over | dma_stop)
|
||||
count_fifo <= 6'h0;
|
||||
else
|
||||
count_fifo <= count_fifo + fifo_read_add - fifo_write_sum;
|
||||
end
|
||||
|
||||
reg arvalid_dma;
|
||||
wire [31:0] araddr_dma;
|
||||
wire [3 :0] arlen_dma;
|
||||
wire [2 :0] arsize_dma;
|
||||
reg getting_dma;
|
||||
always @(posedge clk)begin
|
||||
if(!rst_n)begin
|
||||
arvalid_dma <= 1'b0;
|
||||
getting_dma <= 1'b0;
|
||||
end else if(arvalid_dma & arready)
|
||||
arvalid_dma <= 1'b0;
|
||||
else if(dma_get_order & !getting_dma)begin
|
||||
arvalid_dma <= 1'b1;
|
||||
getting_dma <= 1'b1;
|
||||
end else if(finish_read_order | dma_stop)
|
||||
getting_dma <= 1'b0;
|
||||
end
|
||||
assign araddr_dma = (dma_start & dma_get_order) ? ask_addr : {dma_order_addr[31:5], 5'h0};
|
||||
assign arlen_dma = 4'h3;
|
||||
assign arsize_dma = 3'h3;
|
||||
|
||||
wire [2:0] arsize_ddr_tmp;
|
||||
wire [3:0] arlen_ddr_tmp;
|
||||
wire [5:0] left_fifo = `DMA_WORDSIZE - count_fifo;
|
||||
wire enough_8;
|
||||
assign num_fifo = (count_length >= left_fifo) ? left_fifo : count_length;
|
||||
wire [3:0] arlen_tmp = (num_fifo >= 6'h10) ? 4'hf : (num_fifo-1'b1);
|
||||
assign enough_8 = (num_fifo >= 6'h2);
|
||||
assign arsize_ddr_tmp = (dma_mem_addr[2:0]==3'h0) & enough_8 ? 3'h3 : 3'h2;
|
||||
assign arlen_ddr_tmp = (dma_mem_addr[2:0]==3'h0) & enough_8 ? (num_fifo[5] ? 4'hf : (num_fifo[5:1]-1'b1)): arlen_tmp;
|
||||
|
||||
reg arvalid_ddr;
|
||||
reg [31:0] araddr_ddr;
|
||||
reg [3 :0] arlen_ddr;
|
||||
reg [2: 0] arsize_ddr;
|
||||
always @(posedge clk)begin
|
||||
if(!rst_n)
|
||||
arvalid_ddr <= 1'b0;
|
||||
else if(arready & arvalid_ddr)
|
||||
arvalid_ddr <= 1'b0;
|
||||
else if((read_ready & !dma_get_order | read_ddr_end | read_step_end) & read_ddr_again & !dma_stop)
|
||||
arvalid_ddr <= 1'b1;
|
||||
end
|
||||
|
||||
always @(posedge clk)begin
|
||||
if(!rst_n)
|
||||
begin
|
||||
araddr_ddr <= 32'b0;
|
||||
arsize_ddr <= 3'b0;
|
||||
arlen_ddr <= 4'b0;
|
||||
end
|
||||
else if((read_ready & !dma_get_order | read_ddr_end | read_step_end) & read_ddr_again)begin
|
||||
araddr_ddr <= dma_mem_addr;
|
||||
arsize_ddr <= arsize_ddr_tmp;
|
||||
arlen_ddr <= arlen_ddr_tmp;
|
||||
end
|
||||
end
|
||||
|
||||
assign arvalid = dma_get_order ? arvalid_dma : dma_r_w ? arvalid_ddr : 1'b0;
|
||||
assign araddr = dma_get_order ? {32'h0, araddr_dma} : {32'h0, araddr_ddr};
|
||||
assign arsize = dma_get_order ? arsize_dma : arsize_ddr;
|
||||
assign arlen = dma_get_order ? arlen_dma : arlen_ddr;
|
||||
assign arid = dma_get_order ? {4'h0, 4'h1} : {4'h0, 4'h2};
|
||||
assign arburst = 2'h1;
|
||||
assign arlock = 2'h0;
|
||||
assign arprot = 3'h0;
|
||||
assign arcache = 4'h0;
|
||||
assign rready = 1'h1;
|
||||
|
||||
wire[31:0] count_sou;
|
||||
assign count_sou = araddr_ddr + {read_num, 2'h0};
|
||||
wire [31:0]read_data_word = !count_sou[2] ? rdata[31:0] : rdata[63:32];
|
||||
|
||||
integer i;
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if(~rst_n | dma_stop | dma_single_trans_over)
|
||||
begin
|
||||
for(i=0;i<=31;i=i+1) mem[i] <= 32'b0;
|
||||
end
|
||||
else if(read_ddr & rvalid & rready & rresp_ok & arsize==3'h2)
|
||||
mem[count_fifo_r] <= read_data_word;
|
||||
else if(read_ddr & rvalid & rready & rresp_ok & arsize==3'h3)
|
||||
{mem[count_fifo_r+1], mem[count_fifo_r]} <= rdata;
|
||||
else if(read_dev & apb_penable)
|
||||
mem[count_fifo_r] <= apb_rdata;
|
||||
end
|
||||
|
||||
reg [1:0]reg_num;
|
||||
always@(posedge clk)begin
|
||||
if(~rst_n | dma_stop)begin
|
||||
dma_r_w <= 1'b0;
|
||||
dma_order_addr <= 32'b0;
|
||||
dma_mem_addr <= 32'b0;
|
||||
dma_dev_addr <= 32'b0;
|
||||
dma_length <= 32'b0;
|
||||
dma_step_length<= 32'b0;
|
||||
dma_step_times <= 32'b0;
|
||||
reg_num <= 2'b0;
|
||||
end
|
||||
else begin
|
||||
if(read_ddr & rvalid & rready & rresp_ok | write_ddr & wvalid & wready)
|
||||
dma_mem_addr <= dma_mem_addr + ((size_tmp==3'h3) ? 4'h8 : 3'h4);
|
||||
else if((write_ddr_end | read_ddr_end) & (count_length==32'b0) & dma_step_times>32'b1)begin
|
||||
dma_step_times <= dma_step_times - 1;
|
||||
dma_mem_addr <= dma_mem_addr + {dma_step_length, 2'h0};
|
||||
end else if(read_order & rvalid & rready & rresp_ok & (reg_num==2'h0))begin
|
||||
dma_order_addr <= rdata[31 : 0];
|
||||
dma_mem_addr <= rdata[63 :32];
|
||||
reg_num <= reg_num + 1'b1;
|
||||
end else if(read_order & rvalid & rready & rresp_ok & (reg_num==2'h1))begin
|
||||
dma_dev_addr <= rdata[31 : 0];
|
||||
dma_length <= rdata[63 :32];
|
||||
reg_num <= reg_num + 1'b1;
|
||||
end else if(read_order & rvalid & rready & rresp_ok & (reg_num==2'h2))begin
|
||||
dma_step_length<= rdata[31: 0];
|
||||
dma_step_times <= rdata[63:32];
|
||||
reg_num <= reg_num + 1'b1;
|
||||
end else if(read_order & rvalid & rready & rresp_ok & rlast)begin
|
||||
dma_r_w <= rdata[12];
|
||||
reg_num <= 2'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg dma_int_en;
|
||||
reg dma_int_i;
|
||||
always@(posedge clk)begin
|
||||
if(~rst_n)
|
||||
dma_state_reg <= 32'b0;
|
||||
else if(read_order & rvalid & rready & rresp_ok & rlast)
|
||||
dma_state_reg <= rdata[31:0];
|
||||
else if(dma_start == 1'b1)
|
||||
dma_state_reg[1] <= 1'b0;
|
||||
else if(dma_int_i & dma_int_en)
|
||||
dma_state_reg[1] <= 1'b1;
|
||||
else if(dma_state_reg[1])
|
||||
dma_state_reg[1] <= 1'b0;
|
||||
end
|
||||
|
||||
reg dma_int_tmp;
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if(!rst_n)
|
||||
dma_int_i <= 1'b0;
|
||||
else if(dma_single_trans_over & dma_int_mask & !dma_int_i)
|
||||
dma_int_i <= 1'b1;
|
||||
else if(dma_int_i & dma_int_en)
|
||||
dma_int_i <= 1'b0;
|
||||
end
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if(!rst_n)
|
||||
dma_int_tmp <= 1'b0;
|
||||
else
|
||||
dma_int_tmp <= dma_int_i;
|
||||
end
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if(!rst_n)
|
||||
dma_int_en <= 1'b1;
|
||||
else if(dma_int_tmp & dma_int_en)
|
||||
dma_int_en <= 1'b0;
|
||||
else if(!dma_int_i)
|
||||
dma_int_en <= 1'b1;
|
||||
end
|
||||
|
||||
wire [5:0] write_length;
|
||||
wire enough_8_1;
|
||||
wire [2:0] awsize_ddr_tmp;
|
||||
wire [3:0] awlen_ddr_tmp;
|
||||
wire [3:0] awlen_tmp;
|
||||
assign write_length = (count_fifo >= count_length) ? count_length[5:0] : count_fifo;
|
||||
assign enough_8_1 = (write_length >= 3'h2);
|
||||
assign awlen_tmp = (write_length >= 5'h10) ? 4'hf : (write_length - 1'b1);
|
||||
assign awsize_ddr_tmp = (dma_mem_addr[2:0]==3'h0) & enough_8_1 ? 3'h3 : 3'h2;
|
||||
assign awlen_ddr_tmp = (dma_mem_addr[2:0]==3'h0) & enough_8_1 ? (write_length[5]? 4'hf : (write_length[5:1] - 1'b1)) : awlen_tmp;
|
||||
reg awvalid_ddr;
|
||||
reg [31:0] awaddr_ddr;
|
||||
reg [3 :0] awlen_ddr;
|
||||
reg [2 :0] awsize_ddr;
|
||||
reg wvalid_ddr;
|
||||
always @(posedge clk)begin
|
||||
if(!rst_n)
|
||||
awvalid_ddr <= 1'b0;
|
||||
else if(awvalid_ddr & awready)
|
||||
awvalid_ddr <= 1'b0;
|
||||
else if(write_ddr_again & !write_dma_again & (write_idle | write_ddr_end | write_dma_end | write_step_end) & !dma_stop)
|
||||
awvalid_ddr <= 1'b1;
|
||||
end
|
||||
always @(posedge clk)begin
|
||||
if(!rst_n)
|
||||
begin
|
||||
awaddr_ddr <= 32'b0;
|
||||
awsize_ddr <= 3'b0;
|
||||
awlen_ddr <= 4'b0;
|
||||
end
|
||||
else if(write_ddr)begin
|
||||
awaddr_ddr <= awaddr_ddr;
|
||||
awsize_ddr <= awsize_ddr;
|
||||
awlen_ddr <= awlen_ddr;
|
||||
end else if(write_ddr_again & !write_dma_again & (write_idle | write_ddr_end | write_dma_end | write_step_end))begin
|
||||
awaddr_ddr <= dma_mem_addr;
|
||||
awsize_ddr <= awsize_ddr_tmp;
|
||||
awlen_ddr <= awlen_ddr_tmp;
|
||||
end
|
||||
end
|
||||
always @(posedge clk)begin
|
||||
if(!rst_n)
|
||||
wvalid_ddr <= 1'b0;
|
||||
else if (awvalid_ddr & awready)begin
|
||||
wvalid_ddr <= 1'b1;
|
||||
end
|
||||
else if(write_ddr & wvalid & wready)begin
|
||||
wvalid_ddr <= !wlast;
|
||||
end
|
||||
end
|
||||
assign count_obj = awaddr_ddr + {write_num, 2'h0};
|
||||
wire [63:0] wdata_word = !count_obj[2] ? {32'h0, mem[count_fifo_w]} : {mem[count_fifo_w], 32'h0};
|
||||
wire [7 :0] wstrb_word = !count_obj[2] ? 8'h0f : 8'hf0;
|
||||
wire [63:0] wdata_64 = {mem[count_fifo_w+1], mem[count_fifo_w]};
|
||||
wire [63:0] wdata_ddr;
|
||||
wire [15:0] wstrb_ddr;
|
||||
wire wlast_ddr;
|
||||
assign wdata_ddr = (awsize_ddr==3'h2) ? wdata_word : wdata_64;
|
||||
assign wstrb_ddr = (awsize_ddr==3'h2) ? wstrb_word : 8'hff;
|
||||
assign wlast_ddr = (write_num==awlen_ddr);
|
||||
|
||||
reg wvalid_dma;
|
||||
wire [31:0] awaddr_dma;
|
||||
wire [3 :0] awlen_dma;
|
||||
wire [2 :0] awsize_dma;
|
||||
wire [63:0] wdata_dma;
|
||||
wire [15 :0] wstrb_dma;
|
||||
wire wlast_dma;
|
||||
always @(posedge clk)begin
|
||||
if(!rst_n)
|
||||
awvalid_dma <= 1'b0;
|
||||
else if(awvalid_dma & awready)
|
||||
awvalid_dma <= 1'b0;
|
||||
else if(write_dma_again & !dma_stop & w_dma_wait)
|
||||
awvalid_dma <= 1'b1;
|
||||
end
|
||||
always @(posedge clk)begin
|
||||
if(!rst_n)
|
||||
wvalid_dma <= 1'b0;
|
||||
else if (awvalid_dma & awready)
|
||||
wvalid_dma <= 1'b1;
|
||||
else if(write_dma & wvalid & wready)
|
||||
wvalid_dma <= !wlast;
|
||||
end
|
||||
|
||||
wire [63:0] dma_data0;
|
||||
wire [63:0] dma_data1;
|
||||
wire [63:0] dma_data2;
|
||||
wire [63:0] dma_data3;
|
||||
wire [31:0] dma_state_tmp = {19'h0, dma_r_w, dma_write_state, dma_read_state, dma_trans_over_reg,
|
||||
dma_single_trans_over, dma_int, dma_int_mask};
|
||||
|
||||
assign dma_data0 = {dma_mem_addr, dma_order_addr };
|
||||
assign dma_data1 = {dma_length, dma_dev_addr };
|
||||
assign dma_data2 = {dma_step_times, dma_step_length};
|
||||
assign dma_data3 = {32'h0, dma_state_tmp };
|
||||
|
||||
assign awaddr_dma = ask_addr;
|
||||
assign awlen_dma = 4'h3;
|
||||
assign awsize_dma = 3'h3;
|
||||
|
||||
assign wlast_dma = (dma_num== 2'h3);
|
||||
assign wdata_dma = (dma_num==2'h0) ? dma_data0 : (dma_num==2'h1) ? dma_data1 : (dma_num==2'h2) ? dma_data2 : dma_data3;
|
||||
assign wstrb_dma = (dma_num!=2'h3) ? 8'hff : 8'h0f;
|
||||
|
||||
assign awvalid = awvalid_dma | awvalid_ddr ;
|
||||
assign awaddr = awvalid_dma ? {32'h0, awaddr_dma} : {32'h0, awaddr_ddr};
|
||||
assign awlen = awvalid_dma ? awlen_dma : awlen_ddr;
|
||||
assign awsize = awvalid_dma ? awsize_dma : awsize_ddr;
|
||||
assign awid = awvalid_dma ? {4'h0, 4'h1} : {4'h0, 4'h2};
|
||||
assign awburst = 2'h1;
|
||||
assign awlock = 2'h0;
|
||||
assign awprot = 3'h0;
|
||||
assign awcache = 4'h0;
|
||||
assign wvalid = wvalid_dma | wvalid_ddr ;
|
||||
assign wid = wvalid_dma ? {4'h0, 4'h1} : {4'h0, 4'h2};
|
||||
assign wdata = wvalid_dma ? wdata_dma : wdata_ddr;
|
||||
assign wstrb = wvalid_dma ? wstrb_dma : wstrb_ddr;
|
||||
assign wlast = wvalid_dma ? wlast_dma : wlast_ddr;
|
||||
assign bready = 1'b1;
|
||||
|
||||
wire apb_valid_req;
|
||||
reg apb_psel;
|
||||
reg apb_penable;
|
||||
reg apb_rw;
|
||||
wire [31:0]apb_addr;
|
||||
wire [31:0]apb_wdata;
|
||||
assign apb_valid_req = arvalid_dev || awvalid_dev ;
|
||||
assign apb_addr = dma_dev_addr[31] ? (reg_ac97[32] ? {24'h1fe600, dma_dev_addr[15:8]} :{24'h1fe600, dma_dev_addr[7:0]}) : dma_dev_addr;
|
||||
assign apb_wdata= reg_ac97[32] ? reg_ac97[31:0] : wdata_tmp0;
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if(~rst_n)begin
|
||||
apb_psel<= 1'b0;
|
||||
apb_penable <= 1'b0;
|
||||
apb_rw <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if(dma_gnt) begin
|
||||
if(apb_penable)begin
|
||||
apb_psel <= 1'b0;
|
||||
apb_rw <= 1'b0;
|
||||
apb_penable <= 1'b0;
|
||||
end else if(arvalid_dev | awvalid_dev) begin
|
||||
apb_psel <= 1'b1;
|
||||
apb_rw <= awvalid_dev ;
|
||||
apb_penable <= apb_psel;
|
||||
end else
|
||||
apb_penable <= apb_psel;
|
||||
end else begin
|
||||
apb_psel<= 1'b0;
|
||||
apb_penable <= 1'b0;
|
||||
apb_rw <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
372
resources/soc/rtl/MAC/bd.v
Normal file
372
resources/soc/rtl/MAC/bd.v
Normal file
@ -0,0 +1,372 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
module BD (
|
||||
clk,
|
||||
rst,
|
||||
col,
|
||||
crs,
|
||||
fdp,
|
||||
tprog,
|
||||
preamble,
|
||||
tpend,
|
||||
winp,
|
||||
tiack,
|
||||
coll,
|
||||
carrier,
|
||||
bkoff,
|
||||
lc,
|
||||
lo,
|
||||
nc,
|
||||
ec,
|
||||
cc
|
||||
);
|
||||
|
||||
`include "utility.v"
|
||||
|
||||
input clk;
|
||||
input rst;
|
||||
|
||||
input col;
|
||||
input crs;
|
||||
|
||||
input fdp;
|
||||
|
||||
input tprog;
|
||||
input preamble;
|
||||
input tpend;
|
||||
output winp;
|
||||
wire winp;
|
||||
input tiack;
|
||||
output coll;
|
||||
wire coll;
|
||||
output carrier;
|
||||
wire carrier;
|
||||
output bkoff;
|
||||
wire bkoff;
|
||||
output lc;
|
||||
wire lc;
|
||||
output lo;
|
||||
reg lo;
|
||||
output nc;
|
||||
wire nc;
|
||||
output ec;
|
||||
reg ec;
|
||||
output [3:0] cc;
|
||||
wire [3:0] cc;
|
||||
|
||||
|
||||
reg crs_r;
|
||||
reg inc;
|
||||
|
||||
reg ibkoff;
|
||||
reg ibkoff_r;
|
||||
reg icoll;
|
||||
reg ilc;
|
||||
reg [3:0] ccnt;
|
||||
reg [9:0] bkcnt;
|
||||
reg [8:0] slcnt;
|
||||
reg [9:0] bkrel_c;
|
||||
wire [9:0] p_rand;
|
||||
reg [31:0] lfsr;
|
||||
reg [31:0] lfsr_c;
|
||||
reg iwinp;
|
||||
|
||||
always @(posedge clk)
|
||||
begin : crs_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
crs_r <= 1'b0 ;
|
||||
lo <= 1'b0 ;
|
||||
inc <= 1'b0 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (fdp)
|
||||
begin
|
||||
crs_r <= 1'b0 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
crs_r <= crs ;
|
||||
end
|
||||
|
||||
if (tprog & !inc & !crs_r)
|
||||
begin
|
||||
lo <= 1'b1 ;
|
||||
end
|
||||
else if(!tpend & !tprog)
|
||||
begin
|
||||
lo <= 1'b0 ;
|
||||
end
|
||||
|
||||
if (tprog & crs_r)
|
||||
begin
|
||||
inc <= 1'b0 ;
|
||||
end
|
||||
else if (!tpend & !tprog)
|
||||
begin
|
||||
inc <= 1'b1 ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign nc = inc ;
|
||||
|
||||
always @(ccnt or p_rand)
|
||||
begin : bkrel_proc
|
||||
case (ccnt)
|
||||
4'b0000 :
|
||||
begin
|
||||
bkrel_c <= {9'b000000000, p_rand[0]} ;
|
||||
end
|
||||
4'b0001 :
|
||||
begin
|
||||
bkrel_c <= {8'b00000000, p_rand[1:0]} ;
|
||||
end
|
||||
4'b0010 :
|
||||
begin
|
||||
bkrel_c <= {7'b0000000, p_rand[2:0]} ;
|
||||
end
|
||||
4'b0011 :
|
||||
begin
|
||||
bkrel_c <= {6'b000000, p_rand[3:0]} ;
|
||||
end
|
||||
4'b0100 :
|
||||
begin
|
||||
bkrel_c <= {5'b00000, p_rand[4:0]} ;
|
||||
end
|
||||
4'b0101 :
|
||||
begin
|
||||
bkrel_c <= {4'b0000, p_rand[5:0]} ;
|
||||
end
|
||||
4'b0110 :
|
||||
begin
|
||||
bkrel_c <= {3'b000, p_rand[6:0]} ;
|
||||
end
|
||||
4'b0111 :
|
||||
begin
|
||||
bkrel_c <= {2'b00, p_rand[7:0]} ;
|
||||
end
|
||||
4'b1000 :
|
||||
begin
|
||||
bkrel_c <= {1'b0, p_rand[8:0]} ;
|
||||
end
|
||||
default :
|
||||
begin
|
||||
bkrel_c <= p_rand[9:0] ;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : slcnt_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
slcnt <= {9{1'b1}} ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (tprog & !preamble & !icoll)
|
||||
begin
|
||||
if (slcnt != 9'b000000000)
|
||||
begin
|
||||
slcnt <= slcnt - 1 ;
|
||||
end
|
||||
end
|
||||
else if (ibkoff)
|
||||
begin
|
||||
if (slcnt == 9'b000000000 | icoll)
|
||||
begin
|
||||
slcnt <= SLOT_TIME ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
slcnt <= slcnt - 1 ;
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
slcnt <= SLOT_TIME ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : bkcnt_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
bkcnt <= {10{1'b1}} ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (icoll & !ibkoff)
|
||||
begin
|
||||
bkcnt <= bkrel_c ;
|
||||
end
|
||||
else if (slcnt == 9'b000000000)
|
||||
begin
|
||||
bkcnt <= bkcnt - 1 ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : rand_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
lfsr <= {31{1'b1}};
|
||||
end
|
||||
else
|
||||
begin
|
||||
lfsr <= lfsr_c;
|
||||
end
|
||||
end
|
||||
|
||||
always @(lfsr)
|
||||
begin : lfsr_drv
|
||||
|
||||
reg [31:0] lfsr_n;
|
||||
|
||||
integer i;
|
||||
for(i=0; i<=30; i=i+1)
|
||||
begin
|
||||
lfsr_n[i] = lfsr[i+1];
|
||||
end
|
||||
|
||||
lfsr_n[31] = 1'b0;
|
||||
if(lfsr[0]==1'b1)
|
||||
begin
|
||||
lfsr_n = lfsr_n ^ 32'b10000000000000000000111010100110;
|
||||
end
|
||||
|
||||
lfsr_c <= lfsr_n;
|
||||
|
||||
end
|
||||
|
||||
assign p_rand = lfsr[9:0] ;
|
||||
|
||||
|
||||
always @(posedge clk)
|
||||
begin : ibkoff_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
ibkoff <= 1'b0 ;
|
||||
ibkoff_r <= 1'b0 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
ibkoff_r <= ibkoff ;
|
||||
if(icoll & ccnt!=4'b1111 & !iwinp & !ilc)
|
||||
begin
|
||||
ibkoff <= 1'b1 ;
|
||||
end
|
||||
else if (bkcnt == 10'b0000000000)
|
||||
begin
|
||||
ibkoff <= 1'b0 ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : coll_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
icoll <= 1'b0 ;
|
||||
ilc <= 1'b0 ;
|
||||
ec <= 1'b0 ;
|
||||
iwinp <= 1'b1 ;
|
||||
ccnt <= 4'b0000 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if ((preamble | tprog) & col & !fdp)
|
||||
begin
|
||||
icoll <= 1'b1 ;
|
||||
end
|
||||
else if (!tprog & !preamble)
|
||||
begin
|
||||
icoll <= 1'b0 ;
|
||||
end
|
||||
|
||||
if (tiack)
|
||||
begin
|
||||
ilc <= 1'b0 ;
|
||||
end
|
||||
else if (tprog & icoll & iwinp)
|
||||
begin
|
||||
ilc <= 1'b1 ;
|
||||
end
|
||||
|
||||
if (tiack)
|
||||
begin
|
||||
ec <= 1'b0 ;
|
||||
end
|
||||
else if (icoll & ccnt == 4'b1111 & tprog)
|
||||
begin
|
||||
ec <= 1'b1 ;
|
||||
end
|
||||
|
||||
if (slcnt == 9'b000000000 | !tprog)
|
||||
begin
|
||||
iwinp <= 1'b1 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
iwinp <= 1'b0 ;
|
||||
end
|
||||
|
||||
if (!tpend & !tprog)
|
||||
begin
|
||||
ccnt <= 4'b0000 ;
|
||||
end
|
||||
else if (ibkoff & !ibkoff_r)
|
||||
begin
|
||||
ccnt <= ccnt + 4'b0001 ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign winp = iwinp ;
|
||||
|
||||
assign lc = ilc;
|
||||
|
||||
assign carrier = crs_r ;
|
||||
|
||||
assign coll = icoll ;
|
||||
|
||||
assign bkoff = ibkoff ;
|
||||
|
||||
assign cc = ccnt ;
|
||||
|
||||
endmodule
|
2530
resources/soc/rtl/MAC/csr.v
Normal file
2530
resources/soc/rtl/MAC/csr.v
Normal file
File diff suppressed because it is too large
Load Diff
646
resources/soc/rtl/MAC/dma.v
Normal file
646
resources/soc/rtl/MAC/dma.v
Normal file
@ -0,0 +1,646 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
module DMA (
|
||||
clk,
|
||||
rst,
|
||||
dma_priority,
|
||||
ble,
|
||||
dbo,
|
||||
rdes,
|
||||
rbuf,
|
||||
rstat,
|
||||
tdes,
|
||||
tbuf,
|
||||
tstat,
|
||||
dataack,
|
||||
datai,
|
||||
datareq,
|
||||
datareqc,
|
||||
datarw,
|
||||
dataeob,
|
||||
dataeobc,
|
||||
datao,
|
||||
dataaddr,
|
||||
idataaddr,
|
||||
req1,
|
||||
write1,
|
||||
tcnt1,
|
||||
addr1,
|
||||
datai1,
|
||||
ack1,
|
||||
eob1,
|
||||
datao1,
|
||||
req2,
|
||||
write2,
|
||||
tcnt2,
|
||||
addr2,
|
||||
datai2,
|
||||
ack2,
|
||||
eob2,
|
||||
datao2);
|
||||
|
||||
parameter DATAWIDTH = 32;
|
||||
parameter DATADEPTH = 32;
|
||||
|
||||
`include "utility.v"
|
||||
|
||||
input clk;
|
||||
input rst;
|
||||
|
||||
input [1:0] dma_priority;
|
||||
input ble;
|
||||
input dbo;
|
||||
input rdes;
|
||||
input rbuf;
|
||||
input rstat;
|
||||
input tdes;
|
||||
input tbuf;
|
||||
input tstat;
|
||||
|
||||
|
||||
input dataack;
|
||||
input [DATAWIDTH - 1:0] datai;
|
||||
output datareq;
|
||||
wire datareq;
|
||||
output datareqc;
|
||||
wire datareqc;
|
||||
output datarw;
|
||||
reg datarw;
|
||||
output dataeob;
|
||||
wire dataeob;
|
||||
output dataeobc;
|
||||
wire dataeobc;
|
||||
output [DATAWIDTH - 1:0] datao;
|
||||
wire [DATAWIDTH - 1:0] datao;
|
||||
output [DATADEPTH - 1:0] dataaddr;
|
||||
wire [DATADEPTH - 1:0] dataaddr;
|
||||
output [DATADEPTH - 1:0] idataaddr;
|
||||
wire [DATADEPTH - 1:0] idataaddr;
|
||||
|
||||
input req1;
|
||||
input write1;
|
||||
input [FIFODEPTH_MAX - 1:0] tcnt1;
|
||||
input [DATADEPTH - 1:0] addr1;
|
||||
input [DATAWIDTH - 1:0] datai1;
|
||||
output ack1;
|
||||
wire ack1;
|
||||
output eob1;
|
||||
wire eob1;
|
||||
output [DATAWIDTH - 1:0] datao1;
|
||||
wire [DATAWIDTH - 1:0] datao1;
|
||||
|
||||
input req2;
|
||||
input write2;
|
||||
input [FIFODEPTH_MAX - 1:0] tcnt2;
|
||||
input [DATADEPTH - 1:0] addr2;
|
||||
input [DATAWIDTH - 1:0] datai2;
|
||||
output ack2;
|
||||
wire ack2;
|
||||
output eob2;
|
||||
wire eob2;
|
||||
output [DATAWIDTH - 1:0] datao2;
|
||||
wire [DATAWIDTH - 1:0] datao2;
|
||||
|
||||
|
||||
reg [1:0] dsm_c;
|
||||
reg [1:0] dsm;
|
||||
reg hist1;
|
||||
reg hist2;
|
||||
wire [1:0] dmareq;
|
||||
reg [FIFODEPTH_MAX - 1:0] msmbcnt;
|
||||
reg idatareq;
|
||||
reg idatareqc;
|
||||
reg eob;
|
||||
reg eobc;
|
||||
reg [DATADEPTH - 1:0] addr_c;
|
||||
reg [DATADEPTH - 1:0] addr;
|
||||
reg blesel_c;
|
||||
reg [DATAWIDTH - 1:0] dataible_c;
|
||||
reg [DATAWIDTH - 1:0] dataoble_c;
|
||||
wire [DATAWIDTH_MAX + 1:0] datai_max;
|
||||
reg req_c;
|
||||
reg write_c;
|
||||
reg [FIFODEPTH_MAX - 1:0] tcnt_c;
|
||||
reg [DATADEPTH - 1:0] saddr_c;
|
||||
reg [DATAWIDTH_MAX - 1:0] datai_c;
|
||||
wire [DATAWIDTH_MAX + 1:0] datai_max_c;
|
||||
wire [FIFODEPTH_MAX - 1:0] fzero;
|
||||
wire [DATAWIDTH_MAX + 1:0] dzero;
|
||||
|
||||
assign dmareq = {req2, req1} ;
|
||||
|
||||
always @(dsm or
|
||||
dmareq or
|
||||
hist1 or
|
||||
hist2 or
|
||||
dma_priority or
|
||||
eob or
|
||||
dataack)
|
||||
begin : dsm_proc
|
||||
case (dsm)
|
||||
DSM_IDLE :
|
||||
begin
|
||||
case (dmareq)
|
||||
2'b11 :
|
||||
begin
|
||||
case (dma_priority)
|
||||
2'b01 :
|
||||
begin
|
||||
if (!hist1 & !hist2)
|
||||
begin
|
||||
dsm_c <= DSM_CH2 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
dsm_c <= DSM_CH1 ;
|
||||
end
|
||||
end
|
||||
2'b10 :
|
||||
begin
|
||||
if (hist1 & hist2)
|
||||
begin
|
||||
dsm_c <= DSM_CH1 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
dsm_c <= DSM_CH2 ;
|
||||
end
|
||||
end
|
||||
default :
|
||||
begin
|
||||
if (hist1)
|
||||
begin
|
||||
dsm_c <= DSM_CH1 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
dsm_c <= DSM_CH2 ;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
2'b01 :
|
||||
begin
|
||||
dsm_c <= DSM_CH1 ;
|
||||
end
|
||||
2'b10 :
|
||||
begin
|
||||
dsm_c <= DSM_CH2 ;
|
||||
end
|
||||
default :
|
||||
begin
|
||||
dsm_c <= DSM_IDLE ;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
DSM_CH1 :
|
||||
begin
|
||||
if (eob & dataack)
|
||||
begin
|
||||
dsm_c <= DSM_IDLE ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
dsm_c <= DSM_CH1 ;
|
||||
end
|
||||
end
|
||||
default :
|
||||
begin
|
||||
if (eob & dataack)
|
||||
begin
|
||||
dsm_c <= DSM_IDLE ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
dsm_c <= DSM_CH2 ;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : dsm_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
dsm <= DSM_IDLE ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
dsm <= dsm_c ;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : hist_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
hist1 <= 1'b1 ;
|
||||
hist2 <= 1'b1 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (eob)
|
||||
begin
|
||||
case (dsm)
|
||||
DSM_CH1 :
|
||||
begin
|
||||
hist1 <= 1'b1 ;
|
||||
end
|
||||
DSM_CH2 :
|
||||
begin
|
||||
hist1 <= 1'b0 ;
|
||||
end
|
||||
default :
|
||||
begin
|
||||
hist1 <= hist1 ;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
hist2 <= hist1 ;
|
||||
end
|
||||
end
|
||||
|
||||
always @(dbo or
|
||||
ble or
|
||||
dsm_c or
|
||||
dsm or
|
||||
tdes or
|
||||
tbuf or
|
||||
tstat or
|
||||
rdes or
|
||||
rbuf or
|
||||
rstat)
|
||||
begin : blesel_proc
|
||||
if (dsm_c == DSM_CH1 | dsm == DSM_CH1)
|
||||
begin
|
||||
if ((tbuf & ble) |
|
||||
((tdes | tstat) & dbo))
|
||||
begin
|
||||
blesel_c <= 1'b1 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
blesel_c <= 1'b0 ;
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
if ((rbuf & ble) |
|
||||
((rdes | rstat) & dbo))
|
||||
begin
|
||||
blesel_c <= 1'b1 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
blesel_c <= 1'b0 ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(dsm_c or
|
||||
dsm or
|
||||
req1 or
|
||||
write1 or
|
||||
tcnt1 or
|
||||
addr1 or
|
||||
datai1 or
|
||||
req2 or
|
||||
write2 or
|
||||
tcnt2 or
|
||||
addr2 or
|
||||
datai2)
|
||||
begin : chmux_proc
|
||||
if (dsm_c == DSM_CH1 | dsm == DSM_CH1)
|
||||
begin
|
||||
req_c <= req1 ;
|
||||
write_c <= write1 ;
|
||||
tcnt_c <= tcnt1 ;
|
||||
saddr_c <= addr1 ;
|
||||
datai_c <= {{((DATAWIDTH_MAX+1)-DATAWIDTH){1'b0}},datai1} ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
req_c <= req2 ;
|
||||
write_c <= write2 ;
|
||||
tcnt_c <= tcnt2 ;
|
||||
saddr_c <= addr2 ;
|
||||
datai_c <= {{((DATAWIDTH_MAX+1)-DATAWIDTH){1'b0}},datai2} ;
|
||||
end
|
||||
end
|
||||
|
||||
assign datai_max_c = {dzero[DATAWIDTH_MAX+1:DATAWIDTH],datai_c};
|
||||
|
||||
always @(datai_max_c or blesel_c)
|
||||
begin : dataoble_proc
|
||||
case (DATAWIDTH)
|
||||
32 :
|
||||
begin
|
||||
if (blesel_c)
|
||||
begin
|
||||
dataoble_c <= {datai_max_c[ 7: 0],
|
||||
datai_max_c[15: 8],
|
||||
datai_max_c[23:16],
|
||||
datai_max_c[31:24]};
|
||||
end
|
||||
else
|
||||
begin
|
||||
dataoble_c <= datai_max_c[31:0];
|
||||
end
|
||||
end
|
||||
16 :
|
||||
begin
|
||||
if (blesel_c)
|
||||
begin
|
||||
dataoble_c <= {datai_max_c[7 :0],
|
||||
datai_max_c[15:8]};
|
||||
end
|
||||
else
|
||||
begin
|
||||
dataoble_c <= datai_max_c[15:0];
|
||||
end
|
||||
end
|
||||
default :
|
||||
begin
|
||||
dataoble_c <= datai_max_c[7:0];
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
assign datai_max = {dzero[DATAWIDTH_MAX+1:DATAWIDTH],datai};
|
||||
|
||||
always @(datai_max or blesel_c)
|
||||
begin : dataible_proc
|
||||
case (DATAWIDTH)
|
||||
32 :
|
||||
begin
|
||||
if (blesel_c)
|
||||
begin
|
||||
dataible_c <= {datai_max[ 7: 0],
|
||||
datai_max[15: 8],
|
||||
datai_max[23:16],
|
||||
datai_max[31:24]};
|
||||
end
|
||||
else
|
||||
begin
|
||||
dataible_c <= datai_max[31:0];
|
||||
end
|
||||
end
|
||||
16 :
|
||||
begin
|
||||
if (blesel_c)
|
||||
begin
|
||||
dataible_c <= {datai_max[7 :0],
|
||||
datai_max[15:8]};
|
||||
end
|
||||
else
|
||||
begin
|
||||
dataible_c <= datai_max[15:0];
|
||||
end
|
||||
end
|
||||
default :
|
||||
begin
|
||||
dataible_c <= datai_max[7:0];
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : msmbcnt_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
msmbcnt <= {FIFODEPTH_MAX{1'b0}} ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (!idatareq)
|
||||
begin
|
||||
msmbcnt <= tcnt_c ;
|
||||
end
|
||||
else if (dataack & idatareq)
|
||||
begin
|
||||
msmbcnt <= msmbcnt - 1 ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : datarw_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
datarw <= 1'b1 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (req_c)
|
||||
begin
|
||||
datarw <= ~write_c ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : idatareq_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
idatareq <= 1'b0 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (eob & dataack & idatareq)
|
||||
begin
|
||||
idatareq <= 1'b0 ;
|
||||
end
|
||||
else if (req1 | req2)
|
||||
begin
|
||||
idatareq <= 1'b1 ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign datareq = idatareq ;
|
||||
|
||||
always @(idatareq or
|
||||
dataack or
|
||||
req1 or
|
||||
req2 or
|
||||
eob
|
||||
)
|
||||
begin : idatareqc_comb_proc
|
||||
if (eob & dataack & idatareq)
|
||||
begin
|
||||
idatareqc <= 1'b0 ;
|
||||
end
|
||||
else if (req1 | req2)
|
||||
begin
|
||||
idatareqc <= 1'b1 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
idatareqc <= idatareq ;
|
||||
end
|
||||
end
|
||||
|
||||
assign datareqc = idatareqc ;
|
||||
|
||||
assign dataeob = eob ;
|
||||
|
||||
assign dataeobc = eobc ;
|
||||
|
||||
assign datao1 = dataible_c ;
|
||||
|
||||
assign datao2 = dataible_c ;
|
||||
|
||||
assign datao = dataoble_c ;
|
||||
|
||||
always @(dataack or
|
||||
idatareq or
|
||||
addr or
|
||||
saddr_c or
|
||||
req_c or
|
||||
dsm)
|
||||
begin : addr_proc
|
||||
if (dataack & idatareq)
|
||||
begin
|
||||
case (DATAWIDTH)
|
||||
8 :
|
||||
begin
|
||||
addr_c <= addr + 1 ;
|
||||
end
|
||||
16 :
|
||||
begin
|
||||
addr_c <= {addr[DATADEPTH - 1:1] + 1, 1'b0} ;
|
||||
end
|
||||
default :
|
||||
begin
|
||||
addr_c <= {addr[DATADEPTH - 1:2] + 1, 2'b00} ;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
else if (req_c & dsm == DSM_IDLE)
|
||||
begin
|
||||
addr_c <= saddr_c ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
addr_c <= addr ;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : addr_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
addr <= {DATADEPTH{1'b1}} ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
addr <= addr_c ;
|
||||
end
|
||||
end
|
||||
|
||||
assign dataaddr = addr ;
|
||||
|
||||
assign idataaddr = addr ;
|
||||
|
||||
assign ack1 = (dataack & dsm == DSM_CH1) ? 1'b1 : 1'b0 ;
|
||||
|
||||
assign ack2 = (dataack & dsm == DSM_CH2) ? 1'b1 : 1'b0 ;
|
||||
|
||||
always @(posedge clk)
|
||||
begin : eob_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
eob <= 1'b0 ;
|
||||
end
|
||||
else if (req_c | idatareq)
|
||||
begin
|
||||
if ((idatareq &
|
||||
(msmbcnt == fzero |
|
||||
msmbcnt == {fzero[FIFODEPTH_MAX-1:1], 1'b1} |
|
||||
(msmbcnt == {fzero[FIFODEPTH_MAX-1:2], 2'b10} & dataack)))
|
||||
|
|
||||
(!idatareq &
|
||||
(tcnt_c == fzero |
|
||||
tcnt_c == {fzero[FIFODEPTH_MAX-1:1], 1'b1})))
|
||||
begin
|
||||
eob <= 1'b1 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
eob <= 1'b0 ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(req_c or
|
||||
idatareq or
|
||||
msmbcnt or
|
||||
dataack or
|
||||
tcnt_c or
|
||||
fzero or
|
||||
eob)
|
||||
begin : eob_comb_proc
|
||||
if (req_c | idatareq)
|
||||
begin
|
||||
if ((idatareq &
|
||||
(msmbcnt == fzero |
|
||||
msmbcnt == {fzero[FIFODEPTH_MAX-1:1], 1'b1} |
|
||||
(msmbcnt == {fzero[FIFODEPTH_MAX-1:2], 2'b10} & dataack)))
|
||||
|
|
||||
(!idatareq &
|
||||
(tcnt_c == fzero |
|
||||
tcnt_c == {fzero[FIFODEPTH_MAX-1:1], 1'b1})))
|
||||
begin
|
||||
eobc <= 1'b1 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
eobc <= 1'b0 ;
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
eobc <= eob;
|
||||
end
|
||||
end
|
||||
|
||||
assign eob1 = eob ;
|
||||
|
||||
assign eob2 = eob ;
|
||||
|
||||
assign fzero = {FIFODEPTH_MAX{1'b0}} ;
|
||||
|
||||
assign dzero = {(DATAWIDTH_MAX+1){1'b0}} ;
|
||||
|
||||
endmodule
|
368
resources/soc/rtl/MAC/ethernet_top.v
Normal file
368
resources/soc/rtl/MAC/ethernet_top.v
Normal file
@ -0,0 +1,368 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
module ethernet_top
|
||||
(
|
||||
hclk,
|
||||
hrst_,
|
||||
mawid_o ,
|
||||
mawaddr_o ,
|
||||
mawlen_o ,
|
||||
mawsize_o ,
|
||||
mawburst_o ,
|
||||
mawlock_o ,
|
||||
mawcache_o ,
|
||||
mawprot_o ,
|
||||
mawvalid_o ,
|
||||
mawready_i ,
|
||||
mwid_o ,
|
||||
mwdata_o ,
|
||||
mwstrb_o ,
|
||||
mwlast_o ,
|
||||
mwvalid_o ,
|
||||
mwready_i ,
|
||||
mbid_i ,
|
||||
mbresp_i ,
|
||||
mbvalid_i ,
|
||||
mbready_o ,
|
||||
marid_o ,
|
||||
maraddr_o ,
|
||||
marlen_o ,
|
||||
marsize_o ,
|
||||
marburst_o ,
|
||||
marlock_o ,
|
||||
marcache_o ,
|
||||
marprot_o ,
|
||||
marvalid_o ,
|
||||
marready_i ,
|
||||
mrid_i ,
|
||||
mrdata_i ,
|
||||
mrresp_i ,
|
||||
mrlast_i ,
|
||||
mrvalid_i ,
|
||||
mrready_o ,
|
||||
sawid_i ,
|
||||
sawaddr_i ,
|
||||
sawlen_i ,
|
||||
sawsize_i ,
|
||||
sawburst_i ,
|
||||
sawlock_i ,
|
||||
sawcache_i ,
|
||||
sawprot_i ,
|
||||
sawvalid_i ,
|
||||
sawready_o ,
|
||||
swid_i ,
|
||||
swdata_i ,
|
||||
swstrb_i ,
|
||||
swlast_i ,
|
||||
swvalid_i ,
|
||||
swready_o ,
|
||||
sbid_o ,
|
||||
sbresp_o ,
|
||||
sbvalid_o ,
|
||||
sbready_i ,
|
||||
sarid_i ,
|
||||
saraddr_i ,
|
||||
sarlen_i ,
|
||||
sarsize_i ,
|
||||
sarburst_i ,
|
||||
sarlock_i ,
|
||||
sarcache_i ,
|
||||
sarprot_i ,
|
||||
sarvalid_i ,
|
||||
sarready_o ,
|
||||
srid_o ,
|
||||
srdata_o ,
|
||||
srresp_o ,
|
||||
srlast_o ,
|
||||
srvalid_o ,
|
||||
srready_i ,
|
||||
|
||||
interrupt_0,
|
||||
|
||||
mtxclk_0,
|
||||
mtxen_0,
|
||||
mtxd_0,
|
||||
mtxerr_0,
|
||||
mrxclk_0,
|
||||
mrxdv_0,
|
||||
mrxd_0,
|
||||
mrxerr_0,
|
||||
mcoll_0,
|
||||
mcrs_0,
|
||||
mdc_0,
|
||||
md_i_0,
|
||||
md_o_0,
|
||||
md_oe_0
|
||||
);
|
||||
|
||||
input hclk;
|
||||
input hrst_;
|
||||
|
||||
output [ 3:0] mawid_o ;
|
||||
output [ 31:0] mawaddr_o ;
|
||||
output [ 3:0] mawlen_o ;
|
||||
output [ 2:0] mawsize_o ;
|
||||
output [ 1:0] mawburst_o ;
|
||||
output [ 1:0] mawlock_o ;
|
||||
output [ 3:0] mawcache_o ;
|
||||
output [ 2:0] mawprot_o ;
|
||||
output mawvalid_o ;
|
||||
input mawready_i ;
|
||||
output [ 3:0] mwid_o ;
|
||||
output [ 31:0] mwdata_o ;
|
||||
output [ 3:0] mwstrb_o ;
|
||||
output mwlast_o ;
|
||||
output mwvalid_o ;
|
||||
input mwready_i ;
|
||||
input [ 3:0] mbid_i ;
|
||||
input [ 1:0] mbresp_i ;
|
||||
input mbvalid_i ;
|
||||
output mbready_o ;
|
||||
output [ 3:0] marid_o ;
|
||||
output [ 31:0] maraddr_o ;
|
||||
output [ 3:0] marlen_o ;
|
||||
output [ 2:0] marsize_o ;
|
||||
output [ 1:0] marburst_o ;
|
||||
output [ 1:0] marlock_o ;
|
||||
output [ 3:0] marcache_o ;
|
||||
output [ 2:0] marprot_o ;
|
||||
output marvalid_o ;
|
||||
input marready_i ;
|
||||
input [ 3:0] mrid_i ;
|
||||
input [ 31:0] mrdata_i ;
|
||||
input [ 1:0] mrresp_i ;
|
||||
input mrlast_i ;
|
||||
input mrvalid_i ;
|
||||
output mrready_o ;
|
||||
|
||||
input [ 3:0] sawid_i ;
|
||||
input [ 31:0] sawaddr_i ;
|
||||
input [ 3:0] sawlen_i ;
|
||||
input [ 2:0] sawsize_i ;
|
||||
input [ 1:0] sawburst_i ;
|
||||
input [ 1:0] sawlock_i ;
|
||||
input [ 3:0] sawcache_i ;
|
||||
input [ 2:0] sawprot_i ;
|
||||
input sawvalid_i ;
|
||||
output sawready_o ;
|
||||
input [ 3:0] swid_i ;
|
||||
input [ 31:0] swdata_i ;
|
||||
input [ 3:0] swstrb_i ;
|
||||
input swlast_i ;
|
||||
input swvalid_i ;
|
||||
output swready_o ;
|
||||
output [ 3:0] sbid_o ;
|
||||
output [ 1:0] sbresp_o ;
|
||||
output sbvalid_o ;
|
||||
input sbready_i ;
|
||||
input [ 3:0] sarid_i ;
|
||||
input [ 31:0] saraddr_i ;
|
||||
input [ 3:0] sarlen_i ;
|
||||
input [ 2:0] sarsize_i ;
|
||||
input [ 1:0] sarburst_i ;
|
||||
input [ 1:0] sarlock_i ;
|
||||
input [ 3:0] sarcache_i ;
|
||||
input [ 2:0] sarprot_i ;
|
||||
input sarvalid_i ;
|
||||
output sarready_o ;
|
||||
output [ 3:0] srid_o ;
|
||||
output [ 31:0] srdata_o ;
|
||||
output [ 1:0] srresp_o ;
|
||||
output srlast_o ;
|
||||
output srvalid_o ;
|
||||
input srready_i ;
|
||||
|
||||
input mtxclk_0;
|
||||
output [3:0] mtxd_0;
|
||||
output mtxen_0;
|
||||
output mtxerr_0;
|
||||
|
||||
input mrxclk_0;
|
||||
input [3:0] mrxd_0;
|
||||
input mrxdv_0;
|
||||
input mrxerr_0;
|
||||
|
||||
input mcoll_0;
|
||||
input mcrs_0;
|
||||
|
||||
input md_i_0;
|
||||
output mdc_0;
|
||||
output md_o_0;
|
||||
output md_oe_0;
|
||||
|
||||
output interrupt_0;
|
||||
|
||||
|
||||
`define MAHBDATAWIDTH 32
|
||||
`define TFIFODEPTH 9
|
||||
`define RFIFODEPTH 9
|
||||
`define ADDRDEPTH 6
|
||||
|
||||
wire [`MAHBDATAWIDTH - 1:0] trdata_0;
|
||||
wire twe_0;
|
||||
wire [`TFIFODEPTH - 1:0] twaddr_0;
|
||||
wire [`TFIFODEPTH - 1:0] traddr_0;
|
||||
wire [`MAHBDATAWIDTH - 1:0] twdata_0;
|
||||
|
||||
wire [`MAHBDATAWIDTH - 1:0] rrdata_0;
|
||||
wire rwe_0;
|
||||
wire [`RFIFODEPTH - 1:0] rwaddr_0;
|
||||
wire [`RFIFODEPTH - 1:0] rraddr_0;
|
||||
wire [`MAHBDATAWIDTH - 1:0] rwdata_0;
|
||||
|
||||
|
||||
mac_top u_mac_top_0
|
||||
(
|
||||
.hclk(hclk),
|
||||
.hrst_(hrst_),
|
||||
|
||||
.mawid_o (mawid_o ),
|
||||
.mawaddr_o (mawaddr_o ),
|
||||
.mawlen_o (mawlen_o ),
|
||||
.mawsize_o (mawsize_o ),
|
||||
.mawburst_o (mawburst_o ),
|
||||
.mawlock_o (mawlock_o ),
|
||||
.mawcache_o (mawcache_o ),
|
||||
.mawprot_o (mawprot_o ),
|
||||
.mawvalid_o (mawvalid_o ),
|
||||
.mawready_i (mawready_i ),
|
||||
.mwid_o (mwid_o ),
|
||||
.mwdata_o (mwdata_o ),
|
||||
.mwstrb_o (mwstrb_o ),
|
||||
.mwlast_o (mwlast_o ),
|
||||
.mwvalid_o (mwvalid_o ),
|
||||
.mwready_i (mwready_i ),
|
||||
.mbid_i (mbid_i ),
|
||||
.mbresp_i (mbresp_i ),
|
||||
.mbvalid_i (mbvalid_i ),
|
||||
.mbready_o (mbready_o ),
|
||||
.marid_o (marid_o ),
|
||||
.maraddr_o (maraddr_o ),
|
||||
.marlen_o (marlen_o ),
|
||||
.marsize_o (marsize_o ),
|
||||
.marburst_o (marburst_o ),
|
||||
.marlock_o (marlock_o ),
|
||||
.marcache_o (marcache_o ),
|
||||
.marprot_o (marprot_o ),
|
||||
.marvalid_o (marvalid_o ),
|
||||
.marready_i (marready_i ),
|
||||
.mrid_i (mrid_i ),
|
||||
.mrdata_i (mrdata_i ),
|
||||
.mrresp_i (mrresp_i ),
|
||||
.mrlast_i (mrlast_i ),
|
||||
.mrvalid_i (mrvalid_i ),
|
||||
.mrready_o (mrready_o ),
|
||||
.sawid_i (sawid_i ),
|
||||
.sawaddr_i (sawaddr_i ),
|
||||
.sawlen_i (sawlen_i ),
|
||||
.sawsize_i (sawsize_i ),
|
||||
.sawburst_i (sawburst_i ),
|
||||
.sawlock_i (sawlock_i ),
|
||||
.sawcache_i (sawcache_i ),
|
||||
.sawprot_i (sawprot_i ),
|
||||
.sawvalid_i (sawvalid_i ),
|
||||
.sawready_o (sawready_o ),
|
||||
.swid_i (swid_i ),
|
||||
.swdata_i (swdata_i ),
|
||||
.swstrb_i (swstrb_i ),
|
||||
.swlast_i (swlast_i ),
|
||||
.swvalid_i (swvalid_i ),
|
||||
.swready_o (swready_o ),
|
||||
.sbid_o (sbid_o ),
|
||||
.sbresp_o (sbresp_o ),
|
||||
.sbvalid_o (sbvalid_o ),
|
||||
.sbready_i (sbready_i ),
|
||||
.sarid_i (sarid_i ),
|
||||
.saraddr_i (saraddr_i ),
|
||||
.sarlen_i (sarlen_i ),
|
||||
.sarsize_i (sarsize_i ),
|
||||
.sarburst_i (sarburst_i ),
|
||||
.sarlock_i (sarlock_i ),
|
||||
.sarcache_i (sarcache_i ),
|
||||
.sarprot_i (sarprot_i ),
|
||||
.sarvalid_i (sarvalid_i ),
|
||||
.sarready_o (sarready_o ),
|
||||
.srid_o (srid_o ),
|
||||
.srdata_o (srdata_o ),
|
||||
.srresp_o (srresp_o ),
|
||||
.srlast_o (srlast_o ),
|
||||
.srvalid_o (srvalid_o ),
|
||||
.srready_i (srready_i ),
|
||||
|
||||
.interrupt(interrupt_0),
|
||||
|
||||
.mtxclk(mtxclk_0), .mtxen(mtxen_0), .mtxd(mtxd_0), .mtxerr(mtxerr_0),
|
||||
.mrxclk(mrxclk_0), .mrxdv(mrxdv_0), .mrxd(mrxd_0), .mrxerr(mrxerr_0),
|
||||
.mcoll(mcoll_0), .mcrs(mcrs_0),
|
||||
.mdc(mdc_0), .md_i(md_i_0), .md_o(md_o_0), .md_oe(md_oe_0),
|
||||
|
||||
.trdata(trdata_0),
|
||||
.twe(twe_0),
|
||||
.twaddr(twaddr_0),
|
||||
.traddr(traddr_0),
|
||||
.twdata(twdata_0),
|
||||
|
||||
.rrdata(rrdata_0),
|
||||
.rwe(rwe_0),
|
||||
.rwaddr(rwaddr_0),
|
||||
.rraddr(rraddr_0),
|
||||
.rwdata(rwdata_0)
|
||||
);
|
||||
|
||||
wire [31:0] douta_nc;
|
||||
dpram_512x32 dpram_512x32_tx(
|
||||
.clka (hclk ),
|
||||
.ena (twe_0 ),
|
||||
.wea (twe_0 ),
|
||||
.addra (twaddr_0),
|
||||
.dina (twdata_0),
|
||||
.clkb (mtxclk_0),
|
||||
.addrb (traddr_0),
|
||||
.doutb (trdata_0)
|
||||
);
|
||||
|
||||
wire [31:0] doutb_nc;
|
||||
dpram_512x32 dpram_512x32_rx(
|
||||
.clka (mrxclk_0),
|
||||
.ena (rwe_0 ),
|
||||
.wea (rwe_0 ),
|
||||
.addra (rwaddr_0),
|
||||
.dina (rwdata_0),
|
||||
.clkb (hclk ),
|
||||
.addrb (rraddr_0),
|
||||
.doutb (rrdata_0)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
862
resources/soc/rtl/MAC/mac.v
Normal file
862
resources/soc/rtl/MAC/mac.v
Normal file
@ -0,0 +1,862 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
module MAC (
|
||||
clkdma,
|
||||
clkcsr,
|
||||
rstcsr,
|
||||
clkt,
|
||||
clkr,
|
||||
rsttco,
|
||||
rstrco,
|
||||
interrupt,
|
||||
tps,
|
||||
rps,
|
||||
csrreq,
|
||||
csrrw,
|
||||
csrbe,
|
||||
csrdatai,
|
||||
csraddr,
|
||||
csrack,
|
||||
csrdatao,
|
||||
dataack,
|
||||
datareq,
|
||||
datareqc,
|
||||
datarw,
|
||||
dataeob,
|
||||
dataeobc,
|
||||
datai,
|
||||
dataaddr,
|
||||
datao,
|
||||
trdata,
|
||||
twe,
|
||||
twaddr,
|
||||
traddr,
|
||||
twdata,
|
||||
rrdata,
|
||||
rwe,
|
||||
rwaddr,
|
||||
rraddr,
|
||||
rwdata,
|
||||
frdata,
|
||||
fwe,
|
||||
fwaddr,
|
||||
fraddr,
|
||||
fwdata,
|
||||
match,
|
||||
matchval,
|
||||
matchen,
|
||||
matchdata,
|
||||
sdi,
|
||||
sclk,
|
||||
scs,
|
||||
sdo,
|
||||
rxer,
|
||||
rxdv,
|
||||
col,
|
||||
crs,
|
||||
rxd,
|
||||
txen,
|
||||
txer,
|
||||
txd,
|
||||
mdc,
|
||||
mdi,
|
||||
mdo,
|
||||
mden
|
||||
);
|
||||
|
||||
parameter CSRWIDTH = 32;
|
||||
parameter DATAWIDTH = 32;
|
||||
parameter DATADEPTH = 32;
|
||||
parameter TFIFODEPTH = 9;
|
||||
parameter RFIFODEPTH = 9;
|
||||
parameter TCDEPTH = 1;
|
||||
parameter RCDEPTH = 2;
|
||||
|
||||
`include "utility.v"
|
||||
|
||||
input clkdma;
|
||||
input clkcsr;
|
||||
input rstcsr;
|
||||
input clkt;
|
||||
input clkr;
|
||||
output rsttco;
|
||||
wire rsttco;
|
||||
output rstrco;
|
||||
wire rstrco;
|
||||
|
||||
output interrupt;
|
||||
wire interrupt;
|
||||
|
||||
output tps;
|
||||
wire tps;
|
||||
output rps;
|
||||
wire rps;
|
||||
|
||||
input csrreq;
|
||||
input csrrw;
|
||||
input [CSRWIDTH / 8 - 1:0] csrbe;
|
||||
input [CSRWIDTH - 1:0] csrdatai;
|
||||
input [7:0] csraddr;
|
||||
output csrack;
|
||||
wire csrack;
|
||||
output [CSRWIDTH - 1:0] csrdatao;
|
||||
wire [CSRWIDTH - 1:0] csrdatao;
|
||||
|
||||
input dataack;
|
||||
output datareq;
|
||||
wire datareq;
|
||||
output datareqc;
|
||||
wire datareqc;
|
||||
output datarw;
|
||||
wire datarw;
|
||||
output dataeob;
|
||||
wire dataeob;
|
||||
output dataeobc;
|
||||
wire dataeobc;
|
||||
input [DATAWIDTH - 1:0] datai;
|
||||
output [DATADEPTH - 1:0] dataaddr;
|
||||
wire [DATADEPTH - 1:0] dataaddr;
|
||||
output [DATAWIDTH - 1:0] datao;
|
||||
wire [DATAWIDTH - 1:0] datao;
|
||||
|
||||
input [DATAWIDTH - 1:0] trdata;
|
||||
output twe;
|
||||
wire twe;
|
||||
output [TFIFODEPTH - 1:0] twaddr;
|
||||
wire [TFIFODEPTH - 1:0] twaddr;
|
||||
output [TFIFODEPTH - 1:0] traddr;
|
||||
wire [TFIFODEPTH - 1:0] traddr;
|
||||
output [DATAWIDTH - 1:0] twdata;
|
||||
wire [DATAWIDTH - 1:0] twdata;
|
||||
|
||||
input [DATAWIDTH - 1:0] rrdata;
|
||||
output rwe;
|
||||
wire rwe;
|
||||
output [RFIFODEPTH - 1:0] rwaddr;
|
||||
wire [RFIFODEPTH - 1:0] rwaddr;
|
||||
output [RFIFODEPTH - 1:0] rraddr;
|
||||
wire [RFIFODEPTH - 1:0] rraddr;
|
||||
output [DATAWIDTH - 1:0] rwdata;
|
||||
wire [DATAWIDTH - 1:0] rwdata;
|
||||
|
||||
input [15:0] frdata;
|
||||
output fwe;
|
||||
wire fwe;
|
||||
output [ADDRDEPTH - 1:0] fwaddr;
|
||||
wire [ADDRDEPTH - 1:0] fwaddr;
|
||||
output [ADDRDEPTH - 1:0] fraddr;
|
||||
wire [ADDRDEPTH - 1:0] fraddr;
|
||||
output [15:0] fwdata;
|
||||
wire [15:0] fwdata;
|
||||
|
||||
input match;
|
||||
input matchval;
|
||||
output matchen;
|
||||
wire matchen;
|
||||
output [47:0] matchdata;
|
||||
wire [47:0] matchdata;
|
||||
|
||||
input sdi;
|
||||
output sclk;
|
||||
wire sclk;
|
||||
output scs;
|
||||
wire scs;
|
||||
output sdo;
|
||||
wire sdo;
|
||||
|
||||
input rxer;
|
||||
input rxdv;
|
||||
input col;
|
||||
input crs;
|
||||
input [MIIWIDTH - 1:0] rxd;
|
||||
output txen;
|
||||
wire txen;
|
||||
output txer;
|
||||
wire txer;
|
||||
output [MIIWIDTH - 1:0] txd;
|
||||
wire [MIIWIDTH - 1:0] txd;
|
||||
output mdc;
|
||||
wire mdc;
|
||||
input mdi;
|
||||
output mdo;
|
||||
wire mdo;
|
||||
output mden;
|
||||
wire mden;
|
||||
|
||||
|
||||
wire rstsoft;
|
||||
wire rsttc;
|
||||
wire rstrc;
|
||||
wire rstdmao;
|
||||
wire rstcsro;
|
||||
|
||||
wire [5:0] pbl;
|
||||
wire ac;
|
||||
wire dpd;
|
||||
wire [4:0] dsl;
|
||||
wire tpoll;
|
||||
wire [DATADEPTH - 1:0] tdbad;
|
||||
wire sf;
|
||||
wire [2:0] tm;
|
||||
wire fd;
|
||||
wire ble;
|
||||
wire dbo;
|
||||
wire ra;
|
||||
wire pm;
|
||||
wire pr;
|
||||
wire pb;
|
||||
wire rif;
|
||||
wire ho;
|
||||
wire hp;
|
||||
wire rpoll;
|
||||
wire rpollack;
|
||||
wire [DATADEPTH - 1:0] rdbad;
|
||||
|
||||
wire insert_en;
|
||||
|
||||
wire tdes;
|
||||
wire tbuf;
|
||||
wire tset;
|
||||
wire tstat;
|
||||
wire tu;
|
||||
wire [1:0] ft;
|
||||
wire rdes;
|
||||
wire rstat;
|
||||
wire ru;
|
||||
wire rcomp;
|
||||
wire rcompack;
|
||||
wire tcomp;
|
||||
wire tcompack;
|
||||
|
||||
wire [1:0] dma_priority;
|
||||
wire treq;
|
||||
wire twrite;
|
||||
wire [FIFODEPTH_MAX - 1:0] tcnt;
|
||||
wire [DATADEPTH - 1:0] taddr;
|
||||
wire [DATAWIDTH - 1:0] tdatai;
|
||||
wire tack;
|
||||
wire teob;
|
||||
wire [DATAWIDTH - 1:0] tdatao;
|
||||
wire rreq;
|
||||
wire rwrite;
|
||||
wire [FIFODEPTH_MAX - 1:0] rcnt;
|
||||
wire [DATADEPTH - 1:0] raddr;
|
||||
wire [DATAWIDTH - 1:0] rdatai;
|
||||
wire rack;
|
||||
wire reob;
|
||||
wire [DATAWIDTH - 1:0] rdatao;
|
||||
wire [DATADEPTH - 1:0] idataaddr;
|
||||
|
||||
wire tfifonf;
|
||||
wire tfifocnf;
|
||||
wire tfifoval;
|
||||
wire tfifowe;
|
||||
wire tfifoeof;
|
||||
wire [DATAWIDTH / 8 - 1:0] tfifobe;
|
||||
wire [DATAWIDTH - 1:0] tfifodata;
|
||||
wire [TFIFODEPTH - 1:0] tfifolev;
|
||||
wire [TFIFODEPTH - 1:0] tradg;
|
||||
|
||||
wire etiack;
|
||||
wire etireq;
|
||||
wire tcsne;
|
||||
wire tcachere;
|
||||
wire ic;
|
||||
wire ici;
|
||||
wire aci;
|
||||
wire dpdi;
|
||||
wire lo_o;
|
||||
wire nc_o;
|
||||
wire lc_o;
|
||||
wire ec_o;
|
||||
wire de_o;
|
||||
wire ur_o;
|
||||
wire [3:0] cc_o;
|
||||
wire lo_i;
|
||||
wire nc_i;
|
||||
wire lc_i;
|
||||
wire ec_i;
|
||||
wire de_i;
|
||||
wire ur_i;
|
||||
wire [3:0] cc_i;
|
||||
|
||||
wire tpollack;
|
||||
wire tdbadc;
|
||||
wire [DATADEPTH - 1:0] statado;
|
||||
wire [DATADEPTH - 1:0] statadi;
|
||||
|
||||
wire sofreq;
|
||||
wire eofreq;
|
||||
wire [DATAWIDTH / 8 - 1:0] be;
|
||||
wire [TFIFODEPTH - 1:0] eofad;
|
||||
wire [TFIFODEPTH - 1:0] twadg;
|
||||
wire tireq;
|
||||
wire tiack;
|
||||
wire winp;
|
||||
|
||||
wire coll;
|
||||
wire carrier;
|
||||
wire bkoff;
|
||||
wire tpend;
|
||||
wire tprog;
|
||||
wire preamble;
|
||||
|
||||
wire tcsreq;
|
||||
wire tcsack;
|
||||
|
||||
wire stopt;
|
||||
wire stoptc;
|
||||
wire stoptfifo;
|
||||
wire stoptlsm;
|
||||
|
||||
wire [RFIFODEPTH - 1:0] rradg;
|
||||
wire [RFIFODEPTH - 1:0] rwadg;
|
||||
wire rfifore;
|
||||
wire [DATAWIDTH - 1:0] rfifodata;
|
||||
wire rcachere;
|
||||
wire rcachene;
|
||||
wire rcachenf;
|
||||
wire [DATAWIDTH - 1:0] irwdata;
|
||||
wire irwe;
|
||||
|
||||
wire riack;
|
||||
wire ren;
|
||||
wire rireq;
|
||||
wire ff;
|
||||
wire rf;
|
||||
wire mf;
|
||||
wire db;
|
||||
wire re;
|
||||
wire ce;
|
||||
wire tl;
|
||||
wire ftp;
|
||||
wire ov;
|
||||
wire cs;
|
||||
wire [13:0] length;
|
||||
wire rprog;
|
||||
wire rcpoll;
|
||||
|
||||
|
||||
wire ff_o;
|
||||
wire rf_o;
|
||||
wire mf_o;
|
||||
wire tl_o;
|
||||
wire re_o;
|
||||
wire db_o;
|
||||
wire ce_o;
|
||||
wire ov_o;
|
||||
wire cs_o;
|
||||
wire [13:0] fl_o;
|
||||
|
||||
wire rdbadc;
|
||||
wire erireq;
|
||||
wire eriack;
|
||||
wire rbuf;
|
||||
|
||||
wire foclack;
|
||||
wire mfclack;
|
||||
wire oco;
|
||||
wire mfo;
|
||||
wire [10:0] focg;
|
||||
wire [15:0] mfcg;
|
||||
wire focl;
|
||||
wire mfcl;
|
||||
|
||||
wire stopr;
|
||||
wire stoprc;
|
||||
wire stoprfifo;
|
||||
wire stoprlsm;
|
||||
|
||||
wire rcsack;
|
||||
wire rcsreq;
|
||||
|
||||
DMA #(DATAWIDTH, DATADEPTH) U_DMA(
|
||||
.clk (clkdma),
|
||||
.rst (rstdmao),
|
||||
.dma_priority (dma_priority),
|
||||
.ble (ble),
|
||||
.dbo (dbo),
|
||||
.rdes (rdes),
|
||||
.rbuf (rbuf),
|
||||
.rstat (rstat),
|
||||
.tdes (tdes),
|
||||
.tbuf (tbuf),
|
||||
.tstat (tstat),
|
||||
.dataack (dataack),
|
||||
.datai (datai),
|
||||
.datareq (datareq),
|
||||
.datareqc (datareqc),
|
||||
.datarw (datarw),
|
||||
.dataeob (dataeob),
|
||||
.dataeobc (dataeobc),
|
||||
.datao (datao),
|
||||
.dataaddr (dataaddr),
|
||||
.idataaddr (idataaddr),
|
||||
.req1 (treq),
|
||||
.write1 (twrite),
|
||||
.tcnt1 (tcnt),
|
||||
.addr1 (taddr),
|
||||
.datai1 (tdatao),
|
||||
.ack1 (tack),
|
||||
.eob1 (teob),
|
||||
.datao1 (tdatai),
|
||||
.req2 (rreq),
|
||||
.write2 (rwrite),
|
||||
.tcnt2 (rcnt),
|
||||
.addr2 (raddr),
|
||||
.datai2 (rdatao),
|
||||
.ack2 (rack),
|
||||
.eob2 (reob),
|
||||
.datao2 (rdatai)
|
||||
);
|
||||
|
||||
TLSM #(DATAWIDTH, DATADEPTH, TFIFODEPTH) U_TLSM(
|
||||
.clk (clkdma),
|
||||
.rst (rstdmao),
|
||||
.fifonf (tfifonf),
|
||||
.fifocnf (tfifocnf),
|
||||
.fifoval (tfifoval),
|
||||
.fifowe (tfifowe),
|
||||
.fifoeof (tfifoeof),
|
||||
.fifobe (tfifobe),
|
||||
.fifodata (tfifodata),
|
||||
.fifolev (tfifolev),
|
||||
.ic (ici),
|
||||
.ac (aci),
|
||||
.dpd (dpdi),
|
||||
.statado (statadi),
|
||||
.csne (tcsne),
|
||||
.lo (lo_i),
|
||||
.nc (nc_i),
|
||||
.lc (lc_i),
|
||||
.ec (ec_i),
|
||||
.de (de_i),
|
||||
.ur (ur_i),
|
||||
.cc (cc_i),
|
||||
.cachere (tcachere),
|
||||
.statadi (statado),
|
||||
.dmaack (tack),
|
||||
.dmaeob (teob),
|
||||
.dmadatai (tdatai),
|
||||
.dmaaddr (idataaddr),
|
||||
.dmareq (treq),
|
||||
.dmawr (twrite),
|
||||
.dmacnt (tcnt),
|
||||
.dmaaddro (taddr),
|
||||
.dmadatao (tdatao),
|
||||
.fwe (fwe),
|
||||
.fdata (fwdata),
|
||||
.faddr (fwaddr),
|
||||
.dsl (dsl),
|
||||
.pbl (pbl),
|
||||
.poll (tpoll),
|
||||
.dbadc (tdbadc),
|
||||
.dbad (tdbad),
|
||||
.pollack (tpollack),
|
||||
.tcompack (tcompack),
|
||||
.tcomp (tcomp),
|
||||
.des (tdes),
|
||||
.fbuf (tbuf),
|
||||
.stat (tstat),
|
||||
.setp (tset),
|
||||
.tu (tu),
|
||||
.ft (ft),
|
||||
.stopi (stopt),
|
||||
.stopo (stoptlsm)
|
||||
);
|
||||
|
||||
TFIFO #(DATAWIDTH, DATADEPTH, TFIFODEPTH, TCDEPTH) U_TFIFO(
|
||||
.clk (clkdma),
|
||||
.rst (rstdmao),
|
||||
.ramwe (twe),
|
||||
.ramaddr (twaddr),
|
||||
.ramdata (twdata),
|
||||
.fifowe (tfifowe),
|
||||
.fifoeof (tfifoeof),
|
||||
.fifobe (tfifobe),
|
||||
.fifodata (tfifodata),
|
||||
.fifonf (tfifonf),
|
||||
.fifocnf (tfifocnf),
|
||||
.fifoval (tfifoval),
|
||||
.flev (tfifolev),
|
||||
.ici (ici),
|
||||
.dpdi (dpdi),
|
||||
.aci (aci),
|
||||
.statadi (statadi),
|
||||
.cachere (tcachere),
|
||||
.deo (de_i),
|
||||
.lco (lc_i),
|
||||
.loo (lo_i),
|
||||
.nco (nc_i),
|
||||
.eco (ec_i),
|
||||
.ico (ic),
|
||||
.uro (ur_i),
|
||||
.csne (tcsne),
|
||||
.cco (cc_i),
|
||||
.statado (statado),
|
||||
.sofreq (sofreq),
|
||||
.eofreq (eofreq),
|
||||
.dpdo (dpd),
|
||||
.aco (ac),
|
||||
.beo (be),
|
||||
.eofad (eofad),
|
||||
.wadg (twadg),
|
||||
.tireq (tireq),
|
||||
.winp (winp),
|
||||
.dei (de_o),
|
||||
.lci (lc_o),
|
||||
.loi (lo_o),
|
||||
.nci (nc_o),
|
||||
.eci (ec_o),
|
||||
.uri (ur_o),
|
||||
.cci (cc_o),
|
||||
.radg (tradg),
|
||||
.tiack (tiack),
|
||||
.sf (sf),
|
||||
.fdp (fd),
|
||||
.tm (tm),
|
||||
.pbl (pbl),
|
||||
.etiack (etiack),
|
||||
.etireq (etireq),
|
||||
.stopi (stopt),
|
||||
.stopo (stoptfifo)
|
||||
);
|
||||
|
||||
TC #(TFIFODEPTH, DATAWIDTH) U_TC(
|
||||
.clk (clkt),
|
||||
.rst (rsttc),
|
||||
.txen (txen),
|
||||
.txer (txer),
|
||||
.txd (txd),
|
||||
.ramdata (trdata),
|
||||
.ramaddr (traddr),
|
||||
.wadg (twadg),
|
||||
.radg (tradg),
|
||||
.dpd (dpd),
|
||||
.ac (ac),
|
||||
.sofreq (sofreq),
|
||||
.eofreq (eofreq),
|
||||
.tiack (tiack),
|
||||
.lastbe (be),
|
||||
.eofadg (eofad),
|
||||
.tireq (tireq),
|
||||
.ur (ur_o),
|
||||
.de (de_o),
|
||||
.coll (coll),
|
||||
.carrier (carrier),
|
||||
.bkoff (bkoff),
|
||||
.tpend (tpend),
|
||||
.tprog (tprog),
|
||||
.preamble (preamble),
|
||||
.stopi (stopt),
|
||||
.stopo (stoptc),
|
||||
.tcsack (tcsack),
|
||||
.tcsreq (tcsreq)
|
||||
);
|
||||
|
||||
BD U_BD(
|
||||
.clk (clkt),
|
||||
.rst (rsttc),
|
||||
.col (col),
|
||||
.crs (crs),
|
||||
.fdp (fd),
|
||||
.tprog (tprog),
|
||||
.preamble (preamble),
|
||||
.tpend (tpend),
|
||||
.winp (winp),
|
||||
.tiack (tiack),
|
||||
.coll (coll),
|
||||
.carrier (carrier),
|
||||
.bkoff (bkoff),
|
||||
.lc (lc_o),
|
||||
.lo (lo_o),
|
||||
.nc (nc_o),
|
||||
.ec (ec_o),
|
||||
.cc (cc_o)
|
||||
);
|
||||
|
||||
|
||||
RC #(RFIFODEPTH, DATAWIDTH) U_RC(
|
||||
.clk (clkr),
|
||||
.rst (rstrc),
|
||||
.col (col),
|
||||
.rxdv (rxdv),
|
||||
.rxer (rxer),
|
||||
.rxd (rxd),
|
||||
.ramwe (irwe),
|
||||
.ramaddr (rwaddr),
|
||||
.ramdata (irwdata),
|
||||
.fdata (frdata),
|
||||
.faddr (fraddr),
|
||||
.cachenf (rcachenf),
|
||||
.radg (rradg),
|
||||
.wadg (rwadg),
|
||||
.rprog (rprog),
|
||||
.rcpoll (rcpoll),
|
||||
.riack (riack),
|
||||
.ren (ren),
|
||||
.ra (ra),
|
||||
.pm (pm),
|
||||
.pr (pr),
|
||||
.pb (pb),
|
||||
.rif (rif),
|
||||
.ho (ho),
|
||||
.hp (hp),
|
||||
.rireq (rireq),
|
||||
.ff (ff),
|
||||
.rf (rf),
|
||||
.mf (mf),
|
||||
.db (db),
|
||||
.re (re),
|
||||
.ce (ce),
|
||||
.tl (tl),
|
||||
.ftp (ftp),
|
||||
.ov (ov),
|
||||
.cs (cs),
|
||||
.length (length),
|
||||
.match (match),
|
||||
.matchval (matchval),
|
||||
.matchen (matchen),
|
||||
.matchdata (matchdata),
|
||||
.focl (focl),
|
||||
.foclack (foclack),
|
||||
.oco (oco),
|
||||
.focg (focg),
|
||||
.mfcl (mfcl),
|
||||
.mfclack (mfclack),
|
||||
.mfo (mfo),
|
||||
.mfcg (mfcg),
|
||||
.stopi (stopr),
|
||||
.stopo (stoprc),
|
||||
.rcsack (rcsack),
|
||||
.rcsreq (rcsreq),
|
||||
.insert_en_i (insert_en)
|
||||
);
|
||||
|
||||
RFIFO #(DATAWIDTH, DATADEPTH, RFIFODEPTH, RCDEPTH) U_RFIFO(
|
||||
.clk (clkdma),
|
||||
.rst (rstdmao),
|
||||
.ramdata (rrdata),
|
||||
.ramaddr (rraddr),
|
||||
.fifore (rfifore),
|
||||
.ffo (ff_o),
|
||||
.rfo (rf_o),
|
||||
.mfo (mf_o),
|
||||
.tlo (tl_o),
|
||||
.reo (re_o),
|
||||
.dbo (db_o),
|
||||
.ceo (ce_o),
|
||||
.ovo (ov_o),
|
||||
.cso (cs_o),
|
||||
.flo (fl_o),
|
||||
.fifodata (rfifodata),
|
||||
.cachere (rcachere),
|
||||
.cachene (rcachene),
|
||||
.cachenf (rcachenf),
|
||||
.radg (rradg),
|
||||
.rireq (rireq),
|
||||
.ffi (ff),
|
||||
.rfi (rf),
|
||||
.mfi (mf),
|
||||
.tli (tl),
|
||||
.rei (re),
|
||||
.dbi (db),
|
||||
.cei (ce),
|
||||
.ovi (ov),
|
||||
.csi (cs),
|
||||
.fli (length),
|
||||
.wadg (rwadg),
|
||||
.riack (riack)
|
||||
);
|
||||
|
||||
RLSM #(DATAWIDTH, DATADEPTH, RFIFODEPTH) U_RLSM(
|
||||
.clk (clkdma),
|
||||
.rst (rstdmao),
|
||||
.fifodata (rfifodata),
|
||||
.fifore (rfifore),
|
||||
.cachere (rcachere),
|
||||
.dmaack (rack),
|
||||
.dmaeob (reob),
|
||||
.dmadatai (rdatai),
|
||||
.dmaaddr (idataaddr),
|
||||
.dmareq (rreq),
|
||||
.dmawr (rwrite),
|
||||
.dmacnt (rcnt),
|
||||
.dmaaddro (raddr),
|
||||
.dmadatao (rdatao),
|
||||
.rprog (rprog),
|
||||
.rcpoll (rcpoll),
|
||||
.fifocne (rcachene),
|
||||
.ff (ff_o),
|
||||
.rf (rf_o),
|
||||
.mf (mf_o),
|
||||
.db (db_o),
|
||||
.re (re_o),
|
||||
.ce (ce_o),
|
||||
.tl (tl_o),
|
||||
.ftp (ftp),
|
||||
.ov (ov_o),
|
||||
.cs (cs_o),
|
||||
.length (fl_o),
|
||||
.pbl (pbl),
|
||||
.dsl (dsl),
|
||||
.rpoll (rpoll),
|
||||
.rdbadc (rdbadc),
|
||||
.rdbad (rdbad),
|
||||
.rpollack (rpollack),
|
||||
.bufack (eriack),
|
||||
.rcompack (rcompack),
|
||||
.des (rdes),
|
||||
.fbuf (rbuf),
|
||||
.stat (rstat),
|
||||
.ru (ru),
|
||||
.rcomp (rcomp),
|
||||
.bufcomp (erireq),
|
||||
.stopi (stopr),
|
||||
.stopo (stoprlsm),
|
||||
.insert_en_i (insert_en)
|
||||
);
|
||||
|
||||
CSR #(CSRWIDTH, DATAWIDTH, DATADEPTH, RFIFODEPTH, RCDEPTH) U_CSR(
|
||||
.clk (clkcsr),
|
||||
.rst (rstcsro),
|
||||
.interrupt (interrupt),
|
||||
.rstsofto (rstsoft),
|
||||
.csrreq (csrreq),
|
||||
.csrrw (csrrw),
|
||||
.csrbe (csrbe),
|
||||
.csraddr (csraddr),
|
||||
.csrdatai (csrdatai),
|
||||
.csrack (csrack),
|
||||
.csrdatao (csrdatao),
|
||||
.tprog (tprog),
|
||||
.tireq (tcomp),
|
||||
.unf (ur_i),
|
||||
.tiack (tcompack),
|
||||
.tcsreq (tcsreq),
|
||||
.tcsack (tcsack),
|
||||
.fd (fd),
|
||||
.ic (ic),
|
||||
.etireq (etireq),
|
||||
.etiack (etiack),
|
||||
.tm (tm),
|
||||
.sf (sf),
|
||||
.tset (tset),
|
||||
.tdes (tdes),
|
||||
.tbuf (tbuf),
|
||||
.tstat (tstat),
|
||||
.tu (tu),
|
||||
.tpollack (tpollack),
|
||||
.ft (ft),
|
||||
.tpoll (tpoll),
|
||||
.tdbadc (tdbadc),
|
||||
.tdbad (tdbad),
|
||||
.rireq (rcomp),
|
||||
.rcsreq (rcsreq),
|
||||
.rprog (rprog),
|
||||
.riack (rcompack),
|
||||
.rcsack (rcsack),
|
||||
.ren (ren),
|
||||
.ra (ra),
|
||||
.pm (pm),
|
||||
.pr (pr),
|
||||
.pb (pb),
|
||||
.rif (rif),
|
||||
.ho (ho),
|
||||
.hp (hp),
|
||||
.foclack (foclack),
|
||||
.mfclack (mfclack),
|
||||
.oco (oco),
|
||||
.mfo (mfo),
|
||||
.focg (focg),
|
||||
.mfcg (mfcg),
|
||||
.focl (focl),
|
||||
.mfcl (mfcl),
|
||||
.erireq (erireq),
|
||||
.ru (ru),
|
||||
.rpollack (rpollack),
|
||||
.rdes (rdes),
|
||||
.rbuf (rbuf),
|
||||
.rstat (rstat),
|
||||
.eriack (eriack),
|
||||
.rpoll (rpoll),
|
||||
.rdbadc (rdbadc),
|
||||
.rdbad (rdbad),
|
||||
.ble (ble),
|
||||
.dbo (dbo),
|
||||
.dma_priority (dma_priority),
|
||||
.pbl (pbl),
|
||||
.dsl (dsl),
|
||||
.stoptc (stoptc),
|
||||
.stoptlsm (stoptlsm),
|
||||
.stoptfifo (stoptfifo),
|
||||
.stopt (stopt),
|
||||
.tps (tps),
|
||||
.stoprc (stoprc),
|
||||
.stoprlsm (stoprlsm),
|
||||
.stopr (stopr),
|
||||
.rps (rps),
|
||||
.sdi (sdi),
|
||||
.sclk (sclk),
|
||||
.scs (scs),
|
||||
.sdo (sdo),
|
||||
.mdi (mdi),
|
||||
.mdc (mdc),
|
||||
.mdo (mdo),
|
||||
.mden (mden),
|
||||
.insert_en_o (insert_en)
|
||||
);
|
||||
|
||||
RSTC U_RSTC (
|
||||
.clkdma(clkdma),
|
||||
.clkcsr(clkcsr),
|
||||
.clkt(clkt),
|
||||
.clkr(clkr),
|
||||
.rstcsr(rstcsr),
|
||||
.rstsoft(rstsoft),
|
||||
.rsttc(rsttc),
|
||||
.rstrc(rstrc),
|
||||
.rstdmao(rstdmao),
|
||||
.rstcsro(rstcsro)
|
||||
);
|
||||
|
||||
assign rwe = irwe ;
|
||||
|
||||
assign rwdata = irwdata ;
|
||||
|
||||
assign rsttco = rsttc ;
|
||||
|
||||
assign rstrco = rstrc ;
|
||||
|
||||
endmodule
|
355
resources/soc/rtl/MAC/mac2axi.v
Normal file
355
resources/soc/rtl/MAC/mac2axi.v
Normal file
@ -0,0 +1,355 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
module MAC2AXI (
|
||||
mhclk,
|
||||
mhresetn,
|
||||
shclk,
|
||||
shresetn,
|
||||
|
||||
mawid_o ,
|
||||
mawaddr_o ,
|
||||
mawlen_o ,
|
||||
mawsize_o ,
|
||||
mawburst_o ,
|
||||
mawlock_o ,
|
||||
mawcache_o ,
|
||||
mawprot_o ,
|
||||
mawvalid_o ,
|
||||
mawready_i ,
|
||||
mwid_o ,
|
||||
mwdata_o ,
|
||||
mwstrb_o ,
|
||||
mwlast_o ,
|
||||
mwvalid_o ,
|
||||
mwready_i ,
|
||||
mbid_i ,
|
||||
mbresp_i ,
|
||||
mbvalid_i ,
|
||||
mbready_o ,
|
||||
marid_o ,
|
||||
maraddr_o ,
|
||||
marlen_o ,
|
||||
marsize_o ,
|
||||
marburst_o ,
|
||||
marlock_o ,
|
||||
marcache_o ,
|
||||
marprot_o ,
|
||||
marvalid_o ,
|
||||
marready_i ,
|
||||
mrid_i ,
|
||||
mrdata_i ,
|
||||
mrresp_i ,
|
||||
mrlast_i ,
|
||||
mrvalid_i ,
|
||||
mrready_o ,
|
||||
|
||||
sawid_i ,
|
||||
sawaddr_i ,
|
||||
sawlen_i ,
|
||||
sawsize_i ,
|
||||
sawburst_i ,
|
||||
sawlock_i ,
|
||||
sawcache_i ,
|
||||
sawprot_i ,
|
||||
sawvalid_i ,
|
||||
sawready_o ,
|
||||
swid_i ,
|
||||
swdata_i ,
|
||||
swstrb_i ,
|
||||
swlast_i ,
|
||||
swvalid_i ,
|
||||
swready_o ,
|
||||
sbid_o ,
|
||||
sbresp_o ,
|
||||
sbvalid_o ,
|
||||
sbready_i ,
|
||||
sarid_i ,
|
||||
saraddr_i ,
|
||||
sarlen_i ,
|
||||
sarsize_i ,
|
||||
sarburst_i ,
|
||||
sarlock_i ,
|
||||
sarcache_i ,
|
||||
sarprot_i ,
|
||||
sarvalid_i ,
|
||||
sarready_o ,
|
||||
srid_o ,
|
||||
srdata_o ,
|
||||
srresp_o ,
|
||||
srlast_o ,
|
||||
srvalid_o ,
|
||||
srready_i ,
|
||||
|
||||
datareq,
|
||||
datareqc,
|
||||
datarw,
|
||||
dataeob,
|
||||
dataeobc,
|
||||
dataaddr,
|
||||
datao,
|
||||
dataack,
|
||||
datai,
|
||||
rstcsr,
|
||||
csrack,
|
||||
csrdatao,
|
||||
csrreq,
|
||||
csrrw,
|
||||
csrbe,
|
||||
csrdatai,
|
||||
csraddr
|
||||
);
|
||||
|
||||
parameter MAXIDATAWIDTH = 32;
|
||||
parameter MAXIADDRESSWIDTH = 32;
|
||||
|
||||
parameter SAXIDATAWIDTH = 32;
|
||||
parameter SAXIADDRESSWIDTH = 32;
|
||||
|
||||
parameter MACDATAWIDTH = 32;
|
||||
parameter MACADDRESSWIDTH = 32;
|
||||
|
||||
parameter CSRDATAWIDTH = 32;
|
||||
parameter CSRADDRESSWIDTH = 8;
|
||||
|
||||
|
||||
input mhclk;
|
||||
input mhresetn;
|
||||
output [ 3:0] mawid_o ;
|
||||
output [ 31:0] mawaddr_o ;
|
||||
output [ 3:0] mawlen_o ;
|
||||
output [ 2:0] mawsize_o ;
|
||||
output [ 1:0] mawburst_o ;
|
||||
output [ 1:0] mawlock_o ;
|
||||
output [ 3:0] mawcache_o ;
|
||||
output [ 2:0] mawprot_o ;
|
||||
output mawvalid_o ;
|
||||
input mawready_i ;
|
||||
output [ 3:0] mwid_o ;
|
||||
output [ 31:0] mwdata_o ;
|
||||
output [ 3:0] mwstrb_o ;
|
||||
output mwlast_o ;
|
||||
output mwvalid_o ;
|
||||
input mwready_i ;
|
||||
input [ 3:0] mbid_i ;
|
||||
input [ 1:0] mbresp_i ;
|
||||
input mbvalid_i ;
|
||||
output mbready_o ;
|
||||
output [ 3:0] marid_o ;
|
||||
output [ 31:0] maraddr_o ;
|
||||
output [ 3:0] marlen_o ;
|
||||
output [ 2:0] marsize_o ;
|
||||
output [ 1:0] marburst_o ;
|
||||
output [ 1:0] marlock_o ;
|
||||
output [ 3:0] marcache_o ;
|
||||
output [ 2:0] marprot_o ;
|
||||
output marvalid_o ;
|
||||
input marready_i ;
|
||||
input [ 3:0] mrid_i ;
|
||||
input [ 31:0] mrdata_i ;
|
||||
input [ 1:0] mrresp_i ;
|
||||
input mrlast_i ;
|
||||
input mrvalid_i ;
|
||||
output mrready_o ;
|
||||
|
||||
input shclk;
|
||||
input shresetn;
|
||||
|
||||
input [ 3:0] sawid_i ;
|
||||
input [ 31:0] sawaddr_i ;
|
||||
input [ 3:0] sawlen_i ;
|
||||
input [ 2:0] sawsize_i ;
|
||||
input [ 1:0] sawburst_i ;
|
||||
input [ 1:0] sawlock_i ;
|
||||
input [ 3:0] sawcache_i ;
|
||||
input [ 2:0] sawprot_i ;
|
||||
input sawvalid_i ;
|
||||
output sawready_o ;
|
||||
input [ 3:0] swid_i ;
|
||||
input [ 31:0] swdata_i ;
|
||||
input [ 3:0] swstrb_i ;
|
||||
input swlast_i ;
|
||||
input swvalid_i ;
|
||||
output swready_o ;
|
||||
output [ 3:0] sbid_o ;
|
||||
output [ 1:0] sbresp_o ;
|
||||
output sbvalid_o ;
|
||||
input sbready_i ;
|
||||
input [ 3:0] sarid_i ;
|
||||
input [ 31:0] saraddr_i ;
|
||||
input [ 3:0] sarlen_i ;
|
||||
input [ 2:0] sarsize_i ;
|
||||
input [ 1:0] sarburst_i ;
|
||||
input [ 1:0] sarlock_i ;
|
||||
input [ 3:0] sarcache_i ;
|
||||
input [ 2:0] sarprot_i ;
|
||||
input sarvalid_i ;
|
||||
output sarready_o ;
|
||||
output [ 3:0] srid_o ;
|
||||
output [ 31:0] srdata_o ;
|
||||
output [ 1:0] srresp_o ;
|
||||
output srlast_o ;
|
||||
output srvalid_o ;
|
||||
input srready_i ;
|
||||
input datareq;
|
||||
input datareqc;
|
||||
input datarw;
|
||||
input dataeob;
|
||||
input dataeobc;
|
||||
input [MACADDRESSWIDTH - 1:0] dataaddr;
|
||||
input [MACDATAWIDTH - 1:0] datao;
|
||||
output dataack;
|
||||
wire dataack;
|
||||
output [MACDATAWIDTH - 1:0] datai;
|
||||
wire [MACDATAWIDTH - 1:0] datai;
|
||||
|
||||
|
||||
output rstcsr;
|
||||
wire rstcsr;
|
||||
input csrack;
|
||||
input [CSRDATAWIDTH - 1:0] csrdatao;
|
||||
output csrreq;
|
||||
wire csrreq;
|
||||
output csrrw;
|
||||
wire csrrw;
|
||||
output [CSRDATAWIDTH / 8 - 1:0] csrbe;
|
||||
wire [CSRDATAWIDTH / 8 - 1:0] csrbe;
|
||||
output [CSRDATAWIDTH - 1:0] csrdatai;
|
||||
wire [CSRDATAWIDTH - 1:0] csrdatai;
|
||||
output [CSRADDRESSWIDTH - 1:0] csraddr;
|
||||
wire [CSRADDRESSWIDTH - 1:0] csraddr;
|
||||
|
||||
|
||||
MACDATA2AXI
|
||||
#(MAXIDATAWIDTH, MAXIADDRESSWIDTH, MACDATAWIDTH, MACADDRESSWIDTH)
|
||||
U_MACDATA2AXI (
|
||||
.maclk (mhclk ),
|
||||
.maresetn (mhresetn ),
|
||||
.awid_o (mawid_o ),
|
||||
.awaddr_o (mawaddr_o ),
|
||||
.awlen_o (mawlen_o ),
|
||||
.awsize_o (mawsize_o ),
|
||||
.awburst_o (mawburst_o ),
|
||||
.awlock_o (mawlock_o ),
|
||||
.awcache_o (mawcache_o ),
|
||||
.awprot_o (mawprot_o ),
|
||||
.awvalid_o (mawvalid_o ),
|
||||
.awready_i (mawready_i ),
|
||||
.wid_o (mwid_o ),
|
||||
.wdata_o (mwdata_o ),
|
||||
.wstrb_o (mwstrb_o ),
|
||||
.wlast_o (mwlast_o ),
|
||||
.wvalid_o (mwvalid_o ),
|
||||
.wready_i (mwready_i ),
|
||||
.bid_i (mbid_i ),
|
||||
.bresp_i (mbresp_i ),
|
||||
.bvalid_i (mbvalid_i ),
|
||||
.bready_o (mbready_o ),
|
||||
.arid_o (marid_o ),
|
||||
.araddr_o (maraddr_o ),
|
||||
.arlen_o (marlen_o ),
|
||||
.arsize_o (marsize_o ),
|
||||
.arburst_o (marburst_o ),
|
||||
.arlock_o (marlock_o ),
|
||||
.arcache_o (marcache_o ),
|
||||
.arprot_o (marprot_o ),
|
||||
.arvalid_o (marvalid_o ),
|
||||
.arready_i (marready_i ),
|
||||
.rid_i (mrid_i ),
|
||||
.rdata_i (mrdata_i ),
|
||||
.rresp_i (mrresp_i ),
|
||||
.rlast_i (mrlast_i ),
|
||||
.rvalid_i (mrvalid_i ),
|
||||
.rready_o (mrready_o ),
|
||||
.datareq (datareq ),
|
||||
.datareqc (datareqc ),
|
||||
.datarw (datarw ),
|
||||
.dataeob (dataeob ),
|
||||
.dataeobc (dataeobc ),
|
||||
.dataaddr (dataaddr ),
|
||||
.datao (datao ),
|
||||
.dataack (dataack ),
|
||||
.datai (datai )
|
||||
);
|
||||
MACCSR2AXI
|
||||
#(SAXIDATAWIDTH, SAXIADDRESSWIDTH, CSRDATAWIDTH, CSRADDRESSWIDTH)
|
||||
U_MACCSR2AXI(
|
||||
.saclk (shclk ),
|
||||
.saresetn (shresetn ),
|
||||
.awid_i (sawid_i ),
|
||||
.awaddr_i (sawaddr_i ),
|
||||
.awlen_i (sawlen_i ),
|
||||
.awsize_i (sawsize_i ),
|
||||
.awburst_i (sawburst_i),
|
||||
.awlock_i (sawlock_i ),
|
||||
.awcache_i (sawcache_i),
|
||||
.awprot_i (sawprot_i ),
|
||||
.awvalid_i (sawvalid_i),
|
||||
.awready_o (sawready_o),
|
||||
.wid_i (swid_i ),
|
||||
.wdata_i (swdata_i ),
|
||||
.wstrb_i (swstrb_i ),
|
||||
.wlast_i (swlast_i ),
|
||||
.wvalid_i (swvalid_i ),
|
||||
.wready_o (swready_o ),
|
||||
.bid_o (sbid_o ),
|
||||
.bresp_o (sbresp_o ),
|
||||
.bvalid_o (sbvalid_o ),
|
||||
.bready_i (sbready_i ),
|
||||
.arid_i (sarid_i ),
|
||||
.araddr_i (saraddr_i ),
|
||||
.arlen_i (sarlen_i ),
|
||||
.arsize_i (sarsize_i ),
|
||||
.arburst_i (sarburst_i),
|
||||
.arlock_i (sarlock_i ),
|
||||
.arcache_i (sarcache_i),
|
||||
.arprot_i (sarprot_i ),
|
||||
.arvalid_i (sarvalid_i),
|
||||
.arready_o (sarready_o),
|
||||
.rid_o (srid_o ),
|
||||
.rdata_o (srdata_o ),
|
||||
.rresp_o (srresp_o ),
|
||||
.rlast_o (srlast_o ),
|
||||
.rvalid_o (srvalid_o ),
|
||||
.rready_i (srready_i ),
|
||||
.rstcsr (rstcsr ) ,
|
||||
.csrack (csrack ) ,
|
||||
.csrdatao (csrdatao ) ,
|
||||
.csrreq (csrreq ) ,
|
||||
.csrrw (csrrw ) ,
|
||||
.csrbe (csrbe ) ,
|
||||
.csrdatai (csrdatai ) ,
|
||||
.csraddr (csraddr )
|
||||
);
|
||||
|
||||
endmodule
|
522
resources/soc/rtl/MAC/mac_axi.v
Normal file
522
resources/soc/rtl/MAC/mac_axi.v
Normal file
@ -0,0 +1,522 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
module MAC_AXI (
|
||||
clkt,
|
||||
clkr,
|
||||
rsttco,
|
||||
rstrco,
|
||||
interrupt,
|
||||
tps,
|
||||
rps,
|
||||
mhclk,
|
||||
mhresetn,
|
||||
mawid_o ,
|
||||
mawaddr_o ,
|
||||
mawlen_o ,
|
||||
mawsize_o ,
|
||||
mawburst_o ,
|
||||
mawlock_o ,
|
||||
mawcache_o ,
|
||||
mawprot_o ,
|
||||
mawvalid_o ,
|
||||
mawready_i ,
|
||||
mwid_o ,
|
||||
mwdata_o ,
|
||||
mwstrb_o ,
|
||||
mwlast_o ,
|
||||
mwvalid_o ,
|
||||
mwready_i ,
|
||||
mbid_i ,
|
||||
mbresp_i ,
|
||||
mbvalid_i ,
|
||||
mbready_o ,
|
||||
marid_o ,
|
||||
maraddr_o ,
|
||||
marlen_o ,
|
||||
marsize_o ,
|
||||
marburst_o ,
|
||||
marlock_o ,
|
||||
marcache_o ,
|
||||
marprot_o ,
|
||||
marvalid_o ,
|
||||
marready_i ,
|
||||
mrid_i ,
|
||||
mrdata_i ,
|
||||
mrresp_i ,
|
||||
mrlast_i ,
|
||||
mrvalid_i ,
|
||||
mrready_o ,
|
||||
shclk,
|
||||
shresetn,
|
||||
sawid_i ,
|
||||
sawaddr_i ,
|
||||
sawlen_i ,
|
||||
sawsize_i ,
|
||||
sawburst_i ,
|
||||
sawlock_i ,
|
||||
sawcache_i ,
|
||||
sawprot_i ,
|
||||
sawvalid_i ,
|
||||
sawready_o ,
|
||||
swid_i ,
|
||||
swdata_i ,
|
||||
swstrb_i ,
|
||||
swlast_i ,
|
||||
swvalid_i ,
|
||||
swready_o ,
|
||||
sbid_o ,
|
||||
sbresp_o ,
|
||||
sbvalid_o ,
|
||||
sbready_i ,
|
||||
sarid_i ,
|
||||
saraddr_i ,
|
||||
sarlen_i ,
|
||||
sarsize_i ,
|
||||
sarburst_i ,
|
||||
sarlock_i ,
|
||||
sarcache_i ,
|
||||
sarprot_i ,
|
||||
sarvalid_i ,
|
||||
sarready_o ,
|
||||
srid_o ,
|
||||
srdata_o ,
|
||||
srresp_o ,
|
||||
srlast_o ,
|
||||
srvalid_o ,
|
||||
srready_i ,
|
||||
trdata,
|
||||
twe,
|
||||
twaddr,
|
||||
traddr,
|
||||
twdata,
|
||||
rrdata,
|
||||
rwe,
|
||||
rwaddr,
|
||||
rraddr,
|
||||
rwdata,
|
||||
frdata,
|
||||
fwe,
|
||||
fwaddr,
|
||||
fraddr,
|
||||
fwdata,
|
||||
match,
|
||||
matchval,
|
||||
matchen,
|
||||
matchdata,
|
||||
sdi,
|
||||
sclk,
|
||||
scs,
|
||||
sdo,
|
||||
rxer,
|
||||
rxdv,
|
||||
col,
|
||||
crs,
|
||||
rxd,
|
||||
txen,
|
||||
txer,
|
||||
txd,
|
||||
mdc,
|
||||
mdi,
|
||||
mdo,
|
||||
mden
|
||||
);
|
||||
|
||||
parameter MAXIADDRESSWIDTH = 32;
|
||||
parameter SAXIADDRESSWIDTH = 32;
|
||||
parameter TFIFODEPTH = 9;
|
||||
parameter RFIFODEPTH = 9;
|
||||
parameter TCDEPTH = 1;
|
||||
parameter RCDEPTH = 2;
|
||||
parameter MAXIDATAWIDTH = 32;
|
||||
parameter SAXIDATAWIDTH = 32;
|
||||
`include "utility.v"
|
||||
|
||||
|
||||
input clkt;
|
||||
input clkr;
|
||||
output rsttco;
|
||||
wire rsttco;
|
||||
output rstrco;
|
||||
wire rstrco;
|
||||
|
||||
|
||||
output interrupt;
|
||||
wire interrupt;
|
||||
|
||||
output tps;
|
||||
wire tps;
|
||||
output rps;
|
||||
wire rps;
|
||||
|
||||
input mhclk;
|
||||
input mhresetn;
|
||||
output [ 3:0] mawid_o ;
|
||||
output [ 31:0] mawaddr_o ;
|
||||
output [ 3:0] mawlen_o ;
|
||||
output [ 2:0] mawsize_o ;
|
||||
output [ 1:0] mawburst_o ;
|
||||
output [ 1:0] mawlock_o ;
|
||||
output [ 3:0] mawcache_o ;
|
||||
output [ 2:0] mawprot_o ;
|
||||
output mawvalid_o ;
|
||||
input mawready_i ;
|
||||
output [ 3:0] mwid_o ;
|
||||
output [ 31:0] mwdata_o ;
|
||||
output [ 3:0] mwstrb_o ;
|
||||
output mwlast_o ;
|
||||
output mwvalid_o ;
|
||||
input mwready_i ;
|
||||
input [ 3:0] mbid_i ;
|
||||
input [ 1:0] mbresp_i ;
|
||||
input mbvalid_i ;
|
||||
output mbready_o ;
|
||||
output [ 3:0] marid_o ;
|
||||
output [ 31:0] maraddr_o ;
|
||||
output [ 3:0] marlen_o ;
|
||||
output [ 2:0] marsize_o ;
|
||||
output [ 1:0] marburst_o ;
|
||||
output [ 1:0] marlock_o ;
|
||||
output [ 3:0] marcache_o ;
|
||||
output [ 2:0] marprot_o ;
|
||||
output marvalid_o ;
|
||||
input marready_i ;
|
||||
input [ 3:0] mrid_i ;
|
||||
input [ 31:0] mrdata_i ;
|
||||
input [ 1:0] mrresp_i ;
|
||||
input mrlast_i ;
|
||||
input mrvalid_i ;
|
||||
output mrready_o ;
|
||||
input shclk;
|
||||
input shresetn;
|
||||
|
||||
input [ 3:0] sawid_i ;
|
||||
input [ 31:0] sawaddr_i ;
|
||||
input [ 3:0] sawlen_i ;
|
||||
input [ 2:0] sawsize_i ;
|
||||
input [ 1:0] sawburst_i ;
|
||||
input [ 1:0] sawlock_i ;
|
||||
input [ 3:0] sawcache_i ;
|
||||
input [ 2:0] sawprot_i ;
|
||||
input sawvalid_i ;
|
||||
output sawready_o ;
|
||||
input [ 3:0] swid_i ;
|
||||
input [ 31:0] swdata_i ;
|
||||
input [ 3:0] swstrb_i ;
|
||||
input swlast_i ;
|
||||
input swvalid_i ;
|
||||
output swready_o ;
|
||||
output [ 3:0] sbid_o ;
|
||||
output [ 1:0] sbresp_o ;
|
||||
output sbvalid_o ;
|
||||
input sbready_i ;
|
||||
input [ 3:0] sarid_i ;
|
||||
input [ 31:0] saraddr_i ;
|
||||
input [ 3:0] sarlen_i ;
|
||||
input [ 2:0] sarsize_i ;
|
||||
input [ 1:0] sarburst_i ;
|
||||
input [ 1:0] sarlock_i ;
|
||||
input [ 3:0] sarcache_i ;
|
||||
input [ 2:0] sarprot_i ;
|
||||
input sarvalid_i ;
|
||||
output sarready_o ;
|
||||
output [ 3:0] srid_o ;
|
||||
output [ 31:0] srdata_o ;
|
||||
output [ 1:0] srresp_o ;
|
||||
output srlast_o ;
|
||||
output srvalid_o ;
|
||||
input srready_i ;
|
||||
input [MAXIDATAWIDTH - 1:0] trdata;
|
||||
output twe;
|
||||
wire twe;
|
||||
output [TFIFODEPTH - 1:0] twaddr;
|
||||
wire [TFIFODEPTH - 1:0] twaddr;
|
||||
output [TFIFODEPTH - 1:0] traddr;
|
||||
wire [TFIFODEPTH - 1:0] traddr;
|
||||
output [MAXIDATAWIDTH - 1:0] twdata;
|
||||
wire [MAXIDATAWIDTH - 1:0] twdata;
|
||||
|
||||
|
||||
input [MAXIDATAWIDTH - 1:0] rrdata;
|
||||
output rwe;
|
||||
wire rwe;
|
||||
output [RFIFODEPTH - 1:0] rwaddr;
|
||||
wire [RFIFODEPTH - 1:0] rwaddr;
|
||||
output [RFIFODEPTH - 1:0] rraddr;
|
||||
wire [RFIFODEPTH - 1:0] rraddr;
|
||||
output [MAXIDATAWIDTH - 1:0] rwdata;
|
||||
wire [MAXIDATAWIDTH - 1:0] rwdata;
|
||||
|
||||
input [15:0] frdata;
|
||||
output fwe;
|
||||
wire fwe;
|
||||
output [ADDRDEPTH - 1:0] fwaddr;
|
||||
wire [ADDRDEPTH - 1:0] fwaddr;
|
||||
output [ADDRDEPTH - 1:0] fraddr;
|
||||
wire [ADDRDEPTH - 1:0] fraddr;
|
||||
output [15:0] fwdata;
|
||||
wire [15:0] fwdata;
|
||||
|
||||
input match;
|
||||
input matchval;
|
||||
output matchen;
|
||||
wire matchen;
|
||||
output [47:0] matchdata;
|
||||
wire [47:0] matchdata;
|
||||
|
||||
input sdi;
|
||||
output sclk;
|
||||
wire sclk;
|
||||
output scs;
|
||||
wire scs;
|
||||
output sdo;
|
||||
wire sdo;
|
||||
|
||||
input rxer;
|
||||
input rxdv;
|
||||
input col;
|
||||
input crs;
|
||||
input [MIIWIDTH - 1:0] rxd;
|
||||
output txen;
|
||||
wire txen;
|
||||
output txer;
|
||||
wire txer;
|
||||
output [MIIWIDTH - 1:0] txd;
|
||||
wire [MIIWIDTH - 1:0] txd;
|
||||
output mdc;
|
||||
wire mdc;
|
||||
input mdi;
|
||||
output mdo;
|
||||
wire mdo;
|
||||
output mden;
|
||||
wire mden;
|
||||
|
||||
|
||||
wire datareq;
|
||||
wire datareqc;
|
||||
wire datarw;
|
||||
wire dataeob;
|
||||
wire dataeobc;
|
||||
wire [(MAXIADDRESSWIDTH - 1):0] dataaddr;
|
||||
wire [(MAXIDATAWIDTH - 1):0] datao;
|
||||
wire dataack;
|
||||
wire [(MAXIDATAWIDTH - 1):0] datai;
|
||||
|
||||
wire rstcsr;
|
||||
wire csrack;
|
||||
wire [SAXIDATAWIDTH - 1:0] csrdatao;
|
||||
wire csrreq;
|
||||
wire csrrw;
|
||||
wire [SAXIDATAWIDTH / 8 - 1:0] csrbe;
|
||||
wire [SAXIDATAWIDTH - 1:0] csrdatai;
|
||||
wire [7:0] csraddr;
|
||||
|
||||
MAC
|
||||
#(SAXIDATAWIDTH,
|
||||
MAXIDATAWIDTH,
|
||||
MAXIADDRESSWIDTH,
|
||||
TFIFODEPTH,
|
||||
RFIFODEPTH,
|
||||
TCDEPTH,
|
||||
RCDEPTH)
|
||||
U_MAC (
|
||||
.clkdma (mhclk),
|
||||
.clkcsr (shclk),
|
||||
.clkt (clkt),
|
||||
.clkr (clkr),
|
||||
.rstcsr (rstcsr),
|
||||
.rsttco (rsttco),
|
||||
.rstrco (rstrco),
|
||||
.interrupt (interrupt),
|
||||
.rps (rps),
|
||||
.tps (tps),
|
||||
.csrreq (csrreq),
|
||||
.csrrw (csrrw),
|
||||
.csrbe (csrbe),
|
||||
.csrdatai (csrdatai),
|
||||
.csrack (csrack),
|
||||
.csraddr (csraddr),
|
||||
.csrdatao (csrdatao),
|
||||
.dataack (dataack),
|
||||
.datareq (datareq),
|
||||
.datareqc (datareqc),
|
||||
.datarw (datarw),
|
||||
.dataeob (dataeob),
|
||||
.dataeobc (dataeobc),
|
||||
.datai (datai),
|
||||
.dataaddr (dataaddr),
|
||||
.datao (datao),
|
||||
.trdata (trdata),
|
||||
.twe (twe),
|
||||
.twaddr (twaddr),
|
||||
.traddr (traddr),
|
||||
.twdata (twdata),
|
||||
.rrdata (rrdata),
|
||||
.rwe (rwe),
|
||||
.rwaddr (rwaddr),
|
||||
.rraddr (rraddr),
|
||||
.rwdata (rwdata),
|
||||
.frdata (frdata),
|
||||
.fwe (fwe),
|
||||
.fraddr (fraddr),
|
||||
.fwaddr (fwaddr),
|
||||
.fwdata (fwdata),
|
||||
.match (match),
|
||||
.matchval (matchval),
|
||||
.matchen (matchen),
|
||||
.matchdata (matchdata),
|
||||
.sdi (sdi),
|
||||
.sclk (sclk),
|
||||
.scs (scs),
|
||||
.sdo (sdo),
|
||||
.rxer (rxer),
|
||||
.rxdv (rxdv),
|
||||
.col (col),
|
||||
.crs (crs),
|
||||
.rxd (rxd),
|
||||
.txen (txen),
|
||||
.txer (txer),
|
||||
.txd (txd),
|
||||
.mdi (mdi),
|
||||
.mdo (mdo),
|
||||
.mden (mden),
|
||||
.mdc (mdc)
|
||||
);
|
||||
|
||||
MAC2AXI
|
||||
#(MAXIDATAWIDTH,
|
||||
MAXIADDRESSWIDTH,
|
||||
SAXIDATAWIDTH,
|
||||
SAXIADDRESSWIDTH,
|
||||
MAXIDATAWIDTH,
|
||||
MAXIADDRESSWIDTH,
|
||||
SAXIDATAWIDTH,
|
||||
8)
|
||||
U_MAC2AXI (
|
||||
|
||||
.mhclk (mhclk ),
|
||||
.mhresetn (mhresetn ),
|
||||
.shclk (shclk ),
|
||||
.shresetn (shresetn ),
|
||||
.mawid_o (mawid_o ),
|
||||
.mawaddr_o (mawaddr_o ),
|
||||
.mawlen_o (mawlen_o ),
|
||||
.mawsize_o (mawsize_o ),
|
||||
.mawburst_o (mawburst_o ),
|
||||
.mawlock_o (mawlock_o ),
|
||||
.mawcache_o (mawcache_o ),
|
||||
.mawprot_o (mawprot_o ),
|
||||
.mawvalid_o (mawvalid_o ),
|
||||
.mawready_i (mawready_i ),
|
||||
.mwid_o (mwid_o ),
|
||||
.mwdata_o (mwdata_o ),
|
||||
.mwstrb_o (mwstrb_o ),
|
||||
.mwlast_o (mwlast_o ),
|
||||
.mwvalid_o (mwvalid_o ),
|
||||
.mwready_i (mwready_i ),
|
||||
.mbid_i (mbid_i ),
|
||||
.mbresp_i (mbresp_i ),
|
||||
.mbvalid_i (mbvalid_i ),
|
||||
.mbready_o (mbready_o ),
|
||||
.marid_o (marid_o ),
|
||||
.maraddr_o (maraddr_o ),
|
||||
.marlen_o (marlen_o ),
|
||||
.marsize_o (marsize_o ),
|
||||
.marburst_o (marburst_o ),
|
||||
.marlock_o (marlock_o ),
|
||||
.marcache_o (marcache_o ),
|
||||
.marprot_o (marprot_o ),
|
||||
.marvalid_o (marvalid_o ),
|
||||
.marready_i (marready_i ),
|
||||
.mrid_i (mrid_i ),
|
||||
.mrdata_i (mrdata_i ),
|
||||
.mrresp_i (mrresp_i ),
|
||||
.mrlast_i (mrlast_i ),
|
||||
.mrvalid_i (mrvalid_i ),
|
||||
.mrready_o (mrready_o ),
|
||||
.sawid_i (sawid_i ),
|
||||
.sawaddr_i (sawaddr_i ),
|
||||
.sawlen_i (sawlen_i ),
|
||||
.sawsize_i (sawsize_i ),
|
||||
.sawburst_i (sawburst_i ),
|
||||
.sawlock_i (sawlock_i ),
|
||||
.sawcache_i (sawcache_i ),
|
||||
.sawprot_i (sawprot_i ),
|
||||
.sawvalid_i (sawvalid_i ),
|
||||
.sawready_o (sawready_o ),
|
||||
.swid_i (swid_i ),
|
||||
.swdata_i (swdata_i ),
|
||||
.swstrb_i (swstrb_i ),
|
||||
.swlast_i (swlast_i ),
|
||||
.swvalid_i (swvalid_i ),
|
||||
.swready_o (swready_o ),
|
||||
.sbid_o (sbid_o ),
|
||||
.sbresp_o (sbresp_o ),
|
||||
.sbvalid_o (sbvalid_o ),
|
||||
.sbready_i (sbready_i ),
|
||||
.sarid_i (sarid_i ),
|
||||
.saraddr_i (saraddr_i ),
|
||||
.sarlen_i (sarlen_i ),
|
||||
.sarsize_i (sarsize_i ),
|
||||
.sarburst_i (sarburst_i ),
|
||||
.sarlock_i (sarlock_i ),
|
||||
.sarcache_i (sarcache_i ),
|
||||
.sarprot_i (sarprot_i ),
|
||||
.sarvalid_i (sarvalid_i ),
|
||||
.sarready_o (sarready_o ),
|
||||
.srid_o (srid_o ),
|
||||
.srdata_o (srdata_o ),
|
||||
.srresp_o (srresp_o ),
|
||||
.srlast_o (srlast_o ),
|
||||
.srvalid_o (srvalid_o ),
|
||||
.srready_i (srready_i ),
|
||||
.datareq (datareq ),
|
||||
.datareqc (datareqc ),
|
||||
.datarw (datarw ),
|
||||
.dataeob (dataeob ),
|
||||
.dataeobc (dataeobc ),
|
||||
.dataaddr (dataaddr ),
|
||||
.datao (datao ),
|
||||
.dataack (dataack ),
|
||||
.datai (datai ),
|
||||
.rstcsr (rstcsr ),
|
||||
.csrack (csrack ),
|
||||
.csrdatao (csrdatao ),
|
||||
.csrreq (csrreq ),
|
||||
.csrrw (csrrw ),
|
||||
.csrbe (csrbe ),
|
||||
.csrdatai (csrdatai ),
|
||||
.csraddr (csraddr )
|
||||
);
|
||||
|
||||
endmodule
|
445
resources/soc/rtl/MAC/mac_top.v
Normal file
445
resources/soc/rtl/MAC/mac_top.v
Normal file
@ -0,0 +1,445 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
module mac_top
|
||||
(
|
||||
hclk,
|
||||
hrst_,
|
||||
|
||||
mawid_o ,
|
||||
mawaddr_o ,
|
||||
mawlen_o ,
|
||||
mawsize_o ,
|
||||
mawburst_o ,
|
||||
mawlock_o ,
|
||||
mawcache_o ,
|
||||
mawprot_o ,
|
||||
mawvalid_o ,
|
||||
mawready_i ,
|
||||
mwid_o ,
|
||||
mwdata_o ,
|
||||
mwstrb_o ,
|
||||
mwlast_o ,
|
||||
mwvalid_o ,
|
||||
mwready_i ,
|
||||
mbid_i ,
|
||||
mbresp_i ,
|
||||
mbvalid_i ,
|
||||
mbready_o ,
|
||||
marid_o ,
|
||||
maraddr_o ,
|
||||
marlen_o ,
|
||||
marsize_o ,
|
||||
marburst_o ,
|
||||
marlock_o ,
|
||||
marcache_o ,
|
||||
marprot_o ,
|
||||
marvalid_o ,
|
||||
marready_i ,
|
||||
mrid_i ,
|
||||
mrdata_i ,
|
||||
mrresp_i ,
|
||||
mrlast_i ,
|
||||
mrvalid_i ,
|
||||
mrready_o ,
|
||||
sawid_i ,
|
||||
sawaddr_i ,
|
||||
sawlen_i ,
|
||||
sawsize_i ,
|
||||
sawburst_i ,
|
||||
sawlock_i ,
|
||||
sawcache_i ,
|
||||
sawprot_i ,
|
||||
sawvalid_i ,
|
||||
sawready_o ,
|
||||
swid_i ,
|
||||
swdata_i ,
|
||||
swstrb_i ,
|
||||
swlast_i ,
|
||||
swvalid_i ,
|
||||
swready_o ,
|
||||
sbid_o ,
|
||||
sbresp_o ,
|
||||
sbvalid_o ,
|
||||
sbready_i ,
|
||||
sarid_i ,
|
||||
saraddr_i ,
|
||||
sarlen_i ,
|
||||
sarsize_i ,
|
||||
sarburst_i ,
|
||||
sarlock_i ,
|
||||
sarcache_i ,
|
||||
sarprot_i ,
|
||||
sarvalid_i ,
|
||||
sarready_o ,
|
||||
srid_o ,
|
||||
srdata_o ,
|
||||
srresp_o ,
|
||||
srlast_o ,
|
||||
srvalid_o ,
|
||||
srready_i ,
|
||||
|
||||
interrupt ,
|
||||
|
||||
mtxclk ,
|
||||
mtxen ,
|
||||
mtxd ,
|
||||
mtxerr ,
|
||||
mrxclk ,
|
||||
mrxdv ,
|
||||
mrxd ,
|
||||
mrxerr ,
|
||||
mcoll ,
|
||||
mcrs ,
|
||||
mdc ,
|
||||
md_i ,
|
||||
md_o ,
|
||||
md_oe ,
|
||||
|
||||
trdata ,
|
||||
twe ,
|
||||
twaddr ,
|
||||
traddr ,
|
||||
twdata ,
|
||||
|
||||
rrdata ,
|
||||
rwe ,
|
||||
rwaddr ,
|
||||
rraddr ,
|
||||
rwdata
|
||||
|
||||
);
|
||||
|
||||
|
||||
input hclk;
|
||||
input hrst_;
|
||||
output [ 3:0] mawid_o ;
|
||||
output [ 31:0] mawaddr_o ;
|
||||
output [ 3:0] mawlen_o ;
|
||||
output [ 2:0] mawsize_o ;
|
||||
output [ 1:0] mawburst_o ;
|
||||
output [ 1:0] mawlock_o ;
|
||||
output [ 3:0] mawcache_o ;
|
||||
output [ 2:0] mawprot_o ;
|
||||
output mawvalid_o ;
|
||||
input mawready_i ;
|
||||
output [ 3:0] mwid_o ;
|
||||
output [ 31:0] mwdata_o ;
|
||||
output [ 3:0] mwstrb_o ;
|
||||
output mwlast_o ;
|
||||
output mwvalid_o ;
|
||||
input mwready_i ;
|
||||
input [ 3:0] mbid_i ;
|
||||
input [ 1:0] mbresp_i ;
|
||||
input mbvalid_i ;
|
||||
output mbready_o ;
|
||||
output [ 3:0] marid_o ;
|
||||
output [ 31:0] maraddr_o ;
|
||||
output [ 3:0] marlen_o ;
|
||||
output [ 2:0] marsize_o ;
|
||||
output [ 1:0] marburst_o ;
|
||||
output [ 1:0] marlock_o ;
|
||||
output [ 3:0] marcache_o ;
|
||||
output [ 2:0] marprot_o ;
|
||||
output marvalid_o ;
|
||||
input marready_i ;
|
||||
input [ 3:0] mrid_i ;
|
||||
input [ 31:0] mrdata_i ;
|
||||
input [ 1:0] mrresp_i ;
|
||||
input mrlast_i ;
|
||||
input mrvalid_i ;
|
||||
output mrready_o ;
|
||||
|
||||
input [ 3:0] sawid_i ;
|
||||
input [ 31:0] sawaddr_i ;
|
||||
input [ 3:0] sawlen_i ;
|
||||
input [ 2:0] sawsize_i ;
|
||||
input [ 1:0] sawburst_i ;
|
||||
input [ 1:0] sawlock_i ;
|
||||
input [ 3:0] sawcache_i ;
|
||||
input [ 2:0] sawprot_i ;
|
||||
input sawvalid_i ;
|
||||
output sawready_o ;
|
||||
input [ 3:0] swid_i ;
|
||||
input [ 31:0] swdata_i ;
|
||||
input [ 3:0] swstrb_i ;
|
||||
input swlast_i ;
|
||||
input swvalid_i ;
|
||||
output swready_o ;
|
||||
output [ 3:0] sbid_o ;
|
||||
output [ 1:0] sbresp_o ;
|
||||
output sbvalid_o ;
|
||||
input sbready_i ;
|
||||
input [ 3:0] sarid_i ;
|
||||
input [ 31:0] saraddr_i ;
|
||||
input [ 3:0] sarlen_i ;
|
||||
input [ 2:0] sarsize_i ;
|
||||
input [ 1:0] sarburst_i ;
|
||||
input [ 1:0] sarlock_i ;
|
||||
input [ 3:0] sarcache_i ;
|
||||
input [ 2:0] sarprot_i ;
|
||||
input sarvalid_i ;
|
||||
output sarready_o ;
|
||||
output [ 3:0] srid_o ;
|
||||
output [ 31:0] srdata_o ;
|
||||
output [ 1:0] srresp_o ;
|
||||
output srlast_o ;
|
||||
output srvalid_o ;
|
||||
input srready_i ;
|
||||
input mtxclk;
|
||||
output [3:0] mtxd;
|
||||
output mtxen;
|
||||
output mtxerr;
|
||||
|
||||
input mrxclk;
|
||||
input [3:0] mrxd;
|
||||
input mrxdv;
|
||||
input mrxerr;
|
||||
|
||||
input mcoll;
|
||||
input mcrs;
|
||||
|
||||
input md_i;
|
||||
output mdc;
|
||||
output md_o;
|
||||
output md_oe;
|
||||
|
||||
output interrupt;
|
||||
|
||||
|
||||
`define MAHBDATAWIDTH 32
|
||||
`define TFIFODEPTH 9
|
||||
`define RFIFODEPTH 9
|
||||
`define ADDRDEPTH 6
|
||||
|
||||
input [`MAHBDATAWIDTH - 1:0] trdata;
|
||||
output twe;
|
||||
wire twe;
|
||||
output [`TFIFODEPTH - 1:0] twaddr;
|
||||
wire [`TFIFODEPTH - 1:0] twaddr;
|
||||
output [`TFIFODEPTH - 1:0] traddr;
|
||||
wire [`TFIFODEPTH - 1:0] traddr;
|
||||
output [`MAHBDATAWIDTH - 1:0] twdata;
|
||||
wire [`MAHBDATAWIDTH - 1:0] twdata;
|
||||
|
||||
input [`MAHBDATAWIDTH - 1:0] rrdata;
|
||||
output rwe;
|
||||
wire rwe;
|
||||
output [`RFIFODEPTH - 1:0] rwaddr;
|
||||
wire [`RFIFODEPTH - 1:0] rwaddr;
|
||||
output [`RFIFODEPTH - 1:0] rraddr;
|
||||
wire [`RFIFODEPTH - 1:0] rraddr;
|
||||
output [`MAHBDATAWIDTH - 1:0] rwdata;
|
||||
wire [`MAHBDATAWIDTH - 1:0] rwdata;
|
||||
|
||||
wire tps,rps,rsttco,rstrco,sclk,scs,sdo;
|
||||
|
||||
wire [15:0] frdata;
|
||||
wire fwe;
|
||||
wire [`ADDRDEPTH - 1:0] fwaddr;
|
||||
wire [`ADDRDEPTH - 1:0] fraddr;
|
||||
wire [15:0] fwdata;
|
||||
|
||||
wire match;
|
||||
wire matchval;
|
||||
wire matchen;
|
||||
wire [47:0] matchdata;
|
||||
|
||||
assign match = 1'b0;
|
||||
assign matchval = 1'b0;
|
||||
|
||||
RegFile2_64x16 u_addr_ram
|
||||
(
|
||||
.CLKA(mrxclk), .CENA(1'b0), .AA(fraddr), .QA(frdata),
|
||||
.CLKB(hclk), .CENB(!fwe), .AB(fwaddr), .DB(fwdata)
|
||||
);
|
||||
|
||||
MAC_AXI u_mac_axi (
|
||||
.clkt(mtxclk),
|
||||
.clkr(mrxclk),
|
||||
.rsttco(rsttco),
|
||||
.rstrco(rstrco),
|
||||
.interrupt(interrupt),
|
||||
.tps(tps),
|
||||
.rps(rps),
|
||||
|
||||
.mhclk (hclk ),
|
||||
.mhresetn (hrst_ ),
|
||||
.mawid_o (mawid_o ),
|
||||
.mawaddr_o (mawaddr_o ),
|
||||
.mawlen_o (mawlen_o ),
|
||||
.mawsize_o (mawsize_o ),
|
||||
.mawburst_o (mawburst_o ),
|
||||
.mawlock_o (mawlock_o ),
|
||||
.mawcache_o (mawcache_o ),
|
||||
.mawprot_o (mawprot_o ),
|
||||
.mawvalid_o (mawvalid_o ),
|
||||
.mawready_i (mawready_i ),
|
||||
.mwid_o (mwid_o ),
|
||||
.mwdata_o (mwdata_o ),
|
||||
.mwstrb_o (mwstrb_o ),
|
||||
.mwlast_o (mwlast_o ),
|
||||
.mwvalid_o (mwvalid_o ),
|
||||
.mwready_i (mwready_i ),
|
||||
.mbid_i (mbid_i ),
|
||||
.mbresp_i (mbresp_i ),
|
||||
.mbvalid_i (mbvalid_i ),
|
||||
.mbready_o (mbready_o ),
|
||||
.marid_o (marid_o ),
|
||||
.maraddr_o (maraddr_o ),
|
||||
.marlen_o (marlen_o ),
|
||||
.marsize_o (marsize_o ),
|
||||
.marburst_o (marburst_o ),
|
||||
.marlock_o (marlock_o ),
|
||||
.marcache_o (marcache_o ),
|
||||
.marprot_o (marprot_o ),
|
||||
.marvalid_o (marvalid_o ),
|
||||
.marready_i (marready_i ),
|
||||
.mrid_i (mrid_i ),
|
||||
.mrdata_i (mrdata_i ),
|
||||
.mrresp_i (mrresp_i ),
|
||||
.mrlast_i (mrlast_i ),
|
||||
.mrvalid_i (mrvalid_i ),
|
||||
.mrready_o (mrready_o ),
|
||||
.shclk (hclk ),
|
||||
.shresetn (hrst_ ),
|
||||
.sawid_i (sawid_i ),
|
||||
.sawaddr_i (sawaddr_i ),
|
||||
.sawlen_i (sawlen_i ),
|
||||
.sawsize_i (sawsize_i ),
|
||||
.sawburst_i (sawburst_i ),
|
||||
.sawlock_i (sawlock_i ),
|
||||
.sawcache_i (sawcache_i ),
|
||||
.sawprot_i (sawprot_i ),
|
||||
.sawvalid_i (sawvalid_i ),
|
||||
.sawready_o (sawready_o ),
|
||||
.swid_i (swid_i ),
|
||||
.swdata_i (swdata_i ),
|
||||
.swstrb_i (swstrb_i ),
|
||||
.swlast_i (swlast_i ),
|
||||
.swvalid_i (swvalid_i ),
|
||||
.swready_o (swready_o ),
|
||||
.sbid_o (sbid_o ),
|
||||
.sbresp_o (sbresp_o ),
|
||||
.sbvalid_o (sbvalid_o ),
|
||||
.sbready_i (sbready_i ),
|
||||
.sarid_i (sarid_i ),
|
||||
.saraddr_i (saraddr_i ),
|
||||
.sarlen_i (sarlen_i ),
|
||||
.sarsize_i (sarsize_i ),
|
||||
.sarburst_i (sarburst_i ),
|
||||
.sarlock_i (sarlock_i ),
|
||||
.sarcache_i (sarcache_i ),
|
||||
.sarprot_i (sarprot_i ),
|
||||
.sarvalid_i (sarvalid_i ),
|
||||
.sarready_o (sarready_o ),
|
||||
.srid_o (srid_o ),
|
||||
.srdata_o (srdata_o ),
|
||||
.srresp_o (srresp_o ),
|
||||
.srlast_o (srlast_o ),
|
||||
.srvalid_o (srvalid_o ),
|
||||
.srready_i (srready_i ),
|
||||
.trdata(trdata),
|
||||
.twe(twe),
|
||||
.twaddr(twaddr),
|
||||
.traddr(traddr),
|
||||
.twdata(twdata),
|
||||
.rrdata(rrdata),
|
||||
.rwe(rwe),
|
||||
.rwaddr(rwaddr),
|
||||
.rraddr(rraddr),
|
||||
.rwdata(rwdata),
|
||||
.frdata(frdata),
|
||||
.fwe(fwe),
|
||||
.fwaddr(fwaddr),
|
||||
.fraddr(fraddr),
|
||||
.fwdata(fwdata),
|
||||
.match(match),
|
||||
.matchval(matchval),
|
||||
.matchen(matchen),
|
||||
.matchdata(matchdata),
|
||||
.sdi(1'b0),
|
||||
.sclk(sclk),
|
||||
.scs(scs),
|
||||
.sdo(sdo),
|
||||
.rxer(mrxerr),
|
||||
.rxdv(mrxdv),
|
||||
.col(mcoll),
|
||||
.crs(mcrs),
|
||||
.rxd(mrxd),
|
||||
.txen(mtxen),
|
||||
.txer(mtxerr),
|
||||
.txd(mtxd),
|
||||
.mdc(mdc),
|
||||
.mdi(md_i),
|
||||
.mdo(md_o),
|
||||
.mden(md_oe)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
module RegFile2_64x16 (
|
||||
QA,
|
||||
AA,
|
||||
CLKA,
|
||||
CENA,
|
||||
AB,
|
||||
DB,
|
||||
CLKB,
|
||||
CENB
|
||||
);
|
||||
parameter BITS = 16;
|
||||
parameter word_depth = 64;
|
||||
parameter addr_width = 6;
|
||||
output [15:0] QA;
|
||||
input [5:0] AA;
|
||||
input CLKA;
|
||||
input CENA;
|
||||
input [5:0] AB;
|
||||
input [15:0] DB;
|
||||
input CLKB;
|
||||
input CENB;
|
||||
reg [15:0] QA;
|
||||
|
||||
reg [BITS-1:0] mem [word_depth-1:0];
|
||||
|
||||
wire NOT_CENA;
|
||||
wire NOT_CENB;
|
||||
|
||||
not (NOT_CENA, CENA);
|
||||
always @ ( posedge CLKA ) if ( NOT_CENA ) QA<=mem[AA];
|
||||
|
||||
not (NOT_CENB, CENB);
|
||||
always @ ( posedge CLKB ) if ( NOT_CENB ) mem[AB]<=DB;
|
||||
|
||||
endmodule
|
291
resources/soc/rtl/MAC/maccsr2axi.v
Normal file
291
resources/soc/rtl/MAC/maccsr2axi.v
Normal file
@ -0,0 +1,291 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
module MACCSR2AXI (
|
||||
saclk ,
|
||||
saresetn ,
|
||||
awid_i ,
|
||||
awaddr_i ,
|
||||
awlen_i ,
|
||||
awsize_i ,
|
||||
awburst_i ,
|
||||
awlock_i ,
|
||||
awcache_i ,
|
||||
awprot_i ,
|
||||
awvalid_i ,
|
||||
awready_o ,
|
||||
wid_i ,
|
||||
wdata_i ,
|
||||
wstrb_i ,
|
||||
wlast_i ,
|
||||
wvalid_i ,
|
||||
wready_o ,
|
||||
bid_o ,
|
||||
bresp_o ,
|
||||
bvalid_o ,
|
||||
bready_i ,
|
||||
arid_i ,
|
||||
araddr_i ,
|
||||
arlen_i ,
|
||||
arsize_i ,
|
||||
arburst_i ,
|
||||
arlock_i ,
|
||||
arcache_i ,
|
||||
arprot_i ,
|
||||
arvalid_i ,
|
||||
arready_o ,
|
||||
rid_o ,
|
||||
rdata_o ,
|
||||
rresp_o ,
|
||||
rlast_o ,
|
||||
rvalid_o ,
|
||||
rready_i ,
|
||||
|
||||
rstcsr ,
|
||||
csrack ,
|
||||
csrdatao ,
|
||||
csrreq ,
|
||||
csrrw ,
|
||||
csrbe ,
|
||||
csrdatai ,
|
||||
csraddr
|
||||
);
|
||||
|
||||
|
||||
parameter SAXIDATAWIDTH = 32;
|
||||
parameter SAXIADDRESSWIDTH = 32;
|
||||
parameter CSRDATAWIDTH = 32;
|
||||
parameter CSRADDRESSWIDTH = 8;
|
||||
|
||||
|
||||
|
||||
input saclk;
|
||||
input saresetn;
|
||||
input [ 3:0] awid_i ;
|
||||
input [ 31:0] awaddr_i ;
|
||||
input [ 3:0] awlen_i ;
|
||||
input [ 2:0] awsize_i ;
|
||||
input [ 1:0] awburst_i ;
|
||||
input [ 1:0] awlock_i ;
|
||||
input [ 3:0] awcache_i ;
|
||||
input [ 2:0] awprot_i ;
|
||||
input awvalid_i ;
|
||||
output awready_o ;
|
||||
input [ 3:0] wid_i ;
|
||||
input [ 31:0] wdata_i ;
|
||||
input [ 3:0] wstrb_i ;
|
||||
input wlast_i ;
|
||||
input wvalid_i ;
|
||||
output wready_o ;
|
||||
output [ 3:0] bid_o ;
|
||||
output [ 1:0] bresp_o ;
|
||||
output bvalid_o ;
|
||||
input bready_i ;
|
||||
input [ 3:0] arid_i ;
|
||||
input [ 31:0] araddr_i ;
|
||||
input [ 3:0] arlen_i ;
|
||||
input [ 2:0] arsize_i ;
|
||||
input [ 1:0] arburst_i ;
|
||||
input [ 1:0] arlock_i ;
|
||||
input [ 3:0] arcache_i ;
|
||||
input [ 2:0] arprot_i ;
|
||||
input arvalid_i ;
|
||||
output arready_o ;
|
||||
output [ 3:0] rid_o ;
|
||||
output [ 31:0] rdata_o ;
|
||||
output [ 1:0] rresp_o ;
|
||||
output rlast_o ;
|
||||
output rvalid_o ;
|
||||
input rready_i ;
|
||||
|
||||
|
||||
output rstcsr;
|
||||
wire rstcsr;
|
||||
input csrack;
|
||||
input [CSRDATAWIDTH - 1:0] csrdatao;
|
||||
output csrreq;
|
||||
wire csrreq;
|
||||
output csrrw;
|
||||
wire csrrw;
|
||||
output [CSRDATAWIDTH / 8 - 1:0] csrbe;
|
||||
wire [CSRDATAWIDTH / 8 - 1:0] csrbe;
|
||||
output [CSRDATAWIDTH - 1:0] csrdatai;
|
||||
wire [CSRDATAWIDTH - 1:0] csrdatai;
|
||||
output [CSRADDRESSWIDTH - 1:0] csraddr;
|
||||
wire [CSRADDRESSWIDTH - 1:0] csraddr;
|
||||
|
||||
|
||||
reg isWriting;
|
||||
reg isReading;
|
||||
wire awready;
|
||||
wire arready;
|
||||
wire wvalid;
|
||||
wire wlast;
|
||||
wire wready;
|
||||
wire rvalid;
|
||||
wire rlast;
|
||||
wire rready;
|
||||
|
||||
assign wvalid = wvalid_i;
|
||||
assign wlast = wlast_i;
|
||||
|
||||
always @(posedge saclk)
|
||||
begin
|
||||
if (!saresetn || (wlast && wvalid && wready))
|
||||
begin
|
||||
isWriting <= 1'b0;
|
||||
end
|
||||
else if (awvalid_i && awready)
|
||||
begin
|
||||
isWriting <= 1'b1;
|
||||
end
|
||||
end
|
||||
always @(posedge saclk)
|
||||
begin
|
||||
if (!saresetn || (rlast && rvalid && rready))
|
||||
begin
|
||||
isReading <= 1'b0;
|
||||
end
|
||||
else if (arvalid_i && arready)
|
||||
begin
|
||||
isReading <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
wire arvalid;
|
||||
wire rd_valid;
|
||||
wire [1:0] rresp;
|
||||
wire [31:0] rdata;
|
||||
reg [31:0] rd_addr;
|
||||
reg [3:0] rid;
|
||||
reg [2:0] rd_size;
|
||||
|
||||
|
||||
assign arvalid = arvalid_i;
|
||||
assign rd_valid = arvalid & arready;
|
||||
assign rready = rready_i;
|
||||
assign rresp = 2'b00;
|
||||
|
||||
always @(posedge saclk)
|
||||
if(rd_valid) begin
|
||||
rid <= arid_i;
|
||||
end
|
||||
|
||||
always @(posedge saclk)
|
||||
begin
|
||||
if(!saresetn) begin
|
||||
rd_addr <= 32'h0;
|
||||
end
|
||||
else if (rd_valid) begin
|
||||
rd_addr <= araddr_i;
|
||||
end
|
||||
end
|
||||
|
||||
assign arready = csrack & !isWriting & !isReading;
|
||||
assign rvalid = csrrw & csrack;
|
||||
assign rlast = 1'b1;
|
||||
assign rdata = csrdatao;
|
||||
|
||||
reg [31:0] wr_addr;
|
||||
wire wr_valid;
|
||||
wire [3:0] wr_strb;
|
||||
wire awvalid;
|
||||
wire bready;
|
||||
|
||||
assign awvalid = awvalid_i;
|
||||
assign awready = csrack & !isWriting & !isReading;
|
||||
assign wready = !csrrw && csrack;
|
||||
assign bready = bready_i;
|
||||
assign wr_strb = {4{wvalid}} & wstrb_i;
|
||||
assign wr_valid = awvalid & awready;
|
||||
|
||||
|
||||
always @(posedge saclk)
|
||||
begin
|
||||
if(!saresetn) begin
|
||||
wr_addr <= 32'h0;
|
||||
end
|
||||
else if (wr_valid) begin
|
||||
wr_addr <= awaddr_i;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
wire w_resp_valid;
|
||||
reg w_resp_valid_r;
|
||||
reg[3:0] bid_r;
|
||||
assign w_resp_valid = wvalid & wlast & wready;
|
||||
always @(posedge saclk)
|
||||
if(!saresetn) begin
|
||||
w_resp_valid_r <= 1'b0;
|
||||
bid_r <= 4'b0;
|
||||
end
|
||||
else if(w_resp_valid) begin
|
||||
w_resp_valid_r <= 1'b1;
|
||||
bid_r <= wid_i;
|
||||
end
|
||||
else if(bready) begin
|
||||
w_resp_valid_r <= 1'b0;
|
||||
end
|
||||
|
||||
wire [1:0] bresp = 2'b00;
|
||||
wire [3:0] bid = bid_r;
|
||||
wire bvalid = w_resp_valid_r;
|
||||
|
||||
assign csrdatai = wdata_i;
|
||||
|
||||
assign csrbe = wr_strb;
|
||||
|
||||
assign csraddr = csrrw ? rd_addr[7:0]: wr_addr[7:0];
|
||||
|
||||
assign csrreq = isWriting | isReading;
|
||||
|
||||
assign csrrw = isReading;
|
||||
|
||||
assign rstcsr = ~saresetn;
|
||||
|
||||
assign awready_o = awready;
|
||||
assign wready_o = wready;
|
||||
|
||||
assign bid_o = bid;
|
||||
assign bresp_o = bresp;
|
||||
assign bvalid_o = bvalid;
|
||||
|
||||
assign arready_o = arready;
|
||||
assign rid_o = rid;
|
||||
assign rdata_o = rdata;
|
||||
assign rresp_o = rresp;
|
||||
assign rlast_o = rlast;
|
||||
assign rvalid_o = rvalid;
|
||||
|
||||
endmodule
|
248
resources/soc/rtl/MAC/macdata2axi.v
Normal file
248
resources/soc/rtl/MAC/macdata2axi.v
Normal file
@ -0,0 +1,248 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
module MACDATA2AXI (
|
||||
maclk ,
|
||||
maresetn ,
|
||||
|
||||
awid_o ,
|
||||
awaddr_o ,
|
||||
awlen_o ,
|
||||
awsize_o ,
|
||||
awburst_o ,
|
||||
awlock_o ,
|
||||
awcache_o ,
|
||||
awprot_o ,
|
||||
awvalid_o ,
|
||||
awready_i ,
|
||||
wid_o ,
|
||||
wdata_o ,
|
||||
wstrb_o ,
|
||||
wlast_o ,
|
||||
wvalid_o ,
|
||||
wready_i ,
|
||||
bid_i ,
|
||||
bresp_i ,
|
||||
bvalid_i ,
|
||||
bready_o ,
|
||||
arid_o ,
|
||||
araddr_o ,
|
||||
arlen_o ,
|
||||
arsize_o ,
|
||||
arburst_o ,
|
||||
arlock_o ,
|
||||
arcache_o ,
|
||||
arprot_o ,
|
||||
arvalid_o ,
|
||||
arready_i ,
|
||||
rid_i ,
|
||||
rdata_i ,
|
||||
rresp_i ,
|
||||
rlast_i ,
|
||||
rvalid_i ,
|
||||
rready_o ,
|
||||
datareq ,
|
||||
datareqc ,
|
||||
datarw ,
|
||||
dataeob ,
|
||||
dataeobc ,
|
||||
dataaddr ,
|
||||
datao ,
|
||||
dataack ,
|
||||
datai
|
||||
);
|
||||
|
||||
parameter MAXIDATAWIDTH = 32;
|
||||
parameter MAXIADDRESSWIDTH = 32;
|
||||
parameter MACDATAWIDTH = 32;
|
||||
parameter MACADDRESSWIDTH = 32;
|
||||
|
||||
|
||||
input maclk;
|
||||
input maresetn;
|
||||
output [ 3:0] awid_o ;
|
||||
output [ 31:0] awaddr_o ;
|
||||
output [ 3:0] awlen_o ;
|
||||
output [ 2:0] awsize_o ;
|
||||
output [ 1:0] awburst_o ;
|
||||
output [ 1:0] awlock_o ;
|
||||
output [ 3:0] awcache_o ;
|
||||
output [ 2:0] awprot_o ;
|
||||
output awvalid_o ;
|
||||
input awready_i ;
|
||||
output [ 3:0] wid_o ;
|
||||
output [ 31:0] wdata_o ;
|
||||
output [ 3:0] wstrb_o ;
|
||||
output wlast_o ;
|
||||
output wvalid_o ;
|
||||
input wready_i ;
|
||||
input [ 3:0] bid_i ;
|
||||
input [ 1:0] bresp_i ;
|
||||
input bvalid_i ;
|
||||
output bready_o ;
|
||||
output [ 3:0] arid_o ;
|
||||
output [ 31:0] araddr_o ;
|
||||
output [ 3:0] arlen_o ;
|
||||
output [ 2:0] arsize_o ;
|
||||
output [ 1:0] arburst_o ;
|
||||
output [ 1:0] arlock_o ;
|
||||
output [ 3:0] arcache_o ;
|
||||
output [ 2:0] arprot_o ;
|
||||
output arvalid_o ;
|
||||
input arready_i ;
|
||||
input [ 3:0] rid_i ;
|
||||
input [ 31:0] rdata_i ;
|
||||
input [ 1:0] rresp_i ;
|
||||
input rlast_i ;
|
||||
input rvalid_i ;
|
||||
output rready_o ;
|
||||
|
||||
|
||||
input datareq;
|
||||
input datareqc;
|
||||
input datarw;
|
||||
input dataeob;
|
||||
input dataeobc;
|
||||
input [MACADDRESSWIDTH - 1:0] dataaddr;
|
||||
input [MACDATAWIDTH - 1:0] datao;
|
||||
output dataack;
|
||||
wire dataack;
|
||||
output [MACDATAWIDTH - 1:0] datai;
|
||||
wire [MACDATAWIDTH - 1:0] datai;
|
||||
|
||||
|
||||
assign arid_o = 4'h1;
|
||||
assign arsize_o = 3'b010;
|
||||
assign arlen_o = 4'b0000;
|
||||
assign arburst_o = 2'b01;
|
||||
assign arlock_o = 2'b00;
|
||||
assign arcache_o = 4'b0000;
|
||||
assign arprot_o = 3'b110;
|
||||
|
||||
reg isWriting;
|
||||
reg isReading;
|
||||
|
||||
always @(posedge maclk)
|
||||
begin
|
||||
if (!maresetn || (wlast_o && wvalid_o && wready_i))
|
||||
begin
|
||||
isWriting <= 1'b0;
|
||||
end
|
||||
else if (awvalid_o && awready_i)
|
||||
begin
|
||||
isWriting <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge maclk)
|
||||
begin
|
||||
if (!maresetn || (rlast_i && rvalid_i && rready_o))
|
||||
begin
|
||||
isReading <= 1'b0;
|
||||
end
|
||||
else if (arvalid_o && arready_i)
|
||||
begin
|
||||
isReading <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
reg [MACADDRESSWIDTH-1:0] dataAddr_c_r;
|
||||
wire [MACADDRESSWIDTH-1:0] dataAddr_c;
|
||||
wire dataAddr_sel;
|
||||
reg dataReq_r;
|
||||
|
||||
always @(posedge maclk)
|
||||
begin
|
||||
dataReq_r <= datareq;
|
||||
end
|
||||
|
||||
wire dataAddr_c_r_en;
|
||||
assign dataAddr_c_r_en = (awvalid_o & awready_i) |
|
||||
(arvalid_o & arready_i);
|
||||
always @(posedge maclk)
|
||||
begin
|
||||
if (!maresetn)
|
||||
begin
|
||||
dataAddr_c_r <= 32'd0;
|
||||
end
|
||||
else if ( dataAddr_c_r_en)
|
||||
begin
|
||||
dataAddr_c_r <= dataAddr_c;
|
||||
end
|
||||
end
|
||||
|
||||
assign dataAddr_sel = datareq & (~dataReq_r | dataeob);
|
||||
assign dataAddr_c = dataAddr_sel ? dataaddr : dataAddr_c_r+3'b100;
|
||||
|
||||
wire arvalid;
|
||||
assign arvalid = datareq & datarw & ~isWriting & ~isReading;
|
||||
|
||||
assign araddr_o = dataAddr_c;
|
||||
assign arvalid_o = arvalid;
|
||||
|
||||
assign rready_o = 1'b1;
|
||||
assign datai = rdata_i;
|
||||
wire readDataAck;
|
||||
assign readDataAck = rvalid_i & rready_o;
|
||||
|
||||
assign awid_o = 4'h1;
|
||||
assign awsize_o = 3'b010;
|
||||
assign awlen_o = 4'b0000;
|
||||
assign awburst_o = 2'b01;
|
||||
assign awlock_o = 2'b00;
|
||||
assign awcache_o = 4'b0000;
|
||||
assign awprot_o = 3'b110;
|
||||
|
||||
wire awvalid;
|
||||
assign awvalid = datareq & ~datarw & ~isWriting & ~isReading;
|
||||
|
||||
assign awvalid_o = awvalid;
|
||||
assign awaddr_o = dataAddr_c;
|
||||
|
||||
wire wvalid;
|
||||
assign wid_o = 4'h1;
|
||||
assign wlast_o = 1'b1;
|
||||
assign wdata_o = datao;
|
||||
assign wstrb_o = 4'b1111;
|
||||
|
||||
assign wvalid = (awvalid_o & awready_i) | isWriting;
|
||||
assign wvalid_o = wvalid;
|
||||
|
||||
wire writeDataAck;
|
||||
assign writeDataAck = wvalid & wready_i;
|
||||
|
||||
assign bready_o = 1'b1;
|
||||
|
||||
assign dataack = readDataAck | writeDataAck;
|
||||
|
||||
endmodule
|
1749
resources/soc/rtl/MAC/rc.v
Normal file
1749
resources/soc/rtl/MAC/rc.v
Normal file
File diff suppressed because it is too large
Load Diff
439
resources/soc/rtl/MAC/rfifo.v
Normal file
439
resources/soc/rtl/MAC/rfifo.v
Normal file
@ -0,0 +1,439 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
module RFIFO (
|
||||
clk,
|
||||
rst,
|
||||
ramdata,
|
||||
ramaddr,
|
||||
fifore,
|
||||
ffo,
|
||||
rfo,
|
||||
mfo,
|
||||
tlo,
|
||||
reo,
|
||||
dbo,
|
||||
ceo,
|
||||
ovo,
|
||||
cso,
|
||||
flo,
|
||||
fifodata,
|
||||
cachere,
|
||||
cachene,
|
||||
cachenf,
|
||||
radg,
|
||||
rireq,
|
||||
ffi,
|
||||
rfi,
|
||||
mfi,
|
||||
tli,
|
||||
rei,
|
||||
dbi,
|
||||
cei,
|
||||
ovi,
|
||||
csi,
|
||||
fli,
|
||||
wadg,
|
||||
riack
|
||||
);
|
||||
|
||||
parameter DATAWIDTH = 32;
|
||||
parameter DATADEPTH = 32;
|
||||
parameter FIFODEPTH = 9;
|
||||
parameter CACHEDEPTH = 2;
|
||||
|
||||
input clk;
|
||||
input rst;
|
||||
|
||||
input [DATAWIDTH - 1:0] ramdata;
|
||||
output [FIFODEPTH - 1:0] ramaddr;
|
||||
wire [FIFODEPTH - 1:0] ramaddr;
|
||||
|
||||
input fifore;
|
||||
output ffo;
|
||||
wire ffo;
|
||||
output rfo;
|
||||
wire rfo;
|
||||
output mfo;
|
||||
wire mfo;
|
||||
output tlo;
|
||||
wire tlo;
|
||||
output reo;
|
||||
wire reo;
|
||||
output dbo;
|
||||
wire dbo;
|
||||
output ceo;
|
||||
wire ceo;
|
||||
output ovo;
|
||||
wire ovo;
|
||||
output cso;
|
||||
wire cso;
|
||||
output [13:0] flo;
|
||||
wire [13:0] flo;
|
||||
output [DATAWIDTH - 1:0] fifodata;
|
||||
wire [DATAWIDTH - 1:0] fifodata;
|
||||
|
||||
input cachere;
|
||||
output cachene;
|
||||
wire cachene;
|
||||
|
||||
output cachenf;
|
||||
wire cachenf;
|
||||
output [FIFODEPTH - 1:0] radg;
|
||||
reg [FIFODEPTH - 1:0] radg;
|
||||
|
||||
input rireq;
|
||||
input ffi;
|
||||
input rfi;
|
||||
input mfi;
|
||||
input tli;
|
||||
input rei;
|
||||
input dbi;
|
||||
input cei;
|
||||
input ovi;
|
||||
input csi;
|
||||
input [13:0] fli;
|
||||
input [FIFODEPTH - 1:0] wadg;
|
||||
output riack;
|
||||
wire riack;
|
||||
|
||||
|
||||
parameter CSWIDTH = 23;
|
||||
reg [CSWIDTH - 1:0] csmem[(1'b1 << CACHEDEPTH) - 1:0];
|
||||
wire cswe;
|
||||
wire csre;
|
||||
reg csnf;
|
||||
reg csne;
|
||||
reg [CACHEDEPTH - 1:0] cswad;
|
||||
reg [CACHEDEPTH - 1:0] cswadi;
|
||||
reg [CACHEDEPTH - 1:0] csrad;
|
||||
reg [CACHEDEPTH - 1:0] csrad_r;
|
||||
wire [CSWIDTH - 1:0] csdi;
|
||||
wire [CSWIDTH - 1:0] csdo;
|
||||
|
||||
reg [FIFODEPTH - 1:0] stat;
|
||||
reg [FIFODEPTH - 1:0] rad_c;
|
||||
reg [FIFODEPTH - 1:0] rad;
|
||||
reg [FIFODEPTH - 1:0] wad_c;
|
||||
reg [FIFODEPTH - 1:0] wad;
|
||||
reg [FIFODEPTH - 1:0] wadg_0_r;
|
||||
reg [FIFODEPTH - 1:0] wadg_r;
|
||||
reg [13:0] flibin_c;
|
||||
reg [13:0] flibin;
|
||||
reg [13:0] fli_r;
|
||||
|
||||
reg rireq_r;
|
||||
reg iriack;
|
||||
|
||||
wire [FIFODEPTH - 1:0] fzero;
|
||||
|
||||
always @(posedge clk)
|
||||
begin : csmem_reg_proc
|
||||
if (rst)
|
||||
begin : csmem_reset
|
||||
integer i;
|
||||
for(i = ((1'b1 << CACHEDEPTH) - 1); i >= 0; i = i - 1)
|
||||
begin
|
||||
csmem[i] <= {CSWIDTH{1'b0}};
|
||||
end
|
||||
csrad_r <= csrad ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
csmem[cswad] <= csdi ;
|
||||
csrad_r <= csrad ;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : cswad_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
cswad <= {CACHEDEPTH{1'b1}} ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (cswe)
|
||||
begin
|
||||
cswad <= cswad + 1 ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : csrad_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
csrad <= {CACHEDEPTH{1'b1}} ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (csre)
|
||||
begin
|
||||
csrad <= csrad + 1 ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : csne_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
csne <= 1'b0 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (cswad == csrad)
|
||||
begin
|
||||
csne <= 1'b0 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
csne <= 1'b1 ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(cswad)
|
||||
begin : cswadi_drv
|
||||
cswadi <= cswad + 1;
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : csnf_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
csnf <= 1'b0 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (cswadi == csrad)
|
||||
begin
|
||||
csnf <= 1'b0 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
csnf <= 1'b1 ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(fli_r)
|
||||
begin : flibin_proc
|
||||
reg[13:0] flibin_v;
|
||||
flibin_v[13] = fli_r[13];
|
||||
begin : flibin_loop
|
||||
integer i;
|
||||
for(i = 12; i >= 0; i = i - 1)
|
||||
begin
|
||||
flibin_v[i] = flibin_v[i + 1] ^ fli_r[i];
|
||||
end
|
||||
end
|
||||
flibin_c = flibin_v ;
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : flibin_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
flibin <= {14{1'b0}} ;
|
||||
fli_r <= {14{1'b0}} ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
flibin <= flibin_c ;
|
||||
fli_r <= fli ;
|
||||
end
|
||||
end
|
||||
|
||||
assign cachene = csne ;
|
||||
|
||||
assign cachenf = csnf ;
|
||||
|
||||
assign cswe = rireq_r & ~iriack ;
|
||||
|
||||
assign csdo = csmem[csrad_r] ;
|
||||
|
||||
assign csdi = {ffi, rfi, mfi, tli, rei, dbi, cei, ovi, csi, flibin} ;
|
||||
|
||||
assign ffo = csdo[CSWIDTH - 1] ;
|
||||
|
||||
assign rfo = csdo[CSWIDTH - 2] ;
|
||||
|
||||
assign mfo = csdo[CSWIDTH - 3] ;
|
||||
|
||||
assign tlo = csdo[CSWIDTH - 4] ;
|
||||
|
||||
assign reo = csdo[CSWIDTH - 5] ;
|
||||
|
||||
assign dbo = csdo[CSWIDTH - 6] ;
|
||||
|
||||
assign ceo = csdo[CSWIDTH - 7] ;
|
||||
|
||||
assign ovo = csdo[CSWIDTH - 8] ;
|
||||
|
||||
assign cso = csdo[CSWIDTH - 9];
|
||||
|
||||
assign flo = csdo[13:0] ;
|
||||
|
||||
assign csre = cachere ;
|
||||
|
||||
always @(posedge clk)
|
||||
begin : rireq_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
rireq_r <= 1'b0 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
rireq_r <= rireq ;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : irecack_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
iriack <= 1'b0 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
iriack <= rireq_r ;
|
||||
end
|
||||
end
|
||||
|
||||
assign riack = iriack ;
|
||||
|
||||
always @(rad or fifore)
|
||||
begin : rad_proc
|
||||
if (fifore)
|
||||
begin
|
||||
rad_c <= rad + 1 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
rad_c <= rad ;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : rad_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
rad <= {FIFODEPTH{1'b0}} ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
rad <= rad_c ;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : radg_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
radg <= {FIFODEPTH{1'b0}} ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
radg[FIFODEPTH - 1] <= rad[FIFODEPTH - 1] ;
|
||||
begin : radg_loop
|
||||
integer i;
|
||||
for(i = FIFODEPTH - 2; i >= 0; i = i - 1)
|
||||
begin
|
||||
radg[i] <= rad[i] ^ rad[i + 1] ;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : wadg_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
wadg_0_r <= {FIFODEPTH{1'b0}} ;
|
||||
wadg_r <= {FIFODEPTH{1'b0}} ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
wadg_0_r <= wadg;
|
||||
wadg_r <= wadg_0_r;
|
||||
end
|
||||
end
|
||||
|
||||
always @(wadg_r)
|
||||
begin : wad_proc
|
||||
reg[FIFODEPTH - 1:0] wad_v;
|
||||
wad_v[FIFODEPTH - 1] = wadg_r[FIFODEPTH - 1];
|
||||
begin : wad_loop
|
||||
integer i;
|
||||
for(i = FIFODEPTH - 2; i >= 0; i = i - 1)
|
||||
begin
|
||||
wad_v[i] = wad_v[i + 1] ^ wadg_r[i];
|
||||
end
|
||||
end
|
||||
wad_c = wad_v ;
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : ad_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
wad <= {FIFODEPTH{1'b0}} ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
wad <= wad_c ;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : stat_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
stat <= {FIFODEPTH{1'b0}} ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
stat <= wad - rad ;
|
||||
end
|
||||
end
|
||||
|
||||
assign ramaddr = rad_c ;
|
||||
|
||||
assign fifodata = ramdata ;
|
||||
|
||||
|
||||
assign fzero = {FIFODEPTH{1'b0}};
|
||||
|
||||
endmodule
|
1328
resources/soc/rtl/MAC/rlsm.v
Normal file
1328
resources/soc/rtl/MAC/rlsm.v
Normal file
File diff suppressed because it is too large
Load Diff
158
resources/soc/rtl/MAC/rstc.v
Normal file
158
resources/soc/rtl/MAC/rstc.v
Normal file
@ -0,0 +1,158 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
module RSTC (
|
||||
clkdma,
|
||||
clkcsr,
|
||||
clkt,
|
||||
clkr,
|
||||
rstcsr,
|
||||
rstsoft,
|
||||
rsttc,
|
||||
rstrc,
|
||||
rstdmao,
|
||||
rstcsro
|
||||
);
|
||||
|
||||
input clkdma;
|
||||
input clkcsr;
|
||||
input clkt;
|
||||
input clkr;
|
||||
|
||||
input rstcsr;
|
||||
input rstsoft;
|
||||
output rsttc;
|
||||
reg rsttc;
|
||||
output rstrc;
|
||||
reg rstrc;
|
||||
output rstdmao;
|
||||
reg rstdmao;
|
||||
output rstcsro;
|
||||
reg rstcsro;
|
||||
|
||||
|
||||
reg rstsoft_rc1;
|
||||
reg rstsoft_rc2;
|
||||
reg rstsoft_rc3;
|
||||
reg rstsoft_tc1;
|
||||
reg rstsoft_tc2;
|
||||
reg rstsoft_tc3;
|
||||
reg rstsoft_dma1;
|
||||
reg rstsoft_dma2;
|
||||
reg rstsoft_dma3;
|
||||
reg rstsoft_csr;
|
||||
reg rstsoft_dma_csr1;
|
||||
reg rstsoft_dma_csr2;
|
||||
reg rstsoft_rc_csr1;
|
||||
reg rstsoft_rc_csr2;
|
||||
reg rstsoft_tc_csr1;
|
||||
reg rstsoft_tc_csr2;
|
||||
reg rstcsr_r1;
|
||||
reg rstcsr_r2;
|
||||
reg rstcsr_tc1;
|
||||
reg rstcsr_tc2;
|
||||
reg rstcsr_rc1;
|
||||
reg rstcsr_rc2;
|
||||
reg rstcsr_dma1;
|
||||
reg rstcsr_dma2;
|
||||
|
||||
|
||||
always @(posedge clkcsr)
|
||||
begin : rstsoft_csr_reg_proc
|
||||
if (rstcsr_r2)
|
||||
begin
|
||||
rstsoft_csr <= 1'b0 ;
|
||||
rstsoft_dma_csr1 <= 1'b0 ;
|
||||
rstsoft_dma_csr2 <= 1'b0 ;
|
||||
rstsoft_tc_csr1 <= 1'b0 ;
|
||||
rstsoft_tc_csr2 <= 1'b0 ;
|
||||
rstsoft_rc_csr1 <= 1'b0 ;
|
||||
rstsoft_rc_csr2 <= 1'b0 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (rstsoft)
|
||||
begin
|
||||
rstsoft_csr <= 1'b1 ;
|
||||
end
|
||||
else if (rstsoft_rc_csr2 & rstsoft_tc_csr2 & rstsoft_dma_csr2)
|
||||
begin
|
||||
rstsoft_csr <= 1'b0 ;
|
||||
end
|
||||
rstsoft_dma_csr1 <= rstsoft_dma3;
|
||||
rstsoft_dma_csr2 <= rstsoft_dma_csr1;
|
||||
rstsoft_tc_csr1 <= rstsoft_tc3;
|
||||
rstsoft_tc_csr2 <= rstsoft_tc_csr1;
|
||||
rstsoft_rc_csr1 <= rstsoft_rc3;
|
||||
rstsoft_rc_csr2 <= rstsoft_rc_csr1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clkcsr)
|
||||
begin : rstcsro_reg_proc
|
||||
rstcsr_r1 <= rstcsr;
|
||||
rstcsr_r2 <= rstcsr_r1;
|
||||
rstcsro <= rstcsr_r2 | rstsoft_csr;
|
||||
end
|
||||
|
||||
always @(posedge clkr)
|
||||
begin : rstrc_reg_proc
|
||||
rstcsr_rc1 <= rstcsr;
|
||||
rstcsr_rc2 <= rstcsr_rc1;
|
||||
rstsoft_rc1 <= rstsoft_csr;
|
||||
rstsoft_rc2 <= rstsoft_rc1;
|
||||
rstsoft_rc3 <= rstsoft_rc2;
|
||||
rstrc <= rstcsr_rc2 | rstsoft_rc2;
|
||||
end
|
||||
|
||||
always @(posedge clkt)
|
||||
begin : rsttc_proc
|
||||
rstcsr_tc1 <= rstcsr;
|
||||
rstcsr_tc2 <= rstcsr_tc1;
|
||||
rstsoft_tc1 <= rstsoft_csr;
|
||||
rstsoft_tc2 <= rstsoft_tc1;
|
||||
rstsoft_tc3 <= rstsoft_tc2;
|
||||
rsttc <= rstcsr_tc2 | rstsoft_tc2;
|
||||
end
|
||||
|
||||
always @(posedge clkdma)
|
||||
begin : rstdma_reg_proc
|
||||
rstcsr_dma1 <= rstcsr;
|
||||
rstcsr_dma2 <= rstcsr_dma1;
|
||||
rstsoft_dma1 <= rstsoft_csr;
|
||||
rstsoft_dma2 <= rstsoft_dma1;
|
||||
rstsoft_dma3 <= rstsoft_dma2;
|
||||
rstdmao <= rstcsr_dma2 | rstsoft_dma2;
|
||||
end
|
||||
|
||||
endmodule
|
1296
resources/soc/rtl/MAC/tc.v
Normal file
1296
resources/soc/rtl/MAC/tc.v
Normal file
File diff suppressed because it is too large
Load Diff
815
resources/soc/rtl/MAC/tfifo.v
Normal file
815
resources/soc/rtl/MAC/tfifo.v
Normal file
@ -0,0 +1,815 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
module TFIFO (
|
||||
clk,
|
||||
rst,
|
||||
ramwe,
|
||||
ramaddr,
|
||||
ramdata,
|
||||
fifowe,
|
||||
fifoeof,
|
||||
fifobe,
|
||||
fifodata,
|
||||
fifonf,
|
||||
fifocnf,
|
||||
fifoval,
|
||||
flev,
|
||||
ici,
|
||||
dpdi,
|
||||
aci,
|
||||
statadi,
|
||||
cachere,
|
||||
deo,
|
||||
lco,
|
||||
loo,
|
||||
nco,
|
||||
eco,
|
||||
csne,
|
||||
ico,
|
||||
uro,
|
||||
cco,
|
||||
statado,
|
||||
sofreq,
|
||||
eofreq,
|
||||
dpdo,
|
||||
aco,
|
||||
beo,
|
||||
eofad,
|
||||
wadg,
|
||||
tireq,
|
||||
winp,
|
||||
dei,
|
||||
lci,
|
||||
loi,
|
||||
nci,
|
||||
eci,
|
||||
uri,
|
||||
cci,
|
||||
radg,
|
||||
tiack,
|
||||
sf,
|
||||
fdp,
|
||||
tm,
|
||||
pbl,
|
||||
etiack,
|
||||
etireq,
|
||||
stopi,
|
||||
stopo
|
||||
);
|
||||
|
||||
parameter DATAWIDTH = 32;
|
||||
parameter DATADEPTH = 32;
|
||||
parameter FIFODEPTH = 9;
|
||||
parameter CACHEDEPTH = 1;
|
||||
|
||||
`include "utility.v"
|
||||
|
||||
input clk;
|
||||
input rst;
|
||||
|
||||
output ramwe;
|
||||
wire ramwe;
|
||||
output [FIFODEPTH - 1:0] ramaddr;
|
||||
wire [FIFODEPTH - 1:0] ramaddr;
|
||||
output [DATAWIDTH - 1:0] ramdata;
|
||||
wire [DATAWIDTH - 1:0] ramdata;
|
||||
|
||||
input fifowe;
|
||||
input fifoeof;
|
||||
input [DATAWIDTH / 8 - 1:0] fifobe;
|
||||
input [DATAWIDTH - 1:0] fifodata;
|
||||
output fifonf;
|
||||
reg fifonf;
|
||||
output fifocnf;
|
||||
wire fifocnf;
|
||||
output fifoval;
|
||||
reg fifoval;
|
||||
output [FIFODEPTH - 1:0] flev;
|
||||
wire [FIFODEPTH - 1:0] flev;
|
||||
|
||||
input ici;
|
||||
input dpdi;
|
||||
input aci;
|
||||
input [DATADEPTH - 1:0] statadi;
|
||||
|
||||
input cachere;
|
||||
output deo;
|
||||
wire deo;
|
||||
output lco;
|
||||
wire lco;
|
||||
output loo;
|
||||
wire loo;
|
||||
output nco;
|
||||
wire nco;
|
||||
output eco;
|
||||
wire eco;
|
||||
output csne;
|
||||
wire csne;
|
||||
output ico;
|
||||
wire ico;
|
||||
output uro;
|
||||
wire uro;
|
||||
output [3:0] cco;
|
||||
wire [3:0] cco;
|
||||
output [DATADEPTH - 1:0] statado;
|
||||
wire [DATADEPTH - 1:0] statado;
|
||||
|
||||
output sofreq;
|
||||
wire sofreq;
|
||||
output eofreq;
|
||||
reg eofreq;
|
||||
output dpdo;
|
||||
wire dpdo;
|
||||
output aco;
|
||||
wire aco;
|
||||
output [DATAWIDTH / 8 - 1:0] beo;
|
||||
wire [DATAWIDTH / 8 - 1:0] beo;
|
||||
output [FIFODEPTH - 1:0] eofad;
|
||||
reg [FIFODEPTH - 1:0] eofad;
|
||||
output [FIFODEPTH - 1:0] wadg;
|
||||
reg [FIFODEPTH - 1:0] wadg;
|
||||
|
||||
input tireq;
|
||||
input winp;
|
||||
input dei;
|
||||
input lci;
|
||||
input loi;
|
||||
input nci;
|
||||
input eci;
|
||||
input uri;
|
||||
input [3:0] cci;
|
||||
input [FIFODEPTH - 1:0] radg;
|
||||
output tiack;
|
||||
wire tiack;
|
||||
|
||||
input sf;
|
||||
input fdp;
|
||||
input [2:0] tm;
|
||||
input [5:0] pbl;
|
||||
|
||||
input etiack;
|
||||
output etireq;
|
||||
reg etireq;
|
||||
|
||||
input stopi;
|
||||
output stopo;
|
||||
reg stopo;
|
||||
|
||||
|
||||
parameter CCWIDTH = (3 + DATADEPTH + DATAWIDTH / 8 + FIFODEPTH);
|
||||
reg [CCWIDTH - 1:0] ccmem[(1'b1 << CACHEDEPTH) - 1:0];
|
||||
wire ccwe;
|
||||
wire ccre;
|
||||
reg ccne;
|
||||
reg iccnf;
|
||||
wire [CACHEDEPTH - 1:0] ccwad_c;
|
||||
reg [CACHEDEPTH - 1:0] ccwad;
|
||||
reg [CACHEDEPTH - 1:0] ccrad;
|
||||
reg [CACHEDEPTH - 1:0] ccrad_r;
|
||||
wire [CCWIDTH - 1:0] ccdi;
|
||||
wire [CCWIDTH - 1:0] ccdo;
|
||||
|
||||
parameter CSWIDTH = (DATADEPTH + 11);
|
||||
reg [CSWIDTH - 1:0] csmem[(1'b1 << CACHEDEPTH) - 1:0];
|
||||
wire cswe;
|
||||
reg csre;
|
||||
reg [CACHEDEPTH - 1:0] cswad;
|
||||
wire [CACHEDEPTH - 1:0] csrad_c;
|
||||
reg [CACHEDEPTH - 1:0] csrad;
|
||||
reg [CACHEDEPTH - 1:0] csrad_r;
|
||||
wire [CSWIDTH - 1:0] csdi;
|
||||
wire [CSWIDTH - 1:0] csdo;
|
||||
wire [DATADEPTH - 1:0] statad;
|
||||
wire ic;
|
||||
reg icsne;
|
||||
|
||||
reg tprog;
|
||||
reg tprog_r;
|
||||
|
||||
reg winp_r;
|
||||
reg [FIFODEPTH_MAX - 1:0] tlev_c;
|
||||
reg tresh;
|
||||
reg [FIFODEPTH - 1:0] stat;
|
||||
reg [FIFODEPTH - 1:0] wad;
|
||||
reg [FIFODEPTH - 1:0] rad_c;
|
||||
reg [FIFODEPTH - 1:0] rad;
|
||||
reg [FIFODEPTH - 1:0] radg_0_r;
|
||||
reg [FIFODEPTH - 1:0] radg_r;
|
||||
reg [FIFODEPTH - 1:0] sad;
|
||||
wire [FIFODEPTH - 1:0] eofad_bin;
|
||||
reg pblz;
|
||||
reg [FIFODEPTH_MAX - 1:0] sflev_c;
|
||||
|
||||
reg tireq_r;
|
||||
reg tireq_r2;
|
||||
|
||||
reg stop_r;
|
||||
|
||||
wire [FIFODEPTH - 1:0] fone;
|
||||
wire [FIFODEPTH - 1:0] fzero;
|
||||
|
||||
always @(posedge clk)
|
||||
begin : ccmem_reg_proc
|
||||
if (rst)
|
||||
begin : ccmem_reset
|
||||
integer i;
|
||||
for(i = ((1'b1 << CACHEDEPTH) - 1); i >= 0; i = i - 1)
|
||||
begin
|
||||
ccmem[i] <= {CCWIDTH{1'b0}};
|
||||
end
|
||||
ccrad_r <= {CACHEDEPTH{1'b0}} ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (fifowe | fifoeof)
|
||||
begin
|
||||
ccmem[ccwad] <= ccdi ;
|
||||
end
|
||||
ccrad_r <= ccrad ;
|
||||
end
|
||||
end
|
||||
|
||||
assign ccwad_c = (fifoeof) ? ccwad + 1 : ccwad ;
|
||||
|
||||
always @(posedge clk)
|
||||
begin : ccaddr_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
ccwad <= {CACHEDEPTH{1'b0}} ;
|
||||
ccrad <= {CACHEDEPTH{1'b0}} ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
ccwad <= ccwad_c ;
|
||||
|
||||
if (ccre)
|
||||
begin
|
||||
ccrad <= ccrad + 1 ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : ccfe_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
iccnf <= 1'b1 ;
|
||||
ccne <= 1'b0 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if ((ccwad_c == ccrad) & ccwe)
|
||||
begin
|
||||
iccnf <= 1'b0 ;
|
||||
end
|
||||
else if (ccre)
|
||||
begin
|
||||
iccnf <= 1'b1 ;
|
||||
end
|
||||
|
||||
if (ccwad == ccrad & iccnf)
|
||||
begin
|
||||
ccne <= 1'b0 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
ccne <= 1'b1 ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign fifocnf = iccnf ;
|
||||
|
||||
assign ccdo = ccmem[ccrad_r] ;
|
||||
|
||||
assign ccdi = {ici, aci, dpdi, wad, fifobe, statadi} ;
|
||||
|
||||
assign ccwe = fifoeof ;
|
||||
|
||||
assign ccre = tireq_r & ~tireq_r2 ;
|
||||
|
||||
assign ic = ccdo[CCWIDTH - 1] ;
|
||||
|
||||
assign aco = ccdo[CCWIDTH - 2] ;
|
||||
|
||||
assign dpdo = ccdo[CCWIDTH - 3] ;
|
||||
|
||||
assign eofad_bin = ccdo[CCWIDTH - 4:CCWIDTH - 3 - FIFODEPTH] ;
|
||||
|
||||
always @(posedge clk)
|
||||
begin : eofad_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
eofad <= {FIFODEPTH{1'b0}} ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
eofad[FIFODEPTH - 1] <= eofad_bin[FIFODEPTH - 1] ;
|
||||
begin : eofad_loop
|
||||
integer i;
|
||||
for(i = FIFODEPTH - 2; i >= 0; i = i - 1)
|
||||
begin
|
||||
eofad[i] <= eofad_bin[i] ^ eofad_bin[i + 1] ;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign beo = ccdo[DATADEPTH + DATAWIDTH / 8 - 1:DATADEPTH] ;
|
||||
|
||||
assign statad = ccdo[DATADEPTH - 1:0] ;
|
||||
|
||||
always @(posedge clk)
|
||||
begin : csmem_reg_proc
|
||||
if (rst)
|
||||
begin : csmem_reset
|
||||
integer i;
|
||||
for(i = ((1'b1 << CACHEDEPTH) - 1); i >= 0; i = i - 1)
|
||||
begin
|
||||
csmem[i] <= {CSWIDTH{1'b0}};
|
||||
end
|
||||
csrad_r <= {CACHEDEPTH{1'b0}};
|
||||
end
|
||||
else
|
||||
begin
|
||||
csmem[cswad] <= csdi ;
|
||||
csrad_r <= csrad ;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : csaddr_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
cswad <= {CACHEDEPTH{1'b0}} ;
|
||||
csrad <= {CACHEDEPTH{1'b0}} ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (cswe)
|
||||
begin
|
||||
cswad <= cswad + 1 ;
|
||||
end
|
||||
|
||||
csrad <= csrad_c ;
|
||||
end
|
||||
end
|
||||
|
||||
assign csrad_c = (csre) ? csrad + 1 : csrad ;
|
||||
|
||||
always @(posedge clk)
|
||||
begin : icsne_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
icsne <= 1'b0 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (cswad == csrad | (csre & cswad == csrad_c))
|
||||
begin
|
||||
icsne <= 1'b0 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
icsne <= 1'b1 ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign csne = icsne;
|
||||
|
||||
assign csdo = csmem[csrad_r] ;
|
||||
|
||||
assign csdi = {dei, lci, loi, nci, eci, ic, cci, uri, statad} ;
|
||||
|
||||
assign deo = csdo[CSWIDTH - 1] ;
|
||||
|
||||
assign lco = csdo[CSWIDTH - 2] ;
|
||||
|
||||
assign loo = csdo[CSWIDTH - 3] ;
|
||||
|
||||
assign nco = csdo[CSWIDTH - 4] ;
|
||||
|
||||
assign eco = csdo[CSWIDTH - 5] ;
|
||||
|
||||
assign ico = csdo[CSWIDTH - 6] ;
|
||||
|
||||
assign cco = csdo[CSWIDTH - 7:CSWIDTH - 10] ;
|
||||
|
||||
assign uro = csdo[CSWIDTH - 11] ;
|
||||
|
||||
assign statado = csdo[DATADEPTH - 1:0] ;
|
||||
|
||||
assign cswe = tireq_r & tprog ;
|
||||
|
||||
always @(posedge clk)
|
||||
begin : csre_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
csre <= 1'b0 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
csre <= cachere ;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : tprog_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
tprog <= 1'b0 ;
|
||||
tprog_r <= 1'b0 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
tprog_r <= tprog ;
|
||||
if (tireq_r)
|
||||
begin
|
||||
tprog <= 1'b0 ;
|
||||
end
|
||||
else if ((!sf & !tprog & !tireq_r & tresh) | ccne)
|
||||
begin
|
||||
tprog <= 1'b1 ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : eofreq_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
eofreq <= 1'b0 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (tprog & ccne)
|
||||
begin
|
||||
eofreq <= 1'b1 ;
|
||||
end
|
||||
else if (tireq_r)
|
||||
begin
|
||||
eofreq <= 1'b0 ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : tireq_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
tireq_r <= 1'b0 ;
|
||||
tireq_r2 <= 1'b0 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
tireq_r <= tireq ;
|
||||
tireq_r2 <= tireq_r ;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : etireq_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
etireq <= 1'b0 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (fifoeof)
|
||||
begin
|
||||
etireq <= 1'b1 ;
|
||||
end
|
||||
else if (etiack)
|
||||
begin
|
||||
etireq <= 1'b0 ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign tiack = tireq_r2 ;
|
||||
|
||||
assign sofreq = tprog ;
|
||||
|
||||
always @(posedge clk)
|
||||
begin : addr_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
wad <= {FIFODEPTH{1'b0}} ;
|
||||
wadg <= {FIFODEPTH{1'b0}} ;
|
||||
radg_0_r <= {FIFODEPTH{1'b0}} ;
|
||||
radg_r <= {FIFODEPTH{1'b0}} ;
|
||||
rad <= {FIFODEPTH{1'b0}} ;
|
||||
sad <= {FIFODEPTH{1'b0}} ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (fifowe)
|
||||
begin
|
||||
wad <= wad + 1 ;
|
||||
end
|
||||
|
||||
wadg[FIFODEPTH - 1] <= wad[FIFODEPTH - 1] ;
|
||||
begin : wadg_loop
|
||||
integer i;
|
||||
for(i = FIFODEPTH - 2; i >= 0; i = i - 1)
|
||||
begin
|
||||
wadg[i] <= wad[i] ^ wad[i + 1] ;
|
||||
end
|
||||
end
|
||||
|
||||
radg_0_r <= radg ;
|
||||
radg_r <= radg_0_r ;
|
||||
|
||||
rad <= rad_c ;
|
||||
|
||||
if (!tprog & tprog_r)
|
||||
begin
|
||||
sad <= eofad_bin ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(radg_r)
|
||||
begin : rad_proc
|
||||
reg[FIFODEPTH - 1:0] rad_v;
|
||||
rad_v[FIFODEPTH - 1] = radg_r[FIFODEPTH - 1];
|
||||
begin : rad_loop
|
||||
integer i;
|
||||
for(i = FIFODEPTH - 2; i >= 0; i = i - 1)
|
||||
begin
|
||||
rad_v[i] = rad_v[i + 1] ^ radg_r[i];
|
||||
end
|
||||
end
|
||||
rad_c = rad_v ;
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : stat_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
stat <= {FIFODEPTH{1'b0}} ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if ((!winp_r & !fdp & tprog & !tireq_r) | !tprog_r)
|
||||
begin
|
||||
stat <= wad - sad ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
stat <= wad - rad ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : winp_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
winp_r <= 1'b0 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
winp_r <= winp ;
|
||||
end
|
||||
end
|
||||
|
||||
always @(tm)
|
||||
begin : tresh_proc
|
||||
tlev_c <= {FIFODEPTH_MAX{1'b0}} ;
|
||||
case (DATAWIDTH)
|
||||
8 :
|
||||
begin
|
||||
case (tm)
|
||||
3'b000, 3'b101, 3'b110 :
|
||||
begin
|
||||
tlev_c[10:0] <= 11'b00010000000 ;
|
||||
end
|
||||
3'b001, 3'b111 :
|
||||
begin
|
||||
tlev_c[10:0] <= 11'b00100000000 ;
|
||||
end
|
||||
3'b010 :
|
||||
begin
|
||||
tlev_c[10:0] <= 11'b01000000000 ;
|
||||
end
|
||||
3'b011 :
|
||||
begin
|
||||
tlev_c[10:0] <= 11'b10000000000 ;
|
||||
end
|
||||
default :
|
||||
begin
|
||||
tlev_c[10:0] <= 11'b00001000000 ;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
16 :
|
||||
begin
|
||||
case (tm)
|
||||
3'b000, 3'b101, 3'b110 :
|
||||
begin
|
||||
tlev_c[10:0] <= 11'b00001000000 ;
|
||||
end
|
||||
3'b001, 3'b111 :
|
||||
begin
|
||||
tlev_c[10:0] <= 11'b00010000000 ;
|
||||
end
|
||||
3'b010 :
|
||||
begin
|
||||
tlev_c[10:0] <= 11'b00100000000 ;
|
||||
end
|
||||
3'b011 :
|
||||
begin
|
||||
tlev_c[10:0] <= 11'b01000000000 ;
|
||||
end
|
||||
default :
|
||||
begin
|
||||
tlev_c[10:0] <= 11'b00000100000 ;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
default :
|
||||
begin
|
||||
case (tm)
|
||||
3'b000, 3'b101, 3'b110 :
|
||||
begin
|
||||
tlev_c[10:0] <= 11'b00000100000 ;
|
||||
end
|
||||
3'b001, 3'b111 :
|
||||
begin
|
||||
tlev_c[10:0] <= 11'b00001000000 ;
|
||||
end
|
||||
3'b010 :
|
||||
begin
|
||||
tlev_c[10:0] <= 11'b00010000000 ;
|
||||
end
|
||||
3'b011 :
|
||||
begin
|
||||
tlev_c[10:0] <= 11'b00100000000 ;
|
||||
end
|
||||
default :
|
||||
begin
|
||||
tlev_c[10:0] <= 11'b00000010000 ;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : tresh_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
tresh <= 1'b0 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (stat >= tlev_c[FIFODEPTH - 1:0])
|
||||
begin
|
||||
tresh <= 1'b1 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
tresh <= 1'b0 ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(pbl or pblz)
|
||||
begin : sflev_proc
|
||||
sflev_c[FIFODEPTH_MAX - 1:6] <= {(FIFODEPTH_MAX-6){1'b1}} ;
|
||||
if (pblz)
|
||||
begin
|
||||
sflev_c[5:0] <= 6'b000000 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
sflev_c[5:0] <= ~pbl ;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : fifoval_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
fifoval <= 1'b0 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (stat <= sflev_c[FIFODEPTH - 1:0])
|
||||
begin
|
||||
fifoval <= 1'b1 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
fifoval <= 1'b0 ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : pblz_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
pblz <= 1'b0 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (pbl == 6'b000000)
|
||||
begin
|
||||
pblz <= 1'b1 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
pblz <= 1'b0 ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin : fifonf_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
fifonf <= 1'b1 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if ((stat == {fone[FIFODEPTH - 1:1], 1'b0} & fifowe) |
|
||||
(stat == fone))
|
||||
begin
|
||||
fifonf <= 1'b0 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
fifonf <= 1'b1 ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign flev = stat ;
|
||||
|
||||
assign ramaddr = wad ;
|
||||
|
||||
assign ramdata = fifodata ;
|
||||
|
||||
assign ramwe = fifowe ;
|
||||
|
||||
always @(posedge clk)
|
||||
begin : tstop_reg_proc
|
||||
if (rst)
|
||||
begin
|
||||
stop_r <= 1'b1 ;
|
||||
stopo <= 1'b0 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
stop_r <= stopi ;
|
||||
|
||||
if (stop_r & !ccne & !icsne & stat == fzero & !tprog)
|
||||
begin
|
||||
stopo <= 1'b1 ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
stopo <= 1'b0 ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign fone = {FIFODEPTH{1'b1}} ;
|
||||
|
||||
assign fzero = {FIFODEPTH{1'b0}} ;
|
||||
|
||||
endmodule
|
2197
resources/soc/rtl/MAC/tlsm.v
Normal file
2197
resources/soc/rtl/MAC/tlsm.v
Normal file
File diff suppressed because it is too large
Load Diff
282
resources/soc/rtl/MAC/utility.v
Normal file
282
resources/soc/rtl/MAC/utility.v
Normal file
@ -0,0 +1,282 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
//-----------------------------------------------------------------
|
||||
// 802.3 parameters
|
||||
//-----------------------------------------------------------------
|
||||
// interframe space 1 interval = 60 bit times
|
||||
parameter [3:0] IFS1_TIME = 4'b1110;
|
||||
// interframe space 2 interval = 36 bit times
|
||||
//parameter [3:0] IFS2_TIME = 4'b1000;
|
||||
parameter [3:0] IFS2_TIME = 4'b0110;
|
||||
// slot time interfal = 512 bit times
|
||||
parameter [8:0] SLOT_TIME = 9'b001111111;
|
||||
// maximum number of retransmission attempts = 16
|
||||
parameter [4:0] ATT_MAX = 5'b10000;
|
||||
// proper crc remainder value = 0xc704dd7b
|
||||
parameter [31:0] CRCVAL = 32'b11000111000001001101110101111011;
|
||||
// minimum frame size = 64
|
||||
parameter [6:0] MIN_FRAME = 7'b1000000;
|
||||
// maximum ethernet frame length field value = 1500
|
||||
parameter [15:0] MAX_SIZE = 16'b0000010111011100;
|
||||
// maximum frame size
|
||||
parameter [13:0] MAX_FRAME = 14'b00010111101111; // 1519
|
||||
|
||||
//_________________________________________________________________
|
||||
// Control and Status Register summary
|
||||
//_________________________________________________________________
|
||||
// Register | ID | RV | Description
|
||||
//_________________________________________________________________
|
||||
// CSR0 | 00h | fe000000h | Bus mode
|
||||
// CSR1 | 08h | ffffffffh | Transmit pool demand
|
||||
// CSR2 | 10h | ffffffffh | Teceive pool demand
|
||||
// CSR3 | 18h | ffffffffh | Receive list base address
|
||||
// CSR4 | 20h | ffffffffh | Rransmit list base address
|
||||
// CSR5 | 28h | f0000000h | Status
|
||||
// CSR6 | 30h | 32000040h | Operation mode
|
||||
// CSR7 | 38h | f3fe0000h | Interrupt enable
|
||||
// CSR8 | 40h | e0000000h | Missed frames and overflow cnt
|
||||
// CSR9 | 48h | fff483ffh | MII management
|
||||
// CSR11 | 58h | fffe0000h | Timer and interrupt mitigation
|
||||
//_________________________________________________________________
|
||||
|
||||
//-----------------------------------------------------------------
|
||||
// Special Function Register locations and reset values
|
||||
//-----------------------------------------------------------------
|
||||
// CSR0 : 00h : fe000000h : Bus mode
|
||||
parameter [5:0] CSR0_ID = 6'b000000;
|
||||
// CSR0 reset value
|
||||
parameter [31:0] CSR0_RV = 32'b11111110000000000000000000000000;
|
||||
|
||||
// CSR1 : 08h : ffffffffh : Transmit pool demand
|
||||
parameter [5:0] CSR1_ID = 6'b000010;
|
||||
// CSR1 reset value
|
||||
parameter [31:0] CSR1_RV = 32'b11111111111111111111111111111111;
|
||||
|
||||
// CSR2 : 10h : ffffffffh : Receive pool demand
|
||||
parameter [5:0] CSR2_ID = 6'b000100;
|
||||
// CSR2 reset value
|
||||
parameter [31:0] CSR2_RV = 32'b11111111111111111111111111111111;
|
||||
|
||||
// CSR3 : 18h : ffffffffh : Receive list base address
|
||||
parameter [5:0] CSR3_ID = 6'b000110;
|
||||
// CSR3 reset value
|
||||
parameter [31:0] CSR3_RV = 32'b11111111111111111111111111111111;
|
||||
|
||||
// CSR4 : 20h : ffffffffh : Transmit list base address
|
||||
parameter [5:0] CSR4_ID = 6'b001000;
|
||||
// CSR4 reset value
|
||||
parameter [31:0] CSR4_RV = 32'b11111111111111111111111111111111;
|
||||
|
||||
// CSR5 : 28h : f0000000h : Status
|
||||
parameter [5:0] CSR5_ID = 6'b001010;
|
||||
// CSR5 reset value
|
||||
parameter [31:0] CSR5_RV = 32'b11110000000000000000000000000000;
|
||||
|
||||
// CSR6 : 30h : 32000040h : Operation mode
|
||||
parameter [5:0] CSR6_ID = 6'b001100;
|
||||
// CSR6 reset value
|
||||
parameter [31:0] CSR6_RV = 32'b00110010000000000000000001000000;
|
||||
|
||||
// CSR7 : 38h : f3fe0000h : Interrupt enable
|
||||
parameter [5:0] CSR7_ID = 6'b001110;
|
||||
// CSR7 reset value
|
||||
parameter [31:0] CSR7_RV = 32'b11110011111111100000000000000000;
|
||||
|
||||
// CSR8 : 40h : e0000000h : Missed frames and overflow cnt
|
||||
parameter [5:0] CSR8_ID = 6'b010000;
|
||||
// CSR8 reset value
|
||||
parameter [31:0] CSR8_RV = 32'b11100000000000000000000000000000;
|
||||
|
||||
// CSR9 : 48h : fff483ffh : MII menagement
|
||||
parameter [5:0] CSR9_ID = 6'b010010;
|
||||
// CSR9 reset value
|
||||
parameter [31:0] CSR9_RV = 32'b11111111111101001000001111111111;
|
||||
|
||||
// CSR10 : 50h : 00000000h : Insert function enable
|
||||
parameter [5:0] CSR10_ID = 6'b010100;
|
||||
// CSR11 reset value
|
||||
parameter [31:0] CSR10_RV = 32'b00000000000000000000000000000000;
|
||||
|
||||
// CSR11 : 58h : fffe0000h : Timer and interrupt mitigation
|
||||
parameter [5:0] CSR11_ID = 6'b010110;
|
||||
// CSR11 reset value
|
||||
parameter [31:0] CSR11_RV = 32'b11111111111111100000000000000000;
|
||||
|
||||
// TDES0
|
||||
parameter [31:0] TDES0_RV = 32'b00000000000000000000000000000000;
|
||||
|
||||
// SET0
|
||||
parameter [31:0] SET0_RV = 32'b00000000000000000000000000000000;
|
||||
|
||||
// RDES0
|
||||
parameter [31:0] RDES0_RV = 32'b00000000000000000000000000000000;
|
||||
|
||||
//-----------------------------------------------------------------
|
||||
// Internal interface parameters
|
||||
//-----------------------------------------------------------------
|
||||
// CSR interface address width
|
||||
parameter CSRDEPTH = 8;
|
||||
// Filtering RAM address width
|
||||
parameter ADDRDEPTH = 6;
|
||||
// Filtering RAM data width
|
||||
parameter ADDRWIDTH = 16;
|
||||
// Maximum FIFO depth
|
||||
parameter FIFODEPTH_MAX = 15;
|
||||
// Maximum Data interface address width
|
||||
parameter DATADEPTH_MAX = 32;
|
||||
// Maximum Data interface width
|
||||
parameter DATAWIDTH_MAX = 32;
|
||||
// Maximum CSR interface width
|
||||
parameter CSRWIDTH_MAX = 32;
|
||||
// MII width
|
||||
parameter MIIWIDTH = 4;
|
||||
parameter MIIWIDTH_MAX = 8;
|
||||
|
||||
|
||||
//-----------------------------------------------------------------
|
||||
// Filtering modes
|
||||
//-----------------------------------------------------------------
|
||||
// Filtering mode - PREFECT --
|
||||
parameter [1:0] FT_PERFECT = 2'b00;
|
||||
// Filtering mode - HASH --
|
||||
parameter [1:0] FT_HASH = 2'b01;
|
||||
// Filtering mode - INVERSE --
|
||||
parameter [1:0] FT_INVERSE = 2'b10;
|
||||
// Filtering mode - HONLY --
|
||||
parameter [1:0] FT_HONLY = 2'b11;
|
||||
|
||||
//-----------------------------------------------------------------
|
||||
// Phisical address position in setup frame
|
||||
//-----------------------------------------------------------------
|
||||
parameter [5:0] PERF1_ADDR = 6'b100111;
|
||||
|
||||
//-----------------------------------------------------------------
|
||||
// Ethernet frame fields
|
||||
//-----------------------------------------------------------------
|
||||
// jam field pattern
|
||||
parameter [63:0] JAM_PATTERN = 64'b1010101010101010101010101010101010101010101010101010101010101010;
|
||||
// preamble field pattern
|
||||
parameter [63:0] PRE_PATTERN = 64'b0101010101010101010101010101010101010101010101010101010101010101;
|
||||
// start of frame delimiter pattern
|
||||
parameter [63:0] SFD_PATTERN = 64'b1101010111010101110101011101010111010101110101011101010111010101;
|
||||
// padding field pattern
|
||||
parameter [63:0] PAD_PATTERN = 64'b0000000000000000000000000000000000000000000000000000000000000000;
|
||||
// carrier extension pattern
|
||||
parameter [63:0] EXT_PATTERN = 64'b0000111100001111000011110000111100001111000011110000111100001111;
|
||||
|
||||
//-----------------------------------------------------------------
|
||||
// Enumeration types
|
||||
//-----------------------------------------------------------------
|
||||
|
||||
// DMA state machine
|
||||
parameter [1:0] DSM_IDLE = 0;
|
||||
parameter [1:0] DSM_CH1 = 1;
|
||||
parameter [1:0] DSM_CH2 = 2;
|
||||
|
||||
// process state machine type for HC
|
||||
parameter [1:0] PSM_RUN = 0;
|
||||
parameter [1:0] PSM_SUSPEND = 1;
|
||||
parameter [1:0] PSM_STOP = 2;
|
||||
|
||||
// receive state machine for HC
|
||||
parameter [2:0] RSM_IDLE = 0;
|
||||
parameter [2:0] RSM_ACQ1 = 1; // trying to acquire free descriptor
|
||||
parameter [2:0] RSM_ACQ2 = 2; // trying to acquire free descriptor
|
||||
parameter [2:0] RSM_REC = 3; // receiving frame
|
||||
parameter [2:0] RSM_STORE = 4; // storing frame
|
||||
parameter [2:0] RSM_STAT = 5; // status of the frame
|
||||
|
||||
// linked list state machine for HC
|
||||
parameter [3:0] LSM_IDLE = 0;
|
||||
parameter [3:0] LSM_DES0P = 1; // des0 prefetching
|
||||
parameter [3:0] LSM_DES0 = 2; // des0 fetching
|
||||
parameter [3:0] LSM_DES1 = 3; // des1 fetching
|
||||
parameter [3:0] LSM_DES2 = 4; // des2 fetching
|
||||
parameter [3:0] LSM_DES3 = 5; // des3 fetching
|
||||
parameter [3:0] LSM_BUF1 = 6; // buffer 1 fetching
|
||||
parameter [3:0] LSM_BUF2 = 7; // buffer 2 fetching
|
||||
parameter [3:0] LSM_STAT = 8; // descriptor status storing
|
||||
parameter [3:0] LSM_FSTAT = 9; // frame status storing
|
||||
parameter [3:0] LSM_NXT = 10; // next descriptor's address computing
|
||||
|
||||
// descriptor's control state machine for HC
|
||||
parameter [2:0] CSM_IDLE = 0;
|
||||
parameter [2:0] CSM_F = 1; // first descriptor
|
||||
parameter [2:0] CSM_I = 2; // intermediate descriptor
|
||||
parameter [2:0] CSM_L = 3; // last descriptor
|
||||
parameter [2:0] CSM_FL = 4; // first and last descriptor
|
||||
parameter [2:0] CSM_SET = 5; // setup frame descriptor
|
||||
parameter [2:0] CSM_BAD = 6; // invalid descriptor
|
||||
|
||||
// master interface state machine for HC
|
||||
parameter [1:0] MSM_IDLE = 0;
|
||||
parameter [1:0] MSM_REQ = 1;
|
||||
parameter [1:0] MSM_BURST = 2;
|
||||
|
||||
// receive state machine for RC
|
||||
parameter [3:0] RSM_IDLE_RCSMT = 0;
|
||||
parameter [3:0] RSM_SFD = 1;
|
||||
parameter [3:0] RSM_DEST = 2;
|
||||
parameter [3:0] RSM_SOURCE = 3;
|
||||
parameter [3:0] RSM_LENGTH = 4;
|
||||
parameter [3:0] RSM_INFO = 5;
|
||||
parameter [3:0] RSM_SUCC = 6;
|
||||
parameter [3:0] RSM_INT = 7;
|
||||
parameter [3:0] RSM_INT1 = 8;
|
||||
parameter [3:0] RSM_BAD = 9; // flushing received frame from fifo
|
||||
|
||||
// address filtering state machine
|
||||
parameter [2:0] FSM_IDLE = 0;
|
||||
parameter [2:0] FSM_PERF1 = 1; // checking single physical address
|
||||
parameter [2:0] FSM_PERF16 = 2; // checking 16 addresses
|
||||
parameter [2:0] FSM_HASH = 3; // hash fitering
|
||||
parameter [2:0] FSM_MATCH = 4; // address match
|
||||
parameter [2:0] FSM_FAIL = 5; // address failed
|
||||
|
||||
// deffering state machine for TC
|
||||
parameter [1:0] DSM_WAIT = 0; // end of IFS, waiting for pending frame
|
||||
parameter [1:0] DSM_IFS1 = 1; // calculating interframe space time 1
|
||||
parameter [1:0] DSM_IFS2 = 2; // calculating interframe space time 2
|
||||
|
||||
// transmit state machine for TC
|
||||
parameter [3:0] TSM_IDLE_TCSMT = 0;
|
||||
parameter [3:0] TSM_PREA = 1;
|
||||
parameter [3:0] TSM_SFD = 2;
|
||||
parameter [3:0] TSM_INFO = 3;
|
||||
parameter [3:0] TSM_PAD = 4;
|
||||
parameter [3:0] TSM_CRC = 5;
|
||||
parameter [3:0] TSM_BURST = 6;
|
||||
parameter [3:0] TSM_JAM = 7;
|
||||
parameter [3:0] TSM_FLUSH = 8;
|
||||
parameter [3:0] TSM_INT = 9;
|
896
resources/soc/rtl/SPI/godson_sbridge_spi.v
Normal file
896
resources/soc/rtl/SPI/godson_sbridge_spi.v
Normal file
@ -0,0 +1,896 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
module spi_flash_ctrl(
|
||||
input aclk,
|
||||
input aresetn,
|
||||
input [15:0] spi_addr,
|
||||
input power_down_req,
|
||||
output power_down_ack,
|
||||
input fast_startup,
|
||||
|
||||
input [3:0] s_awlen,
|
||||
input [3:0] s_awcache,
|
||||
input [3:0] s_awid,
|
||||
input [31:0] s_awaddr,
|
||||
input [2:0] s_awsize,
|
||||
input [2:0] s_awprot,
|
||||
input [1:0] s_awburst,
|
||||
input [1:0] s_awlock,
|
||||
input s_awvalid,
|
||||
output s_awready,
|
||||
|
||||
input [3:0] s_wid,
|
||||
input [31:0] s_wdata,
|
||||
input [3:0] s_wstrb,
|
||||
input s_wlast,
|
||||
input s_wvalid,
|
||||
output s_wready,
|
||||
|
||||
output [3:0] s_bid,
|
||||
output [1:0] s_bresp,
|
||||
output s_bvalid,
|
||||
input s_bready,
|
||||
|
||||
input [3:0] s_arlen,
|
||||
input [3:0] s_arcache,
|
||||
input [3:0] s_arid,
|
||||
input [31:0] s_araddr,
|
||||
input [2:0] s_arsize,
|
||||
input [2:0] s_arprot,
|
||||
input [1:0] s_arburst,
|
||||
input [1:0] s_arlock,
|
||||
input s_arvalid,
|
||||
output s_arready,
|
||||
|
||||
output [3:0] s_rid,
|
||||
output [31:0] s_rdata,
|
||||
output [1:0] s_rresp,
|
||||
output s_rlast,
|
||||
output s_rvalid,
|
||||
input s_rready,
|
||||
|
||||
output [3:0] csn_o,
|
||||
output [3:0] csn_en,
|
||||
output sck_o,
|
||||
input sdo_i,
|
||||
output sdo_o,
|
||||
output sdo_en,
|
||||
input sdi_i,
|
||||
output sdi_o,
|
||||
output sdi_en,
|
||||
output inta_o
|
||||
);
|
||||
|
||||
wire areset = ~aresetn;
|
||||
|
||||
wire param_memory_en;
|
||||
wire param_burst_en;
|
||||
wire param_fast_read;
|
||||
wire param_dual_io;
|
||||
wire [1:0] param_tCSH;
|
||||
wire param_tFAST;
|
||||
|
||||
reg [9:0] rd_state;
|
||||
reg [9:0] rd_state_nxt;
|
||||
|
||||
parameter S_IDLE = 10'b0000000001;
|
||||
parameter S_IOREAD = 10'b0000000010;
|
||||
parameter S_CSTURN = 10'b0000000100;
|
||||
parameter S_ADDR = 10'b0000001000;
|
||||
parameter S_DATA = 10'b0000010000;
|
||||
parameter S_WAITBUS= 10'b0000100000;
|
||||
parameter S_PDENTER= 10'b0001000000;
|
||||
parameter S_PDEXIT = 10'b0010000000;
|
||||
parameter S_STARTUP= 10'b0100000000;
|
||||
parameter S_PWRDOWN= 10'b1000000000;
|
||||
|
||||
wire s_idle = rd_state[0];
|
||||
wire s_ioread = rd_state[1];
|
||||
wire s_csturn = rd_state[2];
|
||||
wire s_addr = rd_state[3];
|
||||
wire s_data = rd_state[4];
|
||||
wire s_waitbus= rd_state[5];
|
||||
wire s_pdenter= rd_state[6];
|
||||
wire s_pdexit = rd_state[7];
|
||||
wire s_startup= rd_state[8];
|
||||
wire s_pwrdown= rd_state[9];
|
||||
|
||||
wire ns_idle = rd_state_nxt[0];
|
||||
wire ns_ioread = rd_state_nxt[1];
|
||||
wire ns_csturn = rd_state_nxt[2];
|
||||
wire ns_addr = rd_state_nxt[3];
|
||||
wire ns_data = rd_state_nxt[4];
|
||||
wire ns_waitbus= rd_state_nxt[5];
|
||||
wire ns_pdenter= rd_state_nxt[6];
|
||||
wire ns_pdexit = rd_state_nxt[7];
|
||||
wire ns_startup= rd_state_nxt[8];
|
||||
wire ns_pwrdown= rd_state_nxt[9];
|
||||
|
||||
reg pdreq_r;
|
||||
|
||||
reg [15:0] cs_timer;
|
||||
reg cs;
|
||||
reg [23:0] nxt_addr;
|
||||
|
||||
wire write_valid;
|
||||
wire reg_acc = s_ioread | write_valid;
|
||||
wire reg_ack;
|
||||
wire [7:0] reg_dat_i, reg_dat_o;
|
||||
wire [7:0] param_o;
|
||||
|
||||
reg [31:0] shift_reg;
|
||||
reg [ 1:0] sample;
|
||||
wire [31:0] shift_reg_nxt;
|
||||
wire sr_shift_inst;
|
||||
wire sr_shift_one;
|
||||
wire sr_shift_two;
|
||||
reg sr_shift_inst_r;
|
||||
reg sr_shift_two_r;
|
||||
wire sample_en;
|
||||
wire shift_en;
|
||||
wire dual_out;
|
||||
wire dual_in;
|
||||
wire [1:0] serial_out;
|
||||
wire cyc_end;
|
||||
|
||||
|
||||
reg [2:0] bit_cnt;
|
||||
wire spi_pause;
|
||||
wire spibus_busy;
|
||||
|
||||
reg [5:0] adbit_cnt;
|
||||
reg spi_run;
|
||||
reg sck;
|
||||
|
||||
reg buf_busy;
|
||||
reg [31:0] buf_addr;
|
||||
reg [ 3:0] buf_len;
|
||||
reg [ 2:0] buf_size;
|
||||
reg [ 3:0] buf_id;
|
||||
reg buf_write;
|
||||
reg buf_wrap;
|
||||
|
||||
assign s_arready = s_idle & ~pdreq_r & ~buf_busy & ~s_awvalid;
|
||||
assign s_awready = s_idle & ~pdreq_r & ~buf_busy;
|
||||
|
||||
reg buf_busy_d;
|
||||
wire new_axireq = ~buf_busy_d & buf_busy;
|
||||
wire io_hit =(buf_addr[31:4] == {spi_addr, 12'b0}) &
|
||||
(buf_len == 4'b0);
|
||||
|
||||
wire [63:0] buf_addr_t = (buf_addr[31:20]==12'h1fc)?
|
||||
{12'h0, buf_addr[19:0]}:
|
||||
{ 8'h0, buf_addr[23:0]};
|
||||
|
||||
wire burst_cont = param_burst_en & cs &
|
||||
(buf_addr_t[23:0] == nxt_addr[23:0]);
|
||||
|
||||
wire burst_switch = param_burst_en & cs &
|
||||
(buf_addr_t[23:0] != nxt_addr[23:0]);
|
||||
|
||||
reg [7:0] tot_bytes;
|
||||
wire byte_ready;
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (areset) begin
|
||||
buf_busy <= 1'b0;
|
||||
buf_write <= 1'b0;
|
||||
tot_bytes <= 8'b0;
|
||||
end else begin
|
||||
if ((s_arvalid|s_awvalid)&~buf_busy&s_idle&~pdreq_r) begin
|
||||
buf_busy <= 1'b1;
|
||||
buf_addr <= s_awvalid ? s_awaddr : s_araddr;
|
||||
buf_size <= s_awvalid ? s_awsize : s_arsize;
|
||||
buf_len <= s_awvalid ? s_awlen : s_arlen;
|
||||
buf_id <= s_awvalid ? s_awid : s_arid;
|
||||
buf_write<= s_awvalid;
|
||||
buf_wrap <= s_arvalid & (s_arburst==2'b10) &
|
||||
(|s_araddr[4:2]) & (|s_arlen);
|
||||
tot_bytes<= {8{s_arvalid&~s_awvalid}}&
|
||||
(({4'b0,s_arlen} << s_arsize)|
|
||||
((8'b1<<s_arsize)-8'b1));
|
||||
end else begin
|
||||
if (s_bvalid & s_bready | s_rvalid & s_rready & s_rlast)
|
||||
buf_busy <= 1'b0;
|
||||
if (s_rvalid & s_rready)
|
||||
buf_len <= buf_len - 4'b1;
|
||||
if (s_wvalid & s_wready & s_wlast)
|
||||
buf_write <= 1'b0;
|
||||
if (byte_ready & ~s_rvalid) begin
|
||||
tot_bytes <= tot_bytes - 8'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
buf_busy_d <= buf_busy;
|
||||
end
|
||||
|
||||
reg second_write;
|
||||
always @(posedge aclk) begin
|
||||
if (areset) second_write <= 1'b0;
|
||||
else second_write <= (s_wvalid & s_wready & io_hit & (buf_size==3'b1) & (buf_addr[2:0]==3'b10));
|
||||
end
|
||||
|
||||
assign s_wready = buf_busy & buf_write & s_idle;
|
||||
assign write_valid = s_wvalid & s_wready & io_hit &
|
||||
((buf_size==3'b0) | (buf_size==3'b1 && buf_addr[2:0]==3'b10)) |
|
||||
second_write;
|
||||
|
||||
reg bvalid;
|
||||
always @(posedge aclk) begin
|
||||
if (areset ) bvalid <= 1'b0;
|
||||
else if (s_bvalid & s_bready ) bvalid <= 1'b0;
|
||||
else if (s_wvalid & s_wready & s_wlast) bvalid <= 1'b1;
|
||||
end
|
||||
assign s_bvalid = bvalid;
|
||||
assign s_bid = buf_id;
|
||||
assign s_bresp = 2'b00;
|
||||
|
||||
|
||||
reg rvalid;
|
||||
reg [7:0] rdata[3:0];
|
||||
always @(posedge aclk) begin
|
||||
if (areset)
|
||||
rvalid <= 1'b0;
|
||||
else if (s_rvalid & s_rready) begin
|
||||
rvalid <= 1'b0;
|
||||
end else if (new_axireq & ~buf_write & io_hit & s_idle) begin
|
||||
rvalid <= 1'b1;
|
||||
rdata[buf_addr[1:0]] <= reg_dat_o;
|
||||
end else if (s_data & byte_ready & ~rvalid) begin
|
||||
rvalid <= (&nxt_addr[1:0]) | (~|tot_bytes);
|
||||
rdata[nxt_addr[1:0]] <= shift_reg_nxt[7:0];
|
||||
end
|
||||
end
|
||||
assign s_rvalid = rvalid;
|
||||
assign s_rdata = {rdata[ 3], rdata[ 2], rdata[ 1], rdata[ 0]};
|
||||
assign s_rlast = ~|buf_len;
|
||||
assign s_rid = buf_id;
|
||||
assign s_rresp = 2'b00;
|
||||
|
||||
wire [1:0] sample_in = {2{s_data}}&(param_tFAST ? {sdi_i, sdo_i} :
|
||||
sample[1:0] );
|
||||
|
||||
assign shift_reg_nxt = sr_shift_inst_r?{shift_reg[30:0], 1'b0 }:
|
||||
sr_shift_two_r ?{shift_reg[29:0], sample_in[1:0]}:
|
||||
{shift_reg[30:0], sample_in[1] };
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (s_pwrdown & ~ns_pwrdown) begin
|
||||
shift_reg[31:24] <= 8'hab;
|
||||
end else if (~s_pdenter & ns_pdenter) begin
|
||||
shift_reg[31:24] <= 8'hb9;
|
||||
end else if (~s_addr & ns_addr) begin
|
||||
shift_reg[31:24] <= param_dual_io ? 8'hbb:
|
||||
param_fast_read ? 8'h0b:
|
||||
8'h03;
|
||||
shift_reg[23: 0] <= nxt_addr[23:0];
|
||||
end else if (shift_en) begin
|
||||
shift_reg[31: 0] <= shift_reg_nxt;
|
||||
end
|
||||
if (sample_en) sample[1:0] <= {sdi_i, sdo_i};
|
||||
end
|
||||
assign serial_out = param_dual_io & dual_out ? shift_reg[31:30] :
|
||||
{1'b0, shift_reg[31]};
|
||||
|
||||
wire [3:0] espr;
|
||||
reg [11:0] clkcnt;
|
||||
wire clkena = ~|clkcnt & ~spi_pause;
|
||||
reg [3:0] cswcnt;
|
||||
always @(posedge aclk)
|
||||
if (areset)
|
||||
clkcnt <= 12'h0;
|
||||
else if (~spi_pause) begin
|
||||
if ((|clkcnt) & (spi_run|s_csturn))
|
||||
clkcnt <= clkcnt - 11'h1;
|
||||
else
|
||||
case (espr) // synopsys full_case parallel_case
|
||||
4'b0000: clkcnt <= 12'h0;
|
||||
4'b0001: clkcnt <= 12'h1;
|
||||
4'b0010: clkcnt <= 12'h7;
|
||||
4'b0011: clkcnt <= 12'hf;
|
||||
4'b0100: clkcnt <= 12'h3;
|
||||
4'b0101: clkcnt <= 12'h1f;
|
||||
4'b0110: clkcnt <= 12'h3f;
|
||||
4'b0111: clkcnt <= 12'h7f;
|
||||
4'b1000: clkcnt <= 12'hff;
|
||||
4'b1001: clkcnt <= 12'h1ff;
|
||||
4'b1010: clkcnt <= 12'h3ff;
|
||||
4'b1011: clkcnt <= 12'h7ff;
|
||||
default: clkcnt <= 12'h7ff;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge aclk)
|
||||
if (areset|~s_csturn) cswcnt <= 4'b0;
|
||||
else if (clkena) cswcnt <= cswcnt + 4'b1;
|
||||
|
||||
wire [3:0] cswcnt_w = cswcnt | (4'b1110 << param_tCSH);
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (areset ) spi_run <= 1'b0;
|
||||
else if (ns_addr|ns_data) spi_run <= 1'b1;
|
||||
else if (ns_idle|ns_csturn)spi_run <= 1'b0;
|
||||
else if (ns_pdexit |ns_pdenter)spi_run <= 1'b1;
|
||||
else if (ns_startup|ns_pwrdown)spi_run <= 1'b0;
|
||||
|
||||
if (s_idle |s_csturn) adbit_cnt <= 6'b0;
|
||||
else if (s_addr & cyc_end) adbit_cnt <= adbit_cnt + 6'b1;
|
||||
|
||||
if (areset ) sck <= 1'b0;
|
||||
else if (spi_run & clkena) sck <= ~sck;
|
||||
|
||||
if (areset | s_idle ) bit_cnt <= 3'h0;
|
||||
else if (s_data & cyc_end) bit_cnt <= bit_cnt + 3'b1;
|
||||
else if (s_pdenter&cyc_end)bit_cnt <= bit_cnt + 3'b1;
|
||||
else if (s_pdexit &cyc_end)bit_cnt <= bit_cnt + 3'b1;
|
||||
|
||||
end
|
||||
|
||||
assign byte_ready = s_data & cyc_end & (&({param_dual_io,2'b00}|bit_cnt[2:0]));
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (areset | ~param_memory_en) begin
|
||||
nxt_addr <= 24'b0;
|
||||
cs_timer <= 16'b0;
|
||||
cs <= 1'b0;
|
||||
end else begin
|
||||
nxt_addr <= new_axireq & s_idle ? buf_addr_t :
|
||||
byte_ready & ~spi_pause? (buf_wrap&(&nxt_addr[4:0]) & ~(tot_bytes == 8'b0)?
|
||||
nxt_addr - 24'h1f :
|
||||
nxt_addr + 24'b1) :
|
||||
nxt_addr;
|
||||
cs_timer <= buf_busy|(~cs&~s_startup)|s_pdexit ? 16'b0 :
|
||||
~&cs_timer ? cs_timer+16'b1 :
|
||||
cs_timer ;
|
||||
cs <= ns_addr ? 1'b1 :
|
||||
ns_csturn | (~buf_busy & (&cs_timer)) ? 1'b0 :
|
||||
~param_burst_en & ns_idle ? 1'b0 :
|
||||
write_valid & (buf_addr[3:0]==4'h2) ? 1'b0 :
|
||||
ns_pdenter | ns_pdexit ? 1'b1 :
|
||||
ns_pwrdown | ns_startup ? 1'b0 :
|
||||
cs;
|
||||
end
|
||||
end
|
||||
|
||||
assign cyc_end = spi_run & sck & clkena;
|
||||
|
||||
assign shift_en = spi_run & sck & clkena;
|
||||
assign sample_en = spi_run &~sck & clkena & s_data;
|
||||
|
||||
assign spi_pause = rvalid;
|
||||
|
||||
assign sr_shift_inst = s_addr & (adbit_cnt < 6'd8);
|
||||
assign sr_shift_two =(s_addr & (adbit_cnt >=6'd8) | s_data) & param_dual_io;
|
||||
always @(posedge aclk) begin
|
||||
sr_shift_inst_r <= areset ? 1'b0 :
|
||||
cyc_end|(~s_addr&ns_addr) ? ns_addr & (adbit_cnt < 6'd7) :
|
||||
sr_shift_inst_r;
|
||||
sr_shift_two_r <= areset ? 1'b0 :
|
||||
cyc_end|(~s_data&ns_data) ? (s_addr & (adbit_cnt >=6'd7) | ns_data) & param_dual_io :
|
||||
sr_shift_two_r;
|
||||
end
|
||||
|
||||
assign sr_shift_one = 1'bz;
|
||||
wire addr_done;
|
||||
assign addr_done = param_dual_io ? adbit_cnt == 6'd23 :
|
||||
param_fast_read ? adbit_cnt == 6'd39 :
|
||||
adbit_cnt == 6'd31 ;
|
||||
assign dual_out = param_dual_io &
|
||||
(adbit_cnt >= 6'd8 && adbit_cnt < 6'd22);
|
||||
reg dual_in_r;
|
||||
assign dual_in = param_dual_io &
|
||||
(adbit_cnt >= 6'd22 | s_data | dual_in_r);
|
||||
always @(posedge aclk) begin
|
||||
dual_in_r <= areset ? 1'b0 :
|
||||
s_csturn&cswcnt[0]? 1'b0 :
|
||||
~cs ? 1'b0 :
|
||||
dual_in ? 1'b1 : dual_in_r;
|
||||
end
|
||||
|
||||
|
||||
always @(posedge aclk) begin
|
||||
pdreq_r <= power_down_req;
|
||||
end
|
||||
wire go_power_down = pdreq_r & ~buf_busy;
|
||||
assign power_down_ack = s_pwrdown | s_pdexit | s_startup;
|
||||
|
||||
always @(posedge aclk) begin
|
||||
rd_state <= areset ? S_PWRDOWN : rd_state_nxt;
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
rd_state_nxt = rd_state;
|
||||
case (rd_state) // synopsys parallel_case
|
||||
S_IDLE :if (new_axireq & ~buf_write) begin
|
||||
rd_state_nxt = io_hit ? S_IOREAD:
|
||||
spibus_busy ? S_WAITBUS:
|
||||
burst_cont ? S_DATA :
|
||||
S_CSTURN;
|
||||
end else if (go_power_down) begin
|
||||
rd_state_nxt = cs ? S_CSTURN :
|
||||
S_PDENTER;
|
||||
end
|
||||
S_IOREAD: rd_state_nxt = S_IDLE;
|
||||
S_CSTURN: rd_state_nxt = clkena & (&cswcnt_w)? (go_power_down? S_PDENTER:S_ADDR):
|
||||
S_CSTURN;
|
||||
S_ADDR : rd_state_nxt = clkena & sck &
|
||||
addr_done ? S_DATA : S_ADDR;
|
||||
S_DATA : rd_state_nxt = byte_ready & ~spi_pause & ~|tot_bytes ? S_IDLE:
|
||||
byte_ready & ~spi_pause & buf_wrap
|
||||
& (&nxt_addr[4:0])? S_CSTURN:
|
||||
byte_ready & ~spi_pause & ~param_burst_en ? S_CSTURN:
|
||||
S_DATA;
|
||||
S_WAITBUS:rd_state_nxt = spibus_busy ? S_WAITBUS : S_ADDR;
|
||||
|
||||
S_PWRDOWN:rd_state_nxt = go_power_down ? S_PWRDOWN : S_PDEXIT;
|
||||
S_PDEXIT :rd_state_nxt = cyc_end & (&bit_cnt[2:0]) ? S_STARTUP : S_PDEXIT;
|
||||
S_PDENTER:rd_state_nxt = cyc_end & (&bit_cnt[2:0]) ? S_PWRDOWN : S_PDENTER;
|
||||
S_STARTUP:rd_state_nxt = &(cs_timer[10:0]|{{5{fast_startup}}, 6'b0}) ? S_IDLE :
|
||||
S_STARTUP;
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
wire ss_sck, ss_mosi, ss_miso;
|
||||
wire [7:0] param, softcs, param2;
|
||||
wire sspi_write = buf_write | second_write;
|
||||
|
||||
simple_spi_top simple_spi(
|
||||
.clk_i (aclk ),
|
||||
.rst_i (aresetn ),
|
||||
.cyc_i (buf_busy ),
|
||||
.stb_i (reg_acc ),
|
||||
.adr_i (buf_addr[3:0] ),
|
||||
.we_i (sspi_write ),
|
||||
.dat_i (reg_dat_i ),
|
||||
.dat_o (reg_dat_o ),
|
||||
.ack_o (reg_ack ),
|
||||
.inta_o (inta_o ),
|
||||
|
||||
.sck_o (ss_sck ),
|
||||
.mosi_o (ss_mosi ),
|
||||
.miso_i (ss_miso ),
|
||||
|
||||
.param (param ),
|
||||
.param2 (param2 ),
|
||||
.softcs (softcs ),
|
||||
.busy (spibus_busy )
|
||||
);
|
||||
assign ss_miso = sdi_i;
|
||||
|
||||
assign reg_dat_i = second_write ? s_wdata[ 31: 24] :
|
||||
buf_addr[1:0]==2'h0 ? s_wdata[ 7: 0] :
|
||||
buf_addr[1:0]==2'h1 ? s_wdata[ 15: 8] :
|
||||
buf_addr[1:0]==2'h2 ? s_wdata[ 23: 16] :
|
||||
s_wdata[ 31: 24] ;
|
||||
|
||||
assign param_memory_en = param[0];
|
||||
assign param_burst_en = param[1];
|
||||
assign param_fast_read = param[2];
|
||||
assign param_dual_io = param[3];
|
||||
assign espr = param[7:4];
|
||||
|
||||
assign param_tCSH = param2[1:0];
|
||||
assign param_tFAST = param2[2];
|
||||
assign param_scs = param2[3];
|
||||
|
||||
assign csn_en[0] = param_memory_en? 1'b0: ~softcs[0];
|
||||
assign csn_o [0] = param_memory_en? ~cs : softcs[4];
|
||||
|
||||
assign csn_en[3:1] =~softcs[3:1];
|
||||
assign csn_o [3:1] = softcs[7:5]|{3{cs|(~spibus_busy & param_scs)}};
|
||||
|
||||
assign sdi_en = ~spibus_busy¶m_memory_en? ~dual_out : 1'b1;
|
||||
assign sdi_o = ~spibus_busy¶m_memory_en? serial_out[1] : 1'b0;
|
||||
|
||||
assign sdo_en = ~spibus_busy¶m_memory_en? dual_in : 1'b0;
|
||||
assign sdo_o = ~spibus_busy¶m_memory_en? serial_out[0] | s_data
|
||||
: ss_mosi;
|
||||
|
||||
assign sck_o = ~spibus_busy¶m_memory_en? sck : ss_sck;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module simple_spi_top(
|
||||
input wire clk_i,
|
||||
input wire rst_i,
|
||||
input wire cyc_i,
|
||||
input wire stb_i,
|
||||
input wire [3:0] adr_i,
|
||||
input wire we_i,
|
||||
input wire [7:0] dat_i,
|
||||
output reg [7:0] dat_o,
|
||||
output reg ack_o,
|
||||
output reg inta_o,
|
||||
|
||||
output reg sck_o,
|
||||
output wire mosi_o,
|
||||
input wire miso_i,
|
||||
|
||||
output reg [7:0] param,
|
||||
output reg [7:0] param2,
|
||||
output reg [7:0] softcs,
|
||||
output reg busy
|
||||
);
|
||||
|
||||
reg [7:0] spcr;
|
||||
wire [7:0] spsr;
|
||||
reg [7:0] sper;
|
||||
reg [7:0] treg, rreg;
|
||||
|
||||
wire [7:0] rfdout;
|
||||
reg wfre, rfwe;
|
||||
wire rfre, rffull, rfempty;
|
||||
wire [7:0] wfdout;
|
||||
wire wfwe, wffull, wfempty;
|
||||
|
||||
wire tirq;
|
||||
wire wfov;
|
||||
reg [1:0] state;
|
||||
reg [2:0] bcnt;
|
||||
|
||||
wire wb_acc = cyc_i & stb_i;
|
||||
wire wb_wr = wb_acc & we_i;
|
||||
|
||||
always @(posedge clk_i)
|
||||
if (~rst_i)
|
||||
begin
|
||||
spcr <= 8'h12;
|
||||
sper <= 8'h00;
|
||||
`ifdef FAST_SIMU
|
||||
param<= 8'h1;
|
||||
param2<=8'h07;
|
||||
`else
|
||||
param<= 8'h1;
|
||||
param2<=8'h03;
|
||||
`endif
|
||||
softcs<=8'hf0;
|
||||
end
|
||||
else if (wb_wr)
|
||||
begin
|
||||
if (adr_i == 4'b00)
|
||||
spcr <= dat_i | 8'h10;
|
||||
|
||||
if (adr_i == 4'b11)
|
||||
sper <= dat_i;
|
||||
|
||||
if (adr_i == 4'b0100)
|
||||
param <= dat_i;
|
||||
if (adr_i == 4'b0101)
|
||||
softcs<= dat_i;
|
||||
if (adr_i == 4'b0110)
|
||||
param2 <= dat_i;
|
||||
end
|
||||
|
||||
assign wfwe = wb_acc & (adr_i == 4'b10) & ack_o & we_i;
|
||||
assign wfov = wfwe & wffull;
|
||||
|
||||
always @(*)
|
||||
case(adr_i) // synopsys full_case parallel_case
|
||||
4'b0000: dat_o = spcr;
|
||||
4'b0001: dat_o = spsr;
|
||||
4'b0010: dat_o = rfdout;
|
||||
4'b0011: dat_o = sper;
|
||||
4'b0100: dat_o = param;
|
||||
4'b0101: dat_o = softcs;
|
||||
4'b0110: dat_o = param2;
|
||||
default dat_o = 8'h0;
|
||||
endcase
|
||||
|
||||
assign rfre = wb_acc & (adr_i == 2'b10) & ack_o & ~we_i;
|
||||
|
||||
always @(posedge clk_i)
|
||||
ack_o <= 1'b1;
|
||||
|
||||
wire spie = spcr[7];
|
||||
wire spe = spcr[6];
|
||||
wire dwom = spcr[5];
|
||||
wire mstr = spcr[4];
|
||||
wire cpol = spcr[3];
|
||||
wire cpha = spcr[2];
|
||||
wire [1:0] spr = spcr[1:0];
|
||||
|
||||
wire [1:0] icnt = sper[7:6];
|
||||
wire [1:0] spre = sper[1:0];
|
||||
wire smh_spi= sper[2];
|
||||
|
||||
wire [3:0] espr = {spre, spr};
|
||||
|
||||
wire wr_spsr = wb_wr & (adr_i == 2'b01);
|
||||
|
||||
reg spif;
|
||||
always @(posedge clk_i)
|
||||
if (~spe)
|
||||
spif <= 1'b0;
|
||||
else
|
||||
spif <= (tirq | spif) & ~(wr_spsr & dat_i[7]);
|
||||
|
||||
reg wcol;
|
||||
always @(posedge clk_i)
|
||||
if (~spe)
|
||||
wcol <= 1'b0;
|
||||
else
|
||||
wcol <= (wfov | wcol) & ~(wr_spsr & dat_i[6]);
|
||||
|
||||
assign spsr[7] = spif;
|
||||
assign spsr[6] = wcol;
|
||||
assign spsr[5:4] = 2'b00;
|
||||
assign spsr[3] = wffull;
|
||||
assign spsr[2] = wfempty;
|
||||
assign spsr[1] = rffull;
|
||||
assign spsr[0] = rfempty;
|
||||
|
||||
|
||||
always @(posedge clk_i)
|
||||
inta_o <= spif & spie;
|
||||
|
||||
spi_fifo4 #(8)
|
||||
rfifo(
|
||||
.clk ( clk_i ),
|
||||
.rst ( rst_i ),
|
||||
.clr ( ~spe ),
|
||||
.din ( treg ),
|
||||
.we ( rfwe ),
|
||||
.dout ( rfdout ),
|
||||
.re ( rfre ),
|
||||
.full ( rffull ),
|
||||
.empty ( rfempty )
|
||||
),
|
||||
wfifo(
|
||||
.clk ( clk_i ),
|
||||
.rst ( rst_i ),
|
||||
.clr ( ~spe ),
|
||||
.din ( dat_i ),
|
||||
.we ( wfwe ),
|
||||
.dout ( wfdout ),
|
||||
.re ( wfre ),
|
||||
.full ( wffull ),
|
||||
.empty ( wfempty )
|
||||
);
|
||||
|
||||
reg [11:0] clkcnt;
|
||||
always @(posedge clk_i)
|
||||
if(spe & (|clkcnt & |state))
|
||||
clkcnt <= clkcnt - 11'h1;
|
||||
else
|
||||
case (espr) // synopsys full_case parallel_case
|
||||
4'b0000: clkcnt <= 12'h0;
|
||||
4'b0001: clkcnt <= 12'h1;
|
||||
4'b0010: clkcnt <= 12'h7;
|
||||
4'b0011: clkcnt <= 12'hf;
|
||||
4'b0100: clkcnt <= 12'h3;
|
||||
4'b0101: clkcnt <= 12'h1f;
|
||||
4'b0110: clkcnt <= 12'h3f;
|
||||
4'b0111: clkcnt <= 12'h7f;
|
||||
4'b1000: clkcnt <= 12'hff;
|
||||
4'b1001: clkcnt <= 12'h1ff;
|
||||
4'b1010: clkcnt <= 12'h3ff;
|
||||
4'b1011: clkcnt <= 12'h7ff;
|
||||
default:;
|
||||
endcase
|
||||
|
||||
wire ena = ~|clkcnt;
|
||||
reg sample;
|
||||
always @(posedge clk_i)
|
||||
if (~spe)
|
||||
begin
|
||||
state <= 2'b00;
|
||||
bcnt <= 3'h0;
|
||||
treg <= 8'h00;
|
||||
wfre <= 1'b0;
|
||||
rfwe <= 1'b0;
|
||||
sck_o <= 1'b0;
|
||||
end
|
||||
else if (smh_spi)
|
||||
begin
|
||||
wfre <= 1'b0;
|
||||
rfwe <= 1'b0;
|
||||
|
||||
case (state) //synopsys full_case parallel_case
|
||||
2'b00:
|
||||
begin
|
||||
bcnt <= 3'h7;
|
||||
treg <= wfdout;
|
||||
sck_o <= cpol;
|
||||
|
||||
if (~wfempty) begin
|
||||
wfre <= 1'b1;
|
||||
state <= 2'b01;
|
||||
end
|
||||
end
|
||||
|
||||
2'b01:
|
||||
if (ena) begin
|
||||
sck_o <= ~sck_o;
|
||||
state <= 2'b10;
|
||||
if (cpha==0) sample <= miso_i;
|
||||
end
|
||||
|
||||
2'b10:
|
||||
if (ena) begin
|
||||
sck_o <= ~sck_o;
|
||||
state <= 2'b11;
|
||||
if (cpha==0) begin
|
||||
treg <= {treg[6:0], sample};
|
||||
end else begin
|
||||
sample <= miso_i;
|
||||
end
|
||||
end
|
||||
|
||||
2'b11:
|
||||
if (ena) begin
|
||||
bcnt <= bcnt -3'h1;
|
||||
if (cpha==0) begin
|
||||
sample <= miso_i;
|
||||
end else begin
|
||||
treg <= {treg[6:0], sample};
|
||||
end
|
||||
|
||||
if (~|bcnt) begin
|
||||
state <= 2'b00;
|
||||
sck_o <= cpol;
|
||||
rfwe <= 1'b1;
|
||||
end else begin
|
||||
state <= 2'b10;
|
||||
sck_o <= ~sck_o;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
endcase
|
||||
end
|
||||
else
|
||||
begin
|
||||
wfre <= 1'b0;
|
||||
rfwe <= 1'b0;
|
||||
|
||||
case (state) //synopsys full_case parallel_case
|
||||
2'b00:
|
||||
begin
|
||||
bcnt <= 3'h7;
|
||||
treg <= wfdout;
|
||||
sck_o <= cpol;
|
||||
|
||||
if (~wfempty) begin
|
||||
wfre <= 1'b1;
|
||||
state <= 2'b01;
|
||||
if (cpha) sck_o <= ~sck_o;
|
||||
end
|
||||
end
|
||||
|
||||
2'b01:
|
||||
if (ena) begin
|
||||
sck_o <= ~sck_o;
|
||||
state <= 2'b11;
|
||||
end
|
||||
|
||||
2'b11:
|
||||
if (ena) begin
|
||||
treg <= {treg[6:0], miso_i};
|
||||
bcnt <= bcnt -3'h1;
|
||||
|
||||
if (~|bcnt) begin
|
||||
state <= 2'b00;
|
||||
sck_o <= cpol;
|
||||
rfwe <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
state <= 2'b01;
|
||||
sck_o <= ~sck_o;
|
||||
end
|
||||
end
|
||||
|
||||
2'b10: state <= 2'b00;
|
||||
default: state <=2'b00;
|
||||
endcase
|
||||
end
|
||||
|
||||
assign mosi_o = treg[7];
|
||||
|
||||
reg [1:0] tcnt;
|
||||
always @(posedge clk_i)
|
||||
if (~spe)
|
||||
tcnt <= icnt;
|
||||
else if (rfwe) begin
|
||||
if (|tcnt)
|
||||
tcnt <= tcnt - 2'h1;
|
||||
else
|
||||
tcnt <= icnt;
|
||||
end
|
||||
|
||||
assign tirq = ~|tcnt & rfwe;
|
||||
|
||||
always @(posedge clk_i)
|
||||
busy <= ~wfempty | (|state);
|
||||
endmodule
|
||||
|
||||
module spi_fifo4(clk, rst, clr, din, we, dout, re, full, empty);
|
||||
|
||||
parameter dw = 8;
|
||||
|
||||
input clk, rst;
|
||||
input clr;
|
||||
input [dw:1] din;
|
||||
input we;
|
||||
output [dw:1] dout;
|
||||
input re;
|
||||
output full, empty;
|
||||
|
||||
reg [dw:1] mem[0:3];
|
||||
reg [1:0] wp;
|
||||
reg [1:0] rp;
|
||||
wire [1:0] wp_p1;
|
||||
wire [1:0] wp_p2;
|
||||
wire [1:0] rp_p1;
|
||||
wire full, empty;
|
||||
reg gb;
|
||||
|
||||
always @(posedge clk)
|
||||
if(!rst) wp <= 2'h0;
|
||||
else
|
||||
if(clr) wp <= 2'h0;
|
||||
else
|
||||
if(we) wp <= wp_p1;
|
||||
|
||||
assign wp_p1 = wp + 2'h1;
|
||||
assign wp_p2 = wp + 2'h2;
|
||||
|
||||
always @(posedge clk)
|
||||
if(!rst) rp <= 2'h0;
|
||||
else
|
||||
if(clr) rp <= 2'h0;
|
||||
else
|
||||
if(re) rp <= rp_p1;
|
||||
|
||||
assign rp_p1 = rp + 2'h1;
|
||||
|
||||
assign dout = mem[ rp ];
|
||||
|
||||
always @(posedge clk)
|
||||
if(we) mem[ wp ] <= din;
|
||||
|
||||
assign empty = (wp == rp) & !gb;
|
||||
assign full = (wp == rp) & gb;
|
||||
|
||||
always @(posedge clk)
|
||||
if(!rst) gb <= 1'b0;
|
||||
else
|
||||
if(clr) gb <= 1'b0;
|
||||
else
|
||||
if((wp_p1 == rp) & we) gb <= 1'b1;
|
||||
else
|
||||
if(re) gb <= 1'b0;
|
||||
|
||||
endmodule
|
98
resources/soc/rtl/TOP/config.h
Normal file
98
resources/soc/rtl/TOP/config.h
Normal file
@ -0,0 +1,98 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
`define Lconfbus 10
|
||||
`define Lconfret 9
|
||||
`define Lconfbusreg 64
|
||||
`define Lconfbusaddr 16
|
||||
|
||||
`define ORDER_REG_ADDR 16'h1160
|
||||
|
||||
`define Lawcmd 4
|
||||
`define Lawdirqid 4
|
||||
`define Lawstate 2
|
||||
`define Lawscseti 2
|
||||
`define Lawid 4
|
||||
`define Lawaddr 32
|
||||
`define Lawlen 4
|
||||
`define Lawsize 3
|
||||
`define Lawburst 2
|
||||
`define Lawlock 2
|
||||
`define Lawcache 4
|
||||
`define Lawprot 3
|
||||
`define Lawvalid 1
|
||||
`define Lawready 1
|
||||
`define Lwid 4
|
||||
`define Lwdata 32
|
||||
`define Lwstrb 4
|
||||
`define Lwlast 1
|
||||
`define Lwvalid 1
|
||||
`define Lwready 1
|
||||
`define Lbid 4
|
||||
`define Lbresp 2
|
||||
`define Lbvalid 1
|
||||
`define Lbready 1
|
||||
`define Larcmd 4
|
||||
`define Larcpuno 10
|
||||
`define Larid 4
|
||||
`define Laraddr 32
|
||||
`define Larlen 4
|
||||
`define Larsize 3
|
||||
`define Larburst 2
|
||||
`define Larlock 2
|
||||
`define Larcache 4
|
||||
`define Larprot 3
|
||||
`define Larvalid 1
|
||||
`define Larready 1
|
||||
`define Lrstate 2
|
||||
`define Lrscseti 2
|
||||
`define Lrid 4
|
||||
`define Lrdata 32
|
||||
`define Lrresp 2
|
||||
`define Lrlast 1
|
||||
`define Lrvalid 1
|
||||
`define Lrready 1
|
||||
`define Lrrequest 1
|
||||
/*************************/
|
||||
`define LID 4
|
||||
`define LADDR 32
|
||||
`define LLEN 4
|
||||
`define LSIZE 3
|
||||
`define LDATA 32
|
||||
`define LSTRB 4
|
||||
`define LBURST 2
|
||||
`define LLOCK 2
|
||||
`define LCACHE 4
|
||||
`define LPROT 3
|
||||
`define LRESP 2
|
||||
/************************************/
|
1504
resources/soc/rtl/TOP/soc_up_top.v
Normal file
1504
resources/soc/rtl/TOP/soc_up_top.v
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,7 @@
|
||||
|
||||
1.龙芯开源处理器GS232源码是可以免费获得的。
|
||||
|
||||
2.但是为了更好地对GS232源码进行版本维护和流通追溯,此处无法直接提供源码。
|
||||
|
||||
3.高校老师可在龙芯官网上通过开源申请获得GS232源码。
|
||||
|
82
resources/soc/simu/run/run_func/lib.list
Normal file
82
resources/soc/simu/run/run_func/lib.list
Normal file
@ -0,0 +1,82 @@
|
||||
../../lib/sram_simu.v
|
||||
../../lib/func_emul/cell_emul.v
|
||||
../../lib/glbl.v
|
||||
../../lib/AND2B1L.v
|
||||
../../lib/BUFG.v
|
||||
../../lib/BUFGCE.v
|
||||
../../lib/BUFGMUX.v
|
||||
../../lib/BUFPLL_MCB.v
|
||||
../../lib/DCM_SP.v
|
||||
../../lib/FDRE.v
|
||||
../../lib/FDSE.v
|
||||
../../lib/IBUFG.v
|
||||
../../lib/INV.v
|
||||
../../lib/IOBUF.v
|
||||
../../lib/IOBUFDS.v
|
||||
../../lib/IODRP2.v
|
||||
../../lib/IODRP2_MCB.v
|
||||
../../lib/LUT4.v
|
||||
../../lib/LUT6.v
|
||||
../../lib/LUT6_2.v
|
||||
../../lib/MCB.v
|
||||
../../lib/MUXCY.v
|
||||
../../lib/OBUFDS.v
|
||||
../../lib/OBUFT.v
|
||||
../../lib/OBUFTDS.v
|
||||
../../lib/OR2L.v
|
||||
../../lib/OSERDES2.v
|
||||
../../lib/PLL_ADV.v
|
||||
../../lib/PULLDOWN.v
|
||||
../../lib/PULLUP.v
|
||||
../../lib/SRLC32E.v
|
||||
../../lib/XORCY.v
|
||||
../../lib/BLK_MEM_GEN_V6_2.v
|
||||
../../lib/BLK_MEM_GEN_V6_1.v
|
||||
../../lib/mcb_001.vp
|
||||
../../lib/mcb_002.vp
|
||||
../../lib/mcb_003.vp
|
||||
../../lib/mcb_004.vp
|
||||
../../lib/mcb_005.vp
|
||||
../../lib/mcb_006.vp
|
||||
../../lib/mcb_007.vp
|
||||
../../lib/mcb_008.vp
|
||||
../../lib/mcb_009.vp
|
||||
../../lib/mcb_010.vp
|
||||
../../lib/mcb_011.vp
|
||||
../../lib/mcb_012.vp
|
||||
../../lib/mcb_013.vp
|
||||
../../lib/mcb_014.vp
|
||||
../../lib/mcb_015.vp
|
||||
../../lib/mcb_016.vp
|
||||
../../lib/mcb_017.vp
|
||||
../../lib/mcb_018.vp
|
||||
../../lib/mcb_019.vp
|
||||
../../lib/mcb_020.vp
|
||||
../../lib/mcb_021.vp
|
||||
../../lib/mcb_022.vp
|
||||
../../lib/mcb_023.vp
|
||||
../../lib/mcb_024.vp
|
||||
../../lib/mcb_025.vp
|
||||
../../lib/mcb_026.vp
|
||||
../../lib/mcb_027.vp
|
||||
../../lib/mcb_028.vp
|
||||
../../lib/mcb_029.vp
|
||||
../../lib/mcb_030.vp
|
||||
../../lib/mcb_031.vp
|
||||
../../lib/mcb_032.vp
|
||||
../../lib/mcb_033.vp
|
||||
../../lib/mcb_034.vp
|
||||
../../lib/mcb_035.vp
|
||||
../../lib/mcb_036.vp
|
||||
../../lib/mcb_037.vp
|
||||
../../lib/mcb_038.vp
|
||||
../../lib/mcb_039.vp
|
||||
../../lib/mcb_040.vp
|
||||
../../lib/mcb_041.vp
|
||||
../../lib/mcb_042.vp
|
||||
../../lib/mcb_043.vp
|
||||
../../lib/mcb_044.vp
|
||||
../../lib/mcb_045.vp
|
||||
../../lib/mcb_046.vp
|
||||
../../lib/mcb_047.vp
|
||||
|
3
resources/soc/simu/run/run_func/ncompile
Normal file
3
resources/soc/simu/run/run_func/ncompile
Normal file
@ -0,0 +1,3 @@
|
||||
#!/bin/bash
|
||||
|
||||
ncverilog -f run.f
|
117
resources/soc/simu/run/run_func/rtl.list
Normal file
117
resources/soc/simu/run/run_func/rtl.list
Normal file
@ -0,0 +1,117 @@
|
||||
../../../rtl/TOP/archlab_sopc_top.v
|
||||
|
||||
../../../rtl/CPU/axi_interface.v
|
||||
../../../rtl/CPU/godson_addr_module.v
|
||||
../../../rtl/CPU/godson_alu_module.v
|
||||
../../../rtl/CPU/godson_bus_module.v
|
||||
../../../rtl/CPU/godson_cpu_core.v
|
||||
../../../rtl/CPU/godson_cpu_mid.v
|
||||
../../../rtl/CPU/godson_dcache_module.v
|
||||
../../../rtl/CPU/godson_dcr_module.v
|
||||
../../../rtl/CPU/godson_decoder_module.v
|
||||
../../../rtl/CPU/godson_dtlb_module.v
|
||||
../../../rtl/CPU/godson_ejtag_tap_module.v
|
||||
../../../rtl/CPU/godson_fetch_module.v
|
||||
../../../rtl/CPU/godson_gr_module.v
|
||||
../../../rtl/CPU/godson_hb_module.v
|
||||
../../../rtl/CPU/godson_icache_module.v
|
||||
../../../rtl/CPU/godson_itlb_module.v
|
||||
../../../rtl/CPU/godson_memqueue_module.v
|
||||
../../../rtl/CPU/godson_queue_module.v
|
||||
../../../rtl/CPU/godson_ram_bist.v
|
||||
../../../rtl/CPU/godson_rs_module.v
|
||||
../../../rtl/CPU/godson_tap_buffer_module.v
|
||||
../../../rtl/CPU/tools.v
|
||||
|
||||
../../../rtl/CPU/sram/sram_128x22.v
|
||||
../../../rtl/CPU/sram/sram_128x32.v
|
||||
../../../rtl/CPU/sram/sram_128x64.v
|
||||
../../../rtl/CPU/sram/sram_32x52bit.v
|
||||
|
||||
../../../rtl/AMBA/axi_mux.v
|
||||
../../../rtl/AMBA/axi2apb.v
|
||||
|
||||
../../../rtl/MIG/memc_wrapper.v
|
||||
../../../rtl/MIG/ddr3_3port.v
|
||||
../../../rtl/MIG/infrastructure.v
|
||||
../../../rtl/MIG/axi/a_upsizer.v
|
||||
../../../rtl/MIG/axi/axi_mcb.v
|
||||
../../../rtl/MIG/axi/axi_mcb_ar_channel.v
|
||||
../../../rtl/MIG/axi/axi_mcb_aw_channel.v
|
||||
../../../rtl/MIG/axi/axi_mcb_b_channel.v
|
||||
../../../rtl/MIG/axi/axi_mcb_cmd_arbiter.v
|
||||
../../../rtl/MIG/axi/axi_mcb_cmd_fsm.v
|
||||
../../../rtl/MIG/axi/axi_mcb_cmd_translator.v
|
||||
../../../rtl/MIG/axi/axi_mcb_incr_cmd.v
|
||||
../../../rtl/MIG/axi/axi_mcb_r_channel.v
|
||||
../../../rtl/MIG/axi/axi_mcb_simple_fifo.v
|
||||
../../../rtl/MIG/axi/axi_mcb_w_channel.v
|
||||
../../../rtl/MIG/axi/axi_mcb_wrap_cmd.v
|
||||
../../../rtl/MIG/axi/axi_register_slice.v
|
||||
../../../rtl/MIG/axi/axi_upsizer.v
|
||||
../../../rtl/MIG/axi/axic_register_slice.v
|
||||
../../../rtl/MIG/axi/carry.v
|
||||
../../../rtl/MIG/axi/carry_and.v
|
||||
../../../rtl/MIG/axi/carry_latch_and.v
|
||||
../../../rtl/MIG/axi/carry_latch_or.v
|
||||
../../../rtl/MIG/axi/carry_or.v
|
||||
../../../rtl/MIG/axi/command_fifo.v
|
||||
../../../rtl/MIG/axi/comparator.v
|
||||
../../../rtl/MIG/axi/comparator_mask.v
|
||||
../../../rtl/MIG/axi/comparator_mask_static.v
|
||||
../../../rtl/MIG/axi/comparator_sel.v
|
||||
../../../rtl/MIG/axi/comparator_sel_mask.v
|
||||
../../../rtl/MIG/axi/comparator_sel_mask_static.v
|
||||
../../../rtl/MIG/axi/comparator_sel_static.v
|
||||
../../../rtl/MIG/axi/comparator_static.v
|
||||
../../../rtl/MIG/axi/mcb_ui_top_synch.v
|
||||
../../../rtl/MIG/axi/mux_enc.v
|
||||
../../../rtl/MIG/axi/r_upsizer.v
|
||||
../../../rtl/MIG/axi/w_upsizer.v
|
||||
../../../rtl/MIG/mcb_controller/iodrp_controller.v
|
||||
../../../rtl/MIG/mcb_controller/iodrp_mcb_controller.v
|
||||
../../../rtl/MIG/mcb_controller/mcb_raw_wrapper.v
|
||||
../../../rtl/MIG/mcb_controller/mcb_soft_calibration.v
|
||||
../../../rtl/MIG/mcb_controller/mcb_soft_calibration_top.v
|
||||
../../../rtl/MIG/mcb_controller/mcb_ui_top.v
|
||||
|
||||
../../../rtl/APB_DEV/URT/raminfr.v
|
||||
../../../rtl/APB_DEV/URT/uart_receiver.v
|
||||
../../../rtl/APB_DEV/URT/uart_regs.v
|
||||
../../../rtl/APB_DEV/URT/uart_rfifo.v
|
||||
../../../rtl/APB_DEV/URT/uart_sync_flops.v
|
||||
../../../rtl/APB_DEV/URT/uart_tfifo.v
|
||||
../../../rtl/APB_DEV/URT/uart_top.v
|
||||
../../../rtl/APB_DEV/URT/uart_transmitter.v
|
||||
|
||||
../../../rtl/CONFREG/confreg.v
|
||||
../../../rtl/SPI/godson_sbridge_spi.v
|
||||
|
||||
../../../rtl/MAC/utility.v
|
||||
../../../rtl/MAC/ethernet_top.v
|
||||
../../../rtl/MAC/mac_top.v
|
||||
../../../rtl/MAC/mac_axi.v
|
||||
../../../rtl/MAC/mac.v
|
||||
../../../rtl/MAC/csr.v
|
||||
../../../rtl/MAC/rc.v
|
||||
../../../rtl/MAC/rfifo.v
|
||||
../../../rtl/MAC/rlsm.v
|
||||
../../../rtl/MAC/tc.v
|
||||
../../../rtl/MAC/bd.v
|
||||
../../../rtl/MAC/dma.v
|
||||
../../../rtl/MAC/rstc.v
|
||||
../../../rtl/MAC/tfifo.v
|
||||
../../../rtl/MAC/tlsm.v
|
||||
../../../rtl/MAC/mac2axi.v
|
||||
../../../rtl/MAC/maccsr2axi.v
|
||||
../../../rtl/MAC/macdata2axi.v
|
||||
../../../rtl/MAC/cam.v
|
||||
../../../rtl/MAC/dpram_512x32.v
|
||||
|
||||
../../../rtl/DMA/dma.v
|
||||
|
||||
../../../rtl/APB_DEV/apb_dev_top.v
|
||||
../../../rtl/APB_DEV/apb_mux2.v
|
||||
../../../rtl/APB_DEV/nand_module.v
|
||||
|
||||
../../../rtl/APB_DEV/NAND/nand.v
|
28
resources/soc/simu/run/run_func/run.f
Normal file
28
resources/soc/simu/run/run_func/run.f
Normal file
@ -0,0 +1,28 @@
|
||||
+incdir+../../../rtl/TOP
|
||||
+incdir+../../../rtl/CPU
|
||||
+incdir+../../../rtl/APB_DEV
|
||||
+incdir+../../../rtl/APB_DEV/NAND
|
||||
+incdir+../../../rtl/APB_DEV/URT
|
||||
+incdir+../../../rtl/SPI
|
||||
+incdir+../../../rtl/MIG
|
||||
+incdir+../../../rtl/MAC
|
||||
+incdir+../../../rtl/AMBA
|
||||
+incdir+../../../rtl/CONFREG
|
||||
+incdir+../../testbench
|
||||
+incdir+../../testbench/vmac
|
||||
+nclog_ncsim+ncsim.log
|
||||
+access+rw
|
||||
-sv
|
||||
-64bit
|
||||
-nowarn MRSTAR
|
||||
+pathpulse
|
||||
+profile
|
||||
+define+x1Gb
|
||||
+define+sg15E
|
||||
+define+x16
|
||||
+define+VIRTUAL_MAC
|
||||
+define+_DUMPDUMP
|
||||
-f sys.list
|
||||
-f rtl.list
|
||||
-f lib.list
|
||||
|
11
resources/soc/simu/run/run_func/sys.list
Normal file
11
resources/soc/simu/run/run_func/sys.list
Normal file
@ -0,0 +1,11 @@
|
||||
../../testbench/godson_system.v
|
||||
../../testbench/MX25L6405D.v
|
||||
../../testbench/uart_dev.v
|
||||
../../testbench/ejtag_virtual_host.v
|
||||
../../testbench/ddr3_model_c1.v
|
||||
../../testbench/vmac/virtual_mac.v
|
||||
../../testbench/vmac/mac_top.v
|
||||
../../testbench/vmac/mac_ram.v
|
||||
../../testbench/nand_sim.v
|
||||
|
||||
|
48
resources/soc/simu/soft/func/Makefile
Normal file
48
resources/soc/simu/soft/func/Makefile
Normal file
@ -0,0 +1,48 @@
|
||||
TOPDIR = $(shell pwd)
|
||||
|
||||
CROSS_COMPILE = mipsel-linux-
|
||||
DEBUG = -g
|
||||
FLAGS =
|
||||
|
||||
CC = $(CROSS_COMPILE)gcc
|
||||
LD = $(CROSS_COMPILE)ld
|
||||
OBJCOPY = $(CROSS_COMPILE)objcopy
|
||||
OBJDUMP = $(CROSS_COMPILE)objdump
|
||||
AR = $(CROSS_COMPILE)ar
|
||||
|
||||
export TOPDIR AR CC DEBUG FLAGS
|
||||
|
||||
all:test.bin convert
|
||||
./convert
|
||||
$(OBJDUMP) -ald test >test.s
|
||||
|
||||
libtinyc.a:
|
||||
make -C lib $(TOPDIR)/$@
|
||||
|
||||
start.o:start.S include/ls1d.h include/asm/mipsregs.h include/asm/regdef.h include/asm/ns16550.h
|
||||
$(CC) $(DEBUG) $(FLAGS) -mips32 -EL -c -o $@ $<
|
||||
|
||||
nand.o:nand_test.S include/ls1d.h include/asm/mipsregs.h include/asm/regdef.h include/asm/ns16550.h
|
||||
$(CC) $(DEBUG) $(FLAGS) -mips32 -EL -c -o $@ $<
|
||||
|
||||
main.o:main.c include/*.h
|
||||
$(CC) $(DEBUG) $(FLAGS) -EL -c -o $@ $<
|
||||
|
||||
%.o:source/%.c include/%.h include/ls1d.h
|
||||
$(CC) $(DEBUG) $(FLAGS) -EL -c -o $@ $<
|
||||
|
||||
#test_cycle.o myprintf.o
|
||||
OBJ1 = Interrupt.o lcd.o SystemInit.o Calendar.o key.o battery.o common.o temp_flow.o Infrare.o frame.o MonthData.o isp.o adc.o cmdline.o flash.o dg_rs232.o
|
||||
|
||||
test:start.o nand.o main.o $(OBJ1) libtinyc.a
|
||||
$(LD) -T test.lds -Ttext 0xBFC00000 -Map test.map start.o nand.o main.o $(OBJ1) -o $@ -L . -ltinyc
|
||||
#rm -f *.o
|
||||
|
||||
test.bin:test
|
||||
$(OBJCOPY) --gap-fill=0xff -O binary $< $@
|
||||
|
||||
clean:
|
||||
rm -f *.o *.a test test.bin test.map test.s convert flash.vlog
|
||||
make -C lib clean
|
||||
convert:convert.c
|
||||
gcc -o convert convert.c
|
179
resources/soc/simu/soft/func/config.h
Normal file
179
resources/soc/simu/soft/func/config.h
Normal file
@ -0,0 +1,179 @@
|
||||
#include "include/ls1d.h"
|
||||
#include "include/SystemInit.h"
|
||||
#include "include/Calendar.h"
|
||||
#include "include/lcd.h"
|
||||
#include "include/key.h"
|
||||
#include "include/common.h"
|
||||
#include "include/temp_flow.h"
|
||||
#include "include/MonthData.h"
|
||||
#include "include/Infrare.h"
|
||||
#include "include/frame.h"
|
||||
#include "include/battery.h"
|
||||
#include "include/Interrupt.h"
|
||||
#include "include/xmodem.h"
|
||||
#include "include/isp.h"
|
||||
#include "include/cmdline.h"
|
||||
//#include "myprintf.h"
|
||||
//#include "test_cycle.h"
|
||||
|
||||
//#include <stdio.h>
|
||||
//#include <math.h>
|
||||
|
||||
#define DisableWatchDog() PMU_Command &= 0xdfffffff ;
|
||||
#define EnableWatchDog() PMU_Command |= 0x20000000 ;
|
||||
#define FeedWatchDog() PMU_CommandW = 0x40000000 ;
|
||||
|
||||
#define NUM 10
|
||||
extern _u32 wait[NUM];
|
||||
extern _u32 main_flag;
|
||||
extern _u32 work_mode;
|
||||
extern _u32 *PMU;
|
||||
extern _u32 *Sonar;
|
||||
extern _u32 *Thsens;
|
||||
|
||||
/********************************Defined by user*******************************************************************************************************************/
|
||||
#define IR_PWR_ON PMU_GPIO_O |= (1 << 3) //Infrare receiver power on
|
||||
#define IR_PWR_OFF PMU_GPIO_O &=~(1 << 3) //Infrare receiver power off
|
||||
#define KEY_OFF 0x10 //when the key is off, the key_bit of gpio_in will be high
|
||||
|
||||
#define STDC_CALIBRATE 200 //default value
|
||||
#define COUNT_MASK 0xffffff //refer to count reg, PMU
|
||||
#define COUNT_COMPARE 0X1000000
|
||||
|
||||
#define LCD_MULTIPLE 100000 //every varible printed in lcd will plus LCD_MULTIPLE, thus the real value should divide LCD_MULTIPLE
|
||||
#define LCD_LENGTH 10 //the lcd buf will divide into LCD_LENGTH
|
||||
#define LCD_NUM_LENGTH 8 //the numbers of number that the lcd can print
|
||||
|
||||
#define CJT188_DI_SEQ 1 //it will change the sequence of DI0 and DI1
|
||||
#define CJT188_DEF_READ 0x0e
|
||||
#define CJT188_DEF_WRITE 0x1e
|
||||
|
||||
#define UART1_INT 0 //enable uart1_rx_int when a key comes, then disable it when received a right frame
|
||||
|
||||
|
||||
/***********************************xmodem Option*****************************************************************************************************************/
|
||||
#define FLASH_BLOCK_SIZE 256
|
||||
#define FLASH_ERASE_START 0xbfc00000
|
||||
#define FLASH_ERASE_END 0xbfc0efff //60kB
|
||||
|
||||
/********************************Info flash Option****************************************************************************************************************/
|
||||
#define INFO_FLASH_START 0xbfc0fe00
|
||||
#define AUTO_SAVE_ADDR 0xbfc0fd00
|
||||
|
||||
/********************************Pipe Option**********************************************************************************************************************/
|
||||
#define SOUND_PATH 0.072f //m
|
||||
#define COS_RESULT 1
|
||||
#define K_COEFFICIENT 0.5f
|
||||
#define DIAMETER 0.020f //m
|
||||
#define PI 3.1415926f
|
||||
#define CONST PI/4
|
||||
|
||||
/********************************Compile Option**********************************************************************************************************************/
|
||||
#define ISP 1 //ISP module
|
||||
#define LS1D_FPGA 1 //Choose code for fpga_board or chip_flash.
|
||||
|
||||
#define AD_MODULE 0
|
||||
#define ADC_MODULE 0
|
||||
#define LCD_MODULE 0
|
||||
#define TDC_TEMP_MODULE 0
|
||||
#define TDC_FLOW_MODULE 0
|
||||
#define MONTHDATA_MODULE 0
|
||||
#define KEY_MODULE 0
|
||||
#define MBUS_MODULE 0
|
||||
#define INFRARE_MODULE 0
|
||||
#define CALENDAR_MODULE 0 //need TIMER_MODULE and LCD_MODULE
|
||||
#define FRAME_MODULE 0
|
||||
#define TIMER_MODULE 0
|
||||
|
||||
|
||||
/********************************Debug Option/Print*******************************************************************************************************************/
|
||||
#define PRINT 1 //only print necessory information
|
||||
#if PRINT
|
||||
#define AD_TEST 0 //need TIMER_MODULE for 2s delay
|
||||
#define ADC_TEST 0
|
||||
#define LCD_TEST 0 //need TIMER_MODULE for 1s delay
|
||||
#define TEMP_TEST 0
|
||||
#define FLOW_TEST 0
|
||||
#define MONTHDATA_TEST 0 //use lcd A3
|
||||
#define KEY_TEST 0
|
||||
#define MBUS_TEST 0
|
||||
#define INFRARE_TEST 0
|
||||
#define CALENDAR_TEST 0
|
||||
#define FRAME_TEST 0
|
||||
#define RES_TEST 0
|
||||
#define TIMER_TEST 0
|
||||
#endif
|
||||
|
||||
#if PRINT
|
||||
#define DEBUG 1 //print information in detail
|
||||
#endif
|
||||
|
||||
#if DEBUG
|
||||
#define BUG 1
|
||||
#define debug(fmt,args...) printf(fmt ,##args);
|
||||
#define debugX(level,fmt,args...) if(DEBUG>=level) printf(fmt,##args);
|
||||
#else
|
||||
#define BUG 0
|
||||
#define debug(fmt,args...)
|
||||
#define debugX(level,fmt,args...)
|
||||
#endif
|
||||
|
||||
#if BUG
|
||||
#define BUG() printf("BUG: failure at %s:%d in %s()!\n", __FILE__, __LINE__, __FUNCTION__);
|
||||
#define BUG_ON(condition) if(condition) BUG();
|
||||
#endif /* BUG */
|
||||
|
||||
|
||||
/*************************************main_flag***********************************************************************************************************************/
|
||||
//unsigned char main_flag0;
|
||||
#define test_bit 0x80 //低电压检测
|
||||
#define temp_bit 0x40
|
||||
#define flow_bit 0x20
|
||||
#define month_bit 0x10
|
||||
#define key_bit 0x8
|
||||
#define lcd_bit 0x4
|
||||
#define mbus_bit 0x2
|
||||
#define infrare_bit 0x1
|
||||
//unsigned char main_flag1;
|
||||
#define state_bit 0x8000 //gp21的状态, '0'为正常,'1'为异常
|
||||
#define lowV1_bit 0x4000 //低电压检测1,每隔2秒
|
||||
#define lowV2_bit 0x2000 //低电压检测2,每月7、14、21、28日凌晨3点置'1'
|
||||
#define time_bit 0x1000 //软时钟
|
||||
#define long_key 0x800 //长按键
|
||||
#define month_flag 0x400 //数据月结时间是否为默认时间,默认时间为每月月底,置'1'
|
||||
#define A3_delay 0x200 //A3菜单内3秒自动切换
|
||||
#define wait_halfsec 0x100 //等待0.5秒
|
||||
//unsigned char main_flag2;
|
||||
#define wait_3sec 0x800000 //间隔3秒
|
||||
#define wait_8sec 0x400000 //间隔8秒
|
||||
#define wait_9sec 0x200000 //间隔9秒
|
||||
#define wait_10sec 0x100000 //间隔10秒
|
||||
#define wait_1min 0x80000 //间隔1分钟
|
||||
#define wait_2min 0x40000 //间隔2分钟
|
||||
#define wait_16min 0x20000 //间隔16分钟
|
||||
#define wait_2hour 0x10000 //间隔2小时
|
||||
//unsigned char main_flag3;
|
||||
#define rx_bit 0x80000000 //usart收到一个完整的帧
|
||||
#define infrare_flag 0x40000000 //红外状态,'0'关闭'1'打开
|
||||
#define lowV_flag 0x20000000 //低电压状态为'1'
|
||||
#define wait_oneday 0x10000000 //低电压检测,等待一天
|
||||
#define power_on 0x8000000 //上电检测
|
||||
#define res_valid 0x4000000 //RES_VALID
|
||||
#define per_timer 0x2000000
|
||||
|
||||
/********************************************************************************************************************************************************************/
|
||||
|
||||
/*************************************work_mode***********************************************************************************************************************/
|
||||
#define MODE_0 0
|
||||
#define MODE_1 1
|
||||
#define MODE_2 2
|
||||
#define MODE_3 3
|
||||
#define MODE_4 4
|
||||
#define MODE_5 5
|
||||
#define MODE_6 6
|
||||
#define MODE_7 7
|
||||
#define MODE_8 8
|
||||
#define MODE_9 9
|
||||
|
||||
/********************************************************************************************************************************************************************/
|
||||
|
29
resources/soc/simu/soft/func/convert.c
Normal file
29
resources/soc/simu/soft/func/convert.c
Normal file
@ -0,0 +1,29 @@
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
int main(void)
|
||||
{
|
||||
FILE *in;
|
||||
FILE *out;
|
||||
FILE *out0, *out1, *out2, *out3;
|
||||
FILE *out4, *out5, *out6, *out7;
|
||||
|
||||
int i,j,k;
|
||||
unsigned char mem[32];
|
||||
|
||||
in = fopen("test.bin", "rb");
|
||||
out = fopen("flash.vlog", "w");
|
||||
|
||||
fprintf(out, " @00\n");
|
||||
while(!feof(in)) {
|
||||
if(fread(mem,1,4,in)!=4) {
|
||||
fprintf(out, " %02x %02x %02x %02x\n", mem[0], mem[1], mem[2], mem[3]);
|
||||
break;
|
||||
}
|
||||
fprintf(out, " %02x %02x %02x %02x\n", mem[0], mem[1], mem[2],mem[3]);
|
||||
}
|
||||
fclose(in);
|
||||
fclose(out);
|
||||
|
||||
return 0;
|
||||
}
|
12
resources/soc/simu/soft/func/include/Calendar.h
Normal file
12
resources/soc/simu/soft/func/include/Calendar.h
Normal file
@ -0,0 +1,12 @@
|
||||
struct Date_Time{
|
||||
_u32 Year;
|
||||
_u32 Month;
|
||||
_u32 Day;
|
||||
_u32 Hour;
|
||||
_u32 Minute;
|
||||
_u32 Second;
|
||||
};
|
||||
|
||||
void calendar(struct Date_Time *Date_and_Time);
|
||||
//void calendar(struct Date_Time *Date_and_Time, _u32 lcdmode);
|
||||
void DateInit(struct Date_Time *Date_and_Time);
|
1
resources/soc/simu/soft/func/include/Infrare.h
Normal file
1
resources/soc/simu/soft/func/include/Infrare.h
Normal file
@ -0,0 +1 @@
|
||||
void Infrare(void);
|
9
resources/soc/simu/soft/func/include/Interrupt.h
Normal file
9
resources/soc/simu/soft/func/include/Interrupt.h
Normal file
@ -0,0 +1,9 @@
|
||||
void TIMER_INT();
|
||||
void KEY_INT();
|
||||
void BAT_FAIL();
|
||||
void RES_VALID();
|
||||
void INTC();
|
||||
void Ring();
|
||||
void Per_timer(struct Data *Lcd_data);
|
||||
|
||||
void Interrupt_Init();
|
23
resources/soc/simu/soft/func/include/MonthData.h
Normal file
23
resources/soc/simu/soft/func/include/MonthData.h
Normal file
@ -0,0 +1,23 @@
|
||||
void MonthData(struct Date_Time *Date_and_Time, struct Data *Lcd_data);
|
||||
void Flash_Read_Info();
|
||||
void Flash_Write_Test();
|
||||
extern _u32 Last_month_num;
|
||||
|
||||
#define CHRWRITE 0
|
||||
#define BLKWRITE 1
|
||||
struct Record_0{
|
||||
_u32 Date; /*保存年月信息,Date = Year*1000 + Month*10, 例如2011.10,则Date = 20110100 */
|
||||
_u32 TotalHeat; //xxxxxx.xx, plus 100
|
||||
_u32 TotalFlow; //xxxxxx.xx, plus 100
|
||||
};
|
||||
|
||||
struct Record_1{
|
||||
_u32 Date; /*保存年月日信息,Date = Year*10000 + Month*100 + Day, 例如2011.10.12,则Date = 20111012 */
|
||||
_u32 Time; /*保存时分信息,Time = Hour*100 + Minute, 例如9:30,则Time = 930 */
|
||||
_fp32 TotalHeat;
|
||||
_fp32 TotalFlow;
|
||||
_u32 WorkTime;
|
||||
_u32 ErrTime;
|
||||
};
|
||||
extern struct Record_1 Latest_Record;
|
||||
|
4
resources/soc/simu/soft/func/include/SystemInit.h
Normal file
4
resources/soc/simu/soft/func/include/SystemInit.h
Normal file
@ -0,0 +1,4 @@
|
||||
void Uart0_Init();
|
||||
void SystemInit();
|
||||
void PowerDetec();
|
||||
//void ReLoad();
|
2
resources/soc/simu/soft/func/include/adc.h
Normal file
2
resources/soc/simu/soft/func/include/adc.h
Normal file
@ -0,0 +1,2 @@
|
||||
|
||||
float BatteryMeasure(void)
|
287
resources/soc/simu/soft/func/include/asm/interrupt.h
Normal file
287
resources/soc/simu/soft/func/include/asm/interrupt.h
Normal file
@ -0,0 +1,287 @@
|
||||
#if 1 /*It's not a good method. Don't use it!*/
|
||||
#define SAVE_REGS \
|
||||
li k1, SRAM_BASEADDR+0x1000; \
|
||||
sw $0, 0x0(k1); \
|
||||
sw $1, 0x4(k1); \
|
||||
sw $2, 0x8(k1); \
|
||||
sw $3, 0xc(k1); \
|
||||
sw $4, 0x10(k1); \
|
||||
sw $5, 0x14(k1); \
|
||||
sw $6, 0x18(k1); \
|
||||
sw $7, 0x1c(k1); \
|
||||
sw $8, 0x20(k1); \
|
||||
sw $9, 0x24(k1); \
|
||||
sw $10, 0x28(k1); \
|
||||
sw $11, 0x2c(k1); \
|
||||
sw $12, 0x30(k1); \
|
||||
sw $13, 0x34(k1); \
|
||||
sw $14, 0x38(k1); \
|
||||
sw $15, 0x3c(k1); \
|
||||
sw $16, 0x40(k1); \
|
||||
sw $17, 0x44(k1); \
|
||||
sw $18, 0x48(k1); \
|
||||
sw $19, 0x4c(k1); \
|
||||
sw $20, 0x50(k1); \
|
||||
sw $21, 0x54(k1); \
|
||||
sw $22, 0x58(k1); \
|
||||
sw $23, 0x5c(k1); \
|
||||
sw $24, 0x60(k1); \
|
||||
sw $25, 0x64(k1); \
|
||||
sw $26, 0x68(k1); \
|
||||
sw $27, 0x6c(k1); \
|
||||
sw $28, 0x70(k1); \
|
||||
sw $29, 0x74(k1); \
|
||||
sw $30, 0x78(k1);
|
||||
//sw $31, 0x7c(k1)
|
||||
|
||||
#define LOAD_REGS \
|
||||
li k1, SRAM_BASEADDR+0x1000; \
|
||||
lw $0, 0x0(k1); \
|
||||
lw $1, 0x4(k1); \
|
||||
lw $2, 0x8(k1); \
|
||||
lw $3, 0xc(k1); \
|
||||
lw $4, 0x10(k1); \
|
||||
lw $5, 0x14(k1); \
|
||||
lw $6, 0x18(k1); \
|
||||
lw $7, 0x1c(k1); \
|
||||
lw $8, 0x20(k1); \
|
||||
lw $9, 0x24(k1); \
|
||||
lw $10, 0x28(k1); \
|
||||
lw $11, 0x2c(k1); \
|
||||
lw $12, 0x30(k1); \
|
||||
lw $13, 0x34(k1); \
|
||||
lw $14, 0x38(k1); \
|
||||
lw $15, 0x3c(k1); \
|
||||
lw $16, 0x40(k1); \
|
||||
lw $17, 0x44(k1); \
|
||||
lw $18, 0x48(k1); \
|
||||
lw $19, 0x4c(k1); \
|
||||
lw $20, 0x50(k1); \
|
||||
lw $21, 0x54(k1); \
|
||||
lw $22, 0x58(k1); \
|
||||
lw $23, 0x5c(k1); \
|
||||
lw $24, 0x60(k1); \
|
||||
lw $25, 0x64(k1); \
|
||||
lw $26, 0x68(k1); \
|
||||
lw $27, 0x6c(k1); \
|
||||
lw $28, 0x70(k1); \
|
||||
lw $29, 0x74(k1); \
|
||||
lw $30, 0x78(k1); \
|
||||
//lw $26, 0x7c(k1); \
|
||||
//sw $26, 0x10($30);
|
||||
//lw $31, 0x7c(k1)
|
||||
#endif
|
||||
|
||||
/***********************************method 1*************************************/
|
||||
#if 0
|
||||
#define SAVE_ALL \
|
||||
addi sp, -4; \
|
||||
sw $0, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $1, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $2, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $3, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $4, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $5, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $6, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $7, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $8, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $9, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $10, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $11, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $12, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $13, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $14, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $15, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $16, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $17, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $18, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $19, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $20, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $21, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $22, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $23, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $24, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $25, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $26, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $27, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $28, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $29, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $30, 0x0(sp); \
|
||||
addi sp, -4; \
|
||||
sw $31, 0x0(sp); \
|
||||
addi sp, -4
|
||||
|
||||
|
||||
#define LOAD_ALL \
|
||||
addi sp, 4; \
|
||||
lw $31, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $30, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $29, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $28, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $27, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $26, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $25, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $24, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $23, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $22, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $21, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $20, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $19, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $18, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $17, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $16, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $15, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $14, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $13, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $12, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $11, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $10, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $9, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $8, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $7, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $6, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $5, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $4, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $3, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $2, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $1, 0x0(sp); \
|
||||
addi sp, 4; \
|
||||
lw $0, 0x0(sp); \
|
||||
addi sp, 4
|
||||
#endif
|
||||
/****************************************************************************/
|
||||
|
||||
/*************************************method 2***********************************/
|
||||
#if 1
|
||||
#define SAVE_ALL \
|
||||
addi sp, -132; \
|
||||
sw $0, 0x80(sp); \
|
||||
sw $1, 0x7c(sp); \
|
||||
sw $2, 0x78(sp); \
|
||||
sw $3, 0x74(sp); \
|
||||
sw $4, 0x70(sp); \
|
||||
sw $5, 0x6c(sp); \
|
||||
sw $6, 0x68(sp); \
|
||||
sw $7, 0x64(sp); \
|
||||
sw $8, 0x60(sp); \
|
||||
sw $9, 0x5c(sp); \
|
||||
sw $10, 0x58(sp); \
|
||||
sw $11, 0x54(sp); \
|
||||
sw $12, 0x50(sp); \
|
||||
sw $13, 0x4c(sp); \
|
||||
sw $14, 0x48(sp); \
|
||||
sw $15, 0x44(sp); \
|
||||
sw $16, 0x40(sp); \
|
||||
sw $17, 0x3c(sp); \
|
||||
sw $18, 0x38(sp); \
|
||||
sw $19, 0x34(sp); \
|
||||
sw $20, 0x30(sp); \
|
||||
sw $21, 0x2c(sp); \
|
||||
sw $22, 0x28(sp); \
|
||||
sw $23, 0x24(sp); \
|
||||
sw $24, 0x20(sp); \
|
||||
sw $25, 0x1c(sp); \
|
||||
sw $26, 0x18(sp); \
|
||||
sw $27, 0x14(sp); \
|
||||
sw $28, 0x10(sp); \
|
||||
sw $29, 0xc(sp); \
|
||||
sw $30, 0x8(sp); \
|
||||
sw $31, 0x4(sp)
|
||||
|
||||
|
||||
#define LOAD_ALL \
|
||||
lw $0, 0x80(sp); \
|
||||
lw $1, 0x7c(sp); \
|
||||
lw $2, 0x78(sp); \
|
||||
lw $3, 0x74(sp); \
|
||||
lw $4, 0x70(sp); \
|
||||
lw $5, 0x6c(sp); \
|
||||
lw $6, 0x68(sp); \
|
||||
lw $7, 0x64(sp); \
|
||||
lw $8, 0x60(sp); \
|
||||
lw $9, 0x5c(sp); \
|
||||
lw $10, 0x58(sp); \
|
||||
lw $11, 0x54(sp); \
|
||||
lw $12, 0x50(sp); \
|
||||
lw $13, 0x4c(sp); \
|
||||
lw $14, 0x48(sp); \
|
||||
lw $15, 0x44(sp); \
|
||||
lw $16, 0x40(sp); \
|
||||
lw $17, 0x3c(sp); \
|
||||
lw $18, 0x38(sp); \
|
||||
lw $19, 0x34(sp); \
|
||||
lw $20, 0x30(sp); \
|
||||
lw $21, 0x2c(sp); \
|
||||
lw $22, 0x28(sp); \
|
||||
lw $23, 0x24(sp); \
|
||||
lw $24, 0x20(sp); \
|
||||
lw $25, 0x1c(sp); \
|
||||
lw $26, 0x18(sp); \
|
||||
lw $27, 0x14(sp); \
|
||||
lw $28, 0x10(sp); \
|
||||
lw $29, 0xc(sp); \
|
||||
lw $30, 0x8(sp); \
|
||||
lw $31, 0x4(sp); \
|
||||
addi sp, 132
|
||||
#endif
|
||||
/****************************************************************************/
|
38
resources/soc/simu/soft/func/include/asm/mipsregs.h
Normal file
38
resources/soc/simu/soft/func/include/asm/mipsregs.h
Normal file
@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Coprocessor 0 register names
|
||||
*/
|
||||
#define CP0_INDEX $0
|
||||
#define CP0_RANDOM $1
|
||||
#define CP0_ENTRYLO0 $2
|
||||
#define CP0_ENTRYLO1 $3
|
||||
#define CP0_CONF $3
|
||||
#define CP0_CONTEXT $4
|
||||
#define CP0_PAGEMASK $5
|
||||
#define CP0_WIRED $6
|
||||
#define CP0_INFO $7
|
||||
#define CP0_BADVADDR $8
|
||||
#define CP0_COUNT $9
|
||||
#define CP0_ENTRYHI $10
|
||||
#define CP0_COMPARE $11
|
||||
#define CP0_STATUS $12
|
||||
#define CP0_CAUSE $13
|
||||
#define CP0_EPC $14
|
||||
#define CP0_PRID $15
|
||||
#define CP0_CONFIG $16
|
||||
#define CP0_LLADDR $17
|
||||
#define CP0_WATCHLO $18
|
||||
#define CP0_WATCHHI $19
|
||||
#define CP0_XCONTEXT $20
|
||||
#define CP0_FRAMEMASK $21
|
||||
#define CP0_DIAGNOSTIC $22
|
||||
#define CP0_DEBUG $23
|
||||
#define CP0_DEPC $24
|
||||
#define CP0_PERFORMANCE $25
|
||||
#define CP0_ECC $26
|
||||
#define CP0_CACHEERR $27
|
||||
#define CP0_TAGLO $28
|
||||
#define CP0_TAGHI $29
|
||||
#define CP0_ERROREPC $30
|
||||
#define CP0_DESAVE $31
|
||||
|
||||
|
135
resources/soc/simu/soft/func/include/asm/ns16550.h
Normal file
135
resources/soc/simu/soft/func/include/asm/ns16550.h
Normal file
@ -0,0 +1,135 @@
|
||||
/*
|
||||
* Copyright (c) 2009 yanhua <yanh@lemote.it>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2, or (at
|
||||
* your option) any later version.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_CPU_UART
|
||||
//#define COMMON_COM_BASE_ADDR 0xbff003f8
|
||||
#define COMMON_COM_BASE_ADDR 0xbfd00000
|
||||
#define NS16550HZ 3686400
|
||||
#else
|
||||
#define COMMON_COM_BASE_ADDR 0xbfd003f8
|
||||
#define NS16550HZ 1843200
|
||||
#endif
|
||||
|
||||
#define CONS_BAUD B115200
|
||||
/*
|
||||
* NS16550 UART registers
|
||||
*/
|
||||
|
||||
#define NS16550_CHANA PHYS_TO_K1(UART0_BASE)
|
||||
#define NS16550_CHANB PHYS_TO_K1(UART1_BASE)
|
||||
|
||||
/*
|
||||
* Standard speeds, make these available for start.S et al.
|
||||
*/
|
||||
#define B0 0
|
||||
#define B50 50
|
||||
#define B75 75
|
||||
#define B110 110
|
||||
#define B134 134
|
||||
#define B150 150
|
||||
#define B200 200
|
||||
#define B300 300
|
||||
#define B600 600
|
||||
#define B1200 1200
|
||||
#define B1800 1800
|
||||
#define B2400 2400
|
||||
#define B4800 4800
|
||||
#define B9600 9600
|
||||
#define B19200 19200
|
||||
#define B38400 38400
|
||||
#define B7200 7200
|
||||
#define B14400 14400
|
||||
#define B28800 28800
|
||||
#define B57600 57600
|
||||
#define B76800 76800
|
||||
#define B115200 115200
|
||||
#define B230400 230400
|
||||
|
||||
#ifndef NSREG
|
||||
#define NSREG(x) x
|
||||
#endif
|
||||
|
||||
#define NS16550_DATA 0
|
||||
#define NS16550_IER 1
|
||||
#define NS16550_IIR 2
|
||||
#define NS16550_FIFO 2
|
||||
#define NS16550_CFCR 3
|
||||
#define NS16550_MCR 4
|
||||
#define NS16550_LSR 5
|
||||
#define NS16550_MSR 6
|
||||
#define NS16550_SCR 7
|
||||
|
||||
|
||||
/* interrupt enable register */
|
||||
#define IER_ERXRDY 0x1 /* int on rx ready */
|
||||
#define IER_ETXRDY 0x2 /* int on tx ready */
|
||||
#define IER_ERLS 0x4 /* int on line status change */
|
||||
#define IER_EMSC 0x8 /* int on modem status change */
|
||||
|
||||
/* interrupt identification register */
|
||||
#define IIR_IMASK 0xf /* mask */
|
||||
#define IIR_RXTOUT 0xc /* receive timeout */
|
||||
#define IIR_RLS 0x6 /* receive line status */
|
||||
#define IIR_RXRDY 0x4 /* receive ready */
|
||||
#define IIR_TXRDY 0x2 /* transmit ready */
|
||||
#define IIR_NOPEND 0x1 /* nothing */
|
||||
#define IIR_MLSC 0x0 /* modem status */
|
||||
#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
|
||||
|
||||
/* fifo control register */
|
||||
#define FIFO_ENABLE 0x01 /* enable fifo */
|
||||
#define FIFO_RCV_RST 0x02 /* reset receive fifo */
|
||||
#define FIFO_XMT_RST 0x04 /* reset transmit fifo */
|
||||
#define FIFO_DMA_MODE 0x08 /* enable dma mode */
|
||||
#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */
|
||||
#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */
|
||||
#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */
|
||||
#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */
|
||||
|
||||
/* character format control register */
|
||||
#define CFCR_DLAB 0x80 /* divisor latch */
|
||||
#define CFCR_SBREAK 0x40 /* send break */
|
||||
#define CFCR_PZERO 0x30 /* zero parity */
|
||||
#define CFCR_PONE 0x20 /* one parity */
|
||||
#define CFCR_PEVEN 0x10 /* even parity */
|
||||
#define CFCR_PODD 0x00 /* odd parity */
|
||||
#define CFCR_PENAB 0x08 /* parity enable */
|
||||
#define CFCR_STOPB 0x04 /* 2 stop bits */
|
||||
#define CFCR_8BITS 0x03 /* 8 data bits */
|
||||
#define CFCR_7BITS 0x02 /* 7 data bits */
|
||||
#define CFCR_6BITS 0x01 /* 6 data bits */
|
||||
#define CFCR_5BITS 0x00 /* 5 data bits */
|
||||
|
||||
/* modem control register */
|
||||
#define MCR_LOOPBACK 0x10 /* loopback */
|
||||
#define MCR_IENABLE 0x08 /* output 2 = int enable */
|
||||
#define MCR_DRS 0x04 /* output 1 = xxx */
|
||||
#define MCR_RTS 0x02 /* enable RTS */
|
||||
#define MCR_DTR 0x01 /* enable DTR */
|
||||
|
||||
/* line status register */
|
||||
#define LSR_RCV_FIFO 0x80 /* error in receive fifo */
|
||||
#define LSR_TSRE 0x40 /* transmitter empty */
|
||||
#define LSR_TXRDY 0x20 /* transmitter ready */
|
||||
#define LSR_BI 0x10 /* break detected */
|
||||
#define LSR_FE 0x08 /* framing error */
|
||||
#define LSR_PE 0x04 /* parity error */
|
||||
#define LSR_OE 0x02 /* overrun error */
|
||||
#define LSR_RXRDY 0x01 /* receiver ready */
|
||||
#define LSR_RCV_MASK 0x1f
|
||||
|
||||
/* modem status register */
|
||||
#define MSR_DCD 0x80 /* DCD active */
|
||||
#define MSR_RI 0x40 /* RI active */
|
||||
#define MSR_DSR 0x20 /* DSR active */
|
||||
#define MSR_CTS 0x10 /* CTS active */
|
||||
#define MSR_DDCD 0x08 /* DCD changed */
|
||||
#define MSR_TERI 0x04 /* RI changed */
|
||||
#define MSR_DDSR 0x02 /* DSR changed */
|
||||
#define MSR_DCTS 0x01 /* CTS changed */
|
39
resources/soc/simu/soft/func/include/asm/regdef.h
Normal file
39
resources/soc/simu/soft/func/include/asm/regdef.h
Normal file
@ -0,0 +1,39 @@
|
||||
/*
|
||||
* Symbolic register names for 32 bit ABI
|
||||
*/
|
||||
#define zero $0 /* wired zero */
|
||||
#define AT $1 /* assembler temp - uppercase because of ".set at" */
|
||||
#define v0 $2 /* return value */
|
||||
#define v1 $3
|
||||
#define a0 $4 /* argument registers */
|
||||
#define a1 $5
|
||||
#define a2 $6
|
||||
#define a3 $7
|
||||
#define t0 $8 /* caller saved */
|
||||
#define t1 $9
|
||||
#define t2 $10
|
||||
#define t3 $11
|
||||
#define t4 $12
|
||||
#define t5 $13
|
||||
#define t6 $14
|
||||
#define t7 $15
|
||||
#define s0 $16 /* callee saved */
|
||||
#define s1 $17
|
||||
#define s2 $18
|
||||
#define s3 $19
|
||||
#define s4 $20
|
||||
#define s5 $21
|
||||
#define s6 $22
|
||||
#define s7 $23
|
||||
#define t8 $24 /* caller saved */
|
||||
#define t9 $25
|
||||
#define jp $25 /* PIC jump register */
|
||||
#define k0 $26 /* kernel scratch */
|
||||
#define k1 $27
|
||||
#define gp $28 /* global pointer */
|
||||
#define sp $29 /* stack pointer */
|
||||
#define fp $30 /* frame pointer */
|
||||
#define s8 $30 /* same like fp! */
|
||||
#define ra $31 /* return address */
|
||||
|
||||
|
4
resources/soc/simu/soft/func/include/battery.h
Normal file
4
resources/soc/simu/soft/func/include/battery.h
Normal file
@ -0,0 +1,4 @@
|
||||
|
||||
void ADC_Init(void);
|
||||
void BatteryTest1();
|
||||
void BatteryTest2();
|
9
resources/soc/simu/soft/func/include/cmdline.h
Normal file
9
resources/soc/simu/soft/func/include/cmdline.h
Normal file
@ -0,0 +1,9 @@
|
||||
|
||||
int help(int argc, char argv[][30]);
|
||||
int m4(int argc, char argv[][30]);
|
||||
int m1(int argc, char argv[][30]);
|
||||
int d4(int argc, char argv[][30]);
|
||||
int d1(int argc, char argv[][30]);
|
||||
unsigned int str2num(char str[30]);
|
||||
|
||||
int cmdline(void);
|
5
resources/soc/simu/soft/func/include/common.h
Normal file
5
resources/soc/simu/soft/func/include/common.h
Normal file
@ -0,0 +1,5 @@
|
||||
|
||||
_fp32 bubble_sort(_fp32 *delta, _s32 len);
|
||||
void UintToBcd(_u32 dat, _u8 *bcd_buf);
|
||||
void BcdToUint(_u8 *bcd_buf, _u32 dat);
|
||||
_s32 printf_float(_fp32 data);
|
1
resources/soc/simu/soft/func/include/dg_rs232.h
Normal file
1
resources/soc/simu/soft/func/include/dg_rs232.h
Normal file
@ -0,0 +1 @@
|
||||
int dg_ctrl(int argc, char argv[][30]);
|
6
resources/soc/simu/soft/func/include/flash.h
Normal file
6
resources/soc/simu/soft/func/include/flash.h
Normal file
@ -0,0 +1,6 @@
|
||||
// CONFIDENTIAL
|
||||
|
||||
int verif(int argc, char argv[][30]);
|
||||
int set_pe_time_mode(int argc, char argv[][30]);
|
||||
int flash_tk(int argc, char argv[][30]);
|
||||
int flash_accg(int argc, char argv[][30]);
|
43
resources/soc/simu/soft/func/include/frame.h
Normal file
43
resources/soc/simu/soft/func/include/frame.h
Normal file
@ -0,0 +1,43 @@
|
||||
|
||||
#define ERROR 1
|
||||
#define DATA_LENGTH 100
|
||||
|
||||
extern _u32 RX_IndexW;
|
||||
void IrSend(_u8 *str);
|
||||
void uart_tx();
|
||||
void uart_rx();
|
||||
void Frame_exe(struct Date_Time *Date_and_Time, struct Data *Lcd_data);
|
||||
|
||||
union uint_uchar{
|
||||
_u32 i_value;
|
||||
_u8 c_value[4];
|
||||
};
|
||||
|
||||
/*-----------------协议字段-----------------*/
|
||||
struct FrameFormat{
|
||||
_u8 HeadCode;
|
||||
_u8 TypeCode;
|
||||
_u8 Address[7];
|
||||
_u8 CtrlCode;
|
||||
_u8 DataLen;
|
||||
_u8 DI0,DI1,SER;
|
||||
_u8 Data[DATA_LENGTH];
|
||||
_u8 CheckSum;
|
||||
_u8 TailCode;
|
||||
};
|
||||
|
||||
/****************三川写*****************/
|
||||
struct ModifyData{
|
||||
_u8 seg; //修正段号
|
||||
_u32 flowpoint; //修正流量点,使用时要除以10,xxxxx.x
|
||||
_u8 danwei; //修正单位
|
||||
_u32 flowdata; //标准流量数据,使用时要除以1000,xxx.xxx
|
||||
_u32 rcode; //配对热电阻编号
|
||||
_u32 temp; //标定温度值
|
||||
_u32 rdata; //热电阻阻值,使用时要除以100,xxxx.xx
|
||||
_u32 tempmodify; //温度修正系数,使用时要除以100000,x.xxxxx
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
10
resources/soc/simu/soft/func/include/isp.h
Normal file
10
resources/soc/simu/soft/func/include/isp.h
Normal file
@ -0,0 +1,10 @@
|
||||
void tgt_putchar(_u8 chr);
|
||||
_u8 tgt_getchar();
|
||||
_u8 tgt_testchar();
|
||||
_u32 now();
|
||||
|
||||
void Flash_Erase(_u32 addr);
|
||||
_u32 Flash_Write(_u32 addr, _u32 *data, _u32 num);
|
||||
void spiflash_erase(_u32 addr_start, _u32 addr_end);
|
||||
void spiflash_write(_u32 addr_w, _u32 addr_r, _u32 length);
|
||||
|
1
resources/soc/simu/soft/func/include/key.h
Normal file
1
resources/soc/simu/soft/func/include/key.h
Normal file
@ -0,0 +1 @@
|
||||
void Key(struct Data *Lcd_data);
|
132
resources/soc/simu/soft/func/include/lcd.h
Normal file
132
resources/soc/simu/soft/func/include/lcd.h
Normal file
@ -0,0 +1,132 @@
|
||||
/**************************************************************************
|
||||
***************************************************************************
|
||||
Notice: Some variable of Lcd_data = real_value * LCD_MULTIPLE
|
||||
***************************************************************************
|
||||
**************************************************************************/
|
||||
struct Data{
|
||||
_fp32 total_heat; //累计热量, plus LCD_MULTIPLE
|
||||
_fp32 heat; //热功率, plus LCD_MULTIPLE
|
||||
_fp32 temp1; //入水温度, plus LCD_MULTIPLE
|
||||
_fp32 temp2; //出水温度, plus LCD_MULTIPLE
|
||||
_fp32 temp0; //温差, plus LCD_MULTIPLE
|
||||
_fp32 total_flow; //累计流量, plus LCD_MULTIPLE
|
||||
_fp32 flow; //瞬时流量, plus LCD_MULTIPLE
|
||||
_u32 total_time; //工作时间
|
||||
_u32 alarm_time; //报警时间
|
||||
_u32 date; //年月日
|
||||
_u32 time; //时分秒
|
||||
_u32 usercode;
|
||||
_fp32 version;
|
||||
_u32 history;
|
||||
_u32 lcdmode; //A1_1;
|
||||
_u32 auto_caculate;
|
||||
};
|
||||
void LcdDisplay(struct Date_Time *Date_and_Time, struct Data *Lcd_data);
|
||||
|
||||
//---------------A1菜单-------------
|
||||
#define A1 1
|
||||
#define A1_0 10 //显示A1
|
||||
|
||||
#define A1_1 11
|
||||
#define A1_1_0 (0x08+0x04) //'累积热量 '
|
||||
#define A1_1_1 (0x10+0x20) //'KW*h'
|
||||
|
||||
#define A1_2 12 //一位小数
|
||||
#define A1_2_0 (0x10) //'功率 '
|
||||
#define A1_2_1 (0x00) //
|
||||
|
||||
#define A1_3 13 //'T入 T出' 一位小数
|
||||
#define A1_3_0 (0x20) //'T出'
|
||||
#define A1_3_1 (0x04) //'`C'
|
||||
|
||||
#define A1_4 14 //两位小数
|
||||
#define A1_4_0 (0x02) //'温差 '
|
||||
#define A1_4_1 (0x04) //'`C'
|
||||
|
||||
#define A1_5 15 //两位小数
|
||||
#define A1_5_0 (0x08+0x01) //'累积流量'
|
||||
#define A1_5_1 (0x02) //'m3'
|
||||
|
||||
#define A1_6 16 //三位小数
|
||||
#define A1_6_0 (0x01) //'瞬时流量 '
|
||||
#define A1_6_1 (0x02+0x01+0x80) //'m3/h'
|
||||
|
||||
#define A1_7 17
|
||||
#define A1_7_0 (0x08+0x80) //'累积运行时间'
|
||||
#define A1_7_1 (0x80) //'h'
|
||||
|
||||
#define A1_8 18
|
||||
#define A1_8_0 (0x40) //'报警时间'
|
||||
#define A1_8_1 (0x80) //'h'
|
||||
|
||||
//--------------A2菜单-------------
|
||||
#define A2 2
|
||||
#define A2_0 20 //显示A2
|
||||
|
||||
#define A2_1 21 //年月日
|
||||
#define A2_1_0 (0x80) //'时间'
|
||||
#define A2_1_1 (0x00)
|
||||
|
||||
#define A2_2 22 //时分秒
|
||||
#define A2_2_0 (0x80) //'时间'
|
||||
#define A2_2_1 (0x00)
|
||||
|
||||
#define A2_3 23 //用户编号
|
||||
#define A2_3_0 (0x00) //
|
||||
#define A2_3_1 (0x00)
|
||||
|
||||
#define A2_4 24 //版本号
|
||||
#define A2_4_0 (0x00) //
|
||||
#define A2_4_1 (0x00)
|
||||
|
||||
#define A2_5 25 //低电压'P6'
|
||||
#define A2_5_0 (0x00) //
|
||||
#define A2_5_1 (0x00)
|
||||
|
||||
#define A2_6 26 //屏全显
|
||||
|
||||
//--------------A3菜单--------------
|
||||
#define A3 3
|
||||
#define A3_0 30 //显示A3
|
||||
|
||||
#define A3_1 31 //年月
|
||||
#define A3_1_0 (0x80) //'时间'
|
||||
#define A3_1_1 (0x00)
|
||||
|
||||
#define A3_2 32
|
||||
#define A3_2_0 (0x08+0x01) //'累积流量'
|
||||
#define A3_2_1 (0x02) //'m3'
|
||||
|
||||
#define A3_3 33
|
||||
#define A3_3_0 (0x08+0x04) //'累计热量 '
|
||||
#define A3_3_1 (0x10+0x20) //'KW*h'
|
||||
|
||||
//--------------A4菜单--------------
|
||||
#define A4 4
|
||||
#define A4_0 40 //显示A4
|
||||
|
||||
#define A4_1 41 //三位小数
|
||||
#define A4_1_0 (0x01) //'瞬时流量 '
|
||||
#define A4_1_1 (0x02+0x01+0x80+0x08) //'m3/h'+'检定'
|
||||
|
||||
#define A4_2 42 //五位小数
|
||||
#define A4_2_0 (0x08+0x01) //'累积流量'
|
||||
#define A4_2_1 (0x02+0x08) //'m3'+'检定'
|
||||
|
||||
#define A4_3 43
|
||||
#define A4_3_0 (0x10) //'功率 '
|
||||
#define A4_3_1 (0x00+0x08) // +'检定'
|
||||
|
||||
#define A4_4 44 //四位小数
|
||||
#define A4_4_0 (0x08+0x04) //'累积热量 '
|
||||
#define A4_4_1 (0x10+0x20+0x08) //'KW*h'+'检定'
|
||||
|
||||
#define A4_5 45 //'T入 T出' 两位小数
|
||||
#define A4_5_0 (0x20) //'T出'
|
||||
#define A4_5_1 (0x04+0x08) //'`C'+'检定'
|
||||
|
||||
#define A4_6 46
|
||||
#define A4_6_0 (0x02) //'温差 '
|
||||
#define A4_6_1 (0x04+0x08) //'`C'+'检定'
|
||||
|
||||
|
158
resources/soc/simu/soft/func/include/ls1d.h
Normal file
158
resources/soc/simu/soft/func/include/ls1d.h
Normal file
@ -0,0 +1,158 @@
|
||||
|
||||
/********************************Variable Option**********************************************************************************************************************/
|
||||
typedef char _s8;
|
||||
typedef unsigned char _u8;
|
||||
|
||||
typedef short _s16;
|
||||
typedef unsigned short _u16;
|
||||
|
||||
typedef int _s32;
|
||||
typedef unsigned int _u32;
|
||||
|
||||
typedef float _fp32;
|
||||
|
||||
/********************************LS1D Chip Option**********************************************************************************************************************/
|
||||
/********************************LS1D Address Space********************************/
|
||||
#define UNCACHED_MEMORY_ADDR 0xa0000000
|
||||
#define UNCACHED_TO_PHYS(x) ((x) & 0x1fffffff)
|
||||
#define PHYS_TO_UNCACHED(x) ((x) | UNCACHED_MEMORY_ADDR)
|
||||
|
||||
#define SRAM_BASEADDR PHYS_TO_UNCACHED(0x0) //sram
|
||||
#define SPI_FLASH_BASEADDR PHYS_TO_UNCACHED(0x1e000000) //spi flash
|
||||
#define FLASH_BASEADDR PHYS_TO_UNCACHED(0x1f000000) //spi/nand/lpc
|
||||
#define BOOT_ADDR PHYS_TO_UNCACHED(0x1fc00000) //spi/flash
|
||||
#define FLASH_REG_BASEADDR PHYS_TO_UNCACHED(0x1fe60000) //flash regs
|
||||
#define SPI_REG_BASEADDR PHYS_TO_UNCACHED(0x1fe80000) //spi regs
|
||||
#define UART0_BASEADDR PHYS_TO_UNCACHED(0x1fe40000) // LS 20130123
|
||||
#define UART1_BASEADDR PHYS_TO_UNCACHED(0x1fe88000)
|
||||
#define I2C_BASEADDR PHYS_TO_UNCACHED(0x1fe90000)
|
||||
#define REGS_BASEADDR PHYS_TO_UNCACHED(0x1fea0000) //Interrupt_Regs_Baseaddr
|
||||
|
||||
#define PMU_BASEADDR PHYS_TO_UNCACHED(0x1feb0000)
|
||||
#define SONAR_BASEADDR PHYS_TO_UNCACHED(0x1feb4000)
|
||||
#define THSENS_BASEADDR PHYS_TO_UNCACHED(0x1feb8000)
|
||||
|
||||
#define SLCD_REG_BASEADDR PHYS_TO_UNCACHED(0x1febc000)
|
||||
#define ADC_BASEADDR PHYS_TO_UNCACHED(0x1fea8000)
|
||||
|
||||
/********************************PMU REGS********************************/
|
||||
#define PMU_Timing *(volatile _u32 *)(PMU_BASEADDR)
|
||||
#define PMU_Command *(volatile _u32 *)(PMU_BASEADDR+0x04)
|
||||
#define PMU_Compare *(volatile _u32 *)(PMU_BASEADDR+0x08)
|
||||
|
||||
#define PMU_ChipCtrl *(volatile _u32 *)(PMU_BASEADDR+0x0C)
|
||||
#define PMU_GPIO_OE *(volatile _u32 *)(PMU_BASEADDR+0x10)
|
||||
#define PMU_GPIO_O *(volatile _u32 *)(PMU_BASEADDR+0x14)
|
||||
#define PMU_GPIO_I *(volatile _u32 *)(PMU_BASEADDR+0x18)
|
||||
|
||||
#define PMU_Count *(volatile _u32 *)(PMU_BASEADDR+0x1c)
|
||||
|
||||
#define PMU_UserDat0 *(volatile _u32 *)(PMU_BASEADDR+0x20)
|
||||
#define PMU_UserDat1 *(volatile _u32 *)(PMU_BASEADDR+0x24)
|
||||
#define PMU_UserDat2 *(volatile _u32 *)(PMU_BASEADDR+0x28)
|
||||
#define PMU_UserDat3 *(volatile _u32 *)(PMU_BASEADDR+0x2c)
|
||||
#define PMU_UserDat4 *(volatile _u32 *)(PMU_BASEADDR+0x30)
|
||||
|
||||
#define PMU_AutoSave *(volatile _u32 *)(PMU_BASEADDR+0x34)
|
||||
#define PMU_Exint *(volatile _u32 *)(PMU_BASEADDR+0x38) //external interrupt
|
||||
#define PMU_CommandW *(volatile _u32 *)(PMU_BASEADDR+0x3c)
|
||||
|
||||
/******************************SONAR REGS********************************/
|
||||
#define SONAR_PulseDef *(volatile _u32 *)(SONAR_BASEADDR)
|
||||
#define SONAR_SonarCtrl0 *(volatile _u32 *)(SONAR_BASEADDR+0x04)
|
||||
#define SONAR_SonarCtrl1 *(volatile _u32 *)(SONAR_BASEADDR+0x08)
|
||||
#define SONAR_GateDef1 *(volatile _u32 *)(SONAR_BASEADDR+0x0C)
|
||||
#define SONAR_GateDef2 *(volatile _u32 *)(SONAR_BASEADDR+0x10)
|
||||
#define SONAR_GateDef3 *(volatile _u32 *)(SONAR_BASEADDR+0x14)
|
||||
#define SONAR_WaveW_Cur *(volatile _u32 *)(SONAR_BASEADDR+0x18)
|
||||
#define SONAR_WaveW_Last *(volatile _u32 *)(SONAR_BASEADDR+0x1C)
|
||||
#define SONAR_ResPtr *(volatile _u32 *)(SONAR_BASEADDR+0x20)
|
||||
|
||||
#define SONAR_Result *(volatile _u32 *)(SONAR_BASEADDR+0x40)
|
||||
//Result[15:0] SONAR_BASEADDR + [0x40 ~ 0x7c]
|
||||
|
||||
/*****************************THSENS REGS********************************/
|
||||
#define ThsensCtrl *(volatile _u32 *)(THSENS_BASEADDR)
|
||||
|
||||
|
||||
/*******************************LCD REGS*********************************/
|
||||
#define LCD_FB_0 *(volatile _u32 *)(SLCD_REG_BASEADDR)
|
||||
#define LCD_FB_1 *(volatile _u32 *)(SLCD_REG_BASEADDR+0x04)
|
||||
#define LCD_FB_2 *(volatile _u32 *)(SLCD_REG_BASEADDR+0x08)
|
||||
#define LCD_RefeshRate *(volatile _u32 *)(SLCD_REG_BASEADDR+0x0C)
|
||||
|
||||
/***************************INTERRUPT REGS******************************/
|
||||
#define INT_EN *(volatile _u8 *)(REGS_BASEADDR)
|
||||
#define INT_EGDE *(volatile _u8 *)(REGS_BASEADDR+0x01)
|
||||
#define INT_POL *(volatile _u8 *)(REGS_BASEADDR+0x02)
|
||||
#define INT_CLR *(volatile _u8 *)(REGS_BASEADDR+0x03)
|
||||
#define INT_SET *(volatile _u8 *)(REGS_BASEADDR+0x04)
|
||||
#define INT_OUT *(volatile _u8 *)(REGS_BASEADDR+0x05)
|
||||
|
||||
/*******************************ADC REGS********************************/
|
||||
|
||||
#define ADC_CR *(volatile _u8 *)(ADC_BASEADDR)
|
||||
#define ADC_D0 *(volatile _u8 *)(ADC_BASEADDR+0x1)
|
||||
#define ADC_D1 *(volatile _u8 *)(ADC_BASEADDR+0x2)
|
||||
|
||||
/*******************************I2C REGS********************************/
|
||||
#define IIC_PRER_L *(volatile _u8 *)(I2C_BASEADDR+0x00)
|
||||
#define IIC_PRER_H *(volatile _u8 *)(I2C_BASEADDR+0x01)
|
||||
#define IIC_CTR *(volatile _u8 *)(I2C_BASEADDR+0x02)
|
||||
#define IIC_TXR *(volatile _u8 *)(I2C_BASEADDR+0x03) //w
|
||||
#define IIC_RXR *(volatile _u8 *)(I2C_BASEADDR+0x03) //r
|
||||
#define IIC_CR *(volatile _u8 *)(I2C_BASEADDR+0x04) //w
|
||||
#define IIC_SR *(volatile _u8 *)(I2C_BASEADDR+0x04) //r
|
||||
#define IIC_ADDR *(volatile _u8 *)(I2C_BASEADDR+0x07) // 7ä½å°å MSB æ æ
|
||||
|
||||
/*****************************UART0 REGS********************************/
|
||||
//NS16550
|
||||
#define Uart0_RxData *(volatile _u8 *)(UART0_BASEADDR)
|
||||
#define Uart0_TxData *(volatile _u8 *)(UART0_BASEADDR)
|
||||
#define Uart0_IER *(volatile _u8 *)(UART0_BASEADDR+0x01)
|
||||
#define Uart0_IIR *(volatile _u8 *)(UART0_BASEADDR+0x02) //read only
|
||||
#define Uart0_FCR *(volatile _u8 *)(UART0_BASEADDR+0x02) //write only
|
||||
#define Uart0_LCR *(volatile _u8 *)(UART0_BASEADDR+0x03)
|
||||
#define Uart0_MCR *(volatile _u8 *)(UART0_BASEADDR+0x04)
|
||||
#define Uart0_LSR *(volatile _u8 *)(UART0_BASEADDR+0x05)
|
||||
#define Uart0_MSR *(volatile _u8 *)(UART0_BASEADDR+0x06)
|
||||
|
||||
#define Uart0_BaudL *(volatile _u8 *)(UART0_BASEADDR)
|
||||
#define Uart0_BaudH *(volatile _u8 *)(UART0_BASEADDR+0x01)
|
||||
|
||||
/*****************************UART1 REGS********************************/
|
||||
//NS16550
|
||||
#define Uart1_RxData *(volatile _u8 *)(UART1_BASEADDR)
|
||||
#define Uart1_TxData *(volatile _u8 *)(UART1_BASEADDR)
|
||||
#define Uart1_IER *(volatile _u8 *)(UART1_BASEADDR+0x01)
|
||||
#define Uart1_IIR *(volatile _u8 *)(UART1_BASEADDR+0x02) //read only
|
||||
#define Uart1_FCR *(volatile _u8 *)(UART1_BASEADDR+0x02) //write only
|
||||
#define Uart1_LCR *(volatile _u8 *)(UART1_BASEADDR+0x03)
|
||||
#define Uart1_MCR *(volatile _u8 *)(UART1_BASEADDR+0x04)
|
||||
#define Uart1_LSR *(volatile _u8 *)(UART1_BASEADDR+0x05)
|
||||
#define Uart1_MSR *(volatile _u8 *)(UART1_BASEADDR+0x06)
|
||||
|
||||
#define Uart1_BaudL *(volatile _u8 *)(UART1_BASEADDR)
|
||||
#define Uart1_BaudH *(volatile _u8 *)(UART1_BASEADDR+0x01)
|
||||
|
||||
/*******************************SPI REGS********************************/
|
||||
#define SPI_SPCR *(volatile _u8 *)(SPI_REG_BASEADDR)
|
||||
#define SPI_SPSR *(volatile _u8 *)(SPI_REG_BASEADDR+0x01)
|
||||
#define SPI_TxFIFO *(volatile _u8 *)(SPI_REG_BASEADDR+0x02)
|
||||
#define SPI_RxFIFO *(volatile _u8 *)(SPI_REG_BASEADDR+0x02)
|
||||
#define SPI_SPER *(volatile _u8 *)(SPI_REG_BASEADDR+0x03)
|
||||
#define SPI_SFC_PARAM *(volatile _u8 *)(SPI_REG_BASEADDR+0x04)
|
||||
#define SPI_SFC_SOFTCS *(volatile _u8 *)(SPI_REG_BASEADDR+0x05)
|
||||
#define SPI_SFC_TIMING *(volatile _u8 *)(SPI_REG_BASEADDR+0x06)
|
||||
|
||||
/*****************************FLASH REGS********************************/
|
||||
#define FLASH_CMD_REG *(volatile _u32 *)(FLASH_REG_BASEADDR)
|
||||
#define FLASH_ERASE_ALL 0x80000000
|
||||
#define FLASH_ERASE_CMD 0xa0000000
|
||||
#define FLASH_WRITE_CMD 0xe0000000
|
||||
#define FLASH_PAGE_LATCH_CLEAR 0X40000000
|
||||
#define FLASH_ADDR_MASK 0x7ffff80
|
||||
|
||||
#define FLASH_PAGE_LATCH_BASEADDR 0xbfe68000 //128bytes
|
||||
|
||||
/**********************************************************************************************************************************************************************/
|
11
resources/soc/simu/soft/func/include/temp_flow.h
Normal file
11
resources/soc/simu/soft/func/include/temp_flow.h
Normal file
@ -0,0 +1,11 @@
|
||||
|
||||
void InitTdc(void);
|
||||
//_fp32 Time_Caculate(_u32 *result, struct Data *Lcd_data, _u16 start, _u32 stop_num);
|
||||
//void Flow_Caculate(_fp32 delta_time, _fp32 duration, struct Data *Lcd_data);
|
||||
//void Temp_Caculate(_u32 *result, struct Data *Lcd_data, _u32 num);
|
||||
//void Heat_Caculate(_fp32 duration, struct Data *Lcd_data);
|
||||
_u32 res_ready(struct Data *Lcd_data);
|
||||
|
||||
|
||||
extern _fp32 Last_total_flow; //上次计算时的累积流量
|
||||
|
16
resources/soc/simu/soft/func/include/xmodem.h
Normal file
16
resources/soc/simu/soft/func/include/xmodem.h
Normal file
@ -0,0 +1,16 @@
|
||||
_u32 xmodem(void);
|
||||
|
||||
//³£Êý¶¨Òå
|
||||
#define BLOCKSIZE 128 //M16µÄÒ»¸öFlashҳΪ128×Ö½Ú(64×Ö)
|
||||
|
||||
|
||||
//¶¨ÒåÈ«¾Ö±äÁ¿
|
||||
struct str_XMODEM
|
||||
{
|
||||
unsigned char SOH; //Æðʼ×Ö½Ú
|
||||
unsigned char BlockNo; //Êý¾Ý¿é±àºÅ
|
||||
unsigned char nBlockNo; //Êý¾Ý¿é±àºÅ·´Âë
|
||||
unsigned char Xdata[BLOCKSIZE]; //Êý¾Ý128×Ö½Ú
|
||||
unsigned char CRC16hi; //CRC16УÑéÊý¾Ý¸ßλ
|
||||
unsigned char CRC16lo; //CRC16УÑéÊý¾ÝµÍλ
|
||||
};
|
12
resources/soc/simu/soft/func/lib/Makefile
Normal file
12
resources/soc/simu/soft/func/lib/Makefile
Normal file
@ -0,0 +1,12 @@
|
||||
|
||||
%.o:%.c
|
||||
$(CC) $(DEBUG) $(FLAGS) -EL -c -o $@ $<
|
||||
|
||||
objs= memset.o memcpy.o printf.o udelay.o putchar.o puts.o printhex.o printbase.o memcmp.o strcat.o strchr.o strcmp.o strtok.o strspn.o strcspn.o
|
||||
|
||||
$(TOPDIR)/libtinyc.a: $(objs)
|
||||
$(AR) -cr $@ $?
|
||||
|
||||
clean:
|
||||
rm -f *.o *.a *.s
|
||||
|
16
resources/soc/simu/soft/func/lib/memcmp.c
Normal file
16
resources/soc/simu/soft/func/lib/memcmp.c
Normal file
@ -0,0 +1,16 @@
|
||||
/**
|
||||
* memcmp - Compare two areas of memory
|
||||
* @cs: One area of memory
|
||||
* @ct: Another area of memory
|
||||
* @count: The size of the area.
|
||||
*/
|
||||
int memcmp(const void * cs,const void * ct,int count)
|
||||
{
|
||||
const unsigned char *su1, *su2;
|
||||
signed char res = 0;
|
||||
|
||||
for( su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--)
|
||||
if ((res = *su1 - *su2) != 0)
|
||||
break;
|
||||
return res;
|
||||
}
|
16
resources/soc/simu/soft/func/lib/memcpy.c
Normal file
16
resources/soc/simu/soft/func/lib/memcpy.c
Normal file
@ -0,0 +1,16 @@
|
||||
typedef int size_t;
|
||||
void *memcpy(void *s1, const void *s2, size_t n)
|
||||
{
|
||||
const char *f = s2;
|
||||
char *t = s1;
|
||||
|
||||
if (f < t) {
|
||||
f += n;
|
||||
t += n;
|
||||
while (n-- > 0)
|
||||
*--t = *--f;
|
||||
} else
|
||||
while (n-- > 0)
|
||||
*t++ = *f++;
|
||||
return s1;
|
||||
}
|
10
resources/soc/simu/soft/func/lib/memset.c
Normal file
10
resources/soc/simu/soft/func/lib/memset.c
Normal file
@ -0,0 +1,10 @@
|
||||
typedef int size_t;
|
||||
void * memset(void * s,int c, size_t count)
|
||||
{
|
||||
char *xs = (char *) s;
|
||||
|
||||
while (count--)
|
||||
*xs++ = c;
|
||||
|
||||
return s;
|
||||
}
|
28
resources/soc/simu/soft/func/lib/printbase.c
Normal file
28
resources/soc/simu/soft/func/lib/printbase.c
Normal file
@ -0,0 +1,28 @@
|
||||
int printbase(long v,int w,int base,int sign)
|
||||
{
|
||||
int i,j;
|
||||
int c;
|
||||
char buf[64];
|
||||
unsigned long value;
|
||||
if(sign && v<0)
|
||||
{
|
||||
value = -v;
|
||||
putchar('-');
|
||||
}
|
||||
else value=v;
|
||||
|
||||
for(i=0;value;i++)
|
||||
{
|
||||
buf[i]=value%base;
|
||||
value=value/base;
|
||||
}
|
||||
|
||||
#define max(a,b) (((a)>(b))?(a):(b))
|
||||
|
||||
for(j=max(w,i);j>0;j--)
|
||||
{
|
||||
c=j>i?0:buf[j-1];
|
||||
putchar((c<=9)?c+'0':c-0xa+'a');
|
||||
}
|
||||
return 0;
|
||||
}
|
79
resources/soc/simu/soft/func/lib/printf.c
Normal file
79
resources/soc/simu/soft/func/lib/printf.c
Normal file
@ -0,0 +1,79 @@
|
||||
int printf(char *fmt,...)
|
||||
{
|
||||
int i;
|
||||
char c;
|
||||
void **arg;
|
||||
void *ap;
|
||||
int w;
|
||||
__builtin_va_start(ap,fmt);
|
||||
arg=ap;
|
||||
for(i=0;fmt[i];i++)
|
||||
{
|
||||
c=fmt[i];
|
||||
if(c=='%')
|
||||
{
|
||||
w=1;
|
||||
again:
|
||||
switch(fmt[i+1])
|
||||
{
|
||||
case 's':
|
||||
puts(*arg);
|
||||
arg++;
|
||||
i++;
|
||||
break;
|
||||
case 'c':
|
||||
putchar((long)*arg);
|
||||
arg++;
|
||||
i++;
|
||||
break;
|
||||
case 'u':
|
||||
printbase((long)*arg,w,10,0);
|
||||
arg++;
|
||||
i++;
|
||||
break;
|
||||
case 'd':
|
||||
printbase((long)*arg,w,10,0);
|
||||
arg++;
|
||||
i++;
|
||||
break;
|
||||
case 'o':
|
||||
printbase((long)*arg,w,8,0);
|
||||
arg++;
|
||||
i++;
|
||||
break;
|
||||
case 'b':
|
||||
printbase((long)*arg,w,2,0);
|
||||
arg++;
|
||||
i++;
|
||||
break;
|
||||
case 'p':
|
||||
case 'x':
|
||||
printbase((long)*arg,w,16,0);
|
||||
arg++;
|
||||
i++;
|
||||
break;
|
||||
case '%':
|
||||
putchar('%');
|
||||
i++;
|
||||
break;
|
||||
case '0':
|
||||
i++;
|
||||
case '1' ... '9':
|
||||
for(w=0;fmt[i+1]>'0' && fmt[i+1]<='9';i++)
|
||||
w=w*10+(fmt[i+1]-'0');
|
||||
goto again;
|
||||
break;
|
||||
|
||||
default:
|
||||
putchar('%');
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
else{
|
||||
if(c=='\n') putchar('\r');
|
||||
putchar(c);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
11
resources/soc/simu/soft/func/lib/printhex.c
Normal file
11
resources/soc/simu/soft/func/lib/printhex.c
Normal file
@ -0,0 +1,11 @@
|
||||
int printhex(long v,int w)
|
||||
{
|
||||
int i;
|
||||
int c;
|
||||
for(i=4*(w-1);i>=0;i-=4)
|
||||
{
|
||||
c=(v>>i)&0xf;
|
||||
putchar((c<=9)?c+'0':c-0xa+'a');
|
||||
}
|
||||
return 0;
|
||||
}
|
5
resources/soc/simu/soft/func/lib/putchar.c
Normal file
5
resources/soc/simu/soft/func/lib/putchar.c
Normal file
@ -0,0 +1,5 @@
|
||||
int putchar(unsigned char c)
|
||||
{
|
||||
tgt_putchar(c);
|
||||
return 0;
|
||||
}
|
13
resources/soc/simu/soft/func/lib/puts.c
Normal file
13
resources/soc/simu/soft/func/lib/puts.c
Normal file
@ -0,0 +1,13 @@
|
||||
int puts(char *s)
|
||||
{
|
||||
char c;
|
||||
while((c=*s))
|
||||
{
|
||||
if(c == '\n') putchar('\r');
|
||||
putchar(c);
|
||||
s++;
|
||||
}
|
||||
putchar('\r');
|
||||
putchar('\n');
|
||||
return 0;
|
||||
}
|
48
resources/soc/simu/soft/func/lib/strcat.c
Normal file
48
resources/soc/simu/soft/func/lib/strcat.c
Normal file
@ -0,0 +1,48 @@
|
||||
/* $Id: strcat.c,v 1.1.1.1 2006/09/14 01:59:06 root Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2000-2002 Opsycon AB (www.opsycon.se)
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Opsycon AB.
|
||||
* 4. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
char *
|
||||
strcat(char *dst, const char *src)
|
||||
{
|
||||
char *d;
|
||||
|
||||
if (!dst || !src)
|
||||
return (dst);
|
||||
|
||||
d = dst;
|
||||
for (; *d; d++);
|
||||
for (; *src; src++)
|
||||
*d++ = *src;
|
||||
*d = 0;
|
||||
return (dst);
|
||||
}
|
44
resources/soc/simu/soft/func/lib/strchr.c
Normal file
44
resources/soc/simu/soft/func/lib/strchr.c
Normal file
@ -0,0 +1,44 @@
|
||||
/* $Id: strchr.c,v 1.1.1.1 2006/09/14 01:59:06 root Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2000-2002 Opsycon AB (www.opsycon.se)
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Opsycon AB.
|
||||
* 4. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
char *
|
||||
strchr(const char *p, int c)
|
||||
{
|
||||
if (!p)
|
||||
return (0);
|
||||
|
||||
for (; *p; p++)
|
||||
if (*p == c)
|
||||
return ((char *)p);
|
||||
return (0);
|
||||
}
|
11
resources/soc/simu/soft/func/lib/strcmp.c
Normal file
11
resources/soc/simu/soft/func/lib/strcmp.c
Normal file
@ -0,0 +1,11 @@
|
||||
/*
|
||||
* Compare strings.
|
||||
*/
|
||||
int
|
||||
strcmp(const char *s1, const char *s2)
|
||||
{
|
||||
while (*s1 == *s2++)
|
||||
if (*s1++ == 0)
|
||||
return (0);
|
||||
return (*(const unsigned char *)s1 - *(const unsigned char *)--s2);
|
||||
}
|
48
resources/soc/simu/soft/func/lib/strcspn.c
Normal file
48
resources/soc/simu/soft/func/lib/strcspn.c
Normal file
@ -0,0 +1,48 @@
|
||||
/* $Id: strcspn.c,v 1.1.1.1 2006/09/14 01:59:06 root Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2000-2002 Opsycon AB (www.opsycon.se)
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Opsycon AB.
|
||||
* 4. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
int
|
||||
strcspn (const char *p, const char *s)
|
||||
{
|
||||
int i, j;
|
||||
|
||||
for (i = 0; p[i]; i++) {
|
||||
for (j = 0; s[j]; j++) {
|
||||
if (s[j] == p[i])
|
||||
break;
|
||||
}
|
||||
if (s[j])
|
||||
break;
|
||||
}
|
||||
return (i);
|
||||
}
|
51
resources/soc/simu/soft/func/lib/strspn.c
Normal file
51
resources/soc/simu/soft/func/lib/strspn.c
Normal file
@ -0,0 +1,51 @@
|
||||
/* $Id: strspn.c,v 1.1.1.1 2006/09/14 01:59:06 root Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2000-2002 Opsycon AB (www.opsycon.se)
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Opsycon AB.
|
||||
* 4. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
/* return length of initial segment of p that consists entirely of
|
||||
* characters from s */
|
||||
|
||||
int
|
||||
strspn(const char *p, const char *s)
|
||||
{
|
||||
int i, j;
|
||||
|
||||
for (i = 0; p[i]; i++) {
|
||||
for (j = 0; s[j]; j++) {
|
||||
if (s[j] == p[i])
|
||||
break;
|
||||
}
|
||||
if (!s[j])
|
||||
break;
|
||||
}
|
||||
return (i);
|
||||
}
|
51
resources/soc/simu/soft/func/lib/strtok.c
Normal file
51
resources/soc/simu/soft/func/lib/strtok.c
Normal file
@ -0,0 +1,51 @@
|
||||
/* $Id: strtok.c,v 1.1.1.1 2006/09/14 01:59:06 root Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2000-2002 Opsycon AB (www.opsycon.se)
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Opsycon AB.
|
||||
* 4. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
|
||||
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
char *
|
||||
strtok(char *p, const char *tok)
|
||||
{
|
||||
static char *t; /* XXX */
|
||||
char *r;
|
||||
int n;
|
||||
|
||||
if (p)
|
||||
t = p;
|
||||
|
||||
r = t + strspn (t, tok);
|
||||
if (!(n = strcspn (r, tok)))
|
||||
return (0);
|
||||
t = r + n;
|
||||
if (*t)
|
||||
*t++ = 0;
|
||||
return (r);
|
||||
}
|
13
resources/soc/simu/soft/func/lib/udelay.c
Normal file
13
resources/soc/simu/soft/func/lib/udelay.c
Normal file
@ -0,0 +1,13 @@
|
||||
void udelay(int us)
|
||||
{
|
||||
#if 0
|
||||
int count0,count1;
|
||||
int debug=0;
|
||||
us *=CPU_COUNT_PER_US;
|
||||
asm volatile("mfc0 %0,$9":"=r"(count0));
|
||||
do{
|
||||
asm volatile("mfc0 %0,$9":"=r"(count1));
|
||||
}while(count1 -count0<us);
|
||||
asm volatile("mtc0 %0,$23;"::"r"(debug));
|
||||
#endif
|
||||
}
|
7
resources/soc/simu/soft/func/main.c
Normal file
7
resources/soc/simu/soft/func/main.c
Normal file
@ -0,0 +1,7 @@
|
||||
#include "config.h"
|
||||
|
||||
void main()
|
||||
{
|
||||
SystemInit();
|
||||
cmdline();
|
||||
}
|
284
resources/soc/simu/soft/func/nand_test.S
Normal file
284
resources/soc/simu/soft/func/nand_test.S
Normal file
@ -0,0 +1,284 @@
|
||||
#include "regdef.h"
|
||||
#define SIZE_2K
|
||||
|
||||
###define ECC
|
||||
|
||||
#define NAND_BASE 0xbfe78000
|
||||
#define CONFREG_BASE 0xbfd00000
|
||||
#define NAND_RD_MEM_BASE 0x84600000
|
||||
#define NAND_WR_MEM_BASE 0x84700800
|
||||
#define OPERATION_PAGES 0x1
|
||||
#define OPERATION_GRID 0x7
|
||||
|
||||
|
||||
#ifdef SIZE_2K
|
||||
#define SIZE_OOB 0x40
|
||||
#define SIZE_MAIN 0x800
|
||||
#define ECC_GRID 0xcc
|
||||
#else
|
||||
#define SIZE_OOB 0x10
|
||||
#define SIZE_MAIN 0x200
|
||||
#define ECC_GRID 0xcc
|
||||
#endif
|
||||
|
||||
#ifdef ECC
|
||||
#define NAND_WR_CMD 0x1005
|
||||
#define NAND_RD_CMD 0x4803
|
||||
#define NAND_NUM 204*OPERATION_GRID
|
||||
#define DMA_NUM 47*OPERATION_GRID
|
||||
#else
|
||||
#define NAND_WR_CMD 0x5
|
||||
#define NAND_RD_CMD 0x3
|
||||
#define NAND_NUM 2048*OPERATION_PAGES
|
||||
#define DMA_NUM 512*OPERATION_PAGES
|
||||
#endif
|
||||
|
||||
#define NAND_START_ADDR 0x0
|
||||
#define NAND_END_ADDR 0x4000
|
||||
#define MALLOC_ADDR 0x80020000
|
||||
#define SLOW_LOOP
|
||||
.set noat
|
||||
.set noreorder
|
||||
|
||||
.global nand_test
|
||||
.ent nand_test
|
||||
nand_test:
|
||||
move k0, ra
|
||||
|
||||
la a0, msg_nand_test_begin
|
||||
jal stringserial
|
||||
nop
|
||||
|
||||
li t0, NAND_BASE
|
||||
li t1, 0x40a
|
||||
sw t1, 0xc(t0)
|
||||
li t1, 0x7f85100
|
||||
sw t1, 0x18(t0)
|
||||
li t1, NAND_NUM
|
||||
sw t1, 0x1c(t0)
|
||||
########################################## read_id
|
||||
li t1, 0x21
|
||||
sw t1, 0x0(t0)
|
||||
3:
|
||||
lw a1, 0x0(t0)
|
||||
and a1, a1, 0x400
|
||||
beqz a1, 3b
|
||||
nop
|
||||
########################################## reset
|
||||
li t1, 0x41
|
||||
sw t1, 0x0(t0)
|
||||
3:
|
||||
lw a1, 0x0(t0)
|
||||
and a1, a1, 0x400
|
||||
beqz a1, 3b
|
||||
nop
|
||||
########################################## erase
|
||||
li t1, 0x9
|
||||
sw t1, 0x0(t0)
|
||||
3:
|
||||
lw a1, 0x0(t0)
|
||||
and a1, a1, 0x400
|
||||
beqz a1, 3b
|
||||
nop
|
||||
|
||||
#initial memory data
|
||||
li s0, NAND_WR_MEM_BASE
|
||||
li s1, 0x11223344
|
||||
sw s1, 0x0(s0)
|
||||
li s1, 0x55667788
|
||||
sw s1, 0x4(s0)
|
||||
li s1, 0x99aabbcc
|
||||
sw s1, 0x8(s0)
|
||||
li s1, 0xddeeff00
|
||||
sw s1, 0xc(s0)
|
||||
li s1, 0x12345678
|
||||
sw s1, 0x10(s0)
|
||||
li s1, 0x9abcdef0
|
||||
sw s1, 0x14(s0)
|
||||
li s1, 0x87654321
|
||||
sw s1, 0x18(s0)
|
||||
li s1, 0x0fedcba9
|
||||
sw s1, 0x1c(s0)
|
||||
li s1, 0x5a5a5a5a
|
||||
sw s1, 0x20(s0)
|
||||
li s1, 0xa5a5a5a5
|
||||
sw s1, 0x24(s0)
|
||||
|
||||
########################################## write
|
||||
li a1, 0xa0001000
|
||||
#if 1
|
||||
li a2, 0x00001100
|
||||
sw a2, 0x0(a1) # dma_order_addr
|
||||
li a2, 0x1fe78040
|
||||
sw a2, 0x8(a1) # dma_dev_addr
|
||||
# li a2, DMA_NUM
|
||||
li a2, 10 #10 words, see initial memory data
|
||||
sw a2, 0xc(a1) # dma_length
|
||||
li a2, 0x1
|
||||
sw a2, 0x10(a1) # dma_step_length
|
||||
li a2, 0x1
|
||||
sw a2, 0x14(a1) #step times
|
||||
#endif
|
||||
|
||||
li a2, NAND_WR_MEM_BASE
|
||||
sw a2, 0x4(a1) # dma_mem_addr
|
||||
li a2, 0x00001001
|
||||
sw a2, 0x18(a1)
|
||||
li a1, 0x0001008 # which dma channel to be configured
|
||||
li a2, CONFREG_BASE
|
||||
sw a1, 0x1160(a2)
|
||||
|
||||
li t1, 40 #40 bytes
|
||||
sw t1, 0x1c(t0)
|
||||
|
||||
li t1, 0x0
|
||||
sw t1, 0x0(t0)
|
||||
li t1, NAND_WR_CMD
|
||||
sw t1, 0x0(t0)
|
||||
|
||||
4:
|
||||
lw a1, 0x0(t0)
|
||||
and a1, a1, 0x400
|
||||
beqz a1, 4b
|
||||
nop
|
||||
li a1, 0x0001010 # which dma channel to be configured
|
||||
li a2, CONFREG_BASE
|
||||
sw a1, 0x1160(a2)
|
||||
|
||||
la a0, msg_nand_test_write_end
|
||||
jal stringserial
|
||||
nop
|
||||
########################################## read
|
||||
li a1, 0xa0001000
|
||||
#if 0
|
||||
li a2, 0x00001100
|
||||
sw a2, 0x0(a1) # dma_order_addr
|
||||
li a2, 0x1fe78040
|
||||
sw a2, 0x8(a1) # dma_dev_addr
|
||||
#li a2, 0x2f
|
||||
li a2, 10 # 10 words, see initial memory data
|
||||
sw a2, 0xc(a1) # dma_length
|
||||
li a2, 0x1
|
||||
sw a2, 0x10(a1) # dma_step_length
|
||||
li a2, 0x1
|
||||
sw a2, 0x14(a1) #step times
|
||||
#endif
|
||||
|
||||
li a2, NAND_RD_MEM_BASE
|
||||
sw a2, 0x4(a1) # dma_mem_addr
|
||||
li a2, 0x00000001
|
||||
sw a2, 0x18(a1)
|
||||
li a1, 0x0001008 # which dma channel to be configured
|
||||
li a2, CONFREG_BASE
|
||||
sw a1, 0x1160(a2)
|
||||
|
||||
li t1, 0x0
|
||||
sw t1, 0x0(t0)
|
||||
li t1, NAND_RD_CMD
|
||||
sw t1, 0x0(t0)
|
||||
|
||||
5:
|
||||
lw a1, 0x0(t0)
|
||||
and a1, a1, 0x400
|
||||
beqz a1, 5b
|
||||
nop
|
||||
|
||||
li t1, 0x0
|
||||
sw t1, 0x0(t0)
|
||||
|
||||
la a0, msg_nand_test_read_end
|
||||
jal stringserial
|
||||
nop
|
||||
#############################################check
|
||||
li s0, NAND_RD_MEM_BASE
|
||||
|
||||
lw s2, 0x0(s0)
|
||||
li s1, 0x11223344
|
||||
bne s1, s2, check_err
|
||||
|
||||
lw s2, 0x4(s0)
|
||||
li s1, 0x55667788
|
||||
bne s1, s2, check_err
|
||||
|
||||
lw s2, 0x8(s0)
|
||||
li s1, 0x99aabbcc
|
||||
bne s1, s2, check_err
|
||||
|
||||
lw s2, 0xc(s0)
|
||||
li s1, 0xddeeff00
|
||||
bne s1, s2, check_err
|
||||
|
||||
lw s2, 0x10(s0)
|
||||
li s1, 0x12345678
|
||||
bne s1, s2, check_err
|
||||
|
||||
lw s2, 0x14(s0)
|
||||
li s1, 0x9abcdef0
|
||||
bne s1, s2, check_err
|
||||
|
||||
lw s2, 0x18(s0)
|
||||
li s1, 0x87654321
|
||||
bne s1, s2, check_err
|
||||
|
||||
lw s2, 0x1c(s0)
|
||||
li s1, 0x0fedcba9
|
||||
bne s1, s2, check_err
|
||||
|
||||
lw s2, 0x20(s0)
|
||||
li s1, 0x5a5a5a5a
|
||||
bne s1, s2, check_err
|
||||
|
||||
lw s2, 0x24(s0)
|
||||
li s1, 0xa5a5a5a5
|
||||
bne s1, s2, check_err
|
||||
nop
|
||||
|
||||
la a0, msg_nand_check_ok
|
||||
jal stringserial
|
||||
nop
|
||||
|
||||
b test_end
|
||||
nop
|
||||
|
||||
check_err:
|
||||
la a0, msg_nand_check_fail
|
||||
jal stringserial
|
||||
nop
|
||||
|
||||
test_end:
|
||||
la a0, msg_nand_test_end
|
||||
jal stringserial
|
||||
nop
|
||||
|
||||
move ra, k0
|
||||
jr ra
|
||||
nop
|
||||
|
||||
.end nand_test
|
||||
|
||||
|
||||
.rdata
|
||||
msg_nand_test_end:
|
||||
.asciiz "nand test end\n"
|
||||
msg_nand_test_begin:
|
||||
.asciiz "nand test beg\n"
|
||||
msg_nand_test_addr:
|
||||
.asciiz "Addr:"
|
||||
msg_nand_test_write_begin:
|
||||
.asciiz "wr go\n"
|
||||
msg_nand_test_write_end:
|
||||
.asciiz "wr end\n"
|
||||
msg_nand_test_read_begin:
|
||||
.asciiz "rd go\n"
|
||||
msg_nand_test_read_end:
|
||||
.asciiz "rd end\n"
|
||||
wait_nand_done:
|
||||
.asciiz "wait nand done \n"
|
||||
msg_nand_check_begin:
|
||||
.asciiz "check\n"
|
||||
msg_nand_check_ok:
|
||||
.asciiz "check pass\n"
|
||||
msg_nand_check_fail:
|
||||
.asciiz "check fail\n"
|
||||
hexdecarr:
|
||||
.asciiz "0123456789abcdef"
|
154
resources/soc/simu/soft/func/source/Calendar.c
Normal file
154
resources/soc/simu/soft/func/source/Calendar.c
Normal file
@ -0,0 +1,154 @@
|
||||
/**********************************************************************************************************************************************************************
|
||||
This file uses timer to supply a calendar funciton.
|
||||
**********************************************************************************************************************************************************************/
|
||||
|
||||
#include "../config.h"
|
||||
|
||||
#if CALENDAR_MODULE
|
||||
static void DateLowV(struct Date_Time *Date_and_Time)
|
||||
{
|
||||
switch(Date_and_Time->Day){
|
||||
case 7:
|
||||
case 14:
|
||||
case 21:
|
||||
case 28:
|
||||
if(Date_and_Time->Hour == 3)
|
||||
{
|
||||
main_flag |= test_bit;
|
||||
main_flag |= lowV2_bit;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void AddDay(struct Date_Time *Date_and_Time)
|
||||
{
|
||||
Date_and_Time->Day +=1;
|
||||
Date_and_Time->Hour =0;
|
||||
}
|
||||
|
||||
static void AddMonth(struct Date_Time *Date_and_Time)
|
||||
{
|
||||
Date_and_Time->Month +=1;
|
||||
Date_and_Time->Day =1; //注意,每月第一天是'1',不是'0'
|
||||
Date_and_Time->Hour =0;
|
||||
if(main_flag & month_flag) main_flag |= month_bit; //默认数据月结时间为每月月底
|
||||
}
|
||||
|
||||
static void AddYear(struct Date_Time *Date_and_Time)
|
||||
{
|
||||
Date_and_Time->Year +=1;
|
||||
Date_and_Time->Month =1; //注意
|
||||
Date_and_Time->Day =1; //注意
|
||||
Date_and_Time->Hour =0;
|
||||
if(main_flag & month_flag) main_flag |= month_bit; //默认数据月结时间为每月月底
|
||||
}
|
||||
|
||||
//void calendar(struct Date_Time *Date_and_Time, unsigned short lcdmode)
|
||||
void calendar(struct Date_Time *Date_and_Time)
|
||||
{
|
||||
#if CALENDAR_TEST
|
||||
printf("calendar()...\n");
|
||||
#endif
|
||||
//if(lcdmode == A2_1 || lcdmode == A2_2) //once per second
|
||||
if(1)
|
||||
{
|
||||
Date_and_Time->Second +=1;
|
||||
if(Date_and_Time->Second == 60){
|
||||
Date_and_Time->Minute += 1;
|
||||
Date_and_Time->Second = 0;
|
||||
}
|
||||
if(Date_and_Time->Minute == 60){
|
||||
Date_and_Time->Hour += 1;
|
||||
Date_and_Time->Minute =0;
|
||||
}
|
||||
}
|
||||
else //cpu will sleep less than a day in most.
|
||||
{
|
||||
static _u32 last_count;
|
||||
_u32 count, sleep_time;
|
||||
count = *(volatile _u32 *)0xbfeb001c;
|
||||
count &= COUNT_MASK;
|
||||
sleep_time = (count - last_count)%COUNT_COMPARE;
|
||||
_u32 i;
|
||||
for(i=0;i<(sleep_time/57600);i++) //57600=3600*16, one hour
|
||||
Date_and_Time->Hour += 1;
|
||||
for(i=0;i<((sleep_time%57600)/960);i++) //960=60*16, one minute
|
||||
Date_and_Time->Minute += 1;
|
||||
for(i=0;i<((sleep_time%960)/16);i++)
|
||||
Date_and_Time->Second += 1;
|
||||
last_count = count - (count%16); //This is a good write! Read the last 6 lines to understand it.
|
||||
if(Date_and_Time->Second >= 60)
|
||||
{
|
||||
Date_and_Time->Minute += 1;
|
||||
Date_and_Time->Second %= 60;
|
||||
}
|
||||
if(Date_and_Time->Minute >= 60)
|
||||
{
|
||||
Date_and_Time->Hour += 1;
|
||||
Date_and_Time->Minute %= 60;
|
||||
}
|
||||
}
|
||||
|
||||
if(Date_and_Time->Hour >= 24)
|
||||
{
|
||||
/*闰年*/
|
||||
if((Date_and_Time->Year%400==0)||((Date_and_Time->Year%4 ==0)&&(Date_and_Time->Year%100 !=0))){
|
||||
switch(Date_and_Time->Day){
|
||||
case 29:
|
||||
if(Date_and_Time->Month == 2) AddMonth(Date_and_Time);
|
||||
else AddDay(Date_and_Time);
|
||||
break;
|
||||
case 30:
|
||||
if((Date_and_Time->Month ==4)||(Date_and_Time->Month ==6)||(Date_and_Time->Month ==9)||(Date_and_Time->Month ==11))
|
||||
AddMonth(Date_and_Time);
|
||||
else AddDay(Date_and_Time);
|
||||
break;
|
||||
case 31:
|
||||
if(Date_and_Time->Month == 12) AddYear(Date_and_Time);
|
||||
else AddMonth(Date_and_Time);
|
||||
break;
|
||||
default:
|
||||
AddDay(Date_and_Time);
|
||||
break;
|
||||
}
|
||||
}
|
||||
else{
|
||||
switch(Date_and_Time->Day){
|
||||
case 28:
|
||||
if(Date_and_Time->Month == 2) AddMonth(Date_and_Time);
|
||||
else AddDay(Date_and_Time);
|
||||
break;
|
||||
case 30:
|
||||
if((Date_and_Time->Month ==4)||(Date_and_Time->Month ==6)||(Date_and_Time->Month ==9)||(Date_and_Time->Month ==11))
|
||||
AddMonth(Date_and_Time);
|
||||
else AddDay(Date_and_Time);
|
||||
break;
|
||||
case 31:
|
||||
if(Date_and_Time->Month == 12) AddYear(Date_and_Time);
|
||||
else AddMonth(Date_and_Time);
|
||||
break;
|
||||
default:
|
||||
AddDay(Date_and_Time);
|
||||
break;
|
||||
}
|
||||
}
|
||||
Date_and_Time->Hour %= 24;
|
||||
}
|
||||
|
||||
DateLowV(Date_and_Time);
|
||||
}
|
||||
|
||||
void DateInit(struct Date_Time *Date_and_Time)
|
||||
{
|
||||
Date_and_Time->Year = 2012;
|
||||
Date_and_Time->Month = 1;
|
||||
Date_and_Time->Day = 31;
|
||||
Date_and_Time->Hour = 23;
|
||||
Date_and_Time->Minute = 40; //59;
|
||||
Date_and_Time->Second = 15; //45;
|
||||
main_flag |= month_flag;
|
||||
}
|
||||
#endif
|
33
resources/soc/simu/soft/func/source/Infrare.c
Normal file
33
resources/soc/simu/soft/func/source/Infrare.c
Normal file
@ -0,0 +1,33 @@
|
||||
/**********************************************************************************************************************************************************************
|
||||
This file enables the Infrare receiver to receive signals.
|
||||
**********************************************************************************************************************************************************************/
|
||||
|
||||
#include "../config.h"
|
||||
|
||||
#if INFRARE_MODULE
|
||||
void Infrare()
|
||||
{
|
||||
if((main_flag & wait_8sec)==0){
|
||||
if(main_flag & infrare_flag) //红外处于打开状态
|
||||
{
|
||||
PMU_GPIO_O &= 0xfffffff7; //IR_PWR OFF
|
||||
//rUart1_MCR &= ~0xa0; //MCR bit7: 靠靠; bit6:Rx靠 bit5:Tx靠靠
|
||||
main_flag &= ~infrare_flag;
|
||||
}
|
||||
else //红外处于关闭状态
|
||||
{
|
||||
main_flag |= infrare_flag;
|
||||
PMU_GPIO_OE |= 1 << 3; //靠靠IO 靠
|
||||
PMU_GPIO_O |= 1 << 3; //IR 靠
|
||||
RX_IndexW = 0;
|
||||
#if UART1_INT
|
||||
Uart1_IER |= 0x1; //enable uart1 rx int
|
||||
#endif
|
||||
|
||||
wait[1] = 0;
|
||||
main_flag |= wait_8sec;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
6
resources/soc/simu/soft/func/source/Interrupt.c
Normal file
6
resources/soc/simu/soft/func/source/Interrupt.c
Normal file
@ -0,0 +1,6 @@
|
||||
/**********************************************************************************************************************************************************************
|
||||
This file processes all kinds of interrupt, some parts are placed in start.S.
|
||||
**********************************************************************************************************************************************************************/
|
||||
|
||||
#include "../config.h"
|
||||
|
62
resources/soc/simu/soft/func/source/MonthData.c
Normal file
62
resources/soc/simu/soft/func/source/MonthData.c
Normal file
@ -0,0 +1,62 @@
|
||||
/**********************************************************************************************************************************************************************
|
||||
This file writes the info flash when MonthDate comes.
|
||||
It should need four step to write flash:
|
||||
1) clear page_latch
|
||||
2) write data into page_latch
|
||||
3) clear the flash page
|
||||
4) write the flash page
|
||||
*page_latch just like a buffer.
|
||||
**********************************************************************************************************************************************************************/
|
||||
|
||||
#include "../config.h"
|
||||
|
||||
_u32 Last_month_num; //0~17
|
||||
#if MONTHDATA_MODULE
|
||||
struct Record_1 Latest_Record;
|
||||
|
||||
void Flash_Read_Info()
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
void MonthData(struct Date_Time *Date_and_Time, struct Data *Lcd_data) //flashÖÐÊý¾Ý±£´æ¸ñʽΪBCDÂë
|
||||
{
|
||||
#if MONTHDATA_TEST
|
||||
printf("%s()...\n", __FUNCTION__);
|
||||
#endif
|
||||
struct Record_0 Month_Record;
|
||||
if(Date_and_Time->Month == 1)
|
||||
{
|
||||
Month_Record.Date = (Date_and_Time->Year-1)*1000 + 12*10; //store in _u32 format
|
||||
}
|
||||
else
|
||||
{
|
||||
Month_Record.Date = Date_and_Time->Year*1000 + (Date_and_Time->Month-1)*10; //store in _u32 format
|
||||
} //eg: 20110120
|
||||
|
||||
Month_Record.TotalHeat = (_u32)(Lcd_data->total_heat)*100/LCD_MULTIPLE;
|
||||
Month_Record.TotalFlow = (_u32)(Lcd_data->total_flow)*100/LCD_MULTIPLE;
|
||||
|
||||
//write flash
|
||||
Last_month_num++;
|
||||
Last_month_num %= 18;
|
||||
|
||||
_u32 addr, err=1;
|
||||
addr = INFO_FLASH_START + Last_month_num*12 ;
|
||||
err = Flash_Write( addr, &Month_Record, 3) ;
|
||||
|
||||
BUG_ON(err)
|
||||
|
||||
}
|
||||
|
||||
void Flash_Write_Test()
|
||||
{
|
||||
_u32 data[4];
|
||||
_u32 i,addr;
|
||||
for(i=0;i<4;i++)
|
||||
data[i] = i;
|
||||
addr = 0xbfc0f004;
|
||||
Flash_Write(addr, data, 4) ;
|
||||
|
||||
}
|
||||
#endif
|
118
resources/soc/simu/soft/func/source/SystemInit.c
Normal file
118
resources/soc/simu/soft/func/source/SystemInit.c
Normal file
@ -0,0 +1,118 @@
|
||||
/**********************************************************************************************************************************************************************
|
||||
This file inits some module in LS1D chip.
|
||||
**********************************************************************************************************************************************************************/
|
||||
|
||||
#include "../config.h"
|
||||
#include "../include/asm/ns16550.h"
|
||||
|
||||
void Uart0_Init()
|
||||
{
|
||||
/*
|
||||
8bit 1stop 38400Baut
|
||||
*/
|
||||
#if 1
|
||||
Uart0_FCR = FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_4;
|
||||
Uart0_LCR = CFCR_DLAB;
|
||||
Uart0_FCR = 0xCF;
|
||||
Uart0_BaudL = 0x23; //set 57600Baut
|
||||
Uart0_LCR = CFCR_8BITS; //8bit, 1stop
|
||||
Uart0_MCR = MCR_DTR|MCR_RTS;
|
||||
Uart0_IER = 0;
|
||||
#endif
|
||||
/*the uart0 rx default state is high, it can work when egde_low or no_egde_low.*/
|
||||
#if 0
|
||||
INT_EGDE |= 0x08; //egde change available
|
||||
INT_POL |= 0x08; //low available
|
||||
//INT_POL &= ~0x08; //high available
|
||||
Uart0_IER |= 0x01; //enable uart0 rx int
|
||||
INT_EN |= 0x08; //enable uart0 int
|
||||
#endif
|
||||
|
||||
#if PRINT
|
||||
printf("Uart0 init...\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
static void Uart1_Init(void)
|
||||
{
|
||||
/*
|
||||
8bit 1stop 2400Baut odd parity
|
||||
*/
|
||||
#if 0
|
||||
__asm__ volatile(
|
||||
"lui $2,0xbfe8;\n" \
|
||||
"ori $2,$2,0x8000;\n" \
|
||||
"li $3,7;\n" \
|
||||
"sb $3,2($2);\n" \
|
||||
"li $3,-128;\n" \
|
||||
"sb $3,3($2);\n" \
|
||||
"li $3,-48;\n" \
|
||||
"sb $3,0($2);\n" \
|
||||
"li $3,11;\n" \
|
||||
"sb $3,3($2);\n" \
|
||||
"li $3,3;\n" \
|
||||
"sb $3,4($2);\n" \
|
||||
"li $3,0;\n" \
|
||||
"sb $3,1($2);\n" \
|
||||
:::"$2","$3"
|
||||
);
|
||||
#else
|
||||
Uart1_FCR = FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_1;
|
||||
Uart1_LCR = CFCR_DLAB;
|
||||
Uart1_BaudL = 208; //set 2400Baut
|
||||
Uart1_LCR = CFCR_8BITS|CFCR_PENAB|CFCR_PODD; //8bit, 1stop, odd parity
|
||||
Uart1_MCR = MCR_DTR|MCR_RTS;
|
||||
Uart1_IER = 0;
|
||||
#endif
|
||||
|
||||
/*the uart1 rx default state is low, when IR_PWR is off; only can it work when no_egde_low.*/
|
||||
//INT_EGDE |= 0x04; //egde change available
|
||||
//INT_CLR = 0x3f; //clear all int bit
|
||||
//INT_POL &= ~0x04; //high available
|
||||
INT_POL |= 0x04; //low available
|
||||
INT_EN |= 0x04; //enable uart1 int
|
||||
|
||||
#if PRINT
|
||||
printf("Uart1 init...\n");
|
||||
#endif
|
||||
|
||||
#if !(UART1_INT)
|
||||
_u8 data;
|
||||
data = Uart1_RxData; //clear the receive fifo
|
||||
Uart1_IER |= 0x01; //enable uart1 rx int
|
||||
#endif
|
||||
}
|
||||
|
||||
static void ReLoad() //上电恢复,从掉电保存位置读取数据,重新赋值给变量
|
||||
{
|
||||
#if 0
|
||||
DateInit();
|
||||
#endif
|
||||
|
||||
//Monthdata.h
|
||||
//temp_flow.h
|
||||
//Last_total_flow =
|
||||
}
|
||||
|
||||
void SystemInit()
|
||||
{
|
||||
//DisableWatchDog();
|
||||
/*
|
||||
enable BT\UART\KEY\BAT_FAIL Interrupt
|
||||
*/
|
||||
// Interrupt_Init();
|
||||
|
||||
//Uart0_Init();
|
||||
#if (INFRARE_MODULE|FRAME_MODULE)
|
||||
Uart1_Init();
|
||||
#endif
|
||||
ReLoad();
|
||||
#if (TDC_TEMP_MODULE|TDC_FLOW_MODULE)
|
||||
InitTdc();
|
||||
#endif
|
||||
#if AD_MODULE
|
||||
ADC_Init();
|
||||
#endif
|
||||
|
||||
}
|
||||
|
49
resources/soc/simu/soft/func/source/adc.c
Normal file
49
resources/soc/simu/soft/func/source/adc.c
Normal file
@ -0,0 +1,49 @@
|
||||
#include "../config.h"
|
||||
|
||||
/****************************
|
||||
*ADC* base addr : 0xbfea8000
|
||||
cr offset : 0x0
|
||||
datalow offset : 0x1 (result[3:0] in D0[7:4])
|
||||
datahigh offset : 0x2 (result[11:4] in D1[7:0])
|
||||
*cr* [8] : start
|
||||
[7] : standby (RO)
|
||||
[2:0] : select
|
||||
select=0: adci_a (battery voltage 3~3.7V )
|
||||
select=1: ldo output (core voltage 1.8V )
|
||||
|
||||
Liu Su
|
||||
liusu-cpu@ict.ac.cn
|
||||
****************************/
|
||||
|
||||
#if ADC_MODULE
|
||||
|
||||
#define adc_start 0x80
|
||||
#define adc_standby 0x40
|
||||
|
||||
static _u32 ADC_measure(_u8 adc_sel)
|
||||
{
|
||||
ADC_CR = adc_start | adc_sel;
|
||||
while (ADC_CR & adc_standby != adc_standby) {}
|
||||
return (ADC_D1 << 8 + ADC_D0) >> 4;
|
||||
}
|
||||
|
||||
float BatteryMeasure(void)
|
||||
{
|
||||
float BatteryVoltage;
|
||||
_u32 result_battery, result_core;
|
||||
|
||||
result_core = ADC_measure(0);
|
||||
result_battery = ADC_measure(1);
|
||||
|
||||
BatteryVoltage = 1.8 * result_battery / result_core;
|
||||
//printf("Battery Voltage : %f V\n", BatteryVoltage);
|
||||
return BatteryVoltage;
|
||||
}
|
||||
|
||||
#endif // ADC_MODULE
|
||||
int ADC_test(int argc, char argv[][30])
|
||||
{
|
||||
printf("\nin ADC_test");
|
||||
return 0;
|
||||
}
|
||||
|
148
resources/soc/simu/soft/func/source/battery.c
Normal file
148
resources/soc/simu/soft/func/source/battery.c
Normal file
@ -0,0 +1,148 @@
|
||||
/**********************************************************************************************************************************************************************
|
||||
This file uses ADC module to detect and measure the voltage of battery.
|
||||
**********************************************************************************************************************************************************************/
|
||||
|
||||
#include "../config.h"
|
||||
|
||||
#if AD_MODULE
|
||||
void ADC_Init(void)
|
||||
{
|
||||
IIC_PRER_L = 0x64; //Baud rate= 8M/4/PRER
|
||||
IIC_PRER_H = 0x0;
|
||||
IIC_CTR = 0xa0; //CTR[7]:core_en [6]:int_en [5]:master:1 slave:0 [4]:txr_ok [3]:rxr_ok bit[4,3] use in slave mode
|
||||
|
||||
IIC_TXR = 0x6c; //slave addr + w
|
||||
IIC_CR = 0x90; //start and write
|
||||
while( (IIC_SR & 0x83) != 0x01 );
|
||||
IIC_CR = 0x01;
|
||||
|
||||
IIC_TXR = 0x63; // max11645 config byte converte channel AN1 ,single ended
|
||||
IIC_CR = 0x50; //send congig byte and stop
|
||||
while( (IIC_SR & 0x83) != 0x01 );
|
||||
IIC_CR = 0x01;
|
||||
|
||||
#if AD_TEST
|
||||
printf("AD module initted...\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
static _u32 ADC() //power_detect
|
||||
{
|
||||
_u32 sum = 0;
|
||||
_u32 tmp = 0;
|
||||
_u32 i;
|
||||
for( i = 0; i < 8; i++)
|
||||
{
|
||||
IIC_TXR = 0x6c; //slave addr + w
|
||||
IIC_CR = 0x90; //start and write
|
||||
while( (IIC_SR & 0x83) != 0x01 );
|
||||
IIC_CR = 0x01;
|
||||
|
||||
//IIC_TXR = 0xd2; //max11645 setup byte Vref = 2.048 (internal Vref), if use external Vref :a2
|
||||
IIC_TXR = 0xa2; //max11645 setup byte Vref = 2.048 (internal Vref), if use external Vref :a2
|
||||
IIC_CR = 0x50; //tx and stop
|
||||
while( (IIC_SR & 0x83) != 0x01 );
|
||||
IIC_CR = 0x01;
|
||||
|
||||
/************ read *********************/
|
||||
IIC_TXR = 0x6d; //slave addr + r
|
||||
IIC_CR = 0x90;
|
||||
while( (IIC_SR & 0x83) != 0x01 );
|
||||
IIC_CR = 0x01;
|
||||
|
||||
IIC_CR = 0x20; //read
|
||||
while( (IIC_SR & 0x83) != 0x01 );
|
||||
IIC_CR = 0x01;
|
||||
tmp = IIC_RXR & 0x0f;
|
||||
|
||||
IIC_CR = 0x60; //read & stop
|
||||
while( (IIC_SR & 0x83) != 0x01 );
|
||||
IIC_CR = 0x01;
|
||||
|
||||
tmp = tmp << 8;
|
||||
tmp |= IIC_RXR & 0xff;
|
||||
sum += tmp;
|
||||
}
|
||||
return (sum >> 3);
|
||||
}
|
||||
|
||||
void BatteryTest1()
|
||||
{
|
||||
_u32 i;
|
||||
_fp32 V_BAT;
|
||||
|
||||
i = ADC();
|
||||
V_BAT = 4096*1.8f/i ;
|
||||
#if AD_TEST
|
||||
printf("---------------------------------------------------Battery: 0x%x------------", i);
|
||||
printf_float(V_BAT);
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
if(main_flag & wait_10sec){ //放电测电压
|
||||
if((main_flag & lowV_flag) == 0) //当前为正常状态
|
||||
{
|
||||
if(i<0x0900) //检测为低电压
|
||||
{
|
||||
if(main_flag & wait_oneday) //第二次放电
|
||||
{
|
||||
main_flag |= lowV_flag;
|
||||
main_flag |= lcd_bit;
|
||||
}
|
||||
else //第一次放电
|
||||
{
|
||||
wait[6] = 0;
|
||||
main_flag |= wait_oneday;
|
||||
}
|
||||
}
|
||||
else //检测为正常
|
||||
{
|
||||
}
|
||||
}
|
||||
else //当前已经为低电压状态 或者//延迟一天 第二次放电
|
||||
{
|
||||
if(i>0x0b00){
|
||||
main_flag &= ~lowV_flag;
|
||||
main_flag |= lcd_bit;
|
||||
}
|
||||
}
|
||||
}
|
||||
else //不放电测电压
|
||||
{
|
||||
static unsigned short m;
|
||||
if((main_flag & lowV_flag) == 0) //当前为正常状态
|
||||
{
|
||||
if(i<0x0aaa){
|
||||
main_flag |= lowV_flag;
|
||||
main_flag |= lcd_bit;
|
||||
}
|
||||
}
|
||||
else //当前已经为低电压状态
|
||||
{
|
||||
if(i>0x0b00){
|
||||
if(m==0)
|
||||
{
|
||||
wait[4] = 0;
|
||||
main_flag |= wait_16min;
|
||||
}
|
||||
m = 1;
|
||||
}
|
||||
else m = 0;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
//P3DIR &= ~0x10;
|
||||
}
|
||||
|
||||
void BatteryTest2() //放电
|
||||
{
|
||||
//电池放电
|
||||
#if 0
|
||||
P3DIR |=0x20;
|
||||
P3OUT |=0x20;
|
||||
#endif
|
||||
wait[5] = 0;
|
||||
main_flag |= wait_10sec;
|
||||
}
|
||||
#endif
|
326
resources/soc/simu/soft/func/source/cmdline.c
Normal file
326
resources/soc/simu/soft/func/source/cmdline.c
Normal file
@ -0,0 +1,326 @@
|
||||
#include "../config.h"
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
#define write_u32(addr,value) (*(volatile _u32*)(addr) = (value))
|
||||
#define read_u32(addr) (*(volatile _u32*)(addr))
|
||||
|
||||
#define LS1D
|
||||
int help(int argc, char argv[][30]);
|
||||
int m4(int argc, char argv[][30]);
|
||||
int m1(int argc, char argv[][30]);
|
||||
int d4(int argc, char argv[][30]);
|
||||
int d1(int argc, char argv[][30]);
|
||||
int float_test(int argc, char argv[][30]);
|
||||
|
||||
|
||||
unsigned int str2num(char str[30]);
|
||||
char cmdpara[10][30];
|
||||
char **pp;
|
||||
static _u8 mygetchar();
|
||||
static void myputchar(_u8 chr);
|
||||
struct cmd_struc {
|
||||
const char *cmdname;
|
||||
int (*func) __P((int, char *[]));
|
||||
} cmd[] = {{"exit", NULL},
|
||||
{"help", help},
|
||||
{"m4", m4},
|
||||
{"m1", m1},
|
||||
{"d4", d4},
|
||||
{"d1", d1},
|
||||
{"", NULL}
|
||||
};
|
||||
|
||||
int float_test(int argc, char argv[][30])
|
||||
{
|
||||
unsigned int a,b;
|
||||
float i,j,k,l,m;
|
||||
a = 3000;
|
||||
b = 4096;
|
||||
k = (float)a/(float)b;
|
||||
i = 2.0;
|
||||
j = 3.3;
|
||||
l = 0.99;
|
||||
m = 1.01;
|
||||
i = i/j;
|
||||
l = l/m;
|
||||
k = i/l;
|
||||
if(k>0.99 && k<1.01) a++;
|
||||
else a--;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static void myputchar(_u8 chr)
|
||||
{
|
||||
while(!(Uart0_LSR & 0x20)) ;
|
||||
Uart0_TxData = chr;
|
||||
}
|
||||
|
||||
static _u8 mygetchar()
|
||||
{
|
||||
_u8 chr;
|
||||
// int i=0,j;
|
||||
// while(1) {if(Uart0_LSR & 0x1) break;else
|
||||
// for(i=0;i<100;i++) {j=*(volatile _u32*)(0xbe000000);}}
|
||||
while(!(Uart0_LSR & 0x1)) ;
|
||||
chr = Uart0_RxData ;
|
||||
// printf("f");
|
||||
// printf("%d",chr);
|
||||
return chr;
|
||||
}
|
||||
|
||||
int help(int argc, char argv[][30])
|
||||
{
|
||||
int i;
|
||||
printf("\ncommands:\n");
|
||||
for(i=1;i<100;i++)
|
||||
{
|
||||
if(strcmp(cmd[i].cmdname,"")==0) break;
|
||||
else printf(" %s",cmd[i].cmdname);
|
||||
}
|
||||
// printf("\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned int str2num(char str[30])
|
||||
{
|
||||
int value = 0;
|
||||
int sign = 1;
|
||||
int radix;
|
||||
|
||||
if(*str == '-')
|
||||
{
|
||||
sign = -1;
|
||||
str++;
|
||||
}
|
||||
if(*str == '0' && (*(str+1) == 'x' || *(str+1) == 'X'))
|
||||
{
|
||||
radix = 16;
|
||||
str += 2;
|
||||
}
|
||||
else if(*str == '0') // 八进制首字符为0
|
||||
{
|
||||
radix = 8;
|
||||
str++;
|
||||
}
|
||||
else
|
||||
radix = 10;
|
||||
while(*str)
|
||||
{
|
||||
if(radix == 16)
|
||||
{
|
||||
if(*str >= '0' && *str <= '9')
|
||||
value = value * radix + *str - '0';
|
||||
else
|
||||
value = value * radix + (*str | 0x20) - 'a' + 10;
|
||||
// value = value * radix + *str - 'a' + 10; // 也没问题啊
|
||||
}
|
||||
else
|
||||
value = value * radix + *str - '0';
|
||||
str++;
|
||||
}
|
||||
return (unsigned int *)(sign*value);
|
||||
}
|
||||
|
||||
int m4(int argc, char argv[][30])
|
||||
{
|
||||
unsigned int addr,value;
|
||||
// printf("%s\n",argv[1]);
|
||||
if(argc != 3)
|
||||
{
|
||||
printf("\nusage: m4 <addr> <value>");
|
||||
return 1;
|
||||
}
|
||||
addr=str2num(argv[1]);
|
||||
value=str2num(argv[2]);
|
||||
#ifdef LS1D
|
||||
*(volatile unsigned int*)(addr) = value;
|
||||
#else
|
||||
printf("addr: %x ,value: %x\n",addr,value);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int m1(int argc, char argv[][30])
|
||||
{
|
||||
unsigned int addr,value;
|
||||
// printf("%s\n",argv[1]);
|
||||
if(argc != 3)
|
||||
{
|
||||
printf("\nusage: m1 <addr> <value>");
|
||||
return 1;
|
||||
}
|
||||
addr=str2num(argv[1]);
|
||||
value=str2num(argv[2]);
|
||||
#ifdef LS1D
|
||||
*(volatile unsigned char*)(addr) = value;
|
||||
#else
|
||||
printf("addr: %x ,value: %x\n",addr,value);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int d4(int argc, char argv[][30])
|
||||
{
|
||||
unsigned int addr;
|
||||
if(argc != 2)
|
||||
{
|
||||
printf("\nusage: d4 <addr>");
|
||||
return 1;
|
||||
}
|
||||
addr=str2num(argv[1]);
|
||||
#ifdef LS1D
|
||||
printf("\n0x%08x: %08x",addr,*(volatile unsigned int*)(addr));
|
||||
#else
|
||||
printf("0x%08x:\n",addr);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int d1(int argc, char argv[][30])
|
||||
{
|
||||
unsigned int addr;
|
||||
if(argc != 2)
|
||||
{
|
||||
printf("\nusage: d1 <addr>");
|
||||
return 1;
|
||||
}
|
||||
addr=str2num(argv[1]);
|
||||
#ifdef LS1D
|
||||
printf("\n0x%08x: %02x",addr,*(volatile unsigned char*)(addr));
|
||||
#else
|
||||
printf("0x%08x:\n",addr);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int cmdline(void)
|
||||
{
|
||||
char c;
|
||||
char cmdbuffer[40];
|
||||
char *cbuffer;
|
||||
short ccc,cpc,cbc,i,j;
|
||||
int count=0;
|
||||
// int (*func) (int , char **);
|
||||
int (*op)(int argc,char **argv);
|
||||
i=0;
|
||||
j=0;
|
||||
ccc=0;
|
||||
cpc=0;
|
||||
printf("This is the 1st test!\n");
|
||||
printf("This is the 2nd test!\n");
|
||||
// printf("This is the 3rd test!\n");
|
||||
// printf("This is the 4th test!\n");
|
||||
// printf("This is the 5th test!\n");
|
||||
// test mult
|
||||
int opa = 1;
|
||||
int opb = 2;
|
||||
int result1 = opa * opb;
|
||||
int result10 = 1 * 2;
|
||||
int result2 = (opa+1) * (opb+4);
|
||||
int result20 = 2 * 6;
|
||||
int result3 = (opa+299) * (opb+298);
|
||||
int result30 = 300 * 300;
|
||||
printf("result: %d %d\n", result1, result10);
|
||||
printf("result: %d %d\n", result2, result20);
|
||||
printf("result: %d %d\n", result3, result30);
|
||||
while(1){}
|
||||
while(1)
|
||||
{
|
||||
for(i=0;i<10;i++)
|
||||
for(j=0;j<30;j++)
|
||||
cmdpara[i][j] = '\0';
|
||||
for(i=0;i<40;i++) cmdbuffer[i]= '\0';
|
||||
// printf("\n$ ");
|
||||
cbuffer = cmdpara[0];
|
||||
// printf("@ ");
|
||||
ccc=0;
|
||||
// printf("@ ");
|
||||
cpc=0;
|
||||
// printf("@ ");
|
||||
cbc=0;
|
||||
// printf("@ ");
|
||||
count++;
|
||||
// for(i=0;i<1000;i++) i++;
|
||||
printf("\nS ");
|
||||
// for(i=0;i<500;i++) j=Uart0_LSR;
|
||||
// printf("%4d ",count);
|
||||
// i=1;
|
||||
// while(i++) {printf("\n%4d",i);j++;}
|
||||
// internal loop
|
||||
while(1)
|
||||
{
|
||||
// printf("|\n");
|
||||
c=mygetchar();
|
||||
// printf("%d\n",c);
|
||||
// printf("/");
|
||||
// c=13;
|
||||
// c=53;
|
||||
if(c==8)
|
||||
{
|
||||
cbc=cbc-1;
|
||||
cmdbuffer[cbc] = '\0';
|
||||
myputchar(8);myputchar(32);myputchar(8);
|
||||
}
|
||||
else
|
||||
{
|
||||
cmdbuffer[cbc++] = c;
|
||||
myputchar(c);
|
||||
}
|
||||
// printf("\r%s",cmdbuffer);
|
||||
if(c==10 || c==13) break;
|
||||
}
|
||||
for(i=0;i<cbc;i++){
|
||||
c=cmdbuffer[i];
|
||||
if(c==10 || c==13)
|
||||
{
|
||||
*(cbuffer + ccc) = '\0';
|
||||
break;
|
||||
}
|
||||
else
|
||||
if(c==' ')
|
||||
{
|
||||
*(cbuffer + ccc) = '\0';
|
||||
if(ccc) cpc++;
|
||||
// printf("cpc:%d\n",cpc);
|
||||
cbuffer = cmdpara[cpc];
|
||||
ccc=0;
|
||||
}
|
||||
else
|
||||
{
|
||||
*(cbuffer + ccc) = c;
|
||||
ccc++;
|
||||
}
|
||||
}
|
||||
// cmd decode
|
||||
cbuffer = cmdpara[0];
|
||||
// pp = cmdpara;
|
||||
//for (i=0;i<10;i++)
|
||||
// *pp++ = cmdpara[i];
|
||||
if(strcmp(cbuffer, cmd[0].cmdname)==0) break;
|
||||
else
|
||||
for(i=1;i<100;i++)
|
||||
{
|
||||
if(strcmp(cmd[i].cmdname,"")==0) break;
|
||||
if(strcmp(cbuffer, cmd[i].cmdname)!=0) continue;
|
||||
// printf("match func: %s\n",cmd[i].cmdname);
|
||||
|
||||
op= cmd[i].func;
|
||||
op(cpc+1,cmdpara);
|
||||
// printf("%x",aaa);
|
||||
// printf("1 ");
|
||||
// func = aaa;
|
||||
// printf("%x",func);
|
||||
// j=func(cpc,cmdpara);
|
||||
// printf("%d\n",j);
|
||||
}
|
||||
// printf("argc: %d\n",cpc);
|
||||
// for(i=0; i<10; i++)
|
||||
// if(cmdpara[i][0]=='\0') break;
|
||||
// else printf("argv[%d]: %s\n",i,cmdpara[i]);
|
||||
}
|
||||
return 0;
|
||||
}
|
125
resources/soc/simu/soft/func/source/common.c
Normal file
125
resources/soc/simu/soft/func/source/common.c
Normal file
@ -0,0 +1,125 @@
|
||||
/**********************************************************************************************************************************************************************
|
||||
This file supplies some public function.
|
||||
**********************************************************************************************************************************************************************/
|
||||
|
||||
#include "../config.h"
|
||||
|
||||
_fp32 bubble_sort(_fp32 *delta, _s32 len)
|
||||
{
|
||||
_s32 i, j;
|
||||
_fp32 tmp, sum, average, tmp_print;
|
||||
tmp = sum = average = 0;
|
||||
#if 0 //PRINT
|
||||
for(i = 0; i < len; i++)
|
||||
{
|
||||
//printf("%f ", delta[i]);
|
||||
if(delta[i] < 0)
|
||||
{
|
||||
tmp_print = 0 - delta[i];
|
||||
printf("-%d ", (unsigned int)(tmp_print*1000));
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp_print = delta[i];
|
||||
printf("%d ", (unsigned int)(tmp_print*1000));
|
||||
}
|
||||
if(i == len-1) printf("\r\n");
|
||||
}
|
||||
#endif
|
||||
for(i = len; i > 0; i--)
|
||||
{
|
||||
for(j = 0; j < (i - 1); j++)
|
||||
{
|
||||
if(delta[j] > delta[j+1])
|
||||
{
|
||||
tmp = delta[j];
|
||||
delta[j] = delta[j+1];
|
||||
delta[j+1] = tmp;
|
||||
}
|
||||
}
|
||||
}
|
||||
#if 0 //PRINT
|
||||
for(i = 0; i < len; i++)
|
||||
{
|
||||
//printf("%f ", delta[i]);
|
||||
if(delta[i] < 0)
|
||||
{
|
||||
tmp_print = 0 - delta[i];
|
||||
printf("-%d ", (unsigned int)(tmp_print*1000));
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp_print = delta[i];
|
||||
printf("%d ", (unsigned int)(tmp_print*1000));
|
||||
}
|
||||
if(i == len-1) printf("\r\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
for(i = 1; i < len - 1; i++)
|
||||
{
|
||||
sum += delta[i];
|
||||
}
|
||||
average = sum/(len -2);
|
||||
return average;
|
||||
}
|
||||
|
||||
void UintToBcd(_u32 dat, _u8 *bcd_buf)
|
||||
{
|
||||
//_u32 tmp = dat;
|
||||
|
||||
//if(dat>=100000000) dat=dat%100000000 ;
|
||||
dat = dat%100000000 ;
|
||||
bcd_buf[3] = dat/10000000 ;
|
||||
bcd_buf[3] <<= 4 ;
|
||||
dat = dat%10000000 ;
|
||||
bcd_buf[3] |= (dat/1000000) ;
|
||||
|
||||
dat = dat%1000000 ;
|
||||
bcd_buf[2] = dat/100000 ;
|
||||
bcd_buf[2] <<= 4 ;
|
||||
dat = dat%100000 ;
|
||||
bcd_buf[2] |= (dat/10000) ;
|
||||
|
||||
dat = dat%10000 ;
|
||||
bcd_buf[1] = dat/1000 ;
|
||||
bcd_buf[1] <<= 4 ;
|
||||
dat = dat%1000 ;
|
||||
bcd_buf[1] |= (dat/100) ;
|
||||
|
||||
dat = dat%100 ;
|
||||
bcd_buf[0] = dat/10 ;
|
||||
bcd_buf[0] <<= 4 ;
|
||||
dat = dat%10 ;
|
||||
bcd_buf[0] |= dat ;
|
||||
|
||||
//printf("***: %d\t***BCD:%x %x %x %x\n", tmp, bcd_buf[3], bcd_buf[2], bcd_buf[1], bcd_buf[0]);
|
||||
}
|
||||
|
||||
void BcdToUint(_u8 *bcd_buf, _u32 dat)
|
||||
{
|
||||
dat = ( ( (_u32)bcd_buf[3]>>4 ) *10000000 )
|
||||
+ ( ( (_u32)bcd_buf[3]&0xf )*1000000 )
|
||||
+ ( ( (_u32)bcd_buf[2]>>4 ) *100000 )
|
||||
+ ( ( (_u32)bcd_buf[2]&0xf )*10000 )
|
||||
+ ( ( (_u32)bcd_buf[1]>>4 ) *1000 )
|
||||
+ ( ( (_u32)bcd_buf[1]&0xf )*100 )
|
||||
+ ( ( (_u32)bcd_buf[0]>>4 ) *10 )
|
||||
+ ( ( (_u32)bcd_buf[0]&0xf ) );
|
||||
|
||||
//printf("***BCD:%x %x %x %x\t***: %d\n", bcd_buf[3], bcd_buf[2], bcd_buf[1], bcd_buf[0], dat);
|
||||
}
|
||||
|
||||
//print float number
|
||||
#if PRINT
|
||||
int printf_float(float data)
|
||||
{
|
||||
unsigned int i=0,j=0;
|
||||
i = (unsigned int)(data);
|
||||
j = (unsigned int)((data-i)*1000000);
|
||||
printf("%d.%06d\n", i, j);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
193
resources/soc/simu/soft/func/source/dg_rs232.c
Normal file
193
resources/soc/simu/soft/func/source/dg_rs232.c
Normal file
@ -0,0 +1,193 @@
|
||||
#include <stdio.h>
|
||||
#include "../config.h"
|
||||
#include "../include/asm/ns16550.h"
|
||||
|
||||
#define COM_BASE 0xbfe88000 //com1 for 1D
|
||||
#define NS16550_LSR 5
|
||||
#define NS16550_DATA 0
|
||||
|
||||
#define LSR_TXRDY 0x20
|
||||
#define LSR_RXRDY 0x01
|
||||
|
||||
#define writeb(val, addr) (*(volatile unsigned char*)(addr) = (val))
|
||||
#define readb(addr) (*(volatile unsigned char*)(addr))
|
||||
int dg_write(char *str);
|
||||
int dg_read(char *buffer, unsigned num);
|
||||
static void uart_putchar(char a0);
|
||||
static char uart_getchar(void);
|
||||
static void uart1_init(void)
|
||||
{
|
||||
Uart1_FCR = FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_4;
|
||||
Uart1_LCR = CFCR_DLAB;
|
||||
Uart1_BaudL = 52; //set 9600Baut
|
||||
Uart1_LCR = CFCR_8BITS; //8bit, 1stop
|
||||
Uart1_MCR = MCR_DTR|MCR_RTS;
|
||||
Uart1_IER = 0;
|
||||
}
|
||||
|
||||
int dg_ctrl(int argc, char argv[][30]) // main
|
||||
{
|
||||
char buffer[1024];
|
||||
uart1_init();
|
||||
printf("\n");
|
||||
/* Make sure ip address is supplied on the command line */
|
||||
// if ( argc < 2 ) {
|
||||
// printf("Usage: dg_ctrl IP_ADDRESS\n");
|
||||
// exit(1);
|
||||
// }
|
||||
/* Initialize the sockets library */
|
||||
// init_tcpip();
|
||||
/* Connect to the dg645 */
|
||||
// if ( dg_connect( inet_addr(argv[1]) ) ) {
|
||||
// printf("Connection Succeeded\n");
|
||||
/* Get identification string */
|
||||
dg_write("*idn?\n");
|
||||
// printf("\n*idn?\n");
|
||||
if ( dg_read(buffer,sizeof(buffer)) )
|
||||
printf("%s\n",buffer);
|
||||
else
|
||||
printf("Timeout\n");
|
||||
/* Load default settings */
|
||||
dg_write("*rst\n"); // load default settings
|
||||
dg_write("tsrc 1\n"); // set trigger source to 1(external posedge)
|
||||
dg_write("burc 1\n"); // set burst count to 1
|
||||
dg_write("burd 4e-6\n"); // set burst delay to 4us
|
||||
dg_write("burm 1\n"); // set burst mode to ON
|
||||
dg_write("burp 1e-6\n"); // set burst period to 1us
|
||||
dg_write("dlay 2,0,5e-8\n"); // set A to 0 delay to 50ns
|
||||
dg_write("dlay 3,2,5e-7\n"); // set B to A delay to 500ns
|
||||
dg_write("tlvl 0.9\n"); // set trigger level to 0.9V
|
||||
dg_write("lamp 0,1.66\n"); // set T0 amplitude to 1.66V
|
||||
dg_write("lamp 1,1.66\n"); // set AB amplitude to 1.66V
|
||||
dg_write("*sav 4\n"); // save config to 4
|
||||
// dg_write("*wai\n"); // wait execute
|
||||
/* Make sure all commands have executed before closing connection */
|
||||
// dg_write("*opc?\n");
|
||||
// if ( !dg_read(buffer,sizeof(buffer)) )
|
||||
// printf("Timeout\n");
|
||||
/* Close the connection */
|
||||
// if (dg_close())
|
||||
// printf("Closed connection\n");
|
||||
// else
|
||||
// printf("Unable to close connection");
|
||||
// }
|
||||
// else
|
||||
// printf("Connection Failed\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dg_cmd(int argc, char argv[][30])
|
||||
{
|
||||
printf("\n");
|
||||
dg_write(argv[1]);
|
||||
dg_write("\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dg_write(char *str)
|
||||
{
|
||||
// printf("\n");
|
||||
while(*str != '\0'){
|
||||
uart_putchar(*str);
|
||||
printf("%c",*str);
|
||||
str++;
|
||||
}
|
||||
if(*(str-1) == '\n') printf("\r");
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dg_read(char *buffer, unsigned num)
|
||||
{
|
||||
char t;
|
||||
int count=0;
|
||||
unsigned flag=0;
|
||||
while(1){
|
||||
t=uart_getchar();
|
||||
if(t==-1) {
|
||||
*buffer = '\0'; return count;
|
||||
}
|
||||
//if(t==10 || t==13 || t=='\0') flag=1; //
|
||||
if(flag){
|
||||
*buffer = '\0'; return count;
|
||||
}
|
||||
else{
|
||||
*buffer = t; buffer++; count++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void uart_putchar(char a0)
|
||||
{
|
||||
while((readb(COM_BASE + NS16550_LSR) & LSR_TXRDY)==0){}
|
||||
writeb(a0, COM_BASE + NS16550_DATA);
|
||||
}
|
||||
|
||||
static char uart_getchar()
|
||||
{
|
||||
//printf("fly to here\n");
|
||||
int cnt=0;
|
||||
while(cnt<1000000 && (readb(COM_BASE + NS16550_LSR) & LSR_RXRDY)==0){cnt++;}
|
||||
if (cnt>=1000000) return -1;
|
||||
return readb(COM_BASE + NS16550_DATA);
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
TSRC(?){i} Trigger Source
|
||||
Set (query) the trigger source {to i}. The parameter i determines the trigger
|
||||
source according to the following table:
|
||||
i Trigger Source
|
||||
0 Internal
|
||||
1 External rising edges
|
||||
2 External falling edges
|
||||
3 Single shot external rising edges
|
||||
4 Single shot external falling edges
|
||||
5 Single shot
|
||||
6 Line
|
||||
Example
|
||||
TSRC 5<CR> Set up the DG645 for single shot triggering.
|
||||
|
||||
///-------------------------
|
||||
|
||||
DLAY(?)c{,d,t} Delay
|
||||
Set (query) the delay for channel c {to t relative to channel d}.
|
||||
Example
|
||||
DLAY 2,0,10e-6<CR> Set channel A delay to equal channel T0 plus 10 μs.
|
||||
DLAY 3,2,1e-3<CR> Set channel B delay to equal channel A delay plus 1 ms.
|
||||
DLAY?3<CR> Query channel B. Should return ‘2,+0.001000000000’ to
|
||||
indicate that B = A + 1 ms.
|
||||
|
||||
///-------------------------BURST
|
||||
|
||||
BURC(?){i} Burst Count
|
||||
Set (query) the burst count {to i}. When burst mode is enabled, the DG645
|
||||
outputs burst count delay cycles per trigger.
|
||||
Example
|
||||
BURC 10<CR> Set the burst count to 10 so that the DG645 will output
|
||||
10 delay cycles per triggered burst.
|
||||
|
||||
BURD(?){t} Burst Delay
|
||||
Set (query) the burst delay {to t}. When burst mode is enabled the DG645 delays
|
||||
the first burst pulse relative to the trigger by the burst delay.
|
||||
Example
|
||||
BURD 5e-6<CR> Set the burst delay to 5 μs so that the DG645 will delay the
|
||||
first cycle of the burst by 5 μs relative to the trigger.
|
||||
|
||||
BURM(?){i} Burst Mode
|
||||
Set (query) the burst mode {to i}. If i is 0, burst mode is disabled. If i is 1, burst
|
||||
mode is enabled.
|
||||
|
||||
BURP(?){t} Burst Period
|
||||
Set (query) the burst period {to t}. The burst period sets the time between delay
|
||||
cycles during a burst. The burst period may range from 100 ns to 2000 – 10 ns in
|
||||
10 ns steps.
|
||||
Example
|
||||
BURP 1e-3<CR> Set burst period to 1 ms. When a burst is triggered, the
|
||||
DG645 will generate burst count delay cycles at a 1 kHz rate.
|
||||
|
||||
BURT(?){i} Burst T0 Configuration
|
||||
Set (query) the burst T0 configuration {to i}. If i is 0, the T0 output is enabled for
|
||||
all delay cycles of the burst. If i is 1, the T0 output is enabled for first delay cycle
|
||||
of the burst only.
|
||||
|
||||
*/
|
255
resources/soc/simu/soft/func/source/flash.c
Normal file
255
resources/soc/simu/soft/func/source/flash.c
Normal file
@ -0,0 +1,255 @@
|
||||
#include "../config.h"
|
||||
|
||||
extern unsigned int str2num (char str[30]);
|
||||
void mywait(void);
|
||||
/******************************
|
||||
*Flash Test* CONFIDENTIAL
|
||||
|
||||
>CAUTION<
|
||||
DO NOT add this program to ANY release version!
|
||||
|
||||
Liu Su
|
||||
liusu-cpu@ict.ac.cn
|
||||
******************************/
|
||||
|
||||
//#if FLASH_TEST
|
||||
|
||||
static void flash_clearHVPL(void)
|
||||
{
|
||||
*(volatile _u32*)(0xbfe60000) = 0x40000000;
|
||||
}
|
||||
|
||||
static void flash_erase(_u32 offset)
|
||||
{
|
||||
*(volatile _u32*)(0xbfe60000) = 0xa0000000|offset;
|
||||
}
|
||||
|
||||
static void flash_page(_u32 offset)
|
||||
{
|
||||
*(volatile _u32*)(0xbfe60000) = 0xe0000000|offset;
|
||||
}
|
||||
|
||||
static void flash_setca(_u32 cah, _u32 cal)
|
||||
{
|
||||
*(volatile _u32*)(0xbfe60008) = cal;
|
||||
*(volatile _u32*)(0xbfe60004) = cah;
|
||||
*(volatile _u32*)(0xbfe60000) = 0xf0000000;
|
||||
}
|
||||
|
||||
int set_ca(int argc, char argv[][30])
|
||||
{
|
||||
_u32 cah,cal;
|
||||
if(argc !=3 ) {printf("\nUsage: setca <cah> <cal>");return 1;}
|
||||
cah = str2num(argv[1]);
|
||||
cal = str2num(argv[2]);
|
||||
*(volatile _u32*)(0xbfe60008) = cal;
|
||||
*(volatile _u32*)(0xbfe60004) = cah;
|
||||
*(volatile _u32*)(0xbfe60000) = 0xf0000000;
|
||||
// mywait();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void flash_writepl()
|
||||
{
|
||||
int i;
|
||||
for(i=0; i<128; i+=4)
|
||||
*(volatile _u32*)(0xbf00e000 + i) = i;
|
||||
}
|
||||
|
||||
int verif(int argc, char argv[][30])
|
||||
{
|
||||
printf("\nverif");
|
||||
_u32 page_offset;
|
||||
_u32 page_latch[33];
|
||||
int i;
|
||||
page_offset = 0xe000;
|
||||
printf("\noffset");
|
||||
// crypt
|
||||
flash_setca(0x1f00e100,0x1f00e000);
|
||||
printf("\nsetca\n");
|
||||
// normal page
|
||||
flash_clearHVPL();
|
||||
printf("clearHVPL\n");
|
||||
flash_writepl();
|
||||
printf("writepl\n");
|
||||
flash_erase(page_offset);
|
||||
// mywait();
|
||||
printf("erase\n");
|
||||
flash_page(page_offset);
|
||||
// mywait();
|
||||
printf("page\n");
|
||||
// verif
|
||||
*(volatile _u32*)(0xbfe60010) = 0x14;
|
||||
*(volatile _u32*)(0xbfe60000) = 0x1000e014;
|
||||
while(*(volatile _u32*)(0xbfe60014) & 0x2 != 0x2){}
|
||||
if(*(volatile _u32*)(0xbfe60014) & 0x1)
|
||||
printf("verif correct\n");
|
||||
else
|
||||
printf("verif error");
|
||||
// flash_setca(0x1f000001,0x1f000001);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int set_pe_time_mode(int argc, char argv[][30])
|
||||
{
|
||||
unsigned int mode;
|
||||
mode = str2num(argv[1]);
|
||||
*(volatile _u32*)(0xbfe60024) = mode;
|
||||
/****************************
|
||||
mode: 0: 1.5ms
|
||||
1: 2.0ms
|
||||
2: 2.5ms
|
||||
3: 3.0ms
|
||||
4: 3.5ms
|
||||
****************************/
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void set_pe_time(int mode)
|
||||
{
|
||||
*(volatile _u32*)(0xbfe60024) = mode;
|
||||
}
|
||||
|
||||
int flash_tk(int argc, char argv[][30])
|
||||
{
|
||||
unsigned int i,num;
|
||||
num = str2num(argv[1]);
|
||||
for(i=0; i<num; i++)
|
||||
{
|
||||
*(volatile _u32*)(0xbfe60000) = 0x20000000;
|
||||
while(*(volatile _u32*)(0xbfe60014) & 0x4 != 0x4){}
|
||||
printf("\n%8x%8x",*(volatile _u32*)(0xbfe60018),*(volatile _u32*)(0xbfe6001c));
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int flash_accg(int argc, char argv[][30])
|
||||
{
|
||||
printf("\n%x\n",*(volatile _u32*)(0xbf010008));
|
||||
*(volatile _u32*)(0xbfe60020) = 0x37116327;
|
||||
*(volatile _u32*)(0xbfe60020) = 0x90d112e5;
|
||||
*(volatile _u32*)(0xbfe60020) = 0x41237f48;
|
||||
*(volatile _u32*)(0xbfe60020) = 0xbeb9fb58;
|
||||
printf("%x",*(volatile _u32*)(0xbf010008));
|
||||
return 0;
|
||||
}
|
||||
|
||||
void mywait(void)
|
||||
{
|
||||
__asm__ volatile(
|
||||
".set mips3\n"
|
||||
"wait;\n"
|
||||
".set mips1\n"
|
||||
);
|
||||
}
|
||||
|
||||
int copy_flash(int argc, char argv[][30])
|
||||
{
|
||||
_u32 i,j,k,cnt;
|
||||
flash_setca(0x1f000001,0x1f000000);
|
||||
mywait();
|
||||
flash_clearHVPL();
|
||||
printf("\n");
|
||||
*(volatile _u8*)(0xbfea0000) = 0x10; // open int_en of flash in confreg
|
||||
for(i=511;; i=i-1)
|
||||
{
|
||||
for(j=0;j<128;j+=4){
|
||||
k= *(volatile _u32*)(0xbfc00000+i*128+j);
|
||||
*(volatile _u32*)(0xbf000000+i*128+j) = k;
|
||||
}
|
||||
// if(i%0x80 == 0x7c)
|
||||
// {
|
||||
printf("page %3d\n",i);
|
||||
set_pe_time(2);
|
||||
flash_erase(i*128);
|
||||
mywait();
|
||||
// while(*(volatile _u8*)(0xbfea0005) != 0x10) {}
|
||||
set_pe_time(2);
|
||||
flash_page(i*128);
|
||||
mywait();
|
||||
// while(*(volatile _u8*)(0xbfea0005) != 0x10) {}
|
||||
flash_clearHVPL();
|
||||
// }
|
||||
if(i==0) break;
|
||||
}
|
||||
printf("\n\r\n\r\n");
|
||||
cnt = 0;
|
||||
for(i=0;i<0x10000;i+=4)
|
||||
{
|
||||
j = *(volatile _u32*)(0xbf000000+i);
|
||||
k = *(volatile _u32*)(0xbfc00000+i);
|
||||
cnt = (j==k) ? cnt : cnt + 1;
|
||||
// printf("@%4x : %8x %8x %1d\n",i,j,k,(j==k));
|
||||
}
|
||||
printf("error count: %d\n",cnt);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int write_trim(int argc, char argv[][30])
|
||||
{
|
||||
flash_clearHVPL();
|
||||
*(volatile _u32*)(0xbfe60020) = 0x37116327;
|
||||
*(volatile _u32*)(0xbfe60020) = 0x90d112e5;
|
||||
*(volatile _u32*)(0xbfe60020) = 0x41237f48;
|
||||
*(volatile _u32*)(0xbfe60020) = 0xbeb9fb58;
|
||||
*(volatile _u32*)(0xbf0101f0) = 0x01aadd00;
|
||||
*(volatile _u32*)(0xbf0101f4) = 0x1f190106;
|
||||
*(volatile _u32*)(0xbf0101f8) = 0x091e5522;
|
||||
*(volatile _u32*)(0xbf0101fc) = 0x6d920606;
|
||||
set_pe_time(2);
|
||||
flash_erase(0x10180);
|
||||
mywait();
|
||||
flash_page(0x10180);
|
||||
mywait();
|
||||
printf("\ntrim write ok");
|
||||
return 0;
|
||||
}
|
||||
|
||||
int jump(int argc, char argv[][30])
|
||||
{
|
||||
__asm__ volatile(
|
||||
"li $8, 0xbf000000;\n"
|
||||
"jalr $8;\n"
|
||||
"nop;\n"
|
||||
:::"$8");
|
||||
return 0;
|
||||
}
|
||||
|
||||
int flash_test(int argc, char argv[][30])
|
||||
{
|
||||
_u32 i,j,k,cnt;
|
||||
k = str2num(argv[1]);
|
||||
*(volatile _u8*)(0xbfea0000) = 0x10; // open int_en of flash in confreg
|
||||
flash_setca(0x1f000001,0x1f000000);
|
||||
mywait();
|
||||
flash_clearHVPL();
|
||||
set_pe_time(2);
|
||||
printf("\npaging");
|
||||
*(volatile _u32*)(0xbfe60000) = 0x80000000; // erase all
|
||||
mywait();
|
||||
for(i=0;i<512;i++)
|
||||
{
|
||||
for(j=0;j<128;j+=4){
|
||||
// k= *(volatile _u32*)(0xbfc00000+i*128+j);
|
||||
*(volatile _u32*)(0xbf000000+i*128+j) = k;
|
||||
}
|
||||
// printf("page %3d\n",i);
|
||||
flash_page(i*128);
|
||||
mywait();
|
||||
// while(*(volatile _u8*)(0xbfea0005) != 0x10) {}
|
||||
flash_clearHVPL();
|
||||
}
|
||||
printf("\nverifying\n");
|
||||
cnt = 0;
|
||||
for(i=0;i<0x10000;i+=4)
|
||||
{
|
||||
j = *(volatile _u32*)(0xbf000000+i);
|
||||
// k = *(volatile _u32*)(0xbfc00000+i);
|
||||
cnt = (j==k) ? cnt : cnt + 1;
|
||||
if(j!=k) printf("@addr:0x%4x : j=0x%8x k=0x%8x\n",i,j,k);
|
||||
// printf("@%4x : %8x %8x %1d\n",i,j,k,(j==k));
|
||||
}
|
||||
printf("error count: %d\n",cnt);
|
||||
return 0;
|
||||
}
|
||||
//#endif //FLASH_TEST
|
449
resources/soc/simu/soft/func/source/frame.c
Normal file
449
resources/soc/simu/soft/func/source/frame.c
Normal file
@ -0,0 +1,449 @@
|
||||
/***************************************************************************************************************************************************
|
||||
This file is used for CJT188 protocol.
|
||||
***************************************************************************************************************************************************/
|
||||
#include "../config.h"
|
||||
|
||||
#if FRAME_MODULE
|
||||
|
||||
#define HEAD 0x68
|
||||
#define TAIL 0x16
|
||||
/****************Unit******************/
|
||||
#define danwei_Wh 0x02
|
||||
#define danwei_KWh 0x05
|
||||
#define danwei_MWh 0x08
|
||||
#define danwei_MWhX100 0x0a
|
||||
#define danwei_J 0x01
|
||||
#define danwei_KJ 0x0b
|
||||
#define danwei_MJ 0x0e
|
||||
#define danwei_GJ 0x11
|
||||
#define danwei_GJX100 0x13
|
||||
#define danwei_W 0x14
|
||||
#define danwei_KW 0x17
|
||||
#define danwei_MW 0x1a
|
||||
#define danwei_L 0x29
|
||||
#define danwei_m3 0x2c
|
||||
#define danwei_L_h 0x32
|
||||
#define danwei_m3_h 0x35
|
||||
|
||||
|
||||
void IrSend(_u8 *str)
|
||||
{
|
||||
//IR_PWR_OFF;
|
||||
for( ; *str != '\0';str++)
|
||||
Uart1_TxData = *str;
|
||||
}
|
||||
|
||||
|
||||
_u32 ST; //状态ST
|
||||
/**************************
|
||||
0x0004 //电池欠压
|
||||
0x0000 //阀门开
|
||||
0x0001 //阀门关
|
||||
0x0003 //阀门异常
|
||||
高位由厂商定义
|
||||
***************************/
|
||||
struct FrameFormat Frame;
|
||||
|
||||
static _u8 frame_tx[120] ;
|
||||
static _u8 frame_rx[70];
|
||||
static _u32 UART_OutpLen;
|
||||
static _u32 TX_IndexW;
|
||||
_u32 RX_IndexW;
|
||||
|
||||
void uart_tx(void)
|
||||
{
|
||||
if(UART_OutpLen > 0){
|
||||
UART_OutpLen--;
|
||||
Uart1_TxData = frame_tx[TX_IndexW];
|
||||
TX_IndexW +=1;
|
||||
}
|
||||
else{
|
||||
//IFG1 &= ~UTXIFG0;
|
||||
}
|
||||
}
|
||||
|
||||
void uart_rx(void)
|
||||
{
|
||||
static _u32 rx_head_flag; //'0'尚未收到帧开始符
|
||||
frame_rx[RX_IndexW] = Uart1_RxData; //波特率如果设的比较高,有时候会丢失第一个帧字符???
|
||||
#if PRINT
|
||||
printf("%x ", frame_rx[RX_IndexW]);
|
||||
#endif
|
||||
RX_IndexW +=1;
|
||||
|
||||
static _u32 len;
|
||||
if((rx_head_flag == 0) && (frame_rx[RX_IndexW-1] == HEAD)){
|
||||
len = RX_IndexW + 9;
|
||||
rx_head_flag = 1; //收到帧开始符
|
||||
}
|
||||
if(rx_head_flag == 1){
|
||||
if((frame_rx[RX_IndexW-1] == TAIL) && (RX_IndexW > (len+(_u32)frame_rx[len]+2))){
|
||||
//if(RX_BUFF[len+(_u32)RX_BUFF[len])+2] == TAIL){
|
||||
rx_head_flag = 0;
|
||||
//UART_InpLen = RX_IndexW;
|
||||
RX_IndexW =0;
|
||||
main_flag |= rx_bit; //usart收到一个完整的帧
|
||||
#if PRINT
|
||||
printf("\n");
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/*-----------------------发送应答帧----------------------*/
|
||||
void Answer()
|
||||
{
|
||||
_u32 i=0;
|
||||
_u32 j;
|
||||
_u32 head = 3;
|
||||
Frame.CheckSum = 0x0;
|
||||
frame_tx[i++] = 0xfe;
|
||||
frame_tx[i++] = 0xfe;
|
||||
frame_tx[i++] = 0xfe;
|
||||
frame_tx[i++] = Frame.HeadCode;
|
||||
frame_tx[i++] = Frame.TypeCode;
|
||||
for(j=0;j<7;j++)
|
||||
frame_tx[i++] = Frame.Address[j];
|
||||
frame_tx[i++] = Frame.CtrlCode; //需要进行异常判断后置位
|
||||
frame_tx[i++] = Frame.DataLen;
|
||||
#if CJT188_DI_SEQ
|
||||
frame_tx[i++] = Frame.DI0;
|
||||
frame_tx[i++] = Frame.DI1;
|
||||
#else
|
||||
frame_tx[i++] = Frame.DI1;
|
||||
frame_tx[i++] = Frame.DI0;
|
||||
#endif
|
||||
frame_tx[i++] = Frame.SER;
|
||||
for(j=0;j<((_u32)Frame.DataLen-3);j++)
|
||||
frame_tx[i++] = Frame.Data[j];
|
||||
while(head < i){
|
||||
Frame.CheckSum += frame_tx[head];
|
||||
Frame.CheckSum %= 256;
|
||||
head++;
|
||||
}
|
||||
frame_tx[i++] = Frame.CheckSum;
|
||||
frame_tx[i++] = Frame.TailCode;
|
||||
UART_OutpLen =i;
|
||||
}
|
||||
|
||||
_u32 read1(struct Date_Time *Date_and_Time, struct Data *Lcd_data)
|
||||
{
|
||||
_u32 i=0;
|
||||
_u32 j;
|
||||
_u32 dat;
|
||||
union uint_uchar uint2uchar;
|
||||
Frame.DataLen = 0x2e;
|
||||
|
||||
dat = *(_u32 *)(INFO_FLASH_START + Last_month_num*12 + 4);//total heat of last month
|
||||
UintToBcd(dat, &uint2uchar);
|
||||
for(j=0; j<4; j++)
|
||||
Frame.Data[i++] = uint2uchar.c_value[j];
|
||||
Frame.Data[i++] = danwei_KWh;
|
||||
|
||||
dat = (_u32)Lcd_data->total_heat*100/LCD_MULTIPLE; //当前热量
|
||||
UintToBcd(dat, &uint2uchar);
|
||||
for(j=0; j<4; j++)
|
||||
Frame.Data[i++] = uint2uchar.c_value[j];
|
||||
Frame.Data[i++] = danwei_KWh;
|
||||
|
||||
dat = (_u32)Lcd_data->heat*100/LCD_MULTIPLE; //热功率
|
||||
UintToBcd(dat, &uint2uchar);
|
||||
for(j=0; j<4; j++)
|
||||
Frame.Data[i++] = uint2uchar.c_value[j];
|
||||
Frame.Data[i++] = danwei_KW;
|
||||
|
||||
dat = (_u32)Lcd_data->flow*10000; //瞬时流量
|
||||
UintToBcd(dat, &uint2uchar);
|
||||
for(j=0; j<4; j++)
|
||||
Frame.Data[i++] = uint2uchar.c_value[j];
|
||||
Frame.Data[i++] = danwei_m3;
|
||||
|
||||
dat = (_u32)Lcd_data->total_flow*100/LCD_MULTIPLE; //累计流量
|
||||
UintToBcd(dat, &uint2uchar);
|
||||
for(j=0; j<4; j++)
|
||||
Frame.Data[i++] = uint2uchar.c_value[j];
|
||||
Frame.Data[i++] = danwei_m3;
|
||||
|
||||
dat = (_u32)Lcd_data->temp1*100/LCD_MULTIPLE; //入水温度
|
||||
UintToBcd(dat, &uint2uchar);
|
||||
for(j=1; j<4; j++)
|
||||
Frame.Data[i++] = uint2uchar.c_value[j];
|
||||
|
||||
dat = (_u32)Lcd_data->temp2*100/LCD_MULTIPLE; //出水温度
|
||||
UintToBcd(dat, &uint2uchar);
|
||||
for(j=1; j<4; j++)
|
||||
Frame.Data[i++] = uint2uchar.c_value[j];
|
||||
|
||||
dat = (_u32)Lcd_data->total_time; //累计工作时间
|
||||
UintToBcd(dat, &uint2uchar);
|
||||
for(j=1; j<4; j++)
|
||||
Frame.Data[i++] = uint2uchar.c_value[j];
|
||||
|
||||
//实时时间
|
||||
dat = (_u32)Date_and_Time->Day*1000000 + (_u32)Date_and_Time->Hour*10000 + (_u32)Date_and_Time->Minute*100 + (_u32)Date_and_Time->Second;
|
||||
UintToBcd(dat, &uint2uchar);
|
||||
for(j=0; j<4; j++)
|
||||
Frame.Data[i++] = uint2uchar.c_value[j];
|
||||
dat = (_u32)Date_and_Time->Year*100 + (_u32)Date_and_Time->Month;
|
||||
UintToBcd(dat, &uint2uchar);
|
||||
for(j=0; j<3; j++)
|
||||
Frame.Data[i++] = uint2uchar.c_value[j];
|
||||
|
||||
dat = (_u32)ST; //状态ST
|
||||
UintToBcd(dat, &uint2uchar);
|
||||
Frame.Data[i++] = uint2uchar.c_value[0];
|
||||
Frame.Data[i++] = uint2uchar.c_value[1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
_u32 read2() //上几月月结热量
|
||||
{
|
||||
_u32 j;
|
||||
j = (_u32)Frame.DI1;
|
||||
Frame.DataLen = 0x08;
|
||||
#if 0
|
||||
Flash_Read_Info();
|
||||
_u32 i;
|
||||
for(i=0; i<256; i++)
|
||||
{
|
||||
TXBUF0 = Array[i];
|
||||
while((U0TCTL & TXEPT) == 0) ;
|
||||
}
|
||||
#endif
|
||||
|
||||
_u32 offset;
|
||||
_u32 dat;
|
||||
union uint_uchar uint2uchar;
|
||||
offset = ((Last_month_num-(j-32))%18)*12+4; //0~216
|
||||
dat = *(_u32 *)(INFO_FLASH_START + offset);//total heat
|
||||
UintToBcd(dat, &uint2uchar);
|
||||
for(j=0; j<4; j++)
|
||||
Frame.Data[j] = uint2uchar.c_value[j];
|
||||
Frame.Data[4] = danwei_KWh;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
_u32 read3()
|
||||
{
|
||||
switch(Frame.DI1){
|
||||
case 0x02: //读价格表
|
||||
Frame.DataLen = 0x12;
|
||||
break;
|
||||
case 0x03: //读结算日
|
||||
Frame.DataLen = 0x04;
|
||||
break;
|
||||
case 0x04: //读抄表日
|
||||
Frame.DataLen = 0x04;
|
||||
break;
|
||||
case 0x05: //读购入金额
|
||||
Frame.DataLen = 0x12;
|
||||
break;
|
||||
default:
|
||||
return ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
_u32 read4()
|
||||
{
|
||||
Frame.DataLen = 0x04;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
_u32 read5()
|
||||
{
|
||||
Frame.DataLen = 0x03;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
_u32 write1()
|
||||
{
|
||||
switch(Frame.DI1){
|
||||
case 0x10:
|
||||
Frame.DataLen = 0x05;
|
||||
break;
|
||||
case 0x11:
|
||||
Frame.DataLen = 0x03;
|
||||
break;
|
||||
case 0x12:
|
||||
Frame.DataLen = 0x03;
|
||||
break;
|
||||
case 0x13:
|
||||
Frame.DataLen = 0x08;
|
||||
break;
|
||||
case 0x14:
|
||||
Frame.DataLen = 0x04;
|
||||
break;
|
||||
case 0x15:
|
||||
Frame.DataLen = 0x03;
|
||||
break;
|
||||
case 0x17:
|
||||
Frame.DataLen = 0x05;
|
||||
break;
|
||||
case 0x19:
|
||||
Frame.DataLen = 0x03;
|
||||
break;
|
||||
default:
|
||||
return ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
_u32 write2()
|
||||
{
|
||||
Frame.DataLen = 0x03;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
_u32 write3()
|
||||
{
|
||||
Frame.DataLen = 0x05;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
_u32 write4()
|
||||
{
|
||||
switch(Frame.DI1){
|
||||
case 0x12:
|
||||
Frame.DataLen = 0x05;
|
||||
break;
|
||||
case 0x14:
|
||||
Frame.DataLen = 0x05;
|
||||
break;
|
||||
case 0x16:
|
||||
Frame.DataLen = 0x05;
|
||||
break;
|
||||
default:
|
||||
return ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void do_err()
|
||||
{
|
||||
_u32 dat;
|
||||
union uint_uchar uint2uchar;
|
||||
|
||||
Frame.CtrlCode |= 0x40;
|
||||
Frame.DataLen = 0x03;
|
||||
Frame.DI0 = Frame.SER;
|
||||
UintToBcd(ST, &uint2uchar);
|
||||
Frame.DI1 = uint2uchar.c_value[0];
|
||||
Frame.SER = uint2uchar.c_value[1];
|
||||
}
|
||||
|
||||
//_u32 do_frame() //下位机应答模式,对协议进行解析
|
||||
_u32 do_frame(struct Date_Time *Date_and_Time, struct Data *Lcd_data)
|
||||
{
|
||||
_u32 err;
|
||||
_u32 i,j,head,tail;
|
||||
/*----------------开始帧格式解析----------------*/
|
||||
|
||||
Frame.CheckSum = 0x0;
|
||||
for(i=0;frame_rx[i] == 0xfe;i++);
|
||||
head = i;
|
||||
j = head;
|
||||
|
||||
Frame.HeadCode = frame_rx[head++];
|
||||
Frame.TypeCode = frame_rx[head++];
|
||||
for(i=0;i<7;i++)
|
||||
Frame.Address[i] = frame_rx[head++];
|
||||
Frame.CtrlCode = frame_rx[head++];
|
||||
Frame.DataLen = frame_rx[head++];
|
||||
#if CJT188_DI_SEQ
|
||||
Frame.DI0 = frame_rx[head++];
|
||||
Frame.DI1 = frame_rx[head++];
|
||||
#else
|
||||
Frame.DI1 = frame_rx[head++];
|
||||
Frame.DI0 = frame_rx[head++];
|
||||
#endif
|
||||
Frame.SER = frame_rx[head++];
|
||||
for(i=0;i<((_u32)Frame.DataLen-3);i++)
|
||||
Frame.Data[i] = frame_rx[head++];
|
||||
while(j < head){
|
||||
Frame.CheckSum += frame_rx[j];
|
||||
Frame.CheckSum %= 256;
|
||||
j++;
|
||||
}
|
||||
if(Frame.CheckSum != frame_rx[j]) {
|
||||
return 1;
|
||||
}
|
||||
tail = j+1;
|
||||
Frame.TailCode = frame_rx[tail];
|
||||
/*----------------完成帧格式解析----------------*/
|
||||
|
||||
/*------------------------根据控制码进行类型解析--------------------------*/
|
||||
switch(Frame.CtrlCode){
|
||||
case 0x01: //read data
|
||||
if((Frame.DI0==0x90)&&(Frame.DI1==0x1f)) err = read1(Date_and_Time, Lcd_data);
|
||||
else if(Frame.DI0==0xd1) err = read2();
|
||||
else if(Frame.DI0==0x81) err = read3();
|
||||
break;
|
||||
case 0x09: //读密钥版本号
|
||||
if((Frame.DI0==0x81)&&(Frame.DI1==0x06)) err = read4();
|
||||
break;
|
||||
case 0x03: //读地址
|
||||
if((Frame.DI0==0x81)&&(Frame.DI1==0x0a)) err = read5();
|
||||
break;
|
||||
case 0x04: //写数据
|
||||
if(Frame.DI0==0xa0) err = write1();
|
||||
break;
|
||||
case 0x15: //写地址
|
||||
if((Frame.DI0==0xa0)&&(Frame.DI1==0x18)) err = write2();
|
||||
break;
|
||||
case 0x16: //写机电同步数据
|
||||
if((Frame.DI0==0xa0)&&(Frame.DI1==0x16)) err = write3();
|
||||
break;
|
||||
case CJT188_DEF_READ: //三川读
|
||||
|
||||
break;
|
||||
case CJT188_DEF_WRITE: //三川写
|
||||
if(Frame.DI0==0xb0) err = write4();
|
||||
break;
|
||||
default:
|
||||
err = 2;
|
||||
break;
|
||||
}
|
||||
/*------------------------完成类型解析--------------------------*/
|
||||
Frame.CtrlCode |= 0x80;
|
||||
if(err) do_err();
|
||||
Answer();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void Frame_exe(struct Date_Time *Date_and_Time, struct Data *Lcd_data)
|
||||
{
|
||||
_u32 err;
|
||||
err = do_frame(&Date_and_Time, &Lcd_data);
|
||||
if(err==0)
|
||||
{
|
||||
TX_IndexW = 0;
|
||||
Uart1_TxData = 0xfe;
|
||||
//IFG1 |= UTXIFG0;
|
||||
}
|
||||
else if(err==1)
|
||||
{
|
||||
//TXBUF0 = 0xdd;
|
||||
//while((U0TCTL & TXEPT) == 0) ;
|
||||
}
|
||||
else if(err==2)
|
||||
{
|
||||
//TXBUF0 = 0xee;
|
||||
//while((U0TCTL & TXEPT) == 0) ;
|
||||
}
|
||||
}
|
||||
#endif
|
279
resources/soc/simu/soft/func/source/isp.c
Normal file
279
resources/soc/simu/soft/func/source/isp.c
Normal file
@ -0,0 +1,279 @@
|
||||
|
||||
#include "../config.h"
|
||||
|
||||
#if PRINT
|
||||
void tgt_putchar(_u8 chr)
|
||||
{
|
||||
while(!(Uart0_LSR & 0x20)) ;
|
||||
Uart0_TxData = chr;
|
||||
}
|
||||
|
||||
_u8 tgt_getchar()
|
||||
{
|
||||
_u8 chr;
|
||||
while(!(Uart0_LSR & 0x1)) ;
|
||||
chr = Uart0_RxData ;
|
||||
|
||||
return chr;
|
||||
}
|
||||
|
||||
_u8 tgt_testchar()
|
||||
{
|
||||
_u8 chr;
|
||||
chr = (Uart0_LSR & 0x1);
|
||||
|
||||
return chr;
|
||||
}
|
||||
#endif
|
||||
|
||||
_u32 now()
|
||||
{
|
||||
_u32 count;
|
||||
count = PMU_Count;
|
||||
count &= COUNT_MASK;
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
#if (ISP || MONTHDATA_MODULE)
|
||||
#if (LS1D_FPGA)
|
||||
void spiflash_erase(_u32 addr_start, _u32 addr_end)
|
||||
{
|
||||
__asm__ volatile(
|
||||
"move $15,$31;\n"
|
||||
/**spi_flash init**/
|
||||
"li $8,0xbfe70000;\n"
|
||||
"li $9,0xc0;\n"
|
||||
"sb $9,1($8);\n"
|
||||
"li $9,0x10;\n"
|
||||
"sb $9,4($8);\n"
|
||||
"li $9,0x5;\n"
|
||||
"sb $9,3($8);\n"
|
||||
"li $9,0x1;\n"
|
||||
"sb $9,6($8);\n"
|
||||
"li $9,0x50;\n"
|
||||
"sb $9,0($8);\n"
|
||||
/**spi_flash code_program**/
|
||||
"li $14, 0x1000;\n"
|
||||
"1:li $9,0x11;\n"
|
||||
"sb $9,5($8);\n" /*high cs*/
|
||||
"bal 102f;\n" /*wait sr */
|
||||
"nop;\n"
|
||||
"li $9,6;\n" /* write enable */
|
||||
"bal 101f;\n"
|
||||
"nop;\n"
|
||||
"li $9,0x11;\n" /*high cs*/
|
||||
"sb $9,5($8);\n"
|
||||
"li $9,1;\n" /* write status*/
|
||||
"bal 101f;\n"
|
||||
"nop;\n"
|
||||
"li $9,0;\n" /* write 0*/
|
||||
"bal 103f;\n"
|
||||
"nop;\n"
|
||||
"li $9,0x11;\n" /*high cs*/
|
||||
"sb $9,5($8);\n"
|
||||
"bal 102f;\n" /*wait sr */
|
||||
"nop;\n"
|
||||
"li $9,6;\n" /* write enable */
|
||||
"bal 101f;\n"
|
||||
"nop;\n"
|
||||
"li $9,0x11;\n" /*high cs*/
|
||||
"sb $9,5($8);\n"
|
||||
"li $9,0x20;\n" /*bulk erase, 4kB*/
|
||||
"bal 101f;\n"
|
||||
"nop;\n"
|
||||
"srl $9,$4,16;\n" /*addr*/
|
||||
"bal 103f;\n"
|
||||
"nop;\n"
|
||||
"srl $9,$4,8;\n"
|
||||
"bal 103f;\n"
|
||||
"nop;\n"
|
||||
"move $9,$4;\n"
|
||||
"bal 103f;\n"
|
||||
"nop;\n"
|
||||
"li $9,0x11;\n" /*high cs*/
|
||||
"sb $9,5($8);\n"
|
||||
"bal 102f;\n" /*wait sr*/
|
||||
"nop;"
|
||||
"addu $4,$14;\n"
|
||||
"slt $9,$5,$4;\n"
|
||||
"beqz $9,1b;\n"
|
||||
"nop;\n"
|
||||
"3:\n"
|
||||
"li $9,0x11;\n"
|
||||
"sb $9,5($8);\n" /*high cs*/
|
||||
|
||||
"li $9,0x11;\n"
|
||||
"sb $9,4($8);\n"
|
||||
"b 999f;\n"
|
||||
"nop;\n"
|
||||
|
||||
"101:li $11,1;\n"
|
||||
"sb $11,5($8);\n" /*enable and low cs*/
|
||||
"103:sb $9,2($8);\n"
|
||||
"1:lb $9,1($8);\n"
|
||||
"andi $9,1;\n"
|
||||
"bnez $9,1b;\n"
|
||||
"nop;\n"
|
||||
"lb $9,2($8);\n"
|
||||
"jr $31;\n"
|
||||
"nop\n;"
|
||||
"102:move $10,$31;\n"
|
||||
"1:li $9,5;\n" /*wait read sr*/
|
||||
"bal 101b;\n"
|
||||
"nop;\n"
|
||||
"andi $9,1;\n"
|
||||
"bnez $9,1b;\n" /*can continue read sr,write to gen clock*/
|
||||
"nop;\n"
|
||||
"li $9,0x11;\n" /*high cs*/
|
||||
"sb $9,5($8);\n"
|
||||
"jr $10;\n"
|
||||
"nop;\n"
|
||||
|
||||
"999:move $31,$15;\n"
|
||||
:::"$8","$9","$10","$11","$4","$5","$14","$15"
|
||||
);
|
||||
}
|
||||
void spiflash_write(_u32 addr_w, _u32 addr_r, _u32 length)
|
||||
{
|
||||
__asm__ volatile(
|
||||
"move $15,$31;\n"
|
||||
/**spi_flash init**/
|
||||
"li $8,0xbfe70000;\n"
|
||||
"li $9,0xc0;\n"
|
||||
"sb $9,1($8);\n"
|
||||
"li $9,0x10;\n"
|
||||
"sb $9,4($8);\n"
|
||||
"li $9,0x5;\n"
|
||||
"sb $9,3($8);\n"
|
||||
"li $9,0x1;\n"
|
||||
"sb $9,6($8);\n"
|
||||
"li $9,0x50;\n"
|
||||
"sb $9,0($8);\n"
|
||||
/**spi_flash code_program**/
|
||||
"li $9,0x11;\n"
|
||||
"sb $9,5($8);\n" /*high cs*/
|
||||
"bal 102f;\n" /*wait sr */
|
||||
"nop;\n"
|
||||
"li $9,6;\n" /* write enable */
|
||||
"bal 101f;\n"
|
||||
"nop;\n"
|
||||
"li $9,0x11;\n" /*high cs*/
|
||||
"sb $9,5($8);\n"
|
||||
"li $9,1;\n" /* write status*/
|
||||
"bal 101f;\n"
|
||||
"nop;\n"
|
||||
"li $9,0;\n" /* write 0*/
|
||||
"bal 103f;\n"
|
||||
"nop;\n"
|
||||
"1:li $9,0x11;\n" /*high cs*/
|
||||
"sb $9,5($8);\n"
|
||||
"bal 102f;\n" /*wait sr */
|
||||
"nop;\n"
|
||||
"li $9,6;\n" /* write enable */
|
||||
"bal 101f;\n"
|
||||
"nop;\n"
|
||||
"li $9,0x11;\n" /*high cs*/
|
||||
"sb $9,5($8);\n"
|
||||
"bal 102f;\n" /*wait sr*/
|
||||
"nop;"
|
||||
"li $9,2;\n" /*write sector*/
|
||||
"bal 101f;\n"
|
||||
"nop;\n"
|
||||
"srl $9,$4,16;\n" /*addr*/
|
||||
"bal 103f;\n"
|
||||
"nop;\n"
|
||||
"srl $9,$4,8;\n"
|
||||
"bal 103f;\n"
|
||||
"nop;\n"
|
||||
"move $9,$4;\n"
|
||||
"bal 103f;\n"
|
||||
"nop;\n"
|
||||
"2:lb $9,0($5);\n" /*write 1 data*/
|
||||
"bal 103f;\n"
|
||||
"nop;\n"
|
||||
"addiu $4,1;\n"
|
||||
"addiu $5,1;\n"
|
||||
"addiu $6,-1;\n"
|
||||
"beqz $6,3f;\n"
|
||||
"nop;\n"
|
||||
"b 1b;\n"
|
||||
"nop;\n"
|
||||
"3:\n"
|
||||
"li $9,0x11;\n"
|
||||
"sb $9,5($8);\n" /*high cs*/
|
||||
|
||||
"li $9,0x11;\n"
|
||||
"sb $9,4($8);\n"
|
||||
"b 999f;\n"
|
||||
"nop;\n"
|
||||
|
||||
"101:li $11,1;\n"
|
||||
"sb $11,5($8);\n" /*enable and low cs*/
|
||||
"103:sb $9,2($8);\n"
|
||||
"1:lb $9,1($8);\n"
|
||||
"andi $9,1;\n"
|
||||
"bnez $9,1b;\n"
|
||||
"nop;\n"
|
||||
"lb $9,2($8);\n"
|
||||
"jr $31;\n"
|
||||
"nop\n;"
|
||||
"102:move $10,$31;\n"
|
||||
"1:li $9,5;\n" /*wait read sr*/
|
||||
"bal 101b;\n"
|
||||
"nop;\n"
|
||||
"andi $9,1;\n"
|
||||
"bnez $9,1b;\n" /*can continue read sr,write to gen clock*/
|
||||
"nop;\n"
|
||||
"li $9,0x11;\n" /*high cs*/
|
||||
"sb $9,5($8);\n"
|
||||
"jr $10;\n"
|
||||
"nop;\n"
|
||||
|
||||
"999:move $31,$15;\n"
|
||||
:::"$8","$9","$10","$11","$4","$5","$6","$15"
|
||||
);
|
||||
}
|
||||
#else
|
||||
//²Á³ýaddrËùÔڵĶÎ
|
||||
void Flash_Erase(_u32 addr)
|
||||
{
|
||||
FLASH_CMD_REG = FLASH_ERASE_CMD | (addr & FLASH_ADDR_MASK) ;
|
||||
|
||||
}
|
||||
|
||||
_u32 Flash_Write(_u32 addr, _u32 *data, _u32 num)
|
||||
{
|
||||
FLASH_CMD_REG = FLASH_PAGE_LATCH_CLEAR;
|
||||
/*wait interrupt ? Should I disable other int??????*/
|
||||
//debug("Page_latch is clean now...\n")
|
||||
|
||||
_u32 flash_block_mask = FLASH_BLOCK_SIZE - 1;
|
||||
_u32 *page_data = (_u32 *)(addr & ~flash_block_mask) ;
|
||||
_u32 *old_data = (_u32 *)(addr & ~flash_block_mask) ;
|
||||
_u32 i, j, offset;
|
||||
|
||||
j = 0;
|
||||
offset = ((addr & flash_block_mask)>>2);
|
||||
for(i=0; i<(FLASH_BLOCK_SIZE/4); i++)
|
||||
{
|
||||
if( (offset <= i) && (j < num) )
|
||||
page_data[i] = data[j++];
|
||||
else
|
||||
page_data[i] = old_data[i];
|
||||
}
|
||||
|
||||
Flash_Erase(addr);
|
||||
/*wait interrupt ? */
|
||||
//debug("Flash page is clean now...\n")
|
||||
|
||||
FLASH_CMD_REG = FLASH_WRITE_CMD | (addr & FLASH_ADDR_MASK) ;
|
||||
/*wait interrupt ? */
|
||||
//debug("Flash page write is finish...\n")
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user