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2alu

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This commit is contained in:
cxy004 2022-08-03 11:17:07 +08:00
parent db1aa1d615
commit c2fa121f92
9 changed files with 264 additions and 273 deletions
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44
src/Core/ALU.sv
View File

@ -4,31 +4,41 @@ module ALU(
input word_t a, b, input word_t a, b,
input ALUCtrl_t aluctrl, input ALUCtrl_t aluctrl,
output word_t aluout, output word_t aluout,
output logic valid,
output logic overflow output logic overflow
); );
wire logic alt = aluctrl.alt; logic alt;
logic [4:0] sa;
logic ex;
word_t sl, sr;
word_t b2;
word_t sum;
logic lt, ltu;
wire logic [4:0] sa = a[4:0]; assign alt = aluctrl.alt;
wire logic ex = alt & b[31];
wire word_t sl = b << sa; assign sa = a[4:0];
assign ex = alt & b[31];
assign sl = b << sa;
/* verilator lint_off WIDTH */ /* verilator lint_off WIDTH */
wire word_t sr = {{31{ex}}, b} >> sa; assign sr = {{31{ex}}, b} >> sa;
/* verilator lint_on WIDTH */ /* verilator lint_on WIDTH */
wire word_t b2 = alt ? ~b : b; assign b2 = alt ? ~b : b;
wire word_t sum;
wire logic lt, ltu;
/* verilator lint_off WIDTH */ /* verilator lint_off WIDTH */
assign {lt, ltu, sum} = {a[31], 1'b0, a} + {b2[31], 1'b1, b2} + alt; // alt for cin(CARRY4) at synthesis assign {lt, ltu, sum} = {a[31], 1'b0, a} + {b2[31], 1'b1, b2} + alt; // alt for cin(CARRY4) at synthesis
/* verilator lint_on WIDTH */ /* verilator lint_on WIDTH */
assign aluout = (aluctrl.f_sl ? sl : 32'b0)
| (aluctrl.f_sr ? sr : 32'b0) assign valid = ~aluctrl.f_mov | b == 32'h0 ^ alt;
| (aluctrl.f_add ? sum : 32'b0) assign aluout = (aluctrl.f_sl ? sl : 32'h0)
| (aluctrl.f_and ? a & b : 32'b0) | (aluctrl.f_sr ? sr : 32'h0)
| (aluctrl.f_or ? alt ? ~(a | b) : a | b : 32'b0) | (aluctrl.f_add ? sum : 32'h0)
| (aluctrl.f_xor ? a ^ b : 32'b0) | (aluctrl.f_and ? a & b : 32'h0)
| (aluctrl.f_slt ? {31'b0, lt } : 32'b0) | (aluctrl.f_or ? alt ? ~(a | b) : a | b : 32'h0)
| (aluctrl.f_sltu ? {31'b0, ltu} : 32'b0) | (aluctrl.f_xor ? a ^ b : 32'h0)
| (aluctrl.f_mova ? a : 32'b0); | (aluctrl.f_slt ? {31'b0, lt } : 32'h0)
| (aluctrl.f_sltu ? {31'b0, ltu} : 32'h0)
| (aluctrl.f_mov ? a : 32'h0);
assign overflow = lt ^ sum[31]; assign overflow = lt ^ sum[31];
endmodule endmodule

19
src/Core/Controller.sv
View File

@ -36,16 +36,15 @@ module Controller (
// Take Care of BGO // Take Care of BGO
assign ctrl.BGO = ~inst[26] & (eq | inst[27] & ltz) | inst[26] & (~inst[27] & (~inst[28] & (inst[16] & ~ltz | ~inst[16] & ltz) | inst[28] & ~eq) | inst[27] & ~eq & ~ltz); assign ctrl.BGO = ~inst[26] & (eq | inst[27] & ltz) | inst[26] & (~inst[27] & (~inst[28] & (inst[16] & ~ltz | ~inst[16] & ltz) | inst[28] & ~eq) | inst[27] & ~eq & ~ltz);
assign ctrl.PRV = ~inst[31] & inst[30] & ~inst[29];
assign ctrl.SYSCALL = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[3] & inst[2] & ~inst[0]; assign ctrl.SYSCALL = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[3] & inst[2] & ~inst[0];
assign ctrl.BREAK = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[3] & inst[2] & ~inst[1] & inst[0]; assign ctrl.BREAK = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[3] & inst[2] & ~inst[1] & inst[0];
assign ctrl.ERET = ~inst[31] & inst[30] & inst[4]; assign ctrl.ERET = ~inst[31] & inst[30] & inst[4];
assign ctrl.OFA = ~inst[26] & ~inst[30] & (~inst[29] & ~inst[31] & ~inst[28] & ~inst[27] & inst[5] & ~inst[0] & ~inst[4] & ~inst[2] & ~inst[3] | inst[29] & ~inst[27] & ~inst[31] & ~inst[28]); assign ctrl.OFA = ~inst[26] & ~inst[30] & (~inst[29] & ~inst[31] & ~inst[28] & ~inst[27] & inst[5] & ~inst[0] & ~inst[4] & ~inst[2] & ~inst[3] | inst[29] & ~inst[27] & ~inst[31] & ~inst[28]);
assign ctrl.ES = ~inst[30] & (~inst[28] & ~inst[27] & (~inst[26] & (~inst[3] & inst[2] | inst[3] & (inst[1] | inst[4]) | inst[5]) | inst[26] & inst[19]) | inst[31]) | inst[29]; assign ctrl.ES = ~inst[30] & (~inst[28] & ~inst[27] & (~inst[26] & (~inst[3] & inst[2] | inst[3] & (inst[1] | inst[4]) | inst[5]) | inst[26] & inst[19]) | inst[31]) | inst[29];
assign ctrl.ET = ~inst[26] & ~inst[27] & ~inst[31] & (~inst[30] & ~inst[29] & ~inst[28] & (~inst[3] & ~inst[4] | inst[3] & inst[4] | inst[5]) | inst[30] & inst[29]); assign ctrl.ET = ~inst[31] & ~inst[27] & ~inst[26] & (~inst[30] & ~inst[29] & ~inst[28] & (inst[5] | (~inst[4] & (~inst[3] & ~inst[1] & ~inst[0] | inst[1]) | inst[4] & inst[3])) | inst[30] & inst[29]);
assign ctrl.DS = ~inst[26] & (~inst[28] & ~inst[30] & ~inst[31] & ~inst[29] & ~inst[27] & inst[3] & ~inst[1] & ~inst[4] & ~inst[2] | inst[28] & ~inst[29] & ~inst[31]) | inst[26] & ~inst[31] & ~inst[29] & (~inst[27] & ~inst[19] | inst[28]); assign ctrl.DS = ~inst[26] & (~inst[28] & ~inst[30] & ~inst[31] & ~inst[29] & ~inst[27] & inst[3] & ~inst[1] & ~inst[4] & ~inst[2] | inst[28] & ~inst[29] & ~inst[31]) | inst[26] & ~inst[31] & ~inst[29] & (~inst[27] & ~inst[19] | inst[28]);
assign ctrl.DT = ~inst[28] & ~inst[26] & ~inst[30] & ~inst[31] & ~inst[29] & ~inst[27] & inst[3] & inst[1] & ~inst[5] & ~inst[4] | inst[28] & ~inst[29] & ~inst[31] & ~inst[27]; assign ctrl.DT = ~inst[31] & ~inst[29] & inst[28] & ~inst[27];
assign ctrl.DP0 = ~inst[31] & (~inst[30] & (~inst[26] & (~inst[4] | ~inst[5] | inst[27] | inst[28]) | inst[26] & (~inst[19] | inst[27] | inst[28])) | inst[30] & (~inst[25] | inst[4]) | inst[29]) | inst[31] & inst[30]; assign ctrl.DP0 = ~inst[31] & (~inst[30] & (~inst[26] & (~inst[4] | ~inst[5] | inst[27] | inst[28]) | inst[26] & (~inst[19] | inst[27] | inst[28])) | inst[30] & (~inst[25] | inst[4]) | inst[29]) | inst[31] & inst[30];
assign ctrl.DP1 = ~inst[30] & (~inst[4] | inst[5] | inst[28] | inst[29] | inst[31] | inst[27] | inst[26]) | inst[30] & ~inst[29] & (inst[25] | inst[31]); assign ctrl.DP1 = ~inst[30] & (~inst[4] | inst[5] | inst[28] | inst[29] | inst[31] | inst[27] | inst[26]) | inst[30] & ~inst[29] & (inst[25] | inst[31]);
@ -58,11 +57,11 @@ module Controller (
assign ctrl.ECtrl.OP.f_xor = ~inst[31] & (~inst[28] & ~inst[26] & ~inst[27] & ~inst[29] & inst[5] & ~inst[0] & inst[2] & ~inst[4] & inst[1] | inst[28] & inst[27]); assign ctrl.ECtrl.OP.f_xor = ~inst[31] & (~inst[28] & ~inst[26] & ~inst[27] & ~inst[29] & inst[5] & ~inst[0] & inst[2] & ~inst[4] & inst[1] | inst[28] & inst[27]);
assign ctrl.ECtrl.OP.f_slt = ~inst[31] & ~inst[28] & (~inst[26] & (~inst[29] & inst[5] & ~inst[0] & ~inst[2] & (inst[3] | inst[4]) | inst[27]) | inst[26] & ~inst[29] & ~inst[27] & ~inst[16] & ~inst[18] & ~inst[20]); assign ctrl.ECtrl.OP.f_slt = ~inst[31] & ~inst[28] & (~inst[26] & (~inst[29] & inst[5] & ~inst[0] & ~inst[2] & (inst[3] | inst[4]) | inst[27]) | inst[26] & ~inst[29] & ~inst[27] & ~inst[16] & ~inst[18] & ~inst[20]);
assign ctrl.ECtrl.OP.f_sltu = ~inst[31] & ~inst[28] & (~inst[26] & ~inst[27] & ~inst[29] & inst[5] & inst[0] & ~inst[2] & (inst[3] | inst[4]) | inst[26] & (~inst[29] & ~inst[27] & inst[16] & ~inst[20] | inst[29] & inst[27])); assign ctrl.ECtrl.OP.f_sltu = ~inst[31] & ~inst[28] & (~inst[26] & ~inst[27] & ~inst[29] & inst[5] & inst[0] & ~inst[2] & (inst[3] | inst[4]) | inst[26] & (~inst[29] & ~inst[27] & inst[16] & ~inst[20] | inst[29] & inst[27]));
assign ctrl.ECtrl.OP.f_mova = ~inst[31] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[5] & inst[3] & inst[1]; assign ctrl.ECtrl.OP.f_mov = ~inst[31] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[5] & inst[3] & inst[1];
assign ctrl.ECtrl.OP.alt = ~inst[31] & ~inst[28] & (~inst[29] & ~inst[27] & (~inst[26] & (inst[1] & (inst[0] | inst[5]) | inst[4]) | inst[26] & ~inst[20]) | inst[29] & inst[27]); assign ctrl.ECtrl.OP.alt = ~inst[31] & ~inst[28] & (~inst[29] & ~inst[27] & (~inst[26] & (inst[4] | inst[1] & (inst[5] | inst[0])) | inst[26] & ~inst[20]) | inst[29] & inst[27]);
assign ctrl.ECtrl.SA = SA_t'({(~inst[27] & (~inst[26] & ((inst[3] & inst[1] | inst[2]) | inst[5]) | inst[26] & ~inst[20]) | inst[31]) | inst[29], (~inst[28] & (inst[2] | inst[3] | inst[5] | inst[29] | inst[26]) | inst[28] & (~inst[27] | ~inst[26])) | inst[31]}); assign ctrl.ECtrl.SA = SA_t'({(~inst[27] & (~inst[26] & ((inst[3] & inst[1] | inst[2]) | inst[5]) | inst[26] & ~inst[20]) | inst[31]) | inst[29], (~inst[28] & (inst[2] | inst[3] | inst[5] | inst[29] | inst[26]) | inst[28] & (~inst[27] | ~inst[26])) | inst[31]});
assign ctrl.ECtrl.SB = SB_t'({(inst[26] & ~inst[27] & ~inst[20] | inst[31]) | inst[29], inst[3] & ~inst[5] | inst[26]}); assign ctrl.ECtrl.SB = SB_t'({inst[31] | inst[29] | ~inst[27] & inst[26] & ~inst[20], inst[26] | inst[3] & ~inst[1]});
assign ctrl.MCtrl0.HW = ~inst[30] & ~inst[26] & ~inst[29] & ~inst[28] & ~inst[27] & inst[4] & (~inst[5] & ~inst[1] & inst[0] | inst[3]) | inst[30] & inst[29] & ~inst[1]; assign ctrl.MCtrl0.HW = ~inst[30] & ~inst[26] & ~inst[29] & ~inst[28] & ~inst[27] & inst[4] & (~inst[5] & ~inst[1] & inst[0] | inst[3]) | inst[30] & inst[29] & ~inst[1];
assign ctrl.MCtrl0.LW = ~inst[30] & ~inst[26] & ~inst[29] & ~inst[28] & ~inst[27] & inst[4] & (~inst[5] & inst[1] & inst[0] | inst[3]) | inst[30] & inst[29] & ~inst[1]; assign ctrl.MCtrl0.LW = ~inst[30] & ~inst[26] & ~inst[29] & ~inst[28] & ~inst[27] & inst[4] & (~inst[5] & inst[1] & inst[0] | inst[3]) | inst[30] & inst[29] & ~inst[1];
@ -88,13 +87,9 @@ module Controller (
assign ctrl.MCtrl1.CACHE_OP.index_or_hit = inst[20]; assign ctrl.MCtrl1.CACHE_OP.index_or_hit = inst[20];
assign ctrl.MCtrl1.CACHE_OP.writeback = ~inst[20] & ~inst[19] & inst[16] | inst[18]; assign ctrl.MCtrl1.CACHE_OP.writeback = ~inst[20] & ~inst[19] & inst[16] | inst[18];
assign ctrl.Trap.TEN = ~inst[29] & (~inst[26] & ~inst[30] & ~inst[31] & ~inst[28] & ~inst[27] & inst[4] & inst[5] | inst[26] & ~inst[31] & ~inst[28] & ~inst[27] & inst[19]); assign ctrl.Trap.TEN = ~inst[31] & ~inst[29] & ~inst[28] & ~inst[27] & (~inst[30] & ~inst[26] & inst[5] & inst[4] | inst[26] & inst[19]);
assign ctrl.Trap.TP = TrapOp_t'({~inst[26] & inst[2] | inst[26] & inst[18], ~inst[26] & inst[1] | inst[26] & inst[17]}); assign ctrl.Trap.TP = TrapOp_t'({~inst[26] & inst[2] | inst[26] & inst[18], ~inst[26] & inst[1] | inst[26] & inst[17]});
logic mov, rw, eqz; assign ctrl.WCtrl.RW = ctrl.RD != 5'b00000 & (~inst[30] & (~inst[26] & (~inst[27] & (~inst[31] & (~inst[28] & (~inst[4] & (~inst[3] | ~inst[2] & (inst[0] | inst[1])) | inst[4] & ~inst[5] & ~inst[3] & ~inst[0]) | inst[29]) | inst[31] & ~inst[29]) | inst[27] & (~inst[31] & inst[29] | inst[31] & ~inst[29])) | inst[26] & (~inst[29] & (~inst[27] & ~inst[28] & inst[20] | inst[27] & ~inst[28] | inst[31]) | inst[29] & ~inst[31])) | inst[30] & ~inst[31] & ~inst[3] & (~inst[29] & ~inst[25] & ~inst[23] | inst[29] & inst[1]));
assign mov = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[5] & ~inst[4] & inst[3] & ~inst[2] & inst[1];
assign rw = ~inst[30] & (~inst[26] & (~inst[27] & (~inst[31] & (~inst[28] & (~inst[4] & (~inst[3] | ~inst[2] & (inst[0] | inst[1])) | inst[4] & ~inst[5] & ~inst[3] & ~inst[0]) | inst[29]) | inst[31] & ~inst[29]) | inst[27] & (~inst[31] & inst[29] | inst[31] & ~inst[29])) | inst[26] & (~inst[29] & (~inst[27] & ~inst[28] & inst[20] | inst[27] & ~inst[28] | inst[31]) | inst[29] & ~inst[31])) | inst[30] & ~inst[31] & ~inst[3] & (~inst[29] & ~inst[25] & ~inst[23] | inst[29] & inst[1]);
assign eqz = rt == 32'h0;
assign ctrl.WCtrl.RW = ctrl.RD != 5'b00000 & (~mov | ~inst[0] & eqz | inst[0] & ~eqz) & rw;
endmodule endmodule

170
src/Core/Datapath.sv
View File

@ -119,6 +119,8 @@ module Datapath (
logic D_IB_TLBInvalid; logic D_IB_TLBInvalid;
logic D_IB_AddressError; logic D_IB_AddressError;
logic D_IA_HazardALU2;
logic D_IB_HazardALU2;
logic D_IA_Hazard; logic D_IA_Hazard;
logic D_IB_Hazard; logic D_IB_Hazard;
@ -131,19 +133,20 @@ module Datapath (
word_t E_I0_A; word_t E_I0_A;
word_t E_I0_B; word_t E_I0_B;
logic E_I0_ALUvalid;
logic E_I0_Overflow; logic E_I0_Overflow;
logic E_I0_NowExcValid; logic E_I0_NowExcValid;
logic E_I0_NowExcValidWithoutOF;
logic E_I0_PrevExcValid; logic E_I0_PrevExcValid;
logic [4:0] E_I0_PrevExcCode; logic [4:0] E_I0_PrevExcCode;
logic E_I0_PrevERET; logic E_I0_PrevERET;
logic E_I0_PrevREFILL; logic E_I0_PrevREFILL;
logic E_I0_ExcValidWithoutOF;
word_t E_I1_A; word_t E_I1_A;
word_t E_I1_B; word_t E_I1_B;
word_t E_I1_ADDR; word_t E_I1_ADDR;
logic E_I1_ALUvalid;
logic E_I1_Overflow; logic E_I1_Overflow;
WCtrl_t E_I1_NowWCtrl;
logic E_I1_STRBERROR; logic E_I1_STRBERROR;
logic E_I1_NowExcValid; logic E_I1_NowExcValid;
logic E_I1_NowExcValidWithoutOF; logic E_I1_NowExcValidWithoutOF;
@ -199,6 +202,15 @@ module Datapath (
word_t M_I1_MDataUR; word_t M_I1_MDataUR;
word_t M_I1_MData; word_t M_I1_MData;
word_t M_I0_A;
word_t M_I0_B;
logic M_I0_ALUvalid;
logic M_I0_Overflow;
WCtrl_t M_I0_NowWCtrl;
logic M_I0_NowExcValid;
logic M_I0_PrevExcValid;
logic [4:0] M_I0_PrevExcCode;
logic M_I0_DIV_valid; logic M_I0_DIV_valid;
word_t M_I0_DIVH; word_t M_I0_DIVH;
word_t M_I0_DIVL; word_t M_I0_DIVL;
@ -290,7 +302,7 @@ module Datapath (
assign rstD = D_IA_valid & (D.IA.B & D.IA.BGO | D.IA.JR | D.IA.J) & D_IB_valid & D_readygo; assign rstD = D_IA_valid & (D.IA.B & D.IA.BGO | D.IA.JR | D.IA.J) & D_IB_valid & D_readygo;
assign rstM = C0.cpu_exception.ExcValid; assign rstM = C0.cpu_exception.ExcValid;
assign PF_go = ~D.IA_ExcValid & ~D.IB_ExcValid & ~E_I0_ExcValidWithoutOF & ~E_I1_ExcValidWithoutOF assign PF_go = ~D.IA_ExcValid & ~D.IB_ExcValid & ~E.I0.ExcValid & ~E_I1_ExcValidWithoutOF
& (~D_IB_valid | ~D.IA.JR | PF_pcjr[1:0] == 2'b00); & (~D_IB_valid | ~D.IA.JR | PF_pcjr[1:0] == 2'b00);
assign fetch.req = M_exception.ExcValid assign fetch.req = M_exception.ExcValid
| PF_go & (~D_IB_valid & ~fetch.data_ok | (~D.IA.BJRJ | D_readygo) | PF_go & (~D_IB_valid & ~fetch.data_ok | (~D.IA.BJRJ | D_readygo)
@ -456,8 +468,7 @@ module Datapath (
| D_IA_ri | D_IA_cpu | D_IA_ri | D_IA_cpu
| D_IA_TLBRefill | D_IA_TLBInvalid | D_IA_TLBRefill | D_IA_TLBInvalid
| D_IA_AddressError | D_IA_AddressError
| D.IA.SYSCALL | D.IA.BREAK | D.IA.ERET | D.IA.SYSCALL | D.IA.BREAK | D.IA.ERET);
| D.IA.PRV & ~C0.cp0_in_kernel);
assign D.IA_ERET = D_IA_valid & D.IA_pc[1:0] == 2'b00 & ~D_IA_TLBRefill & ~D_IA_TLBInvalid & ~D_IA_AddressError & ~D_IA_ri & ~D_IA_cpu & D.IA.ERET; assign D.IA_ERET = D_IA_valid & D.IA_pc[1:0] == 2'b00 & ~D_IA_TLBRefill & ~D_IA_TLBInvalid & ~D_IA_AddressError & ~D_IA_ri & ~D_IA_cpu & D.IA.ERET;
assign D.IA_REFILL = D_IA_valid & D.IB_pc[1:0] == 2'b00 & D_IA_TLBRefill; assign D.IA_REFILL = D_IA_valid & D.IB_pc[1:0] == 2'b00 & D_IA_TLBRefill;
assign D.IA_ExcCode = D.IA_pc[1:0] != 2'b00 | D_IA_AddressError ? `EXCCODE_ADEL assign D.IA_ExcCode = D.IA_pc[1:0] != 2'b00 | D_IA_AddressError ? `EXCCODE_ADEL
@ -474,8 +485,7 @@ module Datapath (
| D_IB_TLBRefill | D_IB_TLBInvalid | D_IB_TLBRefill | D_IB_TLBInvalid
| D_IB_AddressError | D_IB_AddressError
| D.IB.SYSCALL | D.IB.BREAK | D.IB.ERET | D.IB.SYSCALL | D.IB.BREAK | D.IB.ERET
| D.IB_Delay & D.IB.BJRJ | D.IB_Delay & D.IB.BJRJ);
| D.IB.PRV & ~C0.cp0_in_kernel);
assign D.IB_ERET = D_IB_valid & D.IB_pc[1:0] == 2'b00 & ~D_IB_TLBRefill & ~D_IB_TLBInvalid & ~D_IB_AddressError & ~D_IB_ri & ~D_IB_cpu & D.IB.ERET & ~D.IB_Delay; assign D.IB_ERET = D_IB_valid & D.IB_pc[1:0] == 2'b00 & ~D_IB_TLBRefill & ~D_IB_TLBInvalid & ~D_IB_AddressError & ~D_IB_ri & ~D_IB_cpu & D.IB.ERET & ~D.IB_Delay;
assign D.IB_REFILL = D_IB_valid & D.IB_pc[1:0] == 2'b00 & D_IB_TLBRefill; assign D.IB_REFILL = D_IB_valid & D.IB_pc[1:0] == 2'b00 & D_IB_TLBRefill;
// EXCCODE_BP and EXCCODE_SYSCALL -> exc.txt // EXCCODE_BP and EXCCODE_SYSCALL -> exc.txt
@ -491,21 +501,34 @@ module Datapath (
: `EXCCODE_RI; : `EXCCODE_RI;
assign D.IB_Delay = D.IA.BJRJ; assign D.IB_Delay = D.IA.BJRJ;
// D.Dispatch
// Not Arith -> Arith
assign D_IA_Hazard = E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.ES & ~E.I0.MCtrl.RS0[2]
| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.ET & ~E.I0.MCtrl.RS0[2]
// Load -> Arith // Load -> Arith
| E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.ES & E.I1.MCtrl.MR assign D_IA_HazardALU2 = E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.ES & E.I1.MCtrl.MR
| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.ET & E.I1.MCtrl.MR | E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.ET & E.I1.MCtrl.MR;
// Load -> Arith
assign D_IB_HazardALU2 = E.I1.WCtrl.RW & D.IB.RS == E.I1.RD & D.IB.ES & E.I1.MCtrl.MR
| E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & D.IB.ET & E.I1.MCtrl.MR
// Arith -> Arith
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ES
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ET;
assign D.A = ~(D.IA.DP0 & D.IA.DP1 | D.IA_ExcValid) ? D.IA.DP1 : D.IB.DP0 & ~D_IA_HazardALU2;
// D.Dispatch
assign D_IA_Hazard = D_IA_HazardALU2 & D.A
// Not Arith -> Arith
| E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.ES & ~E.I0.MCtrl_ALU1
| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.ET & ~E.I0.MCtrl_ALU1
// Load -> MulDiv
| E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.MCtrl0.HLS[2] & E.I1.MCtrl.MR
| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.MCtrl0.HLS[2] & E.I1.MCtrl.MR
// Arith -> B / JR // Arith -> B / JR
| E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.DS | E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.DS
| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.DT | E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.DT
| E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.DS | E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.DS
| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.DT | E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.DT
// Not Arith -> B / JR // Not Arith -> B / JR
| M.I0.WCtrl.RW & D.IA.RS == M.I0.RD & D.IA.DS & ~M.I0.MCtrl.RS0[2] | M.I0.WCtrl.RW & D.IA.RS == M.I0.RD & D.IA.DS & ~M.I0.MCtrl_ALU1
| M.I0.WCtrl.RW & D.IA.RT == M.I0.RD & D.IA.DT & ~M.I0.MCtrl.RS0[2] | M.I0.WCtrl.RW & D.IA.RT == M.I0.RD & D.IA.DT & ~M.I0.MCtrl_ALU1
// Load -> B / JR // Load -> B / JR
| M.I1.WCtrl.RW & D.IA.RS == M.I1.RD & D.IA.DS & M.I1.MCtrl.MR | M.I1.WCtrl.RW & D.IA.RS == M.I1.RD & D.IA.DS & M.I1.MCtrl.MR
| M.I1.WCtrl.RW & D.IA.RT == M.I1.RD & D.IA.DT & M.I1.MCtrl.MR | M.I1.WCtrl.RW & D.IA.RT == M.I1.RD & D.IA.DT & M.I1.MCtrl.MR
@ -514,32 +537,25 @@ module Datapath (
| E.I0.MCtrl.C0W & D.IA.MCtrl1.TLBP & E.I0.MCtrl.C0D == C0_ENTRYHI | E.I0.MCtrl.C0W & D.IA.MCtrl1.TLBP & E.I0.MCtrl.C0D == C0_ENTRYHI
; ;
assign D_IB_Hazard = D_IB_HazardALU2 & ~D.A
// Not Arith -> Arith // Not Arith -> Arith
assign D_IB_Hazard = E.I0.WCtrl.RW & D.IB.RS == E.I0.RD & D.IB.ES & ~E.I0.MCtrl.RS0[2] | E.I0.WCtrl.RW & D.IB.RS == E.I0.RD & D.IB.ES & ~E.I0.MCtrl_ALU1
| E.I0.WCtrl.RW & D.IB.RT == E.I0.RD & D.IB.ET & ~E.I0.MCtrl.RS0[2] | E.I0.WCtrl.RW & D.IB.RT == E.I0.RD & D.IB.ET & ~E.I0.MCtrl_ALU1
// Load -> Arith
| E.I1.WCtrl.RW & D.IB.RS == E.I1.RD & D.IB.ES & E.I1.MCtrl.MR
| E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & D.IB.ET & E.I1.MCtrl.MR
// Arith -> Arith
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ES
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ET
// Load -> MulDiv // Load -> MulDiv
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.MCtrl0.HLS[2] & ~D.IA.DP0 | E.I1.WCtrl.RW & D.IB.RS == E.I1.RD & D.IB.MCtrl0.HLS[2] & E.I1.MCtrl.MR
| E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & D.IB.MCtrl0.HLS[2] & E.I1.MCtrl.MR
// Load -> Arith
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ES & ~D.IA.DP0
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ET & ~D.IA.DP0
// Arith / Load -> MulDiv
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.MCtrl0.HLS[2]
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl0.HLS[2]
// Load -> C0 // Load -> C0
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl0.C0W & ~D.IA.DP0 | D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl0.C0W & ~D.IA.DP0
// Not Arith -> Store // Not Arith -> Store
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl1.MWR & ~D.IA.DP1 | D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl1.MWR & ~D.IA.DP1
// Not Arith -> LWL/LWR // Not Arith -> LWL/LWR
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & |D.IB.MCtrl1.ALR & ~D.IA.DP1 | D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & |D.IB.MCtrl1.ALR & ~D.IA.DP1
// Any -> MOVN/MOVZ
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.DT
// Arith -> MOVN/MOVZ
| E.I0.WCtrl.RW & D.IB.RT == E.I0.RD & D.IB.DT
| E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & D.IB.DT
// Not Arith -> MOVN/MOVZ
| M.I0.WCtrl.RW & D.IB.RT == M.I0.RD & D.IB.DT & ~M.I0.MCtrl.RS0[2]
// Load -> MOVN/MOVZ
| M.I1.WCtrl.RW & D.IB.RT == M.I1.RD & D.IB.DT & M.I1.MCtrl.MR
// CP0 Execution Hazards // CP0 Execution Hazards
// Hazards Related to the TLB // Hazards Related to the TLB
| D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBR & D.IA.MCtrl0.C0D == C0_INDEX | D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBR & D.IA.MCtrl0.C0D == C0_INDEX
@ -563,8 +579,6 @@ module Datapath (
| D.IA.MCtrl0.C0W & D.IB.ERET & D.IA.MCtrl0.C0D == C0_EPC | D.IA.MCtrl0.C0W & D.IB.ERET & D.IA.MCtrl0.C0D == C0_EPC
; ;
assign D.A = (D.IA.DP0 & D.IA.DP1 | D.IA_ExcValid) ? D.IB.DP0 : D.IA.DP1;
assign D_IA_can_dispatch = ~D_IA_valid | D.IA_ExcValid | ~D_IA_Hazard & (~D.IA.BJRJ | D_IB_valid); assign D_IA_can_dispatch = ~D_IA_valid | D.IA_ExcValid | ~D_IA_Hazard & (~D.IA.BJRJ | D_IB_valid);
assign D_IB_can_dispatch = ~D_IB_valid | D.IB_ExcValid & ~(D.IB.ERET & ~D.IB_Delay) | ~D_IB_Hazard & ~D.IB.BJRJ & (D.A ? D.IB.DP0 : D.IB.DP1); assign D_IB_can_dispatch = ~D_IB_valid | D.IB_ExcValid & ~(D.IB.ERET & ~D.IB_Delay) | ~D_IB_Hazard & ~D.IB.BJRJ & (D.A ? D.IB.DP0 : D.IB.DP1);
@ -603,6 +617,7 @@ module Datapath (
assign D.I0.sa = D.A ? D.IB_sa : D.IA_sa; assign D.I0.sa = D.A ? D.IB_sa : D.IA_sa;
assign D.I0.ECtrl = D.A ? D.IB.ECtrl : D.IA.ECtrl; assign D.I0.ECtrl = D.A ? D.IB.ECtrl : D.IA.ECtrl;
assign D.I0.MCtrl = D.A ? D.IB.MCtrl0 : D.IA.MCtrl0; assign D.I0.MCtrl = D.A ? D.IB.MCtrl0 : D.IA.MCtrl0;
assign D.I0.MCtrl_ALU1 = D.I0.MCtrl.RS0[2] & (D.A ? ~D_IB_HazardALU2 : ~D_IA_HazardALU2);
assign D.I0.RD = D.A ? D.IB.RD : D.IA.RD; assign D.I0.RD = D.A ? D.IB.RD : D.IA.RD;
assign D.I0.WCtrl = D.A ? D.IB.WCtrl : D.IA.WCtrl; assign D.I0.WCtrl = D.A ? D.IB.WCtrl : D.IA.WCtrl;
@ -740,13 +755,13 @@ module Datapath (
E.en, E.en,
E.I0.ECtrl E.I0.ECtrl
); );
ffenrc #(19) E_I0_MCtrl_ff ( ffenrc #(20) E_I0_MCtrl_ff (
clk, clk,
rst | rstM, rst | rstM,
D.I0.MCtrl, {D.I0.MCtrl, D.I0.MCtrl_ALU1},
E.en, E.en,
~D_go | ~D_I0_go, ~D_go | ~D_I0_go,
E.I0.MCtrl {E.I0.MCtrl, E.I0.MCtrl_ALU1}
); );
ffenrc #(5 + 1) E_I0_WCtrl_ff ( ffenrc #(5 + 1) E_I0_WCtrl_ff (
clk, clk,
@ -829,14 +844,12 @@ module Datapath (
); );
// E.Exc // E.Exc
assign E_I0_NowExcValidWithoutOF = C0_int & E_valid; assign E_I0_NowExcValid = C0_int & E_valid;
assign E_I0_NowExcValid = E_I0_NowExcValidWithoutOF | E_I0_Overflow & E.I0.OFA;
assign E_I0_ExcValidWithoutOF = E_I0_PrevExcValid | E_I0_NowExcValidWithoutOF;
assign E.I0.ExcValid = E_I0_PrevExcValid | E_I0_NowExcValid; assign E.I0.ExcValid = E_I0_PrevExcValid | E_I0_NowExcValid;
assign E.I0.ERET = E_I0_PrevERET & ~C0_int; assign E.I0.ERET = E_I0_PrevERET & ~C0_int;
assign E.I0.REFILL = E_I0_PrevREFILL & ~C0_int; assign E.I0.REFILL = E_I0_PrevREFILL & ~C0_int;
assign E.I0.ExcCode = C0_int ? 5'h0 assign E.I0.ExcCode = C0_int ? 5'h0
: E_I0_PrevExcValid ? E_I0_PrevExcCode : `EXCCODE_OV; : E_I0_PrevExcCode;
assign E_I1_NowExcValidWithoutOF = C0_int & E_valid | E.I1.MCtrl.MR & E_I1_STRBERROR; assign E_I1_NowExcValidWithoutOF = C0_int & E_valid | E.I1.MCtrl.MR & E_I1_STRBERROR;
assign E_I1_NowExcValid = E_I1_NowExcValidWithoutOF | E_I1_Overflow & E.I1.OFA; assign E_I1_NowExcValid = E_I1_NowExcValidWithoutOF | E_I1_Overflow & E.I1.OFA;
@ -851,7 +864,7 @@ module Datapath (
assign E.I1.BadVAddr = E_I1_PrevExcValid ? E.I1.pc : E.I1.ALUOut; assign E.I1.BadVAddr = E_I1_PrevExcValid ? E.I1.pc : E.I1.ALUOut;
assign E_I0_go = ~E_I0_NowExcValid & (~E.A | ~E_I1_NowExcValid); assign E_I0_go = ~E_I0_NowExcValid & (~E.A | ~E_I1_NowExcValid);
assign E_I1_goWithoutOF = ~E_I1_NowExcValidWithoutOF & (E.A | ~E_I0_NowExcValidWithoutOF); assign E_I1_goWithoutOF = ~E_I1_NowExcValidWithoutOF & (E.A | ~E_I0_NowExcValid);
assign E_I1_go = ~E_I1_NowExcValid & (E.A | ~E_I0_NowExcValid); assign E_I1_go = ~E_I1_NowExcValid & (E.A | ~E_I0_NowExcValid);
// E.I0.ALU // E.I0.ALU
@ -875,6 +888,7 @@ module Datapath (
E_I0_B, E_I0_B,
E.I0.ECtrl.OP, E.I0.ECtrl.OP,
E.I0.ALUOut, E.I0.ALUOut,
E_I0_ALUvalid,
E_I0_Overflow E_I0_Overflow
); );
@ -933,8 +947,10 @@ module Datapath (
E_I1_B, E_I1_B,
E.I1.ECtrl.OP, E.I1.ECtrl.OP,
E.I1.ALUOut, E.I1.ALUOut,
E_I1_ALUvalid,
E_I1_Overflow E_I1_Overflow
); );
assign E_I1_NowWCtrl.RW = E.I1.WCtrl.RW & (E.I1.MCtrl.MR | E_I1_ALUvalid);
// E.I1.MEM // E.I1.MEM
memerror E_I1_memerror ( memerror E_I1_memerror (
@ -1030,7 +1046,15 @@ module Datapath (
{E.I0.ExcValid, E.I0.ERET, E.I0.REFILL, E.I0.ExcCode, E.I0.CE, E.I0.Delay}, {E.I0.ExcValid, E.I0.ERET, E.I0.REFILL, E.I0.ExcCode, E.I0.CE, E.I0.Delay},
M.en, M.en,
~E_go, ~E_go,
{M.I0.ExcValid, M.I0.ERET, M.I0.REFILL, M.I0.ExcCode, M.I0.CE, M.I0.Delay} {M_I0_PrevExcValid, M.I0.ERET, M.I0.REFILL, M_I0_PrevExcCode, M.I0.CE, M.I0.Delay}
);
ffenrc #(1) M_I0_ExcCtrl_ff (
clk,
rst | rstM,
E.I0.OFA,
M.en,
~E_go | ~E_I0_go,
M.I0.OFA
); );
ffen #(5 + 5) M_I0_RST_ff ( ffen #(5 + 5) M_I0_RST_ff (
clk, clk,
@ -1050,13 +1074,25 @@ module Datapath (
M.en, M.en,
M.I0.ALUOut M.I0.ALUOut
); );
ffenrc #(19) M_I0_MCtrl_ff ( ffen #(32 + 5) M_I0_IS_ff (
clk,
{E.I0.imm, E.I0.sa},
M.en,
{M.I0.imm, M.I0.sa}
);
ffen #(14) M_I0_ECtrl_ff (
clk,
E.I0.ECtrl,
M.en,
M.I0.ECtrl
);
ffenrc #(20) M_I0_MCtrl_ff (
clk, clk,
rst | rstM, rst | rstM,
E.I0.MCtrl, {E.I0.MCtrl, E.I0.MCtrl_ALU1},
M.en, M.en,
~E_go | ~E_I0_go, ~E_go | ~E_I0_go,
M.I0.MCtrl {M.I0.MCtrl, M.I0.MCtrl_ALU1}
); );
ffenrc #(5 + 1) M_I0_WCtrl_ff ( ffenrc #(5 + 1) M_I0_WCtrl_ff (
clk, clk,
@ -1124,7 +1160,7 @@ module Datapath (
ffenrc #(5 + 1) M_I1_WCtrl_ff ( ffenrc #(5 + 1) M_I1_WCtrl_ff (
clk, clk,
rst | rstM, rst | rstM,
{E.I1.RD, E.I1.WCtrl}, {E.I1.RD, E_I1_NowWCtrl},
M.en, M.en,
~E_go | ~E_I1_go, ~E_go | ~E_I1_go,
{M.I1.RD, M.I1.WCtrl} {M.I1.RD, M.I1.WCtrl}
@ -1146,6 +1182,10 @@ module Datapath (
dTLBExcValid, dTLBExcValid,
{dTLBRefillB, dTLBInvalidB, dTLBModifiedB, dAddressErrorB} {dTLBRefillB, dTLBInvalidB, dTLBModifiedB, dAddressErrorB}
); );
assign M_I0_NowExcValid = M_I0_Overflow & M.I0.OFA;
assign M.I0.ExcValid = M_I0_PrevExcValid | M_I0_NowExcValid;
assign M.I0.ExcCode = M_I0_PrevExcValid ? M_I0_PrevExcCode
: `EXCCODE_OV;
assign M_I1_NowExcValid = dTLBRefillB | dTLBInvalidB | dTLBModifiedB | dAddressErrorB | M_I1_Trap; assign M_I1_NowExcValid = dTLBRefillB | dTLBInvalidB | dTLBModifiedB | dAddressErrorB | M_I1_Trap;
assign M.I1.ExcValid = M_I1_PrevExcValid | M_I1_NowExcValid; assign M.I1.ExcValid = M_I1_PrevExcValid | M_I1_NowExcValid;
assign M.I1.REFILL = M_I1_PrevREFILL | dTLBRefillB; assign M.I1.REFILL = M_I1_PrevREFILL | dTLBRefillB;
@ -1156,8 +1196,8 @@ module Datapath (
: dTLBInvalidB ? M.I1.MCtrl.MWR ? `EXCCODE_TLBS : `EXCCODE_TLBL : dTLBInvalidB ? M.I1.MCtrl.MWR ? `EXCCODE_TLBS : `EXCCODE_TLBL
: `EXCCODE_MOD; : `EXCCODE_MOD;
assign M_I0_go = ~M.A | ~M_I1_NowExcValid; assign M_I0_go = ~M_I0_NowExcValid & (~M.A | ~M_I1_NowExcValid);
assign M_I1_go = ~M_I1_NowExcValid; assign M_I1_go = ~M_I1_NowExcValid & (M.A | ~M_I0_NowExcValid);
assign {M_exception, M_exception_REFILL} = { assign {M_exception, M_exception_REFILL} = {
M.I1.ExcValid | M.I0.ExcValid, M.I1.ExcValid | M.I0.ExcValid,
@ -1174,6 +1214,32 @@ module Datapath (
M_exception.ERET & M.en M_exception.ERET & M.en
}; };
// M.I0.ALU
mux4 #(32) M_I0_A_mux (
{27'b0, M.I0.sa},
M.I0.pc,
32'd0,
M_I0_ForwardS,
M.I0.ECtrl.SA,
M_I0_A
);
mux3 #(32) M_I0_B_mux (
M_I0_ForwardT,
32'd8,
M.I0.imm,
M.I0.ECtrl.SB,
M_I0_B
);
ALU M_I0_ALU (
M_I0_A,
M_I0_B,
M.I0.ECtrl.OP,
M.I0.ALUOut2,
M_I0_ALUvalid,
M_I0_Overflow
);
assign M_I0_NowWCtrl.RW = M.I0.WCtrl.RW & (~M.I0.MCtrl.RS0[2] | M_I0_ALUvalid);
// M.I0.MUL // M.I0.MUL
ffenr #(97) M_I0_MAS_ff ( ffenr #(97) M_I0_MAS_ff (
clk,rst, clk,rst,
@ -1222,7 +1288,7 @@ module Datapath (
HI, HI,
M_I0_MULTLB, M_I0_MULTLB,
C0_rdata, C0_rdata,
M.I0.ALUOut, M.I0.ALUOut2,
M.I0.MCtrl.RS0, M.I0.MCtrl.RS0,
M.I0.RDataW M.I0.RDataW
); );
@ -1417,7 +1483,7 @@ module Datapath (
ffenrc #(5 + 1) W_I0_WCtrl_ff ( ffenrc #(5 + 1) W_I0_WCtrl_ff (
clk, clk,
rst, rst,
{M.I0.RD, M.I0.WCtrl}, {M.I0.RD, M_I0_NowWCtrl},
W.en, W.en,
~M_go | ~M_I0_go, ~M_go | ~M_I0_go,
{W.I0.RD, W.I0.WCtrl} {W.I0.RD, W.I0.WCtrl}

30
src/include/defines.svh
View File

@ -2,7 +2,7 @@
`define DEFINES_SVH `define DEFINES_SVH
`define ENABLE_TLB `define ENABLE_TLB
`define ENABLE_CpU // `define ENABLE_CpU
`define XLEN 32 `define XLEN 32
`define PCRST 32'hBFC00000 `define PCRST 32'hBFC00000
@ -49,7 +49,7 @@ typedef struct packed {
logic f_xor; logic f_xor;
logic f_slt; logic f_slt;
logic f_sltu; logic f_sltu;
logic f_mova; logic f_mov;
logic alt; logic alt;
} ALUCtrl_t; } ALUCtrl_t;
@ -150,8 +150,6 @@ typedef struct packed {
} WCtrl_t; } WCtrl_t;
typedef struct packed { typedef struct packed {
logic PRV;
logic SYSCALL; logic SYSCALL;
logic BREAK; logic BREAK;
logic ERET; logic ERET;
@ -241,9 +239,10 @@ typedef struct packed {
word_t imm; word_t imm;
logic [4:0] sa; logic [4:0] sa;
ECtrl_t ECtrl; ECtrl_t ECtrl;
MCtrl0_t MCtrl; MCtrl0_t MCtrl;
logic MCtrl_ALU1; // critical
logic [4:0] RD; logic [4:0] RD;
WCtrl_t WCtrl; WCtrl_t WCtrl;
@ -301,10 +300,11 @@ typedef struct packed {
word_t imm; word_t imm;
logic [4:0] sa; logic [4:0] sa;
ECtrl_t ECtrl; ECtrl_t ECtrl;
word_t ALUOut; word_t ALUOut;
MCtrl0_t MCtrl; MCtrl0_t MCtrl;
logic MCtrl_ALU1; // critical
logic [4:0] RD; logic [4:0] RD;
WCtrl_t WCtrl; WCtrl_t WCtrl;
@ -355,6 +355,7 @@ typedef struct packed {
logic [1:0] CE; logic [1:0] CE;
word_t BadVAddr; word_t BadVAddr;
logic Delay; logic Delay;
logic OFA;
logic [4:0] RS; logic [4:0] RS;
logic [4:0] RT; logic [4:0] RT;
@ -363,8 +364,15 @@ typedef struct packed {
word_t ALUOut; word_t ALUOut;
MCtrl0_t MCtrl; word_t imm;
word_t RDataW; logic [4:0] sa;
ECtrl_t ECtrl;
word_t ALUOut2;
MCtrl0_t MCtrl;
logic MCtrl_ALU1; // critical
word_t RDataW;
logic [4:0] RD; logic [4:0] RD;
WCtrl_t WCtrl; WCtrl_t WCtrl;

2
tools/ctrl_maker.py
View File

@ -1,4 +1,4 @@
with open('mctrl1.txt') as f: with open('ectrl.txt') as f:
lines = f.readlines() lines = f.readlines()
title = lines[0].split() title = lines[0].split()
items = [x.split() for x in lines[1:]] items = [x.split() for x in lines[1:]]

4
tools/ectrl.txt
View File

@ -6,8 +6,8 @@
32'b000000???????????????00000000100 SL ? RS 1 1 RT 0 0 ? ? ? // SLLV 32'b000000???????????????00000000100 SL ? RS 1 1 RT 0 0 ? ? ? // SLLV
32'b000000???????????????00000000110 SR 0 RS 1 1 RT 0 0 ? ? ? // SRLV 32'b000000???????????????00000000110 SR 0 RS 1 1 RT 0 0 ? ? ? // SRLV
32'b000000???????????????00000000111 SR 1 RS 1 1 RT 0 0 ? ? ? // SRAV 32'b000000???????????????00000000111 SR 1 RS 1 1 RT 0 0 ? ? ? // SRAV
32'b000000???????????????00000001010 MOVA ? RS 1 1 ? ? ? ? ? ? // MOVZ 32'b000000???????????????00000001010 MOV 0 RS 1 1 RT 0 0 ? ? ? // MOVZ
32'b000000???????????????00000001011 MOVA ? RS 1 1 ? ? ? ? ? ? // MOVN 32'b000000???????????????00000001011 MOV 1 RS 1 1 RT 0 0 ? ? ? // MOVN
32'b000000?????000000000000000001000 ? ? ? ? ? ? ? ? ? ? ? // JR 32'b000000?????000000000000000001000 ? ? ? ? ? ? ? ? ? ? ? // JR
32'b000000?????00000?????00000001001 ADD 0 PC 0 1 EIGHT 0 1 ? ? ? // JALR 32'b000000?????00000?????00000001001 ADD 0 PC 0 1 EIGHT 0 1 ? ? ? // JALR
32'b000000????????????????????001100 ? ? ? ? ? ? ? ? ? ? ? // SYSCALL 32'b000000????????????????????001100 ? ? ? ? ? ? ? ? ? ? ? // SYSCALL

4
tools/global.txt
View File

@ -6,8 +6,8 @@
32'b000000???????????????00000000100 0 0 0 0 1 1 0 0 1 1 // SLLV 32'b000000???????????????00000000100 0 0 0 0 1 1 0 0 1 1 // SLLV
32'b000000???????????????00000000110 0 0 0 0 1 1 0 0 1 1 // SRLV 32'b000000???????????????00000000110 0 0 0 0 1 1 0 0 1 1 // SRLV
32'b000000???????????????00000000111 0 0 0 0 1 1 0 0 1 1 // SRAV 32'b000000???????????????00000000111 0 0 0 0 1 1 0 0 1 1 // SRAV
32'b000000???????????????00000001010 0 0 0 0 1 0 0 1 1 1 // MOVZ 32'b000000???????????????00000001010 0 0 0 0 1 1 0 0 1 1 // MOVZ
32'b000000???????????????00000001011 0 0 0 0 1 0 0 1 1 1 // MOVN 32'b000000???????????????00000001011 0 0 0 0 1 1 0 0 1 1 // MOVN
32'b000000?????000000000000000001000 0 0 0 0 0 0 1 0 1 1 // JR 32'b000000?????000000000000000001000 0 0 0 0 0 0 1 0 1 1 // JR
32'b000000?????00000?????00000001001 0 0 0 0 0 0 1 0 1 1 // JALR 32'b000000?????00000?????00000001001 0 0 0 0 0 0 1 0 1 1 // JALR
32'b000000????????????????????001100 1 0 0 0 0 0 0 0 1 1 // SYSCALL 32'b000000????????????????????001100 1 0 0 0 0 0 0 0 1 1 // SYSCALL

88
tools/privilege.txt
View File

@ -1,88 +0,0 @@
////-------------------------------- PRV
32'b000000000000000000000?????001111 0 // SYNC (NOP)
32'b00000000000???????????????000000 0 // SLL
32'b00000000000???????????????000010 0 // SRL
32'b00000000000???????????????000011 0 // SRA
32'b000000???????????????00000000100 0 // SLLV
32'b000000???????????????00000000110 0 // SRLV
32'b000000???????????????00000000111 0 // SRAV
32'b000000???????????????00000001010 0 // MOVZ
32'b000000???????????????00000001011 0 // MOVN
32'b000000?????000000000000000001000 0 // JR
32'b000000?????00000?????00000001001 0 // JALR
32'b000000????????????????????001100 0 // SYSCALL
32'b000000????????????????????001101 0 // BREAK
32'b0000000000000000?????00000010000 0 // MFHI
32'b000000?????000000000000000010001 0 // MTHI
32'b0000000000000000?????00000010010 0 // MFLO
32'b000000?????000000000000000010011 0 // MTLO
32'b000000??????????0000000000011000 0 // MULT
32'b000000??????????0000000000011001 0 // MULTU
32'b000000??????????0000000000011010 0 // DIV
32'b000000??????????0000000000011011 0 // DIVU
32'b000000???????????????00000100000 0 // ADD
32'b000000???????????????00000100001 0 // ADDU
32'b000000???????????????00000100010 0 // SUB
32'b000000???????????????00000100011 0 // SUBU
32'b000000???????????????00000100100 0 // AND
32'b000000???????????????00000100101 0 // OR
32'b000000???????????????00000100110 0 // XOR
32'b000000???????????????00000100111 0 // NOR
32'b000000???????????????00000101010 0 // SLT
32'b000000???????????????00000101011 0 // SLTU
32'b000000????????????????????110000 0 // TGE
32'b000000????????????????????110001 0 // TGEU
32'b000000????????????????????110010 0 // TLT
32'b000000????????????????????110011 0 // TLTU
32'b000000????????????????????110100 0 // TEQ
32'b000000????????????????????110110 0 // TNE
32'b000001?????00000???????????????? 0 // BLTZ
32'b000001?????00001???????????????? 0 // BGEZ
32'b000001?????01000???????????????? 0 // TGEI
32'b000001?????01001???????????????? 0 // TGEIU
32'b000001?????01010???????????????? 0 // TLTI
32'b000001?????01011???????????????? 0 // TLTIU
32'b000001?????01110???????????????? 0 // TNEI
32'b000001?????01100???????????????? 0 // TEQI
32'b000001?????10000???????????????? 0 // BLTZAL
32'b000001?????10001???????????????? 0 // BGEZAL
32'b000010?????????????????????????? 0 // J
32'b000011?????????????????????????? 0 // JAL
32'b000100?????????????????????????? 0 // BEQ
32'b000101?????????????????????????? 0 // BNE
32'b000110?????00000???????????????? 0 // BLEZ
32'b000111?????00000???????????????? 0 // BGTZ
32'b001000?????????????????????????? 0 // ADDI
32'b001001?????????????????????????? 0 // ADDIU
32'b001010?????????????????????????? 0 // SLTI
32'b001011?????????????????????????? 0 // SLTIU
32'b001100?????????????????????????? 0 // ANDI
32'b001101?????????????????????????? 0 // ORI
32'b001110?????????????????????????? 0 // XORI
32'b00111100000????????????????????? 0 // LUI
32'b01000000000??????????00000000??? 1 // MFC0
32'b01000000100??????????00000000??? 1 // MTC0
32'b01000010000000000000000000000001 1 // TLBR
32'b01000010000000000000000000000010 1 // TLBWI
32'b01000010000000000000000000000110 1 // TLBWR
32'b01000010000000000000000000001000 1 // TLBP
32'b01000010000000000000000000011000 1 // ERET
32'b011100??????????0000000000000000 0 // MADD
32'b011100??????????0000000000000001 0 // MADDU
32'b011100??????????0000000000000100 0 // MSUB
32'b011100??????????0000000000000101 0 // MSUBU
32'b011100???????????????00000000010 0 // MUL
32'b100000?????????????????????????? 0 // LB
32'b100001?????????????????????????? 0 // LH
32'b100010?????????????????????????? 0 // LWL
32'b100011?????????????????????????? 0 // LW
32'b100100?????????????????????????? 0 // LBU
32'b100101?????????????????????????? 0 // LHU
32'b100110?????????????????????????? 0 // LWR
32'b101000?????????????????????????? 0 // SB
32'b101001?????????????????????????? 0 // SH
32'b101010?????????????????????????? 0 // SWL
32'b101011?????????????????????????? 0 // SW
32'b101110?????????????????????????? 0 // SWR
32'b101111?????????????????????????? 0 // CACHE
32'b110011?????????????????????????? 0 // PREF (NOP)

176
tools/wctrl.txt
View File

@ -1,88 +1,88 @@
////-------------------------------- MOV RW RD RD1 RD0 ////-------------------------------- RW RD RD1 RD0
32'b000000000000000000000?????001111 0 0 ? ? ? // SYNC (NOP) 32'b000000000000000000000?????001111 0 ? ? ? // SYNC (NOP)
32'b00000000000???????????????000000 0 1 RD 0 0 // SLL 32'b00000000000???????????????000000 1 RD 0 0 // SLL
32'b00000000000???????????????000010 0 1 RD 0 0 // SRL 32'b00000000000???????????????000010 1 RD 0 0 // SRL
32'b00000000000???????????????000011 0 1 RD 0 0 // SRA 32'b00000000000???????????????000011 1 RD 0 0 // SRA
32'b000000???????????????00000000100 0 1 RD 0 0 // SLLV 32'b000000???????????????00000000100 1 RD 0 0 // SLLV
32'b000000???????????????00000000110 0 1 RD 0 0 // SRLV 32'b000000???????????????00000000110 1 RD 0 0 // SRLV
32'b000000???????????????00000000111 0 1 RD 0 0 // SRAV 32'b000000???????????????00000000111 1 RD 0 0 // SRAV
32'b000000???????????????00000001010 1 1 RD 0 0 // MOVZ 32'b000000???????????????00000001010 1 RD 0 0 // MOVZ
32'b000000???????????????00000001011 1 1 RD 0 0 // MOVN 32'b000000???????????????00000001011 1 RD 0 0 // MOVN
32'b000000?????000000000000000001000 0 0 ? ? ? // JR 32'b000000?????000000000000000001000 0 ? ? ? // JR
32'b000000?????00000?????00000001001 0 1 RD 0 0 // JALR 32'b000000?????00000?????00000001001 1 RD 0 0 // JALR
32'b000000????????????????????001100 0 0 ? ? ? // SYSCALL 32'b000000????????????????????001100 0 ? ? ? // SYSCALL
32'b000000????????????????????001101 0 0 ? ? ? // BREAK 32'b000000????????????????????001101 0 ? ? ? // BREAK
32'b0000000000000000?????00000010000 0 1 RD 0 0 // MFHI 32'b0000000000000000?????00000010000 1 RD 0 0 // MFHI
32'b000000?????000000000000000010001 0 0 ? ? ? // MTHI 32'b000000?????000000000000000010001 0 ? ? ? // MTHI
32'b0000000000000000?????00000010010 0 1 RD 0 0 // MFLO 32'b0000000000000000?????00000010010 1 RD 0 0 // MFLO
32'b000000?????000000000000000010011 0 0 ? ? ? // MTLO 32'b000000?????000000000000000010011 0 ? ? ? // MTLO
32'b000000??????????0000000000011000 0 0 ? ? ? // MULT 32'b000000??????????0000000000011000 0 ? ? ? // MULT
32'b000000??????????0000000000011001 0 0 ? ? ? // MULTU 32'b000000??????????0000000000011001 0 ? ? ? // MULTU
32'b000000??????????0000000000011010 0 0 ? ? ? // DIV 32'b000000??????????0000000000011010 0 ? ? ? // DIV
32'b000000??????????0000000000011011 0 0 ? ? ? // DIVU 32'b000000??????????0000000000011011 0 ? ? ? // DIVU
32'b000000???????????????00000100000 0 1 RD 0 0 // ADD 32'b000000???????????????00000100000 1 RD 0 0 // ADD
32'b000000???????????????00000100001 0 1 RD 0 0 // ADDU 32'b000000???????????????00000100001 1 RD 0 0 // ADDU
32'b000000???????????????00000100010 0 1 RD 0 0 // SUB 32'b000000???????????????00000100010 1 RD 0 0 // SUB
32'b000000???????????????00000100011 0 1 RD 0 0 // SUBU 32'b000000???????????????00000100011 1 RD 0 0 // SUBU
32'b000000???????????????00000100100 0 1 RD 0 0 // AND 32'b000000???????????????00000100100 1 RD 0 0 // AND
32'b000000???????????????00000100101 0 1 RD 0 0 // OR 32'b000000???????????????00000100101 1 RD 0 0 // OR
32'b000000???????????????00000100110 0 1 RD 0 0 // XOR 32'b000000???????????????00000100110 1 RD 0 0 // XOR
32'b000000???????????????00000100111 0 1 RD 0 0 // NOR 32'b000000???????????????00000100111 1 RD 0 0 // NOR
32'b000000???????????????00000101010 0 1 RD 0 0 // SLT 32'b000000???????????????00000101010 1 RD 0 0 // SLT
32'b000000???????????????00000101011 0 1 RD 0 0 // SLTU 32'b000000???????????????00000101011 1 RD 0 0 // SLTU
32'b000000????????????????????110000 0 0 ? ? ? // TGE 32'b000000????????????????????110000 0 ? ? ? // TGE
32'b000000????????????????????110001 0 0 ? ? ? // TGEU 32'b000000????????????????????110001 0 ? ? ? // TGEU
32'b000000????????????????????110010 0 0 ? ? ? // TLT 32'b000000????????????????????110010 0 ? ? ? // TLT
32'b000000????????????????????110011 0 0 ? ? ? // TLTU 32'b000000????????????????????110011 0 ? ? ? // TLTU
32'b000000????????????????????110100 0 0 ? ? ? // TEQ 32'b000000????????????????????110100 0 ? ? ? // TEQ
32'b000000????????????????????110110 0 0 ? ? ? // TNE 32'b000000????????????????????110110 0 ? ? ? // TNE
32'b000001?????00000???????????????? 0 0 ? ? ? // BLTZ 32'b000001?????00000???????????????? 0 ? ? ? // BLTZ
32'b000001?????00001???????????????? 0 0 ? ? ? // BGEZ 32'b000001?????00001???????????????? 0 ? ? ? // BGEZ
32'b000001?????01000???????????????? 0 0 ? ? ? // TGEI 32'b000001?????01000???????????????? 0 ? ? ? // TGEI
32'b000001?????01001???????????????? 0 0 ? ? ? // TGEIU 32'b000001?????01001???????????????? 0 ? ? ? // TGEIU
32'b000001?????01010???????????????? 0 0 ? ? ? // TLTI 32'b000001?????01010???????????????? 0 ? ? ? // TLTI
32'b000001?????01011???????????????? 0 0 ? ? ? // TLTIU 32'b000001?????01011???????????????? 0 ? ? ? // TLTIU
32'b000001?????01110???????????????? 0 0 ? ? ? // TNEI 32'b000001?????01110???????????????? 0 ? ? ? // TNEI
32'b000001?????01100???????????????? 0 0 ? ? ? // TEQI 32'b000001?????01100???????????????? 0 ? ? ? // TEQI
32'b000001?????10000???????????????? 0 1 31 0 1 // BLTZAL 32'b000001?????10000???????????????? 1 31 0 1 // BLTZAL
32'b000001?????10001???????????????? 0 1 31 0 1 // BGEZAL 32'b000001?????10001???????????????? 1 31 0 1 // BGEZAL
32'b000010?????????????????????????? 0 0 ? ? ? // J 32'b000010?????????????????????????? 0 ? ? ? // J
32'b000011?????????????????????????? 0 1 31 0 1 // JAL 32'b000011?????????????????????????? 1 31 0 1 // JAL
32'b000100?????????????????????????? 0 0 ? ? ? // BEQ 32'b000100?????????????????????????? 0 ? ? ? // BEQ
32'b000101?????????????????????????? 0 0 ? ? ? // BNE 32'b000101?????????????????????????? 0 ? ? ? // BNE
32'b000110?????00000???????????????? 0 0 ? ? ? // BLEZ 32'b000110?????00000???????????????? 0 ? ? ? // BLEZ
32'b000111?????00000???????????????? 0 0 ? ? ? // BGTZ 32'b000111?????00000???????????????? 0 ? ? ? // BGTZ
32'b001000?????????????????????????? 0 1 RT 1 ? // ADDI 32'b001000?????????????????????????? 1 RT 1 ? // ADDI
32'b001001?????????????????????????? 0 1 RT 1 ? // ADDIU 32'b001001?????????????????????????? 1 RT 1 ? // ADDIU
32'b001010?????????????????????????? 0 1 RT 1 ? // SLTI 32'b001010?????????????????????????? 1 RT 1 ? // SLTI
32'b001011?????????????????????????? 0 1 RT 1 ? // SLTIU 32'b001011?????????????????????????? 1 RT 1 ? // SLTIU
32'b001100?????????????????????????? 0 1 RT 1 ? // ANDI 32'b001100?????????????????????????? 1 RT 1 ? // ANDI
32'b001101?????????????????????????? 0 1 RT 1 ? // ORI 32'b001101?????????????????????????? 1 RT 1 ? // ORI
32'b001110?????????????????????????? 0 1 RT 1 ? // XORI 32'b001110?????????????????????????? 1 RT 1 ? // XORI
32'b00111100000????????????????????? 0 1 RT 1 ? // LUI 32'b00111100000????????????????????? 1 RT 1 ? // LUI
32'b01000000000??????????00000000??? 0 1 RT 1 ? // MFC0 32'b01000000000??????????00000000??? 1 RT 1 ? // MFC0
32'b01000000100??????????00000000??? 0 0 ? ? ? // MTC0 32'b01000000100??????????00000000??? 0 ? ? ? // MTC0
32'b01000010000000000000000000000001 0 0 ? ? ? // TLBR 32'b01000010000000000000000000000001 0 ? ? ? // TLBR
32'b01000010000000000000000000000010 0 0 ? ? ? // TLBWI 32'b01000010000000000000000000000010 0 ? ? ? // TLBWI
32'b01000010000000000000000000000110 0 0 ? ? ? // TLBWR 32'b01000010000000000000000000000110 0 ? ? ? // TLBWR
32'b01000010000000000000000000001000 0 0 ? ? ? // TLBP 32'b01000010000000000000000000001000 0 ? ? ? // TLBP
32'b01000010000000000000000000011000 0 0 ? ? ? // ERET 32'b01000010000000000000000000011000 0 ? ? ? // ERET
32'b011100??????????0000000000000000 0 0 ? ? ? // MADD 32'b011100??????????0000000000000000 0 ? ? ? // MADD
32'b011100??????????0000000000000001 0 0 ? ? ? // MADDU 32'b011100??????????0000000000000001 0 ? ? ? // MADDU
32'b011100??????????0000000000000100 0 0 ? ? ? // MSUB 32'b011100??????????0000000000000100 0 ? ? ? // MSUB
32'b011100??????????0000000000000101 0 0 ? ? ? // MSUBU 32'b011100??????????0000000000000101 0 ? ? ? // MSUBU
32'b011100???????????????00000000010 0 1 RD 0 0 // MUL 32'b011100???????????????00000000010 1 RD 0 0 // MUL
32'b100000?????????????????????????? 0 1 RT 1 ? // LB 32'b100000?????????????????????????? 1 RT 1 ? // LB
32'b100001?????????????????????????? 0 1 RT 1 ? // LH 32'b100001?????????????????????????? 1 RT 1 ? // LH
32'b100010?????????????????????????? 0 1 RT 1 ? // LWL 32'b100010?????????????????????????? 1 RT 1 ? // LWL
32'b100011?????????????????????????? 0 1 RT 1 ? // LW 32'b100011?????????????????????????? 1 RT 1 ? // LW
32'b100100?????????????????????????? 0 1 RT 1 ? // LBU 32'b100100?????????????????????????? 1 RT 1 ? // LBU
32'b100101?????????????????????????? 0 1 RT 1 ? // LHU 32'b100101?????????????????????????? 1 RT 1 ? // LHU
32'b100110?????????????????????????? 0 1 RT 1 ? // LWR 32'b100110?????????????????????????? 1 RT 1 ? // LWR
32'b101000?????????????????????????? 0 0 ? ? ? // SB 32'b101000?????????????????????????? 0 ? ? ? // SB
32'b101001?????????????????????????? 0 0 ? ? ? // SH 32'b101001?????????????????????????? 0 ? ? ? // SH
32'b101010?????????????????????????? 0 0 ? ? ? // SWL 32'b101010?????????????????????????? 0 ? ? ? // SWL
32'b101011?????????????????????????? 0 0 ? ? ? // SW 32'b101011?????????????????????????? 0 ? ? ? // SW
32'b101110?????????????????????????? 0 0 ? ? ? // SWR 32'b101110?????????????????????????? 0 ? ? ? // SWR
32'b101111?????????????????????????? 0 0 ? ? ? // CACHE 32'b101111?????????????????????????? 0 ? ? ? // CACHE
32'b110011?????????????????????????? 0 0 ? ? ? // PREF (NOP) 32'b110011?????????????????????????? 0 ? ? ? // PREF (NOP)