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feat: reconfigure crossbar

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This commit is contained in:
Paul Pan 2022-07-29 18:26:27 +08:00
parent 7b33e4213a
commit bf7ee46645
2 changed files with 11 additions and 11 deletions
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20
sim/model/axi_crossbar.v
View File

@ -92,34 +92,34 @@ module axi_crossbar #
parameter M_SECURE = {M_COUNT{1'b0}}, parameter M_SECURE = {M_COUNT{1'b0}},
// Slave interface AW channel register type (input) // Slave interface AW channel register type (input)
// 0 to bypass, 1 for simple buffer, 2 for skid buffer // 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter S_AW_REG_TYPE = {S_COUNT{2'd0}}, parameter S_AW_REG_TYPE = {S_COUNT{2'd1}},
// Slave interface W channel register type (input) // Slave interface W channel register type (input)
// 0 to bypass, 1 for simple buffer, 2 for skid buffer // 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter S_W_REG_TYPE = {S_COUNT{2'd0}}, parameter S_W_REG_TYPE = {S_COUNT{2'd1}},
// Slave interface B channel register type (output) // Slave interface B channel register type (output)
// 0 to bypass, 1 for simple buffer, 2 for skid buffer // 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter S_B_REG_TYPE = {S_COUNT{2'd0}}, parameter S_B_REG_TYPE = {S_COUNT{2'd1}},
// Slave interface AR channel register type (input) // Slave interface AR channel register type (input)
// 0 to bypass, 1 for simple buffer, 2 for skid buffer // 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter S_AR_REG_TYPE = {S_COUNT{2'd0}}, parameter S_AR_REG_TYPE = {S_COUNT{2'd1}},
// Slave interface R channel register type (output) // Slave interface R channel register type (output)
// 0 to bypass, 1 for simple buffer, 2 for skid buffer // 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter S_R_REG_TYPE = {S_COUNT{2'd0}}, parameter S_R_REG_TYPE = {S_COUNT{2'd1}},
// Master interface AW channel register type (output) // Master interface AW channel register type (output)
// 0 to bypass, 1 for simple buffer, 2 for skid buffer // 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter M_AW_REG_TYPE = {M_COUNT{2'd0}}, parameter M_AW_REG_TYPE = {M_COUNT{2'd1}},
// Master interface W channel register type (output) // Master interface W channel register type (output)
// 0 to bypass, 1 for simple buffer, 2 for skid buffer // 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter M_W_REG_TYPE = {M_COUNT{2'd0}}, parameter M_W_REG_TYPE = {M_COUNT{2'd1}},
// Master interface B channel register type (input) // Master interface B channel register type (input)
// 0 to bypass, 1 for simple buffer, 2 for skid buffer // 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter M_B_REG_TYPE = {M_COUNT{2'd0}}, parameter M_B_REG_TYPE = {M_COUNT{2'd1}},
// Master interface AR channel register type (output) // Master interface AR channel register type (output)
// 0 to bypass, 1 for simple buffer, 2 for skid buffer // 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter M_AR_REG_TYPE = {M_COUNT{2'd0}}, parameter M_AR_REG_TYPE = {M_COUNT{2'd1}},
// Master interface R channel register type (input) // Master interface R channel register type (input)
// 0 to bypass, 1 for simple buffer, 2 for skid buffer // 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter M_R_REG_TYPE = {M_COUNT{2'd0}} parameter M_R_REG_TYPE = {M_COUNT{2'd1}}
) )
( (
input wire clk, input wire clk,

2
sim/sim_main.cpp
View File

@ -14,7 +14,7 @@ int main(int argc, char **argv, char **env) {
Verilated::mkdir("logs"); Verilated::mkdir("logs");
const int reset_time = 10; const int reset_time = 10;
const int time_limit = 20000; const int time_limit = 2000000;
Vtestbench_top *top = new Vtestbench_top; Vtestbench_top *top = new Vtestbench_top;