From bc549d8bd4141dc6ee940153d155e432e872e8a8 Mon Sep 17 00:00:00 2001 From: Paul Pan Date: Wed, 11 Aug 2021 12:58:02 +0800 Subject: [PATCH] 1. tlb control signals 2. exccode rename 3. tlb datapath partial Co-authored-by: cxy004 Co-authored-by: Hooo1941 --- .editorconfig | 5 ++ src/AXI/AXI.sv | 7 +- src/CP0/CP0.sv | 4 +- src/Core/Controller.sv | 17 +++-- src/Core/Datapath.sv | 148 +++++++++++++++++++++++++++------------- src/MyCPU.sv | 14 ++-- src/include/defines.svh | 53 +++++++++----- tools/RS0.txt | 48 ------------- tools/alusrc.sv | 57 ---------------- tools/ctrl.out.txt | 42 ------------ tools/ctrl.sv | 57 ---------------- tools/ctrl.txt | 58 ---------------- tools/ctrl_maker.py | 2 +- tools/global.txt | 69 +++++++++++++++++++ tools/instrqueue.sv | 16 ----- tools/iq.sv | 21 ------ tools/out1.txt | 19 ------ tools/out2.txt | 88 ------------------------ tools/rs0out.txt | 6 -- tools/tlb.txt | 69 +++++++++++++++++++ 20 files changed, 306 insertions(+), 494 deletions(-) delete mode 100644 tools/RS0.txt delete mode 100644 tools/alusrc.sv delete mode 100644 tools/ctrl.out.txt delete mode 100644 tools/ctrl.sv delete mode 100644 tools/ctrl.txt create mode 100644 tools/global.txt delete mode 100644 tools/instrqueue.sv delete mode 100644 tools/iq.sv delete mode 100644 tools/out1.txt delete mode 100644 tools/out2.txt delete mode 100644 tools/rs0out.txt create mode 100644 tools/tlb.txt diff --git a/.editorconfig b/.editorconfig index a255aa7..581101f 100644 --- a/.editorconfig +++ b/.editorconfig @@ -10,3 +10,8 @@ trim_trailing_whitespace = true [Makefile] indent_style = tab + +[tools/**/*.txt] +charset = utf-8 +indent_style = tab +indent_size = 8 \ No newline at end of file diff --git a/src/AXI/AXI.sv b/src/AXI/AXI.sv index 597a306..71641a5 100644 --- a/src/AXI/AXI.sv +++ b/src/AXI/AXI.sv @@ -26,8 +26,8 @@ module AXI ( // ============================== always_comb begin - inst.rdata = AXIRead.AXIReadData.rdata; - rdata.rdata = AXIRead.AXIReadData.rdata; + inst.rdata = AXIRead.AXIReadData.rdata; + rdata.rdata = AXIRead.AXIReadData.rdata; if (AXIRead.AXIReadData.rid == 0) begin inst.rvalid = AXIRead.AXIReadData.rvalid; @@ -57,12 +57,12 @@ module AXI ( AXIRead.AXIReadAddr.arburst = 2'b10; // Wrap AXIRead.AXIReadAddr.arvalid = rdata.req | inst.req; + rdata.addr_ok = AXIRead.AXIReadData.arready; if (rdata.req) begin AXIRead.AXIReadAddr.arid = 4'b0001; AXIRead.AXIReadAddr.arprot = 3'b001; AXIRead.AXIReadAddr.araddr = rdata.addr; AXIRead.AXIReadAddr.arlen = {1'b0, rdata.size}; - rdata.addr_ok = AXIRead.AXIReadData.arready; inst.addr_ok = 1'b0; end else begin AXIRead.AXIReadAddr.arid = 4'b0000; @@ -70,7 +70,6 @@ module AXI ( AXIRead.AXIReadAddr.araddr = inst.addr; AXIRead.AXIReadAddr.arlen = {1'b0, inst.size}; inst.addr_ok = AXIRead.AXIReadData.arready; - rdata.addr_ok = 1'b0; end end diff --git a/src/CP0/CP0.sv b/src/CP0/CP0.sv index bc28773..de2d0ce 100644 --- a/src/CP0/CP0.sv +++ b/src/CP0/CP0.sv @@ -205,8 +205,8 @@ module CP0 ( if ( exception.ExcCode == `EXCCODE_MOD | exception.ExcCode == `EXCCODE_TLBL | exception.ExcCode == `EXCCODE_TLBS - | exception.ExcCode == `EXCCODE_ADDRR - | exception.ExcCode == `EXCCODE_ADDRW) begin + | exception.ExcCode == `EXCCODE_ADEL + | exception.ExcCode == `EXCCODE_ADES) begin rf_cp0.BadVAddr = exception.BadVAddr; end diff --git a/src/Core/Controller.sv b/src/Core/Controller.sv index e5fe09b..f5f0c92 100644 --- a/src/Core/Controller.sv +++ b/src/Core/Controller.sv @@ -36,7 +36,7 @@ module Controller ( assign ctrl.SYSCALL = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[3] & inst[2] & ~inst[0]; assign ctrl.BREAK = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[3] & inst[2] & inst[0]; - assign ctrl.ERET = inst[30] & inst[25]; + assign ctrl.ERET = inst[30] & inst[4]; assign ctrl.OFA = ~inst[31] & ~inst[28] & ~inst[27] & ~inst[26] & (~inst[30] & inst[5] & ~inst[3] & ~inst[2] & ~inst[0] | inst[29]); assign ctrl.ES = inst[31] | ~inst[30] & ~inst[28] & ~inst[27] & ~inst[26] & (inst[5] | inst[4] & inst[3] & ~inst[2] | ~inst[3] & inst[2]) | inst[29];; @@ -44,8 +44,8 @@ module Controller ( assign ctrl.DS = ~inst[31] & ~inst[29] & (inst[28] | ~inst[27] & (~inst[30] & ~inst[5] & ~inst[4] & inst[3] & ~inst[2] | inst[26])); assign ctrl.DT = ~inst[31] & ~inst[29] & inst[28] & ~inst[27]; - assign ctrl.DP0 = ~inst[31]; - assign ctrl.DP1 = ~inst[30] & (inst[31] | inst[29] | inst[28] | inst[27] | inst[26] | ~inst[4]) | inst[30] & inst[25]; + assign ctrl.DP0 = ~inst[31] & (~inst[30] | inst[29] | ~inst[25] | inst[4]); + assign ctrl.DP1 = inst[26] | (~inst[30] & (inst[31] | inst[29] | inst[28] | inst[27] | ~inst[4]) | inst[30] & (~inst[29] & inst[25] | inst[3])); assign ctrl.ECtrl.OP.f_sl = ~inst[31] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[5] & ~inst[3] & ~inst[1]; assign ctrl.ECtrl.OP.f_sr = ~inst[31] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[5] & inst[1]; @@ -67,10 +67,13 @@ module Controller ( assign ctrl.MCtrl0.C0W = inst[30] & inst[23]; assign ctrl.MCtrl0.RS0 = RS0_t'({~inst[30] & (inst[29] | inst[26] | ~inst[4]), inst[30], ~inst[29] & (inst[30] | ~inst[1])}); - assign ctrl.MCtrl1.MR = inst[31]; - assign ctrl.MCtrl1.MWR = inst[29]; - assign ctrl.MCtrl1.MX = ~inst[28]; - assign ctrl.MCtrl1.SZ = inst[27:26]; + assign ctrl.MCtrl1.MR = inst[31]; + assign ctrl.MCtrl1.MWR = inst[29]; + assign ctrl.MCtrl1.MX = ~inst[28]; + assign ctrl.MCtrl1.SZ = inst[27:26]; + assign ctrl.MCtrl1.TLBR = inst[30] & ~inst[29] & inst[25] & ~inst[3] & ~inst[1]; + assign ctrl.MCtrl1.TLBWI = inst[30] & ~inst[29] & inst[25] & ~inst[3] & inst[1]; + assign ctrl.MCtrl1.TLBP = inst[30] & ~inst[4] & inst[3]; assign ctrl.WCtrl.RW = ctrl.RD != 5'b00000 & (~inst[30] & (~inst[29] & (inst[31] | ~inst[28] & (~inst[27] & (~inst[26] & (~inst[3] & (~inst[4] | ~inst[0]) | inst[3] & (inst[5] | ~inst[4] & ~inst[2] & inst[0])) | inst[26] & inst[20]) | inst[27] & inst[26])) | inst[29] & ~inst[31]) | inst[30] & ~inst[25] & ~inst[23]); diff --git a/src/Core/Datapath.sv b/src/Core/Datapath.sv index 74a744e..c24334b 100644 --- a/src/Core/Datapath.sv +++ b/src/Core/Datapath.sv @@ -2,8 +2,8 @@ `include "CP0.svh" module Datapath ( - input clk, - input rst, + input clk, + input rst, // MMU sramro_i.master fetch_i, @@ -13,6 +13,9 @@ module Datapath ( input logic dTLBRefill, input logic dTLBInvalid, input logic dTLBModified, + output logic tlbr, + output logic tlbwi, + output logic tlbp, // CP0 input logic C0_int, @@ -64,6 +67,11 @@ module Datapath ( word_t IQ_IB_inst; word_t IQ_IB_pc; + logic IQ_IA_TLBRefill; + logic IQ_IA_TLBInvalid; + logic IQ_IB_TLBRefill; + logic IQ_IB_TLBInvalid; + logic [3:0] IQ_valids; // Decode @@ -106,6 +114,11 @@ module Datapath ( logic D_IA_iv; logic D_IB_iv; + logic D_IA_TLBRefill; + logic D_IA_TLBInvalid; + logic D_IB_TLBRefill; + logic D_IB_TLBInvalid; + logic D_IA_DataHazard; logic D_IB_DataHazard; @@ -124,6 +137,7 @@ module Datapath ( logic E_I0_PrevExcValid; logic [4:0] E_I0_PrevExcCode; logic E_I0_PrevERET; + logic E_I0_PrevREFILL; logic E_I0_ExcValidWithoutOF; word_t E_I1_A; @@ -135,6 +149,7 @@ module Datapath ( logic E_I1_PrevExcValid; logic [4:0] E_I1_PrevExcCode; logic E_I1_PrevERET; + logic E_I1_PrevREFILL; logic E_I1_ExcValidWithoutOF; logic E_I0_FS_M_I0; @@ -163,6 +178,8 @@ module Datapath ( // Memory logic M_go; + logic M_I0_go; + logic M_I1_go; EXCEPTION_t M_exception; @@ -201,6 +218,11 @@ module Datapath ( word_t M_I0_HI; word_t M_I0_LO; + logic M_I1_NowExcValid; + logic M_I1_PrevExcValid; + logic [4:0] M_I1_PrevExcCode; + logic M_I1_PrevREFILL; + logic M_I0_FS_M_I1; logic M_I0_FS_W_I0; logic M_I0_FS_W_I1; @@ -272,27 +294,29 @@ module Datapath ( assign F.en = PF.pc[1:0] != 2'b00 & D_IA_can_dispatch | fetch_i.req & fetch_i.addr_ok; + assign F.ExcValid = F.pc[1:0] != 2'b00 | iTLBRefill | iTLBInvalid; + //---------------------------------------------------------------------------// // Instr Queue // //---------------------------------------------------------------------------// - Queue #(64) InstrQueue ( + Queue #(66) InstrQueue ( .clk(clk), .rst(rst | rstD | rstM), - .vinA(fetch_i.data_ok | F.pc[1:0] != 2'b00), - .inA ({F.pc[2] ? fetch_i.rdata1 : fetch_i.rdata0, F.pc}), + .vinA(fetch_i.data_ok | F.ExcValid), + .inA ({F.pc[2] ? fetch_i.rdata1 : fetch_i.rdata0, F.pc, iTLBRefill, iTLBInvalid}), .vinB(fetch_i.data_ok & ~F.pc[2]), - .inB ({fetch_i.rdata1, F.pc[31:3], 3'b100}), + .inB ({fetch_i.rdata1, F.pc[31:3], 3'b100, 2'b00}), .enA (D.en0), .voutA(IQ_IA_valid), - .outA ({IQ_IA_inst, IQ_IA_pc}), + .outA ({IQ_IA_inst, IQ_IA_pc, IQ_IA_TLBRefill, IQ_IA_TLBInvalid}), .enB (D.en1), .voutB(IQ_IB_valid), - .outB ({IQ_IB_inst, IQ_IB_pc}), + .outB ({IQ_IB_inst, IQ_IB_pc, IQ_IB_TLBRefill, IQ_IB_TLBInvalid}), .valids(IQ_valids) ); @@ -302,19 +326,19 @@ module Datapath ( //---------------------------------------------------------------------------// // D.FF - ffenr #(1 + 32 + 32) D_IA_ff ( + ffenr #(1 + 32 + 32 + 2) D_IA_ff ( clk, rst | rstM, - D.en1 ? {IQ_IA_valid & ~rstD, IQ_IA_pc, IQ_IA_inst} : {D_IB_valid, D.IB_pc, D.IB_inst}, + D.en1 ? {IQ_IA_valid & ~rstD, IQ_IA_pc, IQ_IA_inst, IQ_IA_TLBRefill, IQ_IA_TLBInvalid} : {D_IB_valid, D.IB_pc, D.IB_inst, D_IB_TLBRefill, D_IB_TLBInvalid}, ~D_IA_valid | D_go & E.en, - {D_IA_valid, D.IA_pc, D.IA_inst} + {D_IA_valid, D.IA_pc, D.IA_inst, D_IA_TLBRefill, D_IA_TLBInvalid} ); - ffenr #(1 + 32 + 32) D_IB_ff ( + ffenr #(1 + 32 + 32 + 2) D_IB_ff ( clk, rst | rstM, - D.en1 ? {IQ_IB_valid & ~rstD, IQ_IB_pc, IQ_IB_inst} : {IQ_IA_valid & ~rstD, IQ_IA_pc, IQ_IA_inst}, + D.en1 ? {IQ_IB_valid & ~rstD, IQ_IB_pc, IQ_IB_inst, IQ_IB_TLBRefill, IQ_IB_TLBInvalid} : {IQ_IA_valid & ~rstD, IQ_IA_pc, IQ_IA_inst, IQ_IA_TLBRefill, IQ_IA_TLBInvalid}, D.en0, - {D_IB_valid, D.IB_pc, D.IB_inst} + {D_IB_valid, D.IB_pc, D.IB_inst, D_IB_TLBRefill, D_IB_TLBInvalid} ); ffenr #(1) D_IA_Delay_ff ( @@ -390,14 +414,26 @@ module Datapath ( D_IB_iv ); - assign D.IA_ExcValid = D_IA_valid & (D.IA_pc[1:0] != 2'b00 | ~D_IA_iv | D.IA.SYSCALL | D.IA.BREAK | D.IA.ERET); - assign D.IA_ERET = D_IA_valid & D_IA_iv & D.IA.ERET; - assign D.IA_ExcCode = D.IA_pc[1:0] != 2'b00 ? `EXCCODE_ADDRR : ~D_IA_iv ? `EXCCODE_RI : D.IA_inst[0] ? `EXCCODE_BREAK : `EXCCODE_SYSCALL; + assign D.IA_ExcValid = D_IA_valid & (D.IA_pc[1:0] != 2'b00 | D_IA_TLBRefill | D_IA_TLBInvalid | ~D_IA_iv | D.IA.SYSCALL | D.IA.BREAK | D.IA.ERET); + assign D.IA_ERET = D_IA_valid & D_IA_iv & D.IA.ERET; + assign D.IA_REFILL = D_IA_valid & D_IA_TLBRefill; + assign D.IA_ExcCode = D.IA_pc[1:0] != 2'b00 ? `EXCCODE_ADEL + : D_IA_TLBRefill ? `EXCCODE_TLBL + : D_IA_TLBInvalid ? `EXCCODE_TLBL + : ~D_IA_iv ? `EXCCODE_RI + : D.IA_inst[0] ? `EXCCODE_BP : `EXCCODE_SYS; - assign D.IB_ExcValid = D_IB_valid & (D.IB_pc[1:0] != 2'b00 | ~D_IB_iv | D.IB.SYSCALL | D.IB.BREAK | D.IB.ERET | D.IB_Delay & D.IB.BJRJ); - assign D.IB_ERET = D_IB_valid & D_IB_iv & D.IB.ERET & ~D.IB_Delay; - assign D.IB_ExcCode = D.IB_pc[1:0] != 2'b00 ? `EXCCODE_ADDRR : (~D_IB_iv | D.IB.ERET | D.IB_Delay & D.IB.BJRJ) ? `EXCCODE_RI : D.IB_inst[0] ? `EXCCODE_BREAK : `EXCCODE_SYSCALL; - assign D.IB_Delay = D.IA.BJRJ; + assign D.IB_ExcValid = D_IB_valid & (D.IB_pc[1:0] != 2'b00 | D_IB_TLBRefill | D_IB_TLBInvalid | ~D_IB_iv | D.IB.SYSCALL | D.IB.BREAK | D.IB.ERET | D.IB_Delay & D.IB.BJRJ); + assign D.IB_ERET = D_IB_valid & D_IB_iv & D.IB.ERET & ~D.IB_Delay; + assign D.IB_REFILL = D_IB_valid & D_IB_TLBRefill; + assign D.IB_ExcCode = D.IB_pc[1:0] != 2'b00 ? `EXCCODE_ADEL + : D_IB_TLBRefill ? `EXCCODE_TLBL + : D_IB_TLBInvalid ? `EXCCODE_TLBL + : ~D_IB_iv ? `EXCCODE_RI + : D.IB.ERET ? `EXCCODE_RI + : D.IB_Delay & D.IB.BJRJ ? `EXCCODE_RI + : D.IB_inst[0] ? `EXCCODE_BP : `EXCCODE_SYS; + assign D.IB_Delay = D.IA.BJRJ; // D.Dispatch assign D_IA_DataHazard = E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.ES & ~E.I0.MCtrl.RS0[2] @@ -442,6 +478,7 @@ module Datapath ( assign D.I0.pc = D.A ? D.IB_pc : D.IA_pc; assign D.I0.ExcValid = D.A ? D.IB_ExcValid : D.IA_ExcValid; assign D.I0.ERET = D.A ? D.IB_ERET : D.IA_ERET; + assign D.I0.REFILL = D.A ? D.IB_REFILL : D.IA_REFILL; assign D.I0.ExcCode = D.A ? D.IB_ExcCode : D.IA_ExcCode; assign D.I0.Delay = D.A ? D.IB_Delay : D.IA_Delay; assign D.I0.OFA = D.A ? D.IB.OFA : D.IA.OFA; @@ -460,6 +497,7 @@ module Datapath ( assign D.I1.pc = D.A ? D.IA_pc : D.IB_pc; assign D.I1.ExcValid = D.A ? D.IA_ExcValid : D.IB_ExcValid; assign D.I1.ERET = D.A ? D.IA_ERET : D.IB_ERET; + assign D.I1.REFILL = D.A ? D.IA_REFILL : D.IB_REFILL; assign D.I1.ExcCode = D.A ? D.IA_ExcCode : D.IB_ExcCode; assign D.I1.Delay = D.A ? D.IA_Delay : D.IB_Delay; assign D.I1.OFA = D.A ? D.IA.OFA : D.IB.OFA; @@ -547,13 +585,13 @@ module Datapath ( E.en, E.I0.pc ); - ffenrc #(1 + 1 + 5 + 1 + 1) E_I0_Exc_ff ( + ffenrc #(1 + 1 + 1 + 5 + 1 + 1) E_I0_Exc_ff ( clk, rst | rstM, - {D.I0.ExcValid, D.I0.ERET, D.I0.ExcCode, D.I0.Delay, D.I0.OFA}, + {D.I0.ExcValid, D.I0.ERET, D.I0.REFILL, D.I0.ExcCode, D.I0.Delay, D.I0.OFA}, E.en, ~D_go, - {E_I0_PrevExcValid, E_I0_PrevERET, E_I0_PrevExcCode, E.I0.Delay, E.I0.OFA} + {E_I0_PrevExcValid, E_I0_PrevERET, E_I0_PrevREFILL, E_I0_PrevExcCode, E.I0.Delay, E.I0.OFA} ); ffen #(5 + 5) E_I0_RST_ff ( clk, @@ -602,13 +640,13 @@ module Datapath ( E.en, E.I1.pc ); - ffenrc #(1 + 1 + 5 + 1 + 1) E_I1_Exc_ff ( + ffenrc #(1 + 1 + 1 + 5 + 1 + 1) E_I1_Exc_ff ( clk, rst | rstM, - {D.I1.ExcValid, D.I1.ERET, D.I1.ExcCode, D.I1.Delay, D.I1.OFA}, + {D.I1.ExcValid, D.I1.ERET, D.I1.REFILL, D.I1.ExcCode, D.I1.Delay, D.I1.OFA}, E.en, ~D_go, - {E_I1_PrevExcValid, E_I1_PrevERET, E_I1_PrevExcCode, E.I1.Delay, E.I1.OFA} + {E_I1_PrevExcValid, E_I1_PrevERET, E_I1_PrevREFILL, E_I1_PrevExcCode, E.I1.Delay, E.I1.OFA} ); ffen #(5 + 5) E_I1_RST_ff ( clk, @@ -634,7 +672,7 @@ module Datapath ( E.en, E.I1.ECtrl ); - ffenrc #(5) E_I1_MCtrl_ff ( + ffenrc #(8) E_I1_MCtrl_ff ( clk, rst | rstM, D.I1.MCtrl, @@ -653,19 +691,25 @@ module Datapath ( // E.Exc assign E_I0_NowExcValidWithoutOF = C0_int & E_valid; - assign E_I0_NowExcValid = E_I0_NowExcValidWithoutOF | E_I0_Overflow & E.I0.OFA; - assign E_I0_ExcValidWithoutOF = E_I0_PrevExcValid | E_I0_NowExcValidWithoutOF; - assign E.I0.ExcValid = E_I0_PrevExcValid | E_I0_NowExcValid; - assign E.I0.ERET = E_I0_PrevERET & ~C0_int; - assign E.I0.ExcCode = C0_int ? 5'h0 : E_I0_PrevExcValid ? E_I0_PrevExcCode : `EXCCODE_OF; + assign E_I0_NowExcValid = E_I0_NowExcValidWithoutOF | E_I0_Overflow & E.I0.OFA; + assign E_I0_ExcValidWithoutOF = E_I0_PrevExcValid | E_I0_NowExcValidWithoutOF; + assign E.I0.ExcValid = E_I0_PrevExcValid | E_I0_NowExcValid; + assign E.I0.ERET = E_I0_PrevERET & ~C0_int; + assign E.I0.REFILL = E_I0_PrevREFILL & ~C0_int; + assign E.I0.ExcCode = C0_int ? 5'h0 + : E_I0_PrevExcValid ? E_I0_PrevExcCode : `EXCCODE_OV; assign E_I1_NowExcValidWithoutOF = C0_int & E_valid | E.I1.MCtrl.MR & E_I1_STRBERROR; - assign E_I1_NowExcValid = E_I1_NowExcValidWithoutOF | E_I1_Overflow & E.I1.OFA; - assign E_I1_ExcValidWithoutOF = E_I1_PrevExcValid | E_I1_NowExcValidWithoutOF; - assign E.I1.ExcValid = E_I1_PrevExcValid | E_I1_NowExcValid; - assign E.I1.ERET = E_I1_PrevERET & ~C0_int; - assign E.I1.ExcCode = C0_int ? 5'h0 : E_I1_PrevExcValid ? E_I1_PrevExcCode : E_I1_Overflow & E.I1.OFA ? `EXCCODE_OF : E.I1.MCtrl.MWR ? `EXCCODE_ADDRW : `EXCCODE_ADDRR; - assign E.I1.BadVAddr = E_I1_PrevExcValid ? E.I1.pc : E.I1.ALUOut; + assign E_I1_NowExcValid = E_I1_NowExcValidWithoutOF | E_I1_Overflow & E.I1.OFA; + assign E_I1_ExcValidWithoutOF = E_I1_PrevExcValid | E_I1_NowExcValidWithoutOF; + assign E.I1.ExcValid = E_I1_PrevExcValid | E_I1_NowExcValid; + assign E.I1.ERET = E_I1_PrevERET & ~C0_int; + assign E.I1.REFILL = E_I1_PrevREFILL & ~C0_int; + assign E.I1.ExcCode = C0_int ? 5'h0 + : E_I1_PrevExcValid ? E_I1_PrevExcCode + : E_I1_Overflow & E.I1.OFA ? `EXCCODE_OV + : E.I1.MCtrl.MWR ? `EXCCODE_ADES : `EXCCODE_ADEL; + assign E.I1.BadVAddr = E_I1_PrevExcValid ? E.I1.pc : E.I1.ALUOut; assign E_I0_go = ~E_I0_NowExcValid & (~E.A | ~E_I1_NowExcValid); assign E_I1_goWithoutOF = ~E_I1_NowExcValidWithoutOF & (E.A | ~E_I0_NowExcValidWithoutOF); @@ -833,13 +877,13 @@ module Datapath ( M.en, M.I0.pc ); - ffenrc #(1 + 1 + 5 + 1) M_I0_Exc_ff ( + ffenrc #(1 + 1 + 1 + 5 + 1) M_I0_Exc_ff ( clk, rst | rstM, - {E.I0.ExcValid, E.I0.ERET, E.I0.ExcCode, E.I0.Delay}, + {E.I0.ExcValid, E.I0.ERET, E.I0.REFILL, E.I0.ExcCode, E.I0.Delay}, M.en, ~E_go, - {M.I0.ExcValid, M.I0.ERET, M.I0.ExcCode, M.I0.Delay} + {M.I0.ExcValid, M.I0.ERET, M.I0.REFILL, M.I0.ExcCode, M.I0.Delay} ); ffen #(5 + 5) M_I0_RST_ff ( clk, @@ -888,13 +932,13 @@ module Datapath ( M.en, M.I1.pc ); - ffenrc #(1 + 1 + 5 + 32 + 1) M_I1_Exc_ff ( + ffenrc #(1 + 1 + 1 + 5 + 32 + 1) M_I1_Exc_ff ( clk, rst | rstM, - {E.I1.ExcValid, E.I1.ERET, E.I1.ExcCode, E.I1.BadVAddr, E.I1.Delay}, + {E.I1.ExcValid, E.I1.ERET, E.I1.REFILL, E.I1.ExcCode, E.I1.BadVAddr, E.I1.Delay}, M.en, ~E_go, - {M.I1.ExcValid, M.I1.ERET, M.I1.ExcCode, M.I1.BadVAddr, M.I1.Delay} + {M_I1_PrevExcValid, M.I1.ERET, M_I1_PrevREFILL, M_I1_PrevExcCode, M.I1.BadVAddr, M.I1.Delay} ); ffen #(5) M_I1_RT_ff ( clk, @@ -914,7 +958,7 @@ module Datapath ( M.en, M.I1.ALUOut ); - ffenrc #(5) M_I1_MCtrl_ff ( + ffenrc #(8) M_I1_MCtrl_ff ( clk, rst | rstM, E.I1.MCtrl, @@ -933,6 +977,18 @@ module Datapath ( // M.Exc assign M.I0.BadVAddr = M.I0.pc; + + assign M_I1_NowExcValid = dTLBRefill | dTLBInvalid | dTLBModified; + assign M.I1.ExcValid = M_I1_PrevExcValid | M_I1_NowExcValid; + assign M.I1.REFILL = M_I1_PrevREFILL | dTLBRefill; + assign M.I1.ExcCode = M_I1_PrevExcValid ? M_I1_PrevExcCode + : dTLBRefill ? M.I1.MCtrl.MWR ? `EXCCODE_TLBS : `EXCCODE_TLBL + : dTLBInvalid ? M.I1.MCtrl.MWR ? `EXCCODE_TLBS : `EXCCODE_TLBL + : `EXCCODE_MOD; + + assign M_I0_go = ~M.A | ~M_I1_NowExcValid; + assign M_I1_go = ~M_I1_NowExcValid; + assign M_exception = { M.I1.ExcValid | M.I0.ExcValid, ~M.I0.ExcValid | M.I1.ExcValid & M.A ? {M.I1.Delay, M.I1.ExcCode, M.I1.BadVAddr, M.I1.pc, M.I1.ERET} diff --git a/src/MyCPU.sv b/src/MyCPU.sv index cc03897..f3f0896 100644 --- a/src/MyCPU.sv +++ b/src/MyCPU.sv @@ -104,6 +104,9 @@ module mycpu_top ( logic dTLBRefill; logic dTLBInvalid; logic dTLBModified; + logic tlbr; + logic tlbwi; + logic tlbp; AXI axi ( @@ -127,8 +130,8 @@ module mycpu_top ( .rdata_axi (rdata_axi.master), .wdata_axi (wdata_axi.master), .K0 (K0), - .tlbwi (), - .tlbp (), + .tlbwi (tlbwi), + .tlbp (tlbp), .c0_Index (c0_Index), .c0_EntryHi (c0_EntryHi), .c0_PageMask (c0_PageMask), @@ -169,8 +172,8 @@ module mycpu_top ( .EPC (C0_EPC), .ext_int (ext_int), .interrupt (C0_int), - .tlbr (), - .tlbp (), + .tlbr (tlbr), + .tlbp (tlbp), .K0 (K0), .Index (c0_Index), .EntryHi (c0_EntryHi), @@ -195,6 +198,9 @@ module mycpu_top ( .dTLBRefill (dTLBRefill), .dTLBInvalid (dTLBInvalid), .dTLBModified(dTLBModified), + .tlbr (tlbr), + .tlbwi (tlbwi), + .tlbp (tlbp), .C0_int (C0_int), .C0_addr (C0_addr), diff --git a/src/include/defines.svh b/src/include/defines.svh index c2274d7..c9d6a35 100644 --- a/src/include/defines.svh +++ b/src/include/defines.svh @@ -7,19 +7,24 @@ // prio: int // fetch_addr +// fetch_tlb_refill +// fetch_tlb_invalid // ri -// syscall, break, of +// syscall, break, overflow // mem_addr -`define EXCCODE_INT 5'h00 -`define EXCCODE_MOD 5'h01 -`define EXCCODE_TLBL 5'h02 -`define EXCCODE_TLBS 5'h03 -`define EXCCODE_ADDRR 5'h04 -`define EXCCODE_ADDRW 5'h05 -`define EXCCODE_SYSCALL 5'h08 -`define EXCCODE_BREAK 5'h09 -`define EXCCODE_RI 5'h0A -`define EXCCODE_OF 5'h0C +// mem_tlb_refill +// mem_tlb_invalid +// mem_tlb_dirty +`define EXCCODE_INT 5'h00 +`define EXCCODE_MOD 5'h01 +`define EXCCODE_TLBL 5'h02 +`define EXCCODE_TLBS 5'h03 +`define EXCCODE_ADEL 5'h04 +`define EXCCODE_ADES 5'h05 +`define EXCCODE_SYS 5'h08 +`define EXCCODE_BP 5'h09 +`define EXCCODE_RI 5'h0A +`define EXCCODE_OV 5'h0C typedef logic [31:0] word_t; @@ -71,23 +76,26 @@ typedef struct packed { } ECtrl_t; typedef struct packed { - RS0_t RS0; // critical - logic HW; // critical - logic LW; // critical + RS0_t RS0; // critical + logic HW; // critical + logic LW; // critical logic [4:0] C0D; - logic C0W; // critical + logic C0W; // critical HLS_t HLS; } MCtrl0_t; typedef struct packed { - logic MR; // critical - logic MWR; // critical + logic MR; // critical + logic MWR; // critical logic MX; logic [1:0] SZ; + logic TLBWI; // critical + logic TLBR; // critical + logic TLBP; // critical } MCtrl1_t; typedef struct packed { - logic RW; // critical + logic RW; // critical } WCtrl_t; typedef struct packed { @@ -125,6 +133,7 @@ typedef struct packed {word_t pc;} PF_t; typedef struct packed { logic en; word_t pc; + logic ExcValid; } F_t; typedef struct packed { @@ -137,6 +146,7 @@ typedef struct packed { word_t IA_inst; logic IA_ExcValid; logic IA_ERET; + logic IA_REFILL; logic [4:0] IA_ExcCode; logic IA_Delay; word_t IA_S; @@ -148,6 +158,7 @@ typedef struct packed { word_t IB_inst; logic IB_ExcValid; logic IB_ERET; + logic IB_REFILL; logic [4:0] IB_ExcCode; logic IB_Delay; word_t IB_S; @@ -160,6 +171,7 @@ typedef struct packed { logic ExcValid; logic ERET; + logic REFILL; logic [4:0] ExcCode; logic Delay; logic OFA; @@ -185,6 +197,7 @@ typedef struct packed { logic ExcValid; logic ERET; + logic REFILL; logic [4:0] ExcCode; logic Delay; logic OFA; @@ -215,6 +228,7 @@ typedef struct packed { logic ExcValid; logic ERET; + logic REFILL; logic [4:0] ExcCode; logic Delay; logic OFA; @@ -241,6 +255,7 @@ typedef struct packed { logic ExcValid; logic ERET; + logic REFILL; logic [4:0] ExcCode; word_t BadVAddr; logic Delay; @@ -273,6 +288,7 @@ typedef struct packed { logic ExcValid; logic ERET; + logic REFILL; logic [4:0] ExcCode; word_t BadVAddr; logic Delay; @@ -296,6 +312,7 @@ typedef struct packed { logic ExcValid; logic ERET; + logic REFILL; logic [4:0] ExcCode; word_t BadVAddr; logic Delay; diff --git a/tools/RS0.txt b/tools/RS0.txt deleted file mode 100644 index beec9f9..0000000 --- a/tools/RS0.txt +++ /dev/null @@ -1,48 +0,0 @@ -////-------------------------------- RS0 1 0 -32'b00000000000???????????????000000 ALUOut 1 0 -32'b00000000000???????????????000010 ALUOut 1 0 -32'b00000000000???????????????000011 ALUOut 1 0 -32'b000001?????10000???????????????? ALUOut 1 0 -32'b000001?????10001???????????????? ALUOut 1 0 -32'b000011?????????????????????????? ALUOut 1 0 -32'b000000?????00000?????00000001001 ALUOut 1 0 -32'b001000?????????????????????????? ALUOut 1 0 -32'b001001?????????????????????????? ALUOut 1 0 -32'b001010?????????????????????????? ALUOut 1 0 -32'b001011?????????????????????????? ALUOut 1 0 -32'b001100?????????????????????????? ALUOut 1 0 -32'b001101?????????????????????????? ALUOut 1 0 -32'b001110?????????????????????????? ALUOut 1 0 -32'b00111100000????????????????????? ALUOut 1 0 -32'b000000???????????????00000000100 ALUOut 1 0 -32'b000000???????????????00000000110 ALUOut 1 0 -32'b000000???????????????00000000111 ALUOut 1 0 -32'b0000000000000000?????00000010000 HI 0 1 -32'b0000000000000000?????00000010010 LO 0 0 -32'b01000000000??????????00000000??? C0 1 1 -32'b000000?????000000000000000001000 ? ? ? -32'b000000????????????????????001100 ? ? ? -32'b000000????????????????????001101 ? ? ? -32'b000000?????000000000000000010001 ? ? ? -32'b000000?????000000000000000010011 ? ? ? -32'b000000??????????0000000000011000 ? ? ? -32'b000000??????????0000000000011001 ? ? ? -32'b000000??????????0000000000011010 ? ? ? -32'b000000??????????0000000000011011 ? ? ? -32'b000000???????????????0000??????? ? ? ? -32'b000001?????00001???????????????? ? ? ? -32'b000010?????????????????????????? ? ? ? -32'b000100?????????????????????????? ? ? ? -32'b000101?????????????????????????? ? ? ? -32'b000110?????00000???????????????? ? ? ? -32'b000111?????00000???????????????? ? ? ? -32'b01000000100??????????00000000??? ? ? ? -32'b01000010000000000000000000011000 ? ? ? -32'b100000?????????????????????????? ? ? ? -32'b100001?????????????????????????? ? ? ? -32'b100011?????????????????????????? ? ? ? -32'b100100?????????????????????????? ? ? ? -32'b100101?????????????????????????? ? ? ? -32'b101000?????????????????????????? ? ? ? -32'b101001?????????????????????????? ? ? ? -32'b101011?????????????????????????? ? ? ? \ No newline at end of file diff --git a/tools/alusrc.sv b/tools/alusrc.sv deleted file mode 100644 index e72937f..0000000 --- a/tools/alusrc.sv +++ /dev/null @@ -1,57 +0,0 @@ -32'b00000000000???????????????000000 // SLL sa R[rt] R[rd] -32'b00000000000???????????????000010 // SRL sa R[rt] R[rd] -32'b00000000000???????????????000011 // SRA sa R[rt] R[rd] -32'b000000???????????????00000000100 // SLLV R[rs] R[rt] R[rd] -32'b000000???????????????00000000110 // SRLV R[rs] R[rt] R[rd] -32'b000000???????????????00000000111 // SRAV R[rs] R[rt] R[rd] -32'b000000?????000000000000000001000 // JR -32'b000000?????00000?????00000001001 // JALR pc 8 R[rd] -32'b000000????????????????????001100 // SYSCALL -32'b000000????????????????????001101 // BREAK -32'b0000000000000000?????00000010000 // MFHI R[rd] -32'b000000?????000000000000000010001 // MTHI R[rs] R[rt] HI -32'b0000000000000000?????00000010010 // MFLO R[rd] -32'b000000?????000000000000000010011 // MTLO R[rs] R[rt] LO -32'b000000??????????0000000000011000 // MULT -32'b000000??????????0000000000011001 // MULTU -32'b000000??????????0000000000011010 // DIV -32'b000000??????????0000000000011011 // DIVU -32'b000000???????????????00000100000 // ADD R[rs] R[rt] R[rd] -32'b000000???????????????00000100001 // ADDU R[rs] R[rt] R[rd] -32'b000000???????????????00000100010 // SUB R[rs] R[rt] R[rd] -32'b000000???????????????00000100011 // SUBU R[rs] R[rt] R[rd] -32'b000000???????????????00000100100 // AND R[rs] R[rt] R[rd] -32'b000000???????????????00000100101 // OR R[rs] R[rt] R[rd] -32'b000000???????????????00000100110 // XOR R[rs] R[rt] R[rd] -32'b000000???????????????00000100111 // NOR R[rs] R[rt] R[rd] -32'b000000???????????????00000101010 // SLT R[rs] R[rt] R[rd] -32'b000000???????????????00000101011 // SLTU R[rs] R[rt] R[rd] -32'b000001?????00000???????????????? // BLTZ -32'b000001?????10000???????????????? // BLTZAL pc 8 R[31] -32'b000001?????00001???????????????? // BGEZ -32'b000001?????10001???????????????? // BGEZAL pc 8 R[31] -32'b000010?????????????????????????? // J -32'b000011?????????????????????????? // JAL pc 8 R[31] -32'b000100?????????????????????????? // BEQ -32'b000101?????????????????????????? // BNE -32'b000110?????00000???????????????? // BLEZ -32'b000111?????00000???????????????? // BGTZ -32'b001000?????????????????????????? // ADDI R[rs] simm R[rt] -32'b001001?????????????????????????? // ADDIU R[rs] simm R[rt] -32'b001010?????????????????????????? // SLTI R[rs] simm R[rt] -32'b001011?????????????????????????? // SLTIU R[rs] simm R[rt] -32'b001100?????????????????????????? // ANDI R[rs] zimm R[rt] -32'b001101?????????????????????????? // ORI R[rs] zimm R[rt] -32'b001110?????????????????????????? // XORI R[rs] zimm R[rt] -32'b00111100000????????????????????? // LUI 0 uimm R[rt] -32'b01000000000??????????00000000??? // MFC0 0 CP0 R[rd] -32'b01000000100??????????00000000??? // MTC0 0 R[rt] CP0 -32'b01000010000000000000000000011000 // ERET -32'b100000?????????????????????????? // LB R[rs] simm R[rt] -32'b100001?????????????????????????? // LH R[rs] simm R[rt] -32'b100011?????????????????????????? // LW R[rs] simm R[rt] -32'b100100?????????????????????????? // LBU R[rs] simm R[rt] -32'b100101?????????????????????????? // LHU R[rs] simm R[rt] -32'b101000?????????????????????????? // SB R[rs] simm -32'b101001?????????????????????????? // SH R[rs] simm -32'b101011?????????????????????????? // SW R[rs] simm \ No newline at end of file diff --git a/tools/ctrl.out.txt b/tools/ctrl.out.txt deleted file mode 100644 index b3b92d0..0000000 --- a/tools/ctrl.out.txt +++ /dev/null @@ -1,42 +0,0 @@ -ctrl.ERET = inst[30] & inst[25] -ctrl.SYSCALL = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[3] & inst[2] & ~inst[0] -ctrl.BREAK = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[3] & inst[2] & inst[0] - -ctrl.PFCtrl.BJJR = ~inst[26] & (~inst[27] & (~inst[28] & ~inst[30] & ~inst[31] & ~inst[29] & inst[3] & ~inst[4] & ~inst[5] & ~inst[2] | inst[28] & ~inst[31] & ~inst[29]) | inst[27] & ~inst[29]) | inst[26] & ~inst[29] & ~inst[31] -ctrl.PFCtrl.BJR = (~inst[26] & (~inst[28] & ~inst[30] & ~inst[29] & ~inst[31] & ~inst[27] & inst[3] & ~inst[4] & ~inst[5] & ~inst[2] | inst[28] & ~inst[29] & ~inst[31]) | inst[26] & ~inst[29] & ~inst[31] & (~inst[27] | inst[28])) -ctrl.PFCtrl.BE = ~inst[31] & ~inst[29] & inst[28] & ~inst[27] - -ctrl.DCtrl.DP0 = ~inst[31] -ctrl.DCtrl.DP1 = ~inst[30] & (~inst[26] & (~inst[29] & (~inst[28] & (~inst[31] & (~inst[27] & ~inst[4] | inst[27]) | inst[31]) | inst[28]) | inst[29]) | inst[26]) | inst[30] & inst[25] -ctrl.DCtrl.UI = inst[28] & inst[29] & inst[27] & inst[26] -ctrl.DCtrl.IX = ~inst[28] - -ctrl.ECtrl.SA -{'SA': '~inst[31] & ~inst[29] & ~inst[26] & ~inst[30] & ~inst[28] & ~inst[27] & ~inst[5] & ~inst[4] & ~inst[3] & ~inst[2]', 'RS': '(~inst[31] & (~inst[29] & ~inst[26] & ~inst[30] & ~inst[28] & ~inst[27] & (~inst[5] & (~inst[4] & ~inst[3] & inst[2] | inst[4] & inst[3]) | inst[5]) | inst[29] & (~inst[28] | inst[28] & (~inst[27] | inst[27] & ~inst[26]))) | inst[31])' - -ctrl.ECtrl.SB -{'RT': '~inst[29] & ~inst[31] & ~inst[26] & ~inst[30] & ~inst[28] & ~inst[27] & (~inst[5] & (~inst[1] & (~inst[0] & (~inst[3] & ~inst[4] | inst[3] & inst[4]) | inst[0] & inst[4] & inst[3]) | inst[1] & (~inst[4] | inst[4] & inst[3])) | inst[5])', '8': '~inst[29] & ~inst[31] & (~inst[26] & (~inst[30] & (~inst[28] & (~inst[27] & ~inst[5] & (~inst[1] & (~inst[0] & (~inst[3] & inst[4] | inst[3] & ~inst[4]) | inst[0] & (~inst[4] | inst[4] & ~inst[3])) | inst[1] & inst[4] & ~inst[3]) | inst[27]) | inst[28]) | inst[30]) | inst[26])', 'IMM': '(~inst[29] & inst[31] | inst[29])'} - -ctrl.ECtrl.OP[8:1] -{'SR': '~inst[31] & ~inst[26] & ~inst[28] & ~inst[27] & ~inst[30] & ~inst[29] & ~inst[5] & ~inst[3] & (~inst[1] & ~inst[2] | inst[1])', 'SL': '~inst[31] & ~inst[26] & ~inst[28] & ~inst[27] & ~inst[30] & ~inst[29] & ~inst[5] & ~inst[3] & ~inst[1] & inst[2]', 'ADD': '(~inst[31] & (~inst[26] & ~inst[28] & ~inst[27] & (~inst[30] & (~inst[29] & (~inst[5] & inst[3] | inst[5] & ~inst[2] & ~inst[3]) | inst[29]) | inst[30]) | inst[26] & (~inst[29] | inst[29] & (~inst[28] & ~inst[27] | inst[28] & inst[27]))) | inst[31])', 'SLT': '~inst[31] & ~inst[26] & ~inst[28] & (~inst[27] & ~inst[30] & ~inst[29] & inst[5] & ~inst[2] & inst[3] & ~inst[0] | inst[27])', 'SLTU': '~inst[31] & (~inst[26] & ~inst[28] & ~inst[27] & ~inst[30] & ~inst[29] & inst[5] & ~inst[2] & inst[3] & inst[0] | inst[26] & inst[29] & ~inst[28] & inst[27])', 'AND': '~inst[31] & ~inst[26] & (~inst[28] & ~inst[27] & ~inst[30] & ~inst[29] & inst[5] & inst[2] & ~inst[0] & ~inst[1] | inst[28] & ~inst[27])', 'XOR': '~inst[31] & ~inst[26] & (~inst[28] & ~inst[27] & ~inst[30] & ~inst[29] & inst[5] & inst[2] & ~inst[0] & inst[1] | inst[28] & inst[27])', 'OR': '~inst[31] & (~inst[26] & ~inst[28] & ~inst[27] & ~inst[30] & ~inst[29] & inst[5] & inst[2] & inst[0] | inst[26] & inst[29] & inst[28] & ~inst[27])'} - -ctrl.ECtrl.OP[0] = ~inst[31] & (~inst[26] & ~inst[30] & (~inst[27] & ~inst[29] & inst[1] & (~inst[5] & inst[0] | inst[5]) | inst[27]) | inst[26] & inst[27] & inst[29] & ~inst[28])' -ctrl.OFA = ~inst[26] & (~inst[29] & ~inst[30] & ~inst[28] & ~inst[31] & ~inst[27] & inst[5] & ~inst[0] & ~inst[2] & ~inst[3] | inst[29] & ~inst[28] & ~inst[31] & ~inst[27])' -ctrl.MCtrl1.MR = inst[31] -ctrl.MCtrl1.MWR = inst[29] -ctrl.MCtrl1.MX = ~inst[28] - -RD -{'RD': '~inst[29] & ~inst[31] & ~inst[26]', '31': '~inst[29] & ~inst[31] & inst[26]', 'RT': '(~inst[29] & inst[31] | inst[29])'} - -ctrl.WCtrl.RW = (~inst[30] & (~inst[29] & (~inst[31] & ~inst[28] & (~inst[27] & (~inst[26] & (~inst[3] & (~inst[4] | inst[4] & ~inst[0]) | inst[3] & (~inst[5] & ~inst[4] & ~inst[2] & inst[0] | inst[5])) | inst[26] & inst[20]) | inst[27] & inst[26]) | inst[31]) | inst[29] & ~inst[31]) | inst[30] & ~inst[25] & ~inst[23]) - -ctrl.MCtrl0.RS0 -{'ALUOut': '~inst[30] & (~inst[29] & (~inst[26] & ~inst[4] | inst[26]) | inst[29])', 'HI': '~inst[30] & ~inst[29] & ~inst[26] & inst[4] & ~inst[1]', 'LO': '~inst[30] & ~inst[29] & ~inst[26] & inst[4] & inst[1]', 'C0': 'inst[30]'} - -ctrl.MCtrl0.HW = ~inst[26] & ~inst[29] & ~inst[30] & ~inst[28] & ~inst[27] & inst[4] & (~inst[3] & ~inst[1] & inst[0] | inst[3]) -ctrl.MCtrl0.LW = ~inst[26] & ~inst[29] & ~inst[30] & ~inst[28] & ~inst[27] & inst[4] & (~inst[3] & inst[1] & inst[0] | inst[3])' -ctrl.MCtrl0.C0W = inst[30] & inst[23] - -ctrl.MCtrl0.HLS -{'RS': '~inst[3]', 'MULT': 'inst[3] & ~inst[1] & ~inst[0]', 'MULTU': 'inst[3] & ~inst[1] & inst[0]', 'DIV': 'inst[3] & inst[1] & ~inst[0]', 'DIVU': 'inst[3] & inst[1] & inst[0]'} diff --git a/tools/ctrl.sv b/tools/ctrl.sv deleted file mode 100644 index febe2fe..0000000 --- a/tools/ctrl.sv +++ /dev/null @@ -1,57 +0,0 @@ -////-------------------------------- DP0 DP1 ALU ALT IMM LUI A B MR SI MW RW RD FC0 FHI FLO C0W HIW LOW -32'b00000000000???????????????000010 1 1 2 0 ? ? sa rt 0 ? 0 1 rd 0 0 0 0 0 0 // SRL -32'b00000000000???????????????000011 1 1 2 1 ? ? sa rt 0 ? 0 1 rd 0 0 0 0 0 0 // SRA -32'b000000???????????????00000000100 1 1 1 ? ? ? sa rt 0 ? 0 1 rd 0 0 0 0 0 0 // SLLV -32'b000000???????????????00000000110 1 1 2 0 ? ? sa rt 0 ? 0 1 rd 0 0 0 0 0 0 // SRLV -32'b000000???????????????00000000111 1 1 2 1 ? ? sa rt 0 ? 0 1 rd 0 0 0 0 0 0 // SRAV -32'b000000?????000000000000000001000 1 1 ? ? ? ? ? ? 0 ? 0 0 ? ? ? ? 0 0 0 // JR -32'b000000?????00000?????00000001001 1 1 3 0 ? ? pc 8 0 ? 0 1 rd 0 0 0 0 0 0 // JALR -32'b000000????????????????????001100 1 1 ? ? ? ? ? ? 0 ? 0 0 ? ? ? ? 0 0 0 // SYSCALL -32'b000000????????????????????001101 1 1 ? ? ? ? ? ? 0 ? 0 0 ? ? ? ? 0 0 0 // BREAK -32'b0000000000000000?????00000010000 1 0 ? ? ? ? ? ? ? ? ? 1 rd 0 1 ? 0 0 0 // MFHI -32'b000000?????000000000000000010001 1 0 ? ? ? ? ? ? ? ? ? 0 ? ? ? ? 0 1 0 // MTHI -32'b0000000000000000?????00000010010 1 0 ? ? ? ? ? ? ? ? ? 1 rd 0 0 1 0 0 0 // MFLO -32'b000000?????000000000000000010011 1 0 ? ? ? ? ? ? ? ? ? 0 ? ? ? ? 0 0 1 // MTLO -32'b000000??????????0000000000011000 1 0 ? ? ? ? ? ? ? ? ? 0 ? ? ? ? 0 2 2 // MULT -32'b000000??????????0000000000011001 1 0 ? ? ? ? ? ? ? ? ? 0 ? ? ? ? 0 2 2 // MULTU -32'b000000??????????0000000000011010 1 0 ? ? ? ? ? ? ? ? ? 0 ? ? ? ? 0 3 3 // DIV -32'b000000??????????0000000000011011 1 0 ? ? ? ? ? ? ? ? ? 0 ? ? ? ? 0 3 3 // DIVU -32'b000000???????????????00000100000 1 1 3 0 ? ? rs rt 0 ? 0 1 rd 0 0 0 0 0 0 // ADD -32'b000000???????????????00000100001 1 1 3 0 ? ? rs rt 0 ? 0 1 rd 0 0 0 0 0 0 // ADDU -32'b000000???????????????00000100010 1 1 3 1 ? ? rs rt 0 ? 0 1 rd 0 0 0 0 0 0 // SUB -32'b000000???????????????00000100011 1 1 3 1 ? ? rs rt 0 ? 0 1 rd 0 0 0 0 0 0 // SUBU -32'b000000???????????????00000100100 1 1 4 ? ? ? rs rt 0 ? 0 1 rd 0 0 0 0 0 0 // AND -32'b000000???????????????00000100101 1 1 5 0 ? ? rs rt 0 ? 0 1 rd 0 0 0 0 0 0 // OR -32'b000000???????????????00000100110 1 1 6 ? ? ? rs rt 0 ? 0 1 rd 0 0 0 0 0 0 // XOR -32'b000000???????????????00000100111 1 1 5 1 ? ? rs rt 0 ? 0 1 rd 0 0 0 0 0 0 // NOR -32'b000000???????????????00000101010 1 1 7 1 ? ? rs rt 0 ? 0 1 rd 0 0 0 0 0 0 // SLT -32'b000000???????????????00000101011 1 1 8 1 ? ? rs rt 0 ? 0 1 rd 0 0 0 0 0 0 // SLTU -32'b000001?????00000???????????????? 1 1 ? ? ? ? ? ? 0 ? 0 0 ? ? ? ? 0 0 0 // BLTZ -32'b000001?????10000???????????????? 1 1 3 0 ? ? pc 8 0 ? 0 1 31 0 0 0 0 0 0 // BLTZAL -32'b000001?????00001???????????????? 1 1 ? ? ? ? ? ? 0 ? 0 0 ? ? ? ? 0 0 0 // BGEZ -32'b000001?????10001???????????????? 1 1 3 0 ? ? pc 8 0 ? 0 1 31 0 0 0 0 0 0 // BGEZAL -32'b000010?????????????????????????? 1 1 ? ? ? ? ? ? 0 ? 0 0 ? ? ? ? 0 0 0 // J -32'b000011?????????????????????????? 1 1 3 0 ? ? pc 8 0 ? 0 1 31 0 0 0 0 0 0 // JAL -32'b000100?????????????????????????? 1 1 ? ? ? ? ? ? 0 ? 0 0 ? ? ? ? 0 0 0 // BEQ -32'b000101?????????????????????????? 1 1 ? ? ? ? ? ? 0 ? 0 0 ? ? ? ? 0 0 0 // BNE -32'b000110?????00000???????????????? 1 1 ? ? ? ? ? ? 0 ? 0 0 ? ? ? ? 0 0 0 // BLEZ -32'b000111?????00000???????????????? 1 1 ? ? ? ? ? ? 0 ? 0 0 ? ? ? ? 0 0 0 // BGTZ -32'b001000?????????????????????????? 1 1 3 0 1 0 rs imm 0 ? 0 1 rt 0 0 0 0 0 0 // ADDI -32'b001001?????????????????????????? 1 1 3 0 1 0 rs imm 0 ? 0 1 rt 0 0 0 0 0 0 // ADDIU -32'b001010?????????????????????????? 1 1 7 1 1 0 rs imm 0 ? 0 1 rt 0 0 0 0 0 0 // SLTI -32'b001011?????????????????????????? 1 1 8 1 1 0 rs imm 0 ? 0 1 rt 0 0 0 0 0 0 // SLTIU -32'b001100?????????????????????????? 1 1 4 ? 0 0 rs imm 0 ? 0 1 rt 0 0 0 0 0 0 // ANDI -32'b001101?????????????????????????? 1 1 5 0 0 0 rs imm 0 ? 0 1 rt 0 0 0 0 0 0 // ORI -32'b001110?????????????????????????? 1 1 6 ? 0 0 rs imm 0 ? 0 1 rt 0 0 0 0 0 0 // XORI -32'b00111100000????????????????????? 1 1 3 0 ? 1 0 imm 0 ? 0 1 rt 0 0 0 0 0 0 // LUI -32'b01000000000??????????00000000??? 1 0 3 0 ? ? ? ? ? ? ? 1 rd 1 ? ? 0 0 0 // MFC0 -32'b01000000100??????????00000000??? 1 0 3 0 ? ? ? ? ? ? ? 0 ? ? ? ? 1 0 0 // MTC0 -32'b01000010000000000000000000011000 1 1 ? ? ? ? ? ? 0 ? 0 0 ? ? ? ? 0 0 0 // ERET -32'b100000?????????????????????????? 0 1 3 0 1 0 rs imm 1 1 0 1 rt 0 0 0 0 0 0 // LB -32'b100001?????????????????????????? 0 1 3 0 1 0 rs imm 1 1 0 1 rt 0 0 0 0 0 0 // LH -32'b100011?????????????????????????? 0 1 3 0 1 0 rs imm 1 1 0 1 rt 0 0 0 0 0 0 // LW -32'b100100?????????????????????????? 0 1 3 0 1 0 rs imm 1 0 0 1 rt 0 0 0 0 0 0 // LBU -32'b100101?????????????????????????? 0 1 3 0 1 0 rs imm 1 0 0 1 rt 0 0 0 0 0 0 // LHU -32'b101000?????????????????????????? 0 1 3 0 1 0 rs imm 1 ? 1 0 ? ? ? ? 0 0 0 // SB -32'b101001?????????????????????????? 0 1 3 0 1 0 rs imm 1 ? 1 0 ? ? ? ? 0 0 0 // SH -32'b101011?????????????????????????? 0 1 3 0 1 0 rs imm 1 ? 1 0 ? ? ? ? 0 0 0 // SW \ No newline at end of file diff --git a/tools/ctrl.txt b/tools/ctrl.txt deleted file mode 100644 index 8af61a8..0000000 --- a/tools/ctrl.txt +++ /dev/null @@ -1,58 +0,0 @@ -////-------------------------------- ERET SYSCALL BREAK PCS BJRJ JR BJR BE DP0 DP1 UI IX SA SB OP ALT OFA MR MWR MX RD RW RS0 HW LW C0W HLS -32'b00000000000???????????????000000 0 0 0 ? 0 0 0 0 1 1 ? ? SA RT SL 0 0 0 ? ? RD 1 ALUOut 0 0 0 ? -32'b00000000000???????????????000010 0 0 0 ? 0 0 0 0 1 1 ? ? SA RT SR 0 0 0 ? ? RD 1 ALUOut 0 0 0 ? -32'b00000000000???????????????000011 0 0 0 ? 0 0 0 0 1 1 ? ? SA RT SR 1 0 0 ? ? RD 1 ALUOut 0 0 0 ? -32'b000000???????????????00000000100 0 0 0 ? 0 0 0 0 1 1 ? ? RS RT SL ? 0 0 ? ? RD 1 ALUOut 0 0 0 ? -32'b000000???????????????00000000110 0 0 0 ? 0 0 0 0 1 1 ? ? RS RT SR 0 0 0 ? ? RD 1 ALUOut 0 0 0 ? -32'b000000???????????????00000000111 0 0 0 ? 0 0 0 0 1 1 ? ? RS RT SR 1 0 0 ? ? RD 1 ALUOut 0 0 0 ? -32'b000000?????000000000000000001000 0 0 0 JR 1 1 1 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ? -32'b000000?????00000?????00000001001 0 0 0 JR 1 1 1 0 1 1 ? ? PC 8 ADD 0 0 0 ? ? RD 1 ALUOut 0 0 0 ? -32'b000000????????????????????001100 0 1 0 ? 0 0 0 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ? -32'b000000????????????????????001101 0 0 1 ? 0 0 0 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ? -32'b0000000000000000?????00000010000 0 0 0 ? 0 0 0 0 1 0 ? ? PC 8 ? ? 0 ? ? ? RD 1 HI 0 0 0 ? -32'b000000?????000000000000000010001 0 0 0 ? 0 0 0 0 1 0 ? ? PC 8 ? ? 0 ? ? ? ? 0 ? 1 0 0 RS -32'b0000000000000000?????00000010010 0 0 0 ? 0 0 0 0 1 0 ? ? PC 8 ? ? 0 ? ? ? RD 1 LO 0 0 0 ? -32'b000000?????000000000000000010011 0 0 0 ? 0 0 0 0 1 0 ? ? PC 8 ? ? 0 ? ? ? ? 0 ? 0 1 0 RS -32'b000000??????????0000000000011000 0 0 0 ? 0 0 0 0 1 0 ? ? RS RT ? ? 0 ? ? ? ? 0 ? 1 1 0 MULT -32'b000000??????????0000000000011001 0 0 0 ? 0 0 0 0 1 0 ? ? RS RT ? ? 0 ? ? ? ? 0 ? 1 1 0 MULTU -32'b000000??????????0000000000011010 0 0 0 ? 0 0 0 0 1 0 ? ? RS RT ? ? 0 ? ? ? ? 0 ? 1 1 0 DIV -32'b000000??????????0000000000011011 0 0 0 ? 0 0 0 0 1 0 ? ? RS RT ? ? 0 ? ? ? ? 0 ? 1 1 0 DIVU -32'b000000???????????????00000100000 0 0 0 ? 0 0 0 0 1 1 ? ? RS RT ADD 0 1 0 ? ? RD 1 ALUOut 0 0 0 ? -32'b000000???????????????00000100001 0 0 0 ? 0 0 0 0 1 1 ? ? RS RT ADD 0 0 0 ? ? RD 1 ALUOut 0 0 0 ? -32'b000000???????????????00000100010 0 0 0 ? 0 0 0 0 1 1 ? ? RS RT ADD 1 1 0 ? ? RD 1 ALUOut 0 0 0 ? -32'b000000???????????????00000100011 0 0 0 ? 0 0 0 0 1 1 ? ? RS RT ADD 1 0 0 ? ? RD 1 ALUOut 0 0 0 ? -32'b000000???????????????00000100100 0 0 0 ? 0 0 0 0 1 1 ? ? RS RT AND ? 0 0 ? ? RD 1 ALUOut 0 0 0 ? -32'b000000???????????????00000100101 0 0 0 ? 0 0 0 0 1 1 ? ? RS RT OR 0 0 0 ? ? RD 1 ALUOut 0 0 0 ? -32'b000000???????????????00000100110 0 0 0 ? 0 0 0 0 1 1 ? ? RS RT XOR ? 0 0 ? ? RD 1 ALUOut 0 0 0 ? -32'b000000???????????????00000100111 0 0 0 ? 0 0 0 0 1 1 ? ? RS RT OR 1 0 0 ? ? RD 1 ALUOut 0 0 0 ? -32'b000000???????????????00000101010 0 0 0 ? 0 0 0 0 1 1 ? ? RS RT SLT 1 0 0 ? ? RD 1 ALUOut 0 0 0 ? -32'b000000???????????????00000101011 0 0 0 ? 0 0 0 0 1 1 ? ? RS RT SLTU 1 0 0 ? ? RD 1 ALUOut 0 0 0 ? -32'b000001?????00000???????????????? 0 0 0 B 1 0 1 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ? -32'b000001?????10000???????????????? 0 0 0 B 1 0 1 0 1 1 ? ? PC 8 ADD 0 0 0 ? ? 31 1 ALUOut 0 0 0 ? -32'b000001?????00001???????????????? 0 0 0 B 1 0 1 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ? -32'b000001?????10001???????????????? 0 0 0 B 1 0 1 0 1 1 ? ? PC 8 ADD 0 0 0 ? ? 31 1 ALUOut 0 0 0 ? -32'b000010?????????????????????????? 0 0 0 J 1 0 0 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ? -32'b000011?????????????????????????? 0 0 0 J 1 0 0 0 1 1 ? ? PC 8 ADD 0 0 0 ? ? 31 1 ALUOut 0 0 0 ? -32'b000100?????????????????????????? 0 0 0 B 1 0 1 1 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ? -32'b000101?????????????????????????? 0 0 0 B 1 0 1 1 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ? -32'b000110?????00000???????????????? 0 0 0 B 1 0 1 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ? -32'b000111?????00000???????????????? 0 0 0 B 1 0 1 0 1 1 ? ? PC 8 ? ? 0 0 ? ? ? 0 ? 0 0 0 ? -32'b001000?????????????????????????? 0 0 0 ? 0 0 0 0 1 1 0 1 RS IMM ADD 0 1 0 ? ? RT 1 ALUOut 0 0 0 ? -32'b001001?????????????????????????? 0 0 0 ? 0 0 0 0 1 1 0 1 RS IMM ADD 0 0 0 ? ? RT 1 ALUOut 0 0 0 ? -32'b001010?????????????????????????? 0 0 0 ? 0 0 0 0 1 1 0 1 RS IMM SLT 1 0 0 ? ? RT 1 ALUOut 0 0 0 ? -32'b001011?????????????????????????? 0 0 0 ? 0 0 0 0 1 1 0 1 RS IMM SLTU 1 0 0 ? ? RT 1 ALUOut 0 0 0 ? -32'b001100?????????????????????????? 0 0 0 ? 0 0 0 0 1 1 0 0 RS IMM AND ? 0 0 ? ? RT 1 ALUOut 0 0 0 ? -32'b001101?????????????????????????? 0 0 0 ? 0 0 0 0 1 1 0 0 RS IMM OR 0 0 0 ? ? RT 1 ALUOut 0 0 0 ? -32'b001110?????????????????????????? 0 0 0 ? 0 0 0 0 1 1 0 0 RS IMM XOR ? 0 0 ? ? RT 1 ALUOut 0 0 0 ? -32'b00111100000????????????????????? 0 0 0 ? 0 0 0 0 1 1 1 ? 0 IMM ADD 0 0 0 ? ? RT 1 ALUOut 0 0 0 ? -32'b01000000000??????????00000000??? 0 0 0 ? 0 0 0 0 1 0 ? ? 0 IMM ? ? 0 ? ? ? RT 1 C0 0 0 0 ? -32'b01000000100??????????00000000??? 0 0 0 ? 0 0 0 0 1 0 ? ? 0 IMM ? ? 0 ? ? ? ? 0 ? 0 0 1 ? -32'b01000010000000000000000000011000 1 0 0 ? 0 0 0 0 1 1 ? ? 0 IMM ? ? 0 0 ? ? ? 0 ? 0 0 0 ? -32'b100000?????????????????????????? 0 0 0 ? 0 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 0 1 RT 1 ? ? ? ? ? -32'b100001?????????????????????????? 0 0 0 ? 0 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 0 1 RT 1 ? ? ? ? ? -32'b100011?????????????????????????? 0 0 0 ? 0 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 0 ? RT 1 ? ? ? ? ? -32'b100100?????????????????????????? 0 0 0 ? 0 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 0 0 RT 1 ? ? ? ? ? -32'b100101?????????????????????????? 0 0 0 ? 0 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 0 0 RT 1 ? ? ? ? ? -32'b101000?????????????????????????? 0 0 0 ? 0 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 1 ? ? 0 ? ? ? ? ? -32'b101001?????????????????????????? 0 0 0 ? 0 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 1 ? ? 0 ? ? ? ? ? -32'b101011?????????????????????????? 0 0 0 ? 0 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 1 ? ? 0 ? ? ? ? ? diff --git a/tools/ctrl_maker.py b/tools/ctrl_maker.py index 910b26b..ec48f5f 100644 --- a/tools/ctrl_maker.py +++ b/tools/ctrl_maker.py @@ -1,4 +1,4 @@ -with open('ctrl.txt') as f: +with open('global.txt') as f: lines = f.readlines() title = lines[0].split() items = [x.split() for x in lines[1:]] diff --git a/tools/global.txt b/tools/global.txt new file mode 100644 index 0000000..4fd9aab --- /dev/null +++ b/tools/global.txt @@ -0,0 +1,69 @@ +////-------------------------------- ERET DP0 DP1 +32'b00000000000???????????????000010 0 1 1 // SRL +32'b00000000000???????????????000000 0 1 1 // SLL +32'b00000000000???????????????000011 0 1 1 // SRA +32'b000000???????????????00000000100 0 1 1 // SLLV +32'b000000???????????????00000000110 0 1 1 // SRLV +32'b000000???????????????00000000111 0 1 1 // SRAV +32'b000000?????000000000000000001000 0 1 1 // JR +32'b000000?????00000?????00000001001 0 1 1 // JALR +32'b000000????????????????????001100 0 1 1 // SYSCALL +32'b000000????????????????????001101 0 1 1 // BREAK +32'b0000000000000000?????00000010000 0 1 0 // MFHI +32'b000000?????000000000000000010001 0 1 0 // MTHI +32'b0000000000000000?????00000010010 0 1 0 // MFLO +32'b000000?????000000000000000010011 0 1 0 // MTLO +32'b000000??????????0000000000011000 0 1 0 // MULT +32'b000000??????????0000000000011001 0 1 0 // MULTU +32'b000000??????????0000000000011010 0 1 0 // DIV +32'b000000??????????0000000000011011 0 1 0 // DIVU +32'b000000???????????????00000100000 0 1 1 // ADD +32'b000000???????????????00000100001 0 1 1 // ADDU +32'b000000???????????????00000100010 0 1 1 // SUB +32'b000000???????????????00000100011 0 1 1 // SUBU +32'b000000???????????????00000100100 0 1 1 // AND +32'b000000???????????????00000100101 0 1 1 // OR +32'b000000???????????????00000100110 0 1 1 // XOR +32'b000000???????????????00000100111 0 1 1 // NOR +32'b000000???????????????00000101010 0 1 1 // SLT +32'b000000???????????????00000101011 0 1 1 // SLTU +32'b000001?????00000???????????????? 0 1 1 // BLTZ +32'b000001?????10000???????????????? 0 1 1 // BLTZAL +32'b000001?????00001???????????????? 0 1 1 // BGEZ +32'b000001?????10001???????????????? 0 1 1 // BGEZAL +32'b000010?????????????????????????? 0 1 1 // J +32'b000011?????????????????????????? 0 1 1 // JAL +32'b000100?????????????????????????? 0 1 1 // BEQ +32'b000101?????????????????????????? 0 1 1 // BNE +32'b000110?????00000???????????????? 0 1 1 // BLEZ +32'b000111?????00000???????????????? 0 1 1 // BGTZ +32'b001000?????????????????????????? 0 1 1 // ADDI +32'b001001?????????????????????????? 0 1 1 // ADDIU +32'b001010?????????????????????????? 0 1 1 // SLTI +32'b001011?????????????????????????? 0 1 1 // SLTIU +32'b001100?????????????????????????? 0 1 1 // ANDI +32'b001101?????????????????????????? 0 1 1 // ORI +32'b001110?????????????????????????? 0 1 1 // XORI +32'b00111100000????????????????????? 0 1 1 // LUI +32'b01000000000??????????00000000??? 0 1 0 // MFC0 +32'b01000000100??????????00000000??? 0 1 0 // MTC0 +32'b01000010000000000000000000000001 0 0 1 // TLBR +32'b01000010000000000000000000000010 0 0 1 // TLBWI +32'b01000010000000000000000000001000 0 0 1 // TLBP +32'b01000010000000000000000000011000 1 1 1 // ERET +32'b011100???????????????00000000010 0 1 0 // MUL +32'b100000?????????????????????????? 0 0 1 // LB +32'b100001?????????????????????????? 0 0 1 // LH +32'b100011?????????????????????????? 0 0 1 // LW +32'b100100?????????????????????????? 0 0 1 // LBU +32'b100101?????????????????????????? 0 0 1 // LHU +32'b101000?????????????????????????? 0 0 1 // SB +32'b101001?????????????????????????? 0 0 1 // SH +32'b101011?????????????????????????? 0 0 1 // SW +32'b101111?????00000???????????????? 0 0 1 // I-Cache Index Invalid +32'b101111?????01000???????????????? 0 0 1 // I-Cache Index Store Tag +32'b101111?????10000???????????????? 0 0 1 // I-Cache Hit Invalid +32'b101111?????00001???????????????? 0 0 1 // D-Cache Index Writeback Invalid +32'b101111?????01001???????????????? 0 0 1 // D-Cache Index Store Tag +32'b101111?????10001???????????????? 0 0 1 // D-Cache Hit Invalid +32'b101111?????10101???????????????? 0 0 1 // D-Cache Hit Writeback Invalid diff --git a/tools/instrqueue.sv b/tools/instrqueue.sv deleted file mode 100644 index 7ee5626..0000000 --- a/tools/instrqueue.sv +++ /dev/null @@ -1,16 +0,0 @@ -///------ HandShake_out1.readygo HandShake_out2.readygo out1 out2 HandShake_in1.allowin HandShake_in2.allowin en1 en2 en3 en4 di1 di2 di3 di4 -6'b000000 0 0 qi1 qi2 1 1 1 1 0 0 in1 in2 ? ? -6'b000010 0 0 qi1 qi2 1 1 1 1 0 0 in1 in2 ? ? -6'b000011 0 0 qi1 qi2 1 1 1 1 0 0 in1 in2 ? ? -6'b000100 0 0 qi1 qi2 1 0 0 1 1 0 ? in1 in2 ? -6'b000110 1 0 qi1 qi2 1 1 1 1 0 0 in1 in2 ? ? -6'b000111 1 0 qi1 qi2 1 1 1 1 0 0 in1 in2 ? ? -6'b001100 0 0 qi1 qi2 0 0 0 0 1 1 ? ? in1 in2 -6'b001110 1 0 qi1 qi2 1 0 1 1 1 0 qi2 in1 in2 ? -6'b001111 1 1 qi1 qi2 1 1 1 1 0 0 in1 in2 ? ? -6'b011100 0 0 qi1 qi2 0 0 0 0 0 1 ? ? ? in1 -6'b011110 1 0 qi1 qi2 0 0 1 1 1 1 qi2 qi3 in1 in2 -6'b011111 1 1 qi1 qi2 1 0 1 1 1 0 qi3 in1 in2 ? -6'b111100 0 0 qi1 qi2 0 0 0 0 0 0 ? ? ? ? -6'b111110 1 0 qi1 qi2 0 0 1 1 1 1 qi2 qi3 qi4 in1 -6'b111111 1 1 qi1 qi2 0 0 1 1 1 1 qi3 qi4 in1 in2 \ No newline at end of file diff --git a/tools/iq.sv b/tools/iq.sv deleted file mode 100644 index d9c6e0b..0000000 --- a/tools/iq.sv +++ /dev/null @@ -1,21 +0,0 @@ -///------ en3 en4 -6'b000000 0 0 -6'b000001 0 0 -6'b000010 0 0 -6'b000011 0 0 -6'b000100 1 0 -6'b000101 0 0 -6'b000110 0 0 -6'b000111 0 0 -6'b001100 1 1 -6'b001101 0 0 -6'b001110 1 0 -6'b001111 0 0 -6'b011100 0 1 -6'b011101 0 0 -6'b011110 1 1 -6'b011111 1 0 -6'b111100 0 0 -6'b111101 0 0 -6'b111110 1 1 -6'b111111 1 1 \ No newline at end of file diff --git a/tools/out1.txt b/tools/out1.txt deleted file mode 100644 index 0509c85..0000000 --- a/tools/out1.txt +++ /dev/null @@ -1,19 +0,0 @@ -assign ctrl.ERET = inst[30] & inst[25]; -assign ctrl.SYSCALL = ~inst[26] & ~inst[29] & ~inst[30] & ~inst[28] & ~inst[31] & ~inst[27] & inst[2] & inst[3] & ~inst[0]; -assign ctrl.BREAK = ~inst[26] & ~inst[29] & ~inst[30] & ~inst[28] & ~inst[31] & ~inst[27] & inst[2] & inst[3] & inst[0]; -assign ctrl.PFCtrl.BJRJ = ~inst[26] & (~inst[27] & (~inst[28] & ~inst[30] & ~inst[31] & ~inst[29] & inst[3] & ~inst[4] & ~inst[5] & ~inst[2] | inst[28] & ~inst[31] & ~inst[29]) | inst[27] & ~inst[29]) | inst[26] & ~inst[29] & ~inst[31]; -assign ctrl.PFCtrl.BJR = ~inst[26] & (~inst[28] & ~inst[30] & ~inst[29] & ~inst[31] & ~inst[27] & inst[3] & ~inst[4] & ~inst[5] & ~inst[2] | inst[28] & ~inst[29] & ~inst[31]) | inst[26] & ~inst[29] & ~inst[31] & (~inst[27] | inst[27] & inst[28]); -assign ctrl.PFCtrl.BE = inst[28] & ~inst[29] & ~inst[31] & ~inst[27]; -assign ctrl.DCtrl.DP0 = ~inst[31]; -assign ctrl.DCtrl.DP1 = ~inst[30] & (~inst[26] & (~inst[29] & (~inst[28] & (~inst[31] & (~inst[27] & ~inst[4] | inst[27]) | inst[31]) | inst[28]) | inst[29]) | inst[26]) | inst[30] & inst[25]; -assign ctrl.DCtrl.UI = inst[28] & inst[27] & inst[26]; -assign ctrl.DCtrl.IX = ~inst[28] | inst[28] & inst[31]; -assign ctrl.ECtrl.ALT = ~inst[31] & (~inst[26] & (~inst[27] & ~inst[29] & inst[1] & (~inst[5] & inst[0] | inst[5]) | inst[27]) | inst[26] & inst[27] & inst[29] & ~inst[28]); -assign ctrl.OFA = ~inst[26] & (~inst[29] & ~inst[30] & ~inst[28] & ~inst[31] & ~inst[27] & inst[5] & ~inst[0] & ~inst[2] & ~inst[3] | inst[29] & ~inst[28] & ~inst[31] & ~inst[27]); -assign ctrl.MCtrl1.MR = inst[31]; -assign ctrl.MCtrl1.MWR = inst[29]; -assign ctrl.MCtrl1.MX = ~inst[28]; -assign ctrl.WCtrl.RW = ~inst[30] & (~inst[29] & (~inst[31] & ~inst[28] & (~inst[27] & (~inst[26] & (~inst[3] & (~inst[4] | inst[4] & ~inst[0]) | inst[3] & (~inst[5] & ~inst[4] & ~inst[2] & inst[0] | inst[5])) | inst[26] & inst[20]) | inst[27] & inst[26]) | inst[31]) | inst[29] & ~inst[31]) | inst[30] & ~inst[25] & ~inst[23]; -assign ctrl.MCtrl0.HW = ~inst[26] & ~inst[29] & ~inst[30] & ~inst[28] & ~inst[27] & inst[4] & (~inst[3] & ~inst[1] & inst[0] | inst[3]); -assign ctrl.MCtrl0.LW = ~inst[26] & ~inst[29] & ~inst[30] & ~inst[28] & ~inst[27] & inst[4] & (~inst[3] & inst[1] & inst[0] | inst[3]); -assign ctrl.MCtrl0.C0W = inst[30] & inst[23]; diff --git a/tools/out2.txt b/tools/out2.txt deleted file mode 100644 index a939441..0000000 --- a/tools/out2.txt +++ /dev/null @@ -1,88 +0,0 @@ -SA -'SA': '~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[5] & (~inst[4] & ~inst[3] & ~inst[2] & ~inst[1] | ~inst[4] & ~inst[3] & ~inst[2] & inst[1])' -'RS': '~inst[30] & (~inst[29] & (~inst[31] & ~inst[26] & ~inst[28] & ~inst[27] & (~inst[5] & (~inst[1] & (~inst[4] & ~inst[3] & inst[2] | inst[4] & inst[3]) | inst[1] & (~inst[3] & ~inst[4] & inst[2] | inst[3])) | inst[5]) | inst[31]) | inst[29] & (~inst[28] | inst[28] & (~inst[27] | inst[27] & ~inst[26])))' -'PC': '~inst[30] & ~inst[29] & ~inst[31] & (~inst[26] & (~inst[28] & (~inst[27] & ~inst[5] & (~inst[1] & (~inst[4] & inst[3] | inst[4] & ~inst[3]) | inst[1] & ~inst[3] & inst[4]) | inst[27]) | inst[28]) | inst[26])' -'0': '(~inst[30] & inst[29] & inst[28] & inst[27] & inst[26] | inst[30])' - - 2'b11 & (~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[5] & ~inst[4] & ~inst[3] & ~inst[2]) -| 2'b10 & (~inst[30] & (~inst[29] & (~inst[26] & ~inst[28] & ~inst[27] & ((~inst[1] & (~inst[4] & ~inst[3] & inst[2] | inst[4] & inst[3]) | inst[1] & (~inst[4] & inst[2] | inst[3])) | inst[5]) | inst[31]) | inst[29] & (~inst[28] | ~inst[27] | ~inst[26]))) -| 2'b01 & (~inst[31] & ~inst[30] & ~inst[29] & (((~inst[5] & (~inst[1] & (~inst[4] & inst[3] | inst[4] & ~inst[3]) | inst[1] & ~inst[3] & inst[4]) | inst[27]) | inst[28]) | inst[26])) -| 2'b00 & (inst[29] & inst[28] & inst[27] & inst[26] | inst[30]) - -'SA': 2'b11 -'RS': 2'b10 -'PC': 2'b01 -'0' : 2'b00 - -SA -{'SA': '~[30] & ~[29] & ~[31] & ~[26] & ~[28] & ~[27] & ~[5] & (~[1] & ~[4] & ~[3] & ~[2] | [1] & ~[3] & ~[4] & ~[2])', 'RS': '~[30] & (~[29] & (~[31] & ~[26] & ~[28] & ~[27] & (~[5] & (~[1] & (~[4] & ~[3] & [2] | [4] & [3]) | [1] & (~[3] & ~[4] & [2] | [3])) | [5]) | [31]) | [29] & (~[28] | [28] & (~[27] | [27] & ~[26])))', 'PC': '~[30] & ~[29] & ~[31] & (~[26] & (~[28] & (~[27] & ~[5] & (~[1] & (~[4] & [3] | [4] & ~[3]) | [1] & ~[3] & [4]) | [27]) | [28]) | [26])', '0': '(~[30] & [29] & [28] & [27] & [26] | [30])'} -1 -{'0': '~[29] & ~[31] & (~[26] & (~[28] & ~[30] & (~[27] & ~[5] & (~[2] & (~[3] | [3] & ~[4]) | [2] & [3]) | [27]) | [28]) | [26])', '1': '(~[29] & (~[31] & ~[26] & ~[28] & (~[30] & ~[27] & (~[5] & (~[2] & [3] & [4] | [2] & ~[3]) | [5]) | [30]) | [31]) | [29])'} -0 -{'0': '(~[30] & ~[31] & (~[29] & ~[26] & ~[28] & ~[27] & ~[5] & ~[4] & ~[2] & ~[3] | [29] & [28] & [27] & [26]) | [30])', '1': '~[30] & (~[31] & (~[29] & (~[26] & (~[28] & (~[27] & (~[5] & (~[4] & (~[2] & [3] | [2]) | [4]) | [5]) | [27]) | [28]) | [26]) | [29] & (~[28] | [28] & (~[27] | [27] & ~[26]))) | [31])'} - - -{((~inst[26] & ~inst[28] & (~inst[27] & ((~inst[2] & inst[3] & inst[4] | inst[2] & ~inst[3]) | inst[5]) | inst[30]) | inst[31]) | inst[29]),~inst[30] & ((~inst[29] & (inst[3] | inst[2] | inst[4] | inst[5] | inst[27] | inst[28] | inst[26]) | inst[29] & (~inst[28] | ~inst[27] | ~inst[26])) | inst[31])} - - -SB -'RT': '~inst[29] & ~inst[31] & ~inst[26] & ~inst[30] & ~inst[28] & ~inst[27] & (~inst[5] & (~inst[1] & (~inst[0] & (~inst[3] & ~inst[4] | inst[3] & inst[4]) | inst[0] & inst[4] & inst[3]) | inst[1] & (~inst[4] | inst[4] & inst[3])) | inst[5])' -'8': '~inst[29] & ~inst[31] & (~inst[26] & ~inst[30] & (~inst[28] & (~inst[27] & ~inst[5] & (~inst[1] & (~inst[0] & (~inst[3] & inst[4] | inst[3] & ~inst[4]) | inst[0] & (~inst[4] | inst[4] & ~inst[3])) | inst[1] & inst[4] & ~inst[3]) | inst[27]) | inst[28]) | inst[26])' -'IMM': '(~inst[29] & (~inst[31] & ~inst[26] & inst[30] | inst[31]) | inst[29])' - - 2'b10 & (~inst[29] & ~inst[31] & ~inst[26] & ~inst[30] & ~inst[28] & ~inst[27] & ((~inst[1] & (~inst[0] & (~inst[3] & ~inst[4] | inst[3] & inst[4]) | inst[0] & inst[4] & inst[3]) | inst[1] & (~inst[4] | inst[4] & inst[3])) | inst[5])) -| 2'b01 & (~inst[29] & ~inst[31] & (~inst[30] & ((~inst[5] & (~inst[1] & (~inst[0] & (~inst[3] & inst[4] | inst[3] & ~inst[4]) | inst[0] & (~inst[4] | ~inst[3])) | inst[1] & inst[4] & ~inst[3]) | inst[27]) | inst[28]) | inst[26])) -| 2'b00 & (inst[30] & ~inst[26] | inst[31] | inst[29]) -RT: 10 -8: 01 -IMM:00 - -SB -{'RT': '~[29] & ~[31] & ~[26] & ~[30] & ~[28] & ~[27] & (~[5] & (~[1] & (~[0] & (~[3] & ~[4] | [3] & [4]) | [0] & [4] & [3]) | [1] & (~[4] | [4] & [3])) | [5])', '8': '~[29] & ~[31] & (~[26] & ~[30] & (~[28] & (~[27] & ~[5] & (~[1] & (~[0] & (~[3] & [4] | [3] & ~[4]) | [0] & (~[4] | [4] & ~[3])) | [1] & [4] & ~[3]) | [27]) | [28]) | [26])', 'IMM': '(~[29] & (~[31] & ~[26] & [30] | [31]) | [29])'} -1 -{'0': '~[26] & ~[29] & ~[30] & ~[28] & ~[31] & ~[27] & (~[5] & (~[1] & (~[0] & (~[3] & ~[4] | [3] & [4]) | [0] & [4] & [3]) | [1] & (~[4] | [4] & [3])) | [5])', '1': '(~[26] & (~[29] & (~[30] & (~[28] & (~[31] & (~[27] & ~[5] & (~[1] & (~[0] & (~[3] & [4] | [3] & ~[4]) | [0] & (~[4] | [4] & ~[3])) | [1] & [4] & ~[3]) | [27]) | [31]) | [28]) | [30]) | [29]) | [26])'} -0 -{'0': '~[29] & ~[31] & ~[30]', '1': '(~[29] & (~[31] & [30] | [31]) | [29])'} - -{(~inst[5] & (~inst[1] & (~inst[0] & (~inst[3] & inst[4] | inst[3] & ~inst[4]) | inst[0] & (~inst[4] | ~inst[3])) | inst[1] & inst[4] & ~inst[3]) | inst[27] | inst[31] | inst[28] | inst[30] | inst[29] | inst[26]),((inst[30] | inst[31]) | inst[29])} - -OP -assign ctrl.ECtrl.OP.f_sr = ~inst[31] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[5] & ~inst[3] & (~inst[2] | inst[1]); -assign ctrl.ECtrl.OP.f_sl = ~inst[31] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[5] & ~inst[3] & inst[2] & ~inst[1]; -assign ctrl.ECtrl.OP.f_add = ((~inst[26] & ~inst[28] & ~inst[27] & ((~inst[5] & inst[3] | inst[5] & ~inst[3] & ~inst[2]) | inst[29]) | inst[26] & (~inst[29] | (~inst[28] & ~inst[27] | inst[28] & inst[27]))) | inst[31]); -assign ctrl.ECtrl.OP.f_slt = ~inst[31] & ~inst[26] & ~inst[28] & (~inst[29] & inst[5] & inst[3] & ~inst[2] & ~inst[0] | inst[27]); -assign ctrl.ECtrl.OP.f_sltu = ~inst[31] & (~inst[26] & ~inst[28] & ~inst[27] & ~inst[29] & inst[5] & ~inst[2] & inst[3] & inst[0] | inst[26] & inst[29] & ~inst[28] & inst[27]); -assign ctrl.ECtrl.OP.f_ans = ~inst[31] & ~inst[26] & (~inst[28] & ~inst[27] & ~inst[29] & inst[5] & inst[2] & ~inst[0] & ~inst[1] | inst[28] & ~inst[27]); -assign ctrl.ECtrl.OP.f_xor = ~inst[31] & ~inst[26] & (~inst[28] & ~inst[27] & ~inst[29] & inst[5] & inst[2] & ~inst[0] & inst[1] | inst[28] & inst[27]); -assign ctrl.ECtrl.OP.f_or = ~inst[31] & (~inst[26] & ~inst[28] & ~inst[27] & ~inst[29] & inst[5] & inst[2] & inst[0] | inst[26] & inst[29] & inst[28] & ~inst[27]); - - - - - -RD -'RD': '~inst[31] & ~inst[29] & ~inst[26]' -'31': '~inst[31] & ~inst[29] & inst[26]' -'RT': 'inst[31] | inst[29]' - -{inst[31] | inst[29], inst[26]} -RT: 1? -RD: 00 -31: 01 - - - -RS0 -{'ALUOut': '~[30] & (~[29] & (~[26] & ~[4] | [26]) | [29])', 'HI': '~[30] & ~[29] & ~[26] & [4] & ~[1]', 'LO': '~[30] & ~[29] & ~[26] & [4] & [1]', 'C0': '[30]'} -0 -{'1': '(~[29] & ~[28] & (~[26] & ~[4] | [26]) | [29])', '0': '~[29] & (~[28] & ~[26] & [4] | [28])'} -1 -{'0': '~[30] & (~[29] & (~[26] & (~[4] | [4] & [1]) | [26]) | [29])', '1': } - -{(~inst[29] & ~inst[26] & inst[4] & ~inst[1] | inst[30]),(~inst[28] & (~inst[4] | inst[26]) | inst[29])} - - - - -HLS -{'RS': '~inst[3]', 'MULT': 'inst[3] & ~inst[1] & ~inst[0]', 'MULTU': 'inst[3] & ~inst[1] & inst[0]', 'DIV': 'inst[3] & inst[1] & ~inst[0]', 'DIVU': 'inst[3] & inst[1] & inst[0]'} diff --git a/tools/rs0out.txt b/tools/rs0out.txt deleted file mode 100644 index 00e2a27..0000000 --- a/tools/rs0out.txt +++ /dev/null @@ -1,6 +0,0 @@ -RS0 -{'ALUOut': '~[30] & (~[29] & (~[26] & ~[4] | [26]) | [29])', 'HI': '~[30] & ~[29] & ~[26] & [4] & ~[1]', 'LO': '~[30] & ~[29] & ~[26] & [4] & [1]', 'C0': '[30]'} -1 -{'1': '(~[29] & (~[26] & ~[4] | [26]) | [29])', '0': '~[29] & ~[26] & [4]'} -0 -{'0': '~[30] & (~[29] & (~[26] & (~[4] | [4] & [1]) | [26]) | [29])', '1': '(~[30] & ~[29] & ~[26] & [4] & ~[1] | [30])'} diff --git a/tools/tlb.txt b/tools/tlb.txt new file mode 100644 index 0000000..722309a --- /dev/null +++ b/tools/tlb.txt @@ -0,0 +1,69 @@ +////-------------------------------- TLBR TLBWI TLBP +32'b00000000000???????????????000000 0 0 0 // SLL +32'b00000000000???????????????000010 0 0 0 // SRL +32'b00000000000???????????????000011 0 0 0 // SRA +32'b000000???????????????00000000100 0 0 0 // SLLV +32'b000000???????????????00000000110 0 0 0 // SRLV +32'b000000???????????????00000000111 0 0 0 // SRAV +32'b000000?????000000000000000001000 0 0 0 // JR +32'b000000?????00000?????00000001001 0 0 0 // JALR +32'b000000????????????????????001100 0 0 0 // SYSCALL +32'b000000????????????????????001101 0 0 0 // BREAK +32'b0000000000000000?????00000010000 0 0 0 // MFHI +32'b000000?????000000000000000010001 0 0 0 // MTHI +32'b0000000000000000?????00000010010 0 0 0 // MFLO +32'b000000?????000000000000000010011 0 0 0 // MTLO +32'b000000??????????0000000000011000 0 0 0 // MULT +32'b000000??????????0000000000011001 0 0 0 // MULTU +32'b000000??????????0000000000011010 0 0 0 // DIV +32'b000000??????????0000000000011011 0 0 0 // DIVU +32'b000000???????????????00000100000 0 0 0 // ADD +32'b000000???????????????00000100001 0 0 0 // ADDU +32'b000000???????????????00000100010 0 0 0 // SUB +32'b000000???????????????00000100011 0 0 0 // SUBU +32'b000000???????????????00000100100 0 0 0 // AND +32'b000000???????????????00000100101 0 0 0 // OR +32'b000000???????????????00000100110 0 0 0 // XOR +32'b000000???????????????00000100111 0 0 0 // NOR +32'b000000???????????????00000101010 0 0 0 // SLT +32'b000000???????????????00000101011 0 0 0 // SLTU +32'b000001?????00000???????????????? 0 0 0 // BLTZ +32'b000001?????10000???????????????? 0 0 0 // BLTZAL +32'b000001?????00001???????????????? 0 0 0 // BGEZ +32'b000001?????10001???????????????? 0 0 0 // BGEZAL +32'b000010?????????????????????????? 0 0 0 // J +32'b000011?????????????????????????? 0 0 0 // JAL +32'b000100?????????????????????????? 0 0 0 // BEQ +32'b000101?????????????????????????? 0 0 0 // BNE +32'b000110?????00000???????????????? 0 0 0 // BLEZ +32'b000111?????00000???????????????? 0 0 0 // BGTZ +32'b001000?????????????????????????? 0 0 0 // ADDI +32'b001001?????????????????????????? 0 0 0 // ADDIU +32'b001010?????????????????????????? 0 0 0 // SLTI +32'b001011?????????????????????????? 0 0 0 // SLTIU +32'b001100?????????????????????????? 0 0 0 // ANDI +32'b001101?????????????????????????? 0 0 0 // ORI +32'b001110?????????????????????????? 0 0 0 // XORI +32'b00111100000????????????????????? 0 0 0 // LUI +32'b01000000000??????????00000000??? 0 0 0 // MFC0 +32'b01000000100??????????00000000??? 0 0 0 // MTC0 +32'b01000010000000000000000000000001 1 0 0 // TLBR +32'b01000010000000000000000000000010 0 1 0 // TLBWI +32'b01000010000000000000000000001000 0 0 1 // TLBP +32'b01000010000000000000000000011000 0 0 0 // ERET +32'b011100???????????????00000000010 0 0 0 // MUL +32'b100000?????????????????????????? 0 0 0 // LB +32'b100001?????????????????????????? 0 0 0 // LH +32'b100011?????????????????????????? 0 0 0 // LW +32'b100100?????????????????????????? 0 0 0 // LBU +32'b100101?????????????????????????? 0 0 0 // LHU +32'b101000?????????????????????????? 0 0 0 // SB +32'b101001?????????????????????????? 0 0 0 // SH +32'b101011?????????????????????????? 0 0 0 // SW +32'b101111?????00000???????????????? 0 0 0 // I-Cache Index Invalid +32'b101111?????01000???????????????? 0 0 0 // I-Cache Index Store Tag +32'b101111?????10000???????????????? 0 0 0 // I-Cache Hit Invalid +32'b101111?????00001???????????????? 0 0 0 // D-Cache Index Writeback Invalid +32'b101111?????01001???????????????? 0 0 0 // D-Cache Index Store Tag +32'b101111?????10001???????????????? 0 0 0 // D-Cache Hit Invalid +32'b101111?????10101???????????????? 0 0 0 // D-Cache Hit Writeback Invalid \ No newline at end of file