Config1 auto generate

src/CP0/CP0.sv

@@ -62,7 +62,25 @@ module CP0 (
   // | Watch registers implemented | Code compression implemented |
   // |                 1 |               0 |
   // | EJTAG implemented | FPU implemented |
-  assign rf_cp0.Config1      = 32'b0_000111_000_100_011_001_011_011_0_0_0_0_0_0_0;
+
+  /*verilator lint_off WIDTH*/
+  assign rf_cp0.Config1.Config2        = 1'b0;
+  assign rf_cp0.Config1.MMUSize        = `TLB_ENTRY_NUM - 6'b1;
+  assign rf_cp0.Config1.ICacheSets     = (`IC_TAGL - `IC_INDEXL - 6); // 0->64 1->128 ...
+  assign rf_cp0.Config1.ICacheLineSize = 2 ** `IC_INDEXL;
+  assign rf_cp0.Config1.ICacheAssoc    = `IC_WAYS - 1;
+  assign rf_cp0.Config1.DCacheSets     = (`DC_TAGL - `DC_INDEXL - 6); // 0->64 1->128 ...
+  assign rf_cp0.Config1.DCacheLineSize = 2 ** `DC_INDEXL;
+  assign rf_cp0.Config1.DCacheAssoc    = `DC_WAYS - 1;
+  assign rf_cp0.Config1.CP2            = 1'b0;
+  assign rf_cp0.Config1.MD             = 1'b0;
+  assign rf_cp0.Config1.Perf           = 1'b0;
+  assign rf_cp0.Config1.Watch          = 1'b0;
+  assign rf_cp0.Config1.Compression    = 1'b0;
+  assign rf_cp0.Config1.EJTAG          = 1'b0;
+  assign rf_cp0.Config1.FPU            = 1'b0;
+  /*verilator lint_on WIDTH*/
+
   assign rf_cp0.EBase.one    = 1'b1;
   assign rf_cp0.EBase.zero1  = 1'b0;
   assign rf_cp0.EBase.zero2  = 2'b0;

src/include/CP0.svh

@@ -92,6 +92,24 @@ typedef struct packed {
   logic [9:0]  CPUNum;
 } CP0_REGS_EBASE_t;
 
+typedef struct packed {
+  logic       Config2;         // Config2
+  logic [5:0] MMUSize;         // MMU Size
+  logic [2:0] ICacheSets;      // I$ sets per way
+  logic [2:0] ICacheLineSize;  // I$ line size
+  logic [2:0] ICacheAssoc;     // I$ associativity
+  logic [2:0] DCacheSets;      // D$ sets per way
+  logic [2:0] DCacheLineSize;  // D$ line size
+  logic [2:0] DCacheAssoc;     // D$ associativity
+  logic       CP2;             // Coprocessor 2 implemented
+  logic       MD;              // MD
+  logic       Perf;            // Performance Counter registers
+  logic       Watch;           // Watch registers implemented
+  logic       Compression;     // Code compression implemented
+  logic       EJTAG;           // EJTAG implemented
+  logic       FPU;             // FPU implemented
+} CP0_REGS_CONFIG1_t;
+
 typedef struct packed {
   // ==== sel0 ====
   // word_t DESAVE,
@@ -129,7 +147,7 @@ typedef struct packed {
   Index_t           Index;
 
   // ==== sel1 ====
-  word_t            Config1;
+  CP0_REGS_CONFIG1_t Config1;
   CP0_REGS_EBASE_t   EBase;
 } CP0_REGS_t;
 

src/include/Cache.svh

@@ -10,6 +10,7 @@
 `define IC_DATA_LENGTH (2 ** `IC_INDEXL * 8)  // 64Bytes
 `define IC_ROW_LENGTH  (`IC_DATA_LENGTH / `XLEN - 1)
 `define IC_INDEX_DEPTH (2 ** (`IC_TAGL - `IC_INDEXL))
+`define IC_WAYS        4
 
 typedef logic     [`IC_DATA_LENGTH-1:0] ICData_t;
 typedef logic         [32-`IC_TAGL-1:0] ICTagL_t;
@@ -48,6 +49,7 @@ typedef struct packed {
 `define DC_DATA_LENGTH (2 ** `DC_INDEXL * 8)      // 8Bytes
 `define DC_ROW_LENGTH  (`DC_DATA_LENGTH / `XLEN - 1)
 `define DC_INDEX_DEPTH (2 ** (`DC_TAGL - `DC_INDEXL))
+`define DC_WAYS        4
 
 typedef logic     [`DC_DATA_LENGTH-1:0] DCData_t;
 typedef logic         [32-`DC_TAGL-1:0] DCTagL_t;

src/include/TLB.svh

@@ -1,6 +1,12 @@
 `ifndef TLB_SVH
 `define TLB_SVH
 
+`ifdef ENABLE_TLB
+  `define TLB_ENTRY_NUM 8
+`else
+  `define TLB_ENTRY_NUM 0
+`endif
+
 typedef struct packed {
   logic [18:0] VPN2;
   logic [ 4:0] zero;