diff --git a/README.md b/README.md index 507b678..24221f1 100644 --- a/README.md +++ b/README.md @@ -2,3 +2,18 @@ Magically Improved Pipeline Stages === Our awesome `MIPS` CPU written in `SystemVerilog` for Loongson Cup + +``` +. +├── fpga <-- 实验箱测试顶层文件 +├── resources <-- 资源包 +│ └── 2020 <-- 2020年资源包 +│ ├── cpu132_gettrace <-- 性能测试基准(gs132) +│ ├── soc_axi_func <-- AXI功能测试 +│ ├── soc_axi_perf <-- AXI性能测试 +│ └── soft <-- 测试用程序 +│ ├── func <-- 功能测试 +│ ├── memory_game <-- 记忆游戏 +│ └── perf_func <-- 性能测试 +└── src <-- CPU设计代码 +``` diff --git a/fpga/.gitignore b/fpga/.gitignore new file mode 100644 index 0000000..4da8b30 --- /dev/null +++ b/fpga/.gitignore @@ -0,0 +1 @@ +/vivado/* \ No newline at end of file diff --git a/fpga/constraints.xdc b/fpga/constraints.xdc new file mode 100644 index 0000000..66a78ed --- /dev/null +++ b/fpga/constraints.xdc @@ -0,0 +1,215 @@ +#时钟信号连接 +set_property PACKAGE_PIN AC19 [get_ports clk] +create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { clk }]; + +#脉冲开关，用于输入作为复位信号，低电平有效 +set_property PACKAGE_PIN Y3 [get_ports resetn] + +#脉冲开关，用于输入作为单步执行的clk +set_property PACKAGE_PIN Y5 [get_ports btn_clk] + +set_property IOSTANDARD LVCMOS33 [get_ports clk] +set_property IOSTANDARD LVCMOS33 [get_ports resetn] +set_property IOSTANDARD LVCMOS33 [get_ports btn_clk] + +#触摸屏引脚连接 +set_property PACKAGE_PIN J25 [get_ports lcd_rst] +set_property PACKAGE_PIN H18 [get_ports lcd_cs] +set_property PACKAGE_PIN K16 [get_ports lcd_rs] +set_property PACKAGE_PIN L8 [get_ports lcd_wr] +set_property PACKAGE_PIN K8 [get_ports lcd_rd] +set_property PACKAGE_PIN J15 [get_ports lcd_bl_ctr] +set_property PACKAGE_PIN H9 [get_ports {lcd_data_io[0]}] +set_property PACKAGE_PIN K17 [get_ports {lcd_data_io[1]}] +set_property PACKAGE_PIN J20 [get_ports {lcd_data_io[2]}] +set_property PACKAGE_PIN M17 [get_ports {lcd_data_io[3]}] +set_property PACKAGE_PIN L17 [get_ports {lcd_data_io[4]}] +set_property PACKAGE_PIN L18 [get_ports {lcd_data_io[5]}] +set_property PACKAGE_PIN L15 [get_ports {lcd_data_io[6]}] +set_property PACKAGE_PIN M15 [get_ports {lcd_data_io[7]}] +set_property PACKAGE_PIN M16 [get_ports {lcd_data_io[8]}] +set_property PACKAGE_PIN L14 [get_ports {lcd_data_io[9]}] +set_property PACKAGE_PIN M14 [get_ports {lcd_data_io[10]}] +set_property PACKAGE_PIN F22 [get_ports {lcd_data_io[11]}] +set_property PACKAGE_PIN G22 [get_ports {lcd_data_io[12]}] +set_property PACKAGE_PIN G21 [get_ports {lcd_data_io[13]}] +set_property PACKAGE_PIN H24 [get_ports {lcd_data_io[14]}] +set_property PACKAGE_PIN J16 [get_ports {lcd_data_io[15]}] +set_property PACKAGE_PIN L19 [get_ports ct_int] +set_property PACKAGE_PIN J24 [get_ports ct_sda] +set_property PACKAGE_PIN H21 [get_ports ct_scl] +set_property PACKAGE_PIN G24 [get_ports ct_rstn] + +set_property IOSTANDARD LVCMOS33 [get_ports lcd_rst] +set_property IOSTANDARD LVCMOS33 [get_ports lcd_cs] +set_property IOSTANDARD LVCMOS33 [get_ports lcd_rs] +set_property IOSTANDARD LVCMOS33 [get_ports lcd_wr] +set_property IOSTANDARD LVCMOS33 [get_ports lcd_rd] +set_property IOSTANDARD LVCMOS33 [get_ports lcd_bl_ctr] +set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[8]}] +set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[9]}] +set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[10]}] +set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[11]}] +set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[12]}] +set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[13]}] +set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[14]}] +set_property IOSTANDARD LVCMOS33 [get_ports {lcd_data_io[15]}] +set_property IOSTANDARD LVCMOS33 [get_ports ct_int] +set_property IOSTANDARD LVCMOS33 [get_ports ct_sda] +set_property IOSTANDARD LVCMOS33 [get_ports ct_scl] +set_property IOSTANDARD LVCMOS33 [get_ports ct_rstn] + +set_property PACKAGE_PIN V8 [get_ports {key_col[0]}] +set_property PACKAGE_PIN V9 [get_ports {key_col[1]}] +set_property PACKAGE_PIN Y8 [get_ports {key_col[2]}] +set_property PACKAGE_PIN V7 [get_ports {key_col[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {key_col[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {key_col[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {key_col[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {key_col[0]}] +set_property PACKAGE_PIN U7 [get_ports {key_row[0]}] +set_property PACKAGE_PIN W8 [get_ports {key_row[1]}] +set_property PACKAGE_PIN Y7 [get_ports {key_row[2]}] +set_property PACKAGE_PIN AA8 [get_ports {key_row[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {key_row[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {key_row[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {key_row[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {key_row[0]}] +set_property PACKAGE_PIN AA7 [get_ports {sw[6]}] +set_property PACKAGE_PIN Y6 [get_ports {sw[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] + +set_property PACKAGE_PIN V6 [get_ports btn_ledgr] +set_property IOSTANDARD LVCMOS33 [get_ports btn_ledgr] +set_property PACKAGE_PIN AC21 [get_ports {sw[0]}] +set_property PACKAGE_PIN AD24 [get_ports {sw[1]}] +set_property PACKAGE_PIN AC22 [get_ports {sw[2]}] +set_property PACKAGE_PIN AC23 [get_ports {sw[3]}] +set_property PACKAGE_PIN AB6 [get_ports {sw[4]}] +set_property PACKAGE_PIN W6 [get_ports {sw[5]}] + +set_property PACKAGE_PIN H7 [get_ports {led[0]}] +set_property PACKAGE_PIN D5 [get_ports {led[1]}] +set_property PACKAGE_PIN A3 [get_ports {led[2]}] +set_property PACKAGE_PIN A5 [get_ports {led[3]}] +set_property PACKAGE_PIN A4 [get_ports {led[4]}] +set_property PACKAGE_PIN F7 [get_ports {led[5]}] +set_property PACKAGE_PIN G8 [get_ports {led[6]}] +set_property PACKAGE_PIN H8 [get_ports {led[7]}] +set_property PACKAGE_PIN J8 [get_ports {led[8]}] +set_property PACKAGE_PIN J23 [get_ports {led[9]}] +set_property PACKAGE_PIN J26 [get_ports {led[10]}] +set_property PACKAGE_PIN G9 [get_ports {led[11]}] +set_property PACKAGE_PIN J19 [get_ports {led[12]}] +set_property PACKAGE_PIN H23 [get_ports {led[13]}] +set_property PACKAGE_PIN J21 [get_ports {led[14]}] +set_property PACKAGE_PIN K23 [get_ports {led[15]}] + +set_property PACKAGE_PIN G7 [get_ports {ledr[0]}] +set_property PACKAGE_PIN F8 [get_ports {ledg[0]}] +set_property PACKAGE_PIN B5 [get_ports {ledr[1]}] +set_property PACKAGE_PIN D6 [get_ports {ledg[1]}] + +set_property PACKAGE_PIN D3 [get_ports {num_csn[0]}] +set_property PACKAGE_PIN D25 [get_ports {num_csn[1]}] +set_property PACKAGE_PIN D26 [get_ports {num_csn[2]}] +set_property PACKAGE_PIN E25 [get_ports {num_csn[3]}] +set_property PACKAGE_PIN E26 [get_ports {num_csn[4]}] +set_property PACKAGE_PIN G25 [get_ports {num_csn[5]}] +set_property PACKAGE_PIN G26 [get_ports {num_csn[6]}] +set_property PACKAGE_PIN H26 [get_ports {num_csn[7]}] + +set_property PACKAGE_PIN A2 [get_ports num_a] +set_property PACKAGE_PIN D4 [get_ports num_b] +set_property PACKAGE_PIN E5 [get_ports num_c] +set_property PACKAGE_PIN B4 [get_ports num_d] +set_property PACKAGE_PIN B2 [get_ports num_e] +set_property PACKAGE_PIN E6 [get_ports num_f] +set_property PACKAGE_PIN C3 [get_ports num_g] +set_property PACKAGE_PIN C4 [get_ports num_dp] + +set_property PACKAGE_PIN F3 [get_ports {dot_r[1]}] +set_property PACKAGE_PIN F4 [get_ports {dot_r[2]}] +set_property PACKAGE_PIN C2 [get_ports {dot_r[3]}] +set_property PACKAGE_PIN F5 [get_ports {dot_r[4]}] +set_property PACKAGE_PIN H3 [get_ports {dot_r[5]}] +set_property PACKAGE_PIN B1 [get_ports {dot_r[6]}] +set_property PACKAGE_PIN G4 [get_ports {dot_r[7]}] +set_property PACKAGE_PIN J5 [get_ports {dot_r[8]}] + +set_property PACKAGE_PIN G6 [get_ports {dot_c[1]}] +set_property PACKAGE_PIN G5 [get_ports {dot_c[2]}] +set_property PACKAGE_PIN H6 [get_ports {dot_c[3]}] +set_property PACKAGE_PIN J4 [get_ports {dot_c[4]}] +set_property PACKAGE_PIN J6 [get_ports {dot_c[5]}] +set_property PACKAGE_PIN E3 [get_ports {dot_c[6]}] +set_property PACKAGE_PIN C1 [get_ports {dot_c[7]}] +set_property PACKAGE_PIN H4 [get_ports {dot_c[8]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {dot_c[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {dot_c[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {dot_c[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {dot_c[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {dot_c[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {dot_c[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {dot_c[8]}] +set_property IOSTANDARD LVCMOS33 [get_ports {dot_c[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {dot_r[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {dot_r[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {dot_r[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {dot_r[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {dot_r[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {dot_r[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {dot_r[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {dot_r[8]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {ledg[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {ledg[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {ledr[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {ledr[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {num_csn[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {num_csn[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {num_csn[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {num_csn[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {num_csn[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {num_csn[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {num_csn[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {num_csn[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports num_a] +set_property IOSTANDARD LVCMOS33 [get_ports num_c] +set_property IOSTANDARD LVCMOS33 [get_ports num_b] +set_property IOSTANDARD LVCMOS33 [get_ports num_d] +set_property IOSTANDARD LVCMOS33 [get_ports num_dp] +set_property IOSTANDARD LVCMOS33 [get_ports num_e] +set_property IOSTANDARD LVCMOS33 [get_ports num_f] +set_property IOSTANDARD LVCMOS33 [get_ports num_g] \ No newline at end of file diff --git a/fpga/script.tcl b/fpga/script.tcl new file mode 100644 index 0000000..647dad7 --- /dev/null +++ b/fpga/script.tcl @@ -0,0 +1,24 @@ +# TODO: test whether it works +set outputDir ./vivado + +# Add Source +read_verilog -sv [ glob ./src/**/*.sv ] +read_verilog -sv [ glob ../src/**/*.sv ] +read_checkpoint ./src/lcd_module.dcp +read_ip [ glob ./ip/*.xci ] +read_xdc ./constraints.xdc + +# Run +synth_design -top [lindex [find_top] 0] -part xc7a200tfbg676-2 +opt_design +place_design +phys_opt_design +route_design + +# Report +report_timing_summary -file $outputDir/post_route_timing_summary.rpt +report_timing -sort_by group -max_paths 100 -path_type summary -file $outputDir/post_route_timing.rpt +report_utilization -file $outputDir/post_route_util.rpt + +# Bitstream +write_bitstream $outputDir/awesome.bit diff --git a/fpga/src/fpga.sv b/fpga/src/fpga.sv new file mode 100644 index 0000000..0869f6a --- /dev/null +++ b/fpga/src/fpga.sv @@ -0,0 +1,45 @@ +// Design Top Copied from FPGA_green_test +module fpga_test ( + input clk, + input resetn, + input btn_clk, + + input btn_ledgr, + + input [7:0] sw, + + output [15:0] led, + output [ 1:0] ledr, + output [ 1:0] ledg, + + output [7:0] num_csn, + output num_a, + output num_b, + output num_c, + output num_d, + output num_e, + output num_f, + output num_g, + output num_dp, + + output [3:0] key_col, + input [3:0] key_row, + + output [8:1] dot_r, + output [8:1] dot_c, + + //触摸屏相关接口，不需要更改 + output lcd_rst, + output lcd_cs, + output lcd_rs, + output lcd_wr, + output lcd_rd, + inout [15:0] lcd_data_io, + output lcd_bl_ctr, + inout ct_int, + inout ct_sda, + output ct_scl, + output ct_rstn +); + +endmodule diff --git a/fpga/src/lcd_module.dcp b/fpga/src/lcd_module.dcp new file mode 100644 index 0000000..b60aed8 Binary files /dev/null and b/fpga/src/lcd_module.dcp differ