From b4760f89fdc761081ae79f34ed38bf5adfd0fc57 Mon Sep 17 00:00:00 2001
From: cxy004 <cxy004@qq.com>
Date: Mon, 2 Aug 2021 17:16:34 +0800
Subject: [PATCH] HLS fix

---
 src/Core/Controller.sv  |  2 +-
 src/Core/Datapath.sv    | 12 ++++++------
 src/include/defines.svh | 10 +++++-----
 3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/Core/Controller.sv b/src/Core/Controller.sv
index 5659b6c..d6f52af 100644
--- a/src/Core/Controller.sv
+++ b/src/Core/Controller.sv
@@ -62,7 +62,7 @@ module Controller (
 
   assign ctrl.MCtrl0.HW  = ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[4] & (inst[3] | ~inst[1] & inst[0]);
   assign ctrl.MCtrl0.LW  = ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[4] & (inst[3] | inst[1] & inst[0]);
-  assign ctrl.MCtrl0.HLS = HLS_t'({inst[30] | inst[29] | inst[28] | inst[27] | inst[26] | inst[4] & ~inst[3], inst[1:0]});
+  assign ctrl.MCtrl0.HLS = HLS_t'({~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & (~inst[4] | inst[3]), inst[1:0]});
   assign ctrl.MCtrl0.C0D = inst[15:11];
   assign ctrl.MCtrl0.C0W = inst[30] & inst[23];
   assign ctrl.MCtrl0.RS0 = RS0_t'({inst[29] | inst[26] | ~inst[4], inst[30] | ~inst[29] & ~inst[26] & inst[4] & ~inst[1]});
diff --git a/src/Core/Datapath.sv b/src/Core/Datapath.sv
index 3e28fd3..1ac549b 100644
--- a/src/Core/Datapath.sv
+++ b/src/Core/Datapath.sv
@@ -426,7 +426,7 @@ module Datapath (
                          | E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & D.IB.ET & E.I1.MCtrl.MR
                          | D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ES
                          | D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ET
-                         | D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & ~D.IB.DP1 & (D.IB.MCtrl0.HW ^ D.IB.MCtrl0.LW) & ~D.IA.DP0
+                         | D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & ~D.IB.DP1 & D.IB.MCtrl0.HLS[2] & ~D.IA.DP0
                          | D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & ~D.IB.DP1 & D.IB.MCtrl0.C0W & ~D.IA.DP0;
 
   assign D.A = (D.IA.DP0 & D.IA.DP1 | D.IA_ExcValid) ? D.IB.DP0 : D.IA.DP1;
@@ -882,7 +882,7 @@ module Datapath (
   ffenr #(6) M_I0_MULT_CNTR_ff (
       clk,
       rst | rstM,
-      {E.I0.MCtrl.HLS[2:1] == 2'b00 & E_go & E_I0_go & M.en, M_I0_MULT_CNTR[5:1]},
+      {E.I0.MCtrl.HLS[2:1] == 2'b10 & E_go & E_I0_go & M.en, M_I0_MULT_CNTR[5:1]},
       1'b1,
       M_I0_MULT_CNTR
   );
@@ -982,7 +982,7 @@ module Datapath (
       {M_I0_DIVHB,    M_I0_DIVLB},
       {M_I0_DIVUHB,   M_I0_DIVULB},
       {M_I0_ForwardS, M_I0_ForwardS},
-      M.I0.MCtrl.HLS,
+      {~M.I0.MCtrl.HLS[2], M.I0.MCtrl.HLS[1:0]},
       {M_I0_HI,       M_I0_LO}
   );
   ffen #(32) HI_ff (
@@ -1051,9 +1051,9 @@ module Datapath (
   );
 
   assign M.en = M_go & W.en;
-  assign M_go = (M.I0.MCtrl.HLS != DIV  | M_I0_DIV_bvalid)
-              & (M.I0.MCtrl.HLS != DIVU | M_I0_DIVU_bvalid)
-              & (M.I0.MCtrl.HLS[2:1] != 2'b00 | M_I0_MULT_bvalid)
+  assign M_go = (M.I0.MCtrl.HLS[2:1] != 2'b10 | M_I0_MULT_bvalid)
+              & (M.I0.MCtrl.HLS      != DIV   | M_I0_DIV_bvalid)
+              & (M.I0.MCtrl.HLS      != DIVU  | M_I0_DIVU_bvalid)
               & (~M.I1.MCtrl.MR | M_I1_DataR_OK)
               & (~M_exception.ExcValid | fetch_i.req & fetch_i.addr_ok);
 
diff --git a/src/include/defines.svh b/src/include/defines.svh
index 9eb440f..6f9dcf8 100644
--- a/src/include/defines.svh
+++ b/src/include/defines.svh
@@ -66,11 +66,11 @@ typedef enum logic [1:0] {
 } RS0_t;
 
 typedef enum logic [2:0] {
-  MULT  = 3'b000,
-  MULTU = 3'b001,
-  DIV   = 3'b010,
-  DIVU  = 3'b011,
-  HLRS  = 3'b100   // 3'b1??
+  HLRS  = 3'b000,   // 3'b0??
+  MULT  = 3'b100,
+  MULTU = 3'b101,
+  DIV   = 3'b110,
+  DIVU  = 3'b111
 } HLS_t;
 
 typedef struct packed {