Merge branch 'soc_top'
This commit is contained in:
commit
b3238b0f86
@ -15,8 +15,3 @@ indent_style = tab
|
||||
charset = utf-8
|
||||
indent_style = tab
|
||||
indent_size = 8
|
||||
|
||||
[resources/project/include/*.h]
|
||||
charset = utf-8
|
||||
indent_style = tab
|
||||
indent_size = 8
|
||||
|
||||
3
.gitignore
vendored
3
.gitignore
vendored
@ -1,2 +1,5 @@
|
||||
vivado.log
|
||||
vivado.jou
|
||||
.library_mapping.xml
|
||||
.project
|
||||
.settings
|
||||
17
.vscode/c_cpp_properties.json
vendored
17
.vscode/c_cpp_properties.json
vendored
@ -1,17 +0,0 @@
|
||||
{
|
||||
"configurations": [
|
||||
{
|
||||
"name": "Linux",
|
||||
"includePath": [
|
||||
"${workspaceFolder}/**",
|
||||
"/usr/share/verilator/include"
|
||||
],
|
||||
"defines": [],
|
||||
"compilerPath": "/usr/sbin/clang",
|
||||
"cStandard": "c17",
|
||||
"cppStandard": "c++14",
|
||||
"intelliSenseMode": "linux-clang-x64"
|
||||
}
|
||||
],
|
||||
"version": 4
|
||||
}
|
||||
67
.vscode/settings.json
vendored
67
.vscode/settings.json
vendored
@ -1,67 +0,0 @@
|
||||
{
|
||||
"files.associations": {
|
||||
"cctype": "cpp",
|
||||
"clocale": "cpp",
|
||||
"cmath": "cpp",
|
||||
"cstdarg": "cpp",
|
||||
"cstddef": "cpp",
|
||||
"cstdio": "cpp",
|
||||
"cstdlib": "cpp",
|
||||
"cstring": "cpp",
|
||||
"ctime": "cpp",
|
||||
"cwchar": "cpp",
|
||||
"cwctype": "cpp",
|
||||
"array": "cpp",
|
||||
"atomic": "cpp",
|
||||
"bit": "cpp",
|
||||
"*.tcc": "cpp",
|
||||
"bitset": "cpp",
|
||||
"chrono": "cpp",
|
||||
"compare": "cpp",
|
||||
"concepts": "cpp",
|
||||
"condition_variable": "cpp",
|
||||
"cstdint": "cpp",
|
||||
"deque": "cpp",
|
||||
"list": "cpp",
|
||||
"map": "cpp",
|
||||
"set": "cpp",
|
||||
"string": "cpp",
|
||||
"unordered_map": "cpp",
|
||||
"unordered_set": "cpp",
|
||||
"vector": "cpp",
|
||||
"exception": "cpp",
|
||||
"algorithm": "cpp",
|
||||
"functional": "cpp",
|
||||
"iterator": "cpp",
|
||||
"memory": "cpp",
|
||||
"memory_resource": "cpp",
|
||||
"numeric": "cpp",
|
||||
"random": "cpp",
|
||||
"ratio": "cpp",
|
||||
"string_view": "cpp",
|
||||
"system_error": "cpp",
|
||||
"tuple": "cpp",
|
||||
"type_traits": "cpp",
|
||||
"utility": "cpp",
|
||||
"fstream": "cpp",
|
||||
"initializer_list": "cpp",
|
||||
"iosfwd": "cpp",
|
||||
"iostream": "cpp",
|
||||
"istream": "cpp",
|
||||
"limits": "cpp",
|
||||
"mutex": "cpp",
|
||||
"new": "cpp",
|
||||
"numbers": "cpp",
|
||||
"ostream": "cpp",
|
||||
"semaphore": "cpp",
|
||||
"sstream": "cpp",
|
||||
"stdexcept": "cpp",
|
||||
"stop_token": "cpp",
|
||||
"streambuf": "cpp",
|
||||
"thread": "cpp",
|
||||
"cinttypes": "cpp",
|
||||
"typeinfo": "cpp",
|
||||
"iomanip": "cpp"
|
||||
},
|
||||
"editor.defaultFormatter": "bmpenuelas.systemverilog-formatter-vscode"
|
||||
}
|
||||
22
README.md
22
README.md
@ -1,28 +1,22 @@
|
||||
Magically Improved Pipeline Stages
|
||||
===
|
||||
|
||||
Our awesome `MIPS` CPU written in `SystemVerilog` for Loongson Cup
|
||||
Our awesome `MIPS` CPU written in `SystemVerilog` for Loongson Cup 2021
|
||||
|
||||
```
|
||||
.
|
||||
├── resources <-- 资源包
|
||||
│ └── 2021 <-- 2021年资源包
|
||||
│ ├── cpu132_gettrace <-- 性能测试基准(gs132)
|
||||
│ ├── soc_axi_func <-- AXI功能测试
|
||||
│ ├── soc_axi_perf <-- AXI性能测试
|
||||
│ ├── soc_axi_system <-- AXI系统测试
|
||||
│ └── soft <-- 测试用程序
|
||||
│ ├── func <-- 功能测试
|
||||
│ ├── memory_game <-- 记忆游戏
|
||||
│ └── perf_func <-- 性能测试
|
||||
├── resources <-- 资源
|
||||
│ ├── 2021 <-- 2021 资源包
|
||||
│ ├── ping-pong-mips32 <-- 决赛项目 ping pong
|
||||
│ └── system_top <-- 决赛项目 ping pong 用的外围顶层
|
||||
├── src <-- CPU设计代码
|
||||
│ ├── AXI <-- AXI总线交互
|
||||
│ ├── Cache <-- Cache
|
||||
│ ├── Core <-- CPU核心
|
||||
│ ├── CP0 <-- CP0 协处理器
|
||||
│ ├── Gadgets <-- 小部件
|
||||
│ ├── include <-- 头文件
|
||||
│ ├── IP <-- 用到的IP
|
||||
│ ├── MMU <-- 地址转换单元
|
||||
│ └── testbench <-- 测试脚本
|
||||
└── tools <-- controller生成器
|
||||
│ └── MMU <-- 地址转换单元
|
||||
└── tools <-- 控制信号生成器
|
||||
```
|
||||
|
||||
@ -3,7 +3,8 @@
|
||||
`define SIMULATION_PC
|
||||
`define TRACE_REF_FILE "../../../../../../../cpu132_gettrace/golden_trace.txt"
|
||||
`define CONFREG_NUM_REG soc_lite.u_confreg.num_data
|
||||
`define CONFREG_OPEN_TRACE soc_lite.u_confreg.open_trace
|
||||
//`define CONFREG_OPEN_TRACE soc_lite.u_confreg.open_trace
|
||||
`define CONFREG_OPEN_TRACE 1'b0
|
||||
`define CONFREG_NUM_MONITOR soc_lite.u_confreg.num_monitor
|
||||
`define CONFREG_UART_DISPLAY soc_lite.u_confreg.write_uart_valid
|
||||
`define CONFREG_UART_DATA soc_lite.u_confreg.write_uart_data
|
||||
@ -43,7 +44,7 @@ module tb2_top ();
|
||||
end
|
||||
end
|
||||
|
||||
soc_axi_lite_top2 #(
|
||||
soc_axi_lite_top #(
|
||||
.SIMULATION(1'b1)
|
||||
) soc_lite (
|
||||
.resetn(resetn),
|
||||
@ -84,11 +85,11 @@ module tb2_top ();
|
||||
assign debug_wb_rf_wen = soc_lite.debug_wb_rf_wen;
|
||||
assign debug_wb_rf_wnum = soc_lite.debug_wb_rf_wnum;
|
||||
assign debug_wb_rf_wdata = soc_lite.debug_wb_rf_wdata;
|
||||
assign debug_wb1_pc = soc_lite.debug_wb1_pc;
|
||||
assign debug_wb1_rf_wen = soc_lite.debug_wb1_rf_wen;
|
||||
assign debug_wb1_rf_wnum = soc_lite.debug_wb1_rf_wnum;
|
||||
assign debug_wb1_rf_wdata = soc_lite.debug_wb1_rf_wdata;
|
||||
assign debug_wb_pc_A = soc_lite.debug_wb_pc_A;
|
||||
assign debug_wb1_pc = soc_lite.u_cpu.debug_wb1_pc;
|
||||
assign debug_wb1_rf_wen = soc_lite.u_cpu.debug_wb1_rf_wen;
|
||||
assign debug_wb1_rf_wnum = soc_lite.u_cpu.debug_wb1_rf_wnum;
|
||||
assign debug_wb1_rf_wdata = soc_lite.u_cpu.debug_wb1_rf_wdata;
|
||||
assign debug_wb_pc_A = soc_lite.u_cpu.debug_wb_pc_A;
|
||||
|
||||
// open the trace file;
|
||||
integer trace_ref;
|
||||
@ -145,7 +146,7 @@ module tb2_top ();
|
||||
#2;
|
||||
if (!resetn) begin
|
||||
debug_wb_err <= 1'b0;
|
||||
end else if (!debug_end && `CONFREG_OPEN_TRACE) begin
|
||||
end else if (!debug_end) begin
|
||||
if (debug_wb_pc_A) begin
|
||||
dbg_0_rf_wen <= debug_wb1_rf_wen;
|
||||
dbg_0_pc <= debug_wb1_pc;
|
||||
@ -168,16 +169,16 @@ module tb2_top ();
|
||||
dbg_0_rf_wdata <= debug_wb_rf_wdata;
|
||||
end
|
||||
|
||||
if (|dbg_0_rf_wen) begin
|
||||
if (|dbg_0_rf_wen && `CONFREG_OPEN_TRACE) begin
|
||||
$display("mycpu0 : PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h, wen= %d",
|
||||
dbg_0_pc, dbg_0_rf_wnum, dbg_0_rf_wdata, |dbg_0_rf_wen);
|
||||
end
|
||||
if (|dbg_1_rf_wen) begin
|
||||
if (|dbg_1_rf_wen && `CONFREG_OPEN_TRACE) begin
|
||||
$display("mycpu1 : PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h, wen= %d",
|
||||
dbg_1_pc, dbg_1_rf_wnum, dbg_1_rf_wdata, |dbg_1_rf_wen);
|
||||
end
|
||||
|
||||
if (|dbg_0_rf_wen && dbg_0_rf_wnum != 5'd0) begin
|
||||
if (|dbg_0_rf_wen && dbg_0_rf_wnum != 5'd0 && `CONFREG_OPEN_TRACE) begin
|
||||
if ( (dbg_0_pc !== ref_trace[0].ref_wb_pc )
|
||||
|| (dbg_0_rf_wnum !== ref_trace[0].ref_wb_rf_wnum )
|
||||
|| (dbg_0_rf_wdata !== ref_trace[0].ref_wb_rf_wdata)
|
||||
@ -198,7 +199,7 @@ module tb2_top ();
|
||||
$finish;
|
||||
end else ref_trace.pop_front();
|
||||
end
|
||||
if (|dbg_1_rf_wen && dbg_1_rf_wnum != 5'd0) begin
|
||||
if (|dbg_1_rf_wen && dbg_1_rf_wnum != 5'd0 && `CONFREG_OPEN_TRACE) begin
|
||||
if ( (dbg_1_pc !== ref_trace[0].ref_wb_pc )
|
||||
|| (dbg_1_rf_wnum !== ref_trace[0].ref_wb_rf_wnum )
|
||||
|| (dbg_1_rf_wdata !== ref_trace[0].ref_wb_rf_wdata)
|
||||
@ -237,6 +238,7 @@ module tb2_top ();
|
||||
err_count, confreg_num_reg[31:24]);
|
||||
$display("--------------------------------------------------------------");
|
||||
err_count <= err_count + 1'b1;
|
||||
$finish;
|
||||
end else if (confreg_num_reg[31:24] != confreg_num_reg_r[31:24] + 1'b1) begin
|
||||
$display("--------------------------------------------------------------");
|
||||
$display("[%t] Error(%d)!!! Unknown, Functional Test Point numbers are unequal!", $time,
|
||||
@ -244,6 +246,7 @@ module tb2_top ();
|
||||
$display("--------------------------------------------------------------");
|
||||
$display("==============================================================");
|
||||
err_count <= err_count + 1'b1;
|
||||
$finish;
|
||||
end else begin
|
||||
$display("----[%t] Number 8'd%02d Functional Test Point PASS!!!", $time,
|
||||
confreg_num_reg[31:24]);
|
||||
@ -266,7 +269,7 @@ module tb2_top ();
|
||||
end
|
||||
end
|
||||
|
||||
//妯℃嫙涓插彛鎵撳嵃
|
||||
// Uart Display
|
||||
logic uart_display;
|
||||
logic [7:0] uart_data;
|
||||
assign uart_display = `CONFREG_UART_DISPLAY;
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
TOPDIR=$(shell pwd)
|
||||
|
||||
#export LD_PRELOAD =
|
||||
CFLAGS := -D_KERNEL -fno-builtin -mips1 -DMEMSTART=0x80000000 -DMEMSIZE=0x04000 -DCPU_COUNT_PER_US=1000 -I $(TOPDIR)/include
|
||||
CFLAGS := -D_KERNEL -fno-builtin -mips32r2 -DMEMSTART=0x80000000 -DMEMSIZE=0x04000 -DCPU_COUNT_PER_US=1000 -I $(TOPDIR)/include
|
||||
CFLAGS += -fno-reorder-blocks -fno-reorder-functions -msoft-float
|
||||
|
||||
OBJDIR = ./obj
|
||||
|
||||
@ -1,89 +0,0 @@
|
||||
n10_sltiu.S
|
||||
n11_sll.S
|
||||
n12_sw.S
|
||||
n13_j.S
|
||||
n14_jal.S
|
||||
n15_jr.S
|
||||
n16_beq_ds.S
|
||||
n17_bne_ds.S
|
||||
n18_j_ds.S
|
||||
n19_jal_ds.S
|
||||
n1_lui.S
|
||||
n20_jr_ds.S
|
||||
n21_add.S
|
||||
n22_addi.S
|
||||
n23_sub.S
|
||||
n24_subu.S
|
||||
n25_sltu.S
|
||||
n26_and.S
|
||||
n27_andi.S
|
||||
n28_nor.S
|
||||
n29_ori.S
|
||||
n2_addu.S
|
||||
n30_xor.S
|
||||
n31_xori.S
|
||||
n32_sllv.S
|
||||
n33_sra.S
|
||||
n34_srav.S
|
||||
n35_srl.S
|
||||
n36_srlv.S
|
||||
n37_bgez.S
|
||||
n38_bgtz.S
|
||||
n39_blez.S
|
||||
n3_addiu.S
|
||||
n40_bltz.S
|
||||
n41_bltzal.S
|
||||
n42_bgezal.S
|
||||
n43_jalr.S
|
||||
n44_div.S
|
||||
n45_divu.S
|
||||
n46_mult.S
|
||||
n47_multu.S
|
||||
n48_mfhi.S
|
||||
n49_mflo.S
|
||||
n4_beq.S
|
||||
n50_mthi.S
|
||||
n51_mtlo.S
|
||||
n52_bgez_ds.S
|
||||
n53_bgtz_ds.S
|
||||
n54_blez_ds.S
|
||||
n55_bltz_ds.S
|
||||
n56_bltzal_ds.S
|
||||
n57_bgezal_ds.S
|
||||
n58_jalr_ds.S
|
||||
n59_lb.S
|
||||
n5_bne.S
|
||||
n60_lbu.S
|
||||
n61_lh.S
|
||||
n62_lhu.S
|
||||
n63_sb.S
|
||||
n64_sh.S
|
||||
n65_syscall_ex.S
|
||||
n66_break_ex.S
|
||||
n67_add_ov_ex.S
|
||||
n68_addi_ov_ex.S
|
||||
n69_sub_ov_ex.S
|
||||
n6_lw.S
|
||||
n70_lw_adel_ex.S
|
||||
n71_lh_adel_ex.S
|
||||
n72_lhu_adel_ex.S
|
||||
n73_sw_ades_ex.S
|
||||
n74_sh_ades_ex.S
|
||||
n75_ft_adel_ex.S
|
||||
n76_ri_ex.S
|
||||
n77_soft_int_ex.S
|
||||
n78_beq_ds_ex.S
|
||||
n79_bne_ds_ex.S
|
||||
n7_or.S
|
||||
n80_bgez_ds_ex.S
|
||||
n81_bgtz_ds_ex.S
|
||||
n82_blez_ds_ex.S
|
||||
n83_bltz_ds_ex.S
|
||||
n84_bltzal_ds_ex.S
|
||||
n85_bgezal_ds_ex.S
|
||||
n86_j_ds_ex.S
|
||||
n87_jal_ds_ex.S
|
||||
n88_jr_ds_ex.S
|
||||
n89_jalr_ds_ex.S
|
||||
n8_slt.S
|
||||
n9_slti.S
|
||||
@ -1290,3 +1290,240 @@
|
||||
mtc0 v1, c0_cause; \
|
||||
1: b 1b; \
|
||||
nop
|
||||
|
||||
/*90*/
|
||||
#define TEST_LWL(data, base_addr, offset, offset_align, ref, confuse) \
|
||||
LI(t1, data); \
|
||||
LI(t0, base_addr); \
|
||||
LI(v1, ref); \
|
||||
LI(v0, confuse); \
|
||||
sw t1, offset_align(t0); \
|
||||
lwl v0, offset(t0); \
|
||||
bne v0, v1, inst_error; \
|
||||
nop
|
||||
|
||||
/*91*/
|
||||
#define TEST_LWR(data, base_addr, offset, offset_align, ref, confuse) \
|
||||
LI(t1, data); \
|
||||
LI(t0, base_addr); \
|
||||
LI(v1, ref); \
|
||||
LI(v0, confuse); \
|
||||
sw t1, offset_align(t0); \
|
||||
lwr v0, offset(t0); \
|
||||
bne v0, v1, inst_error; \
|
||||
nop
|
||||
|
||||
/*92*/
|
||||
#define TEST_SWL(data, base_addr, offset, offset_align, ref, confuse) \
|
||||
LI(t1, data); \
|
||||
LI(t0, base_addr); \
|
||||
LI(v0, confuse); \
|
||||
LI(v1, ref); \
|
||||
sw v0, offset_align(t0); \
|
||||
swl t1, offset(t0); \
|
||||
lw v0, offset_align(t0); \
|
||||
bne v0, v1, inst_error; \
|
||||
nop
|
||||
|
||||
/*93*/
|
||||
#define TEST_SWR(data, base_addr, offset, offset_align, ref, confuse) \
|
||||
LI(t1, data); \
|
||||
LI(t0, base_addr); \
|
||||
LI(v0, confuse); \
|
||||
LI(v1, ref); \
|
||||
sw v0, offset_align(t0); \
|
||||
swr t1, offset(t0); \
|
||||
lw v0, offset_align(t0); \
|
||||
bne v0, v1, inst_error; \
|
||||
nop
|
||||
|
||||
/*95*/
|
||||
#define TEST_MADD_HL(in_a, in_b, raw_hi, raw_lo, ref_hi, ref_lo) \
|
||||
li t0, in_a; \
|
||||
li t1, in_b; \
|
||||
li a0, raw_hi; \
|
||||
li a1, raw_lo; \
|
||||
mthi a0; \
|
||||
mtlo a1; \
|
||||
madd t0, t1; \
|
||||
mflo s5; \
|
||||
mfhi s6; \
|
||||
li v0, ref_lo; \
|
||||
li v1, ref_hi; \
|
||||
bne v0, s5, inst_error; \
|
||||
nop; \
|
||||
bne v1, s6, inst_error; \
|
||||
nop
|
||||
|
||||
#define TEST_MADD(in_a, in_b, ref_lo, ref_hi) \
|
||||
li t0, in_a; \
|
||||
li t1, in_b; \
|
||||
mthi zero; \
|
||||
mtlo zero; \
|
||||
madd t0, t1; \
|
||||
mflo s5; \
|
||||
mfhi s6; \
|
||||
li v0, ref_lo; \
|
||||
li v1, ref_hi; \
|
||||
bne v0, s5, inst_error; \
|
||||
nop; \
|
||||
bne v1, s6, inst_error; \
|
||||
nop
|
||||
|
||||
/*96*/
|
||||
#define TEST_MADDU_HL(in_a, in_b, raw_hi, raw_lo, ref_hi, ref_lo) \
|
||||
li t0, in_a; \
|
||||
li t1, in_b; \
|
||||
li a0, raw_hi; \
|
||||
li a1, raw_lo; \
|
||||
mthi a0; \
|
||||
mtlo a1; \
|
||||
maddu t0, t1; \
|
||||
mflo s5; \
|
||||
mfhi s6; \
|
||||
li v0, ref_lo; \
|
||||
li v1, ref_hi; \
|
||||
bne v0, s5, inst_error; \
|
||||
nop; \
|
||||
bne v1, s6, inst_error; \
|
||||
nop
|
||||
|
||||
#define TEST_MADDU(in_a, in_b, ref_lo, ref_hi) \
|
||||
li t0, in_a; \
|
||||
li t1, in_b; \
|
||||
mthi zero; \
|
||||
mtlo zero; \
|
||||
maddu t0, t1; \
|
||||
mflo s5; \
|
||||
mfhi s6; \
|
||||
li v0, ref_lo; \
|
||||
li v1, ref_hi; \
|
||||
bne v0, s5, inst_error; \
|
||||
nop; \
|
||||
bne v1, s6, inst_error; \
|
||||
nop
|
||||
|
||||
/*97*/
|
||||
#define TEST_MSUB_HL(in_a, in_b, raw_hi, raw_lo, ref_hi, ref_lo) \
|
||||
li t0, in_a; \
|
||||
li t1, in_b; \
|
||||
li a0, raw_hi; \
|
||||
li a1, raw_lo; \
|
||||
mthi a0; \
|
||||
mtlo a1; \
|
||||
msub t0, t1; \
|
||||
mflo s5; \
|
||||
mfhi s6; \
|
||||
li v0, ref_lo; \
|
||||
li v1, ref_hi; \
|
||||
bne v0, s5, inst_error; \
|
||||
nop; \
|
||||
bne v1, s6, inst_error; \
|
||||
nop
|
||||
|
||||
#define TEST_MSUBU_HL(in_a, in_b, raw_hi, raw_lo, ref_hi, ref_lo) \
|
||||
li t0, in_a; \
|
||||
li t1, in_b; \
|
||||
li a0, raw_hi; \
|
||||
li a1, raw_lo; \
|
||||
mthi a0; \
|
||||
mtlo a1; \
|
||||
msubu t0, t1; \
|
||||
mflo s5; \
|
||||
mfhi s6; \
|
||||
li v0, ref_lo; \
|
||||
li v1, ref_hi; \
|
||||
bne v0, s5, inst_error; \
|
||||
nop; \
|
||||
bne v1, s6, inst_error; \
|
||||
nop
|
||||
|
||||
/*CACHE instruction*/
|
||||
|
||||
// address and result stored in v0
|
||||
#define GET_ICACHE_INDEX \
|
||||
srl v0, v0, 5; \
|
||||
andi v0, v0, 0x3f; \
|
||||
nop
|
||||
|
||||
#define GET_DCACHE_INDEX \
|
||||
srl v0, v0, 4; \
|
||||
andi v0, v0, 0x7f; \
|
||||
nop
|
||||
|
||||
/*98*/
|
||||
/*
|
||||
* addr1 : uncached
|
||||
* addr2 : cached and mapped to addr1
|
||||
*/
|
||||
#define TEST_CACHE_DCACHE_HIT(addr1, addr2, offset, data1, data2) \
|
||||
LI(t0, addr1); \
|
||||
LI(t1, addr2); \
|
||||
LI(t2, data1); \
|
||||
LI(t3, data2); \
|
||||
/* prepare -> hit writeback invalidate */ \
|
||||
sw t2, offset(t1); \
|
||||
cache 21, offset(t1); \
|
||||
lw a0, offset(t0); \
|
||||
bne t2, a0, inst_error; \
|
||||
nop; \
|
||||
lw a0, offset(t1); \
|
||||
bne t2, a0, inst_error; \
|
||||
nop; \
|
||||
/* test hit invalidate */ \
|
||||
sw t3, offset(t1); \
|
||||
cache 17, offset(t1); \
|
||||
lw a0, offset(t0); \
|
||||
bne a0, t2, inst_error; \
|
||||
nop; \
|
||||
lw a0, offset(t1); \
|
||||
bne a0, t2, inst_error; \
|
||||
nop; \
|
||||
/* test hit writeback invalidate */ \
|
||||
sw t3, offset(t1); \
|
||||
cache 21, offset(t1); \
|
||||
lw a0, offset(t0); \
|
||||
bne a0, t3, inst_error; \
|
||||
nop; \
|
||||
lw a0, offset(t1); \
|
||||
bne a0, t3, inst_error; \
|
||||
nop; \
|
||||
/* test multiple*/ \
|
||||
addi a1, t1, 4; \
|
||||
cache 17, offset(t1); \
|
||||
cache 17, offset(a1); \
|
||||
sw t2, offset(t1); \
|
||||
sw t3, offset(a1); \
|
||||
cache 21, offset(t1); \
|
||||
cache 21, offset(a1); \
|
||||
addi a1, t0, 4; \
|
||||
lw v0, offset(t0); \
|
||||
lw v1, offset(a1); \
|
||||
bne v0, t2, inst_error; \
|
||||
nop; \
|
||||
bne v1, t3, inst_error; \
|
||||
nop; \
|
||||
sw t3, offset(t0); \
|
||||
sw t2, offset(a1); \
|
||||
addi a1, t1, 4; \
|
||||
lw v0, offset(t1); \
|
||||
lw v1, offset(a1); \
|
||||
bne v0, t3, inst_error; \
|
||||
nop; \
|
||||
bne v1, t2, inst_error; \
|
||||
nop; \
|
||||
sw t2, offset(t1); \
|
||||
sw t3, offset(a1); \
|
||||
cache 17, offset(t1); \
|
||||
cache 17, offset(a1); \
|
||||
bne v0, t3, inst_error; \
|
||||
nop; \
|
||||
bne v1, t2, inst_error; \
|
||||
nop; \
|
||||
addi a1, t0, 4; \
|
||||
lw v0, offset(t0); \
|
||||
lw v1, offset(a1); \
|
||||
bne v0, t3, inst_error; \
|
||||
nop; \
|
||||
bne v1, t2, inst_error; \
|
||||
nop
|
||||
|
||||
51
resources/2021/soft/func/inst/n100_movz_movn.S
Normal file
51
resources/2021/soft/func/inst/n100_movz_movn.S
Normal file
@ -0,0 +1,51 @@
|
||||
#include <asm.h>
|
||||
#include <regdef.h>
|
||||
#include <inst_test.h>
|
||||
|
||||
LEAF(n100_movz_movn_test)
|
||||
.set noreorder
|
||||
addiu s0, s0 ,1
|
||||
li s2, 0x0
|
||||
###test inst
|
||||
li a0, 0xAAAAAAAA # RD
|
||||
li v0, 0xAAAAAAAA # RD REF
|
||||
li a1, 0x12345678 # RS
|
||||
li v1, 0 # RT
|
||||
|
||||
li v1, 0
|
||||
add a0, v0, zero
|
||||
movn a0, a1, v1
|
||||
bne a0, v0, inst_error
|
||||
nop
|
||||
|
||||
li v1, 1
|
||||
add a0, v0, zero
|
||||
movn a0, a1, v1
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
|
||||
li v1, 0
|
||||
add a0, v0, zero
|
||||
movz a0, a1, v1
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
|
||||
li v1, 1
|
||||
add a0, v0, zero
|
||||
movz a0, a1, v1
|
||||
bne a0, v0, inst_error
|
||||
nop
|
||||
|
||||
###detect exception
|
||||
bne s2, zero, inst_error
|
||||
nop
|
||||
###score ++
|
||||
addiu s3, s3, 1
|
||||
###output (s0<<24)|s3
|
||||
inst_error:
|
||||
sll t1, s0, 24
|
||||
or t0, t1, s3
|
||||
sw t0, 0(s1)
|
||||
jr ra
|
||||
nop
|
||||
END(n100_movz_movn_test)
|
||||
380
resources/2021/soft/func/inst/n101_trap.S
Normal file
380
resources/2021/soft/func/inst/n101_trap.S
Normal file
@ -0,0 +1,380 @@
|
||||
#include <asm.h>
|
||||
#include <regdef.h>
|
||||
#include <inst_test.h>
|
||||
|
||||
LEAF(n101_trap_test)
|
||||
.set noreorder
|
||||
addiu s0, s0, 1
|
||||
li t0, 0x800d0000
|
||||
li s2, 0x09
|
||||
sw s2, 0(t0) # Trap EX
|
||||
##clear cause.TI, status.EXL
|
||||
mtc0 zero, c0_compare
|
||||
lui s7,0x0040
|
||||
mtc0 s7, c0_status
|
||||
nop
|
||||
lui s7, 0x9 # Trap ex, ref return value.
|
||||
###test inst
|
||||
|
||||
###################################################
|
||||
# TEQ #
|
||||
###################################################
|
||||
|
||||
## 1
|
||||
la s4, trap_pc1
|
||||
li a0, -1
|
||||
li a1, 0
|
||||
addi a1, a1, -1
|
||||
trap_pc1:
|
||||
teq a0, a1
|
||||
bne s2, s7, inst_error
|
||||
nop
|
||||
|
||||
## 2 Load
|
||||
la s4, trap_pc2
|
||||
li a0, 0x9
|
||||
lw a1, 0(t0)
|
||||
trap_pc2:
|
||||
teq a0, a1
|
||||
bne s2, s7, inst_error
|
||||
nop
|
||||
|
||||
## 3 DIV Zero
|
||||
la s4, trap_pc3
|
||||
li a0, 1
|
||||
li a1, 0
|
||||
div zero, a0, a1
|
||||
trap_pc3:
|
||||
teq a1, zero
|
||||
bne s2, s7, inst_error
|
||||
nop
|
||||
|
||||
## 4 DIV
|
||||
la s4, trap_pc4
|
||||
li a0, 5
|
||||
li a1, 2
|
||||
div zero, a0, a1
|
||||
trap_pc4:
|
||||
teq zero, zero
|
||||
bne s2, s7, inst_error
|
||||
nop
|
||||
li a1, 1
|
||||
mfhi a0
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
li a1, 2
|
||||
mflo a0
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
|
||||
|
||||
###################################################
|
||||
# TEQI #
|
||||
###################################################
|
||||
|
||||
## 5
|
||||
la s4, trap_pc5
|
||||
li a0, -1
|
||||
trap_pc5:
|
||||
teqi a0, -1
|
||||
bne s2, s7, inst_error
|
||||
nop
|
||||
|
||||
## 6 Load
|
||||
la s4, trap_pc6
|
||||
lw a1, 0(t0)
|
||||
trap_pc6:
|
||||
teq a1, 0x9
|
||||
bne s2, s7, inst_error
|
||||
nop
|
||||
|
||||
## 7 DIV Zero
|
||||
la s4, trap_pc7
|
||||
li a0, 1
|
||||
li a1, 0
|
||||
div zero, a0, a1
|
||||
trap_pc7:
|
||||
teqi a1, 0
|
||||
bne s2, s7, inst_error
|
||||
nop
|
||||
|
||||
## 8 DIV
|
||||
la s4, trap_pc8
|
||||
li a0, 5
|
||||
li a1, 2
|
||||
div zero, a0, a1
|
||||
trap_pc8:
|
||||
teqi zero, 0
|
||||
bne s2, s7, inst_error
|
||||
nop
|
||||
li a1, 1
|
||||
mfhi a0
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
li a1, 2
|
||||
mflo a0
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
|
||||
###################################################
|
||||
# TGE #
|
||||
###################################################
|
||||
|
||||
## 9
|
||||
la s4, trap_pc9
|
||||
li a0, -1
|
||||
li a1, 1
|
||||
trap_pc9:
|
||||
tge a1, a0
|
||||
bne s2, s7, inst_error
|
||||
nop
|
||||
|
||||
## 10 Load
|
||||
la s4, trap_pc10
|
||||
li a0, 0x8
|
||||
lw a1, 0(t0)
|
||||
trap_pc10:
|
||||
tge a1, a0
|
||||
bne s2, s7, inst_error
|
||||
nop
|
||||
|
||||
## 11 DIV Zero
|
||||
la s4, trap_pc11
|
||||
li a0, 1
|
||||
li a1, 0
|
||||
div zero, a0, a1
|
||||
trap_pc11:
|
||||
tge a1, zero
|
||||
bne s2, s7, inst_error
|
||||
nop
|
||||
|
||||
## 12 DIV
|
||||
la s4, trap_pc12
|
||||
li a0, 5
|
||||
li a1, 2
|
||||
div zero, a0, a1
|
||||
trap_pc12:
|
||||
tge zero, zero
|
||||
bne s2, s7, inst_error
|
||||
nop
|
||||
li a1, 1
|
||||
mfhi a0
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
li a1, 2
|
||||
mflo a0
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
|
||||
###################################################
|
||||
# TGEI #
|
||||
###################################################
|
||||
|
||||
## 13
|
||||
la s4, trap_pc13
|
||||
li a0, -1
|
||||
trap_pc13:
|
||||
tgei a0, -2
|
||||
bne s2, s7, inst_error
|
||||
nop
|
||||
|
||||
## 14 Load
|
||||
la s4, trap_pc14
|
||||
lw a1, 0(t0)
|
||||
trap_pc14:
|
||||
tgei a1, 0x8
|
||||
bne s2, s7, inst_error
|
||||
nop
|
||||
|
||||
## 15 DIV Zero
|
||||
la s4, trap_pc15
|
||||
li a0, 1
|
||||
li a1, 0
|
||||
div zero, a0, a1
|
||||
trap_pc15:
|
||||
tgei a1, 0
|
||||
bne s2, s7, inst_error
|
||||
nop
|
||||
|
||||
## 16 DIV
|
||||
la s4, trap_pc16
|
||||
li a0, 5
|
||||
li a1, 2
|
||||
div zero, a0, a1
|
||||
trap_pc16:
|
||||
tgei zero, 0
|
||||
bne s2, s7, inst_error
|
||||
nop
|
||||
li a1, 1
|
||||
mfhi a0
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
li a1, 2
|
||||
mflo a0
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
|
||||
###################################################
|
||||
# TGEIU #
|
||||
###################################################
|
||||
|
||||
## 17
|
||||
la s4, trap_pc17
|
||||
li a0, -1
|
||||
trap_pc17:
|
||||
tgeiu a0, 0
|
||||
bne s2, s7, inst_error
|
||||
nop
|
||||
|
||||
###################################################
|
||||
# TGEU #
|
||||
###################################################
|
||||
|
||||
## 18
|
||||
la s4, trap_pc18
|
||||
li a0, -1
|
||||
li a1, 0
|
||||
trap_pc18:
|
||||
tgeu a0, a1
|
||||
bne s2, s7, inst_error
|
||||
nop
|
||||
|
||||
###################################################
|
||||
# TLT #
|
||||
###################################################
|
||||
|
||||
## 19
|
||||
la s4, trap_pc19
|
||||
li a0, -1
|
||||
li a1, 1
|
||||
trap_pc19:
|
||||
tlt a0, a1
|
||||
bne s2, s7, inst_error
|
||||
nop
|
||||
|
||||
## 20 Load
|
||||
la s4, trap_pc20
|
||||
li a0, 0x8
|
||||
lw a1, 0(t0)
|
||||
trap_pc20:
|
||||
tlt a0, a1
|
||||
bne s2, s7, inst_error
|
||||
nop
|
||||
|
||||
## 21 DIV
|
||||
la s4, trap_pc21
|
||||
li a0, 5
|
||||
li a1, 2
|
||||
div zero, a0, a1
|
||||
trap_pc21:
|
||||
tlt a1, a0
|
||||
bne s2, s7, inst_error
|
||||
nop
|
||||
li a1, 1
|
||||
mfhi a0
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
li a1, 2
|
||||
mflo a0
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
|
||||
###################################################
|
||||
# TLTI #
|
||||
###################################################
|
||||
|
||||
## 22
|
||||
la s4, trap_pc22
|
||||
li a0, -2
|
||||
trap_pc22:
|
||||
tlti a0, -1
|
||||
bne s2, s7, inst_error
|
||||
nop
|
||||
|
||||
## 23 Load
|
||||
la s4, trap_pc23
|
||||
lw a1, 0(t0)
|
||||
trap_pc23:
|
||||
tlti a1, 0x10
|
||||
bne s2, s7, inst_error
|
||||
nop
|
||||
|
||||
## 24 DIV
|
||||
la s4, trap_pc24
|
||||
li a0, 5
|
||||
li a1, 2
|
||||
div zero, a0, a1
|
||||
trap_pc24:
|
||||
tlti a1, 256
|
||||
bne s2, s7, inst_error
|
||||
nop
|
||||
li a1, 1
|
||||
mfhi a0
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
li a1, 2
|
||||
mflo a0
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
|
||||
###################################################
|
||||
# TLTIU #
|
||||
###################################################
|
||||
|
||||
## 25
|
||||
la s4, trap_pc25
|
||||
li a0, 1
|
||||
trap_pc25:
|
||||
tltiu a0, -1
|
||||
bne s2, s7, inst_error
|
||||
nop
|
||||
|
||||
###################################################
|
||||
# TLTU #
|
||||
###################################################
|
||||
|
||||
## 26
|
||||
la s4, trap_pc26
|
||||
li a0, 0
|
||||
li a1, -1
|
||||
trap_pc26:
|
||||
tltu a0, a1
|
||||
bne s2, s7, inst_error
|
||||
nop
|
||||
|
||||
###################################################
|
||||
# TNE #
|
||||
###################################################
|
||||
|
||||
## 27
|
||||
la s4, trap_pc27
|
||||
li a0, 0
|
||||
li a1, -1
|
||||
trap_pc27:
|
||||
tne a0, a1
|
||||
bne s2, s7, inst_error
|
||||
nop
|
||||
|
||||
###################################################
|
||||
# TNEI #
|
||||
###################################################
|
||||
|
||||
## 28
|
||||
la s4, trap_pc28
|
||||
li a1, -1
|
||||
trap_pc28:
|
||||
tnei a1, -2
|
||||
bne s2, s7, inst_error
|
||||
nop
|
||||
|
||||
|
||||
###score ++
|
||||
addiu s3, s3, 1
|
||||
###output (s0<<24)|s3
|
||||
inst_error:
|
||||
sll t1, s0, 24
|
||||
or t0, t1, s3
|
||||
sw t0, 0(s1)
|
||||
jr ra
|
||||
nop
|
||||
END(n101_trap_test)
|
||||
41
resources/2021/soft/func/inst/n90_lwl.S
Normal file
41
resources/2021/soft/func/inst/n90_lwl.S
Normal file
@ -0,0 +1,41 @@
|
||||
#include <asm.h>
|
||||
#include <regdef.h>
|
||||
#include <inst_test.h>
|
||||
|
||||
LEAF(n90_lwl_test)
|
||||
.set noreorder
|
||||
addiu s0, s0 ,1
|
||||
li s2, 0x0
|
||||
###test inst
|
||||
TEST_LWL(0xc822c7e8, 0x800d34c0, 0x000066a8, 0x000066a8, 0xE8B6C7D8, 0xA5B6C7D8)
|
||||
TEST_LWL(0xc822c7e8, 0x800d34c0, 0x000066a9, 0x000066a8, 0xC7E8C7D8, 0xA5B6C7D8)
|
||||
TEST_LWL(0xc822c7e8, 0x800d34c0, 0x000066aA, 0x000066a8, 0x22C7E8D8, 0xA5B6C7D8)
|
||||
TEST_LWL(0xc822c7e8, 0x800d34c0, 0x000066aB, 0x000066a8, 0xC822C7E8, 0xA5B6C7D8)
|
||||
|
||||
TEST_LWL(0x71737c10, 0x800df660, 0x000002e4, 0x000002e4, 0x10B6C7D8, 0xA5B6C7D8)
|
||||
TEST_LWL(0x71737c10, 0x800df660, 0x000002e5, 0x000002e4, 0x7C10C7D8, 0xA5B6C7D8)
|
||||
TEST_LWL(0x71737c10, 0x800df660, 0x000002e6, 0x000002e4, 0x737C10D8, 0xA5B6C7D8)
|
||||
TEST_LWL(0x71737c10, 0x800df660, 0x000002e7, 0x000002e4, 0x71737C10, 0xA5B6C7D8)
|
||||
|
||||
TEST_LWL(0x03682420, 0x800d24e4, 0x00001680, 0x00001680, 0x20B6C7D8, 0xA5B6C7D8)
|
||||
TEST_LWL(0x03682420, 0x800d24e4, 0x00001681, 0x00001680, 0x2420C7D8, 0xA5B6C7D8)
|
||||
TEST_LWL(0x03682420, 0x800d24e4, 0x00001682, 0x00001680, 0x682420D8, 0xA5B6C7D8)
|
||||
TEST_LWL(0x03682420, 0x800d24e4, 0x00001683, 0x00001680, 0x03682420, 0xA5B6C7D8)
|
||||
|
||||
TEST_LWL(0x6f59f5d3, 0x800dabdc, 0x000001b0, 0x000001b0, 0xd3B6C7D8, 0xA5B6C7D8)
|
||||
TEST_LWL(0x6f59f5d3, 0x800dabdc, 0x000001b1, 0x000001b0, 0xf5d3C7D8, 0xA5B6C7D8)
|
||||
TEST_LWL(0x6f59f5d3, 0x800dabdc, 0x000001b2, 0x000001b0, 0x59f5d3D8, 0xA5B6C7D8)
|
||||
TEST_LWL(0x6f59f5d3, 0x800dabdc, 0x000001b3, 0x000001b0, 0x6f59f5d3, 0xA5B6C7D8)
|
||||
###detect exception
|
||||
bne s2, zero, inst_error
|
||||
nop
|
||||
###score ++
|
||||
addiu s3, s3, 1
|
||||
###output (s0<<24)|s3
|
||||
inst_error:
|
||||
sll t1, s0, 24
|
||||
or t0, t1, s3
|
||||
sw t0, 0(s1)
|
||||
jr ra
|
||||
nop
|
||||
END(n90_lwl_test)
|
||||
41
resources/2021/soft/func/inst/n91_lwr.S
Normal file
41
resources/2021/soft/func/inst/n91_lwr.S
Normal file
@ -0,0 +1,41 @@
|
||||
#include <asm.h>
|
||||
#include <regdef.h>
|
||||
#include <inst_test.h>
|
||||
|
||||
LEAF(n91_lwr_test)
|
||||
.set noreorder
|
||||
addiu s0, s0 ,1
|
||||
li s2, 0x0
|
||||
###test inst
|
||||
TEST_LWR(0xc822c7e8, 0x800d34c0, 0x000066a8, 0x000066a8, 0xc822c7e8, 0xA5B6C7D8)
|
||||
TEST_LWR(0xc822c7e8, 0x800d34c0, 0x000066a9, 0x000066a8, 0xA5c822c7, 0xA5B6C7D8)
|
||||
TEST_LWR(0xc822c7e8, 0x800d34c0, 0x000066aA, 0x000066a8, 0xA5B6c822, 0xA5B6C7D8)
|
||||
TEST_LWR(0xc822c7e8, 0x800d34c0, 0x000066aB, 0x000066a8, 0xA5B6C7c8, 0xA5B6C7D8)
|
||||
|
||||
TEST_LWR(0x71737c10, 0x800df660, 0x000002e4, 0x000002e4, 0x71737c10, 0xA5B6C7D8)
|
||||
TEST_LWR(0x71737c10, 0x800df660, 0x000002e5, 0x000002e4, 0xA571737c, 0xA5B6C7D8)
|
||||
TEST_LWR(0x71737c10, 0x800df660, 0x000002e6, 0x000002e4, 0xA5B67173, 0xA5B6C7D8)
|
||||
TEST_LWR(0x71737c10, 0x800df660, 0x000002e7, 0x000002e4, 0xA5B6C771, 0xA5B6C7D8)
|
||||
|
||||
TEST_LWR(0x03682420, 0x800d24e4, 0x00001680, 0x00001680, 0x03682420, 0xA5B6C7D8)
|
||||
TEST_LWR(0x03682420, 0x800d24e4, 0x00001681, 0x00001680, 0xA5036824, 0xA5B6C7D8)
|
||||
TEST_LWR(0x03682420, 0x800d24e4, 0x00001682, 0x00001680, 0xA5B60368, 0xA5B6C7D8)
|
||||
TEST_LWR(0x03682420, 0x800d24e4, 0x00001683, 0x00001680, 0xA5B6C703, 0xA5B6C7D8)
|
||||
|
||||
TEST_LWR(0x6f59f5d3, 0x800dabdc, 0x000001b0, 0x000001b0, 0x6f59f5d3, 0xA5B6C7D8)
|
||||
TEST_LWR(0x6f59f5d3, 0x800dabdc, 0x000001b1, 0x000001b0, 0xA56f59f5, 0xA5B6C7D8)
|
||||
TEST_LWR(0x6f59f5d3, 0x800dabdc, 0x000001b2, 0x000001b0, 0xA5B66f59, 0xA5B6C7D8)
|
||||
TEST_LWR(0x6f59f5d3, 0x800dabdc, 0x000001b3, 0x000001b0, 0xA5B6C76f, 0xA5B6C7D8)
|
||||
###detect exception
|
||||
bne s2, zero, inst_error
|
||||
nop
|
||||
###score ++
|
||||
addiu s3, s3, 1
|
||||
###output (s0<<24)|s3
|
||||
inst_error:
|
||||
sll t1, s0, 24
|
||||
or t0, t1, s3
|
||||
sw t0, 0(s1)
|
||||
jr ra
|
||||
nop
|
||||
END(n91_lwr_test)
|
||||
41
resources/2021/soft/func/inst/n92_swl.S
Normal file
41
resources/2021/soft/func/inst/n92_swl.S
Normal file
@ -0,0 +1,41 @@
|
||||
#include <asm.h>
|
||||
#include <regdef.h>
|
||||
#include <inst_test.h>
|
||||
|
||||
LEAF(n92_swl_test)
|
||||
.set noreorder
|
||||
addiu s0, s0 ,1
|
||||
li s2, 0x0
|
||||
###test inst
|
||||
TEST_SWL(0xc822c7e8, 0x800d34c0, 0x000066a8, 0x000066a8, 0xA5B6C7c8, 0xA5B6C7D8)
|
||||
TEST_SWL(0xc822c7e8, 0x800d34c0, 0x000066a9, 0x000066a8, 0xA5B6c822, 0xA5B6C7D8)
|
||||
TEST_SWL(0xc822c7e8, 0x800d34c0, 0x000066aA, 0x000066a8, 0xA5c822c7, 0xA5B6C7D8)
|
||||
TEST_SWL(0xc822c7e8, 0x800d34c0, 0x000066aB, 0x000066a8, 0xc822c7e8, 0xA5B6C7D8)
|
||||
|
||||
TEST_SWL(0x71737c10, 0x800df660, 0x000002e4, 0x000002e4, 0xA5B6C771, 0xA5B6C7D8)
|
||||
TEST_SWL(0x71737c10, 0x800df660, 0x000002e5, 0x000002e4, 0xA5B67173, 0xA5B6C7D8)
|
||||
TEST_SWL(0x71737c10, 0x800df660, 0x000002e6, 0x000002e4, 0xA571737c, 0xA5B6C7D8)
|
||||
TEST_SWL(0x71737c10, 0x800df660, 0x000002e7, 0x000002e4, 0x71737c10, 0xA5B6C7D8)
|
||||
|
||||
TEST_SWL(0x03682420, 0x800d24e4, 0x00001680, 0x00001680, 0xA5B6C703, 0xA5B6C7D8)
|
||||
TEST_SWL(0x03682420, 0x800d24e4, 0x00001681, 0x00001680, 0xA5B60368, 0xA5B6C7D8)
|
||||
TEST_SWL(0x03682420, 0x800d24e4, 0x00001682, 0x00001680, 0xA5036824, 0xA5B6C7D8)
|
||||
TEST_SWL(0x03682420, 0x800d24e4, 0x00001683, 0x00001680, 0x03682420, 0xA5B6C7D8)
|
||||
|
||||
TEST_SWL(0x6f59f5d3, 0x800dabdc, 0x000001b0, 0x000001b0, 0xA5B6C76f, 0xA5B6C7D8)
|
||||
TEST_SWL(0x6f59f5d3, 0x800dabdc, 0x000001b1, 0x000001b0, 0xA5B66f59, 0xA5B6C7D8)
|
||||
TEST_SWL(0x6f59f5d3, 0x800dabdc, 0x000001b2, 0x000001b0, 0xA56f59f5, 0xA5B6C7D8)
|
||||
TEST_SWL(0x6f59f5d3, 0x800dabdc, 0x000001b3, 0x000001b0, 0x6f59f5d3, 0xA5B6C7D8)
|
||||
###detect exception
|
||||
bne s2, zero, inst_error
|
||||
nop
|
||||
###score ++
|
||||
addiu s3, s3, 1
|
||||
###output (s0<<24)|s3
|
||||
inst_error:
|
||||
sll t1, s0, 24
|
||||
or t0, t1, s3
|
||||
sw t0, 0(s1)
|
||||
jr ra
|
||||
nop
|
||||
END(n92_swl_test)
|
||||
41
resources/2021/soft/func/inst/n93_swr.S
Normal file
41
resources/2021/soft/func/inst/n93_swr.S
Normal file
@ -0,0 +1,41 @@
|
||||
#include <asm.h>
|
||||
#include <regdef.h>
|
||||
#include <inst_test.h>
|
||||
|
||||
LEAF(n93_swr_test)
|
||||
.set noreorder
|
||||
addiu s0, s0 ,1
|
||||
li s2, 0x0
|
||||
###test inst
|
||||
TEST_SWR(0xc822c7e8, 0x800d34c0, 0x000066a8, 0x000066a8, 0xc822c7e8, 0xA5B6C7D8)
|
||||
TEST_SWR(0xc822c7e8, 0x800d34c0, 0x000066a9, 0x000066a8, 0x22c7e8D8, 0xA5B6C7D8)
|
||||
TEST_SWR(0xc822c7e8, 0x800d34c0, 0x000066aA, 0x000066a8, 0xc7e8C7D8, 0xA5B6C7D8)
|
||||
TEST_SWR(0xc822c7e8, 0x800d34c0, 0x000066aB, 0x000066a8, 0xe8B6C7D8, 0xA5B6C7D8)
|
||||
|
||||
TEST_SWR(0x71737c10, 0x800df660, 0x000002e4, 0x000002e4, 0x71737c10, 0xA5B6C7D8)
|
||||
TEST_SWR(0x71737c10, 0x800df660, 0x000002e5, 0x000002e4, 0x737c10D8, 0xA5B6C7D8)
|
||||
TEST_SWR(0x71737c10, 0x800df660, 0x000002e6, 0x000002e4, 0x7c10C7D8, 0xA5B6C7D8)
|
||||
TEST_SWR(0x71737c10, 0x800df660, 0x000002e7, 0x000002e4, 0x10B6C7D8, 0xA5B6C7D8)
|
||||
|
||||
TEST_SWR(0x03682420, 0x800d24e4, 0x00001680, 0x00001680, 0x03682420, 0xA5B6C7D8)
|
||||
TEST_SWR(0x03682420, 0x800d24e4, 0x00001681, 0x00001680, 0x682420D8, 0xA5B6C7D8)
|
||||
TEST_SWR(0x03682420, 0x800d24e4, 0x00001682, 0x00001680, 0x2420C7D8, 0xA5B6C7D8)
|
||||
TEST_SWR(0x03682420, 0x800d24e4, 0x00001683, 0x00001680, 0x20B6C7D8, 0xA5B6C7D8)
|
||||
|
||||
TEST_SWR(0x6f59f5d3, 0x800dabdc, 0x000001b0, 0x000001b0, 0x6f59f5d3, 0xA5B6C7D8)
|
||||
TEST_SWR(0x6f59f5d3, 0x800dabdc, 0x000001b1, 0x000001b0, 0x59f5d3D8, 0xA5B6C7D8)
|
||||
TEST_SWR(0x6f59f5d3, 0x800dabdc, 0x000001b2, 0x000001b0, 0xf5d3C7D8, 0xA5B6C7D8)
|
||||
TEST_SWR(0x6f59f5d3, 0x800dabdc, 0x000001b3, 0x000001b0, 0xd3B6C7D8, 0xA5B6C7D8)
|
||||
###detect exception
|
||||
bne s2, zero, inst_error
|
||||
nop
|
||||
###score ++
|
||||
addiu s3, s3, 1
|
||||
###output (s0<<24)|s3
|
||||
inst_error:
|
||||
sll t1, s0, 24
|
||||
or t0, t1, s3
|
||||
sw t0, 0(s1)
|
||||
jr ra
|
||||
nop
|
||||
END(n93_swr_test)
|
||||
33
resources/2021/soft/func/inst/n94_perf_sync_as_nop.S
Normal file
33
resources/2021/soft/func/inst/n94_perf_sync_as_nop.S
Normal file
@ -0,0 +1,33 @@
|
||||
#include <asm.h>
|
||||
#include <regdef.h>
|
||||
#include <inst_test.h>
|
||||
|
||||
LEAF(n94_perf_sync_nop_test)
|
||||
.set noreorder
|
||||
addiu s0, s0 ,1
|
||||
li s2, 0x0
|
||||
###test inst
|
||||
addiu t0, zero, 0x12
|
||||
addiu t1, zero, 0x12
|
||||
addiu v0, zero, 0x34
|
||||
addiu v1, zero, 0x34
|
||||
.word 0xCD02F0F0
|
||||
.word 0x54F
|
||||
bne t0, t1, inst_error
|
||||
nop
|
||||
bne v0, v1, inst_error
|
||||
nop
|
||||
|
||||
###detect exception
|
||||
bne s2, zero, inst_error
|
||||
nop
|
||||
###score ++
|
||||
addiu s3, s3, 1
|
||||
###output (s0<<24)|s3
|
||||
inst_error:
|
||||
sll t1, s0, 24
|
||||
or t0, t1, s3
|
||||
sw t0, 0(s1)
|
||||
jr ra
|
||||
nop
|
||||
END(n94_perf_sync_nop_test)
|
||||
284
resources/2021/soft/func/inst/n95_madd.S
Normal file
284
resources/2021/soft/func/inst/n95_madd.S
Normal file
@ -0,0 +1,284 @@
|
||||
#include <asm.h>
|
||||
#include <regdef.h>
|
||||
#include <inst_test.h>
|
||||
|
||||
LEAF(n95_madd_test)
|
||||
.set noreorder
|
||||
addiu s0, s0 ,1
|
||||
li s2, 0x0
|
||||
###test inst
|
||||
TEST_MADD(0x45b90738, 0xd70d64f0, 0x0a20a480, 0xf4d903bb)
|
||||
TEST_MADD(0x99a451b0, 0xbe3d9998, 0x8552b080, 0x1a4b01ae)
|
||||
TEST_MADD(0x85931c58, 0xfb710fb5, 0xda843238, 0x022e0ede)
|
||||
TEST_MADD(0x650e4043, 0x64c17218, 0x7076dc48, 0x27c5ede2)
|
||||
TEST_MADD(0xa00c6c50, 0x8e9df080, 0x78d12800, 0x2a7f453e)
|
||||
TEST_MADD(0x99c874b6, 0xd7ce83e0, 0xe7934140, 0x100c6ff4)
|
||||
TEST_MADD(0x1c62f360, 0x34580400, 0xb4cd8000, 0x05cddbe4)
|
||||
TEST_MADD(0x99b80b00, 0x6c463000, 0x84100000, 0xd4bd99c9)
|
||||
TEST_MADD(0xdc823390, 0x5208f838, 0x1aeec780, 0xf4a0762c)
|
||||
TEST_MADD(0xe53080d8, 0x848a9c5a, 0xf600ebf0, 0x0cedfd5c)
|
||||
TEST_MADD(0x7f2163d8, 0xab5bba80, 0x9904dc00, 0xd5f77755)
|
||||
TEST_MADD(0xea7b88c0, 0x23eed510, 0xd3004c00, 0xfcfad0a2)
|
||||
TEST_MADD(0x7389b4fd, 0xea063940, 0x0ba79440, 0xf614f983)
|
||||
TEST_MADD(0xbcdf9b20, 0xc1451978, 0x4e96d700, 0x1072da6a)
|
||||
TEST_MADD(0xdcacfd50, 0x809d0a80, 0x7273c800, 0x1193d5fc)
|
||||
TEST_MADD(0x55ed3100, 0xbe5ba9f2, 0x3a915200, 0xe9f79db9)
|
||||
TEST_MADD(0xcedb5fd8, 0xe1793b60, 0x4672b900, 0x05dc29af)
|
||||
TEST_MADD(0x9d32f1b0, 0xbb2016b8, 0x2362d680, 0x1a94e275)
|
||||
TEST_MADD(0x7091ae43, 0xdb390460, 0x9b456520, 0xefd4042c)
|
||||
TEST_MADD(0x549bf440, 0xd1dc9f40, 0x2ab0d000, 0xf0c048d0)
|
||||
TEST_MADD(0x63b241cc, 0x48aefe14, 0xbfdd8bf0, 0x1c4e489c)
|
||||
TEST_MADD(0x4c925040, 0x0855d2c8, 0x7d633200, 0x027e3e22)
|
||||
TEST_MADD(0xdb2dfd2c, 0x6c0e9f09, 0xad443a8c, 0xf0754c72)
|
||||
TEST_MADD(0xdfdc9250, 0xbf1f15c3, 0x04b402f0, 0x082517d4)
|
||||
TEST_MADD(0x1b339b35, 0x98c14bc0, 0x0021eec0, 0xf50792e7)
|
||||
TEST_MADD(0xc8618b98, 0x69452a40, 0x1141d600, 0xe920fb5e)
|
||||
TEST_MADD(0x2aea0580, 0x7f50d684, 0xf943d600, 0x1557a5d1)
|
||||
TEST_MADD(0x5c69f5ec, 0x9ee23bd2, 0xfcf11f98, 0xdcf11afe)
|
||||
TEST_MADD(0xb7b66b40, 0x8b50c179, 0xa013f140, 0x20f2d35b)
|
||||
TEST_MADD(0x514e33b6, 0x7dc39988, 0x30153eb0, 0x27f14e94)
|
||||
TEST_MADD(0x27c24e12, 0xbc0e6874, 0x70beb028, 0xf572a01c)
|
||||
TEST_MADD(0xe7e6eddc, 0x13a7cad0, 0x21d4dac0, 0xfe265835)
|
||||
TEST_MADD(0xa85111c0, 0xa29d50f0, 0x844ca400, 0x1ffc597a)
|
||||
TEST_MADD(0x73d52eb8, 0x142ba310, 0x32fa1380, 0x0920663d)
|
||||
TEST_MADD(0x41156884, 0x794c5fb2, 0x9ddba7c8, 0x1ed68915)
|
||||
TEST_MADD(0xa8774820, 0xb2cf0480, 0xaaa49000, 0x1a64deef)
|
||||
TEST_MADD(0xb69bcb80, 0x88d55520, 0xdf8af000, 0x2229cfd4)
|
||||
TEST_MADD(0xe84175d8, 0x94048f1c, 0xaf5c8ba0, 0x0a03f608)
|
||||
TEST_MADD(0x6fdedbd8, 0x67dd7f60, 0x341a9900, 0x2d637581)
|
||||
TEST_MADD(0xa2319526, 0xd5f88700, 0x40770a00, 0x0f669a83)
|
||||
TEST_MADD(0x61f8b9bc, 0x146e6d38, 0xd445ad20, 0x07d1b12e)
|
||||
TEST_MADD(0xb9002828, 0x0310a1b9, 0xc4de2ce8, 0xff2663a0)
|
||||
TEST_MADD(0xb4418f47, 0x943f129c, 0xc27f4d44, 0x1fe1ae2e)
|
||||
TEST_MADD(0xd7011f8c, 0x70d8ea80, 0x6585be00, 0xededc132)
|
||||
TEST_MADD(0x058b9998, 0x55395538, 0x3b611140, 0x01d897ed)
|
||||
TEST_MADD(0xc13b7fc0, 0xda192fbb, 0x0caa9140, 0x094afe25)
|
||||
TEST_MADD(0x776d24b0, 0x66f0a9a4, 0x1423b0c0, 0x3005c214)
|
||||
TEST_MADD(0x6c6ae338, 0x5c4abc80, 0x827ebc00, 0x27161062)
|
||||
TEST_MADD(0x9dc090e0, 0xb6324980, 0x55585000, 0x1c530986)
|
||||
TEST_MADD(0x86d609de, 0xcd4bcb2e, 0x9e52cfe4, 0x17ff7c93)
|
||||
TEST_MADD(0x1400c7dc, 0x466a6d5e, 0x967a0ec8, 0x05808784)
|
||||
TEST_MADD(0xa2d88860, 0x26423686, 0x52dba240, 0xf2140c3a)
|
||||
TEST_MADD(0x6770770a, 0x812cbe10, 0x6f18dca0, 0xccc14912)
|
||||
TEST_MADD(0x95627048, 0xc1bae8ca, 0xf1bdd8d0, 0x19eeeef0)
|
||||
TEST_MADD(0x1dbadda0, 0x5d2b0f50, 0x9741a200, 0x0ad1e2ad)
|
||||
TEST_MADD(0xc7cf4f96, 0x7dd33820, 0x29f4c2c0, 0xe461dd69)
|
||||
TEST_MADD(0xa1d8f960, 0xb83e3183, 0xbf02fc20, 0x1a641a33)
|
||||
TEST_MADD(0xcc2c955e, 0x63c2877e, 0x8bf21644, 0xebcddc1e)
|
||||
TEST_MADD(0xd2d44530, 0x602b39e6, 0x4d2dd920, 0xef07f962)
|
||||
TEST_MADD(0x886c3ad7, 0xe011a4c0, 0xaf24dd40, 0x0eea3ae0)
|
||||
TEST_MADD(0x0c45d0c8, 0x830e02fb, 0x57054418, 0xfa029504)
|
||||
TEST_MADD(0x49979c44, 0x298742f0, 0x604807c0, 0x0bf02a38)
|
||||
TEST_MADD(0x2037c800, 0xfb355f34, 0xa68ca000, 0xff65a09f)
|
||||
TEST_MADD(0x21e68aeb, 0xc1cc4ec0, 0x897fca40, 0xf7c351f4)
|
||||
TEST_MADD(0xe2c488b8, 0x8ed6a9d8, 0x6de4d340, 0x0cebf803)
|
||||
TEST_MADD(0x0622c000, 0x849e669e, 0x21f28000, 0xfd0af6e8)
|
||||
TEST_MADD(0xfe11325e, 0x5a980480, 0x4132a700, 0xff50e5e2)
|
||||
TEST_MADD(0xb582a660, 0x27161c30, 0x3ef1b200, 0xf4a0785f)
|
||||
TEST_MADD(0xde436ee0, 0x0b8fd2ea, 0x09b718c0, 0xfe79f1a3)
|
||||
TEST_MADD(0x3ca5ebcc, 0x7fca89b0, 0xc03a4840, 0x1e464b84)
|
||||
TEST_MADD(0xed8ac2a2, 0x8e11d628, 0xe523d550, 0x0836ec19)
|
||||
TEST_MADD(0xee62ac9c, 0x446aed90, 0x59e583c0, 0xfb4ada5c)
|
||||
TEST_MADD(0xa5a41fa0, 0x901ecf7a, 0x5a897240, 0x277d522a)
|
||||
TEST_MADD(0x1665a95c, 0x01fa0f1c, 0x27e2ea10, 0x002c4643)
|
||||
TEST_MADD(0xf760c288, 0x024d9a70, 0x0242eb80, 0xffec246c)
|
||||
TEST_MADD(0xb91b1700, 0xff6a7770, 0x198b1000, 0x0029690d)
|
||||
TEST_MADD(0x38a15d4c, 0x4d378f48, 0xf7d3b160, 0x1114d36c)
|
||||
TEST_MADD(0xe1d0a988, 0x29062820, 0x95c27100, 0xfb29b14f)
|
||||
TEST_MADD(0xb657c3ec, 0x42373c21, 0x02ef916c, 0xecf2bc11)
|
||||
TEST_MADD(0x8cd72e00, 0x0657e392, 0xc2823c00, 0xfd2581d5)
|
||||
TEST_MADD(0xcffca4a4, 0xf52aba30, 0x85e606c0, 0x02082174)
|
||||
TEST_MADD(0xd823b826, 0xed601012, 0xaa4552ac, 0x02e66439)
|
||||
TEST_MADD(0x306f7f24, 0x6384a554, 0x3c17ebd0, 0x12d436f0)
|
||||
TEST_MADD(0x0c59e770, 0x3e387808, 0x47cbbb80, 0x03007f82)
|
||||
TEST_MADD(0xc1dd451c, 0xe125f520, 0x97d86f80, 0x077cfe1d)
|
||||
TEST_MADD(0xef4e68d4, 0x9ff2ad9b, 0xa5b8bc5c, 0x06437714)
|
||||
TEST_MADD(0x7ef6ec24, 0xb177da10, 0xdd416a40, 0xd90d3e0e)
|
||||
TEST_MADD(0x6fb25f72, 0x791ebb10, 0x583a3d20, 0x34d8b7a2)
|
||||
TEST_MADD(0x58101600, 0xd3840640, 0xbc898000, 0xf0b29693)
|
||||
TEST_MADD(0x07affc60, 0x5ea8d5b0, 0x94f96200, 0x02d7b093)
|
||||
TEST_MADD(0xf952c740, 0x73978b1c, 0x7dfd8b00, 0xfcfc3bb4)
|
||||
TEST_MADD(0x8f689828, 0x91565574, 0x7b5a3a20, 0x30abad94)
|
||||
TEST_MADD(0x914d8000, 0xba3b44b8, 0x85b40000, 0x1e2b2e25)
|
||||
TEST_MADD(0x4d2e3cf5, 0x70e9d5e8, 0x159c1708, 0x220aba3e)
|
||||
TEST_MADD(0xb037ad58, 0x11952040, 0xbfce5600, 0xfa8538dd)
|
||||
TEST_MADD(0xa4246038, 0x111ad568, 0x7085aec0, 0xf9dcc982)
|
||||
TEST_MADD(0xef964a3a, 0xd18d5d08, 0x519b63d0, 0x02fa582f)
|
||||
TEST_MADD(0xa4a7728e, 0x97843fdc, 0x884f6408, 0x25482191)
|
||||
TEST_MADD(0xdf30b100, 0x250933f8, 0x236e7800, 0xfb40dba2)
|
||||
TEST_MADD(0x1d5818a4, 0xe5093304, 0x940d0e90, 0xfce8c358)
|
||||
TEST_MADD(0x15122298, 0xcbbb9870, 0xc9816280, 0xfbb2afa1)
|
||||
TEST_MADD(0x88ca117e, 0x0e125f90, 0x0d0398e0, 0xf9727eaa)
|
||||
TEST_MADD(0xdf4ef397, 0xda63b6b6, 0xacb3875a, 0x04cd8c0a)
|
||||
TEST_MADD(0x6683ae60, 0x63fc1988, 0x187c0300, 0x2809e048)
|
||||
TEST_MADD(0xe6a56cae, 0xd0003efb, 0x9483b29a, 0x04c0f562)
|
||||
TEST_MADD(0x7d58aade, 0x5b2167ac, 0xd4f01f28, 0x2c9edfed)
|
||||
TEST_MADD(0x61118bd0, 0x9e016e14, 0x0b424c40, 0xdad7d349)
|
||||
TEST_MADD(0x7fdd22be, 0xfdcc9fee, 0xad924ea4, 0xfee69cb0)
|
||||
TEST_MADD(0x70e273a0, 0xd87fc19c, 0xdf8a1580, 0xee94f3a5)
|
||||
TEST_MADD(0x3940dad6, 0xa37c292b, 0x429907f2, 0xeb4f351f)
|
||||
TEST_MADD(0xba7ab435, 0x2322d7d0, 0xbf14ee10, 0xf6755053)
|
||||
TEST_MADD(0x0b238760, 0x2bff2a02, 0xe31ccec0, 0x01ea11f4)
|
||||
TEST_MADD(0xaa6a9390, 0x8d3ab108, 0xc1fb2c80, 0x265e80ac)
|
||||
TEST_MADD(0xe3667224, 0xbf514d80, 0x7cf1e600, 0x0739e7c6)
|
||||
TEST_MADD(0x53b1b42e, 0x7c608578, 0x67285b90, 0x28a9a18c)
|
||||
TEST_MADD(0x8241ddf4, 0x4a8d0e90, 0xa6943140, 0xdb61c148)
|
||||
TEST_MADD(0x7cdcd5cf, 0xe584065f, 0xecb231d1, 0xf3151a6c)
|
||||
TEST_MADD(0x50445224, 0xb34e8c5c, 0x687134f0, 0xe7f4141e)
|
||||
TEST_MADD(0x436d75a7, 0x2cb9b728, 0x81e3c318, 0x0bc7ba90)
|
||||
TEST_MADD(0xdb906f30, 0x0eafa7d0, 0x3fb2a700, 0xfde8e5ee)
|
||||
TEST_MADD(0x5aa5b57e, 0xeb138c80, 0x1475a700, 0xf8975429)
|
||||
TEST_MADD(0xbc61fc9c, 0x2c0b0f78, 0xb66f8d20, 0xf45deb8a)
|
||||
TEST_MADD(0x8b3566b7, 0x2b021ecc, 0xbb054bd4, 0xec61009e)
|
||||
TEST_MADD(0x666e54e8, 0xed91452c, 0x37411fe0, 0xf89fefde)
|
||||
TEST_MADD(0xc6e59380, 0xfa935180, 0xc8f54000, 0x0135c230)
|
||||
TEST_MADD(0xd921e0b0, 0x1f7d65c0, 0x3cfdf400, 0xfb38104d)
|
||||
TEST_MADD(0x7b8db2e2, 0x84d37b50, 0xa9807ca0, 0xc48d6ea8)
|
||||
TEST_MADD(0xf89e1b58, 0x26be32a0, 0x9f784700, 0xfee1fbf1)
|
||||
TEST_MADD(0x524aa0a6, 0x0b334594, 0xd3839df8, 0x0399b022)
|
||||
TEST_MADD(0xa3be10e8, 0x18dbc860, 0x1af39700, 0xf70a9cf8)
|
||||
TEST_MADD(0x073cf5be, 0x4fbf4882, 0xccd43a7c, 0x0241385d)
|
||||
TEST_MADD(0x91db7100, 0x1f78ebb0, 0xaf98b000, 0xf2758c24)
|
||||
TEST_MADD(0xc49e36d8, 0x2044fa90, 0xabedc980, 0xf883c6c2)
|
||||
TEST_MADD(0xaf4ab2b8, 0xf0086f40, 0x4bea7600, 0x0508ac17)
|
||||
TEST_MADD(0xc72f0de2, 0x407a26e0, 0x62efb1c0, 0xf1b0a744)
|
||||
TEST_MADD(0x95d26876, 0x9aaece1c, 0xaf4660e8, 0x2a05a9e7)
|
||||
TEST_MADD(0x72e2ec10, 0xb9098e00, 0xbb80e000, 0xe0275a3b)
|
||||
TEST_MADD(0xdeb27a9c, 0x506c0849, 0x8e89d67c, 0xf589b888)
|
||||
TEST_MADD(0x530194f0, 0x00000000, 0x00000000, 0x00000000)
|
||||
TEST_MADD(0x5a1a4f60, 0x00000000, 0x00000000, 0x00000000)
|
||||
TEST_MADD(0x5cc4e136, 0x00000000, 0x00000000, 0x00000000)
|
||||
TEST_MADD(0xab7a14c0, 0x00000000, 0x00000000, 0x00000000)
|
||||
TEST_MADD(0x44d126d0, 0x00000000, 0x00000000, 0x00000000)
|
||||
TEST_MADD(0x0f114ff0, 0x00000000, 0x00000000, 0x00000000)
|
||||
TEST_MADD(0x60bfe48e, 0x00000000, 0x00000000, 0x00000000)
|
||||
TEST_MADD(0x102ceba0, 0x00000000, 0x00000000, 0x00000000)
|
||||
TEST_MADD(0x7b21e54d, 0x00000000, 0x00000000, 0x00000000)
|
||||
TEST_MADD(0x5d72f954, 0x00000000, 0x00000000, 0x00000000)
|
||||
TEST_MADD(0x2699b2d4, 0x00000000, 0x00000000, 0x00000000)
|
||||
TEST_MADD(0x66b6dc30, 0x00000000, 0x00000000, 0x00000000)
|
||||
TEST_MADD(0x00000000, 0x4ae569a0, 0x00000000, 0x00000000)
|
||||
TEST_MADD(0x00000000, 0x2582c9c0, 0x00000000, 0x00000000)
|
||||
TEST_MADD(0x00000000, 0xa2f01d2e, 0x00000000, 0x00000000)
|
||||
TEST_MADD(0x00000000, 0x2c5300d7, 0x00000000, 0x00000000)
|
||||
TEST_MADD(0x00000000, 0x7a95fab0, 0x00000000, 0x00000000)
|
||||
TEST_MADD(0x00000000, 0xf415d1b4, 0x00000000, 0x00000000)
|
||||
TEST_MADD(0x00000000, 0x0caf7d5c, 0x00000000, 0x00000000)
|
||||
TEST_MADD(0x00000000, 0xae15e524, 0x00000000, 0x00000000)
|
||||
TEST_MADD(0x00000000, 0x00000000, 0x00000000, 0x00000000)
|
||||
|
||||
TEST_MADD_HL(0x3ffa9606, 0x2ec9a237, 0x4f85ec7, 0x49b98207, 0x10a9ca06, 0x7a358951)
|
||||
TEST_MADD_HL(0x2a484469, 0x49cd5c37, 0x3fa82db5, 0x183a608f, 0x4bd8b450, 0xdf6bcf1e)
|
||||
TEST_MADD_HL(0x7710d9e, 0x50e34fd8, 0x60c5acb, 0x2a7aa93b, 0x8664a9d, 0xc82be88b)
|
||||
TEST_MADD_HL(0x21af30ae, 0x1ca02d03, 0x685858bd, 0x4ccefd25, 0x6c1c957a, 0xf22b252f)
|
||||
TEST_MADD_HL(0x66e1d799, 0x15e2a286, 0x549dd00, 0x192b8658, 0xe157860, 0xbfe3326e)
|
||||
TEST_MADD_HL(0x2cdf6375, 0x46894689, 0x4b567cb6, 0x4c91a38e, 0x57b3a1d1, 0x9cecdb2b)
|
||||
TEST_MADD_HL(0x384ff312, 0x4d113d2d, 0x2f3bf51a, 0x6cde72ab, 0x402fcbfa, 0xee0976d5)
|
||||
TEST_MADD_HL(0x4f8f28d6, 0x700964be, 0x6d5d7152, 0x7ebc2a16, 0x902efe87, 0x867610ea)
|
||||
TEST_MADD_HL(0x7268c53b, 0x4e97d2f6, 0x423151f2, 0x77039cdb, 0x6551181e, 0xa948898d)
|
||||
TEST_MADD_HL(0x34a1dac8, 0x731edd3, 0x2191539d, 0x14aaaf82, 0x230c0478, 0xa5e52a5a)
|
||||
TEST_MADD_HL(0x38a93df0, 0x780fdf0d, 0x69ee8549, 0x760b12a2, 0x84815d9a, 0xe4a747d2)
|
||||
TEST_MADD_HL(0x4dc97219, 0x55706f51, 0x1b0139ac, 0x55296e02, 0x34f74683, 0x824f5eeb)
|
||||
TEST_MADD_HL(0x4b344740, 0x460cfbd0, 0x6f65df3a, 0x2aa79291, 0x83f9fb22, 0x5dfd3691)
|
||||
TEST_MADD_HL(0x57b9e34c, 0x2b18f00b, 0x75bbcb52, 0x18cab68, 0x8480902f, 0x1ec0afac)
|
||||
TEST_MADD_HL(0x658790b5, 0x4a97352d, 0x5ce17a3b, 0x2aa4a63e, 0x7a76a21c, 0xc1318f0f)
|
||||
TEST_MADD_HL(0x6b8988a4, 0x27b50c98, 0x68e046e4, 0x58074456, 0x798e483d, 0x3c0c15b6)
|
||||
TEST_MADD_HL(0x28d1c4d1, 0x1d0057d6, 0x6bb9e389, 0x494e5c23, 0x7059b4d6, 0x5f8be9d9)
|
||||
TEST_MADD_HL(0x587bb637, 0x834133, 0x7600c26c, 0x5f1dd4c0, 0x762e2043, 0xa72c18b5)
|
||||
TEST_MADD_HL(0x2b68665a, 0x4893d96a, 0x125d7428, 0x14877c51, 0x1eabe2c1, 0xa2322795)
|
||||
TEST_MADD_HL(0xb5c1cf2, 0x1b2da090, 0x4748e98a, 0x75ee72e4, 0x487da6e9, 0x85ffb04)
|
||||
TEST_MADD_HL(0xcdcf4d3, 0x5a3d34b1, 0x75173633, 0x14005110, 0x799ff791, 0x5ec772f3)
|
||||
TEST_MADD_HL(0x6371ed7e, 0x6c616d5e, 0x40cb334f, 0x205fd567, 0x6ae51c27, 0x4b11afab)
|
||||
TEST_MADD_HL(0x1ee83aa2, 0x3f599121, 0x37a988e2, 0x74ab081a, 0x3f4f7f92, 0x3a2258fc)
|
||||
TEST_MADD_HL(0x2b224e5a, 0x42474ca6, 0x7a1b42a8, 0x1e1a36ee, 0x85461e49, 0x3491bd4a)
|
||||
TEST_MADD_HL(0x6971661b, 0xed01afa, 0x3fd96431, 0xe2b4d80, 0x45f34f05, 0xfb37c1de)
|
||||
TEST_MADD_HL(0x7aa889a, 0x3232730c, 0x5b5cb929, 0x7b926513, 0x5cdd8a98, 0x3501fa4b)
|
||||
TEST_MADD_HL(0x521db924, 0x45955f95, 0x47055a30, 0x7bfc519f, 0x5d57470c, 0xc4f16f93)
|
||||
TEST_MADD_HL(0x1e57cdc0, 0x3e302706, 0x457bbe9e, 0x356fcb3e, 0x4cdab789, 0x5fd6ddbe)
|
||||
TEST_MADD_HL(0x453e578b, 0x296c5885, 0x70ec10da, 0xdef7d87, 0x7c205b1d, 0xa70ec0be)
|
||||
TEST_MADD_HL(0x1f0789c7, 0x772750f, 0x54fbf440, 0x27b6cf32, 0x55e30890, 0x36bdd4db)
|
||||
TEST_MADD_HL(0x28c2bf37, 0x3eb5b830, 0x4f997d14, 0x653227e4, 0x59959668, 0x87088a34)
|
||||
TEST_MADD_HL(0x3ff09fd3, 0x7f40c729, 0xf11ce77, 0x58f3e39a, 0x2eda5ba7, 0x447a8165)
|
||||
TEST_MADD_HL(0x7a8ee4fa, 0x7fad66c1, 0x322337be, 0x19f196bf, 0x6f431f18, 0x31d9d339)
|
||||
TEST_MADD_HL(0x7ec260f7, 0x34621f16, 0x55bda8f, 0x67fc7485, 0x1f4bec0f, 0x20fcb2bf)
|
||||
TEST_MADD_HL(0x464d0d26, 0x3ea0a65e, 0x57d155b0, 0x1917b2b4, 0x69041cb7, 0x4ba92aa8)
|
||||
TEST_MADD_HL(0x69ffdb6a, 0x1103fa4b, 0x41e22644, 0x2b05c73b, 0x48edc978, 0xb17e9349)
|
||||
TEST_MADD_HL(0x494cbe3, 0x7ff21fe4, 0x1e553b8e, 0x63afc33, 0x209f61ee, 0x79070f5f)
|
||||
TEST_MADD_HL(0x1f515041, 0x60734879, 0x928cbbb, 0x2046748c, 0x14f56438, 0x397aab45)
|
||||
TEST_MADD_HL(0x33586380, 0x39e493af, 0x6452f37d, 0x3d654dfd, 0x6fef79fc, 0x35f3d27d)
|
||||
TEST_MADD_HL(0x42e048bc, 0x2ef92fa8, 0x6db210c7, 0x596094f7, 0x79f77672, 0xf0c6d457)
|
||||
TEST_MADD_HL(0x5b773b03, 0x771e9c22, 0xce24ba6, 0x6ee43f56, 0x3771a7d6, 0x8c09e9bc)
|
||||
TEST_MADD_HL(0x7b0030d9, 0x2f5d4582, 0x76136f99, 0x6d8732c9, 0x8cd54908, 0x869f7dfb)
|
||||
TEST_MADD_HL(0x1576a666, 0x4225125c, 0x6276ce2f, 0x4dded742, 0x680280c5, 0xb4f3cfea)
|
||||
TEST_MADD_HL(0x51e52cc5, 0x1c1eac43, 0x2fcfd730, 0x74ac61e, 0x38ceb80c, 0x3b6fd9ad)
|
||||
TEST_MADD_HL(0xd63d3c, 0x3c8dc70b, 0x45e03303, 0x6a1aaf64, 0x4612e003, 0xc6f4f4f8)
|
||||
TEST_MADD_HL(0x3d04a2b3, 0x1efe47fc, 0x4333b47d, 0x60e23ca, 0x4a96db4f, 0xc757f0fe)
|
||||
TEST_MADD_HL(0x6ac8e244, 0x5111ef21, 0x7617b3a, 0x6ac0b700, 0x293285e8, 0x44675dc4)
|
||||
TEST_MADD_HL(0x7d7e66ff, 0x3ca4b10e, 0x410ab06c, 0x38ae81db, 0x5ec50c55, 0x3a2a72cd)
|
||||
TEST_MADD_HL(0x7986f836, 0x204afbb8, 0x53b458b1, 0x76c68901, 0x6308d03a, 0xa4c1e1d1)
|
||||
TEST_MADD_HL(0x3b8aff19, 0x7690a3b, 0x70480e48, 0x519504e4, 0x720149a5, 0xc8d5c9a7)
|
||||
TEST_MADD_HL(0x5970628c, 0x23f253dc, 0x2f669193, 0x67d82f66, 0x3bf59896, 0xb843b6)
|
||||
TEST_MADD_HL(0x62a37156, 0x688bf56c, 0x28da9632, 0x7b36f4ae, 0x5122e98b, 0xfd5412f6)
|
||||
TEST_MADD_HL(0x1d6c7ee8, 0x17242ebe, 0x3e27a206, 0x2e3be9ab, 0x40d08a0e, 0x342fc9db)
|
||||
TEST_MADD_HL(0x2f233874, 0x48f65d8c, 0x43084058, 0x3090409f, 0x5077854a, 0xa2cd440f)
|
||||
TEST_MADD_HL(0x18b105e, 0x7a4eeaac, 0x7310cd6c, 0x6a9a07f9, 0x73cd8d02, 0x59a2f321)
|
||||
TEST_MADD_HL(0x25e35403, 0x47ee0bfd, 0x50552c62, 0x56773971, 0x5afa73cd, 0x7c876168)
|
||||
TEST_MADD_HL(0x67aef435, 0x788bb051, 0x65bd08fd, 0x46b41b5f, 0x968f9edd, 0xcdbad024)
|
||||
TEST_MADD_HL(0x22e4dc4d, 0x7facb0bc, 0x4e2baddc, 0x5607716c, 0x5f92c101, 0x844a29f8)
|
||||
TEST_MADD_HL(0x2f3e84a9, 0x603a9790, 0x3e11105b, 0x7334dfab, 0x4fd3523d, 0x54e92dbb)
|
||||
TEST_MADD_HL(0x25a8bf94, 0x223ec179, 0x7430048f, 0x6d8da55e, 0x7939a955, 0x8096c652)
|
||||
TEST_MADD_HL(0x20628e96, 0x424891e9, 0x2cfcebf6, 0x15335ae7, 0x355f82e6, 0x27da176d)
|
||||
TEST_MADD_HL(0x6e69a55e, 0x332e77d3, 0x5c510119, 0x7679ae46, 0x726417b5, 0x44facc0)
|
||||
TEST_MADD_HL(0xeb9c8ab, 0x339bbb12, 0x28b0c362, 0x3695ef65, 0x2ba8bb9b, 0x85c3f46b)
|
||||
TEST_MADD_HL(0x7d0b9c64, 0x45820225, 0x753834fa, 0x6e626136, 0x972bd712, 0xf710c3aa)
|
||||
TEST_MADD_HL(0x9e615f8, 0xd0546c8, 0x6d7de141, 0x551b140e, 0x6dfec49a, 0xb60dce)
|
||||
TEST_MADD_HL(0x15a53409, 0x3aa005a0, 0x16729b72, 0x5d2c4093, 0x1b6790f6, 0xae10f333)
|
||||
TEST_MADD_HL(0x5d764422, 0x40d671f8, 0x7e4cc0b1, 0x25eb8cbc, 0x95f89c32, 0x58fc8fac)
|
||||
TEST_MADD_HL(0x14345e1a, 0x3400927c, 0x7e3c4a3, 0x19f39e23, 0xbfe7350, 0x8fc06bb)
|
||||
TEST_MADD_HL(0x431b6455, 0x76c26e15, 0x7ecc8946, 0x4661c588, 0x9dee2122, 0xc3278681)
|
||||
TEST_MADD_HL(0x28d5005f, 0xa6864e1, 0x570cc176, 0x79d338e0, 0x58b5ba19, 0x6dc5a85f)
|
||||
TEST_MADD_HL(0x2bb06474, 0x13c232f5, 0x2be48281, 0x2933779, 0x2f43be54, 0x1ea027d)
|
||||
TEST_MADD_HL(0x66851d6b, 0x4f96265f, 0x27efb289, 0x588f6b87, 0x47cee7fa, 0x6805383c)
|
||||
TEST_MADD_HL(0x6642506b, 0x593a2d0a, 0x3eb658ad, 0x45869592, 0x625aa3a6, 0x577e88c0)
|
||||
TEST_MADD_HL(0x3be1d1aa, 0x255733c3, 0x349adebd, 0x59affc21, 0x3d56e7e4, 0xc63d8e9f)
|
||||
TEST_MADD_HL(0x16aa3ce5, 0x44ae086c, 0x8dee349, 0x414af426, 0xef383ea, 0x5aa9ccc2)
|
||||
TEST_MADD_HL(0x754a9f3, 0x21bac617, 0x38634d12, 0x3b01dd94, 0x395a902a, 0x2c9d1469)
|
||||
TEST_MADD_HL(0x17eff7d8, 0x6eb296fa, 0x1aa3da71, 0xbb98100, 0x24fda9e8, 0x2b7a19f0)
|
||||
TEST_MADD_HL(0x2a058b26, 0x472f997c, 0x1303a677, 0x31a66c51, 0x1eb30044, 0xf27988b9)
|
||||
TEST_MADD_HL(0x628582af, 0x315cb320, 0x5a40959b, 0x1ae2df0e, 0x6d3fd089, 0x3bd791ee)
|
||||
TEST_MADD_HL(0xce49f7f, 0x404b91e, 0x58bffef3, 0xe782829, 0x58f3ce56, 0x4281a00b)
|
||||
TEST_MADD_HL(0x3bdee326, 0x26603511, 0x7aecbc33, 0x515714ee, 0x83e651e9, 0x426b0874)
|
||||
TEST_MADD_HL(0x57eba2c1, 0x65878679, 0x1aa9c58b, 0x6594d212, 0x3d884833, 0x43ecc54b)
|
||||
TEST_MADD_HL(0x31704326, 0x4f8780f1, 0x724f5c1b, 0x6f62c32c, 0x81ab2bee, 0x3eaef9f2)
|
||||
TEST_MADD_HL(0x7ef027ff, 0x6df84a6b, 0x29178f14, 0x5685062e, 0x5f9eeda9, 0x227d73c3)
|
||||
TEST_MADD_HL(0x2065af1b, 0x58cfeda5, 0x2b08f712, 0x67643fbd, 0x36463b8f, 0x4adf1b24)
|
||||
TEST_MADD_HL(0x77af1e48, 0x5c94dff4, 0x39c063fc, 0x42840a8c, 0x6508eccf, 0x426d9f2c)
|
||||
TEST_MADD_HL(0x7b28ac0a, 0x520ec0ca, 0x12f1355f, 0x7d22570a, 0x3a6b5573, 0xc8cd96ee)
|
||||
TEST_MADD_HL(0x401610e1, 0x4449fc8c, 0x6830f3d4, 0x57d7f884, 0x794955d3, 0xb0afaf90)
|
||||
TEST_MADD_HL(0x27c8f73c, 0x5bc4c900, 0x50df921f, 0x5c205ee1, 0x5f22971b, 0xc42e7ae1)
|
||||
TEST_MADD_HL(0x73d355a1, 0x7c06d299, 0x5305fe9f, 0x46959a40, 0x8b237255, 0xd9e7d979)
|
||||
TEST_MADD_HL(0x660269ef, 0x348cdd06, 0x6c065cc1, 0xb3c33c, 0x80f6fba9, 0xf4e991d6)
|
||||
TEST_MADD_HL(0x53caf6fd, 0x400c0314, 0x30b8dd46, 0x6232ccc5, 0x45af898b, 0x22cf0f89)
|
||||
TEST_MADD_HL(0x7b663c4c, 0x70ed71ea, 0x741c60bf, 0x65f29626, 0xaa8b8faf, 0x645f3f9e)
|
||||
TEST_MADD_HL(0x21a8e4b, 0x8bb61df, 0x3e9135f8, 0x66e5d0c8, 0x3ea3949e, 0x94bb2f1d)
|
||||
TEST_MADD_HL(0x14d0eaa9, 0x4ae67521, 0x4afe1086, 0x7cfa7e07, 0x51153194, 0x54fdfad0)
|
||||
TEST_MADD_HL(0x313ccf02, 0x259a6aee, 0x5293de2b, 0xe9d678, 0x59cf5b3b, 0xc65d1e54)
|
||||
TEST_MADD_HL(0x4bd68daf, 0x716f6457, 0x38884eb9, 0x26e74b9f, 0x5a230304, 0x6a0ace18)
|
||||
TEST_MADD_HL(0x68d50008, 0x324b867, 0x687e8657, 0x48ab311c, 0x69c80ece, 0xa783f454)
|
||||
TEST_MADD_HL(0x6d360b8a, 0xb7c4550, 0x7d4325e7, 0xf0e383e, 0x82297c25, 0x45e6055e)
|
||||
TEST_MADD_HL(0x1f1d19b9, 0x1c91739d, 0x146ee94b, 0x1f99220c, 0x17e7c5a4, 0x14c90381)
|
||||
|
||||
|
||||
###detect exception
|
||||
bne s2, zero, inst_error
|
||||
nop
|
||||
###score ++
|
||||
addiu s3, s3, 1
|
||||
###output (s0<<24)|s3
|
||||
inst_error:
|
||||
sll t1, s0, 24
|
||||
or t0, t1, s3
|
||||
sw t0, 0(s1)
|
||||
jr ra
|
||||
nop
|
||||
END(n95_madd_test)
|
||||
266
resources/2021/soft/func/inst/n96_maddu.S
Normal file
266
resources/2021/soft/func/inst/n96_maddu.S
Normal file
@ -0,0 +1,266 @@
|
||||
#include <asm.h>
|
||||
#include <regdef.h>
|
||||
#include <inst_test.h>
|
||||
|
||||
LEAF(n96_maddu_test)
|
||||
.set noreorder
|
||||
addiu s0, s0 ,1
|
||||
li s2, 0x0
|
||||
###test inst
|
||||
TEST_MADDU(0x99c9a500, 0x6c1a1b60, 0xb204e000, 0x40f0c088)
|
||||
TEST_MADDU(0xee026dc0, 0xd85e0aec, 0xcf06ad00, 0xc9297ba5)
|
||||
TEST_MADDU(0xa49b33d4, 0x894d6a78, 0x76fa1360, 0x5848d5e0)
|
||||
TEST_MADDU(0xd16d0152, 0xbcd4f694, 0x22318f68, 0x9a7a44f5)
|
||||
TEST_MADDU(0x9880cf50, 0xd7e33d18, 0x01697f80, 0x809b8cb9)
|
||||
TEST_MADDU(0x686decfc, 0x2bb09c9f, 0x19efc084, 0x11d28245)
|
||||
TEST_MADDU(0x290ca739, 0xc1cc4ec0, 0xdedcc8c0, 0x1f134cc7)
|
||||
TEST_MADDU(0x1d1eb998, 0xd5b8328e, 0x048aa250, 0x184f8441)
|
||||
TEST_MADDU(0x79b7d394, 0x0ba99ece, 0x6f359918, 0x058b8bf3)
|
||||
TEST_MADDU(0x0d7f9488, 0x3647ab9c, 0x53ad5ae0, 0x02dcb0c3)
|
||||
TEST_MADDU(0x3196de58, 0x4c28d54e, 0x80b6f6d0, 0x0ec0b2e6)
|
||||
TEST_MADDU(0x473a0e0a, 0xe0925338, 0x28f45030, 0x3e7b828c)
|
||||
TEST_MADDU(0x3721c560, 0xe7f35d08, 0xf7e20b00, 0x31f3e230)
|
||||
TEST_MADDU(0x536cd050, 0x675dc658, 0xb3957b80, 0x21af56fa)
|
||||
TEST_MADDU(0x2310a2f4, 0x07cd8030, 0x0dfc8dc0, 0x01119a56)
|
||||
TEST_MADDU(0xc2fd5307, 0x034a3375, 0xaa575733, 0x02817c64)
|
||||
TEST_MADDU(0x79fba360, 0xcc308ea8, 0xc3c27700, 0x614ba958)
|
||||
TEST_MADDU(0x3f1c7b7a, 0x89f4a9ff, 0xa52a8886, 0x22028f22)
|
||||
TEST_MADDU(0x6451cbd8, 0x85dc2080, 0xc800ec00, 0x3474c1ee)
|
||||
TEST_MADDU(0x8885fb40, 0x65a9fc18, 0xcd228e00, 0x36378303)
|
||||
TEST_MADDU(0x71f5e890, 0x1c7fba40, 0x47e2c400, 0x0cafc157)
|
||||
TEST_MADDU(0x527b08db, 0xc4c2d838, 0x3c58b7e8, 0x3f64f9ae)
|
||||
TEST_MADDU(0xd2d00316, 0x5ce48028, 0x99a37b70, 0x4c7eebe7)
|
||||
TEST_MADDU(0xa47ba800, 0x83d06930, 0x0f178000, 0x54b12f06)
|
||||
TEST_MADDU(0xcb3eee22, 0x59a7fa20, 0x0698f840, 0x472e3d6c)
|
||||
TEST_MADDU(0x4092ce98, 0xef2cbae3, 0x5667a0c8, 0x3c54573f)
|
||||
TEST_MADDU(0x76a3d520, 0x0219a7f1, 0xa0638320, 0x00f92b7e)
|
||||
TEST_MADDU(0x4dba87a0, 0xabfd53c0, 0xaefe9800, 0x3438835d)
|
||||
TEST_MADDU(0xb21ddb80, 0x86c4337c, 0x4730d200, 0x5dc42393)
|
||||
TEST_MADDU(0x24bf43c2, 0x5ebb156c, 0xebf57fd8, 0x0d9915aa)
|
||||
TEST_MADDU(0x88933830, 0x9b18625e, 0xd61101a0, 0x52be254c)
|
||||
TEST_MADDU(0x3bd6f96c, 0x1c413041, 0xa4c5946c, 0x069ac024)
|
||||
TEST_MADDU(0x0b093c0a, 0xf967e2ce, 0xea75240c, 0x0ac075e3)
|
||||
TEST_MADDU(0xf0e46398, 0x95dbf923, 0xbf2075c8, 0x8d03ebc7)
|
||||
TEST_MADDU(0x109f0e5c, 0xc6bd4b78, 0x25afaf20, 0x0ce74f6f)
|
||||
TEST_MADDU(0x23a1f870, 0x88a80670, 0xec2f5100, 0x13056f2b)
|
||||
TEST_MADDU(0x383bf8e0, 0x78e11c9e, 0x011c1a40, 0x1a8d8fa8)
|
||||
TEST_MADDU(0x7a249e47, 0xde35e25c, 0x8f968f84, 0x6a0576d6)
|
||||
TEST_MADDU(0x9bbd1a87, 0x87bced28, 0x133f2018, 0x5293a823)
|
||||
TEST_MADDU(0x58b0b4c2, 0x4b2eaf04, 0x7f2f7108, 0x1a0bf157)
|
||||
TEST_MADDU(0xabb5baa8, 0xe59a0d6c, 0x3c3546e0, 0x9a00e44b)
|
||||
TEST_MADDU(0xef331cb8, 0xb5a98f8c, 0x6a767ca0, 0xa9bd922c)
|
||||
TEST_MADDU(0xfbd21f10, 0xe381c1fc, 0x2351a3c0, 0xdfcaf53e)
|
||||
TEST_MADDU(0x0e437d14, 0xf76494cd, 0x982ab904, 0x0dc8b855)
|
||||
TEST_MADDU(0x36f97280, 0xd2dc44ac, 0x9802ee00, 0x2d47ed0a)
|
||||
TEST_MADDU(0xc0196848, 0x23e672e2, 0x6f8e1f90, 0x1af0664a)
|
||||
TEST_MADDU(0xad0af755, 0x46ab8a3c, 0xebacc9ec, 0x2fc4f364)
|
||||
TEST_MADDU(0x78c438e8, 0xb59296e0, 0x2159bb00, 0x55a7e351)
|
||||
TEST_MADDU(0x95417ec8, 0xcdef10ec, 0x35056060, 0x7810d489)
|
||||
TEST_MADDU(0xabd42ba4, 0x9f4dfd40, 0xa07ffd00, 0x6aed1fe7)
|
||||
TEST_MADDU(0x9c767890, 0x13f10784, 0x19f21a40, 0x0c301b12)
|
||||
TEST_MADDU(0x337174a4, 0x53b2a442, 0x38012248, 0x10d1aeb6)
|
||||
TEST_MADDU(0x8bbc4c00, 0x4f9ed450, 0x81c7c000, 0x2b75cd8e)
|
||||
TEST_MADDU(0x98e39c2e, 0xdb32e0b0, 0x201f9fa0, 0x82e91940)
|
||||
TEST_MADDU(0x6b08ed68, 0x1ec93800, 0x8a96c000, 0x0cdf2d3e)
|
||||
TEST_MADDU(0xdedaacc4, 0x652203d0, 0xe7baab40, 0x5809e285)
|
||||
TEST_MADDU(0xa7151a96, 0x4efab6b6, 0x74638aa4, 0x338c0ff5)
|
||||
TEST_MADDU(0xb11df5a0, 0x7312ec50, 0x1d0c4200, 0x4f9d8cf1)
|
||||
TEST_MADDU(0x800e4cb0, 0x39de6540, 0x58749c00, 0x1cf26e1f)
|
||||
TEST_MADDU(0x6ba01e66, 0x6141f7c8, 0xf05229b0, 0x28e36757)
|
||||
TEST_MADDU(0x05c01d30, 0x51b5330e, 0x694228a0, 0x01d5db36)
|
||||
TEST_MADDU(0x7b685660, 0x557152ba, 0x15d981c0, 0x2930459d)
|
||||
TEST_MADDU(0x4396b2d6, 0x7d40f2c4, 0x67ef37d8, 0x2111bb17)
|
||||
TEST_MADDU(0xa33d54b2, 0x1ff7f310, 0xb0f84120, 0x1462886b)
|
||||
TEST_MADDU(0x827d4976, 0x46c7d260, 0x13f85840, 0x24141cb6)
|
||||
TEST_MADDU(0xb2c46680, 0x2106dc9b, 0xec000f80, 0x17101bdd)
|
||||
TEST_MADDU(0x61e8744c, 0xf0485710, 0x136d18c0, 0x5be597b4)
|
||||
TEST_MADDU(0x510523c0, 0xc4eef4ec, 0xd34ff500, 0x3e538fa9)
|
||||
TEST_MADDU(0x6cab5300, 0x24d47fd0, 0x05607000, 0x0fa24bce)
|
||||
TEST_MADDU(0x113f38b0, 0x960f0fb8, 0x8c130e80, 0x0a1c0efa)
|
||||
TEST_MADDU(0xa4cd966c, 0x8946015e, 0x3e9ba7a8, 0x585f1698)
|
||||
TEST_MADDU(0x997ab490, 0x8318fc14, 0x64d3db40, 0x4e98c507)
|
||||
TEST_MADDU(0x3bf04cfc, 0x4303bb23, 0x950a9a74, 0x0fb0c3c7)
|
||||
TEST_MADDU(0xf58f5fa3, 0x6095f500, 0x0065ff00, 0x5ca59b52)
|
||||
TEST_MADDU(0xabaa4e80, 0x370ea7f2, 0x2b33b500, 0x24eb6acc)
|
||||
TEST_MADDU(0x3a8cff75, 0xc7c89600, 0x24168e00, 0x2db17b0a)
|
||||
TEST_MADDU(0x6952957c, 0x9f95ba00, 0x05c81800, 0x41a7e46f)
|
||||
TEST_MADDU(0xf003fcc0, 0x6bf9ab92, 0xa2da6580, 0x653bbf60)
|
||||
TEST_MADDU(0x948df508, 0x9aa84872, 0xb1615d90, 0x59bf0c99)
|
||||
TEST_MADDU(0xe14aa0c0, 0xf0d16230, 0x0c47a400, 0xd3ee3b0a)
|
||||
TEST_MADDU(0xb1d8a680, 0x99f2fdf0, 0xbca89800, 0x6af34ab9)
|
||||
TEST_MADDU(0x06d53ad0, 0x6289382a, 0xdd292620, 0x02a14a1f)
|
||||
TEST_MADDU(0xb406d184, 0xce15399c, 0xa0a21070, 0x90ec69aa)
|
||||
TEST_MADDU(0xff4c6260, 0xf71b2a00, 0x8843c000, 0xf66dc9db)
|
||||
TEST_MADDU(0x02f13cac, 0xea42d2c0, 0xf50a9900, 0x02b14612)
|
||||
TEST_MADDU(0x7fb89370, 0x6495a978, 0x480a0c80, 0x322ec492)
|
||||
TEST_MADDU(0xdb044c80, 0x5bb448cc, 0x06f0f600, 0x4e74c47f)
|
||||
TEST_MADDU(0xa90dec6c, 0xf03cd014, 0x2e7e3870, 0x9ea53651)
|
||||
TEST_MADDU(0x72b3e604, 0x3ccf167e, 0xd78b8df8, 0x1b3ef373)
|
||||
TEST_MADDU(0xf181714c, 0xe0304af4, 0x585ff470, 0xd37ed21d)
|
||||
TEST_MADDU(0x7a1bddc0, 0x5b74305c, 0xd697b100, 0x2b9f5384)
|
||||
TEST_MADDU(0x53901b70, 0x582d6690, 0xbeae0f00, 0x1cc85b3d)
|
||||
TEST_MADDU(0x1abfafc4, 0x4c4d5a00, 0x71bee800, 0x07f8fd3d)
|
||||
TEST_MADDU(0xc401c3d9, 0x644283da, 0x12aad1ca, 0x4cc39de9)
|
||||
TEST_MADDU(0xc3d92a7c, 0x10f8e302, 0x007e48f8, 0x0cfbfab4)
|
||||
TEST_MADDU(0x58474c02, 0x9f6992fe, 0xaae88dfc, 0x36f8b023)
|
||||
TEST_MADDU(0xbb0f6845, 0x164774b0, 0x6ef9f370, 0x1047897f)
|
||||
TEST_MADDU(0x3a0547ba, 0x97b4583e, 0x02b74f0c, 0x2261fd05)
|
||||
TEST_MADDU(0xc418111b, 0xf49130d0, 0x430df5f0, 0xbb562753)
|
||||
TEST_MADDU(0x696fdee5, 0x716028d0, 0xd098e210, 0x2eb1fc25)
|
||||
TEST_MADDU(0x6b09a660, 0xe6f17192, 0x2e5142c0, 0x608f9f0c)
|
||||
TEST_MADDU(0xe52e58ea, 0xc1a21800, 0x0669f000, 0xad590dd9)
|
||||
TEST_MADDU(0x1060c3f6, 0x0eede718, 0xb8a35910, 0x00f48315)
|
||||
TEST_MADDU(0xdf061f84, 0xd9f51b0d, 0x05f685b4, 0xbde1b924)
|
||||
TEST_MADDU(0x2ef301f4, 0x5f1a8bd0, 0xd6491240, 0x11710c0b)
|
||||
TEST_MADDU(0x46c24000, 0x73818980, 0x95600000, 0x1fed10a3)
|
||||
TEST_MADDU(0x257e27d0, 0x1dcebf84, 0x0e20b740, 0x045d9213)
|
||||
TEST_MADDU(0xa94202b9, 0x78c54868, 0x23f22328, 0x4fd960f2)
|
||||
TEST_MADDU(0x2981ba00, 0xfa88781d, 0x52e21200, 0x289ed008)
|
||||
TEST_MADDU(0x3ee64b08, 0x5534a83a, 0x470a3fd0, 0x14ef6706)
|
||||
TEST_MADDU(0x9178bce0, 0x6bd37980, 0x1a445000, 0x3d45a280)
|
||||
TEST_MADDU(0x0bcfbae8, 0xe12afb00, 0x3e517800, 0x0a638eef)
|
||||
TEST_MADDU(0xeea80fda, 0x99dd6bd0, 0x205eff20, 0x8f70dd11)
|
||||
TEST_MADDU(0xcd7ccc40, 0x79ffffca, 0x27acea80, 0x61ed792b)
|
||||
TEST_MADDU(0xf0d9a3fc, 0xbd1da000, 0xa6098000, 0xb1ec8d40)
|
||||
TEST_MADDU(0x575f3e98, 0x71669498, 0xf94d0a40, 0x26b40d4a)
|
||||
TEST_MADDU(0x1cc38b14, 0x5973913a, 0xb40fd688, 0x0a0cf782)
|
||||
TEST_MADDU(0x89c6f81f, 0xa2802db0, 0x5fe80850, 0x5774e516)
|
||||
TEST_MADDU(0x455a3838, 0x847ad600, 0x15aed000, 0x23e3cbf5)
|
||||
TEST_MADDU(0x3dfb93e4, 0x4f109ba8, 0x99e419a0, 0x1324a80c)
|
||||
TEST_MADDU(0x7a51a910, 0x2038e3d6, 0xa4ac8360, 0x0f6563db)
|
||||
TEST_MADDU(0xa0042132, 0x78d9f754, 0x10c42268, 0x4b8a2da8)
|
||||
TEST_MADDU(0x194f7a4e, 0xc9fad040, 0x9569f380, 0x13f8333b)
|
||||
TEST_MADDU(0x28e55f80, 0xa3d2a69c, 0x7eb33200, 0x1a2bb294)
|
||||
TEST_MADDU(0xbcc4d7a8, 0x923c7e90, 0x6c3dfe80, 0x6bd4de73)
|
||||
TEST_MADDU(0x9f32e060, 0x3178e100, 0x44346000, 0x1ec3e8b7)
|
||||
TEST_MADDU(0xe9b87330, 0x372b4f78, 0x2311ce80, 0x325e2b48)
|
||||
TEST_MADDU(0x10483e78, 0xefa70d6a, 0x315df5b0, 0x0f3e124d)
|
||||
TEST_MADDU(0x6285d9a4, 0x48238818, 0x39978760, 0x1bc351e3)
|
||||
TEST_MADDU(0x8ee83024, 0x2a47e0d0, 0x88c29d40, 0x179a37ca)
|
||||
TEST_MADDU(0x4f1eb000, 0x22e9e3b4, 0x07a3c000, 0x0aca5cae)
|
||||
TEST_MADDU(0x57aea34c, 0x00000000, 0x00000000, 0x00000000)
|
||||
TEST_MADDU(0x04dbdd80, 0x00000000, 0x00000000, 0x00000000)
|
||||
TEST_MADDU(0x79d5a6b7, 0x00000000, 0x00000000, 0x00000000)
|
||||
TEST_MADDU(0x9ad90f8c, 0x00000000, 0x00000000, 0x00000000)
|
||||
TEST_MADDU(0x8237f918, 0x00000000, 0x00000000, 0x00000000)
|
||||
TEST_MADDU(0xc5ecadb0, 0x00000000, 0x00000000, 0x00000000)
|
||||
TEST_MADDU(0x00000000, 0xcec8f500, 0x00000000, 0x00000000)
|
||||
TEST_MADDU(0x00000000, 0x0fed823c, 0x00000000, 0x00000000)
|
||||
TEST_MADDU(0x00000000, 0x3ac7f7a0, 0x00000000, 0x00000000)
|
||||
TEST_MADDU(0x00000000, 0x04e4cfaa, 0x00000000, 0x00000000)
|
||||
TEST_MADDU(0x00000000, 0x00000000, 0x00000000, 0x00000000)
|
||||
|
||||
TEST_MADDU_HL(0x12471494, 0x379b6b90, 0x78df9403, 0x392aaef2, 0x7cd7f226, 0x785c1e32)
|
||||
TEST_MADDU_HL(0x3ef010c5, 0x2f8f1eae, 0x18770af3, 0x4d255c49, 0x24284dab, 0xbf52d82f)
|
||||
TEST_MADDU_HL(0x77e28abd, 0x4d0e7770, 0xabab929, 0x2c7b1271, 0x2ed0a336, 0x5d6ba021)
|
||||
TEST_MADDU_HL(0x8e92fd5, 0x74b77414, 0x58f4a911, 0x361e7d54, 0x5d04b579, 0x4745bdf8)
|
||||
TEST_MADDU_HL(0x1938de8f, 0x2fcdfcef, 0x3a17226c, 0x24c75b61, 0x3eccdebe, 0x2576e6e2)
|
||||
TEST_MADDU_HL(0x5c91e035, 0x4091b48d, 0x2817d7b7, 0x3792ce3d, 0x3f70ffae, 0x3958f6e)
|
||||
TEST_MADDU_HL(0x573f7e82, 0x4fed6eea, 0x404f0930, 0x20633813, 0x5b8c8ccf, 0x6522b6e7)
|
||||
TEST_MADDU_HL(0x537ce400, 0x163644aa, 0x4541154f, 0x27e902a8, 0x4c7f83a3, 0xdd686aa8)
|
||||
TEST_MADDU_HL(0x53eba1ab, 0xfb1d143, 0x53dcf5d6, 0x54f90b0, 0x59020ed3, 0x27327b71)
|
||||
TEST_MADDU_HL(0x54ec98ab, 0x1f72de78, 0x2e8f1c0e, 0x645eaad0, 0x38fdddb4, 0x10d084f8)
|
||||
TEST_MADDU_HL(0x64e7801c, 0x30a1c24e, 0x2e5d7df4, 0x50c6d1e3, 0x4188a827, 0x5001126b)
|
||||
TEST_MADDU_HL(0x1734f792, 0x187d1fdd, 0x3a3cab8d, 0x332f3d34, 0x3c74fa83, 0x382da43e)
|
||||
TEST_MADDU_HL(0x2202d172, 0x4f47beea, 0x18179d0b, 0x714d13a9, 0x22a003d2, 0xe3f121dd)
|
||||
TEST_MADDU_HL(0x4409b00c, 0x3375bc8d, 0x4213d30, 0x1b11828, 0x11ce75cc, 0x71cbdec4)
|
||||
TEST_MADDU_HL(0x7f1ebb87, 0x6cd177f7, 0x794fff0, 0x17c03916, 0x3d9dfab6, 0x14c9e957)
|
||||
TEST_MADDU_HL(0x5312265f, 0x2fe293e5, 0x3df07825, 0x6d7699f0, 0x4d7a5334, 0x799979eb)
|
||||
TEST_MADDU_HL(0x42858c2d, 0x398180c, 0x32656077, 0x5608d077, 0x335476a6, 0xbb279a93)
|
||||
TEST_MADDU_HL(0x726303f8, 0x29897956, 0x6bc6808, 0x35d3f0c9, 0x194bb0df, 0x47af7e19)
|
||||
TEST_MADDU_HL(0x67cae968, 0x626332ea, 0x54f99455, 0x10e95eb1, 0x7cdd79cb, 0xa53107c1)
|
||||
TEST_MADDU_HL(0x362afffe, 0x63ead9ec, 0x3bf55225, 0x566922fc, 0x5119a48e, 0xf1376f24)
|
||||
TEST_MADDU_HL(0x2f4cc800, 0x2f02ab39, 0xf927a1, 0x7c8f399f, 0x9a8be95, 0xde3fc19f)
|
||||
TEST_MADDU_HL(0x5e2d7f32, 0x6d2e702d, 0x184ea6c4, 0x2c0f1141, 0x40791b5d, 0xc6b04d0b)
|
||||
TEST_MADDU_HL(0x1af9ad13, 0x41addf35, 0x5b06075c, 0x49c6a4e0, 0x61f1be8d, 0x261206cf)
|
||||
TEST_MADDU_HL(0x7d54070f, 0xdf9030e, 0x36c49e47, 0x84a51d8, 0x3d9bcadc, 0x7f8ee1aa)
|
||||
TEST_MADDU_HL(0x6e969fa5, 0x64a25d41, 0x7a60238, 0x982d1f0, 0x331efc2e, 0x502a4bd5)
|
||||
TEST_MADDU_HL(0x63c92e9f, 0x14f2fb1, 0x3da5c978, 0x1d55b849, 0x3e287053, 0xd0f2538)
|
||||
TEST_MADDU_HL(0x22a7c873, 0x3e159587, 0x2d7da400, 0x27139ff7, 0x35e5328d, 0x60a8439c)
|
||||
TEST_MADDU_HL(0x32cd765e, 0x6580bcf8, 0x4a0760aa, 0x38d100aa, 0x5e2bfc98, 0x97c8b3ba)
|
||||
TEST_MADDU_HL(0x5a5eecdf, 0x26602a06, 0x5eb12341, 0x2081d6df, 0x6c3d2cd8, 0xbf37fa19)
|
||||
TEST_MADDU_HL(0x722bd92f, 0x3dfedef1, 0x646bfda8, 0x2af105bc, 0x80121b57, 0x5c313cfb)
|
||||
TEST_MADDU_HL(0x3c6d1d10, 0x4727c095, 0x11cf88b8, 0x6a7b283f, 0x229b2ddc, 0x4939128f)
|
||||
TEST_MADDU_HL(0x222ee50b, 0x38a2c266, 0x2562ca8e, 0x52666c0, 0x2cf2c84a, 0x865dff22)
|
||||
TEST_MADDU_HL(0x2d2b6408, 0x55061a6a, 0x673584df, 0x70bafdcb, 0x763600c3, 0x8d0b391b)
|
||||
TEST_MADDU_HL(0x13c5f68c, 0x17477da3, 0x1099d39d, 0x20d1a05f, 0x1266225f, 0x5613f783)
|
||||
TEST_MADDU_HL(0x7e14167e, 0x45cfb8e6, 0x60df292c, 0x227b24ed, 0x8340e089, 0xfe93ea21)
|
||||
TEST_MADDU_HL(0x358434c3, 0x5211bc64, 0x54ae6a01, 0x528b95a9, 0x65d67811, 0x47e265d5)
|
||||
TEST_MADDU_HL(0x6ccd0172, 0x426f80a6, 0x458b71a3, 0x38fd3c5, 0x61c7af93, 0x15a5c3b1)
|
||||
TEST_MADDU_HL(0x43a8d72a, 0x6c91404e, 0x7cfe1c95, 0x25020099, 0x99afbafb, 0x8f080f65)
|
||||
TEST_MADDU_HL(0x1bf9daeb, 0x7ee36dea, 0x70a573fd, 0x630aca9d, 0x7e83484d, 0x2003f46b)
|
||||
TEST_MADDU_HL(0x832cc93, 0x56e53456, 0x1fd1a8f, 0x68ded0dd, 0x4c58266, 0xdcfc663f)
|
||||
TEST_MADDU_HL(0x2034359f, 0x31b9e802, 0x68bedd10, 0x5023f5ab, 0x6f003e3e, 0x100b78e9)
|
||||
TEST_MADDU_HL(0x7fc21ad1, 0x151115d, 0x4dbd9b8e, 0x4f1e03ff, 0x4e65d2bd, 0xe98aa2ec)
|
||||
TEST_MADDU_HL(0x5e65cb18, 0x283a27db, 0x52cb975f, 0x6396cdec, 0x61a0f0dd, 0x6a0c3374)
|
||||
TEST_MADDU_HL(0x583786cf, 0xf1f0084, 0x6b70eee5, 0x7895807e, 0x70a6deb2, 0x6948033a)
|
||||
TEST_MADDU_HL(0x56b5fb8, 0x4e7ba185, 0x16eac59d, 0x6f9497d0, 0x18941ac9, 0xd4f80a68)
|
||||
TEST_MADDU_HL(0x4961ee1e, 0x4a1eb631, 0x198eded6, 0x7b90e68b, 0x2ecdfb5e, 0xba1cce49)
|
||||
TEST_MADDU_HL(0x5894328e, 0x75dd0b43, 0x2069cba8, 0x3bc64fb0, 0x49320298, 0x5351a4da)
|
||||
TEST_MADDU_HL(0x728b8d15, 0x5c4ab78b, 0x1aac3796, 0x49073512, 0x43f7ccc0, 0x90b8d279)
|
||||
TEST_MADDU_HL(0x28b6e197, 0x1e01ef43, 0x4ce12d8c, 0x42ed0346, 0x51a6eac0, 0x3afd06cb)
|
||||
TEST_MADDU_HL(0x3874288c, 0x122db66d, 0x33212911, 0x206fc0e6, 0x37236890, 0xb7548c82)
|
||||
TEST_MADDU_HL(0x120f8aec, 0x7b5abf8e, 0x3ee29ad6, 0x87cff8a, 0x4796798f, 0xe0ba2272)
|
||||
TEST_MADDU_HL(0x4a08faac, 0x62df3d6, 0x25cc7244, 0x27c8aca4, 0x2795f23c, 0xa9777c6c)
|
||||
TEST_MADDU_HL(0x4f74c4b, 0x3236eb26, 0x57a027d7, 0x1d9184a1, 0x58998577, 0x9b21b0c3)
|
||||
TEST_MADDU_HL(0x1264d6cf, 0x72e85402, 0x4e08deac, 0x7917b95d, 0x564a77c0, 0x8df552fb)
|
||||
TEST_MADDU_HL(0x7b700bb9, 0x43d37782, 0x6b86b521, 0x3263852c, 0x8c3aff2c, 0xb37781e)
|
||||
TEST_MADDU_HL(0x7fc49c47, 0x6bf6e60d, 0x1d5654ce, 0x787ffdaa, 0x5338bbdf, 0x731db745)
|
||||
TEST_MADDU_HL(0x727c1efd, 0x56629161, 0xec00a1d, 0x85e0f29, 0x3561d10d, 0x91cd1a06)
|
||||
TEST_MADDU_HL(0x1791cb08, 0x348db590, 0x6cb7d333, 0x54bc9437, 0x718e7c75, 0x1eb370b7)
|
||||
TEST_MADDU_HL(0x2a2de535, 0x7e449852, 0x48cfb6c6, 0x787ff654, 0x5d9d9ae0, 0x335ed94e)
|
||||
TEST_MADDU_HL(0x5b703fe, 0x23b6562d, 0xf73cd15, 0x7e056a8d, 0x103fe4aa, 0x8b1c7233)
|
||||
TEST_MADDU_HL(0x419372dd, 0x474636f0, 0x4b5b31f9, 0xe254444, 0x5d9d1338, 0x56099174)
|
||||
TEST_MADDU_HL(0x55590837, 0x714f617a, 0x6526c9f5, 0x25290fe7, 0x8aed8d8e, 0x5dacd11d)
|
||||
TEST_MADDU_HL(0x11d452d2, 0x5dc96306, 0x36f40328, 0x3dbd2330, 0x3d7c2bd9, 0x15a04a1c)
|
||||
TEST_MADDU_HL(0x64bdfb59, 0x2526dc27, 0x63f80739, 0x4389e817, 0x7296c763, 0xcb1aea6)
|
||||
TEST_MADDU_HL(0x73c7b598, 0x7d0e8612, 0xb1905b9, 0x19be878b, 0x43a81af2, 0xed26dc3b)
|
||||
TEST_MADDU_HL(0x70106dc8, 0x15e9c436, 0x5bfc723e, 0x3d564b2e, 0x65942017, 0xc7e2935e)
|
||||
TEST_MADDU_HL(0x2ffc1617, 0x1876039f, 0x64537768, 0x4f284c48, 0x68e9385a, 0x67964991)
|
||||
TEST_MADDU_HL(0x2387e16c, 0x602ab641, 0x958a59e, 0x10704785, 0x16b187bd, 0x2beb4bf1)
|
||||
TEST_MADDU_HL(0x1e8586bf, 0xa4d6eef, 0x2182206f, 0x40dc1c53, 0x22bc9316, 0x1cddfaa4)
|
||||
TEST_MADDU_HL(0x44fc51b9, 0x63a1962e, 0x2bf716be, 0x15df8c65, 0x46d03580, 0x4371a1a3)
|
||||
TEST_MADDU_HL(0x3fb7edba, 0x5fd69523, 0x248e8661, 0x14f87093, 0x3c693078, 0x97f73301)
|
||||
TEST_MADDU_HL(0x703af3cb, 0x2101828c, 0x4fb13065, 0x31f67ec9, 0x5e297348, 0xa0cbe7cd)
|
||||
TEST_MADDU_HL(0x755a3bd5, 0x2a76632b, 0x59f4d40a, 0x5412aa44, 0x6d6be6e8, 0x758c160b)
|
||||
TEST_MADDU_HL(0x586ac1a0, 0x386489b0, 0x23f6825e, 0x494270c4, 0x377095fa, 0xd6c62ec4)
|
||||
TEST_MADDU_HL(0x41a7f92f, 0x1c54ccd8, 0x6c70e33c, 0x45a42e24, 0x73b50224, 0x6d5be1cc)
|
||||
TEST_MADDU_HL(0x2be97eb, 0x6ddd2844, 0x5db2156a, 0x3b0870e1, 0x5edf9b10, 0xf244834d)
|
||||
TEST_MADDU_HL(0x7990b391, 0x42500c88, 0x68b7dfc, 0x7c9609c7, 0x2608cf73, 0x59303acf)
|
||||
TEST_MADDU_HL(0x3146b2c6, 0x1bcc90f0, 0x6d05d919, 0x20f06d30, 0x725fae30, 0x6f8f66d0)
|
||||
TEST_MADDU_HL(0x2ec0e51f, 0x4e8280d3, 0x1726e300, 0x50832916, 0x257d7e4b, 0x17cd81a3)
|
||||
TEST_MADDU_HL(0x38868439, 0x3a55de43, 0x3b70c619, 0x23e9b82c, 0x485235cb, 0x66b4c117)
|
||||
TEST_MADDU_HL(0xd433aa8, 0x52c57991, 0x1a8e335c, 0x2c91cedb, 0x1ed7f72e, 0x69a77003)
|
||||
TEST_MADDU_HL(0x489a374a, 0x605fb3de, 0x6dda7d35, 0x37753a1d, 0x892f762e, 0x464fea49)
|
||||
TEST_MADDU_HL(0x3f628b6c, 0x761bb04c, 0x708c911b, 0x28d7bc8c, 0x8dcad86a, 0x3657609c)
|
||||
TEST_MADDU_HL(0x423497e5, 0x37447a5c, 0x18439c51, 0x2754cf4f, 0x268e9e90, 0x8e72879b)
|
||||
TEST_MADDU_HL(0x41fca361, 0x125b6e14, 0x6bc59386, 0x7e80280f, 0x7080e831, 0x19eb99a3)
|
||||
TEST_MADDU_HL(0x63ba79fa, 0x209f18a3, 0x4b5eaa2e, 0x561f08cf, 0x5813f3d8, 0x539022fd)
|
||||
TEST_MADDU_HL(0x766e8ce0, 0x6aa4a286, 0x55ff1bd, 0x55506fe0, 0x36b5e214, 0x47d3ed20)
|
||||
TEST_MADDU_HL(0x5f8a7973, 0x2eb8856, 0x287eafaa, 0x5c24d924, 0x2995ab9c, 0x67bfbdc6)
|
||||
TEST_MADDU_HL(0x502b6eeb, 0xe96c1a4, 0x3f2dce4a, 0x657645ee, 0x43bf6472, 0x579a7f7a)
|
||||
TEST_MADDU_HL(0x1dc9c803, 0x26fab530, 0x628ac580, 0x2e463b4b, 0x6713e553, 0x3373dadb)
|
||||
TEST_MADDU_HL(0x5ea3b996, 0x443e2edb, 0x5de4209e, 0x33232e1b, 0x771e9ae3, 0x5edfe56d)
|
||||
TEST_MADDU_HL(0x2e827fcb, 0x349e83c3, 0x643d3f7f, 0x2fb68e18, 0x6dcc8def, 0x7fccc6b9)
|
||||
TEST_MADDU_HL(0x1700168f, 0x742fac6, 0x78b09b15, 0x2619824b, 0x7957a040, 0xc0109ae5)
|
||||
TEST_MADDU_HL(0x32aba435, 0x2500245a, 0x3cfc8389, 0x593c2e07, 0x444f5976, 0xf5ab5ca9)
|
||||
TEST_MADDU_HL(0x9582e69, 0x5af34557, 0xda02fc5, 0x87f0bee, 0x10f21151, 0xf1a41e9d)
|
||||
TEST_MADDU_HL(0x416b8be0, 0x70358eb, 0x2a096b00, 0x2ab2b7f1, 0x2bd436ce, 0xf4211e91)
|
||||
TEST_MADDU_HL(0xec4333c, 0x20190b40, 0xadd6d5e, 0x7ae04bb, 0xcb76594, 0xa7ca67bb)
|
||||
TEST_MADDU_HL(0xe7ed76, 0x3b08e3f3, 0x327b073, 0xdd87b91, 0x35d2c3b, 0x2f3e8493)
|
||||
TEST_MADDU_HL(0x7d5c8736, 0x3124c2ec, 0x569e03b3, 0x66c7adf2, 0x6eaeba0b, 0x70233fba)
|
||||
TEST_MADDU_HL(0x3f7a2a21, 0x6857f494, 0x293edd6d, 0x1db19b2, 0x431e4db3, 0xddd9e8c6)
|
||||
|
||||
###detect exception
|
||||
bne s2, zero, inst_error
|
||||
nop
|
||||
###score ++
|
||||
addiu s3, s3, 1
|
||||
###output (s0<<24)|s3
|
||||
inst_error:
|
||||
sll t1, s0, 24
|
||||
or t0, t1, s3
|
||||
sw t0, 0(s1)
|
||||
jr ra
|
||||
nop
|
||||
END(n96_maddu_test)
|
||||
224
resources/2021/soft/func/inst/n97_msub.S
Normal file
224
resources/2021/soft/func/inst/n97_msub.S
Normal file
@ -0,0 +1,224 @@
|
||||
#include <asm.h>
|
||||
#include <regdef.h>
|
||||
#include <inst_test.h>
|
||||
|
||||
LEAF(n97_msub_msubu_test)
|
||||
.set noreorder
|
||||
addiu s0, s0 ,1
|
||||
li s2, 0x0
|
||||
###test inst
|
||||
TEST_MSUB_HL(0x653ad29b, 0x76d69606, 0x5b51b550, 0x52f1d93e, 0x2c53bdbd, 0xfc98179c)
|
||||
TEST_MSUB_HL(0x3987c8e8, 0x66c6efd3, 0x59ceb551, 0x7a864962, 0x42b5e65a, 0x779b1a2a)
|
||||
TEST_MSUB_HL(0x14f0afe7, 0x7926ed46, 0x568b2f1f, 0x3c78e0a9, 0x4ca23cd8, 0x6485ec7f)
|
||||
TEST_MSUB_HL(0x4984d062, 0x5931b20e, 0x11606a6c, 0x7111bde6, 0xf7c2f86c, 0x1e28348a)
|
||||
TEST_MSUB_HL(0x50f6207e, 0x6a5c6e62, 0x64672756, 0x5a596e84, 0x42c40285, 0xc0e2da48)
|
||||
TEST_MSUB_HL(0xfda3c90, 0x76279850, 0x79cdf16c, 0x767db788, 0x727ce5d4, 0x54654a88)
|
||||
TEST_MSUB_HL(0xdb09d5a, 0x2ac7bcf5, 0x7a9451f9, 0x78c8a150, 0x784aa9c3, 0x963df22e)
|
||||
TEST_MSUB_HL(0x728e6edb, 0x76807fba, 0x3adace5c, 0x6ecab994, 0x5d3a6e4, 0x2acf8976)
|
||||
TEST_MSUB_HL(0x99e9252, 0x148751eb, 0x4a3a802a, 0x67d355be, 0x49750708, 0xd5b91278)
|
||||
TEST_MSUB_HL(0x6224e178, 0x5586312e, 0x303e4c81, 0x443dd148, 0xf749b7b, 0xb5a555b8)
|
||||
TEST_MSUB_HL(0x7a6baf0e, 0x8e87ba3, 0x5a071dee, 0x2b3b571d, 0x55c493bf, 0x66df2733)
|
||||
TEST_MSUB_HL(0xc256d9a, 0x5738e5a0, 0x2ce6e069, 0x47819e95, 0x28c37514, 0xe5625c55)
|
||||
TEST_MSUB_HL(0x39cac749, 0x634a9310, 0x526e5452, 0x10d6e2dc, 0x3c041370, 0x2da1834c)
|
||||
TEST_MSUB_HL(0x5d3389cf, 0x6a34e320, 0x589ca9d8, 0x3a5ab22f, 0x31f211a0, 0x2caaeb4f)
|
||||
TEST_MSUB_HL(0x75c59150, 0x6214f602, 0x78496e33, 0x41923aa7, 0x4b2a27f6, 0x82243807)
|
||||
TEST_MSUB_HL(0x56eddf, 0x66227f6d, 0x1ab8ec52, 0x5bdbac93, 0x1a963dd4, 0xa538c3a0)
|
||||
TEST_MSUB_HL(0x50fb7a05, 0x5e615275, 0x6e464e5, 0x232e7fc7, 0xe90944b8, 0x8145217e)
|
||||
TEST_MSUB_HL(0xf93166b, 0x5ba0258e, 0x42a9f4cf, 0x1822b6a6, 0x3d16eda0, 0x266ed04c)
|
||||
TEST_MSUB_HL(0x4a179c16, 0xe04c7e1, 0x104509d, 0x517abd82, 0xfcf5a3dc, 0x340d742c)
|
||||
TEST_MSUB_HL(0x4b7085c5, 0x3f6dac3a, 0x55d95ff7, 0x58d2b049, 0x43285d62, 0x379305a7)
|
||||
TEST_MSUB_HL(0xaa0737d, 0xd1ccee, 0xd1821db, 0x26682a2b, 0xd0f6c5b, 0x20282ff5)
|
||||
TEST_MSUB_HL(0x5e79fdc2, 0x585a72bc, 0x4519fc38, 0x233464ca, 0x247eabc2, 0x8869a652)
|
||||
TEST_MSUB_HL(0x7a163fc0, 0x318dab3c, 0x10e7f9e9, 0x22abeda6, 0xf94627ca, 0xcc1fbca6)
|
||||
TEST_MSUB_HL(0x38f77743, 0xa993245, 0x393419ea, 0x20eef786, 0x36d8582b, 0x8be5bc77)
|
||||
TEST_MSUB_HL(0x40e3b1dc, 0x46c2107f, 0xea90ada, 0x5dcbe66e, 0xfcb9977d, 0x100ea4a)
|
||||
TEST_MSUB_HL(0x2083372e, 0x540e61d0, 0x219bafdf, 0x1e220360, 0x16eece2a, 0xdf18c000)
|
||||
TEST_MSUB_HL(0x10dc9660, 0x1a9ebbe2, 0x2029d751, 0x70394df6, 0x1e68fb86, 0xdc646d36)
|
||||
TEST_MSUB_HL(0x3f2bab7a, 0x2189e5ca, 0xfdf7cdf, 0x1da7c42, 0x798d4b1, 0x9ab70bfe)
|
||||
TEST_MSUB_HL(0x132b903, 0x31b31493, 0x333751c8, 0x7f6484af, 0x32fbc5ce, 0xe8b70bf6)
|
||||
TEST_MSUB_HL(0x2ea407c2, 0x6039ca33, 0x431238b7, 0x76df3194, 0x318a2e72, 0x43e091ee)
|
||||
TEST_MSUB_HL(0x266735f5, 0x15810e2f, 0x65a013b6, 0x193493d8, 0x62664026, 0x1dd945dd)
|
||||
TEST_MSUB_HL(0x3ebf076b, 0x3df77bc6, 0x2bfbe446, 0x54ff7411, 0x1ccbb6db, 0x5d724e4f)
|
||||
TEST_MSUB_HL(0x379f61f8, 0x3045bae1, 0x3ee8bffb, 0x787a637c, 0x346bb70c, 0xe05f1884)
|
||||
TEST_MSUB_HL(0x13a6cc29, 0x724e1160, 0x794b93ed, 0x77b0d737, 0x70854edb, 0x8f178ed7)
|
||||
TEST_MSUB_HL(0x517e6dc8, 0x3588e50f, 0x70295555, 0x5e03fbe5, 0x5f1e9485, 0xc527a52d)
|
||||
TEST_MSUB_HL(0x35e24b2b, 0x4a799cce, 0x268a9b78, 0x227c4d9a, 0x16dd98c6, 0xeb429d00)
|
||||
TEST_MSUB_HL(0x5d6e4b1, 0x5750659b, 0x60bac54f, 0x102f1dee, 0x5ebce81e, 0x2088d1c3)
|
||||
TEST_MSUB_HL(0x5eb9b65a, 0x71be78da, 0x1289b0e1, 0x710205f1, 0xe8733cd6, 0xa8968d4d)
|
||||
TEST_MSUB_HL(0x205ac6e5, 0x12b5fef9, 0x451989ec, 0x842c49d, 0x42bc2787, 0xc4b719e0)
|
||||
TEST_MSUB_HL(0x6ac18ba0, 0x3b5abbbe, 0x57ccb937, 0x5f5cc852, 0x3f0c47b3, 0xcc794792)
|
||||
TEST_MSUB_HL(0x3a36817e, 0x22597664, 0x2c8aac8c, 0x78ffa473, 0x24bb177a, 0xdb36fb3b)
|
||||
TEST_MSUB_HL(0x94b1c2b, 0x3b3ea0bf, 0x12a7cd47, 0xf30dadb, 0x108137c2, 0x7321f6c6)
|
||||
TEST_MSUB_HL(0x56875266, 0x175c77f2, 0x198804be, 0x2f1717b8, 0x11a29b2a, 0xb535c94c)
|
||||
TEST_MSUB_HL(0x2702cb64, 0xbb5890e, 0x42108d7d, 0x2fadba9d, 0x4047c4e3, 0x74fa1725)
|
||||
TEST_MSUB_HL(0x3874fcbf, 0x7d835901, 0x6efed5c6, 0x3fe383ec, 0x5350bede, 0xc2d3202d)
|
||||
TEST_MSUB_HL(0x7eab14ba, 0x4ca58c1c, 0x17411ed4, 0x1b9f93a1, 0xf1546b15, 0x1db19749)
|
||||
TEST_MSUB_HL(0x4fecfc46, 0x2da1f64, 0x38fdf5dc, 0x769d96ee, 0x381a0248, 0x2be29196)
|
||||
TEST_MSUB_HL(0x5d5c942a, 0x58e756b6, 0x4929959e, 0x778d7b31, 0x28bd6486, 0xdc100955)
|
||||
TEST_MSUB_HL(0xe7f0a4f, 0x5a105b19, 0x6ea8d02b, 0x447f4f13, 0x698f3972, 0x467d385c)
|
||||
TEST_MSUB_HL(0x11a03f16, 0x257a6bcb, 0x2751e1a2, 0x6ed73676, 0x24bd4aba, 0x3beafe04)
|
||||
TEST_MSUB_HL(0x55a90dfa, 0x4c02effd, 0x5f21c632, 0x3aa3e07b, 0x45b29a6c, 0x6a90aa69)
|
||||
TEST_MSUB_HL(0x1acb778, 0x5ea82ac5, 0x6bd190d4, 0x2b77e448, 0x6b330bd6, 0x14b504f0)
|
||||
TEST_MSUB_HL(0x4751f808, 0x648f4128, 0x559f2d46, 0x1c3d4f8d, 0x399b3f72, 0x7afc864d)
|
||||
TEST_MSUB_HL(0x615bb121, 0x4fbf8adb, 0x14100a0d, 0x495197af, 0xf5bbe62c, 0x3bc64674)
|
||||
TEST_MSUB_HL(0x1c1f4bba, 0x78351f3c, 0x403701a3, 0x77fe7efa, 0x3302803b, 0x38fb3962)
|
||||
TEST_MSUB_HL(0x79bbf352, 0x75447a98, 0x71880850, 0x668b8ac6, 0x39c491e3, 0x7135fe16)
|
||||
TEST_MSUB_HL(0x5acfbaf1, 0x3e4e5927, 0x799a678, 0x2994acad, 0xf17f8c46, 0xc88368f6)
|
||||
TEST_MSUB_HL(0xbc49373, 0x486dc63, 0xf151e23, 0x812fba8, 0xedfd8ce, 0x9225222f)
|
||||
TEST_MSUB_HL(0x65308927, 0x3ee9bbb, 0x3e373e5b, 0x4bcd1e4a, 0x3ca95c12, 0x70c51cd)
|
||||
TEST_MSUB_HL(0x3f71a8a1, 0x42736c2, 0x6c599e03, 0xdaf4590, 0x6b521f7d, 0xcb74858e)
|
||||
TEST_MSUB_HL(0x5289ee2f, 0x383464a7, 0x76df1e4a, 0x636ae025, 0x64c00db8, 0xda237c)
|
||||
TEST_MSUB_HL(0x425f8b2d, 0x3a578387, 0x203f4da5, 0x42fec3ec, 0x111ef78a, 0xe0195831)
|
||||
TEST_MSUB_HL(0x6faadcab, 0x6e45ca23, 0x33ec63a, 0x227836a3, 0xd324ea2f, 0x17e61d42)
|
||||
TEST_MSUB_HL(0x6831ece9, 0x7b34c54c, 0x43852e7a, 0x75ffcf9b, 0x115fb735, 0x98a2d6f)
|
||||
TEST_MSUB_HL(0x61ce863f, 0x366c2195, 0x648a151, 0x520cc94, 0xf17dc10a, 0x8c0a8ae9)
|
||||
TEST_MSUB_HL(0x55e8b3f1, 0x7ea15962, 0x7357c60a, 0x2aaa6c8d, 0x48d91821, 0x9875c14b)
|
||||
TEST_MSUB_HL(0x43f4295, 0x50bbf92e, 0x27756bcc, 0x1a733a06, 0x261e88a5, 0x9c7b5640)
|
||||
TEST_MSUB_HL(0x1c960182, 0x26dc410c, 0x694482fb, 0xfb8544b, 0x64eda695, 0xa964033)
|
||||
TEST_MSUB_HL(0x2b4971f0, 0x149db311, 0x59ddf03b, 0x218d37af, 0x56618902, 0x46d1d6bf)
|
||||
TEST_MSUB_HL(0x3b0a871f, 0x349f63af, 0x5704d894, 0x7a60c78, 0x4ae1f29a, 0x60f1b147)
|
||||
TEST_MSUB_HL(0x644bbdb6, 0x21622dea, 0x1fd20c13, 0x1b2375b3, 0x12bdd1a3, 0x7e30f57)
|
||||
TEST_MSUB_HL(0x44a3b8d2, 0x65075d53, 0x5d4be302, 0x268c2fcc, 0x42355197, 0x8394f9b6)
|
||||
TEST_MSUB_HL(0x15b56e80, 0x52d7302c, 0x2a512948, 0x205dc36f, 0x234acc6d, 0x92f6c56f)
|
||||
TEST_MSUB_HL(0x3cfc3229, 0x6edcfb63, 0x134d198, 0x5456c5d6, 0xe6cbcf6c, 0xc0652cfb)
|
||||
TEST_MSUB_HL(0x57c37528, 0x45594144, 0x1bd3706b, 0x60408149, 0x40d2883, 0xecae3aa9)
|
||||
TEST_MSUB_HL(0x1e3ff749, 0x176f6a52, 0x67df7b55, 0x5a8e5abd, 0x651a91d1, 0x6605eb5b)
|
||||
TEST_MSUB_HL(0x6fcfff73, 0x72c4e565, 0x1234ccab, 0x8f9f091, 0xe0142d79, 0x125c4932)
|
||||
TEST_MSUB_HL(0x796fcd66, 0x6b2ac2e2, 0x6972c893, 0x7568ed6a, 0x369cc4f0, 0x32524d5e)
|
||||
TEST_MSUB_HL(0x4624f99d, 0x5c99a05c, 0x74e0f718, 0x5893c0e5, 0x5b81955a, 0x6c72ec79)
|
||||
TEST_MSUB_HL(0x20527488, 0x27d29c11, 0x40f554fa, 0x2556d4d7, 0x3bee2de1, 0x714a37cf)
|
||||
TEST_MSUB_HL(0x40183803, 0x1b6730aa, 0x481e2f1e, 0x2134cb82, 0x4141cb48, 0x2c6a0984)
|
||||
TEST_MSUB_HL(0x13a6f2d8, 0x72906018, 0x33826fda, 0x113fb8f4, 0x2ab7026c, 0xd507f4b4)
|
||||
TEST_MSUB_HL(0x1bf51ef, 0x1fd42fa0, 0xd76f6b0, 0x6028135, 0xd3f5901, 0x3786ad5)
|
||||
TEST_MSUB_HL(0x7bf4113b, 0x434441f8, 0x2dc09077, 0x2a65f8ce, 0xd2ea32f, 0x18e94ca6)
|
||||
TEST_MSUB_HL(0x592614c8, 0x137fd912, 0x53371898, 0x2ef22783, 0x4c6cbf91, 0x7b6f2973)
|
||||
TEST_MSUB_HL(0x53f095ba, 0x517883fa, 0x62fc7b4f, 0x38814c85, 0x4845d7e3, 0x19c0e6e1)
|
||||
TEST_MSUB_HL(0x5e2bb3a9, 0x4dc7194c, 0x58f65813, 0x40aad98d, 0x3c59f5c2, 0x89c70261)
|
||||
TEST_MSUB_HL(0x2205800a, 0x345e5465, 0x55b3823c, 0x1e0d918c, 0x4ebddafd, 0xd832c59a)
|
||||
TEST_MSUB_HL(0x166854c3, 0x6fab94d9, 0x7546f3b0, 0x7616ed31, 0x6b80b237, 0xfb6557e6)
|
||||
TEST_MSUB_HL(0x57f627a, 0x12505315, 0x5c2192a1, 0x5ccc386c, 0x5bbce41d, 0x424b966a)
|
||||
TEST_MSUB_HL(0x24b0cae1, 0x379092cc, 0x15c677c0, 0x763f7c39, 0xdcfc3ad, 0xf0197eed)
|
||||
TEST_MSUB_HL(0x5f5dff14, 0xd8d5906, 0x40982019, 0x125ed2bc, 0x3b8bb235, 0xa678e444)
|
||||
TEST_MSUB_HL(0x5465f427, 0x46661c55, 0x48551eb2, 0x5d2c9294, 0x311f93f9, 0x3f143da1)
|
||||
TEST_MSUB_HL(0x252f972e, 0x657c73a9, 0x7c50ca0, 0x5a086a41, 0xf9073221, 0xc6bf2e3)
|
||||
TEST_MSUB_HL(0x2cdf19d4, 0x4bbc33c5, 0x3a0bfe68, 0x595c77b4, 0x2cc5a4ed, 0x4bd85b90)
|
||||
TEST_MSUB_HL(0x38c447b3, 0x79221c10, 0x19202fa0, 0x7f70e60a, 0xfe43d972, 0x5a8ed6da)
|
||||
TEST_MSUB_HL(0x66312aca, 0x219006e8, 0x2b5667ca, 0x3697403c, 0x1df092dc, 0x5767bd2c)
|
||||
TEST_MSUB_HL(0x11c2e197, 0x1180b6e3, 0x3c8638aa, 0x1ac1d8a8, 0x3b4f598d, 0xfc1275c3)
|
||||
TEST_MSUB_HL(0x5d5604b2, 0x71ca081f, 0x22110abe, 0x6b678ad1, 0xf89469d6, 0x27636943)
|
||||
TEST_MSUB_HL(0x16ec7337, 0x13fa64bb, 0x6b43a44b, 0x25ea90c3, 0x6979abd0, 0x717aeb96)
|
||||
|
||||
TEST_MSUBU_HL(0x28b7857, 0x52f377bb, 0x52a991ac, 0x31edc0a, 0x51d6798c, 0x39b8837d)
|
||||
TEST_MSUBU_HL(0x2585bac6, 0x2ae1664c, 0x5744da28, 0x34554896, 0x50fbdffc, 0x2430f1ce)
|
||||
TEST_MSUBU_HL(0x2f502115, 0x58b32ea9, 0x293d200e, 0xbb23f14, 0x18d87708, 0x102ba237)
|
||||
TEST_MSUBU_HL(0x30cd1df9, 0x530bb814, 0x2556f4f, 0x637a5774, 0xf280b2b0, 0x21360800)
|
||||
TEST_MSUBU_HL(0x3ce24838, 0xb3e1428, 0x3953ce99, 0x339e4b63, 0x36a751e6, 0x1d0ea2a3)
|
||||
TEST_MSUBU_HL(0x37e2e8ba, 0x698bdc10, 0x2a61e22b, 0x791c24c, 0x13574877, 0xe2655eac)
|
||||
TEST_MSUBU_HL(0x43b0ca6f, 0x49f08ea, 0x67dfb494, 0x72b03402, 0x66a6e441, 0x95d2b28c)
|
||||
TEST_MSUBU_HL(0x1481d106, 0x5ca3ce47, 0x5c87fa3, 0x6faa9c52, 0xfe5cb957, 0xaa4cfa8)
|
||||
TEST_MSUBU_HL(0x694ff0f, 0x68c0e153, 0x3cf3217b, 0x4dccb382, 0x3a41a452, 0xd411d2a5)
|
||||
TEST_MSUBU_HL(0x31296ac0, 0xad383b0, 0x52638767, 0x49a447fa, 0x504f4ace, 0xcf4aa3fa)
|
||||
TEST_MSUBU_HL(0x2ede55a4, 0x13c5f6bf, 0xca12569, 0x49215ccc, 0x90266c9, 0x97bfdf70)
|
||||
TEST_MSUBU_HL(0x4f7331f2, 0x56a0250b, 0x2877adeb, 0x785f1406, 0xd9547a5, 0xe4f3f4a0)
|
||||
TEST_MSUBU_HL(0x5aad27f5, 0x155a6eaa, 0x12fc0f7c, 0x27850adb, 0xb6bd322, 0x643b3c29)
|
||||
TEST_MSUBU_HL(0x101d8532, 0x67aa7390, 0x65a5462d, 0x17503521, 0x5f1eaab5, 0x32abd301)
|
||||
TEST_MSUBU_HL(0x4b7389ca, 0x78a8d914, 0x27d25cd6, 0x20c36e74, 0x4427072, 0x2f6070ac)
|
||||
TEST_MSUBU_HL(0x47975c65, 0x5ca693b1, 0xc7a7f91, 0x7ed53914, 0xf29184e9, 0xdfa2583f)
|
||||
TEST_MSUBU_HL(0x494ac7c6, 0x41f22d66, 0x63d80c75, 0x25b43642, 0x50f6ba0b, 0xad9ecf5e)
|
||||
TEST_MSUBU_HL(0x2662a7e8, 0x30737970, 0x6c876ff3, 0x6f134511, 0x65439ff1, 0x15552791)
|
||||
TEST_MSUBU_HL(0x73bbea04, 0x4a30ae51, 0x7420108b, 0x7898d2f6, 0x5295bcdc, 0x18550fb2)
|
||||
TEST_MSUBU_HL(0x4d165b1c, 0x78b35570, 0x34597457, 0x525f6854, 0x1000f946, 0x57c34014)
|
||||
TEST_MSUBU_HL(0x553f8cfc, 0x715342e4, 0x6690c118, 0x73b6df54, 0x40d3f9fc, 0x331056e4)
|
||||
TEST_MSUBU_HL(0x5fb68b1, 0x165e92e9, 0xa1c8809, 0x50fb43de, 0x996b74a, 0xd67608c5)
|
||||
TEST_MSUBU_HL(0x1d1d543a, 0x190811e5, 0x66efe18, 0x37534535, 0x39635ea, 0xedaf1353)
|
||||
TEST_MSUBU_HL(0x4612e9db, 0x5817bf5e, 0x417bb9d8, 0x674a2ab1, 0x295eb960, 0x4530e747)
|
||||
TEST_MSUBU_HL(0x53e4b754, 0x1d2df28e, 0x3d57f031, 0x6e85dafd, 0x33c7f8bb, 0xf296c265)
|
||||
TEST_MSUBU_HL(0x1aeb4bef, 0x21b688e6, 0x4f043d51, 0x6ecd9fcb, 0x4b78b6da, 0x74266f11)
|
||||
TEST_MSUBU_HL(0x749da6f6, 0x1aff9b1d, 0x6142dc5e, 0x11e93b20, 0x54f669b7, 0x1cec5f42)
|
||||
TEST_MSUBU_HL(0x55e1fc1e, 0x29d20b07, 0x56a77b52, 0x1b84f268, 0x489fd2dd, 0x6de5c396)
|
||||
TEST_MSUBU_HL(0x262c9b3b, 0x37976ba7, 0x7fa8b2a8, 0x501a70f7, 0x775e88f1, 0x8752847a)
|
||||
TEST_MSUBU_HL(0x63bb0f2b, 0x1ee7247d, 0x45a835ab, 0xe2d54b7, 0x399e3de2, 0x53e7e0b8)
|
||||
TEST_MSUBU_HL(0x16d1fd8a, 0x42369890, 0x204a8799, 0x1b3337f7, 0x1a638656, 0x876eaa57)
|
||||
TEST_MSUBU_HL(0x479e1972, 0x2478d13c, 0x2c20b4b8, 0xe94fcc1, 0x21ecac7f, 0x3d50f409)
|
||||
TEST_MSUBU_HL(0x4dbc15e, 0x6d6785ab, 0x43627f55, 0x4efd668a, 0x414ef70c, 0x11eb66c0)
|
||||
TEST_MSUBU_HL(0x40bbea98, 0x558ff351, 0x49eaeb6, 0x51bbc6ca, 0xeefbe352, 0xf3b044b2)
|
||||
TEST_MSUBU_HL(0x6093c95e, 0xfb26b7b, 0x61b878bc, 0xb91bae6, 0x5bcc80a1, 0x5a09b0bc)
|
||||
TEST_MSUBU_HL(0x5b84b5bf, 0x6d83a2ab, 0x56ec9216, 0x1689f468, 0x2fc601a3, 0xa624afd3)
|
||||
TEST_MSUBU_HL(0x77f277b2, 0x2001e76e, 0x420ee536, 0x7053591c, 0x330fb1de, 0x64704ca0)
|
||||
TEST_MSUBU_HL(0x5be01c4d, 0x35e94d15, 0x78d2e147, 0x4fb8ea0f, 0x6579c0c7, 0xaabe6ebe)
|
||||
TEST_MSUBU_HL(0x40ade265, 0x3450bcea, 0x638442d8, 0x4bf8dac7, 0x564c8aca, 0x3735be75)
|
||||
TEST_MSUBU_HL(0x7e7612ae, 0x4bbd6867, 0x9708fe9, 0x53b6f351, 0xe40667b1, 0xb628bf4f)
|
||||
TEST_MSUBU_HL(0x535f3e12, 0x24fd0e6f, 0x46db5761, 0x70d01442, 0x3acf88d3, 0x35552e74)
|
||||
TEST_MSUBU_HL(0x5073607b, 0x29f332db, 0x44b26968, 0x59818ebe, 0x37838174, 0xb634ff85)
|
||||
TEST_MSUBU_HL(0x1cfe5f95, 0x5600ecd8, 0x1d0fc957, 0x29a84554, 0x13523a68, 0x24ea439c)
|
||||
TEST_MSUBU_HL(0x49550a0, 0x7585ca4d, 0x5fc49005, 0x21ba4f9b, 0x5da9ecf9, 0xec12cf7b)
|
||||
TEST_MSUBU_HL(0x42ecbb32, 0x35246354, 0x1c20f365, 0x709d95c9, 0xe3c6d62, 0x4183d361)
|
||||
TEST_MSUBU_HL(0x7419d2df, 0x6a2867a0, 0x54e2c189, 0x37282dcc, 0x24bdbd30, 0xfa54a96c)
|
||||
TEST_MSUBU_HL(0x42be9054, 0x2fe65d14, 0x4ff1ccd2, 0x285b7d63, 0x4374c0d8, 0x9f91b2d3)
|
||||
TEST_MSUBU_HL(0x69ec6de, 0x5aebb8ea, 0x187743c5, 0x5c5cc5e4, 0x161d5952, 0x96816ef8)
|
||||
TEST_MSUBU_HL(0x55714c25, 0x164da192, 0x7dc3daf, 0x62bf12fe, 0x6a9823, 0x521d60e4)
|
||||
TEST_MSUBU_HL(0x3b4d004, 0x7f965c65, 0x5b757356, 0x3929ae0f, 0x599c92db, 0xe9ba2c7b)
|
||||
TEST_MSUBU_HL(0x73b69969, 0x3f674145, 0x1fe59b, 0x363c3f50, 0xe37749e2, 0x18d23d03)
|
||||
TEST_MSUBU_HL(0x6952f8be, 0x64c6a94c, 0x1f4b8c08, 0x4492c689, 0xf5d5670a, 0x9ec78021)
|
||||
TEST_MSUBU_HL(0x7c1736a7, 0x7ea12910, 0x69aa106d, 0xd853ec4, 0x2c488506, 0x34a1554)
|
||||
TEST_MSUBU_HL(0x336780bb, 0x4a5100f3, 0x6af27e2f, 0x758a1f38, 0x5c064f08, 0xe11fedb7)
|
||||
TEST_MSUBU_HL(0x8f55942, 0x72e552ac, 0x323e6d31, 0x7ecb9d70, 0x2e392514, 0xa7528118)
|
||||
TEST_MSUBU_HL(0x4e976289, 0x7764454c, 0x20a328f9, 0x252093f6, 0xfbfc01c2, 0xd61c664a)
|
||||
TEST_MSUBU_HL(0x55f2c459, 0xc618770, 0x76103e7d, 0x2ec2236a, 0x71e81ed3, 0xfd484d7a)
|
||||
TEST_MSUBU_HL(0x51f1896, 0x1d3493fe, 0x6a663, 0x93c35ec, 0xff711353, 0x1ccbaf18)
|
||||
TEST_MSUBU_HL(0x7385e4e, 0x1584473d, 0x6e2aea62, 0x7ca832eb, 0x6d8f8f93, 0x1bda1855)
|
||||
TEST_MSUBU_HL(0x4ebc2913, 0x794f5344, 0x38a5ac13, 0x2cc2d6ab, 0x135656fc, 0x9999c49f)
|
||||
TEST_MSUBU_HL(0x7430b8f3, 0x1a0cc11d, 0x2c2e31cb, 0x61c8824d, 0x205b7514, 0x23705bc6)
|
||||
TEST_MSUBU_HL(0x3c8dbcc5, 0x2006f3e9, 0x656989df, 0x4781742a, 0x5dd62d42, 0x93b3a5dd)
|
||||
TEST_MSUBU_HL(0x9cc1464, 0x6d7ec0d7, 0x5a005521, 0x158c64bc, 0x55cf969f, 0x2ea444c0)
|
||||
TEST_MSUBU_HL(0x26719f24, 0x275e4d4b, 0x37c91d3e, 0x4d8faf3b, 0x31dfa4ab, 0xf2303baf)
|
||||
TEST_MSUBU_HL(0x4062b346, 0x47d4d9ad, 0x4d77e855, 0x1af6e384, 0x3b670021, 0xe556736)
|
||||
TEST_MSUBU_HL(0x297c10d3, 0x6d7280b1, 0x21521197, 0x2d43583a, 0xf95b053, 0x211c3657)
|
||||
TEST_MSUBU_HL(0x7699f96c, 0x39da7124, 0x6a039deb, 0x6d31c72a, 0x4f3621d9, 0x567a07fa)
|
||||
TEST_MSUBU_HL(0x3f9a4c4c, 0x5866787c, 0x4c4b54ab, 0x5600349d, 0x3654d507, 0xad379fcd)
|
||||
TEST_MSUBU_HL(0x1f7d63a5, 0x3ce50e0d, 0x256d3bdd, 0x1032f3d0, 0x1defab9d, 0xccc8de6f)
|
||||
TEST_MSUBU_HL(0x437fdd49, 0x16596290, 0x6beb0007, 0x4ae3de52, 0x66067192, 0x2be07342)
|
||||
TEST_MSUBU_HL(0x7c720e04, 0x61240393, 0x195157f1, 0x355f997b, 0xea189eda, 0xed27812f)
|
||||
TEST_MSUBU_HL(0x2f907235, 0xcbb380d, 0x2ae26f1f, 0x6979c49f, 0x2884e0d7, 0x7d715fee)
|
||||
TEST_MSUBU_HL(0x73551bdc, 0x6286df46, 0xfe501e0, 0x78c1e65a, 0xe381aa12, 0xff0fa432)
|
||||
TEST_MSUBU_HL(0x3a9535c8, 0x446b3c37, 0x4a48c3f9, 0x67dd08cb, 0x3aa0978b, 0x3e9b9ad3)
|
||||
TEST_MSUBU_HL(0x26bc9209, 0x527ada3d, 0x4fcd71cc, 0x51966f4b, 0x43527422, 0x801f926)
|
||||
TEST_MSUBU_HL(0x2150d558, 0x1b72c5fe, 0x346614bc, 0x69a059f4, 0x30d39e78, 0xde0ff4a4)
|
||||
TEST_MSUBU_HL(0x6790345d, 0x5ec02e34, 0x56dc9ef9, 0x1456f285, 0x3087ece6, 0xb5e399a1)
|
||||
TEST_MSUBU_HL(0x15c8f2cb, 0x61d121ea, 0x3cc9159a, 0x60691d20, 0x347625aa, 0x6cb40492)
|
||||
TEST_MSUBU_HL(0x11993bc2, 0x3a717e85, 0x1f3a8844, 0x647aebb2, 0x1b360364, 0x7fd363e8)
|
||||
TEST_MSUBU_HL(0x78c45017, 0x1a0af228, 0x76a21125, 0x31a6c3cb, 0x6a58f71b, 0x485e8233)
|
||||
TEST_MSUBU_HL(0x1ecafa6c, 0x26e76f1f, 0x3410cc4d, 0xfe1ba4f, 0x2f62d49b, 0x5344933b)
|
||||
TEST_MSUBU_HL(0x35cc774f, 0x102bec26, 0x75731285, 0x55494f0e, 0x720d1017, 0xe0adc554)
|
||||
TEST_MSUBU_HL(0x3230f978, 0x3fe1f00b, 0x6da0e757, 0x3086b7c3, 0x611a8dd7, 0x54137f9b)
|
||||
TEST_MSUBU_HL(0x6e01f0ae, 0x773bd5fa, 0x59dfb011, 0x188c696, 0x26a312ca, 0x9c48f6aa)
|
||||
TEST_MSUBU_HL(0x4db41462, 0x4bc9366b, 0x6306e7a8, 0x4eb9d15c, 0x4c0612c7, 0x2136a066)
|
||||
TEST_MSUBU_HL(0x5cd408ae, 0x381f90dd, 0x4f302965, 0x1c39c078, 0x3ad6554a, 0x973a6242)
|
||||
TEST_MSUBU_HL(0x7194c55c, 0xb2ed2c9, 0x58e54d25, 0x4a8d4791, 0x53ef2269, 0xa850da55)
|
||||
TEST_MSUBU_HL(0x79d19214, 0x84592de, 0xa676d04, 0x67280834, 0x677c514, 0x3eb7f2dc)
|
||||
TEST_MSUBU_HL(0x35c600bb, 0x3d573d2e, 0x10d8e87a, 0x7f5e9f4b, 0x3f66729, 0xd910eeb1)
|
||||
TEST_MSUBU_HL(0x249a587b, 0x1c52cda4, 0x7968c7d2, 0x28afbc02, 0x755c0f4d, 0x518e8e36)
|
||||
TEST_MSUBU_HL(0x1a38374e, 0xefe4e16, 0x59ed4ef4, 0x65543e2c, 0x58643027, 0xe041b978)
|
||||
TEST_MSUBU_HL(0x460828b2, 0x77ceb952, 0x15c7390b, 0x28d5a1b1, 0xf500e0dd, 0x5793f6ad)
|
||||
TEST_MSUBU_HL(0x5638bd34, 0x24d867aa, 0x31e09091, 0x3e6aa728, 0x2577b32c, 0x34bd16a0)
|
||||
TEST_MSUBU_HL(0x4e516f14, 0x66c33dba, 0x776c5e78, 0x220929b, 0x57fc314c, 0x1f421a13)
|
||||
TEST_MSUBU_HL(0x1420f940, 0x712adc6a, 0x43379665, 0x24db3d8a, 0x3a51a9a2, 0x5481090a)
|
||||
TEST_MSUBU_HL(0x22797603, 0x973885e, 0x31850e8d, 0x53b1d5b9, 0x303f3a7a, 0x60de89f)
|
||||
TEST_MSUBU_HL(0xa237683, 0x6372fab7, 0x2b091b40, 0x7855f2c0, 0x2718d6b3, 0x27ea4d1b)
|
||||
TEST_MSUBU_HL(0x7a291e75, 0x4e1fc41d, 0x70ab7a86, 0x47dc370e, 0x4b63caae, 0x9fb72fcd)
|
||||
TEST_MSUBU_HL(0x7aa5c79a, 0x1346b2e1, 0xedb6e19, 0x28a20641, 0x59f4141, 0x160883e7)
|
||||
TEST_MSUBU_HL(0x1c16b855, 0x52caf402, 0x4cad5304, 0x2c147c4d, 0x4397c745, 0x9f2407a3)
|
||||
|
||||
###detect exception
|
||||
bne s2, zero, inst_error
|
||||
nop
|
||||
###score ++
|
||||
addiu s3, s3, 1
|
||||
###output (s0<<24)|s3
|
||||
inst_error:
|
||||
sll t1, s0, 24
|
||||
or t0, t1, s3
|
||||
sw t0, 0(s1)
|
||||
jr ra
|
||||
nop
|
||||
END(n97_msub_msubu_test)
|
||||
318
resources/2021/soft/func/inst/n98_cache_dcache.S
Normal file
318
resources/2021/soft/func/inst/n98_cache_dcache.S
Normal file
@ -0,0 +1,318 @@
|
||||
#include <asm.h>
|
||||
#include <regdef.h>
|
||||
#include <inst_test.h>
|
||||
|
||||
LEAF(n98_cache_dcache_test)
|
||||
.set noreorder
|
||||
addiu s0, s0 ,1
|
||||
li s2, 0x0
|
||||
###test inst
|
||||
|
||||
## CACHE 17 D-Cache Hit Invalid
|
||||
## CACHE 21 D-Cache Hit Writeback Invalid
|
||||
|
||||
TEST_CACHE_DCACHE_HIT(0xa00d0000, 0x800d0000, 0, 0xA5A5A5A5, 0x12345678)
|
||||
TEST_CACHE_DCACHE_HIT(0xa00d0004, 0x800d0004, 0, 0xABCDEFAB, 0xF0F0F0F0)
|
||||
TEST_CACHE_DCACHE_HIT(0xa00d0008, 0x800d0008, 4, 0x87654321, 0xAABBCCDD)
|
||||
TEST_CACHE_DCACHE_HIT(0xa00d000C, 0x800d000C, 4, 0xF0F0F0F0, 0xABCDEFAB)
|
||||
|
||||
TEST_CACHE_DCACHE_HIT(0xa00d0010, 0x800d0010, 0, 0xA5A5A5A5, 0x12345678)
|
||||
TEST_CACHE_DCACHE_HIT(0xa00d0018, 0x800d0018, 0, 0xABCDEFAB, 0xF0F0F0F0)
|
||||
TEST_CACHE_DCACHE_HIT(0xa00d0020, 0x800d0020, 4, 0x87654321, 0xAABBCCDD)
|
||||
TEST_CACHE_DCACHE_HIT(0xa00d0028, 0x800d0028, 4, 0xF0F0F0F0, 0xABCDEFAB)
|
||||
|
||||
.n98_con_prepare1:
|
||||
li a0, 0x12345678
|
||||
li v0, 0x800d0000
|
||||
li v1, 64*4*4
|
||||
add v1, v0, v1
|
||||
.n98_con_prepare1_loop:
|
||||
beq v0, v1, .n98_con_check1
|
||||
nop
|
||||
sw a0, 0(v0)
|
||||
sw a0, 4(v0)
|
||||
sw a0, 8(v0)
|
||||
sw a0, 12(v0)
|
||||
cache 21, 0(v0) # Hit Writeback Invalid
|
||||
cache 21, 4(v0)
|
||||
cache 21, 8(v0)
|
||||
cache 21, 12(v0)
|
||||
addi v0, v0, 16
|
||||
j .n98_con_prepare1_loop
|
||||
nop
|
||||
.n98_con_check1:
|
||||
li v0, 0xa00d0000
|
||||
li v1, 64*4*4
|
||||
add v1, v0, v1
|
||||
.n98_con_check1_loop:
|
||||
beq v0, v1, .n98_con_check2
|
||||
nop
|
||||
lw a1, 0(v0)
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
lw a1, 4(v0)
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
lw a1, 8(v0)
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
lw a1, 12(v0)
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
addi v0, v0, 16
|
||||
j .n98_con_check1_loop
|
||||
nop
|
||||
.n98_con_check2:
|
||||
li v0, 0x800d0000
|
||||
li v1, 64*4*4
|
||||
add v1, v0, v1
|
||||
.n98_con_check2_loop:
|
||||
beq v0, v1, .n98_con_prepare3
|
||||
nop
|
||||
lw a1, 0(v0)
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
lw a1, 4(v0)
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
lw a1, 8(v0)
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
lw a1, 12(v0)
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
addi v0, v0, 16
|
||||
j .n98_con_check2_loop
|
||||
nop
|
||||
|
||||
.n98_con_prepare3:
|
||||
li a0, 0xA5A5A5A5
|
||||
li v0, 0x800d0000
|
||||
li v1, 64*4*4
|
||||
add v1, v0, v1
|
||||
.n98_con_prepare3_loop:
|
||||
beq v0, v1, .n98_con_check3
|
||||
nop
|
||||
sw a0, 0(v0)
|
||||
sw a0, 4(v0)
|
||||
sw a0, 8(v0)
|
||||
sw a0, 12(v0)
|
||||
cache 17, 0(v0) # Hit Invalid
|
||||
cache 17, 4(v0)
|
||||
cache 17, 8(v0)
|
||||
cache 17, 12(v0)
|
||||
addi v0, v0, 16
|
||||
j .n98_con_prepare3_loop
|
||||
nop
|
||||
.n98_con_check3:
|
||||
li a0, 0x12345678
|
||||
li v0, 0x800d0000
|
||||
li v1, 64*4*4
|
||||
add v1, v0, v1
|
||||
.n98_con_check4_loop:
|
||||
beq v0, v1, .n98_con_end
|
||||
nop
|
||||
lw a1, 0(v0)
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
lw a1, 4(v0)
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
lw a1, 8(v0)
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
lw a1, 12(v0)
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
addi v0, v0, 16
|
||||
j .n98_con_check4_loop
|
||||
nop
|
||||
.n98_con_end:
|
||||
nop
|
||||
|
||||
|
||||
/* TEST D-CACHE Index OP */
|
||||
## CACHE 1 D-Cache Index Writeback Invalid
|
||||
## CACHE 9 D-Cache Index Store Tag
|
||||
|
||||
.n98_c1_prepare:
|
||||
li a0, 0x11223344
|
||||
li v0, 0x800d0000
|
||||
li v1, 0x800d0200
|
||||
.n98_c1_loop:
|
||||
beq v0, v1, .n98_c1_check
|
||||
nop
|
||||
sw a0, 0(v0)
|
||||
sw a0, 4(v0)
|
||||
sw a0, 8(v0)
|
||||
sw a0, 12(v0)
|
||||
addi a1, v0, 0
|
||||
GET_DCACHE_INDEX
|
||||
cache 1, 0(v0)
|
||||
addi v0, a1, 16
|
||||
j .n98_c1_loop
|
||||
nop
|
||||
.n98_c1_check:
|
||||
li v0, 0xa00d0000
|
||||
li v1, 0xa00d0200
|
||||
.n98_c1_check_loop:
|
||||
beq v0, v1, .n98_c1_check2
|
||||
nop
|
||||
lw a1, 0(v0)
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
addi v0, v0, 4
|
||||
j .n98_c1_check_loop
|
||||
nop
|
||||
.n98_c1_check2:
|
||||
li v0, 0x800d0000
|
||||
li v1, 0x800d0200
|
||||
.n98_c1_check2_loop:
|
||||
beq v0, v1, .n98_c9_prepare
|
||||
nop
|
||||
lw a1, 0(v0)
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
addi v0, v0, 4
|
||||
j .n98_c1_check2_loop
|
||||
nop
|
||||
|
||||
|
||||
.n98_c9_prepare:
|
||||
li v0, 0x800d0000
|
||||
li v1, 0x800d0200
|
||||
.n98_c9_loop:
|
||||
beq v0, v1, .n98_c9_check
|
||||
nop
|
||||
sw zero, 0(v0)
|
||||
sw zero, 4(v0)
|
||||
sw zero, 8(v0)
|
||||
sw zero, 12(v0)
|
||||
addi a1, v0, 0
|
||||
GET_DCACHE_INDEX
|
||||
cache 9, 0(v0)
|
||||
addi v0, a1, 16
|
||||
j .n98_c9_loop
|
||||
nop
|
||||
.n98_c9_check:
|
||||
li v0, 0xa00d0000
|
||||
li v1, 0xa00d0200
|
||||
.n98_c9_check_loop:
|
||||
beq v0, v1, .n98_c9_check2
|
||||
nop
|
||||
lw a1, 0(v0)
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
addi v0, v0, 4
|
||||
j .n98_c9_check_loop
|
||||
nop
|
||||
.n98_c9_check2:
|
||||
li v0, 0x800d0000
|
||||
li v1, 0x800d0200
|
||||
.n98_c9_check2_loop:
|
||||
beq v0, v1, .n98_done
|
||||
nop
|
||||
lw a1, 0(v0)
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
addi v0, v0, 4
|
||||
j .n98_c9_check2_loop
|
||||
nop
|
||||
|
||||
.n98_done:
|
||||
nop
|
||||
|
||||
## CACHE 1 D-Cache Index Writeback Invalid
|
||||
|
||||
## Enforced test on writeback whole line
|
||||
|
||||
li t0, 0xa00d0000
|
||||
li t1, 0xa00d0800
|
||||
li t2, 0xa00d1000
|
||||
li t3, 0xa00d1800
|
||||
|
||||
li v0, 0xa00d000c
|
||||
.n98_en_rst:
|
||||
beq t0, v0, .n98_en_w_bgn
|
||||
nop
|
||||
sw zero, 0(t0)
|
||||
sw zero, 0(t1)
|
||||
sw zero, 0(t2)
|
||||
sw zero, 0(t3)
|
||||
addi t0, t0, 4
|
||||
addi t1, t1, 4
|
||||
addi t2, t2, 4
|
||||
addi t3, t3, 4
|
||||
j .n98_en_rst
|
||||
nop
|
||||
|
||||
.n98_en_w_bgn:
|
||||
li t0, 0x800d0000
|
||||
li t1, 0x800d0800
|
||||
li t2, 0x800d1000
|
||||
li t3, 0x800d1800
|
||||
|
||||
li v0, 0x800d000c
|
||||
li a0, 0xa5a50000
|
||||
.n98_en_w:
|
||||
beq t0, v0, .n98_en_chk_bgn
|
||||
nop
|
||||
sw a0, 0(t0)
|
||||
sw a0, 0(t1)
|
||||
sw a0, 0(t2)
|
||||
sw a0, 0(t3)
|
||||
addi t0, t0, 4
|
||||
addi t1, t1, 4
|
||||
addi t2, t2, 4
|
||||
addi t3, t3, 4
|
||||
addi a0, a0, 1
|
||||
j .n98_en_w
|
||||
nop
|
||||
|
||||
.n98_en_chk_bgn:
|
||||
li t0, 0xa00d0000
|
||||
li t1, 0xa00d0800
|
||||
li t2, 0xa00d1000
|
||||
li t3, 0xa00d1800
|
||||
li v0, 0xa00d000c
|
||||
li a0, 0xa5a50000
|
||||
|
||||
cache 1, 0(zero)
|
||||
.n98_en_chk:
|
||||
beq t0, v0, .n98_en_end
|
||||
nop
|
||||
lw a1, 0(t0)
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
lw a1, 0(t1)
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
lw a1, 0(t2)
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
lw a1, 0(t3)
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
addi t0, t0, 4
|
||||
addi t1, t1, 4
|
||||
addi t2, t2, 4
|
||||
addi t3, t3, 4
|
||||
addi a0, a0, 1
|
||||
j .n98_en_chk
|
||||
nop
|
||||
.n98_en_end:
|
||||
nop
|
||||
|
||||
###detect exception
|
||||
bne s2, zero, inst_error
|
||||
nop
|
||||
###score ++
|
||||
addiu s3, s3, 1
|
||||
###output (s0<<24)|s3
|
||||
inst_error:
|
||||
sll t1, s0, 24
|
||||
or t0, t1, s3
|
||||
sw t0, 0(s1)
|
||||
jr ra
|
||||
nop
|
||||
END(n98_cache_dcache_test)
|
||||
441
resources/2021/soft/func/inst/n99_cache_icache.S
Normal file
441
resources/2021/soft/func/inst/n99_cache_icache.S
Normal file
@ -0,0 +1,441 @@
|
||||
#include <asm.h>
|
||||
#include <regdef.h>
|
||||
#include <inst_test.h>
|
||||
|
||||
LEAF(n99_cache_icache_test)
|
||||
.set noreorder
|
||||
addiu s0, s0 ,1
|
||||
li s2, 0x0
|
||||
###test inst
|
||||
|
||||
.n99_1_prepare:
|
||||
addi a1, zero, 0
|
||||
.n99_1:
|
||||
addi a0, zero, 0
|
||||
.n99_1_replace:
|
||||
nop # will be replaced with "addi a0, a0, 1" -> 20840001
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
bne a1, zero, .n99_2_prepare # jump out 2nd
|
||||
nop
|
||||
addi a1, a1, 1
|
||||
.n99_1_work:
|
||||
la v0, .n99_1_replace
|
||||
li v1, 0x20840001
|
||||
li t0, 0x20000000
|
||||
subu v0, v0, t0 # v0 <- 9fcxxxxx
|
||||
sw v1, 0(v0)
|
||||
cache 21, 0(v0) # D-Cache Hit WriteBack Invalid
|
||||
cache 16, 0(v0) # I-Cache Hit Invalid
|
||||
# TODO: clear Datapath on CACHE
|
||||
# using enough nop to stop prefetch
|
||||
nop;nop;nop;nop;nop;nop;
|
||||
nop;nop;nop;nop;nop;nop;
|
||||
j .n99_1
|
||||
nop
|
||||
|
||||
|
||||
.n99_2_prepare:
|
||||
addi a1, zero, 0
|
||||
.n99_2:
|
||||
addi a0, zero, 0
|
||||
.n99_2_replace:
|
||||
nop # will be replaced with "addi a0, a0, 1" -> 20840001
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
bne a1, zero, .n99_3_prepare # jump out 2nd
|
||||
nop
|
||||
addi a1, a1, 1
|
||||
.n99_2_work:
|
||||
la v0, .n99_2_replace
|
||||
li v1, 0x20840001
|
||||
li t0, 0x20000000
|
||||
subu v0, v0, t0
|
||||
sw v1, 0(v0)
|
||||
cache 21, 0(v0) # D-Cache Hit WriteBack Invalid
|
||||
addi t0, zero, 0
|
||||
addi t1, zero, 64 # I-Cache Index Max 64
|
||||
.n99_2_loop:
|
||||
beq t0, t1, .n99_2_check
|
||||
nop
|
||||
cache 0, 0(t0) # I-Cache Index Invalid
|
||||
addi t0, t0, 1
|
||||
j .n99_2_loop
|
||||
nop
|
||||
.n99_2_check:
|
||||
# TODO: clear Datapath on CACHE
|
||||
# using enough nop to stop prefetch
|
||||
nop;nop;nop;nop;nop;nop;
|
||||
nop;nop;nop;nop;nop;nop;
|
||||
j .n99_2
|
||||
nop
|
||||
|
||||
|
||||
.n99_3_prepare:
|
||||
addi a1, zero, 0
|
||||
.n99_3:
|
||||
addi a0, zero, 0
|
||||
.n99_3_replace:
|
||||
nop # will be replaced with "addi a0, a0, 1" -> 20840001
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
bne a1, zero, .n99_4_prepare # jump out 2nd
|
||||
nop
|
||||
addi a1, a1, 1
|
||||
.n99_3_work:
|
||||
la v0, .n99_3_replace
|
||||
li v1, 0x20840001
|
||||
li t0, 0x20000000
|
||||
subu v0, v0, t0
|
||||
sw v1, 0(v0)
|
||||
cache 21, 0(v0) # D-Cache Hit WriteBack Invalid
|
||||
addi t0, zero, 0
|
||||
addi t1, zero, 64 # I-Cache Index Max 64
|
||||
.n99_3_loop:
|
||||
beq t0, t1, .n99_3_check
|
||||
nop
|
||||
cache 8, 0(t0) # I-Cache Index Store Tag
|
||||
addi t0, t0, 1
|
||||
j .n99_3_loop
|
||||
nop
|
||||
.n99_3_check:
|
||||
# TODO: clear Datapath on CACHE
|
||||
# using enough nop to stop prefetch
|
||||
nop;nop;nop;nop;nop;nop;
|
||||
nop;nop;nop;nop;nop;nop;
|
||||
j .n99_3
|
||||
nop
|
||||
|
||||
|
||||
.n99_4_prepare:
|
||||
addi a1, zero, 0
|
||||
.n99_4:
|
||||
addi a0, zero, 0
|
||||
.n99_4_replace:
|
||||
nop # will be replaced with "addi a0, a0, 1" -> 20840001
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
bne a1, zero, .n99_5_prepare # jump out 2nd
|
||||
nop
|
||||
addi a1, a1, 1
|
||||
.n99_4_work:
|
||||
la v0, .n99_4_replace
|
||||
li v1, 0x20840001
|
||||
li t0, 0x20000000
|
||||
subu v0, v0, t0 # v0 <- 9fcxxxxx
|
||||
sw v1, 0(v0)
|
||||
cache 21, 0(v0) # D-Cache Hit WriteBack Invalid
|
||||
GET_ICACHE_INDEX # convert v0 into its index
|
||||
cache 0, 0(v0) # I-Cache Hit Invalid
|
||||
# TODO: clear Datapath on CACHE
|
||||
# using enough nop to stop prefetch
|
||||
nop;nop;nop;nop;nop;nop;
|
||||
nop;nop;nop;nop;nop;nop;
|
||||
j .n99_4
|
||||
nop
|
||||
|
||||
|
||||
.n99_5_prepare:
|
||||
addi a1, zero, 0
|
||||
.n99_5:
|
||||
addi a0, zero, 0
|
||||
.n99_5_replace:
|
||||
nop # will be replaced with "addi a0, a0, 1" -> 20840001
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
bne a1, zero, .n99_con_prepare # jump out 2nd
|
||||
nop
|
||||
addi a1, a1, 1
|
||||
.n99_5_work:
|
||||
la v0, .n99_5_replace
|
||||
li v1, 0x20840001
|
||||
li t0, 0x20000000
|
||||
subu v0, v0, t0 # v0 <- 9fcxxxxx
|
||||
sw v1, 0(v0)
|
||||
cache 21, 0(v0) # D-Cache Hit WriteBack Invalid
|
||||
GET_ICACHE_INDEX # convert v0 into its index
|
||||
cache 8, 0(v0) # I-Cache Index Store Tag
|
||||
# TODO: clear Datapath on CACHE
|
||||
# using enough nop to stop prefetch
|
||||
nop;nop;nop;nop;nop;nop;
|
||||
nop;nop;nop;nop;nop;nop;
|
||||
j .n99_5
|
||||
nop
|
||||
|
||||
.n99_con_prepare:
|
||||
addi a1, zero, 0
|
||||
.n99_con:
|
||||
addi a0, zero, 0
|
||||
# nop # very tricky -> align 16 <- no need
|
||||
.n99_con_replace:
|
||||
nop;nop;nop;nop; # addi a0, zero, 5; addi a1, zero, 6; mul a0, a0, a1; nop;
|
||||
nop;nop;nop;nop; # addi a0, a0, 12; addi a1, a1, 1; div a0, a1; nop;
|
||||
nop;nop;nop;nop; # mflo a0; addi a1, zero, 1; nop; nop;
|
||||
nop;nop;nop;nop; # nop; addi a0, a0, -1; nop; nop;
|
||||
nop;nop;nop;nop; # nop; nop; addi a0, a0, -1; nop;
|
||||
nop;nop;nop;nop; # nop; nop; nop; addi a0, a0, -1;
|
||||
nop;nop;nop;nop; # addi a0, a0, -1; nop; nop; nop;
|
||||
nop;nop;nop;nop; # nop; addi a0, a0, -1; nop; nop;
|
||||
|
||||
bne a0, a1, inst_error
|
||||
nop
|
||||
bne a1, zero, .n99_success # jump out 2nd
|
||||
nop
|
||||
addi a1, a1, 1
|
||||
.n99_con_work:
|
||||
la v0, .n99_con_replace
|
||||
li t0, 0x20000000
|
||||
subu v0, v0, t0 # v0 <- 9fcxxxxx
|
||||
addi t0, zero, 0
|
||||
|
||||
# addi a0, zero, 5; addi a1, zero, 6; mul a0, a0, a1; nop;
|
||||
li v1, 0x20040005 # addi a0, zero, 5
|
||||
sw v1, 0(v0)
|
||||
li v1, 0x20050006 # addi a1, zero, 6
|
||||
sw v1, 4(v0)
|
||||
li v1, 0x70852002 # mul a0, a0, a1
|
||||
sw v1, 8(v0)
|
||||
cache 21, 0(v0)
|
||||
|
||||
# addi a0, a0, 12; addi a1, a1, 1; div a0, a1; nop;
|
||||
addi v0, v0, 16
|
||||
li v1, 0x2084000C # addi a0, a0, 12
|
||||
sw v1, 0(v0)
|
||||
li v1, 0x20A50001 # addi a1, a1, 1
|
||||
sw v1, 4(v0)
|
||||
li v1, 0x0085001a # div a0, a1
|
||||
sw v1, 8(v0)
|
||||
cache 21, 0(v0)
|
||||
|
||||
# mfhi a0; addi a1, zero, 1; nop; nop;
|
||||
addi v0, v0, 16
|
||||
li v1, 0x00002012 # mflo a0
|
||||
sw v1, 0(v0)
|
||||
li v1, 0x20050001 # addi a1, zero, 1
|
||||
sw v1, 4(v0)
|
||||
cache 21, 0(v0)
|
||||
|
||||
# nop; addi a0, a0, -1; nop; nop;
|
||||
addi v0, v0, 16
|
||||
li v1, 0x2084FFFF # addi a0, a0, -1
|
||||
sw v1, 4(v0)
|
||||
cache 21, 0(v0)
|
||||
|
||||
# nop; nop; addi a0, a0, -1; nop;
|
||||
addi v0, v0, 16
|
||||
sw v1, 8(v0)
|
||||
cache 21, 0(v0)
|
||||
|
||||
# nop; nop; nop; addi a0, a0, -1;
|
||||
addi v0, v0, 16
|
||||
sw v1, 12(v0)
|
||||
cache 21, 0(v0)
|
||||
|
||||
# addi a0, a0, -1; nop; nop; nop;
|
||||
addi v0, v0, 16
|
||||
sw v1, 0(v0)
|
||||
cache 21, 0(v0)
|
||||
|
||||
# nop; addi a0, a0, -1; nop; nop;
|
||||
addi v0, v0, 16
|
||||
sw v1, 4(v0)
|
||||
cache 21, 4(v0)
|
||||
|
||||
addi v0, zero, 0
|
||||
addi v1, zero, 64
|
||||
.n99_con_loop:
|
||||
beq v0, v1, .n99_con_loop_end
|
||||
nop
|
||||
cache 0, 0(v0)
|
||||
cache 0, 1(v0)
|
||||
cache 0, 2(v0)
|
||||
cache 0, 3(v0)
|
||||
cache 0, 4(v0)
|
||||
cache 0, 5(v0)
|
||||
cache 0, 6(v0)
|
||||
cache 0, 7(v0)
|
||||
addi v0, v0, 8
|
||||
j .n99_con_loop
|
||||
nop
|
||||
|
||||
.n99_con_loop_end:
|
||||
# TODO: clear Datapath on CACHE
|
||||
# using enough nop to stop prefetch
|
||||
nop;nop;nop;nop;nop;nop;
|
||||
nop;nop;nop;nop;nop;nop;
|
||||
j .n99_con
|
||||
nop
|
||||
|
||||
.n99_success:
|
||||
nop
|
||||
|
||||
/* Hand-make disasm of the NOPs
|
||||
0cc 20040005 addi a0, zero, 5
|
||||
0d0 20050006 addi a1, zero, 6
|
||||
0d4 70852002 mul a0, a0, a1
|
||||
0d8 00000000 nop
|
||||
0dc 2084000C addi a0, a0, 12
|
||||
0e0 20A50001 addi a1, a1, 1
|
||||
0e4 0085001A div a0, a1
|
||||
0e8 00000000 nop
|
||||
0ec 00002012 mflo a0
|
||||
0f0 20050001 addi a1, zero, 1
|
||||
0f4 00000000 nop
|
||||
0f8 00000000 nop
|
||||
0fc 00000000 nop
|
||||
100 2084FFFF addi a0, a0, -1
|
||||
104 00000000 nop
|
||||
108 00000000 nop
|
||||
10c 00000000 nop
|
||||
110 00000000 nop
|
||||
114 2084FFFF addi a0, a0, -1
|
||||
118 00000000 nop
|
||||
11c 00000000 nop
|
||||
120 00000000 nop
|
||||
124 00000000 nop
|
||||
128 2084FFFF addi a0, a0, -1
|
||||
12c 2084FFFF addi a0, a0, -1
|
||||
130 00000000 nop
|
||||
134 00000000 nop
|
||||
138 00000000 nop
|
||||
13c 00000000 nop
|
||||
140 2084FFFF addi a0, a0, -1
|
||||
144 00000000 nop
|
||||
148 00000000 nop
|
||||
*/
|
||||
|
||||
/*
|
||||
Enhanced test:
|
||||
1. fill 800d0000, 800D0800, 800D1000, 800D1800 with instructions
|
||||
2. jump to 800d0000, 800D0800, 800D1000, 800D1800 and execute
|
||||
3. return back to here and check registers
|
||||
4. modify 800d0000, 800D0800, 800D1000, 800D1800
|
||||
5. same as 2 3
|
||||
|
||||
20050000 addi $a1, $zero, 0
|
||||
03e00008 jr $ra
|
||||
20a5000[] addi $a1, $a1, [case]
|
||||
|
||||
*/
|
||||
.n99_en_bgn:
|
||||
move a0, ra
|
||||
|
||||
li t0, 0x800d0000
|
||||
li t1, 0x800d0800
|
||||
li t2, 0x800d1000
|
||||
li t3, 0x800d1800
|
||||
|
||||
li a1, 0x20050000
|
||||
li a2, 0x03e00008
|
||||
li a3, 0x20a50000
|
||||
|
||||
.n98_en_step1:
|
||||
sw a1, 0(t0)
|
||||
sw a1, 0(t1)
|
||||
sw a1, 0(t2)
|
||||
sw a1, 0(t3)
|
||||
|
||||
sw a2, 4(t0)
|
||||
sw a2, 4(t1)
|
||||
sw a2, 4(t2)
|
||||
sw a2, 4(t3)
|
||||
|
||||
sw a3, 8(t0)
|
||||
addi a3, a3, 1
|
||||
sw a3, 8(t1)
|
||||
addi a3, a3, 1
|
||||
sw a3, 8(t2)
|
||||
addi a3, a3, 1
|
||||
sw a3, 8(t3)
|
||||
addi a3, a3, 1
|
||||
|
||||
cache 1, 0(zero)
|
||||
cache 0, 0(zero)
|
||||
|
||||
.n98_en_step23:
|
||||
li a1, 0
|
||||
li a2, 0
|
||||
jalr t0
|
||||
nop
|
||||
bne a1, a2, inst_error
|
||||
nop
|
||||
|
||||
li a1, 0
|
||||
li a2, 1
|
||||
jalr t1
|
||||
nop
|
||||
bne a1, a2, inst_error
|
||||
nop
|
||||
|
||||
li a1, 0
|
||||
li a2, 2
|
||||
jalr t2
|
||||
nop
|
||||
bne a1, a2, inst_error
|
||||
nop
|
||||
|
||||
li a1, 0
|
||||
li a2, 3
|
||||
jalr t3
|
||||
nop
|
||||
bne a1, a2, inst_error
|
||||
nop
|
||||
|
||||
.n98_en_step4:
|
||||
sw a3, 8(t0)
|
||||
addi a3, a3, 1
|
||||
sw a3, 8(t1)
|
||||
addi a3, a3, 1
|
||||
sw a3, 8(t2)
|
||||
addi a3, a3, 1
|
||||
sw a3, 8(t3)
|
||||
addi a3, a3, 1
|
||||
|
||||
cache 1, 0(zero)
|
||||
cache 0, 0(zero)
|
||||
|
||||
.n98_en_step5:
|
||||
li a1, 0
|
||||
li a2, 4
|
||||
jalr t0
|
||||
nop
|
||||
bne a1, a2, inst_error
|
||||
nop
|
||||
|
||||
li a1, 0
|
||||
li a2, 5
|
||||
jalr t1
|
||||
nop
|
||||
bne a1, a2, inst_error
|
||||
nop
|
||||
|
||||
li a1, 0
|
||||
li a2, 6
|
||||
jalr t2
|
||||
nop
|
||||
bne a1, a2, inst_error
|
||||
nop
|
||||
|
||||
li a1, 0
|
||||
li a2, 7
|
||||
jalr t3
|
||||
nop
|
||||
bne a1, a2, inst_error
|
||||
nop
|
||||
|
||||
.n98_en_rst:
|
||||
move ra, a0
|
||||
|
||||
###detect exception
|
||||
bne s2, zero, inst_error
|
||||
nop
|
||||
###score ++
|
||||
addiu s3, s3, 1
|
||||
###output (s0<<24)|s3
|
||||
inst_error:
|
||||
sll t1, s0, 24
|
||||
or t0, t1, s3
|
||||
sw t0, 0(s1)
|
||||
jr ra
|
||||
nop
|
||||
END(n99_cache_icache_test)
|
||||
@ -2,7 +2,7 @@
|
||||
#include <regdef.h>
|
||||
#include <cpu_cde.h>
|
||||
|
||||
#define TEST_NUM 89
|
||||
#define TEST_NUM 101
|
||||
|
||||
|
||||
##s0, number
|
||||
@ -83,6 +83,9 @@ test_finish:
|
||||
li k0, 0x08 # int
|
||||
beq k1, k0, int_ex
|
||||
nop
|
||||
li k0, 0x09 # trap
|
||||
beq k1, k0, trap_ex
|
||||
nop
|
||||
|
||||
syscall_ex:
|
||||
addu s2, zero, zero
|
||||
@ -244,6 +247,25 @@ int_ex:
|
||||
b ex_ret
|
||||
nop
|
||||
|
||||
trap_ex:
|
||||
addu s2, zero, zero
|
||||
mfc0 k0, c0_epc
|
||||
bne k0, s4, ex_finish
|
||||
nop
|
||||
mfc0 k0, c0_cause
|
||||
andi k0, k0, 0x7c # 6..2
|
||||
li k1, 0x34 # Trap EXCCODE << 2
|
||||
bne k0, k1, ex_finish
|
||||
nop
|
||||
mfc0 k0, c0_status
|
||||
andi k0, k0, 0x02 # EXL
|
||||
li k1, 0x02
|
||||
bne k0, k1, ex_finish
|
||||
nop
|
||||
lui s2, 0x9
|
||||
b ex_finish
|
||||
nop
|
||||
|
||||
ex_finish:
|
||||
mfc0 k0,c0_cause
|
||||
lui k1,0x8000
|
||||
@ -297,8 +319,28 @@ inst_test:
|
||||
la t9, kseg0_kseg1 #####
|
||||
jr t9 #kseg0 -> kseg1
|
||||
nop #####
|
||||
|
||||
kseg0_kseg1:
|
||||
|
||||
jal n98_cache_dcache_test
|
||||
nop
|
||||
jal wait_1s
|
||||
nop
|
||||
|
||||
la t1, n99_kseg1_kseg0
|
||||
li t2, 0x20000000
|
||||
subu t9, t1, t2
|
||||
jr t9
|
||||
nop
|
||||
n99_kseg1_kseg0:
|
||||
jal n99_cache_icache_test
|
||||
nop
|
||||
jal wait_1s
|
||||
nop
|
||||
la t9, n99_kseg0_kseg1
|
||||
jr t9
|
||||
nop
|
||||
n99_kseg0_kseg1:
|
||||
|
||||
jal n2_addu_test #addu
|
||||
nop
|
||||
jal wait_1s
|
||||
@ -651,6 +693,49 @@ kseg0_kseg1:
|
||||
nop
|
||||
jal wait_1s
|
||||
nop
|
||||
jal n90_lwl_test
|
||||
nop
|
||||
jal wait_1s
|
||||
nop
|
||||
jal n91_lwr_test
|
||||
nop
|
||||
jal wait_1s
|
||||
nop
|
||||
jal n92_swl_test
|
||||
nop
|
||||
jal wait_1s
|
||||
nop
|
||||
jal n93_swr_test
|
||||
nop
|
||||
jal wait_1s
|
||||
nop
|
||||
jal n94_perf_sync_nop_test
|
||||
nop
|
||||
jal wait_1s
|
||||
nop
|
||||
jal n95_madd_test
|
||||
nop
|
||||
jal wait_1s
|
||||
nop
|
||||
jal n96_maddu_test
|
||||
nop
|
||||
jal wait_1s
|
||||
nop
|
||||
jal n97_msub_msubu_test
|
||||
nop
|
||||
jal wait_1s
|
||||
nop
|
||||
|
||||
|
||||
jal n100_movz_movn_test
|
||||
nop
|
||||
jal wait_1s
|
||||
nop
|
||||
jal n101_trap_test
|
||||
nop
|
||||
jal wait_1s
|
||||
nop
|
||||
|
||||
###check io access
|
||||
LI (a0, IO_SIMU_ADDR)
|
||||
LI (t0, 0x1234)
|
||||
|
||||
@ -1,11 +0,0 @@
|
||||
digraph ICache{
|
||||
splines=ortho
|
||||
compound=true
|
||||
node [shape=Mrecord]
|
||||
edge [arrowhead=normal]
|
||||
|
||||
IDLE->LOOKUP[xlabel="req" weight=5 color=green]
|
||||
LOOKUP->REPLACE[xlabel="~hit" color=blue]
|
||||
LOOKUP->IDLE[xlabel="hit" color=red]
|
||||
REPLACE->IDLE[xlabel="refilled" color=orange]
|
||||
}
|
||||
@ -1,59 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN"
|
||||
"http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
|
||||
<!-- Generated by graphviz version 2.48.0 (0)
|
||||
-->
|
||||
<!-- Title: ICache Pages: 1 -->
|
||||
<svg width="137pt" height="191pt"
|
||||
viewBox="0.00 0.00 136.50 191.00" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
|
||||
<g id="graph0" class="graph" transform="scale(1 1) rotate(0) translate(4 187)">
|
||||
<title>ICache</title>
|
||||
<polygon fill="white" stroke="transparent" points="-4,4 -4,-187 132.5,-187 132.5,4 -4,4"/>
|
||||
<!-- IDLE -->
|
||||
<g id="node1" class="node">
|
||||
<title>IDLE</title>
|
||||
<path fill="none" stroke="black" d="M20.5,-146.5C20.5,-146.5 50.5,-146.5 50.5,-146.5 56.5,-146.5 62.5,-152.5 62.5,-158.5 62.5,-158.5 62.5,-170.5 62.5,-170.5 62.5,-176.5 56.5,-182.5 50.5,-182.5 50.5,-182.5 20.5,-182.5 20.5,-182.5 14.5,-182.5 8.5,-176.5 8.5,-170.5 8.5,-170.5 8.5,-158.5 8.5,-158.5 8.5,-152.5 14.5,-146.5 20.5,-146.5"/>
|
||||
<text text-anchor="middle" x="35.5" y="-160.8" font-family="Times,serif" font-size="14.00">IDLE</text>
|
||||
</g>
|
||||
<!-- LOOKUP -->
|
||||
<g id="node2" class="node">
|
||||
<title>LOOKUP</title>
|
||||
<path fill="none" stroke="black" d="M12,-73.5C12,-73.5 59,-73.5 59,-73.5 65,-73.5 71,-79.5 71,-85.5 71,-85.5 71,-97.5 71,-97.5 71,-103.5 65,-109.5 59,-109.5 59,-109.5 12,-109.5 12,-109.5 6,-109.5 0,-103.5 0,-97.5 0,-97.5 0,-85.5 0,-85.5 0,-79.5 6,-73.5 12,-73.5"/>
|
||||
<text text-anchor="middle" x="35.5" y="-87.8" font-family="Times,serif" font-size="14.00">LOOKUP</text>
|
||||
</g>
|
||||
<!-- IDLE->LOOKUP -->
|
||||
<g id="edge1" class="edge">
|
||||
<title>IDLE->LOOKUP</title>
|
||||
<path fill="none" stroke="green" d="M26.5,-146.46C26.5,-146.46 26.5,-119.59 26.5,-119.59"/>
|
||||
<polygon fill="green" stroke="green" points="30,-119.59 26.5,-109.59 23,-119.59 30,-119.59"/>
|
||||
<text text-anchor="middle" x="17.5" y="-121.82" font-family="Times,serif" font-size="14.00">req</text>
|
||||
</g>
|
||||
<!-- LOOKUP->IDLE -->
|
||||
<g id="edge3" class="edge">
|
||||
<title>LOOKUP->IDLE</title>
|
||||
<path fill="none" stroke="red" d="M44.5,-109.54C44.5,-109.54 44.5,-136.41 44.5,-136.41"/>
|
||||
<polygon fill="red" stroke="red" points="41,-136.41 44.5,-146.41 48,-136.41 41,-136.41"/>
|
||||
<text text-anchor="middle" x="37" y="-126.78" font-family="Times,serif" font-size="14.00">hit</text>
|
||||
</g>
|
||||
<!-- REPLACE -->
|
||||
<g id="node3" class="node">
|
||||
<title>REPLACE</title>
|
||||
<path fill="none" stroke="black" d="M41,-0.5C41,-0.5 94,-0.5 94,-0.5 100,-0.5 106,-6.5 106,-12.5 106,-12.5 106,-24.5 106,-24.5 106,-30.5 100,-36.5 94,-36.5 94,-36.5 41,-36.5 41,-36.5 35,-36.5 29,-30.5 29,-24.5 29,-24.5 29,-12.5 29,-12.5 29,-6.5 35,-0.5 41,-0.5"/>
|
||||
<text text-anchor="middle" x="67.5" y="-14.8" font-family="Times,serif" font-size="14.00">REPLACE</text>
|
||||
</g>
|
||||
<!-- LOOKUP->REPLACE -->
|
||||
<g id="edge2" class="edge">
|
||||
<title>LOOKUP->REPLACE</title>
|
||||
<path fill="none" stroke="blue" d="M50,-73.46C50,-73.46 50,-46.59 50,-46.59"/>
|
||||
<polygon fill="blue" stroke="blue" points="53.5,-46.59 50,-36.59 46.5,-46.59 53.5,-46.59"/>
|
||||
<text text-anchor="middle" x="39" y="-48.82" font-family="Times,serif" font-size="14.00">~hit</text>
|
||||
</g>
|
||||
<!-- REPLACE->IDLE -->
|
||||
<g id="edge4" class="edge">
|
||||
<title>REPLACE->IDLE</title>
|
||||
<path fill="none" stroke="orange" d="M88.5,-36.63C88.5,-75.64 88.5,-164 88.5,-164 88.5,-164 72.62,-164 72.62,-164"/>
|
||||
<polygon fill="orange" stroke="orange" points="72.62,-160.5 62.62,-164 72.62,-167.5 72.62,-160.5"/>
|
||||
<text text-anchor="middle" x="108.5" y="-112.06" font-family="Times,serif" font-size="14.00">refilled</text>
|
||||
</g>
|
||||
</g>
|
||||
</svg>
|
||||
|
Before Width: | Height: | Size: 3.5 KiB |
@ -1,23 +0,0 @@
|
||||
digraph drState{
|
||||
splines=polyline
|
||||
compound=true
|
||||
node [shape=Mrecord]
|
||||
edge [arrowhead=normal]
|
||||
|
||||
IDLE -> REFILL [label=<write <br/> ~cached or hit>]
|
||||
IDLE -> IDLE [label=<cached <br/> & hit>]
|
||||
IDLE -> WA [label=<cached <br/> ~hit <br/> ~axi.addr_ok>]
|
||||
IDLE -> WD1 [label=<cached <br/> ~hit <br/> axi.addr_ok>]
|
||||
|
||||
WA -> WA [label="~axi.addr_ok"]
|
||||
WA -> WD1 [label="~axi.rvalid"]
|
||||
WA -> WD2 [label=<axi.rvalid <br/>& cached>]
|
||||
WA -> IDLE [label=<axi.rvalid <br/>& ~cached>]
|
||||
|
||||
WD1 -> IDLE [label="axi.rvalid & ~cached"]
|
||||
WD1 -> WD2 [label="axi.rvalid & cached"]
|
||||
WD2 -> WD3 [label="axi.rvalid"]
|
||||
WD3 -> WD4 [label="axi.rvalid"]
|
||||
WD4 -> REFILL [label="axi.rvalid"]
|
||||
REFILL -> IDLE [label="sync with dwState"]
|
||||
}
|
||||
@ -1,161 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN"
|
||||
"http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
|
||||
<!-- Generated by graphviz version 2.48.0 (0)
|
||||
-->
|
||||
<!-- Title: drState Pages: 1 -->
|
||||
<svg width="505pt" height="611pt"
|
||||
viewBox="0.00 0.00 505.00 611.00" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
|
||||
<g id="graph0" class="graph" transform="scale(1 1) rotate(0) translate(4 607)">
|
||||
<title>drState</title>
|
||||
<polygon fill="white" stroke="transparent" points="-4,4 -4,-607 501,-607 501,4 -4,4"/>
|
||||
<!-- IDLE -->
|
||||
<g id="node1" class="node">
|
||||
<title>IDLE</title>
|
||||
<path fill="none" stroke="black" d="M185,-566.5C185,-566.5 215,-566.5 215,-566.5 221,-566.5 227,-572.5 227,-578.5 227,-578.5 227,-590.5 227,-590.5 227,-596.5 221,-602.5 215,-602.5 215,-602.5 185,-602.5 185,-602.5 179,-602.5 173,-596.5 173,-590.5 173,-590.5 173,-578.5 173,-578.5 173,-572.5 179,-566.5 185,-566.5"/>
|
||||
<text text-anchor="middle" x="200" y="-580.8" font-family="Times,serif" font-size="14.00">IDLE</text>
|
||||
</g>
|
||||
<!-- IDLE->IDLE -->
|
||||
<g id="edge2" class="edge">
|
||||
<title>IDLE->IDLE</title>
|
||||
<path fill="none" stroke="black" d="M227.24,-595.36C237.02,-595.6 245,-591.98 245,-584.5 245,-579.83 241.88,-576.66 237.16,-575"/>
|
||||
<polygon fill="black" stroke="black" points="237.62,-571.53 227.24,-573.64 236.67,-578.47 237.62,-571.53"/>
|
||||
<text text-anchor="start" x="245" y="-588.3" font-family="Times,serif" font-size="14.00">cached </text>
|
||||
<text text-anchor="start" x="249" y="-573.3" font-family="Times,serif" font-size="14.00"> & hit</text>
|
||||
</g>
|
||||
<!-- REFILL -->
|
||||
<g id="node2" class="node">
|
||||
<title>REFILL</title>
|
||||
<path fill="none" stroke="black" d="M99,-0.5C99,-0.5 137,-0.5 137,-0.5 143,-0.5 149,-6.5 149,-12.5 149,-12.5 149,-24.5 149,-24.5 149,-30.5 143,-36.5 137,-36.5 137,-36.5 99,-36.5 99,-36.5 93,-36.5 87,-30.5 87,-24.5 87,-24.5 87,-12.5 87,-12.5 87,-6.5 93,-0.5 99,-0.5"/>
|
||||
<text text-anchor="middle" x="118" y="-14.8" font-family="Times,serif" font-size="14.00">REFILL</text>
|
||||
</g>
|
||||
<!-- IDLE->REFILL -->
|
||||
<g id="edge1" class="edge">
|
||||
<title>IDLE->REFILL</title>
|
||||
<path fill="none" stroke="black" d="M172.75,-573.42C144.37,-562.93 104,-548 104,-548 104,-548 0,-463.5 0,-463.5 0,-463.5 0,-463.5 0,-105.5 0,-105.5 50.96,-68.36 85.91,-42.89"/>
|
||||
<polygon fill="black" stroke="black" points="88.38,-45.42 94.4,-36.7 84.26,-39.76 88.38,-45.42"/>
|
||||
<text text-anchor="start" x="25" y="-286.3" font-family="Times,serif" font-size="14.00">write </text>
|
||||
<text text-anchor="start" x="0" y="-271.3" font-family="Times,serif" font-size="14.00"> ~cached or hit</text>
|
||||
</g>
|
||||
<!-- WA -->
|
||||
<g id="node3" class="node">
|
||||
<title>WA</title>
|
||||
<path fill="none" stroke="black" d="M158,-444.5C158,-444.5 188,-444.5 188,-444.5 194,-444.5 200,-450.5 200,-456.5 200,-456.5 200,-468.5 200,-468.5 200,-474.5 194,-480.5 188,-480.5 188,-480.5 158,-480.5 158,-480.5 152,-480.5 146,-474.5 146,-468.5 146,-468.5 146,-456.5 146,-456.5 146,-450.5 152,-444.5 158,-444.5"/>
|
||||
<text text-anchor="middle" x="173" y="-458.8" font-family="Times,serif" font-size="14.00">WA</text>
|
||||
</g>
|
||||
<!-- IDLE->WA -->
|
||||
<g id="edge3" class="edge">
|
||||
<title>IDLE->WA</title>
|
||||
<path fill="none" stroke="black" d="M176.84,-566.37C164.57,-557.3 152,-548 152,-548 152,-548 152,-503 152,-503 152,-503 155.15,-497.07 159.01,-489.81"/>
|
||||
<polygon fill="black" stroke="black" points="162.12,-491.41 163.73,-480.94 155.94,-488.13 162.12,-491.41"/>
|
||||
<text text-anchor="start" x="169" y="-536.8" font-family="Times,serif" font-size="14.00">cached </text>
|
||||
<text text-anchor="start" x="175" y="-521.8" font-family="Times,serif" font-size="14.00"> ~hit </text>
|
||||
<text text-anchor="start" x="152" y="-506.8" font-family="Times,serif" font-size="14.00"> ~axi.addr_ok</text>
|
||||
</g>
|
||||
<!-- WD1 -->
|
||||
<g id="node4" class="node">
|
||||
<title>WD1</title>
|
||||
<path fill="none" stroke="black" d="M284,-352.5C284,-352.5 314,-352.5 314,-352.5 320,-352.5 326,-358.5 326,-364.5 326,-364.5 326,-376.5 326,-376.5 326,-382.5 320,-388.5 314,-388.5 314,-388.5 284,-388.5 284,-388.5 278,-388.5 272,-382.5 272,-376.5 272,-376.5 272,-364.5 272,-364.5 272,-358.5 278,-352.5 284,-352.5"/>
|
||||
<text text-anchor="middle" x="299" y="-366.8" font-family="Times,serif" font-size="14.00">WD1</text>
|
||||
</g>
|
||||
<!-- IDLE->WD1 -->
|
||||
<g id="edge4" class="edge">
|
||||
<title>IDLE->WD1</title>
|
||||
<path fill="none" stroke="black" d="M227.4,-573.04C254.83,-562.57 293,-548 293,-548 293,-548 311,-422 311,-422 311,-422 311,-407 311,-407 311,-407 309.79,-403.42 308.14,-398.54"/>
|
||||
<polygon fill="black" stroke="black" points="311.38,-397.19 304.86,-388.83 304.75,-399.43 311.38,-397.19"/>
|
||||
<text text-anchor="start" x="321.5" y="-473.8" font-family="Times,serif" font-size="14.00">cached </text>
|
||||
<text text-anchor="start" x="327.5" y="-458.8" font-family="Times,serif" font-size="14.00"> ~hit </text>
|
||||
<text text-anchor="start" x="308" y="-443.8" font-family="Times,serif" font-size="14.00"> axi.addr_ok</text>
|
||||
</g>
|
||||
<!-- REFILL->IDLE -->
|
||||
<g id="edge14" class="edge">
|
||||
<title>REFILL->IDLE</title>
|
||||
<path fill="none" stroke="black" d="M118,-36.9C118,-62.03 118,-105.5 118,-105.5 118,-463.5 118,-463.5 118,-463.5 118,-463.5 148,-548 148,-548 148,-548 156.48,-553.79 166.59,-560.69"/>
|
||||
<polygon fill="black" stroke="black" points="164.68,-563.63 174.91,-566.37 168.63,-557.84 164.68,-563.63"/>
|
||||
<text text-anchor="middle" x="168" y="-278.8" font-family="Times,serif" font-size="14.00">sync with dwState</text>
|
||||
</g>
|
||||
<!-- WA->IDLE -->
|
||||
<g id="edge8" class="edge">
|
||||
<title>WA->IDLE</title>
|
||||
<path fill="none" stroke="black" d="M196.96,-480.71C211.79,-491.35 228,-503 228,-503 228,-503 228,-548 228,-548 228,-548 224.59,-552.33 220.14,-557.96"/>
|
||||
<polygon fill="black" stroke="black" points="217.12,-556.15 213.67,-566.17 222.61,-560.48 217.12,-556.15"/>
|
||||
<text text-anchor="start" x="230.5" y="-529.3" font-family="Times,serif" font-size="14.00">axi.rvalid </text>
|
||||
<text text-anchor="start" x="228" y="-514.3" font-family="Times,serif" font-size="14.00">& ~cached</text>
|
||||
</g>
|
||||
<!-- WA->WA -->
|
||||
<g id="edge5" class="edge">
|
||||
<title>WA->WA</title>
|
||||
<path fill="none" stroke="black" d="M200.24,-471.49C210.02,-471.68 218,-468.69 218,-462.5 218,-458.73 215.04,-456.14 210.51,-454.74"/>
|
||||
<polygon fill="black" stroke="black" points="210.59,-451.23 200.24,-453.51 209.75,-458.18 210.59,-451.23"/>
|
||||
<text text-anchor="middle" x="254.5" y="-458.8" font-family="Times,serif" font-size="14.00">~axi.addr_ok</text>
|
||||
</g>
|
||||
<!-- WA->WD1 -->
|
||||
<g id="edge6" class="edge">
|
||||
<title>WA->WD1</title>
|
||||
<path fill="none" stroke="black" d="M197,-444.36C216.79,-430.22 245.05,-410.04 266.81,-394.49"/>
|
||||
<polygon fill="black" stroke="black" points="268.99,-397.24 275.09,-388.58 264.92,-391.54 268.99,-397.24"/>
|
||||
<text text-anchor="middle" x="277" y="-410.8" font-family="Times,serif" font-size="14.00">~axi.rvalid</text>
|
||||
</g>
|
||||
<!-- WD2 -->
|
||||
<g id="node5" class="node">
|
||||
<title>WD2</title>
|
||||
<path fill="none" stroke="black" d="M248,-264.5C248,-264.5 278,-264.5 278,-264.5 284,-264.5 290,-270.5 290,-276.5 290,-276.5 290,-288.5 290,-288.5 290,-294.5 284,-300.5 278,-300.5 278,-300.5 248,-300.5 248,-300.5 242,-300.5 236,-294.5 236,-288.5 236,-288.5 236,-276.5 236,-276.5 236,-270.5 242,-264.5 248,-264.5"/>
|
||||
<text text-anchor="middle" x="263" y="-278.8" font-family="Times,serif" font-size="14.00">WD2</text>
|
||||
</g>
|
||||
<!-- WA->WD2 -->
|
||||
<g id="edge7" class="edge">
|
||||
<title>WA->WD2</title>
|
||||
<path fill="none" stroke="black" d="M178.31,-444.39C187.88,-413.59 207,-352 207,-352 207,-352 226.53,-328.11 242.52,-308.55"/>
|
||||
<polygon fill="black" stroke="black" points="245.25,-310.74 248.87,-300.79 239.83,-306.31 245.25,-310.74"/>
|
||||
<text text-anchor="start" x="207" y="-374.3" font-family="Times,serif" font-size="14.00">axi.rvalid </text>
|
||||
<text text-anchor="start" x="208.5" y="-359.3" font-family="Times,serif" font-size="14.00">& cached</text>
|
||||
</g>
|
||||
<!-- WD1->IDLE -->
|
||||
<g id="edge9" class="edge">
|
||||
<title>WD1->IDLE</title>
|
||||
<path fill="none" stroke="black" d="M319.69,-388.79C343.98,-409.08 381,-440 381,-440 381,-440 381,-485 381,-485 381,-485 310,-548 310,-548 310,-548 268.74,-561.31 236.76,-571.64"/>
|
||||
<polygon fill="black" stroke="black" points="235.63,-568.32 227.19,-574.72 237.78,-574.98 235.63,-568.32"/>
|
||||
<text text-anchor="middle" x="439" y="-458.8" font-family="Times,serif" font-size="14.00">axi.rvalid & ~cached</text>
|
||||
</g>
|
||||
<!-- WD1->WD2 -->
|
||||
<g id="edge10" class="edge">
|
||||
<title>WD1->WD2</title>
|
||||
<path fill="none" stroke="black" d="M291.71,-352.1C286.66,-340.01 279.82,-323.68 274.09,-309.99"/>
|
||||
<polygon fill="black" stroke="black" points="277.24,-308.46 270.15,-300.58 270.78,-311.16 277.24,-308.46"/>
|
||||
<text text-anchor="middle" x="337.5" y="-322.8" font-family="Times,serif" font-size="14.00">axi.rvalid & cached</text>
|
||||
</g>
|
||||
<!-- WD3 -->
|
||||
<g id="node6" class="node">
|
||||
<title>WD3</title>
|
||||
<path fill="none" stroke="black" d="M203,-176.5C203,-176.5 233,-176.5 233,-176.5 239,-176.5 245,-182.5 245,-188.5 245,-188.5 245,-200.5 245,-200.5 245,-206.5 239,-212.5 233,-212.5 233,-212.5 203,-212.5 203,-212.5 197,-212.5 191,-206.5 191,-200.5 191,-200.5 191,-188.5 191,-188.5 191,-182.5 197,-176.5 203,-176.5"/>
|
||||
<text text-anchor="middle" x="218" y="-190.8" font-family="Times,serif" font-size="14.00">WD3</text>
|
||||
</g>
|
||||
<!-- WD2->WD3 -->
|
||||
<g id="edge11" class="edge">
|
||||
<title>WD2->WD3</title>
|
||||
<path fill="none" stroke="black" d="M253.89,-264.1C247.51,-251.89 238.86,-235.37 231.65,-221.59"/>
|
||||
<polygon fill="black" stroke="black" points="234.68,-219.82 226.94,-212.58 228.47,-223.07 234.68,-219.82"/>
|
||||
<text text-anchor="middle" x="269" y="-234.8" font-family="Times,serif" font-size="14.00">axi.rvalid</text>
|
||||
</g>
|
||||
<!-- WD4 -->
|
||||
<g id="node7" class="node">
|
||||
<title>WD4</title>
|
||||
<path fill="none" stroke="black" d="M158,-88.5C158,-88.5 188,-88.5 188,-88.5 194,-88.5 200,-94.5 200,-100.5 200,-100.5 200,-112.5 200,-112.5 200,-118.5 194,-124.5 188,-124.5 188,-124.5 158,-124.5 158,-124.5 152,-124.5 146,-118.5 146,-112.5 146,-112.5 146,-100.5 146,-100.5 146,-94.5 152,-88.5 158,-88.5"/>
|
||||
<text text-anchor="middle" x="173" y="-102.8" font-family="Times,serif" font-size="14.00">WD4</text>
|
||||
</g>
|
||||
<!-- WD3->WD4 -->
|
||||
<g id="edge12" class="edge">
|
||||
<title>WD3->WD4</title>
|
||||
<path fill="none" stroke="black" d="M208.89,-176.1C202.51,-163.89 193.86,-147.37 186.65,-133.59"/>
|
||||
<polygon fill="black" stroke="black" points="189.68,-131.82 181.94,-124.58 183.47,-135.07 189.68,-131.82"/>
|
||||
<text text-anchor="middle" x="224" y="-146.8" font-family="Times,serif" font-size="14.00">axi.rvalid</text>
|
||||
</g>
|
||||
<!-- WD4->REFILL -->
|
||||
<g id="edge13" class="edge">
|
||||
<title>WD4->REFILL</title>
|
||||
<path fill="none" stroke="black" d="M161.87,-88.1C153.99,-75.78 143.29,-59.05 134.43,-45.2"/>
|
||||
<polygon fill="black" stroke="black" points="137.26,-43.12 128.93,-36.58 131.37,-46.89 137.26,-43.12"/>
|
||||
<text text-anchor="middle" x="174" y="-58.8" font-family="Times,serif" font-size="14.00">axi.rvalid</text>
|
||||
</g>
|
||||
</g>
|
||||
</svg>
|
||||
|
Before Width: | Height: | Size: 11 KiB |
@ -1,29 +0,0 @@
|
||||
digraph dwState{
|
||||
splines=polyline
|
||||
compound=true
|
||||
node [shape=Mrecord]
|
||||
edge [arrowhead=normal]
|
||||
|
||||
IDLE -> WD1 [label="~axi.wready"]
|
||||
IDLE -> WD2 [label=<axi.wready <br/> & cached>]
|
||||
IDLE -> WB [label=<axi.wready <br/> & ~cached <br/> & ~axi.data_ok>]
|
||||
IDLE -> WAITR [label="sync with drState"]
|
||||
|
||||
WD1 -> WD2 [label=<axi.wready <br/> & cached>]
|
||||
WD1 -> WB [label=<axi.wready <br/> & ~cached <br/> & ~axi.data_ok>]
|
||||
WD1 -> IDLE [label=<axi.wready <br/> & ~cached <br/> & axi.data_ok>]
|
||||
|
||||
WD2 -> WD3 [label="axi.wready"]
|
||||
|
||||
WD3 -> WD4 [label="axi.wready"]
|
||||
|
||||
WD4 -> WB [label=<axi.wready<br/> & ~axi.data_ok>]
|
||||
WD4 -> IDLE [label="sync with drState"]
|
||||
WD4 -> WAITR [label="sync with drState"]
|
||||
|
||||
WB -> IDLE [label="sync with drState"]
|
||||
WB -> IDLE [label="sync with drState"]
|
||||
WB -> WAITR [label="sync with drState"]
|
||||
|
||||
WAITR -> IDLE [label="sync with drState"]
|
||||
}
|
||||
@ -1,176 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN"
|
||||
"http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
|
||||
<!-- Generated by graphviz version 2.48.0 (0)
|
||||
-->
|
||||
<!-- Title: dwState Pages: 1 -->
|
||||
<svg width="877pt" height="671pt"
|
||||
viewBox="0.00 0.00 877.00 671.00" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
|
||||
<g id="graph0" class="graph" transform="scale(1 1) rotate(0) translate(4 667)">
|
||||
<title>dwState</title>
|
||||
<polygon fill="white" stroke="transparent" points="-4,4 -4,-667 873,-667 873,4 -4,4"/>
|
||||
<!-- IDLE -->
|
||||
<g id="node1" class="node">
|
||||
<title>IDLE</title>
|
||||
<path fill="none" stroke="black" d="M359,-626.5C359,-626.5 389,-626.5 389,-626.5 395,-626.5 401,-632.5 401,-638.5 401,-638.5 401,-650.5 401,-650.5 401,-656.5 395,-662.5 389,-662.5 389,-662.5 359,-662.5 359,-662.5 353,-662.5 347,-656.5 347,-650.5 347,-650.5 347,-638.5 347,-638.5 347,-632.5 353,-626.5 359,-626.5"/>
|
||||
<text text-anchor="middle" x="374" y="-640.8" font-family="Times,serif" font-size="14.00">IDLE</text>
|
||||
</g>
|
||||
<!-- WD1 -->
|
||||
<g id="node2" class="node">
|
||||
<title>WD1</title>
|
||||
<path fill="none" stroke="black" d="M345,-508.5C345,-508.5 375,-508.5 375,-508.5 381,-508.5 387,-514.5 387,-520.5 387,-520.5 387,-532.5 387,-532.5 387,-538.5 381,-544.5 375,-544.5 375,-544.5 345,-544.5 345,-544.5 339,-544.5 333,-538.5 333,-532.5 333,-532.5 333,-520.5 333,-520.5 333,-514.5 339,-508.5 345,-508.5"/>
|
||||
<text text-anchor="middle" x="360" y="-522.8" font-family="Times,serif" font-size="14.00">WD1</text>
|
||||
</g>
|
||||
<!-- IDLE->WD1 -->
|
||||
<g id="edge1" class="edge">
|
||||
<title>IDLE->WD1</title>
|
||||
<path fill="none" stroke="black" d="M371.93,-626.38C369.66,-607.54 365.97,-576.97 363.3,-554.8"/>
|
||||
<polygon fill="black" stroke="black" points="366.75,-554.19 362.07,-544.69 359.8,-555.03 366.75,-554.19"/>
|
||||
<text text-anchor="middle" x="403" y="-581.8" font-family="Times,serif" font-size="14.00">~axi.wready</text>
|
||||
</g>
|
||||
<!-- WD2 -->
|
||||
<g id="node3" class="node">
|
||||
<title>WD2</title>
|
||||
<path fill="none" stroke="black" d="M554,-405.5C554,-405.5 584,-405.5 584,-405.5 590,-405.5 596,-411.5 596,-417.5 596,-417.5 596,-429.5 596,-429.5 596,-435.5 590,-441.5 584,-441.5 584,-441.5 554,-441.5 554,-441.5 548,-441.5 542,-435.5 542,-429.5 542,-429.5 542,-417.5 542,-417.5 542,-411.5 548,-405.5 554,-405.5"/>
|
||||
<text text-anchor="middle" x="569" y="-419.8" font-family="Times,serif" font-size="14.00">WD2</text>
|
||||
</g>
|
||||
<!-- IDLE->WD2 -->
|
||||
<g id="edge2" class="edge">
|
||||
<title>IDLE->WD2</title>
|
||||
<path fill="none" stroke="black" d="M401.02,-633.61C429.72,-623.11 471,-608 471,-608 471,-608 555,-490 555,-490 555,-490 559.35,-469.63 563.21,-451.61"/>
|
||||
<polygon fill="black" stroke="black" points="566.65,-452.22 565.32,-441.71 559.81,-450.76 566.65,-452.22"/>
|
||||
<text text-anchor="start" x="541" y="-530.3" font-family="Times,serif" font-size="14.00">axi.wready </text>
|
||||
<text text-anchor="start" x="544.5" y="-515.3" font-family="Times,serif" font-size="14.00"> & cached</text>
|
||||
</g>
|
||||
<!-- WB -->
|
||||
<g id="node4" class="node">
|
||||
<title>WB</title>
|
||||
<path fill="none" stroke="black" d="M356,-88.5C356,-88.5 386,-88.5 386,-88.5 392,-88.5 398,-94.5 398,-100.5 398,-100.5 398,-112.5 398,-112.5 398,-118.5 392,-124.5 386,-124.5 386,-124.5 356,-124.5 356,-124.5 350,-124.5 344,-118.5 344,-112.5 344,-112.5 344,-100.5 344,-100.5 344,-94.5 350,-88.5 356,-88.5"/>
|
||||
<text text-anchor="middle" x="371" y="-102.8" font-family="Times,serif" font-size="14.00">WB</text>
|
||||
</g>
|
||||
<!-- IDLE->WB -->
|
||||
<g id="edge3" class="edge">
|
||||
<title>IDLE->WB</title>
|
||||
<path fill="none" stroke="black" d="M346.83,-637.15C303.1,-626.94 222,-608 222,-608 222,-608 123,-527.5 123,-527.5 123,-527.5 123,-527.5 123,-208.5 123,-208.5 222,-143 222,-143 222,-143 289.7,-126.87 333.83,-116.36"/>
|
||||
<polygon fill="black" stroke="black" points="334.75,-119.73 343.67,-114.01 333.13,-112.92 334.75,-119.73"/>
|
||||
<text text-anchor="start" x="136" y="-375.8" font-family="Times,serif" font-size="14.00">axi.wready </text>
|
||||
<text text-anchor="start" x="134" y="-360.8" font-family="Times,serif" font-size="14.00"> & ~cached </text>
|
||||
<text text-anchor="start" x="123" y="-345.8" font-family="Times,serif" font-size="14.00"> & ~axi.data_ok</text>
|
||||
</g>
|
||||
<!-- WAITR -->
|
||||
<g id="node5" class="node">
|
||||
<title>WAITR</title>
|
||||
<path fill="none" stroke="black" d="M545,-0.5C545,-0.5 581,-0.5 581,-0.5 587,-0.5 593,-6.5 593,-12.5 593,-12.5 593,-24.5 593,-24.5 593,-30.5 587,-36.5 581,-36.5 581,-36.5 545,-36.5 545,-36.5 539,-36.5 533,-30.5 533,-24.5 533,-24.5 533,-12.5 533,-12.5 533,-6.5 539,-0.5 545,-0.5"/>
|
||||
<text text-anchor="middle" x="563" y="-14.8" font-family="Times,serif" font-size="14.00">WAITR</text>
|
||||
</g>
|
||||
<!-- IDLE->WAITR -->
|
||||
<g id="edge4" class="edge">
|
||||
<title>IDLE->WAITR</title>
|
||||
<path fill="none" stroke="black" d="M346.81,-638.86C290.43,-629.24 166,-608 166,-608 166,-608 0,-527.5 0,-527.5 0,-527.5 0,-527.5 0,-105.5 0,-105.5 393.36,-45.41 522.48,-25.69"/>
|
||||
<polygon fill="black" stroke="black" points="523.37,-29.09 532.73,-24.12 522.32,-22.17 523.37,-29.09"/>
|
||||
<text text-anchor="middle" x="47.5" y="-297.8" font-family="Times,serif" font-size="14.00">sync with drState</text>
|
||||
</g>
|
||||
<!-- WD1->IDLE -->
|
||||
<g id="edge7" class="edge">
|
||||
<title>WD1->IDLE</title>
|
||||
<path fill="none" stroke="black" d="M332.7,-539.32C308.84,-549.65 278,-563 278,-563 278,-563 278,-608 278,-608 278,-608 310.02,-619.84 337.07,-629.84"/>
|
||||
<polygon fill="black" stroke="black" points="336.15,-633.24 346.75,-633.42 338.58,-626.67 336.15,-633.24"/>
|
||||
<text text-anchor="start" x="287" y="-596.8" font-family="Times,serif" font-size="14.00">axi.wready </text>
|
||||
<text text-anchor="start" x="285" y="-581.8" font-family="Times,serif" font-size="14.00"> & ~cached </text>
|
||||
<text text-anchor="start" x="278" y="-566.8" font-family="Times,serif" font-size="14.00"> & axi.data_ok</text>
|
||||
</g>
|
||||
<!-- WD1->WD2 -->
|
||||
<g id="edge5" class="edge">
|
||||
<title>WD1->WD2</title>
|
||||
<path fill="none" stroke="black" d="M387.14,-511.93C425.51,-492.74 491,-460 491,-460 491,-460 512.23,-450.34 532.53,-441.1"/>
|
||||
<polygon fill="black" stroke="black" points="534.07,-444.24 541.72,-436.92 531.17,-437.87 534.07,-444.24"/>
|
||||
<text text-anchor="start" x="491" y="-478.8" font-family="Times,serif" font-size="14.00">axi.wready </text>
|
||||
<text text-anchor="start" x="494.5" y="-463.8" font-family="Times,serif" font-size="14.00"> & cached</text>
|
||||
</g>
|
||||
<!-- WD1->WB -->
|
||||
<g id="edge6" class="edge">
|
||||
<title>WD1->WB</title>
|
||||
<path fill="none" stroke="black" d="M359.4,-508.32C357.71,-459.59 353,-324 353,-324 353,-324 353,-279 353,-279 353,-279 363.07,-183.02 368.15,-134.66"/>
|
||||
<polygon fill="black" stroke="black" points="371.65,-134.88 369.21,-124.57 364.68,-134.15 371.65,-134.88"/>
|
||||
<text text-anchor="start" x="366" y="-312.8" font-family="Times,serif" font-size="14.00">axi.wready </text>
|
||||
<text text-anchor="start" x="364" y="-297.8" font-family="Times,serif" font-size="14.00"> & ~cached </text>
|
||||
<text text-anchor="start" x="353" y="-282.8" font-family="Times,serif" font-size="14.00"> & ~axi.data_ok</text>
|
||||
</g>
|
||||
<!-- WD3 -->
|
||||
<g id="node6" class="node">
|
||||
<title>WD3</title>
|
||||
<path fill="none" stroke="black" d="M560,-283.5C560,-283.5 590,-283.5 590,-283.5 596,-283.5 602,-289.5 602,-295.5 602,-295.5 602,-307.5 602,-307.5 602,-313.5 596,-319.5 590,-319.5 590,-319.5 560,-319.5 560,-319.5 554,-319.5 548,-313.5 548,-307.5 548,-307.5 548,-295.5 548,-295.5 548,-289.5 554,-283.5 560,-283.5"/>
|
||||
<text text-anchor="middle" x="575" y="-297.8" font-family="Times,serif" font-size="14.00">WD3</text>
|
||||
</g>
|
||||
<!-- WD2->WD3 -->
|
||||
<g id="edge8" class="edge">
|
||||
<title>WD2->WD3</title>
|
||||
<path fill="none" stroke="black" d="M569.86,-405.31C570.84,-385.61 572.47,-353.08 573.63,-329.89"/>
|
||||
<polygon fill="black" stroke="black" points="577.14,-329.82 574.14,-319.66 570.15,-329.47 577.14,-329.82"/>
|
||||
<text text-anchor="middle" x="602.5" y="-360.8" font-family="Times,serif" font-size="14.00">axi.wready</text>
|
||||
</g>
|
||||
<!-- WB->IDLE -->
|
||||
<g id="edge13" class="edge">
|
||||
<title>WB->IDLE</title>
|
||||
<path fill="none" stroke="black" d="M348.1,-124.63C309.58,-153.45 236,-208.5 236,-208.5 236,-527.5 236,-527.5 236,-527.5 236,-527.5 274,-608 274,-608 274,-608 308.67,-620.31 337.18,-630.43"/>
|
||||
<polygon fill="black" stroke="black" points="336.34,-633.85 346.94,-633.89 338.69,-627.25 336.34,-633.85"/>
|
||||
<text text-anchor="middle" x="283.5" y="-360.8" font-family="Times,serif" font-size="14.00">sync with drState</text>
|
||||
</g>
|
||||
<!-- WB->IDLE -->
|
||||
<g id="edge14" class="edge">
|
||||
<title>WB->IDLE</title>
|
||||
<path fill="none" stroke="black" d="M385.59,-124.63C410.12,-153.45 457,-208.5 457,-208.5 457,-527.5 457,-527.5 457,-527.5 457,-527.5 441,-608 441,-608 441,-608 426.19,-615.85 410.49,-624.17"/>
|
||||
<polygon fill="black" stroke="black" points="408.45,-621.29 401.25,-629.06 411.73,-627.47 408.45,-621.29"/>
|
||||
<text text-anchor="middle" x="504.5" y="-360.8" font-family="Times,serif" font-size="14.00">sync with drState</text>
|
||||
</g>
|
||||
<!-- WB->WAITR -->
|
||||
<g id="edge15" class="edge">
|
||||
<title>WB->WAITR</title>
|
||||
<path fill="none" stroke="black" d="M398.1,-93.36C430.74,-78.74 485.85,-54.06 523.29,-37.29"/>
|
||||
<polygon fill="black" stroke="black" points="525.18,-40.28 532.87,-32.99 522.32,-33.89 525.18,-40.28"/>
|
||||
<text text-anchor="middle" x="525.5" y="-58.8" font-family="Times,serif" font-size="14.00">sync with drState</text>
|
||||
</g>
|
||||
<!-- WAITR->IDLE -->
|
||||
<g id="edge16" class="edge">
|
||||
<title>WAITR->IDLE</title>
|
||||
<path fill="none" stroke="black" d="M593.23,-31.82C651.57,-55.6 774,-105.5 774,-105.5 774,-527.5 774,-527.5 774,-527.5 774,-527.5 554,-608 554,-608 554,-608 464.08,-625.73 411.35,-636.13"/>
|
||||
<polygon fill="black" stroke="black" points="410.47,-632.74 401.34,-638.11 411.83,-639.61 410.47,-632.74"/>
|
||||
<text text-anchor="middle" x="821.5" y="-297.8" font-family="Times,serif" font-size="14.00">sync with drState</text>
|
||||
</g>
|
||||
<!-- WD4 -->
|
||||
<g id="node7" class="node">
|
||||
<title>WD4</title>
|
||||
<path fill="none" stroke="black" d="M570,-191.5C570,-191.5 600,-191.5 600,-191.5 606,-191.5 612,-197.5 612,-203.5 612,-203.5 612,-215.5 612,-215.5 612,-221.5 606,-227.5 600,-227.5 600,-227.5 570,-227.5 570,-227.5 564,-227.5 558,-221.5 558,-215.5 558,-215.5 558,-203.5 558,-203.5 558,-197.5 564,-191.5 570,-191.5"/>
|
||||
<text text-anchor="middle" x="585" y="-205.8" font-family="Times,serif" font-size="14.00">WD4</text>
|
||||
</g>
|
||||
<!-- WD3->WD4 -->
|
||||
<g id="edge9" class="edge">
|
||||
<title>WD3->WD4</title>
|
||||
<path fill="none" stroke="black" d="M575.32,-283.26C575.61,-267.29 576,-246 576,-246 576,-246 576.91,-242.42 578.14,-237.54"/>
|
||||
<polygon fill="black" stroke="black" points="581.54,-238.39 580.61,-227.83 574.76,-236.67 581.54,-238.39"/>
|
||||
<text text-anchor="middle" x="606.5" y="-249.8" font-family="Times,serif" font-size="14.00">axi.wready</text>
|
||||
</g>
|
||||
<!-- WD4->IDLE -->
|
||||
<g id="edge11" class="edge">
|
||||
<title>WD4->IDLE</title>
|
||||
<path fill="none" stroke="black" d="M610.09,-227.63C623.38,-236.7 637,-246 637,-246 637,-246 651,-300.5 651,-300.5 651,-527.5 651,-527.5 651,-527.5 651,-527.5 500,-608 500,-608 500,-608 448.24,-622.58 411.07,-633.06"/>
|
||||
<polygon fill="black" stroke="black" points="409.71,-629.8 401.03,-635.88 411.6,-636.54 409.71,-629.8"/>
|
||||
<text text-anchor="middle" x="698.5" y="-419.8" font-family="Times,serif" font-size="14.00">sync with drState</text>
|
||||
</g>
|
||||
<!-- WD4->WB -->
|
||||
<g id="edge10" class="edge">
|
||||
<title>WD4->WB</title>
|
||||
<path fill="none" stroke="black" d="M557.81,-198.23C530.05,-187.75 491,-173 491,-173 491,-173 468,-143 468,-143 468,-143 434.97,-130.91 407.46,-120.84"/>
|
||||
<polygon fill="black" stroke="black" points="408.61,-117.54 398.02,-117.39 406.21,-124.11 408.61,-117.54"/>
|
||||
<text text-anchor="start" x="505.5" y="-161.8" font-family="Times,serif" font-size="14.00">axi.wready</text>
|
||||
<text text-anchor="start" x="491" y="-146.8" font-family="Times,serif" font-size="14.00"> & ~axi.data_ok</text>
|
||||
</g>
|
||||
<!-- WD4->WAITR -->
|
||||
<g id="edge12" class="edge">
|
||||
<title>WD4->WAITR</title>
|
||||
<path fill="none" stroke="black" d="M584.11,-191.49C582.03,-151.52 577,-55 577,-55 577,-55 575.52,-51.24 573.52,-46.17"/>
|
||||
<polygon fill="black" stroke="black" points="576.76,-44.85 569.84,-36.83 570.25,-47.42 576.76,-44.85"/>
|
||||
<text text-anchor="middle" x="627.5" y="-102.8" font-family="Times,serif" font-size="14.00">sync with drState</text>
|
||||
</g>
|
||||
</g>
|
||||
</svg>
|
||||
|
Before Width: | Height: | Size: 12 KiB |
@ -1,9 +0,0 @@
|
||||
digraph dwaState{
|
||||
splines=polyline
|
||||
compound=true
|
||||
node [shape=Mrecord]
|
||||
edge [arrowhead=normal]
|
||||
|
||||
IDLE -> WA [label=<req <br/> & ~axi.addr_ok>]
|
||||
WA -> IDLE [label="axi.addr_ok"]
|
||||
}
|
||||
@ -1,40 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN"
|
||||
"http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
|
||||
<!-- Generated by graphviz version 2.48.0 (0)
|
||||
-->
|
||||
<!-- Title: dwaState Pages: 1 -->
|
||||
<svg width="164pt" height="148pt"
|
||||
viewBox="0.00 0.00 164.00 148.00" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
|
||||
<g id="graph0" class="graph" transform="scale(1 1) rotate(0) translate(4 144)">
|
||||
<title>dwaState</title>
|
||||
<polygon fill="white" stroke="transparent" points="-4,4 -4,-144 160,-144 160,4 -4,4"/>
|
||||
<!-- IDLE -->
|
||||
<g id="node1" class="node">
|
||||
<title>IDLE</title>
|
||||
<path fill="none" stroke="black" d="M41,-103.5C41,-103.5 71,-103.5 71,-103.5 77,-103.5 83,-109.5 83,-115.5 83,-115.5 83,-127.5 83,-127.5 83,-133.5 77,-139.5 71,-139.5 71,-139.5 41,-139.5 41,-139.5 35,-139.5 29,-133.5 29,-127.5 29,-127.5 29,-115.5 29,-115.5 29,-109.5 35,-103.5 41,-103.5"/>
|
||||
<text text-anchor="middle" x="56" y="-117.8" font-family="Times,serif" font-size="14.00">IDLE</text>
|
||||
</g>
|
||||
<!-- WA -->
|
||||
<g id="node2" class="node">
|
||||
<title>WA</title>
|
||||
<path fill="none" stroke="black" d="M41,-0.5C41,-0.5 71,-0.5 71,-0.5 77,-0.5 83,-6.5 83,-12.5 83,-12.5 83,-24.5 83,-24.5 83,-30.5 77,-36.5 71,-36.5 71,-36.5 41,-36.5 41,-36.5 35,-36.5 29,-30.5 29,-24.5 29,-24.5 29,-12.5 29,-12.5 29,-6.5 35,-0.5 41,-0.5"/>
|
||||
<text text-anchor="middle" x="56" y="-14.8" font-family="Times,serif" font-size="14.00">WA</text>
|
||||
</g>
|
||||
<!-- IDLE->WA -->
|
||||
<g id="edge1" class="edge">
|
||||
<title>IDLE->WA</title>
|
||||
<path fill="none" stroke="black" d="M28.98,-103.37C14.66,-94.3 0,-85 0,-85 0,-85 0,-55 0,-55 0,-55 9.31,-49.1 20.34,-42.11"/>
|
||||
<polygon fill="black" stroke="black" points="22.41,-44.94 28.98,-36.63 18.66,-39.02 22.41,-44.94"/>
|
||||
<text text-anchor="start" x="34.5" y="-73.8" font-family="Times,serif" font-size="14.00">req </text>
|
||||
<text text-anchor="start" x="0" y="-58.8" font-family="Times,serif" font-size="14.00"> & ~axi.addr_ok</text>
|
||||
</g>
|
||||
<!-- WA->IDLE -->
|
||||
<g id="edge2" class="edge">
|
||||
<title>WA->IDLE</title>
|
||||
<path fill="none" stroke="black" d="M73.09,-36.83C81.97,-45.85 91,-55 91,-55 91,-55 91,-85 91,-85 91,-85 86.34,-89.73 80.42,-95.74"/>
|
||||
<polygon fill="black" stroke="black" points="77.62,-93.59 73.09,-103.17 82.6,-98.5 77.62,-93.59"/>
|
||||
<text text-anchor="middle" x="123.5" y="-66.3" font-family="Times,serif" font-size="14.00">axi.addr_ok</text>
|
||||
</g>
|
||||
</g>
|
||||
</svg>
|
||||
|
Before Width: | Height: | Size: 2.4 KiB |
@ -1,20 +0,0 @@
|
||||
digraph iState{
|
||||
splines=polyline
|
||||
compound=true
|
||||
node [shape=Mrecord]
|
||||
edge [arrowhead=normal]
|
||||
|
||||
IDLE -> WA [label=<cached <br/>& ~hit <br/>& ~axi.addr_ok>]
|
||||
IDLE -> WD1 [label=<cached <br/>& ~hit <br/>& axi.addr_ok>]
|
||||
|
||||
WA -> WD1 [label=<axi.addr_ok<br/>&~axi.rvalid>]
|
||||
WA -> WD2 [label=<axi.addr_ok<br/>&axi.rvalid>]
|
||||
|
||||
WD1 -> WD2 [label="axi.rvalid"]
|
||||
|
||||
WD2 -> WD3 [label=<axi.rvalid <br/>& cached>]
|
||||
WD2 -> IDLE [label=<axi.rvalid <br/>& ~cached>]
|
||||
WD3 -> WD8 [style=dashed label="axi.rvalid"]
|
||||
WD8 -> REFILL [label="sync with dwState"]
|
||||
REFILL -> IDLE
|
||||
}
|
||||
@ -1,132 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN"
|
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"http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
|
||||
<!-- Generated by graphviz version 2.48.0 (0)
|
||||
-->
|
||||
<!-- Title: iState Pages: 1 -->
|
||||
<svg width="322pt" height="641pt"
|
||||
viewBox="0.00 0.00 322.00 641.00" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
|
||||
<g id="graph0" class="graph" transform="scale(1 1) rotate(0) translate(4 637)">
|
||||
<title>iState</title>
|
||||
<polygon fill="white" stroke="transparent" points="-4,4 -4,-637 318,-637 318,4 -4,4"/>
|
||||
<!-- IDLE -->
|
||||
<g id="node1" class="node">
|
||||
<title>IDLE</title>
|
||||
<path fill="none" stroke="black" d="M169,-596.5C169,-596.5 199,-596.5 199,-596.5 205,-596.5 211,-602.5 211,-608.5 211,-608.5 211,-620.5 211,-620.5 211,-626.5 205,-632.5 199,-632.5 199,-632.5 169,-632.5 169,-632.5 163,-632.5 157,-626.5 157,-620.5 157,-620.5 157,-608.5 157,-608.5 157,-602.5 163,-596.5 169,-596.5"/>
|
||||
<text text-anchor="middle" x="184" y="-610.8" font-family="Times,serif" font-size="14.00">IDLE</text>
|
||||
</g>
|
||||
<!-- WA -->
|
||||
<g id="node2" class="node">
|
||||
<title>WA</title>
|
||||
<path fill="none" stroke="black" d="M12,-474.5C12,-474.5 42,-474.5 42,-474.5 48,-474.5 54,-480.5 54,-486.5 54,-486.5 54,-498.5 54,-498.5 54,-504.5 48,-510.5 42,-510.5 42,-510.5 12,-510.5 12,-510.5 6,-510.5 0,-504.5 0,-498.5 0,-498.5 0,-486.5 0,-486.5 0,-480.5 6,-474.5 12,-474.5"/>
|
||||
<text text-anchor="middle" x="27" y="-488.8" font-family="Times,serif" font-size="14.00">WA</text>
|
||||
</g>
|
||||
<!-- IDLE->WA -->
|
||||
<g id="edge1" class="edge">
|
||||
<title>IDLE->WA</title>
|
||||
<path fill="none" stroke="black" d="M156.83,-607.32C112.13,-597.15 28,-578 28,-578 28,-578 27.62,-545.59 27.32,-520.92"/>
|
||||
<polygon fill="black" stroke="black" points="30.82,-520.56 27.2,-510.6 23.82,-520.64 30.82,-520.56"/>
|
||||
<text text-anchor="start" x="51" y="-566.8" font-family="Times,serif" font-size="14.00">cached </text>
|
||||
<text text-anchor="start" x="51.5" y="-551.8" font-family="Times,serif" font-size="14.00">& ~hit </text>
|
||||
<text text-anchor="start" x="28" y="-536.8" font-family="Times,serif" font-size="14.00">& ~axi.addr_ok</text>
|
||||
</g>
|
||||
<!-- WD1 -->
|
||||
<g id="node3" class="node">
|
||||
<title>WD1</title>
|
||||
<path fill="none" stroke="black" d="M115,-367.5C115,-367.5 145,-367.5 145,-367.5 151,-367.5 157,-373.5 157,-379.5 157,-379.5 157,-391.5 157,-391.5 157,-397.5 151,-403.5 145,-403.5 145,-403.5 115,-403.5 115,-403.5 109,-403.5 103,-397.5 103,-391.5 103,-391.5 103,-379.5 103,-379.5 103,-373.5 109,-367.5 115,-367.5"/>
|
||||
<text text-anchor="middle" x="130" y="-381.8" font-family="Times,serif" font-size="14.00">WD1</text>
|
||||
</g>
|
||||
<!-- IDLE->WD1 -->
|
||||
<g id="edge2" class="edge">
|
||||
<title>IDLE->WD1</title>
|
||||
<path fill="none" stroke="black" d="M177.03,-596.34C165.57,-568.12 144,-515 144,-515 144,-515 137.1,-451.64 132.99,-413.91"/>
|
||||
<polygon fill="black" stroke="black" points="136.42,-413.13 131.86,-403.56 129.46,-413.88 136.42,-413.13"/>
|
||||
<text text-anchor="start" x="163" y="-503.8" font-family="Times,serif" font-size="14.00">cached </text>
|
||||
<text text-anchor="start" x="163.5" y="-488.8" font-family="Times,serif" font-size="14.00">& ~hit </text>
|
||||
<text text-anchor="start" x="144" y="-473.8" font-family="Times,serif" font-size="14.00">& axi.addr_ok</text>
|
||||
</g>
|
||||
<!-- WA->WD1 -->
|
||||
<g id="edge3" class="edge">
|
||||
<title>WA->WD1</title>
|
||||
<path fill="none" stroke="black" d="M31.45,-474.32C36.78,-453.74 45,-422 45,-422 45,-422 70.33,-411.42 93.33,-401.81"/>
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<polygon fill="black" stroke="black" points="94.76,-405.01 102.64,-397.93 92.06,-398.55 94.76,-405.01"/>
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<text text-anchor="start" x="48" y="-440.8" font-family="Times,serif" font-size="14.00">axi.addr_ok</text>
|
||||
<text text-anchor="start" x="45" y="-425.8" font-family="Times,serif" font-size="14.00">&~axi.rvalid</text>
|
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</g>
|
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<!-- WD2 -->
|
||||
<g id="node4" class="node">
|
||||
<title>WD2</title>
|
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<path fill="none" stroke="black" d="M157,-279.5C157,-279.5 187,-279.5 187,-279.5 193,-279.5 199,-285.5 199,-291.5 199,-291.5 199,-303.5 199,-303.5 199,-309.5 193,-315.5 187,-315.5 187,-315.5 157,-315.5 157,-315.5 151,-315.5 145,-309.5 145,-303.5 145,-303.5 145,-291.5 145,-291.5 145,-285.5 151,-279.5 157,-279.5"/>
|
||||
<text text-anchor="middle" x="172" y="-293.8" font-family="Times,serif" font-size="14.00">WD2</text>
|
||||
</g>
|
||||
<!-- WA->WD2 -->
|
||||
<g id="edge4" class="edge">
|
||||
<title>WA->WD2</title>
|
||||
<path fill="none" stroke="black" d="M27.27,-474.45C27.82,-440.35 29,-367 29,-367 29,-367 93.2,-336.25 135.57,-315.95"/>
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<polygon fill="black" stroke="black" points="137.26,-319.02 144.77,-311.55 134.24,-312.71 137.26,-319.02"/>
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<text text-anchor="start" x="29" y="-389.3" font-family="Times,serif" font-size="14.00">axi.addr_ok</text>
|
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<text text-anchor="start" x="29.5" y="-374.3" font-family="Times,serif" font-size="14.00">&axi.rvalid</text>
|
||||
</g>
|
||||
<!-- WD1->WD2 -->
|
||||
<g id="edge5" class="edge">
|
||||
<title>WD1->WD2</title>
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<path fill="none" stroke="black" d="M138.5,-367.1C144.46,-354.89 152.53,-338.37 159.26,-324.59"/>
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<polygon fill="black" stroke="black" points="162.41,-326.11 163.66,-315.58 156.12,-323.03 162.41,-326.11"/>
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<text text-anchor="middle" x="179" y="-337.8" font-family="Times,serif" font-size="14.00">axi.rvalid</text>
|
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</g>
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<!-- WD2->IDLE -->
|
||||
<g id="edge7" class="edge">
|
||||
<title>WD2->IDLE</title>
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<path fill="none" stroke="black" d="M190.07,-315.83C199.46,-324.85 209,-334 209,-334 209,-334 224,-470 224,-470 224,-470 224,-515 224,-515 224,-515 206.59,-557.88 194.74,-587.06"/>
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<polygon fill="black" stroke="black" points="191.49,-585.76 190.97,-596.34 197.97,-588.39 191.49,-585.76"/>
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<text text-anchor="start" x="223.5" y="-440.8" font-family="Times,serif" font-size="14.00">axi.rvalid </text>
|
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<text text-anchor="start" x="221" y="-425.8" font-family="Times,serif" font-size="14.00">& ~cached</text>
|
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</g>
|
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<!-- WD3 -->
|
||||
<g id="node5" class="node">
|
||||
<title>WD3</title>
|
||||
<path fill="none" stroke="black" d="M178,-176.5C178,-176.5 208,-176.5 208,-176.5 214,-176.5 220,-182.5 220,-188.5 220,-188.5 220,-200.5 220,-200.5 220,-206.5 214,-212.5 208,-212.5 208,-212.5 178,-212.5 178,-212.5 172,-212.5 166,-206.5 166,-200.5 166,-200.5 166,-188.5 166,-188.5 166,-182.5 172,-176.5 178,-176.5"/>
|
||||
<text text-anchor="middle" x="193" y="-190.8" font-family="Times,serif" font-size="14.00">WD3</text>
|
||||
</g>
|
||||
<!-- WD2->WD3 -->
|
||||
<g id="edge6" class="edge">
|
||||
<title>WD2->WD3</title>
|
||||
<path fill="none" stroke="black" d="M175.56,-279.37C178.79,-263.84 183.6,-240.7 187.35,-222.66"/>
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<polygon fill="black" stroke="black" points="190.81,-223.22 189.42,-212.72 183.96,-221.8 190.81,-223.22"/>
|
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<text text-anchor="start" x="185" y="-249.8" font-family="Times,serif" font-size="14.00">axi.rvalid </text>
|
||||
<text text-anchor="start" x="186.5" y="-234.8" font-family="Times,serif" font-size="14.00">& cached</text>
|
||||
</g>
|
||||
<!-- WD8 -->
|
||||
<g id="node6" class="node">
|
||||
<title>WD8</title>
|
||||
<path fill="none" stroke="black" d="M183,-88.5C183,-88.5 213,-88.5 213,-88.5 219,-88.5 225,-94.5 225,-100.5 225,-100.5 225,-112.5 225,-112.5 225,-118.5 219,-124.5 213,-124.5 213,-124.5 183,-124.5 183,-124.5 177,-124.5 171,-118.5 171,-112.5 171,-112.5 171,-100.5 171,-100.5 171,-94.5 177,-88.5 183,-88.5"/>
|
||||
<text text-anchor="middle" x="198" y="-102.8" font-family="Times,serif" font-size="14.00">WD8</text>
|
||||
</g>
|
||||
<!-- WD3->WD8 -->
|
||||
<g id="edge8" class="edge">
|
||||
<title>WD3->WD8</title>
|
||||
<path fill="none" stroke="black" stroke-dasharray="5,2" d="M194.01,-176.1C194.7,-164.25 195.63,-148.32 196.41,-134.79"/>
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<polygon fill="black" stroke="black" points="199.92,-134.77 197.01,-124.58 192.93,-134.36 199.92,-134.77"/>
|
||||
<text text-anchor="middle" x="221" y="-146.8" font-family="Times,serif" font-size="14.00">axi.rvalid</text>
|
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</g>
|
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<!-- REFILL -->
|
||||
<g id="node7" class="node">
|
||||
<title>REFILL</title>
|
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<path fill="none" stroke="black" d="M237,-0.5C237,-0.5 275,-0.5 275,-0.5 281,-0.5 287,-6.5 287,-12.5 287,-12.5 287,-24.5 287,-24.5 287,-30.5 281,-36.5 275,-36.5 275,-36.5 237,-36.5 237,-36.5 231,-36.5 225,-30.5 225,-24.5 225,-24.5 225,-12.5 225,-12.5 225,-6.5 231,-0.5 237,-0.5"/>
|
||||
<text text-anchor="middle" x="256" y="-14.8" font-family="Times,serif" font-size="14.00">REFILL</text>
|
||||
</g>
|
||||
<!-- WD8->REFILL -->
|
||||
<g id="edge9" class="edge">
|
||||
<title>WD8->REFILL</title>
|
||||
<path fill="none" stroke="black" d="M198.68,-88.4C199.26,-73.75 200,-55 200,-55 200,-55 209.31,-49.1 220.34,-42.11"/>
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<polygon fill="black" stroke="black" points="222.41,-44.94 228.98,-36.63 218.66,-39.02 222.41,-44.94"/>
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<text text-anchor="middle" x="250" y="-58.8" font-family="Times,serif" font-size="14.00">sync with dwState</text>
|
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</g>
|
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<!-- REFILL->IDLE -->
|
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<g id="edge10" class="edge">
|
||||
<title>REFILL->IDLE</title>
|
||||
<path fill="none" stroke="black" d="M277.23,-36.63C288.48,-45.7 300,-55 300,-55 300,-55 314,-105.5 314,-105.5 314,-493.5 314,-493.5 314,-493.5 314,-493.5 248.26,-554.19 210.28,-589.25"/>
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<polygon fill="black" stroke="black" points="207.6,-586.95 202.63,-596.31 212.35,-592.1 207.6,-586.95"/>
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</g>
|
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</g>
|
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</svg>
|
||||
|
Before Width: | Height: | Size: 8.8 KiB |
7
resources/project/.gitignore
vendored
7
resources/project/.gitignore
vendored
@ -1,7 +0,0 @@
|
||||
.idea/
|
||||
obj/
|
||||
*.a
|
||||
*.o
|
||||
bin.lds
|
||||
convert
|
||||
compile_commands.json
|
||||
@ -1,69 +0,0 @@
|
||||
CROSS_COMPILE ?= mipsel-linux-gnu-
|
||||
CC = ${CROSS_COMPILE}gcc
|
||||
LD = ${CROSS_COMPILE}ld
|
||||
OBJCOPY = ${CROSS_COMPILE}objcopy
|
||||
OBJDUMP = ${CROSS_COMPILE}objdump
|
||||
AR = ${CROSS_COMPILE}ar
|
||||
|
||||
CFLAGS = -O3 -fno-pic -mno-branch-likely -mno-abicalls -msoft-float -fno-builtin -mno-shared -mips1 -EL -nostdinc -nostdlib
|
||||
|
||||
OBJ_DIR = obj
|
||||
|
||||
USER_DIR = src
|
||||
USER_OBJ_DIR = obj/user
|
||||
USER_SRC = $(wildcard $(USER_DIR)/*.S) $(wildcard $(USER_DIR)/*.c)
|
||||
USER_OBJ := $(patsubst $(USER_DIR)/%.S, $(USER_OBJ_DIR)/%.o, $(USER_SRC))
|
||||
USER_OBJ := $(patsubst $(USER_DIR)/%.c, $(USER_OBJ_DIR)/%.o, $(USER_OBJ))
|
||||
|
||||
TINY_C_DIR = lib
|
||||
TINY_C_OBJ_DIR = obj/tinyc
|
||||
TINY_C_SRC = $(wildcard $(TINY_C_DIR)/*.S) $(wildcard $(TINY_C_DIR)/*.c)
|
||||
TINY_C_OBJ := $(patsubst $(TINY_C_DIR)/%.S, $(TINY_C_OBJ_DIR)/%.o, $(TINY_C_SRC))
|
||||
TINY_C_OBJ := $(patsubst $(TINY_C_DIR)/%.c, $(TINY_C_OBJ_DIR)/%.o, $(TINY_C_OBJ))
|
||||
TINY_C_TARGET = $(TINY_C_OBJ_DIR)/libtinyc.a
|
||||
|
||||
default: all
|
||||
|
||||
%.o : %.S
|
||||
$(CC) -c -I include $(CFLAGS) -o $@ $<
|
||||
|
||||
%.o : %.c
|
||||
$(CC) -c -I include $(CFLAGS) -o $@ $<
|
||||
|
||||
$(TINY_C_TARGET): $(TINY_C_OBJ)
|
||||
$(AR) -cr $@ $^
|
||||
|
||||
bin.lds: bin.lds.S
|
||||
$(CC) -EL -E -P -o $@ $<
|
||||
|
||||
main.elf: start.o bin.lds $(TINY_C_TARGET) $(USER_OBJ)
|
||||
$(LD) -g -EL -T bin.lds start.o $(USER_OBJ) $(TINY_C_TARGET) -o $(OBJ_DIR)/$@
|
||||
$(OBJDUMP) -alD $(OBJ_DIR)/$@ > $(OBJ_DIR)/test.s
|
||||
|
||||
axi_ram.bin: main.elf
|
||||
$(OBJCOPY) -O binary -j .text -j .data $(OBJ_DIR)/$< $(OBJ_DIR)/$@
|
||||
|
||||
all: env convert axi_ram.bin
|
||||
./convert axi_ram.bin $(OBJ_DIR)/
|
||||
|
||||
convert: convert.c
|
||||
clang -o convert convert.c
|
||||
|
||||
env:
|
||||
mkdir -p $(USER_OBJ_DIR)
|
||||
mkdir -p $(TINY_C_OBJ_DIR)
|
||||
|
||||
clean:
|
||||
rm -f *.o *.bin *.elf *.a testbin *.s *.vlog *.coe *.data *.mif
|
||||
rm -f bin.lds convert
|
||||
rm -rf obj
|
||||
|
||||
help:
|
||||
@echo "####################################################################"
|
||||
@echo "### help for compiling our awesome project ###"
|
||||
@echo "####################################################################"
|
||||
@echo "### options: ###"
|
||||
@echo "### make : get compiled result, which is saved in ./obj ###"
|
||||
@echo "### make clean: remove *.o, *.a, and ./obj ###"
|
||||
@echo "### make help : show help information ###"
|
||||
@echo "####################################################################"
|
||||
@ -1,54 +0,0 @@
|
||||
ENTRY(_init)
|
||||
OUTPUT("main.elf")
|
||||
OUTPUT_ARCH("mips:isa32r2")
|
||||
OUTPUT_FORMAT("elf32-tradlittlemips")
|
||||
|
||||
PROVIDE(MEM_SIZE = 0x88000000);
|
||||
SECTIONS
|
||||
{
|
||||
/* SPI-FLASH mapped to bfc0_0000 */
|
||||
. = 0x80000000;
|
||||
.text : {
|
||||
*(.text.init)
|
||||
|
||||
. = 0x380;
|
||||
*(.text.exception)
|
||||
|
||||
. = 0x1000;
|
||||
_text_ebase_begin = .;
|
||||
*(.text.ebase)
|
||||
_text_ebase_end = .;
|
||||
|
||||
. = ALIGN(0x1000);
|
||||
_text_code_begin = .;
|
||||
*(.text)
|
||||
_text_code_end = .;
|
||||
}
|
||||
|
||||
/* . = 0x807F0000; */
|
||||
.data : {
|
||||
*(.rodata*)
|
||||
*(.data)
|
||||
_gp = ALIGN(16) + 0x7ff0;
|
||||
*(.got.plt) *(.got)
|
||||
*(.sdata) *(.sdata.*) *(.lit8) *(.lit4)
|
||||
. = ALIGN(16);
|
||||
}
|
||||
.bss : {
|
||||
_sbss = .;
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = .;
|
||||
}
|
||||
|
||||
. = ALIGN(0x1000);
|
||||
_heap = . ;
|
||||
|
||||
_stack = MEM_SIZE - 4;
|
||||
|
||||
|
||||
/DISCARD/ : {
|
||||
*(.MIPS.abiflags)
|
||||
}
|
||||
}
|
||||
@ -1,84 +0,0 @@
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
|
||||
void binary_out(FILE* out,unsigned char* mem)
|
||||
{
|
||||
char tmp;
|
||||
unsigned char num[8];
|
||||
num[0] = 1;
|
||||
num[1] = 2;
|
||||
num[2] = 4;
|
||||
num[3] = 8;
|
||||
num[4] = 16;
|
||||
num[5] = 32;
|
||||
num[6] = 64;
|
||||
num[7] = 128;
|
||||
for(int i=3;i>=0;i--)
|
||||
{
|
||||
for(int j=7;j>=0;j--)
|
||||
{
|
||||
if( (mem[i] & num[j] ) != 0)
|
||||
tmp = '1';
|
||||
else
|
||||
tmp = '0';
|
||||
fprintf(out,"%c",tmp);
|
||||
}
|
||||
}
|
||||
fprintf(out,"\n");
|
||||
return;
|
||||
}
|
||||
|
||||
int main(int argc, char** argv)
|
||||
{
|
||||
FILE *in;
|
||||
FILE *out;
|
||||
|
||||
if(argc < 3){
|
||||
fprintf(stderr, "Usage: convert main.bin main.data directory\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
char str_bin[256];
|
||||
char str_coe[256], str_mif[256];
|
||||
strncpy(str_bin, argv[2], 256);
|
||||
strncpy(str_coe, argv[2], 256);
|
||||
strncpy(str_mif, argv[2], 256);
|
||||
strncat(str_bin, argv[1], 256);
|
||||
strncat(str_coe, "axi_ram.coe", 256);
|
||||
strncat(str_mif, "axi_ram.mif", 256);
|
||||
//printf("%s\n%s\n%s\n%s\n%s\n%s\n", str_bin, str_data, str_inst_coe, str_inst_mif, str_data_coe, str_data_mif);
|
||||
|
||||
int i,j,k;
|
||||
unsigned char mem[32];
|
||||
|
||||
in = fopen(str_bin, "rb");
|
||||
out = fopen(str_coe,"w");
|
||||
|
||||
fprintf(out, "memory_initialization_radix = 16;\n");
|
||||
fprintf(out, "memory_initialization_vector =\n");
|
||||
while(!feof(in)) {
|
||||
if(fread(mem,1,4,in)!=4) {
|
||||
fprintf(out, "%02x%02x%02x%02x\n", mem[3], mem[2], mem[1], mem[0]);
|
||||
break;
|
||||
}
|
||||
fprintf(out, "%02x%02x%02x%02x\n", mem[3], mem[2], mem[1],mem[0]);
|
||||
}
|
||||
fclose(in);
|
||||
fclose(out);
|
||||
|
||||
in = fopen(str_bin, "rb");
|
||||
out = fopen(str_mif,"w");
|
||||
|
||||
while(!feof(in)) {
|
||||
if(fread(mem,1,4,in)!=4) {
|
||||
binary_out(out,mem);
|
||||
break;
|
||||
}
|
||||
binary_out(out,mem);
|
||||
}
|
||||
fclose(in);
|
||||
fclose(out);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1,254 +0,0 @@
|
||||
/* $OpenBSD: asm.h,v 1.2 1998/03/16 09:03:02 pefo Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1992, 1993
|
||||
* The Regents of the University of California. All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to Berkeley by
|
||||
* Ralph Campbell.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by the University of
|
||||
* California, Berkeley and its contributors.
|
||||
* 4. Neither the name of the University nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* Copyright (C) 1989 Digital Equipment Corporation.
|
||||
* Permission to use, copy, modify, and distribute this software and
|
||||
* its documentation for any purpose and without fee is hereby granted,
|
||||
* provided that the above copyright notice appears in all copies.
|
||||
* Digital Equipment Corporation makes no representations about the
|
||||
* suitability of this software for any purpose. It is provided "as is"
|
||||
* without express or implied warranty.
|
||||
*/
|
||||
|
||||
#ifndef _MIPS_ASM_H
|
||||
#define _MIPS_ASM_H
|
||||
|
||||
#include <asm/regdef.h>
|
||||
|
||||
#ifndef ABICALLS
|
||||
#define ABICALLS .abicalls
|
||||
#endif
|
||||
|
||||
#if defined(ABICALLS) && !defined(_KERNEL)
|
||||
ABICALLS
|
||||
#endif
|
||||
|
||||
#define RCSID(x)
|
||||
|
||||
/*
|
||||
* Define how to access unaligned data word
|
||||
*/
|
||||
#if defined(__MIPSEL__)
|
||||
#define LWLO lwl
|
||||
#define LWHI lwr
|
||||
#define SWLO swl
|
||||
#define SWHI swr
|
||||
#else
|
||||
#if defined(__MIPSEB__)
|
||||
#define LWLO lwr
|
||||
#define LWHI lwl
|
||||
#define SWLO swr
|
||||
#define SWHI swl
|
||||
#else
|
||||
#error "__MIPSEL__ or __MIPSEB__ must be defined"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Code for setting gp reg if abicalls are used.
|
||||
*/
|
||||
#if defined(ABICALLS) && !defined(_KERNEL)
|
||||
#define ABISETUP \
|
||||
.set noreorder; \
|
||||
.cpload t9; \
|
||||
.set reorder;
|
||||
#else
|
||||
#define ABISETUP
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Define -pg profile entry code.
|
||||
*/
|
||||
#if defined(GPROF) || defined(PROF)
|
||||
#define MCOUNT \
|
||||
subu sp, sp, 32; \
|
||||
.cprestore 16; \
|
||||
sw ra, 28(sp); \
|
||||
sw gp, 24(sp); \
|
||||
.set noat; \
|
||||
.set noreorder; \
|
||||
move AT, ra; \
|
||||
jal _mcount; \
|
||||
subu sp, sp, 8; \
|
||||
lw ra, 28(sp); \
|
||||
addu sp, sp, 32; \
|
||||
.set reorder; \
|
||||
.set at;
|
||||
#else
|
||||
#define MCOUNT
|
||||
#endif
|
||||
|
||||
/*
|
||||
* LEAF(x)
|
||||
*
|
||||
* Declare a leaf routine.
|
||||
*/
|
||||
#define LEAF(x) \
|
||||
.align 3; \
|
||||
.globl x; \
|
||||
.ent x, 0; \
|
||||
x: ; \
|
||||
.frame sp, 0, ra; \
|
||||
ABISETUP \
|
||||
MCOUNT
|
||||
|
||||
#define ALEAF(x) \
|
||||
.globl x; \
|
||||
x:
|
||||
|
||||
/*
|
||||
* NLEAF(x)
|
||||
*
|
||||
* Declare a non-profiled leaf routine.
|
||||
*/
|
||||
#define NLEAF(x) \
|
||||
.align 3; \
|
||||
.globl x; \
|
||||
.ent x, 0; \
|
||||
x: ; \
|
||||
.frame sp, 0, ra; \
|
||||
ABISETUP
|
||||
|
||||
/*
|
||||
* NON_LEAF(x)
|
||||
*
|
||||
* Declare a non-leaf routine (a routine that makes other C calls).
|
||||
*/
|
||||
#define NON_LEAF(x, fsize, retpc) \
|
||||
.align 3; \
|
||||
.globl x; \
|
||||
.ent x, 0; \
|
||||
x: ; \
|
||||
.frame sp, fsize, retpc; \
|
||||
ABISETUP \
|
||||
MCOUNT
|
||||
|
||||
/*
|
||||
* NNON_LEAF(x)
|
||||
*
|
||||
* Declare a non-profiled non-leaf routine
|
||||
* (a routine that makes other C calls).
|
||||
*/
|
||||
#define NNON_LEAF(x, fsize, retpc) \
|
||||
.align 3; \
|
||||
.globl x; \
|
||||
.ent x, 0; \
|
||||
x: ; \
|
||||
.frame sp, fsize, retpc \
|
||||
ABISETUP
|
||||
|
||||
/*
|
||||
* END(x)
|
||||
*
|
||||
* Mark end of a procedure.
|
||||
*/
|
||||
#define END(x) \
|
||||
.end x
|
||||
|
||||
/*
|
||||
* Macros to panic and printf from assembly language.
|
||||
*/
|
||||
#define PANIC(msg) \
|
||||
la a0, 9f; \
|
||||
jal panic; \
|
||||
MSG(msg)
|
||||
|
||||
#define PRINTF(msg) \
|
||||
la a0, 9f; \
|
||||
jal printf; \
|
||||
MSG(msg)
|
||||
|
||||
#define MSG(msg) \
|
||||
.rdata; \
|
||||
9: .asciiz msg; \
|
||||
.text
|
||||
|
||||
#define ASMSTR(str) \
|
||||
.asciiz str; \
|
||||
.align 3
|
||||
|
||||
#if (_MIPS_SZPTR == 32)
|
||||
#define PTR_ADD add
|
||||
#define PTR_ADDU addu
|
||||
#define PTR_ADDI addi
|
||||
#define PTR_ADDIU addiu
|
||||
#define PTR_SUB sub
|
||||
#define PTR_SUBU subu
|
||||
#define PTR_L lw
|
||||
#define PTR_S sw
|
||||
#define PTR_LA la
|
||||
#define PTR_LI li
|
||||
#define PTR_SLL sll
|
||||
#define PTR_SLLV sllv
|
||||
#define PTR_SRL srl
|
||||
#define PTR_SRLV srlv
|
||||
#define PTR_SRA sra
|
||||
#define PTR_SRAV srav
|
||||
|
||||
#define PTR_SCALESHIFT 2
|
||||
|
||||
#define PTR .word
|
||||
#define PTRSIZE 4
|
||||
#define PTRLOG 2
|
||||
#endif
|
||||
|
||||
#if (_MIPS_SZPTR == 64)
|
||||
#define PTR_ADD dadd
|
||||
#define PTR_ADDU daddu
|
||||
#define PTR_ADDI daddi
|
||||
#define PTR_ADDIU daddiu
|
||||
#define PTR_SUB dsub
|
||||
#define PTR_SUBU dsubu
|
||||
#define PTR_L ld
|
||||
#define PTR_S sd
|
||||
#define PTR_LA dla
|
||||
#define PTR_LI dli
|
||||
#define PTR_SLL dsll
|
||||
#define PTR_SLLV dsllv
|
||||
#define PTR_SRL dsrl
|
||||
#define PTR_SRLV dsrlv
|
||||
#define PTR_SRA dsra
|
||||
#define PTR_SRAV dsrav
|
||||
|
||||
#define PTR_SCALESHIFT 3
|
||||
|
||||
#define PTR .dword
|
||||
#define PTRSIZE 8
|
||||
#define PTRLOG 3
|
||||
#endif
|
||||
|
||||
#endif /* !_MIPS_ASM_H */
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,113 +0,0 @@
|
||||
/* $OpenBSD: regdef.h,v 1.3 1999/01/27 04:46:06 imp Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1992, 1993
|
||||
* The Regents of the University of California. All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to Berkeley by
|
||||
* Ralph Campbell. This file is derived from the MIPS RISC
|
||||
* Architecture book by Gerry Kane.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by the University of
|
||||
* California, Berkeley and its contributors.
|
||||
* 4. Neither the name of the University nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* @(#)regdef.h 8.1 (Berkeley) 6/10/93
|
||||
*/
|
||||
#ifndef _MIPS_REGDEF_H_
|
||||
#define _MIPS_REGDEF_H_
|
||||
|
||||
#define zero $0 /* always zero */
|
||||
#define AT $at /* assembler temp */
|
||||
#define v0 $2 /* return value */
|
||||
#define v1 $3
|
||||
#define a0 $4 /* argument registers */
|
||||
#define a1 $5
|
||||
#define a2 $6
|
||||
#define a3 $7
|
||||
#define t0 $8 /* temp registers (not saved across subroutine calls) */
|
||||
#define t1 $9
|
||||
#define t2 $10
|
||||
#define t3 $11
|
||||
#define t4 $12
|
||||
#define t5 $13
|
||||
#define t6 $14
|
||||
#define t7 $15
|
||||
#define s0 $16 /* saved across subroutine calls (callee saved) */
|
||||
#define s1 $17
|
||||
#define s2 $18
|
||||
#define s3 $19
|
||||
#define s4 $20
|
||||
#define s5 $21
|
||||
#define s6 $22
|
||||
#define s7 $23
|
||||
#define t8 $24 /* two more temp registers */
|
||||
#define t9 $25
|
||||
#define k0 $26 /* kernel temporary */
|
||||
#define k1 $27
|
||||
#define gp $28 /* global pointer */
|
||||
#define sp $29 /* stack pointer */
|
||||
#define s8 $30 /* one more callee saved */
|
||||
#define ra $31 /* return address */
|
||||
#define fp $30
|
||||
|
||||
#define c0_index $0
|
||||
#define c0_random $1
|
||||
#define c0_entrylo0 $2
|
||||
#define c0_entrylo1 $3
|
||||
#define c0_conf $3
|
||||
#define c0_context $4
|
||||
#define c0_pagemask $5
|
||||
#define c0_wired $6
|
||||
#define c0_info $7
|
||||
#define c0_badvaddr $8
|
||||
#define c0_count $9
|
||||
#define c0_entryhi $10
|
||||
#define c0_compare $11
|
||||
#define c0_status $12
|
||||
#define c0_cause $13
|
||||
#define c0_epc $14
|
||||
#define c0_prid $15
|
||||
#define c0_config $16
|
||||
#define c0_lladdr $17
|
||||
#define c0_watchlo $18
|
||||
#define c0_watchhi $19
|
||||
#define c0_xcontext $20
|
||||
#define c0_framemask $21
|
||||
#define c0_diagnostic $22
|
||||
#define c0_debug $23
|
||||
#define c0_depc $24
|
||||
#define c0_performance $25
|
||||
#define c0_ecc $26
|
||||
#define c0_cacheerr $27
|
||||
#define c0_taglo $28
|
||||
#define c0_taghi $29
|
||||
#define c0_errorepc $30
|
||||
#define c0_desave $31
|
||||
|
||||
|
||||
#endif /* !_MIPS_REGDEF_H_ */
|
||||
@ -1,35 +0,0 @@
|
||||
//soc confreg
|
||||
|
||||
#define CONFREG_CR0 0xbfd00000
|
||||
#define CONFREG_CR1 0xbfd00004
|
||||
#define CONFREG_CR2 0xbfd00008
|
||||
#define CONFREG_CR3 0xbfd0000c
|
||||
#define CONFREG_CR4 0xbfd00010
|
||||
#define CONFREG_CR5 0xbfd00014
|
||||
#define CONFREG_CR6 0xbfd00018
|
||||
#define CONFREG_CR7 0xbfd0001c
|
||||
|
||||
#define UART_ADDR 0xbfe40000
|
||||
#define LED_ADDR 0xbfd0f000
|
||||
#define LED_RG0_ADDR 0xbfd0f004
|
||||
#define LED_RG1_ADDR 0xbfd0f008
|
||||
#define NUM_ADDR 0xbfd0f010
|
||||
#define SWITCH_ADDR 0xbfd0f020
|
||||
#define BTN_KEY_ADDR 0xbfd0f024
|
||||
#define BTN_STEP_ADDR 0xbfd0f028
|
||||
#define TIMER_ADDR 0xbfd0e000
|
||||
|
||||
#define SOC_LED (* (volatile unsigned *) LED_ADDR )
|
||||
#define SOC_LED_RG0 (* (volatile unsigned *) LED_RG0_ADDR )
|
||||
#define SOC_LED_RG1 (* (volatile unsigned *) LED_RG1_ADDR )
|
||||
#define SOC_NUM (* (volatile unsigned *) NUM_ADDR )
|
||||
#define SOC_SWITCHE (* (volatile unsigned *) SWITCH_ADDR )
|
||||
#define SOC_BTN_KEY (* (volatile unsigned *) BTN_KEY_ADDR )
|
||||
#define SOC_BTN_STEP (* (volatile unsigned *) BTN_STEP_ADDR )
|
||||
#define SOC_TIMER (* (volatile unsigned *) TIMER_ADDR )
|
||||
|
||||
#define write_confreg_cr(num,data) *((volatile int *)(CONFREG_CR0+4*num)) = data
|
||||
#define read_confreg_cr(num,data) data=*((volatile int *)(CONFREG_CR0+4*num))
|
||||
#define NOP addu zero, zero, zero
|
||||
#define LI(reg, imm) \
|
||||
li reg, imm
|
||||
@ -1,13 +0,0 @@
|
||||
#ifndef PROJECT_INCLUDE_TINY_H_
|
||||
#define PROJECT_INCLUDE_TINY_H_
|
||||
|
||||
void WRITESERIAL(char);
|
||||
char READSERIAL();
|
||||
unsigned READSERIALWORD();
|
||||
|
||||
char* itoa(int num, char* str, int base);
|
||||
int putchar(char c);
|
||||
int vsprintf(char* buf, const char* fmt, va_list args);
|
||||
int printf(const char* fmt, ...);
|
||||
|
||||
#endif //PROJECT_INCLUDE_TINY_H_
|
||||
@ -1,79 +0,0 @@
|
||||
#include <asm/asm.h>
|
||||
#include <asm/regdef.h>
|
||||
#include <cpu_cde.h>
|
||||
|
||||
.text
|
||||
.set noreorder
|
||||
.set noat
|
||||
.p2align 2
|
||||
.global WRITESERIAL
|
||||
.global READSERIAL
|
||||
.global READSERIALWORD
|
||||
|
||||
WRITESERIAL: // 写串口：将a0的低八位写入串口
|
||||
li t1, UART_ADDR
|
||||
.TESTW:
|
||||
lb t0, 5(t1) // 查看串口状态, LSR
|
||||
andi t0, t0, 0x20 // 截取写状态位, TXRDY
|
||||
beq t0, zero, .TESTW // 状态位为零则循环检测
|
||||
nop
|
||||
.WSERIAL: // 否则可写入
|
||||
sb a0, 0(t1) // 写入, DATA
|
||||
jr ra
|
||||
nop
|
||||
|
||||
READSERIAL: // 读串口：将读到的数据写入v0低八位
|
||||
li t1, UART_ADDR
|
||||
.TESTR:
|
||||
lb t0, 5(t1) // 查看串口状态, LSR
|
||||
andi t0, t0, 0x01 // 截取读状态位, RXRDY
|
||||
bne t0, zero, .RSERIAL // 状态位非零可读进入读
|
||||
nop
|
||||
j .TESTR // 检测验证
|
||||
nop
|
||||
.RSERIAL:
|
||||
lb v0, 0(t1) // 读出, DATA
|
||||
jr ra
|
||||
nop
|
||||
|
||||
READSERIALWORD:
|
||||
addiu sp, sp, -0x14 // 保存ra,s0
|
||||
sw ra, 0x0(sp)
|
||||
sw s0, 0x4(sp)
|
||||
sw s1, 0x8(sp)
|
||||
sw s2, 0xC(sp)
|
||||
sw s3, 0x10(sp)
|
||||
|
||||
jal READSERIAL // 读串口获得八个比特
|
||||
nop
|
||||
or s0, zero, v0 // 结果存入s0
|
||||
jal READSERIAL // 读串口获得八个比特
|
||||
nop
|
||||
or s1, zero, v0 // 结果存入s1
|
||||
jal READSERIAL // 读串口获得八个比特
|
||||
nop
|
||||
or s2, zero, v0 // 结果存入s2
|
||||
jal READSERIAL // 读串口获得八个比特
|
||||
nop
|
||||
or s3, zero, v0 // 结果存入s3
|
||||
|
||||
andi s0, s0, 0x00FF // 截取低八位
|
||||
andi s3, s3, 0x00FF
|
||||
andi s2, s2, 0x00FF
|
||||
andi s1, s1, 0x00FF
|
||||
or v0, zero, s3 // 存高八位
|
||||
sll v0, v0, 8 // 左移
|
||||
or v0, v0, s2 // 存八位
|
||||
sll v0, v0, 8 // 左移
|
||||
or v0, v0, s1 // 存八位
|
||||
sll v0, v0, 8 // 左移
|
||||
or v0, v0, s0 // 存低八位
|
||||
|
||||
lw ra, 0x0(sp) // 恢复ra,s0
|
||||
lw s0, 0x4(sp)
|
||||
lw s1, 0x8(sp)
|
||||
lw s2, 0xC(sp)
|
||||
lw s3, 0x10(sp)
|
||||
addiu sp, sp, 0x14
|
||||
jr ra
|
||||
nop
|
||||
@ -1,110 +0,0 @@
|
||||
#include "tiny.h"
|
||||
|
||||
int putchar(char c)
|
||||
{
|
||||
WRITESERIAL(c);
|
||||
return c;
|
||||
}
|
||||
|
||||
char* itoa(int num, char* str, int base)
|
||||
{
|
||||
if (num == 0 || base <= 1)
|
||||
{
|
||||
str[0] = '0';
|
||||
str[1] = '\0';
|
||||
return str;
|
||||
}
|
||||
|
||||
int neg = 0, i = 0;
|
||||
if (num < 0 && base == 10)
|
||||
{
|
||||
neg = 1;
|
||||
num = -num;
|
||||
}
|
||||
|
||||
while (num != 0)
|
||||
{
|
||||
int rem = num % base;
|
||||
str[i] = (rem > 9) ? (rem - 10) + 'A' : rem + '0';
|
||||
num /= base;
|
||||
i++;
|
||||
}
|
||||
|
||||
if (neg == 1)
|
||||
{
|
||||
str[i++] = '-';
|
||||
str[i] = '\0';
|
||||
}
|
||||
else
|
||||
str[i] = '\0';
|
||||
|
||||
i--;
|
||||
|
||||
int start = 0;
|
||||
while (start < i)
|
||||
{
|
||||
char tmp = *(str + i);
|
||||
*(str + i) = *(str + start);
|
||||
*(str + start) = tmp;
|
||||
start++;
|
||||
i--;
|
||||
}
|
||||
|
||||
return str;
|
||||
}
|
||||
|
||||
int vsprintf(char* buf, const char* fmt, va_list args)
|
||||
{
|
||||
char* p;
|
||||
char tmp[256];
|
||||
va_list p_next_arg = args;
|
||||
|
||||
for (p = buf; *fmt; fmt++)
|
||||
{
|
||||
if (*fmt != '%')
|
||||
{
|
||||
*p++ = *fmt;
|
||||
continue;
|
||||
}
|
||||
|
||||
fmt++;
|
||||
|
||||
switch (*fmt)
|
||||
{
|
||||
case 'x':
|
||||
// itoa(tmp, *((int *)p_next_arg));
|
||||
itox(*((int*)p_next_arg), tmp, 16);
|
||||
strcpy(p, tmp);
|
||||
p_next_arg += 4;
|
||||
p += strlen(tmp);
|
||||
break;
|
||||
case 'd':
|
||||
itox(*((int*)p_next_arg), tmp, 10);
|
||||
strcpy(p, tmp);
|
||||
p_next_arg += 4;
|
||||
p += strlen(tmp);
|
||||
break;
|
||||
case 's':
|
||||
strcpy(p, (char*)(*((unsigned*)p_next_arg)));
|
||||
p += strlen((char*)(*((unsigned*)p_next_arg)));
|
||||
p_next_arg += 4;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return (p - buf);
|
||||
}
|
||||
|
||||
int printf(const char* fmt, ...)
|
||||
{
|
||||
int i;
|
||||
char buf[256];
|
||||
|
||||
va_list arg = (va_list)((char*)(&fmt) + 4); /*4是参数fmt所占堆栈中的大小*/
|
||||
i = vsprintf(buf, fmt, arg);
|
||||
write(buf, i);
|
||||
|
||||
return i;
|
||||
}
|
||||
@ -1,6 +0,0 @@
|
||||
#include "soc.h"
|
||||
|
||||
int main()
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
@ -1,6 +0,0 @@
|
||||
#ifndef PROJECT_SRC_SOC_H_
|
||||
#define PROJECT_SRC_SOC_H_
|
||||
|
||||
#include "cpu_cde.h"
|
||||
|
||||
#endif //PROJECT_SRC_SOC_H_
|
||||
@ -1,39 +0,0 @@
|
||||
#include <asm/asm.h>
|
||||
#include <asm/regdef.h>
|
||||
#include <cpu_cde.h>
|
||||
|
||||
.set noreorder
|
||||
.section .text.init
|
||||
.globl _init
|
||||
_init:
|
||||
lui t2, 0x0040
|
||||
mtc0 t2, c0_status # turn off timer interrupt
|
||||
mtc0 zero, c0_cause # clear cause
|
||||
la sp, _stack # setup stack
|
||||
la gp, _gp # setup small data
|
||||
|
||||
# Copy text to a000_0000 -> 8000_0000
|
||||
la t0, _text_code_begin
|
||||
la t1, _text_code_end
|
||||
li t2, 0xa0000000
|
||||
or t0, t0, t2
|
||||
or t1, t1, t2
|
||||
li t2, 0xbfc00000
|
||||
or t2, t2, t0
|
||||
copy:
|
||||
lw t3, 0(t2)
|
||||
addiu t2, t2, 4
|
||||
sw t3, 0(t0)
|
||||
addiu t0, t0, 4
|
||||
bne t0, t1, copy
|
||||
nop
|
||||
|
||||
lui k0, %hi(main)
|
||||
addiu k0, %lo(main)
|
||||
jr k0
|
||||
nop
|
||||
|
||||
.section .text.exception
|
||||
_EXCEPTION:
|
||||
b _EXCEPTION
|
||||
nop
|
||||
@ -1,5 +1,4 @@
|
||||
`include "AXI.svh"
|
||||
`include "sram.svh"
|
||||
|
||||
module AXI (
|
||||
input clk,
|
||||
|
||||
9
src/AXI/AXIRead_i.sv
Normal file
9
src/AXI/AXIRead_i.sv
Normal file
@ -0,0 +1,9 @@
|
||||
`include "AXI.svh"
|
||||
|
||||
interface AXIRead_i;
|
||||
AXIReadAddr_t AXIReadAddr;
|
||||
AXIReadData_t AXIReadData;
|
||||
|
||||
modport master(input AXIReadData, output AXIReadAddr);
|
||||
modport slave(input AXIReadAddr, output AXIReadData);
|
||||
endinterface //AXIRead
|
||||
9
src/AXI/AXIWrite_i.sv
Normal file
9
src/AXI/AXIWrite_i.sv
Normal file
@ -0,0 +1,9 @@
|
||||
`include "AXI.svh"
|
||||
|
||||
interface AXIWrite_i;
|
||||
AXIWriteAddr_t AXIWriteAddr;
|
||||
AXIWriteData_t AXIWriteData;
|
||||
|
||||
modport master(input AXIWriteData, output AXIWriteAddr);
|
||||
modport slave(input AXIWriteAddr, output AXIWriteData);
|
||||
endinterface //AXIWrite
|
||||
@ -24,20 +24,20 @@ module CP0 (
|
||||
input logic tlbr,
|
||||
input logic tlbp,
|
||||
output logic [2:0] K0,
|
||||
output logic in_kernel,
|
||||
output Random_t Random,
|
||||
output Index_t Index,
|
||||
output EntryHi_t EntryHi,
|
||||
output PageMask_t PageMask,
|
||||
output EntryLo_t EntryLo1,
|
||||
output EntryLo_t EntryLo0,
|
||||
input EntryHi_t tlb_EntryHi,
|
||||
input PageMask_t tlb_PageMask,
|
||||
input EntryLo_t tlb_EntryLo1,
|
||||
input EntryLo_t tlb_EntryLo0,
|
||||
input Index_t tlb_Index
|
||||
);
|
||||
|
||||
CP0_REGS_t rf_cp0;
|
||||
reg count_lo;
|
||||
logic count_lo;
|
||||
|
||||
// int comb logic
|
||||
assign interrupt = (rf_cp0.Status.EXL == 1'b0)
|
||||
@ -45,7 +45,6 @@ module CP0 (
|
||||
& |{rf_cp0.Cause.IP & rf_cp0.Status.IM,
|
||||
rf_cp0.Cause.TI & rf_cp0.Status.IM[7]};
|
||||
|
||||
assign rf_cp0.TagLo.zero = 9'b0;
|
||||
assign rf_cp0.Config.M = 1'b1;
|
||||
assign rf_cp0.Config.zero = 15'b0;
|
||||
assign rf_cp0.Config.BE = 1'b0;
|
||||
@ -54,20 +53,32 @@ module CP0 (
|
||||
assign rf_cp0.Config.MT = 3'b001;
|
||||
assign rf_cp0.Config.zero1 = 4'b0;
|
||||
assign rf_cp0.Cause.zero1 = 14'b0;
|
||||
assign rf_cp0.Cause.IP[7:2] = ext_int;
|
||||
assign rf_cp0.Cause.IP[7:2] = {rf_cp0.Cause.TI | ext_int[5], ext_int[4:0]};
|
||||
assign rf_cp0.Cause.zero2 = 1'b0;
|
||||
assign rf_cp0.Cause.zero3 = 2'b00;
|
||||
assign rf_cp0.Status.zero1 = 9'b0;
|
||||
assign rf_cp0.Status.zero2 = 6'b0;
|
||||
assign rf_cp0.Status.zero3 = 6'b0;
|
||||
assign rf_cp0.Status.zero3 = 3'b0;
|
||||
assign rf_cp0.Status.zero4 = 2'b0;
|
||||
assign rf_cp0.EntryHi.zero = 5'b0;
|
||||
assign rf_cp0.PageMask.zero1 = 7'b0;
|
||||
assign rf_cp0.PageMask.zero2 = 13'b0;
|
||||
assign rf_cp0.Wired.zero = 29'b0;
|
||||
assign rf_cp0.EntryLo1.zero = 6'b0;
|
||||
assign rf_cp0.EntryLo0.zero = 6'b0;
|
||||
assign rf_cp0.Index.zero = 29'b0;
|
||||
assign rf_cp0.Random.zero = 29'b0;
|
||||
assign rf_cp0.Index.zero = 28'b0;
|
||||
|
||||
assign rf_cp0.Config1 = 32'b0_000011_000_100_011_001_011_011_0000000;
|
||||
// Vol III Figure 9-1
|
||||
// | 31 | 30...25 | 24...22 | 21...19 | 18...16 |
|
||||
// | Config2 | MMU SIZE | iCache sets per way | iCache line size | iCache associativity |
|
||||
// | 15...13 | 12...10 | 9...7 |
|
||||
// | dCache sets per way | dCache line size | dCache associativity |
|
||||
// | 6 | 5 | 4 |
|
||||
// | Coprocessor 2 implemented | MD | Performance Counter registers |
|
||||
// | 3 | 2 |
|
||||
// | Watch registers implemented | Code compression implemented |
|
||||
// | 1 | 0 |
|
||||
// | EJTAG implemented | FPU implemented |
|
||||
assign rf_cp0.Config1 = 32'b0_000111_000_100_011_001_011_011_0_0_0_0_0_0_0;
|
||||
assign rf_cp0.EBase.one = 1'b1;
|
||||
assign rf_cp0.EBase.zero1 = 1'b0;
|
||||
assign rf_cp0.EBase.zero2 = 2'b0;
|
||||
@ -76,10 +87,6 @@ module CP0 (
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (rst) begin
|
||||
// rf_cp0 = {504'b0, 8'b10000011, 105'b0, 1'b1, 117'b0, 1'b1, 288'b0};
|
||||
rf_cp0.TagLo.Tag = 21'b0;
|
||||
rf_cp0.TagLo.D = 1'b0;
|
||||
rf_cp0.TagLo.V = 1'b0;
|
||||
rf_cp0.Config.K0 = 3'b011;
|
||||
rf_cp0.EPC = 32'h0;
|
||||
rf_cp0.Cause.BD = 1'b0;
|
||||
@ -88,6 +95,7 @@ module CP0 (
|
||||
rf_cp0.Cause.ExcCode = 5'b0;
|
||||
rf_cp0.Status.Bev = 1'b1;
|
||||
rf_cp0.Status.IM = 8'b0;
|
||||
rf_cp0.Status.UM = 1'b0;
|
||||
rf_cp0.Status.EXL = 1'b0;
|
||||
rf_cp0.Status.IE = 1'b0;
|
||||
rf_cp0.Compare = 32'hFFFF_FFFF;
|
||||
@ -95,7 +103,7 @@ module CP0 (
|
||||
rf_cp0.EntryHi.ASID = 8'b0;
|
||||
rf_cp0.Count = 32'h0;
|
||||
rf_cp0.BadVAddr = 32'h0;
|
||||
rf_cp0.PageMask.Mask = 12'b0;
|
||||
rf_cp0.Wired.Wired = 3'b0;
|
||||
rf_cp0.EntryLo1.PFN = 20'b0;
|
||||
rf_cp0.EntryLo1.C = 3'b0;
|
||||
rf_cp0.EntryLo1.D = 1'b0;
|
||||
@ -107,7 +115,8 @@ module CP0 (
|
||||
rf_cp0.EntryLo0.V = 1'b0;
|
||||
rf_cp0.EntryLo0.G = 1'b0;
|
||||
rf_cp0.Index.P = 1'b0;
|
||||
rf_cp0.Index.Index = 2'b0;
|
||||
rf_cp0.Index.Index = 3'b0;
|
||||
rf_cp0.Random.Random = 3'b111;
|
||||
|
||||
rf_cp0.EBase.EBase = 18'b0;
|
||||
|
||||
@ -122,11 +131,7 @@ module CP0 (
|
||||
// 31: rf_cp0.DESAVE = wdata;
|
||||
// 30: rf_cp0.ErrorEPC = wdata;
|
||||
// 29: rf_cp0.TagHi = wdata;
|
||||
28: begin
|
||||
rf_cp0.TagLo.Tag = wdata[22:2];
|
||||
rf_cp0.TagLo.D = wdata[1];
|
||||
rf_cp0.TagLo.V = wdata[0];
|
||||
end
|
||||
// 28: rf_cp0.TagLo = wdata;
|
||||
// 27: rf_cp0.CacheErr = wdata;
|
||||
// 26: rf_cp0.Errctl = wdata;
|
||||
// 25: rf_cp0.PerfCnt = wdata;
|
||||
@ -146,6 +151,7 @@ module CP0 (
|
||||
12: begin
|
||||
rf_cp0.Status.Bev = wdata[22];
|
||||
rf_cp0.Status.IM = wdata[15:8];
|
||||
rf_cp0.Status.UM = wdata[4];
|
||||
rf_cp0.Status.EXL = wdata[1];
|
||||
rf_cp0.Status.IE = wdata[0];
|
||||
end
|
||||
@ -160,8 +166,8 @@ module CP0 (
|
||||
9: rf_cp0.Count = wdata;
|
||||
8: rf_cp0.BadVAddr = wdata;
|
||||
// 7: rf_cp0.HWREna = wdata;
|
||||
// 6: rf_cp0.Wired = wdata;
|
||||
5: rf_cp0.PageMask.Mask = wdata[24:13];
|
||||
6: rf_cp0.Wired.Wired = wdata[2:0];
|
||||
// 5: rf_cp0.PageMask.Mask = wdata[24:13];
|
||||
// 4: rf_cp0.Context = wdata;
|
||||
3: begin
|
||||
rf_cp0.EntryLo1.PFN = wdata[25:6];
|
||||
@ -179,7 +185,7 @@ module CP0 (
|
||||
end
|
||||
// 1: rf_cp0.Random = wdata;
|
||||
0: begin
|
||||
rf_cp0.Index.Index = wdata[1:0];
|
||||
rf_cp0.Index.Index = wdata[2:0];
|
||||
end
|
||||
default: begin
|
||||
end
|
||||
@ -189,7 +195,7 @@ module CP0 (
|
||||
if (tlbr) begin
|
||||
rf_cp0.EntryHi.VPN2 = tlb_EntryHi.VPN2;
|
||||
rf_cp0.EntryHi.ASID = tlb_EntryHi.ASID;
|
||||
rf_cp0.PageMask.Mask = tlb_PageMask.Mask;
|
||||
// rf_cp0.PageMask.Mask = tlb_PageMask.Mask;
|
||||
rf_cp0.EntryLo0.PFN = tlb_EntryLo0.PFN;
|
||||
rf_cp0.EntryLo0.C = tlb_EntryLo0.C;
|
||||
rf_cp0.EntryLo0.D = tlb_EntryLo0.D;
|
||||
@ -201,11 +207,15 @@ module CP0 (
|
||||
rf_cp0.EntryLo1.V = tlb_EntryLo1.V;
|
||||
rf_cp0.EntryLo1.G = tlb_EntryLo1.G;
|
||||
end
|
||||
|
||||
if (tlbp) begin
|
||||
rf_cp0.Index.P = tlb_Index.P;
|
||||
rf_cp0.Index.Index = tlb_Index.Index;
|
||||
end
|
||||
|
||||
rf_cp0.Random.Random = &rf_cp0.Random.Random ? rf_cp0.Wired.Wired
|
||||
: rf_cp0.Random.Random + 1'b1;
|
||||
|
||||
if (rf_cp0.Count == rf_cp0.Compare) rf_cp0.Cause.TI = 1;
|
||||
|
||||
if (exception.ERET) rf_cp0.Status.EXL = 1'b0;
|
||||
@ -239,7 +249,7 @@ module CP0 (
|
||||
// 31: rdata = rf_cp0.DESAVE;
|
||||
// 30: rdata = rf_cp0.ErrorEPC;
|
||||
// 29: rdata = rf_cp0.TagHi;
|
||||
28: rdata = rf_cp0.TagLo;
|
||||
// 28: rdata = rf_cp0.TagLo;
|
||||
// 27: rdata = rf_cp0.CacheErr;
|
||||
// 26: rdata = rf_cp0.Errctl;
|
||||
// 25: rdata = rf_cp0.PerfCnt;
|
||||
@ -262,12 +272,13 @@ module CP0 (
|
||||
9: rdata = rf_cp0.Count;
|
||||
8: rdata = rf_cp0.BadVAddr;
|
||||
// 7: rdata = rf_cp0.HWREna;
|
||||
// 6: rdata = rf_cp0.Wired;
|
||||
5: rdata = rf_cp0.PageMask;
|
||||
6: rdata = rf_cp0.Wired;
|
||||
// 5: rdata = rf_cp0.PageMask;
|
||||
5: rdata = 32'h0;
|
||||
// 4: rdata = rf_cp0.Context;
|
||||
3: rdata = rf_cp0.EntryLo1;
|
||||
2: rdata = rf_cp0.EntryLo0;
|
||||
// 1: rdata = rf_cp0.Random;
|
||||
1: rdata = rf_cp0.Random;
|
||||
0: rdata = rf_cp0.Index;
|
||||
default: rdata = 32'h0;
|
||||
endcase
|
||||
@ -277,10 +288,13 @@ module CP0 (
|
||||
assign EBase = rf_cp0.EBase[31:12];
|
||||
|
||||
assign K0 = rf_cp0.Config.K0;
|
||||
assign Random = rf_cp0.Random;
|
||||
assign Index = rf_cp0.Index;
|
||||
assign EntryHi = rf_cp0.EntryHi;
|
||||
assign PageMask = rf_cp0.PageMask;
|
||||
// assign PageMask = rf_cp0.PageMask;
|
||||
assign EntryLo1 = rf_cp0.EntryLo1;
|
||||
assign EntryLo0 = rf_cp0.EntryLo0;
|
||||
|
||||
assign in_kernel = ~rf_cp0.Status.UM | rf_cp0.Status.EXL; // currently no ERL
|
||||
|
||||
endmodule
|
||||
|
||||
@ -1,5 +1,4 @@
|
||||
`include "defines.svh"
|
||||
`include "sram.svh"
|
||||
`include "DCache.svh"
|
||||
`include "AXI.svh"
|
||||
|
||||
@ -52,22 +51,15 @@ module DCache (
|
||||
|
||||
DCData_t wdata1[4], wdata2[4];
|
||||
|
||||
logic clear;
|
||||
|
||||
// ===========================
|
||||
// ======== Flip-Flop ========
|
||||
// ===========================
|
||||
|
||||
ffen #(`DC_TAGL-`DC_INDEXL) index_ff (
|
||||
clk,
|
||||
port.index,
|
||||
port.req,
|
||||
index1
|
||||
);
|
||||
ffen #(4) wen_ff (
|
||||
clk,
|
||||
wen,
|
||||
en2,
|
||||
wen2
|
||||
);
|
||||
ffen #(`DC_TAGL-`DC_INDEXL) index_ff (clk, port.index, port.req, index1);
|
||||
ffen #(4) wen_ff (clk, wen, en2, wen2);
|
||||
ffen #(1) clear_ff (clk, port.clearWb, en2, clear);
|
||||
|
||||
// ===============================
|
||||
// ======== State Machine ========
|
||||
@ -92,12 +84,12 @@ module DCache (
|
||||
end
|
||||
end
|
||||
LOOKUP: begin
|
||||
if (~port.valid) begin
|
||||
if (~port.valid & ~port.clearWb) begin
|
||||
if (~port.req) begin
|
||||
nextState = IDLE;
|
||||
end
|
||||
end else begin
|
||||
if (hit) begin
|
||||
if (hit & ~port.clearWb | port.clear & ~port.clearWb) begin
|
||||
if (port.wvalid) begin
|
||||
bwe1 = 1'b1;
|
||||
nextState = IDLE;
|
||||
@ -118,6 +110,7 @@ module DCache (
|
||||
nextState = IDLE;
|
||||
end
|
||||
end
|
||||
default: begin nextState = IDLE; end
|
||||
endcase
|
||||
end
|
||||
|
||||
@ -146,7 +139,8 @@ module DCache (
|
||||
assign hitWay[1] = tagV[1] & tagOut[1].tag == port.tag1;
|
||||
assign hitWay[2] = tagV[2] & tagOut[2].tag == port.tag1;
|
||||
assign hitWay[3] = tagV[3] & tagOut[3].tag == port.tag1;
|
||||
assign hit = |{hitWay};
|
||||
// 在 clearWb状态下确保命中
|
||||
assign hit = |{hitWay} | port.clear & port.clearWb;
|
||||
|
||||
assign cacheLine = (hitWay[0] ? dataOut[0] : `DC_DATA_LENGTH'b0)
|
||||
| (hitWay[1] ? dataOut[1] : `DC_DATA_LENGTH'b0)
|
||||
@ -161,7 +155,14 @@ module DCache (
|
||||
// ==============================
|
||||
|
||||
// Choose Victim
|
||||
assign victim = tagV[0] == 0 ? 4'b0001
|
||||
assign victim = port.clear & port.clearWb & ~port.clearIdx ? hitWay // Hit Address Writeback -> hitWay
|
||||
// Hit Index Writeback -> clear valid + dirty way
|
||||
: port.clear & port.clearWb & port.clearIdx & tagV[0] & tagOut[0].dirty ? 4'b0001
|
||||
: port.clear & port.clearWb & port.clearIdx & tagV[1] & tagOut[1].dirty ? 4'b0010
|
||||
: port.clear & port.clearWb & port.clearIdx & tagV[2] & tagOut[2].dirty ? 4'b0100
|
||||
: port.clear & port.clearWb & port.clearIdx & tagV[3] & tagOut[3].dirty ? 4'b1000
|
||||
// Normal mode
|
||||
: tagV[0] == 0 ? 4'b0001
|
||||
: tagV[1] == 0 ? 4'b0010
|
||||
: tagV[2] == 0 ? 4'b0100
|
||||
: tagV[3] == 0 ? 4'b1000
|
||||
@ -173,7 +174,11 @@ module DCache (
|
||||
: nowLRU[1] == 0 ? 4'b0010
|
||||
: nowLRU[2] == 0 ? 4'b0100
|
||||
: 4'b1000;
|
||||
assign wen = hit ? hitWay : victim;
|
||||
|
||||
assign wen = port.clear & port.clearIdx & ~port.clearWb ? 4'b1111 // Index Invalidate
|
||||
: port.clear & ~port.clearIdx & ~port.clearWb ? hitWay // Hit Invalidate
|
||||
: port.clear & port.clearWb ? victim // Writeback Invalidate
|
||||
: hit ? hitWay : victim;
|
||||
|
||||
assign port.dirt_valid = (state == LOOKUP)
|
||||
& |{tagV & {tagOut[3].dirty, tagOut[2].dirty, tagOut[1].dirty, tagOut[0].dirty} & victim};
|
||||
@ -190,7 +195,8 @@ module DCache (
|
||||
| (victim[3] ? dataOut[3] : `DC_DATA_LENGTH'b0);
|
||||
|
||||
// Update LRU
|
||||
assign nextLRU = {
|
||||
assign nextLRU = port.clear & port.clearIdx ? nowLRU :
|
||||
{
|
||||
wen[3] | nowLRU[3] & ~&{nowLRU | wen},
|
||||
wen[2] | nowLRU[2] & ~&{nowLRU | wen},
|
||||
wen[1] | nowLRU[1] & ~&{nowLRU | wen},
|
||||
@ -200,12 +206,16 @@ module DCache (
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst) begin
|
||||
for (integer i = 0; i < 128; i++)
|
||||
`ifndef VERILATOR
|
||||
LRU[i] <= 4'b0;
|
||||
`else
|
||||
LRU[i] = 4'b0;
|
||||
`endif
|
||||
end else begin
|
||||
if (port.req) begin
|
||||
if (state != IDLE)
|
||||
LRU[index1] = nextLRU;
|
||||
nowLRU = LRU[port.index];
|
||||
LRU[index1] <= nextLRU;
|
||||
nowLRU <= LRU[port.index];
|
||||
end
|
||||
end
|
||||
end
|
||||
@ -240,10 +250,10 @@ module DCache (
|
||||
assign DataRAM2.wen = (bwe1 & wen[2]) | (bwe2 & wen2[2]);
|
||||
assign DataRAM3.wen = (bwe1 & wen[3]) | (bwe2 & wen2[3]);
|
||||
// 写数据
|
||||
assign TagRAM0.wdata = {port.tag1, port.wvalid, 1'b1};
|
||||
assign TagRAM1.wdata = {port.tag1, port.wvalid, 1'b1};
|
||||
assign TagRAM2.wdata = {port.tag1, port.wvalid, 1'b1};
|
||||
assign TagRAM3.wdata = {port.tag1, port.wvalid, 1'b1};
|
||||
assign TagRAM0.wdata = {port.tag1, port.wvalid, ~(port.clear | bwe2 & clear)};
|
||||
assign TagRAM1.wdata = {port.tag1, port.wvalid, ~(port.clear | bwe2 & clear)};
|
||||
assign TagRAM2.wdata = {port.tag1, port.wvalid, ~(port.clear | bwe2 & clear)};
|
||||
assign TagRAM3.wdata = {port.tag1, port.wvalid, ~(port.clear | bwe2 & clear)};
|
||||
|
||||
assign DataRAM0.wdata = state == LOOKUP ? wdata1[0] : wdata2[0];
|
||||
assign DataRAM1.wdata = state == LOOKUP ? wdata1[1] : wdata2[1];
|
||||
@ -282,6 +292,7 @@ module DCache (
|
||||
if (port.wstrb[1]) wdata1[i][15: 8] = port.wdata[15: 8];
|
||||
if (port.wstrb[0]) wdata1[i][ 7: 0] = port.wdata[ 7: 0];
|
||||
end
|
||||
default: begin end
|
||||
endcase
|
||||
case (port.sel1)
|
||||
2'b11: begin
|
||||
@ -308,6 +319,7 @@ module DCache (
|
||||
if (port.wstrb[1]) wdata2[i][15: 8] = port.wdata[15: 8];
|
||||
if (port.wstrb[0]) wdata2[i][ 7: 0] = port.wdata[ 7: 0];
|
||||
end
|
||||
default: begin end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
37
src/Cache/DCache_i.sv
Normal file
37
src/Cache/DCache_i.sv
Normal file
@ -0,0 +1,37 @@
|
||||
`include "DCache.svh"
|
||||
|
||||
interface DCache_i;
|
||||
logic req;
|
||||
logic valid;
|
||||
DCIndexL_t index;
|
||||
DCTagL_t tag1;
|
||||
logic [1:0] sel1; // addr[3:2]
|
||||
logic hit;
|
||||
logic rvalid; // MMU(AXI) -> DCache
|
||||
DCData_t rdata;
|
||||
logic wvalid;
|
||||
word_t wdata;
|
||||
logic [3:0] wstrb;
|
||||
logic dirt_valid;
|
||||
word_t dirt_addr;
|
||||
DCData_t dirt_data;
|
||||
DCData_t row;
|
||||
logic clear;
|
||||
logic clearIdx;
|
||||
logic clearWb;
|
||||
|
||||
modport cache(
|
||||
input req, valid,
|
||||
input index, tag1, sel1,
|
||||
input rvalid, rdata, wvalid, wdata, wstrb,
|
||||
output hit, dirt_valid, dirt_addr, dirt_data, row,
|
||||
input clear, clearIdx, clearWb
|
||||
);
|
||||
modport mmu(
|
||||
output req, valid,
|
||||
output index, tag1, sel1,
|
||||
output rvalid, rdata, wvalid, wdata, wstrb,
|
||||
input hit, dirt_valid, dirt_addr, dirt_data, row,
|
||||
output clear, clearIdx, clearWb
|
||||
);
|
||||
endinterface //DCache_i
|
||||
@ -1,5 +1,4 @@
|
||||
`include "defines.svh"
|
||||
`include "sram.svh"
|
||||
`include "ICache.svh"
|
||||
`include "AXI.svh"
|
||||
|
||||
@ -68,7 +67,7 @@ module ICache (
|
||||
end
|
||||
end
|
||||
LOOKUP: begin
|
||||
if (~port.valid | hit) begin
|
||||
if (~port.valid | hit | port.clear) begin
|
||||
if (~port.req) begin
|
||||
nextState = IDLE;
|
||||
end
|
||||
@ -82,6 +81,7 @@ module ICache (
|
||||
nextState = IDLE;
|
||||
end
|
||||
end
|
||||
default: begin nextState = IDLE; end
|
||||
endcase
|
||||
end
|
||||
|
||||
@ -133,7 +133,7 @@ module ICache (
|
||||
nowLRU[1] == 0 ? 4'b0010 :
|
||||
nowLRU[2] == 0 ? 4'b0100 :
|
||||
4'b1000;
|
||||
assign wen = hit ? hitWay : victim;
|
||||
assign wen = (hit | port.clear) ? hitWay : victim;
|
||||
|
||||
// Update LRU
|
||||
assign nextLRU = {
|
||||
@ -149,8 +149,8 @@ module ICache (
|
||||
always_ff @(posedge clk) begin
|
||||
if (port.req) begin
|
||||
if (state != IDLE)
|
||||
LRU[index1] = nextLRU;
|
||||
nowLRU = LRU[port.index];
|
||||
LRU[index1] <= nextLRU;
|
||||
nowLRU <= LRU[port.index];
|
||||
end
|
||||
end
|
||||
|
||||
@ -164,7 +164,7 @@ module ICache (
|
||||
port.req,
|
||||
baddr
|
||||
);
|
||||
assign bwe = (state == REPLACE) & port.rvalid;
|
||||
assign bwe = state == REPLACE & port.rvalid;
|
||||
|
||||
// 地址
|
||||
assign TagRAM0.addr = baddr;
|
||||
@ -176,19 +176,19 @@ module ICache (
|
||||
assign DataRAM2.addr = baddr;
|
||||
assign DataRAM3.addr = baddr;
|
||||
// 写使能
|
||||
assign TagRAM0.wen = bwe & wen2[0];
|
||||
assign TagRAM1.wen = bwe & wen2[1];
|
||||
assign TagRAM2.wen = bwe & wen2[2];
|
||||
assign TagRAM3.wen = bwe & wen2[3];
|
||||
assign DataRAM0.wen = bwe & wen2[0];
|
||||
assign DataRAM1.wen = bwe & wen2[1];
|
||||
assign DataRAM2.wen = bwe & wen2[2];
|
||||
assign DataRAM3.wen = bwe & wen2[3];
|
||||
assign TagRAM0.wen = bwe & wen2[0] | port.clear & (wen[0] | port.clearIdx);
|
||||
assign TagRAM1.wen = bwe & wen2[1] | port.clear & (wen[1] | port.clearIdx);
|
||||
assign TagRAM2.wen = bwe & wen2[2] | port.clear & (wen[2] | port.clearIdx);
|
||||
assign TagRAM3.wen = bwe & wen2[3] | port.clear & (wen[3] | port.clearIdx);
|
||||
assign DataRAM0.wen = bwe & wen2[0] | port.clear & (wen[0] | port.clearIdx);
|
||||
assign DataRAM1.wen = bwe & wen2[1] | port.clear & (wen[1] | port.clearIdx);
|
||||
assign DataRAM2.wen = bwe & wen2[2] | port.clear & (wen[2] | port.clearIdx);
|
||||
assign DataRAM3.wen = bwe & wen2[3] | port.clear & (wen[3] | port.clearIdx);
|
||||
// 写数据
|
||||
assign TagRAM0.wdata = {port.tag1, 1'b1};
|
||||
assign TagRAM1.wdata = {port.tag1, 1'b1};
|
||||
assign TagRAM2.wdata = {port.tag1, 1'b1};
|
||||
assign TagRAM3.wdata = {port.tag1, 1'b1};
|
||||
assign TagRAM0.wdata = {port.tag1, ~port.clear};
|
||||
assign TagRAM1.wdata = {port.tag1, ~port.clear};
|
||||
assign TagRAM2.wdata = {port.tag1, ~port.clear};
|
||||
assign TagRAM3.wdata = {port.tag1, ~port.clear};
|
||||
assign DataRAM0.wdata = port.rdata;
|
||||
assign DataRAM1.wdata = port.rdata;
|
||||
assign DataRAM2.wdata = port.rdata;
|
||||
|
||||
29
src/Cache/ICache_i.sv
Normal file
29
src/Cache/ICache_i.sv
Normal file
@ -0,0 +1,29 @@
|
||||
`include "ICache.svh"
|
||||
|
||||
interface ICache_i;
|
||||
logic req;
|
||||
logic valid;
|
||||
ICIndexL_t index;
|
||||
ICTagL_t tag1;
|
||||
logic hit;
|
||||
ICData_t row;
|
||||
logic rvalid;
|
||||
ICData_t rdata;
|
||||
logic clear;
|
||||
logic clearIdx;
|
||||
|
||||
modport cache(
|
||||
input req, valid,
|
||||
input index, tag1,
|
||||
output hit, row,
|
||||
input rvalid, rdata,
|
||||
input clear, clearIdx
|
||||
);
|
||||
modport mmu(
|
||||
output req, valid,
|
||||
output index, tag1,
|
||||
input hit, row,
|
||||
output rvalid, rdata,
|
||||
output clear, clearIdx
|
||||
);
|
||||
endinterface //ICache_i
|
||||
@ -11,13 +11,17 @@ module ALU(
|
||||
wire logic [4:0] sa = a[4:0];
|
||||
wire logic ex = alt & b[31];
|
||||
wire word_t sl = b << sa;
|
||||
/* verilator lint_off WIDTH */
|
||||
wire word_t sr = {{31{ex}}, b} >> sa;
|
||||
/* verilator lint_on WIDTH */
|
||||
|
||||
wire word_t b2 = alt ? ~b : b;
|
||||
wire word_t sum;
|
||||
wire logic lt, ltu;
|
||||
|
||||
/* verilator lint_off WIDTH */
|
||||
assign {lt, ltu, sum} = {a[31], 1'b0, a} + {b2[31], 1'b1, b2} + alt; // alt for cin(CARRY4) at synthesis
|
||||
/* verilator lint_on WIDTH */
|
||||
assign aluout = (aluctrl.f_sl ? sl : 32'b0)
|
||||
| (aluctrl.f_sr ? sr : 32'b0)
|
||||
| (aluctrl.f_add ? sum : 32'b0)
|
||||
@ -25,6 +29,7 @@ module ALU(
|
||||
| (aluctrl.f_or ? alt ? ~(a | b) : a | b : 32'b0)
|
||||
| (aluctrl.f_xor ? a ^ b : 32'b0)
|
||||
| (aluctrl.f_slt ? {31'b0, lt } : 32'b0)
|
||||
| (aluctrl.f_sltu ? {31'b0, ltu} : 32'b0);
|
||||
| (aluctrl.f_sltu ? {31'b0, ltu} : 32'b0)
|
||||
| (aluctrl.f_mova ? a : 32'b0);
|
||||
assign overflow = lt ^ sum[31];
|
||||
endmodule
|
||||
|
||||
@ -4,6 +4,7 @@ module Controller (
|
||||
input word_t inst,
|
||||
input logic eq,
|
||||
input logic ltz,
|
||||
input word_t rt,
|
||||
output Ctrl_t ctrl,
|
||||
output word_t imm,
|
||||
output logic [4:0] sa
|
||||
@ -15,7 +16,7 @@ module Controller (
|
||||
inst[15:11],
|
||||
5'b11111,
|
||||
ctrl.RT,
|
||||
{~inst[29] & (inst[31] | inst[30]) | inst[29] & ~inst[30], inst[26]},
|
||||
{~inst[29] & inst[30] | inst[29] & ~inst[30] | inst[31], inst[26]},
|
||||
ctrl.RD
|
||||
);
|
||||
|
||||
@ -24,59 +25,72 @@ module Controller (
|
||||
{16'b0, inst[15:0]},
|
||||
{{16{inst[15]}}, inst[15:0]},
|
||||
{inst[15:0], 16'b0},
|
||||
{inst[28] & inst[27] & inst[26], inst[31] | ~inst[28]},
|
||||
{~inst[31] & inst[28] & inst[27] & inst[26], inst[31] | ~inst[28]},
|
||||
imm
|
||||
);
|
||||
|
||||
assign ctrl.BJRJ = ~inst[29] & (~inst[31] & (~inst[30] & ~inst[5] & ~inst[4] & inst[3] & ~inst[2] | inst[28] | inst[26]) | inst[27] & ~inst[26]);
|
||||
assign ctrl.B = ~inst[31] & ~inst[29] & (inst[28] | ~inst[27] & inst[26]);
|
||||
assign ctrl.JR = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[5] & ~inst[4] & inst[3] & ~inst[2];
|
||||
assign ctrl.BJRJ = ~inst[26] & (~inst[27] & (~inst[28] & ~inst[30] & ~inst[31] & ~inst[29] & inst[3] & ~inst[1] & ~inst[4] & ~inst[2] | inst[28] & ~inst[29] & ~inst[31]) | inst[27] & ~inst[31] & ~inst[29]) | inst[26] & ~inst[31] & ~inst[29] & (~inst[19] | inst[27] | inst[28]);
|
||||
assign ctrl.B = ~inst[26] & inst[28] & ~inst[29] & ~inst[31] | inst[26] & ~inst[31] & ~inst[29] & (~inst[27] & ~inst[19] | inst[28]);
|
||||
assign ctrl.JR = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[4] & inst[3] & ~inst[2] & ~inst[1];
|
||||
assign ctrl.J = ~inst[31] & ~inst[29] & ~inst[28] & inst[27];
|
||||
// Take Care of BGO
|
||||
assign ctrl.BGO = ~inst[26] & (eq | inst[27] & ltz) | inst[26] & (~inst[27] & (~inst[28] & (inst[16] & ~ltz | ~inst[16] & ltz) | inst[28] & ~eq) | inst[27] & ~eq & ~ltz);
|
||||
|
||||
assign ctrl.PRV = ~inst[31] & inst[30] & ~inst[29];
|
||||
assign ctrl.SYSCALL = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[3] & inst[2] & ~inst[0];
|
||||
assign ctrl.BREAK = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[3] & inst[2] & inst[0];
|
||||
assign ctrl.ERET = inst[30] & inst[4];
|
||||
assign ctrl.OFA = ~inst[31] & ~inst[28] & ~inst[27] & ~inst[26] & (~inst[30] & inst[5] & ~inst[3] & ~inst[2] & ~inst[0] | inst[29]);
|
||||
assign ctrl.BREAK = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[3] & inst[2] & ~inst[1] & inst[0];
|
||||
assign ctrl.ERET = ~inst[31] & inst[30] & inst[4];
|
||||
assign ctrl.OFA = ~inst[26] & ~inst[30] & (~inst[29] & ~inst[31] & ~inst[28] & ~inst[27] & inst[5] & ~inst[0] & ~inst[4] & ~inst[2] & ~inst[3] | inst[29] & ~inst[27] & ~inst[31] & ~inst[28]);
|
||||
|
||||
assign ctrl.ES = inst[31] | ~inst[30] & ~inst[28] & ~inst[27] & ~inst[26] & (inst[5] | inst[4] & inst[3] & ~inst[2] | ~inst[3] & inst[2]) | inst[29];;
|
||||
assign ctrl.ET = ~inst[31] & ~inst[27] & ~inst[26] & (~inst[30] & ~inst[29] & ~inst[28] & (inst[5] | (~inst[1] & (~inst[4] & ~inst[3] & ~inst[0] | inst[4] & inst[3]) | inst[1] & (~inst[4] | inst[3]))) | inst[30] & inst[29]);
|
||||
assign ctrl.DS = ~inst[31] & ~inst[29] & (inst[28] | ~inst[27] & (~inst[30] & ~inst[5] & ~inst[4] & inst[3] & ~inst[2] | inst[26]));
|
||||
assign ctrl.DT = ~inst[31] & ~inst[29] & inst[28] & ~inst[27];
|
||||
assign ctrl.ES = ~inst[30] & (~inst[28] & ~inst[27] & (~inst[26] & (~inst[3] & inst[2] | inst[3] & (inst[1] | inst[4]) | inst[5]) | inst[26] & inst[19]) | inst[31]) | inst[29];
|
||||
assign ctrl.ET = ~inst[26] & ~inst[27] & ~inst[31] & (~inst[30] & ~inst[29] & ~inst[28] & (~inst[3] & ~inst[4] | inst[3] & inst[4] | inst[5]) | inst[30] & inst[29]);
|
||||
assign ctrl.DS = ~inst[26] & (~inst[28] & ~inst[30] & ~inst[31] & ~inst[29] & ~inst[27] & inst[3] & ~inst[1] & ~inst[4] & ~inst[2] | inst[28] & ~inst[29] & ~inst[31]) | inst[26] & ~inst[31] & ~inst[29] & (~inst[27] & ~inst[19] | inst[28]);
|
||||
assign ctrl.DT = ~inst[28] & ~inst[26] & ~inst[30] & ~inst[31] & ~inst[29] & ~inst[27] & inst[3] & inst[1] & ~inst[5] & ~inst[4] | inst[28] & ~inst[29] & ~inst[31] & ~inst[27];
|
||||
|
||||
assign ctrl.DP0 = ~inst[31] & (~inst[30] | inst[29] | ~inst[25] | inst[4]);
|
||||
assign ctrl.DP1 = inst[26] | (~inst[30] & (inst[31] | inst[29] | inst[28] | inst[27] | ~inst[4]) | inst[30] & (~inst[29] & inst[25] | inst[3]));
|
||||
assign ctrl.DP0 = ~inst[31] & (~inst[30] & (~inst[26] & (~inst[4] | ~inst[5] | inst[27] | inst[28]) | inst[26] & (~inst[19] | inst[27] | inst[28])) | inst[30] & (~inst[25] | inst[4]) | inst[29]) | inst[31] & inst[30];
|
||||
assign ctrl.DP1 = ~inst[30] & (~inst[4] | inst[5] | inst[28] | inst[29] | inst[31] | inst[27] | inst[26]) | inst[30] & ~inst[29] & (inst[25] | inst[31]);
|
||||
|
||||
assign ctrl.ECtrl.OP.f_sl = ~inst[31] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[5] & ~inst[3] & ~inst[1];
|
||||
assign ctrl.ECtrl.OP.f_sr = ~inst[31] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[5] & inst[1];
|
||||
assign ctrl.ECtrl.OP.f_add = inst[31] | ~inst[28] & (~inst[26] & ~inst[27] & (inst[29] | ~inst[5] & inst[3] & ~inst[1] | inst[5] & ~inst[3] & ~inst[2]) | inst[26] & (~inst[29] | ~inst[27]));
|
||||
assign ctrl.ECtrl.OP.f_and = ~inst[31] & (~inst[28] & ~inst[29] & ~inst[27] & ~inst[26] & inst[5] & inst[2] & ~inst[0] & ~inst[1] | inst[28] & ~inst[27] & ~inst[26]);
|
||||
assign ctrl.ECtrl.OP.f_or = ~inst[31] & (~inst[28] & ~inst[29] & ~inst[27] & ~inst[26] & inst[5] & inst[2] & inst[0] | inst[28] & ~inst[27] & inst[26]);
|
||||
assign ctrl.ECtrl.OP.f_xor = ~inst[31] & (~inst[28] & ~inst[29] & ~inst[27] & ~inst[26] & inst[5] & inst[2] & ~inst[0] & inst[1] | inst[28] & inst[27]);
|
||||
assign ctrl.ECtrl.OP.f_slt = ~inst[31] & ~inst[28] & ~inst[26] & (~inst[29] & inst[5] & inst[3] & ~inst[2] & ~inst[0] | inst[27]);
|
||||
assign ctrl.ECtrl.OP.f_sltu = ~inst[31] & ~inst[28] & (~inst[26] & ~inst[29] & ~inst[27] & inst[5] & inst[3] & ~inst[2] & inst[0] | inst[26] & inst[29] & inst[27]);
|
||||
assign ctrl.ECtrl.OP.alt = ~inst[31] & (~inst[26] & (~inst[29] & inst[1] & (inst[5] | inst[0]) | inst[27]) | inst[26] & inst[29] & inst[27]);
|
||||
assign ctrl.ECtrl.OP.f_sr = ~inst[31] & ~inst[28] & ~inst[26] & ~inst[27] & ~inst[29] & ~inst[5] & ~inst[3] & inst[1];
|
||||
assign ctrl.ECtrl.OP.f_add = (~inst[28] & (~inst[26] & ~inst[27] & ((~inst[5] & inst[3] & ~inst[1] | inst[5] & (~inst[0] & (~inst[2] & ~inst[4] & ~inst[3] | inst[2] & inst[4]) | inst[0] & ~inst[2] & ~inst[4] & ~inst[3])) | inst[29]) | inst[26] & (~inst[29] & ((~inst[16] & (inst[20] | inst[18]) | inst[16] & inst[20]) | inst[27]) | inst[29] & ~inst[27])) | inst[31]);
|
||||
assign ctrl.ECtrl.OP.f_and = ~inst[31] & (~inst[28] & ~inst[26] & ~inst[27] & ~inst[29] & inst[5] & ~inst[0] & inst[2] & ~inst[4] & ~inst[1] | inst[28] & ~inst[27] & ~inst[26]);
|
||||
assign ctrl.ECtrl.OP.f_or = ~inst[31] & (~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[5] & inst[2] & inst[0] | inst[28] & ~inst[27] & inst[26]);
|
||||
assign ctrl.ECtrl.OP.f_xor = ~inst[31] & (~inst[28] & ~inst[26] & ~inst[27] & ~inst[29] & inst[5] & ~inst[0] & inst[2] & ~inst[4] & inst[1] | inst[28] & inst[27]);
|
||||
assign ctrl.ECtrl.OP.f_slt = ~inst[31] & ~inst[28] & (~inst[26] & (~inst[29] & inst[5] & ~inst[0] & ~inst[2] & (inst[3] | inst[4]) | inst[27]) | inst[26] & ~inst[29] & ~inst[27] & ~inst[16] & ~inst[18] & ~inst[20]);
|
||||
assign ctrl.ECtrl.OP.f_sltu = ~inst[31] & ~inst[28] & (~inst[26] & ~inst[27] & ~inst[29] & inst[5] & inst[0] & ~inst[2] & (inst[3] | inst[4]) | inst[26] & (~inst[29] & ~inst[27] & inst[16] & ~inst[20] | inst[29] & inst[27]));
|
||||
assign ctrl.ECtrl.OP.f_mova = ~inst[31] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[5] & inst[3] & inst[1];
|
||||
assign ctrl.ECtrl.OP.alt = ~inst[31] & ~inst[28] & (~inst[29] & ~inst[27] & (~inst[26] & (inst[1] & (inst[0] | inst[5]) | inst[4]) | inst[26] & ~inst[20]) | inst[29] & inst[27]);
|
||||
|
||||
assign ctrl.ECtrl.SA = SA_t'({inst[31] | inst[29] | ~inst[26] & (inst[5] | inst[2]), inst[31] | (~inst[28] & (inst[29] | inst[26] | inst[5] | inst[3] | inst[2]) | inst[28] & (~inst[27] | ~inst[26]))});
|
||||
assign ctrl.ECtrl.SB = SB_t'({inst[31] | inst[29], inst[26] | ~inst[5] & inst[3]});
|
||||
assign ctrl.ECtrl.SA = SA_t'({(~inst[27] & (~inst[26] & ((inst[3] & inst[1] | inst[2]) | inst[5]) | inst[26] & ~inst[20]) | inst[31]) | inst[29], (~inst[28] & (inst[2] | inst[3] | inst[5] | inst[29] | inst[26]) | inst[28] & (~inst[27] | ~inst[26])) | inst[31]});
|
||||
assign ctrl.ECtrl.SB = SB_t'({(inst[26] & ~inst[27] & ~inst[20] | inst[31]) | inst[29], inst[3] & ~inst[5] | inst[26]});
|
||||
|
||||
assign ctrl.MCtrl0.HW = ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[4] & (inst[3] | ~inst[1] & inst[0]);
|
||||
assign ctrl.MCtrl0.LW = ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[4] & (inst[3] | inst[1] & inst[0]);
|
||||
assign ctrl.MCtrl0.HLS = HLS_t'({~inst[27] & ~inst[26] & (~inst[30] & ~inst[31] & ~inst[29] & ~inst[28] & inst[4] & inst[3] | inst[30] & inst[29]), ~inst[30] & inst[1], inst[0]});
|
||||
assign ctrl.MCtrl0.HW = ~inst[30] & ~inst[26] & ~inst[29] & ~inst[28] & ~inst[27] & inst[4] & (~inst[5] & ~inst[1] & inst[0] | inst[3]) | inst[30] & inst[29] & ~inst[1];
|
||||
assign ctrl.MCtrl0.LW = ~inst[30] & ~inst[26] & ~inst[29] & ~inst[28] & ~inst[27] & inst[4] & (~inst[5] & inst[1] & inst[0] | inst[3]) | inst[30] & inst[29] & ~inst[1];
|
||||
assign ctrl.MCtrl0.HLS = HLS_t'({(~inst[30] & ~inst[26] & ~inst[27] & ~inst[31] & ~inst[29] & ~inst[28] & inst[4] & inst[3] | inst[30] & inst[29]), inst[1] & ~inst[30], inst[0]});
|
||||
assign ctrl.MCtrl0.MAS = MAS_t'({inst[2], inst[30] & ~inst[2] & ~inst[1]});
|
||||
assign ctrl.MCtrl0.C0D = inst[15:11];
|
||||
assign ctrl.MCtrl0.C0W = inst[30] & ~inst[29] & inst[23] & ~inst[3];
|
||||
assign ctrl.MCtrl0.C0W = ~inst[31] & inst[30] & ~inst[29] & inst[23] & ~inst[3];
|
||||
assign ctrl.MCtrl0.SEL = inst[2:0];
|
||||
assign ctrl.MCtrl0.RS0 = RS0_t'({~inst[30] & (inst[29] | inst[26] | ~inst[4]), inst[30], ~inst[29] & (inst[30] | ~inst[1])});
|
||||
assign ctrl.MCtrl0.RS0 = RS0_t'({~inst[30] & (~inst[4] | inst[5] | inst[29] | inst[26]), inst[30], ~inst[29] & (~inst[1] | inst[30])});
|
||||
|
||||
assign ctrl.MCtrl1.MR = inst[31];
|
||||
assign ctrl.MCtrl1.MR = inst[31] & ~inst[30];
|
||||
assign ctrl.MCtrl1.MWR = inst[29];
|
||||
assign ctrl.MCtrl1.MX = ~inst[28];
|
||||
assign ctrl.MCtrl1.ALR = ALR_t'({inst[28] & inst[27] & ~inst[26], ~inst[28] & inst[27] & ~inst[26]});
|
||||
assign ctrl.MCtrl1.SZ = inst[27:26];
|
||||
assign ctrl.MCtrl1.TLBR = inst[30] & ~inst[29] & inst[25] & ~inst[3] & ~inst[1];
|
||||
assign ctrl.MCtrl1.TLBWI = inst[30] & ~inst[29] & inst[25] & ~inst[3] & inst[1];
|
||||
assign ctrl.MCtrl1.TLBP = inst[30] & ~inst[4] & inst[3];
|
||||
assign ctrl.MCtrl1.TLBR = ~inst[31] & inst[30] & ~inst[29] & inst[25] & ~inst[3] & ~inst[1];
|
||||
assign ctrl.MCtrl1.TLBWI = ~inst[31] & inst[30] & ~inst[29] & inst[25] & ~inst[3] & inst[1];
|
||||
assign ctrl.MCtrl1.TLBWR = ~inst[31] & inst[30] & ~inst[29] & inst[25] & ~inst[3] & (inst[2] | ~inst[1]);
|
||||
assign ctrl.MCtrl1.TLBP = ~inst[31] & inst[30] & ~inst[4] & inst[3];
|
||||
assign ctrl.MCtrl1.CACHE_OP = CacheOp_t'({inst[29] & inst[28] & inst[26] & inst[16], inst[29] & inst[28] & inst[26] & ~inst[20], inst[29] & inst[28] & inst[26] & ~inst[18] & (inst[20] | inst[19] | ~inst[16])});
|
||||
|
||||
assign ctrl.WCtrl.RW = ctrl.RD != 5'b00000 & (~inst[30] & (~inst[29] & (inst[31] | ~inst[28] & (~inst[27] & (~inst[26] & (~inst[3] & (~inst[4] | ~inst[0]) | inst[3] & (inst[5] | ~inst[4] & ~inst[2] & inst[0])) | inst[26] & inst[20]) | inst[27] & inst[26])) | inst[29] & ~inst[31]) | inst[30] & (inst[29] | ~inst[25] & ~inst[23]));
|
||||
// assign ctrl.WCtrl.RW = ctrl.RD != 5'b00000 & (~inst[30] & (~inst[29] & (inst[31] | ~inst[28] & (~inst[27] & (~inst[26] & (~inst[3] & (~inst[4] | ~inst[0]) | inst[3] & (inst[5] | ~inst[4] & ~inst[2] & inst[0])) | inst[26] & inst[20]) | inst[27] & inst[26])) | inst[29] & ~inst[31]) | inst[30] & ~inst[25] & ~inst[23]);
|
||||
assign ctrl.Trap.TEN = ~inst[30] & ~inst[27] & (~inst[26] & ~inst[31] & ~inst[29] & ~inst[28] & inst[4] & inst[5] | inst[26] & ~inst[31] & ~inst[29] & ~inst[28] & inst[19]) | inst[30] & ~inst[29] & ~inst[31];
|
||||
assign ctrl.Trap.TP = TrapOp_t'({~inst[26] & inst[2] | inst[26] & inst[18], ~inst[26] & inst[1] | inst[26] & inst[17]});
|
||||
|
||||
logic mov, rw, eqz;
|
||||
assign mov = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[5] & ~inst[4] & inst[3] & ~inst[2] & inst[1];
|
||||
assign rw = ~inst[30] & (~inst[26] & (~inst[27] & (~inst[31] & (~inst[28] & (~inst[4] & (~inst[3] | ~inst[2] & (inst[0] | inst[1])) | inst[4] & ~inst[5] & ~inst[3] & ~inst[0]) | inst[29]) | inst[31] & ~inst[29]) | inst[27] & (~inst[31] & inst[29] | inst[31] & ~inst[29])) | inst[26] & (~inst[29] & (~inst[27] & ~inst[28] & inst[20] | inst[27] & ~inst[28] | inst[31]) | inst[29] & ~inst[31])) | inst[30] & ~inst[31] & ~inst[3] & (~inst[29] & ~inst[25] & ~inst[23] | inst[29] & inst[1]);
|
||||
assign eqz = rt == 32'h0;
|
||||
assign ctrl.WCtrl.RW = ctrl.RD != 5'b00000 & (~mov | ~inst[0] & eqz | inst[0] & ~eqz) & rw;
|
||||
|
||||
endmodule
|
||||
|
||||
@ -1,5 +1,7 @@
|
||||
`include "sram.svh"
|
||||
`include "defines.svh"
|
||||
`include "CP0.svh"
|
||||
`include "ICache.svh"
|
||||
`include "DCache.svh"
|
||||
|
||||
module Datapath (
|
||||
input clk,
|
||||
@ -8,12 +10,16 @@ module Datapath (
|
||||
// MMU
|
||||
sramro_i.master fetch_i,
|
||||
sram_i.master mem_i,
|
||||
output CacheOp_t cache_op,
|
||||
input logic iTLBRefill,
|
||||
input logic iTLBInvalid,
|
||||
input logic iAddressError,
|
||||
input logic dTLBRefill,
|
||||
input logic dTLBInvalid,
|
||||
input logic dTLBModified,
|
||||
input logic dAddressError,
|
||||
output logic tlb_tlbwi,
|
||||
output logic tlb_tlbwr,
|
||||
output logic tlb_tlbp,
|
||||
output logic c0_tlbr,
|
||||
output logic c0_tlbp,
|
||||
@ -29,6 +35,7 @@ module Datapath (
|
||||
input word_t C0_ERETPC,
|
||||
input logic C0_Bev,
|
||||
input logic [19:0] C0_EBase,
|
||||
input logic C0_kernel,
|
||||
|
||||
//debug interface
|
||||
output wire [31:0] debug_wb_pc,
|
||||
@ -73,8 +80,10 @@ module Datapath (
|
||||
|
||||
logic IQ_IA_TLBRefill;
|
||||
logic IQ_IA_TLBInvalid;
|
||||
logic IQ_IA_AddressError;
|
||||
logic IQ_IB_TLBRefill;
|
||||
logic IQ_IB_TLBInvalid;
|
||||
logic IQ_IB_AddressError;
|
||||
|
||||
logic [3:0] IQ_valids;
|
||||
|
||||
@ -120,8 +129,10 @@ module Datapath (
|
||||
|
||||
logic D_IA_TLBRefill;
|
||||
logic D_IA_TLBInvalid;
|
||||
logic D_IA_AddressError;
|
||||
logic D_IB_TLBRefill;
|
||||
logic D_IB_TLBInvalid;
|
||||
logic D_IB_AddressError;
|
||||
|
||||
logic D_IA_Hazard;
|
||||
logic D_IB_Hazard;
|
||||
@ -146,6 +157,7 @@ module Datapath (
|
||||
|
||||
word_t E_I1_A;
|
||||
word_t E_I1_B;
|
||||
word_t E_I1_ADDR;
|
||||
logic E_I1_Overflow;
|
||||
logic E_I1_STRBERROR;
|
||||
logic E_I1_NowExcValid;
|
||||
@ -189,6 +201,7 @@ module Datapath (
|
||||
logic dTLBRefillB;
|
||||
logic dTLBInvalidB;
|
||||
logic dTLBModifiedB;
|
||||
logic dAddressErrorB;
|
||||
EXCEPTION_t M_exception;
|
||||
logic M_exception_REFILL;
|
||||
|
||||
@ -196,6 +209,9 @@ module Datapath (
|
||||
logic [15:0] M_I1_Half;
|
||||
word_t M_I1_ByteX;
|
||||
word_t M_I1_HalfX;
|
||||
word_t M_I1_MDataA;
|
||||
word_t M_I1_MDataUL;
|
||||
word_t M_I1_MDataUR;
|
||||
word_t M_I1_MData;
|
||||
|
||||
logic M_I0_DIV_valid;
|
||||
@ -219,6 +235,16 @@ module Datapath (
|
||||
word_t M_I0_MULTUH;
|
||||
word_t M_I0_MULTUL;
|
||||
|
||||
word_t M_I0_MULTHF;
|
||||
word_t M_I0_MULTLF;
|
||||
word_t M_I0_MULTUHF;
|
||||
|
||||
logic M_I0_MAS_bvalid;
|
||||
word_t M_I0_MASH;
|
||||
word_t M_I0_MASL;
|
||||
word_t M_I0_MUASH;
|
||||
word_t M_I0_MUASL;
|
||||
|
||||
logic M_I0_MULT_bvalid;
|
||||
word_t M_I0_MULTLB;
|
||||
word_t M_I0_MULTHB;
|
||||
@ -227,6 +253,7 @@ module Datapath (
|
||||
word_t M_I0_HI;
|
||||
word_t M_I0_LO;
|
||||
|
||||
logic M_I1_Trap;
|
||||
logic M_I1_NowExcValid;
|
||||
logic M_I1_PrevExcValid;
|
||||
logic [4:0] M_I1_PrevExcCode;
|
||||
@ -304,29 +331,30 @@ module Datapath (
|
||||
|
||||
assign F.en = PF.pc[1:0] != 2'b00 & D_IA_can_dispatch | fetch_i.req & fetch_i.addr_ok;
|
||||
|
||||
assign F.ExcValid = F.pc[1:0] != 2'b00 | iTLBRefill | iTLBInvalid;
|
||||
assign F.ExcValid = F.pc[1:0] != 2'b00 | iTLBRefill | iTLBInvalid | iAddressError;
|
||||
|
||||
//---------------------------------------------------------------------------//
|
||||
// Instr Queue //
|
||||
//---------------------------------------------------------------------------//
|
||||
|
||||
Queue #(66) InstrQueue (
|
||||
Queue #(67) InstrQueue (
|
||||
.clk(clk),
|
||||
.rst(rst | rstD | rstM),
|
||||
|
||||
.vinA(fetch_i.data_ok | F.ExcValid),
|
||||
.inA ({F.pc[2] ? fetch_i.rdata1 : fetch_i.rdata0, F.pc, iTLBRefill, iTLBInvalid}),
|
||||
.inA ({F.pc[2] ? fetch_i.rdata1 : fetch_i.rdata0, F.pc,
|
||||
iTLBRefill, iTLBInvalid, iAddressError}),
|
||||
|
||||
.vinB(fetch_i.data_ok & ~F.pc[2]),
|
||||
.inB ({fetch_i.rdata1, F.pc[31:3], 3'b100, 2'b00}),
|
||||
.inB ({fetch_i.rdata1, F.pc[31:3], 3'b100, 3'b00}),
|
||||
|
||||
.enA (D.en0),
|
||||
.voutA(IQ_IA_valid),
|
||||
.outA ({IQ_IA_inst, IQ_IA_pc, IQ_IA_TLBRefill, IQ_IA_TLBInvalid}),
|
||||
.outA ({IQ_IA_inst, IQ_IA_pc, IQ_IA_TLBRefill, IQ_IA_TLBInvalid, IQ_IA_AddressError}),
|
||||
|
||||
.enB (D.en1),
|
||||
.voutB(IQ_IB_valid),
|
||||
.outB ({IQ_IB_inst, IQ_IB_pc, IQ_IB_TLBRefill, IQ_IB_TLBInvalid}),
|
||||
.outB ({IQ_IB_inst, IQ_IB_pc, IQ_IB_TLBRefill, IQ_IB_TLBInvalid, IQ_IB_AddressError}),
|
||||
|
||||
.valids(IQ_valids)
|
||||
);
|
||||
@ -336,19 +364,21 @@ module Datapath (
|
||||
//---------------------------------------------------------------------------//
|
||||
|
||||
// D.FF
|
||||
ffenr #(1 + 32 + 32 + 2) D_IA_ff (
|
||||
ffenr #(1 + 32 + 32 + 3) D_IA_ff (
|
||||
clk,
|
||||
rst | rstM,
|
||||
D.en1 ? {IQ_IA_valid & ~rstD, IQ_IA_pc, IQ_IA_inst, IQ_IA_TLBRefill, IQ_IA_TLBInvalid} : {D_IB_valid, D.IB_pc, D.IB_inst, D_IB_TLBRefill, D_IB_TLBInvalid},
|
||||
D.en1 ? {IQ_IA_valid & ~rstD, IQ_IA_pc, IQ_IA_inst, IQ_IA_TLBRefill, IQ_IA_TLBInvalid, IQ_IA_AddressError}
|
||||
: {D_IB_valid, D.IB_pc, D.IB_inst, D_IB_TLBRefill, D_IB_TLBInvalid, D_IB_AddressError},
|
||||
~D_IA_valid | D_go & E.en,
|
||||
{D_IA_valid, D.IA_pc, D.IA_inst, D_IA_TLBRefill, D_IA_TLBInvalid}
|
||||
{D_IA_valid, D.IA_pc, D.IA_inst, D_IA_TLBRefill, D_IA_TLBInvalid, D_IA_AddressError}
|
||||
);
|
||||
ffenr #(1 + 32 + 32 + 2) D_IB_ff (
|
||||
ffenr #(1 + 32 + 32 + 3) D_IB_ff (
|
||||
clk,
|
||||
rst | rstM,
|
||||
D.en1 ? {IQ_IB_valid & ~rstD, IQ_IB_pc, IQ_IB_inst, IQ_IB_TLBRefill, IQ_IB_TLBInvalid} : {IQ_IA_valid & ~rstD, IQ_IA_pc, IQ_IA_inst, IQ_IA_TLBRefill, IQ_IA_TLBInvalid},
|
||||
D.en1 ? {IQ_IB_valid & ~rstD, IQ_IB_pc, IQ_IB_inst, IQ_IB_TLBRefill, IQ_IB_TLBInvalid, IQ_IB_AddressError}
|
||||
: {IQ_IA_valid & ~rstD, IQ_IA_pc, IQ_IA_inst, IQ_IA_TLBRefill, IQ_IA_TLBInvalid, IQ_IA_AddressError},
|
||||
D.en0,
|
||||
{D_IB_valid, D.IB_pc, D.IB_inst, D_IB_TLBRefill, D_IB_TLBInvalid}
|
||||
{D_IB_valid, D.IB_pc, D.IB_inst, D_IB_TLBRefill, D_IB_TLBInvalid, D_IB_AddressError}
|
||||
);
|
||||
|
||||
ffenr #(1) D_IA_Delay_ff (
|
||||
@ -362,6 +392,7 @@ module Datapath (
|
||||
// Register File
|
||||
RF RegisterFile (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.raddr1(D.IA.RS),
|
||||
.raddr2(D.IA.RT),
|
||||
.raddr3(D.IB.RS),
|
||||
@ -401,6 +432,7 @@ module Datapath (
|
||||
.inst(D.IA_inst),
|
||||
.eq (D_IA_ForwardS == D_IA_ForwardT),
|
||||
.ltz (D_IA_ForwardS[31]),
|
||||
.rt (D_IA_ForwardT),
|
||||
.ctrl(D.IA),
|
||||
.imm (D.IA_imm),
|
||||
.sa (D.IA_sa)
|
||||
@ -409,6 +441,7 @@ module Datapath (
|
||||
.inst(D.IB_inst),
|
||||
.eq (D_IB_ForwardS == D_IB_ForwardT),
|
||||
.ltz (D_IB_ForwardS[31]),
|
||||
.rt (D_IB_ForwardT),
|
||||
.ctrl(D.IB),
|
||||
.imm (D.IB_imm),
|
||||
.sa (D.IB_sa)
|
||||
@ -424,25 +457,42 @@ module Datapath (
|
||||
D_IB_iv
|
||||
);
|
||||
|
||||
assign D.IA_ExcValid = D_IA_valid & (D.IA_pc[1:0] != 2'b00 | D_IA_TLBRefill | D_IA_TLBInvalid | ~D_IA_iv | D.IA.SYSCALL | D.IA.BREAK | D.IA.ERET);
|
||||
assign D.IA_ERET = D_IA_valid & D.IA_pc[1:0] == 2'b00 & ~D_IA_TLBRefill & ~D_IA_TLBInvalid & D_IA_iv & D.IA.ERET;
|
||||
// INFO: Merge "pc[1:0] != 2'b00" into AddressError
|
||||
assign D.IA_ExcValid = D_IA_valid & ( D.IA_pc[1:0] != 2'b00
|
||||
| ~D_IA_iv
|
||||
| D_IA_TLBRefill | D_IA_TLBInvalid
|
||||
| D_IA_AddressError
|
||||
| D.IA.SYSCALL | D.IA.BREAK | D.IA.ERET
|
||||
| D.IA.PRV & ~C0_kernel);
|
||||
assign D.IA_ERET = D_IA_valid & D.IA_pc[1:0] == 2'b00 & ~D_IA_TLBRefill & ~D_IA_TLBInvalid & ~D_IA_AddressError & D_IA_iv & D.IA.ERET;
|
||||
assign D.IA_REFILL = D_IA_valid & D.IB_pc[1:0] == 2'b00 & D_IA_TLBRefill;
|
||||
assign D.IA_ExcCode = D.IA_pc[1:0] != 2'b00 ? `EXCCODE_ADEL
|
||||
assign D.IA_ExcCode = D.IA_pc[1:0] != 2'b00 | D_IA_AddressError ? `EXCCODE_ADEL
|
||||
: D_IA_TLBRefill ? `EXCCODE_TLBL
|
||||
: D_IA_TLBInvalid ? `EXCCODE_TLBL
|
||||
: ~D_IA_iv ? `EXCCODE_RI
|
||||
: D.IA_inst[0] ? `EXCCODE_BP : `EXCCODE_SYS;
|
||||
: ~D.IA_inst[30] & D.IA_inst[0] ? `EXCCODE_BP
|
||||
: ~D.IA_inst[30] & ~D.IA_inst[0] ? `EXCCODE_SYS
|
||||
: `EXCCODE_CPU;
|
||||
|
||||
assign D.IB_ExcValid = D_IB_valid & (D.IB_pc[1:0] != 2'b00 | D_IB_TLBRefill | D_IB_TLBInvalid | ~D_IB_iv | D.IB.SYSCALL | D.IB.BREAK | D.IB.ERET | D.IB_Delay & D.IB.BJRJ);
|
||||
assign D.IB_ERET = D_IB_valid & D.IB_pc[1:0] == 2'b00 & ~D_IB_TLBRefill & ~D_IB_TLBInvalid & D_IB_iv & D.IB.ERET & ~D.IB_Delay;
|
||||
assign D.IB_ExcValid = D_IB_valid & ( D.IB_pc[1:0] != 2'b00
|
||||
| ~D_IB_iv
|
||||
| D_IB_TLBRefill | D_IB_TLBInvalid
|
||||
| D_IB_AddressError
|
||||
| D.IB.SYSCALL | D.IB.BREAK | D.IB.ERET
|
||||
| D.IB_Delay & D.IB.BJRJ
|
||||
| D.IB.PRV & ~C0_kernel);
|
||||
assign D.IB_ERET = D_IB_valid & D.IB_pc[1:0] == 2'b00 & ~D_IB_TLBRefill & ~D_IB_TLBInvalid & ~D_IB_AddressError & D_IB_iv & D.IB.ERET & ~D.IB_Delay;
|
||||
assign D.IB_REFILL = D_IB_valid & D.IB_pc[1:0] == 2'b00 & D_IB_TLBRefill;
|
||||
assign D.IB_ExcCode = D.IB_pc[1:0] != 2'b00 ? `EXCCODE_ADEL
|
||||
// EXCCODE_BP and EXCCODE_SYSCALL -> exc.txt
|
||||
assign D.IB_ExcCode = D.IB_pc[1:0] != 2'b00 | D_IB_AddressError ? `EXCCODE_ADEL
|
||||
: D_IB_TLBRefill ? `EXCCODE_TLBL
|
||||
: D_IB_TLBInvalid ? `EXCCODE_TLBL
|
||||
: ~D_IB_iv ? `EXCCODE_RI
|
||||
: D.IB.ERET ? `EXCCODE_RI
|
||||
: D.IB_Delay & D.IB.BJRJ ? `EXCCODE_RI
|
||||
: D.IB_inst[0] ? `EXCCODE_BP : `EXCCODE_SYS;
|
||||
: ~D.IB_inst[30] & D.IB_inst[0] ? `EXCCODE_BP
|
||||
: ~D.IB_inst[30] & ~D.IB_inst[0] ? `EXCCODE_SYS
|
||||
: `EXCCODE_CPU;
|
||||
assign D.IB_Delay = D.IA.BJRJ;
|
||||
|
||||
// D.Dispatch
|
||||
@ -483,25 +533,27 @@ module Datapath (
|
||||
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl0.C0W & ~D.IA.DP0
|
||||
// Not Arith -> Store
|
||||
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl1.MWR & ~D.IA.DP1
|
||||
// Not Arith -> LWL/LWR
|
||||
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & |D.IB.MCtrl1.ALR & ~D.IA.DP1
|
||||
// CP0 Execution Hazards
|
||||
// Hazards Related to the TLB
|
||||
| D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBR & D.IA.MCtrl0.C0D == C0_INDEX
|
||||
| D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBWI & D.IA.MCtrl0.C0D == C0_ENTRYHI
|
||||
| D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBWI & D.IA.MCtrl0.C0D == C0_ENTRYLO0
|
||||
| D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBWI & D.IA.MCtrl0.C0D == C0_ENTRYLO1
|
||||
| D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBWI & D.IA.MCtrl0.C0D == C0_INDEX
|
||||
| D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBWI & D.IA.MCtrl0.C0D == C0_PAGEMASK
|
||||
| D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBWI & D.IA.MCtrl0.C0D == C0_INDEX & ~D.IB.MCtrl1.TLBWR
|
||||
// | D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBWI & D.IA.MCtrl0.C0D == C0_PAGEMASK
|
||||
| E.I0.MCtrl.C0W & D.IB.MCtrl1.TLBP & E.I0.MCtrl.C0D == C0_ENTRYHI
|
||||
| D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBP & D.IA.MCtrl0.C0D == C0_ENTRYHI
|
||||
| D.IA.MCtrl0.C0W & D.IB.MCtrl1.MR & D.IA.MCtrl0.C0D == C0_ENTRYHI
|
||||
// TODO: CACHE
|
||||
| D.IA.MCtrl1.TLBR & D.IB.MCtrl0.C0W
|
||||
| D.IA.MCtrl1.TLBP & D.IB.MCtrl0.C0W
|
||||
| D.IA.MCtrl1.TLBR & D.IB.WCtrl.RW & D.IB.MCtrl0.C0D == C0_ENTRYHI & D.IB.MCtrl0.RS0 == C0
|
||||
| D.IA.MCtrl1.TLBR & D.IB.WCtrl.RW & D.IB.MCtrl0.C0D == C0_ENTRYLO0 & D.IB.MCtrl0.RS0 == C0
|
||||
| D.IA.MCtrl1.TLBR & D.IB.WCtrl.RW & D.IB.MCtrl0.C0D == C0_ENTRYLO1 & D.IB.MCtrl0.RS0 == C0
|
||||
| D.IA.MCtrl1.TLBR & D.IB.WCtrl.RW & D.IB.MCtrl0.C0D == C0_PAGEMASK & D.IB.MCtrl0.RS0 == C0
|
||||
| D.IA.MCtrl1.TLBP & D.IB.WCtrl.RW & D.IB.MCtrl0.C0D == C0_INDEX & D.IB.MCtrl0.RS0 == C0
|
||||
| D.IA.MCtrl1.TLBR & D.IB.WCtrl.RW & D.IB.MCtrl0.C0D == C0_ENTRYHI & D.IB.MCtrl0.RS0 == RS0_C0
|
||||
| D.IA.MCtrl1.TLBR & D.IB.WCtrl.RW & D.IB.MCtrl0.C0D == C0_ENTRYLO0 & D.IB.MCtrl0.RS0 == RS0_C0
|
||||
| D.IA.MCtrl1.TLBR & D.IB.WCtrl.RW & D.IB.MCtrl0.C0D == C0_ENTRYLO1 & D.IB.MCtrl0.RS0 == RS0_C0
|
||||
// | D.IA.MCtrl1.TLBR & D.IB.WCtrl.RW & D.IB.MCtrl0.C0D == C0_PAGEMASK & D.IB.MCtrl0.RS0 == RS0_C0
|
||||
| D.IA.MCtrl1.TLBP & D.IB.WCtrl.RW & D.IB.MCtrl0.C0D == C0_INDEX & D.IB.MCtrl0.RS0 == RS0_C0
|
||||
// Hazards Related to Exceptions or Interrupts
|
||||
| D.IA.MCtrl0.C0W & D.IB.ERET & D.IA.MCtrl0.C0D == C0_EPC
|
||||
;
|
||||
@ -556,6 +608,7 @@ module Datapath (
|
||||
assign D.I1.sa = D.A ? D.IA_sa : D.IB_sa;
|
||||
assign D.I1.ECtrl = D.A ? D.IA.ECtrl : D.IB.ECtrl;
|
||||
assign D.I1.MCtrl = D.A ? D.IA.MCtrl1 : D.IB.MCtrl1;
|
||||
assign D.I1.Trap = D.A ? D.IA.Trap : D.IB.Trap;
|
||||
assign D.I1.RD = D.A ? D.IA.RD : D.IB.RD;
|
||||
assign D.I1.WCtrl = D.A ? D.IA.WCtrl : D.IB.WCtrl;
|
||||
|
||||
@ -666,13 +719,13 @@ module Datapath (
|
||||
E.en,
|
||||
{E.I0.imm, E.I0.sa}
|
||||
);
|
||||
ffen #(13) E_I0_ECtrl_ff (
|
||||
ffen #(14) E_I0_ECtrl_ff (
|
||||
clk,
|
||||
D.I0.ECtrl,
|
||||
E.en,
|
||||
E.I0.ECtrl
|
||||
);
|
||||
ffenrc #(17) E_I0_MCtrl_ff (
|
||||
ffenrc #(19) E_I0_MCtrl_ff (
|
||||
clk,
|
||||
rst | rstM,
|
||||
D.I0.MCtrl,
|
||||
@ -729,13 +782,13 @@ module Datapath (
|
||||
E.en,
|
||||
{E.I1.imm, E.I1.sa}
|
||||
);
|
||||
ffen #(13) E_I1_ECtrl_ff (
|
||||
ffen #(14) E_I1_ECtrl_ff (
|
||||
clk,
|
||||
D.I1.ECtrl,
|
||||
E.en,
|
||||
E.I1.ECtrl
|
||||
);
|
||||
ffenrc #(8) E_I1_MCtrl_ff (
|
||||
ffenrc #(14) E_I1_MCtrl_ff (
|
||||
clk,
|
||||
rst | rstM,
|
||||
D.I1.MCtrl,
|
||||
@ -743,6 +796,14 @@ module Datapath (
|
||||
~D_go | ~D_I1_go,
|
||||
E.I1.MCtrl
|
||||
);
|
||||
ffenrc #(3) E_I1_Trap_ff (
|
||||
clk,
|
||||
rst | rstM,
|
||||
D.I1.Trap,
|
||||
E.en,
|
||||
~D_go | ~D_I1_go,
|
||||
E.I1.Trap
|
||||
);
|
||||
ffenrc #(5 + 1) E_I1_WCtrl_ff (
|
||||
clk,
|
||||
rst | rstM,
|
||||
@ -869,9 +930,13 @@ module Datapath (
|
||||
|
||||
assign tlb_tlbp = E.I1.MCtrl.TLBP;
|
||||
assign mem_i.req = E.I1.MCtrl.MR & E_I1_goWithoutOF & M.en & ~rstM;
|
||||
assign mem_i.addr = E_I1_ForwardS + E.I1.imm;
|
||||
assign E_I1_ADDR = E_I1_ForwardS + E.I1.imm;
|
||||
assign mem_i.addr = |E.I1.MCtrl.ALR ? {E_I1_ADDR[31:2], 2'b0}
|
||||
: (cache_op == CNOP | ~cache_op[1]) ? E_I1_ADDR
|
||||
: cache_op[2] ? {E_I1_ADDR[32-`DC_INDEXL-1:0], `DC_INDEXL'b0}
|
||||
: {E_I1_ADDR[32-`IC_INDEXL-1:0], `IC_INDEXL'b0};
|
||||
assign mem_i.size = {E.I1.MCtrl.SZ[1], E.I1.MCtrl.SZ[0] & ~E.I1.MCtrl.SZ[1]};
|
||||
// assign mem_i.addr = E.I1.ALUOut;
|
||||
assign cache_op = E.I1.MCtrl.CACHE_OP;
|
||||
|
||||
assign E.en = E_go & M.en;
|
||||
assign E_go = ~mem_i.req | mem_i.addr_ok;
|
||||
@ -968,7 +1033,7 @@ module Datapath (
|
||||
M.en,
|
||||
M.I0.ALUOut
|
||||
);
|
||||
ffenrc #(17) M_I0_MCtrl_ff (
|
||||
ffenrc #(19) M_I0_MCtrl_ff (
|
||||
clk,
|
||||
rst | rstM,
|
||||
E.I0.MCtrl,
|
||||
@ -1023,7 +1088,7 @@ module Datapath (
|
||||
M.en,
|
||||
M.I1.ALUOut
|
||||
);
|
||||
ffenrc #(8) M_I1_MCtrl_ff (
|
||||
ffenrc #(14) M_I1_MCtrl_ff (
|
||||
clk,
|
||||
rst | rstM,
|
||||
E.I1.MCtrl,
|
||||
@ -1031,6 +1096,14 @@ module Datapath (
|
||||
~E_go | ~E_I1_go,
|
||||
M.I1.MCtrl
|
||||
);
|
||||
ffenrc #(3) M_I1_Trap_ff (
|
||||
clk,
|
||||
rst | rstM,
|
||||
E.I1.Trap,
|
||||
M.en,
|
||||
~E_go | ~E_I1_go,
|
||||
M.I1.Trap
|
||||
);
|
||||
ffenrc #(5 + 1) M_I1_WCtrl_ff (
|
||||
clk,
|
||||
rst | rstM,
|
||||
@ -1050,16 +1123,18 @@ module Datapath (
|
||||
1'b1,
|
||||
dTLBExcValid
|
||||
);
|
||||
buffer0 #(3) dTLBExc_buffer (
|
||||
myBuffer0 #(4) dExc_buffer (
|
||||
clk, rst,
|
||||
{dTLBRefill, dTLBInvalid, dTLBModified},
|
||||
{dTLBRefill, dTLBInvalid, dTLBModified, dAddressError},
|
||||
dTLBExcValid,
|
||||
{dTLBRefillB, dTLBInvalidB, dTLBModifiedB}
|
||||
{dTLBRefillB, dTLBInvalidB, dTLBModifiedB, dAddressErrorB}
|
||||
);
|
||||
assign M_I1_NowExcValid = dTLBRefillB | dTLBInvalidB | dTLBModifiedB;
|
||||
assign M_I1_NowExcValid = dTLBRefillB | dTLBInvalidB | dTLBModifiedB | dAddressErrorB | M_I1_Trap;
|
||||
assign M.I1.ExcValid = M_I1_PrevExcValid | M_I1_NowExcValid;
|
||||
assign M.I1.REFILL = M_I1_PrevREFILL | dTLBRefillB;
|
||||
assign M.I1.ExcCode = M_I1_PrevExcValid ? M_I1_PrevExcCode
|
||||
: M_I1_Trap ? `EXCCODE_TR
|
||||
: dAddressErrorB ? M.I1.MCtrl.MWR ? `EXCCODE_ADES : `EXCCODE_ADES
|
||||
: dTLBRefillB ? M.I1.MCtrl.MWR ? `EXCCODE_TLBS : `EXCCODE_TLBL
|
||||
: dTLBInvalidB ? M.I1.MCtrl.MWR ? `EXCCODE_TLBS : `EXCCODE_TLBL
|
||||
: `EXCCODE_MOD;
|
||||
@ -1082,17 +1157,31 @@ module Datapath (
|
||||
};
|
||||
|
||||
// M.I0.MUL
|
||||
buffer #(96) M_I0_MULT_buffer (
|
||||
ffenr #(97) M_I0_MAS_ff (
|
||||
clk,rst,
|
||||
M_I0_MULT_CNTR[0],
|
||||
{M_I0_MULTL, M_I0_MULTH, M_I0_MULTUH},
|
||||
{M_I0_MULTL, M_I0_MULTH, M_I0_MULTUH, M_I0_MULT_CNTR[0]},
|
||||
1'b1,
|
||||
{M_I0_MULTLF, M_I0_MULTHF, M_I0_MULTUHF, M_I0_MAS_bvalid}
|
||||
);
|
||||
|
||||
// TODO: Optimize ME
|
||||
assign {M_I0_MUASH, M_I0_MUASL} = M.I0.MCtrl.MAS[0] ? {HI, LO} + {M_I0_MULTUHF, M_I0_MULTLF}
|
||||
: {HI, LO} - {M_I0_MULTUHF, M_I0_MULTLF};
|
||||
assign {M_I0_MASH, M_I0_MASL} = M.I0.MCtrl.MAS[0] ? $signed({HI, LO}) + $signed({M_I0_MULTHF, M_I0_MULTLF})
|
||||
: $signed({HI, LO}) - $signed({M_I0_MULTHF, M_I0_MULTLF});
|
||||
|
||||
myBuffer #(96) M_I0_MULT_buffer (
|
||||
clk, rst,
|
||||
M_I0_MULT_CNTR[0] & M.I0.MCtrl.MAS == 2'b00 | M_I0_MAS_bvalid & |M.I0.MCtrl.MAS,
|
||||
M.I0.MCtrl.MAS == 2'b00 ? {M_I0_MULTL, M_I0_MULTH, M_I0_MULTUH}
|
||||
: {M_I0_MASL, M_I0_MASH, M_I0_MUASH},
|
||||
M.en,
|
||||
M_I0_MULT_bvalid,
|
||||
{M_I0_MULTLB, M_I0_MULTHB, M_I0_MULTUHB}
|
||||
);
|
||||
|
||||
// M.I0.DIV
|
||||
buffer #(64) M_I0_DIV_buffer (
|
||||
myBuffer #(64) M_I0_DIV_buffer (
|
||||
clk, rst,
|
||||
M_I0_DIV_valid,
|
||||
{M_I0_DIVL, M_I0_DIVH},
|
||||
@ -1100,7 +1189,7 @@ module Datapath (
|
||||
M_I0_DIV_bvalid,
|
||||
{M_I0_DIVLB, M_I0_DIVHB}
|
||||
);
|
||||
buffer #(64) M_I0_DIVU_buffer (
|
||||
myBuffer #(64) M_I0_DIVU_buffer (
|
||||
clk, rst,
|
||||
M_I0_DIVU_valid,
|
||||
{M_I0_DIVUL, M_I0_DIVUH},
|
||||
@ -1131,13 +1220,13 @@ module Datapath (
|
||||
ffen #(32) HI_ff (
|
||||
clk,
|
||||
M_I0_HI,
|
||||
M.I0.MCtrl.HW & M_I0_go,
|
||||
M.I0.MCtrl.HW & M_go,
|
||||
HI
|
||||
);
|
||||
ffen #(32) LO_ff (
|
||||
clk,
|
||||
M_I0_LO,
|
||||
M.I0.MCtrl.LW & M_I0_go,
|
||||
M.I0.MCtrl.LW & M_go,
|
||||
LO
|
||||
);
|
||||
|
||||
@ -1148,15 +1237,17 @@ module Datapath (
|
||||
|
||||
// M.I1.MEM
|
||||
assign tlb_tlbwi = M.I1.MCtrl.TLBWI;
|
||||
assign tlb_tlbwr = M.I1.MCtrl.TLBWR;
|
||||
assign c0_tlbr = M.I1.MCtrl.TLBR;
|
||||
assign c0_tlbp = M.I1.MCtrl.TLBP & M.en;
|
||||
assign mem_i.wr = M.I1.MCtrl.MWR;
|
||||
memoutput M_I1_memoutput (
|
||||
M.I1.ALUOut[1:0],
|
||||
M_I1_ForwardT,
|
||||
M.I1.MCtrl.SZ,
|
||||
mem_i.wdata,
|
||||
mem_i.wstrb
|
||||
.addr (M.I1.ALUOut[1:0]),
|
||||
.data (M_I1_ForwardT),
|
||||
.size (M.I1.MCtrl.SZ),
|
||||
.alr (M.I1.MCtrl.ALR),
|
||||
.wdata(mem_i.wdata),
|
||||
.wstrb(mem_i.wstrb)
|
||||
);
|
||||
|
||||
mux4 #(8) M_I1_Byte_mux (
|
||||
@ -1183,11 +1274,34 @@ module Datapath (
|
||||
M.I1.MCtrl.MX,
|
||||
M_I1_HalfX
|
||||
);
|
||||
mux3 #(32) M_I1_MData_mux (
|
||||
mux3 #(32) M_I1_MDataA_mux (
|
||||
M_I1_ByteX,
|
||||
M_I1_HalfX,
|
||||
M_I1_DataR,
|
||||
M.I1.MCtrl.SZ,
|
||||
M_I1_MDataA
|
||||
);
|
||||
mux4 #(32) M_I1_MDataUL_mux (
|
||||
{M_I1_DataR[ 7:0], M_I1_ForwardT[23:0]},
|
||||
{M_I1_DataR[15:0], M_I1_ForwardT[15:0]},
|
||||
{M_I1_DataR[23:0], M_I1_ForwardT[ 7:0]},
|
||||
M_I1_DataR,
|
||||
M.I1.ALUOut[1:0],
|
||||
M_I1_MDataUL
|
||||
);
|
||||
mux4 #(32) M_I1_MDataUR_mux (
|
||||
M_I1_DataR,
|
||||
{M_I1_ForwardT[31:24], M_I1_DataR[31: 8]},
|
||||
{M_I1_ForwardT[31:16], M_I1_DataR[31:16]},
|
||||
{M_I1_ForwardT[31: 8], M_I1_DataR[31:24]},
|
||||
M.I1.ALUOut[1:0],
|
||||
M_I1_MDataUR
|
||||
);
|
||||
mux3 #(32) M_I1_MData_mux (
|
||||
M_I1_MDataA,
|
||||
M_I1_MDataUL,
|
||||
M_I1_MDataUR,
|
||||
M.I1.MCtrl.ALR,
|
||||
M_I1_MData
|
||||
);
|
||||
mux2 #(32) M_I1_DataRW_mux (
|
||||
@ -1197,7 +1311,7 @@ module Datapath (
|
||||
M.I1.RDataW
|
||||
);
|
||||
|
||||
buffer #(32) M_I1_DataR_buffer (
|
||||
myBuffer #(32) M_I1_DataR_buffer (
|
||||
clk, rst,
|
||||
mem_i.data_ok,
|
||||
mem_i.rdata,
|
||||
@ -1206,6 +1320,13 @@ module Datapath (
|
||||
M_I1_DataR
|
||||
);
|
||||
|
||||
// M.I1.TRAP
|
||||
assign M_I1_Trap = M.I1.Trap.TEN & ( M.I1.Trap.TP == NE ? M.I1.ALUOut != 32'b0
|
||||
: M.I1.Trap.TP == EQ ? M.I1.ALUOut == 32'b0
|
||||
: M.I1.Trap.TP == LT ? M.I1.ALUOut[0] == 1'b1
|
||||
: M.I1.Trap.TP == GE ? M.I1.ALUOut[0] == 1'b0
|
||||
: 1'b0);
|
||||
|
||||
assign M.en = M_go & W.en;
|
||||
assign M_go = (M.I0.MCtrl.HLS[2:1] != 2'b10 | M_I0_MULT_bvalid)
|
||||
& (M.I0.MCtrl.HLS != DIV | M_I0_DIV_bvalid)
|
||||
|
||||
@ -1,17 +1,5 @@
|
||||
`include "defines.svh"
|
||||
|
||||
module pcenr (
|
||||
input clk, rst,
|
||||
input word_t d,
|
||||
input logic en,
|
||||
output word_t q
|
||||
);
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (rst) q <= (`PCRST - 8);
|
||||
else if (en) q <= d;
|
||||
endmodule
|
||||
|
||||
module instr_valid (
|
||||
input word_t instr,
|
||||
output logic valid
|
||||
@ -19,12 +7,15 @@ module instr_valid (
|
||||
|
||||
always_comb
|
||||
casez (instr)
|
||||
32'b000000000000000000000?????001111: valid = 1'b1; // SYNC (NOP)
|
||||
32'b00000000000???????????????000000: valid = 1'b1; // SLL
|
||||
32'b00000000000???????????????000010: valid = 1'b1; // SRL
|
||||
32'b00000000000???????????????000011: valid = 1'b1; // SRA
|
||||
32'b000000???????????????00000000100: valid = 1'b1; // SLLV
|
||||
32'b000000???????????????00000000110: valid = 1'b1; // SRLV
|
||||
32'b000000???????????????00000000111: valid = 1'b1; // SRAV
|
||||
32'b000000???????????????00000001010: valid = 1'b1; // MOVZ
|
||||
32'b000000???????????????00000001011: valid = 1'b1; // MOVN
|
||||
32'b000000?????000000000000000001000: valid = 1'b1; // JR
|
||||
32'b000000?????00000?????00000001001: valid = 1'b1; // JALR
|
||||
32'b000000????????????????????001100: valid = 1'b1; // SYSCALL
|
||||
@ -47,9 +38,21 @@ module instr_valid (
|
||||
32'b000000???????????????00000100111: valid = 1'b1; // NOR
|
||||
32'b000000???????????????00000101010: valid = 1'b1; // SLT
|
||||
32'b000000???????????????00000101011: valid = 1'b1; // SLTU
|
||||
32'b000000????????????????????110000: valid = 1'b1; // TGE
|
||||
32'b000000????????????????????110001: valid = 1'b1; // TGEU
|
||||
32'b000000????????????????????110010: valid = 1'b1; // TLT
|
||||
32'b000000????????????????????110011: valid = 1'b1; // TLTU
|
||||
32'b000000????????????????????110100: valid = 1'b1; // TEQ
|
||||
32'b000000????????????????????110110: valid = 1'b1; // TNE
|
||||
32'b000001?????00000????????????????: valid = 1'b1; // BLTZ
|
||||
32'b000001?????10000????????????????: valid = 1'b1; // BLTZAL
|
||||
32'b000001?????00001????????????????: valid = 1'b1; // BGEZ
|
||||
32'b000001?????01000????????????????: valid = 1'b1; // TGEI
|
||||
32'b000001?????01001????????????????: valid = 1'b1; // TGEIU
|
||||
32'b000001?????01010????????????????: valid = 1'b1; // TLTI
|
||||
32'b000001?????01011????????????????: valid = 1'b1; // TLTIU
|
||||
32'b000001?????01110????????????????: valid = 1'b1; // TNEI
|
||||
32'b000001?????01100????????????????: valid = 1'b1; // TEQI
|
||||
32'b000001?????10000????????????????: valid = 1'b1; // BLTZAL
|
||||
32'b000001?????10001????????????????: valid = 1'b1; // BGEZAL
|
||||
32'b000010??????????????????????????: valid = 1'b1; // J
|
||||
32'b000011??????????????????????????: valid = 1'b1; // JAL
|
||||
@ -69,108 +72,34 @@ module instr_valid (
|
||||
32'b01000000100??????????00000000???: valid = 1'b1; // MTC0
|
||||
32'b01000010000000000000000000000001: valid = 1'b1; // TLBR
|
||||
32'b01000010000000000000000000000010: valid = 1'b1; // TLBWI
|
||||
32'b01000010000000000000000000000110: valid = 1'b1; // TLBWR
|
||||
32'b01000010000000000000000000001000: valid = 1'b1; // TLBP
|
||||
32'b01000010000000000000000000011000: valid = 1'b1; // ERET
|
||||
32'b011100??????????0000000000000000: valid = 1'b1; // MADD
|
||||
32'b011100??????????0000000000000001: valid = 1'b1; // MADDU
|
||||
32'b011100??????????0000000000000100: valid = 1'b1; // MSUB
|
||||
32'b011100??????????0000000000000101: valid = 1'b1; // MSUBU
|
||||
32'b011100???????????????00000000010: valid = 1'b1; // MUL
|
||||
32'b100000??????????????????????????: valid = 1'b1; // LB
|
||||
32'b100001??????????????????????????: valid = 1'b1; // LH
|
||||
32'b100010??????????????????????????: valid = 1'b1; // LWL
|
||||
32'b100011??????????????????????????: valid = 1'b1; // LW
|
||||
32'b100100??????????????????????????: valid = 1'b1; // LBU
|
||||
32'b100101??????????????????????????: valid = 1'b1; // LHU
|
||||
32'b100110??????????????????????????: valid = 1'b1; // LWR
|
||||
32'b101000??????????????????????????: valid = 1'b1; // SB
|
||||
32'b101001??????????????????????????: valid = 1'b1; // SH
|
||||
32'b101010??????????????????????????: valid = 1'b1; // SWL
|
||||
32'b101011??????????????????????????: valid = 1'b1; // SW
|
||||
// 32'b101111?????00000????????????????: valid = 1'b1; // I-Cache Index Invalid
|
||||
// 32'b101111?????01000????????????????: valid = 1'b1; // I-Cache Index Store Tag
|
||||
// 32'b101111?????10000????????????????: valid = 1'b1; // I-Cache Hit Invalid
|
||||
// 32'b101111?????00001????????????????: valid = 1'b1; // D-Cache Index Writeback Invalid
|
||||
// 32'b101111?????01001????????????????: valid = 1'b1; // D-Cache Index Store Tag
|
||||
// 32'b101111?????10001????????????????: valid = 1'b1; // D-Cache Hit Invalid
|
||||
// 32'b101111?????10101????????????????: valid = 1'b1; // D-Cache Hit Writeback Invalid
|
||||
32'b101110??????????????????????????: valid = 1'b1; // SWR
|
||||
32'b101111?????00000????????????????: valid = 1'b1; // I-Cache Index Invalid
|
||||
32'b101111?????01000????????????????: valid = 1'b1; // I-Cache Index Store Tag
|
||||
32'b101111?????10000????????????????: valid = 1'b1; // I-Cache Hit Invalid
|
||||
32'b101111?????00001????????????????: valid = 1'b1; // D-Cache Index Writeback Invalid
|
||||
32'b101111?????01001????????????????: valid = 1'b1; // D-Cache Index Store Tag
|
||||
32'b101111?????10001????????????????: valid = 1'b1; // D-Cache Hit Invalid
|
||||
32'b101111?????10101????????????????: valid = 1'b1; // D-Cache Hit Writeback Invalid
|
||||
32'b110011??????????????????????????: valid = 1'b1; // PREF (NOP)
|
||||
default: valid = 1'b0;
|
||||
endcase
|
||||
endmodule
|
||||
|
||||
module memerror (
|
||||
input logic [1:0] addr,
|
||||
input logic [1:0] size,
|
||||
output logic error
|
||||
);
|
||||
|
||||
always_comb
|
||||
casez (size)
|
||||
2'b1?: begin
|
||||
error = (addr != 2'b00);
|
||||
end
|
||||
2'b01: begin
|
||||
error = (addr[0] != 1'b0);
|
||||
end
|
||||
2'b00: begin
|
||||
error = 1'b0;
|
||||
end
|
||||
endcase
|
||||
endmodule
|
||||
|
||||
module memoutput (
|
||||
input logic [1:0] addr,
|
||||
input word_t data,
|
||||
input logic [1:0] size,
|
||||
output word_t wdata,
|
||||
output logic [3:0] wstrb
|
||||
);
|
||||
|
||||
always_comb
|
||||
casez (size)
|
||||
2'b1?: begin
|
||||
wdata = data;
|
||||
wstrb = 4'b1111;
|
||||
end
|
||||
2'b01: begin
|
||||
wdata = {2{data[15:0]}};
|
||||
wstrb = addr[1] ? 4'b1100 : 4'b0011;
|
||||
end
|
||||
2'b00: begin
|
||||
wdata = {4{data[7:0]}};
|
||||
case (addr)
|
||||
2'b11: wstrb = 4'b1000;
|
||||
2'b10: wstrb = 4'b0100;
|
||||
2'b01: wstrb = 4'b0010;
|
||||
2'b00: wstrb = 4'b0001;
|
||||
endcase
|
||||
end
|
||||
endcase
|
||||
endmodule
|
||||
|
||||
// module memoutput (
|
||||
// input logic [1:0] addr,
|
||||
// input word_t data,
|
||||
// input logic [1:0] size,
|
||||
// output word_t wdata,
|
||||
// output logic [3:0] wstrb,
|
||||
// output logic error
|
||||
// );
|
||||
|
||||
// always_comb
|
||||
// casez (size)
|
||||
// 2'b1?: begin
|
||||
// wdata = data;
|
||||
// wstrb = 4'b1111;
|
||||
// error = (addr != 2'b00);
|
||||
// end
|
||||
// 2'b01: begin
|
||||
// wdata = {2{data[15:0]}};
|
||||
// wstrb = addr[1] ? 4'b1100 : 4'b0011;
|
||||
// error = (addr[0] != 1'b0);
|
||||
// end
|
||||
// 2'b00: begin
|
||||
// wdata = {4{data[7:0]}};
|
||||
// case (addr)
|
||||
// 2'b11: wstrb = 4'b1000;
|
||||
// 2'b10: wstrb = 4'b0100;
|
||||
// 2'b01: wstrb = 4'b0010;
|
||||
// 2'b00: wstrb = 4'b0001;
|
||||
// endcase
|
||||
// error = 1'b0;
|
||||
// end
|
||||
// endcase
|
||||
// endmodule
|
||||
23
src/Core/Gadgets/memerror.sv
Normal file
23
src/Core/Gadgets/memerror.sv
Normal file
@ -0,0 +1,23 @@
|
||||
module memerror (
|
||||
input logic [1:0] addr,
|
||||
input logic [1:0] size,
|
||||
output logic error
|
||||
);
|
||||
|
||||
always_comb
|
||||
casez (size)
|
||||
2'b11: begin
|
||||
error = (addr != 2'b00);
|
||||
end
|
||||
2'b10: begin
|
||||
error = 1'b0;
|
||||
end
|
||||
2'b01: begin
|
||||
error = (addr[0] != 1'b0);
|
||||
end
|
||||
2'b00: begin
|
||||
error = 1'b0;
|
||||
end
|
||||
default: begin error = 1'b1; end
|
||||
endcase
|
||||
endmodule
|
||||
60
src/Core/Gadgets/memoutput.sv
Normal file
60
src/Core/Gadgets/memoutput.sv
Normal file
@ -0,0 +1,60 @@
|
||||
`include "defines.svh"
|
||||
|
||||
module memoutput (
|
||||
input logic [1:0] addr,
|
||||
input word_t data,
|
||||
input logic [1:0] size,
|
||||
input ALR_t alr,
|
||||
output word_t wdata,
|
||||
output logic [3:0] wstrb
|
||||
);
|
||||
// TODO: wdata fill zero or replica
|
||||
always_comb
|
||||
casez (size)
|
||||
2'b11: begin
|
||||
wdata = data;
|
||||
wstrb = 4'b1111;
|
||||
end
|
||||
2'b10: begin
|
||||
wdata = data;
|
||||
case (addr)
|
||||
2'b11: begin
|
||||
wstrb = alr[0] ? 4'b1111 : 4'b1000;
|
||||
wdata = alr[0] ? data
|
||||
: {data[7:0], data[31:8]};
|
||||
end
|
||||
2'b10: begin
|
||||
wstrb = alr[0] ? 4'b0111 : 4'b1100;
|
||||
wdata = alr[0] ? {data[7:0], data[31:8]}
|
||||
: {data[15:0], data[31:16]};
|
||||
end
|
||||
2'b01: begin
|
||||
wstrb = alr[0] ? 4'b0011 : 4'b1110;
|
||||
wdata = alr[0] ? {data[15:0], data[31:16]}
|
||||
: {data[23:0], data[31:24]};
|
||||
end
|
||||
2'b00: begin
|
||||
wstrb = alr[0] ? 4'b0001 : 4'b1111;
|
||||
wdata = alr[0] ? {data[23:0], data[31:24]}
|
||||
: data;
|
||||
end
|
||||
default: begin wstrb = 4'b0000; end
|
||||
endcase
|
||||
end
|
||||
2'b01: begin
|
||||
wdata = {2{data[15:0]}};
|
||||
wstrb = addr[1] ? 4'b1100 : 4'b0011;
|
||||
end
|
||||
2'b00: begin
|
||||
wdata = {4{data[7:0]}};
|
||||
case (addr)
|
||||
2'b11: wstrb = 4'b1000;
|
||||
2'b10: wstrb = 4'b0100;
|
||||
2'b01: wstrb = 4'b0010;
|
||||
2'b00: wstrb = 4'b0001;
|
||||
default: wstrb = 4'b0000;
|
||||
endcase
|
||||
end
|
||||
default: begin wstrb = 4'b0000; end
|
||||
endcase
|
||||
endmodule
|
||||
13
src/Core/Gadgets/pcenr.sv
Normal file
13
src/Core/Gadgets/pcenr.sv
Normal file
@ -0,0 +1,13 @@
|
||||
`include "defines.svh"
|
||||
|
||||
module pcenr (
|
||||
input clk, rst,
|
||||
input word_t d,
|
||||
input logic en,
|
||||
output word_t q
|
||||
);
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (rst) q <= (`PCRST - 8);
|
||||
else if (en) q <= d;
|
||||
endmodule
|
||||
@ -1,7 +1,8 @@
|
||||
`include "defines.svh"
|
||||
|
||||
module RF (
|
||||
input clk,
|
||||
input logic clk,
|
||||
input logic rst,
|
||||
input logic [4:0] raddr1,
|
||||
input logic [4:0] raddr2,
|
||||
input logic [4:0] raddr3,
|
||||
@ -20,11 +21,11 @@ module RF (
|
||||
|
||||
word_t rf[31:0];
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if(we1 & waddr1 != 0)
|
||||
rf[waddr1] <= wdata1;
|
||||
if(we2 & waddr2 != 0)
|
||||
rf[waddr2] <= wdata2;
|
||||
always_ff @(posedge clk)
|
||||
if (rst) for (int i = 0; i < 32; i = i + 1) rf[i] <= 32'b0;
|
||||
else begin
|
||||
if (we1 & waddr1 != 0) rf[waddr1] <= wdata1;
|
||||
if (we2 & waddr2 != 0) rf[waddr2] <= wdata2;
|
||||
end
|
||||
|
||||
assign rdata1 = raddr1 != 0 ? rf[raddr1] : 32'b0;
|
||||
|
||||
263
src/Gadgets.sv
263
src/Gadgets.sv
@ -1,263 +0,0 @@
|
||||
module ffen #(
|
||||
parameter WIDTH = 8
|
||||
) (
|
||||
input logic clk,
|
||||
input logic [WIDTH-1:0] d,
|
||||
input logic en,
|
||||
output logic [WIDTH-1:0] q
|
||||
);
|
||||
|
||||
always_ff @(posedge clk) if (en) q <= d;
|
||||
endmodule
|
||||
|
||||
module ffenr #(
|
||||
parameter WIDTH = 8
|
||||
) (
|
||||
input logic clk,
|
||||
input logic rst,
|
||||
input logic [WIDTH-1:0] d,
|
||||
input logic en,
|
||||
output logic [WIDTH-1:0] q
|
||||
);
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (rst) q <= {WIDTH{1'b0}};
|
||||
else if (en) q <= d;
|
||||
endmodule
|
||||
|
||||
module ffenrc #(
|
||||
parameter WIDTH = 8
|
||||
) (
|
||||
input logic clk,
|
||||
input logic rst,
|
||||
input logic [WIDTH-1:0] d,
|
||||
input logic en,
|
||||
input logic c,
|
||||
output logic [WIDTH-1:0] q
|
||||
);
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (rst) q <= {WIDTH{1'b0}};
|
||||
else if (en) q <= c ? {WIDTH{1'b0}} : d;
|
||||
endmodule
|
||||
|
||||
module mux2 #(
|
||||
parameter WIDTH = 8
|
||||
) (
|
||||
input logic [WIDTH-1:0] d0,
|
||||
input logic [WIDTH-1:0] d1,
|
||||
input logic s,
|
||||
output logic [WIDTH-1:0] q
|
||||
);
|
||||
|
||||
assign q = s ? d1 : d0;
|
||||
|
||||
endmodule
|
||||
|
||||
module mux3 #(
|
||||
parameter WIDTH = 8
|
||||
) (
|
||||
input logic [WIDTH-1:0] d0,
|
||||
input logic [WIDTH-1:0] d1,
|
||||
input logic [WIDTH-1:0] d2,
|
||||
input logic [ 1:0] s,
|
||||
output logic [WIDTH-1:0] q
|
||||
);
|
||||
|
||||
assign q = s[1] ? d2 : s[0] ? d1 : d0;
|
||||
|
||||
endmodule
|
||||
|
||||
module mux4 #(
|
||||
parameter WIDTH = 8
|
||||
) (
|
||||
input logic [WIDTH-1:0] d0,
|
||||
input logic [WIDTH-1:0] d1,
|
||||
input logic [WIDTH-1:0] d2,
|
||||
input logic [WIDTH-1:0] d3,
|
||||
input logic [ 1:0] s,
|
||||
output logic [WIDTH-1:0] q
|
||||
);
|
||||
|
||||
assign q = s[1] ? s[0] ? d3 : d2 : s[0] ? d1 : d0;
|
||||
|
||||
endmodule
|
||||
|
||||
module mux5 #(
|
||||
parameter WIDTH = 8
|
||||
) (
|
||||
input logic [WIDTH-1:0] d0,
|
||||
input logic [WIDTH-1:0] d1,
|
||||
input logic [WIDTH-1:0] d2,
|
||||
input logic [WIDTH-1:0] d3,
|
||||
input logic [WIDTH-1:0] d4,
|
||||
input logic [ 2:0] s,
|
||||
output logic [WIDTH-1:0] q
|
||||
);
|
||||
|
||||
assign q = s[2] ? d4 : s[1] ? s[0] ? d3 : d2 : s[0] ? d1 : d0;
|
||||
|
||||
endmodule
|
||||
|
||||
module mux6 #(
|
||||
parameter WIDTH = 8
|
||||
) (
|
||||
input logic [WIDTH-1:0] d0,
|
||||
input logic [WIDTH-1:0] d1,
|
||||
input logic [WIDTH-1:0] d2,
|
||||
input logic [WIDTH-1:0] d3,
|
||||
input logic [WIDTH-1:0] d4,
|
||||
input logic [WIDTH-1:0] d5,
|
||||
|
||||
input logic [ 2:0] s,
|
||||
output logic [WIDTH-1:0] q
|
||||
);
|
||||
|
||||
always_comb begin
|
||||
case (s)
|
||||
3'b000: q = d0;
|
||||
3'b001: q = d1;
|
||||
3'b010: q = d2;
|
||||
3'b011: q = d3;
|
||||
3'b100: q = d4;
|
||||
default: q = d5;
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
|
||||
module prio_mux4 #(
|
||||
parameter WIDTH = 8
|
||||
) (
|
||||
input logic [WIDTH-1:0] d0,
|
||||
input logic [WIDTH-1:0] d1,
|
||||
input logic [WIDTH-1:0] d2,
|
||||
input logic [WIDTH-1:0] d3,
|
||||
input logic [ 2:0] s,
|
||||
output logic [WIDTH-1:0] q
|
||||
);
|
||||
|
||||
assign q = s[2] ? d3 : s[1] ? d2 : s[0] ? d1 : d0;
|
||||
|
||||
endmodule
|
||||
|
||||
module prio_mux5 #(
|
||||
parameter WIDTH = 8
|
||||
) (
|
||||
input logic [WIDTH-1:0] d0,
|
||||
input logic [WIDTH-1:0] d1,
|
||||
input logic [WIDTH-1:0] d2,
|
||||
input logic [WIDTH-1:0] d3,
|
||||
input logic [WIDTH-1:0] d4,
|
||||
input logic [ 3:0] s,
|
||||
output logic [WIDTH-1:0] q
|
||||
);
|
||||
|
||||
assign q = s[3] ? d4 : s[2] ? d3 : s[1] ? d2 : s[0] ? d1 : d0;
|
||||
|
||||
endmodule
|
||||
|
||||
module onehot_bin4 (
|
||||
input logic [3:0] onehot,
|
||||
output logic [1:0] bin
|
||||
);
|
||||
assign bin = {onehot[3] | onehot[2], onehot[3] | onehot[1]};
|
||||
endmodule
|
||||
|
||||
module onehot_bin8 (
|
||||
input logic [7:0] onehot,
|
||||
output logic [2:0] bin
|
||||
);
|
||||
logic [1:0] bin1, bin0;
|
||||
onehot_bin4 onehot_bin4_1(onehot[7:4], bin1);
|
||||
onehot_bin4 onehot_bin4_0(onehot[3:0], bin0);
|
||||
assign bin = {|{onehot[7:4]}, bin1 | bin0};
|
||||
endmodule
|
||||
|
||||
module onehot_bin16 (
|
||||
input logic [15:0] onehot,
|
||||
output logic [ 3:0] bin
|
||||
);
|
||||
logic [2:0] bin1, bin0;
|
||||
onehot_bin8 onehot_bin8_1(onehot[15:8], bin1);
|
||||
onehot_bin8 onehot_bin8_0(onehot[ 7:0], bin0);
|
||||
assign bin = {|{onehot[15:8]}, bin1 | bin0};
|
||||
endmodule
|
||||
|
||||
module onehot_bin32 (
|
||||
input logic [31:0] onehot,
|
||||
output logic [ 4:0] bin
|
||||
);
|
||||
logic [3:0] bin1, bin0;
|
||||
onehot_bin16 onehot_bin16_1(onehot[31:16], bin1);
|
||||
onehot_bin16 onehot_bin16_0(onehot[15: 0], bin0);
|
||||
assign bin = {|{onehot[31:16]}, bin1 | bin0};
|
||||
endmodule
|
||||
|
||||
module extender #(
|
||||
parameter OWIDTH = 8,
|
||||
parameter IWIDTH = 8
|
||||
) (
|
||||
input logic [IWIDTH-1:0] d,
|
||||
input logic s,
|
||||
output logic [OWIDTH-1:0] q
|
||||
);
|
||||
|
||||
assign q = {{(OWIDTH - IWIDTH) {s & d[IWIDTH-1]}}, d};
|
||||
|
||||
endmodule
|
||||
|
||||
module buffer0 #(
|
||||
parameter WIDTH = 8
|
||||
) (
|
||||
input clk,
|
||||
input rst,
|
||||
input logic [WIDTH-1:0] data,
|
||||
input logic en,
|
||||
output logic [WIDTH-1:0] bdata
|
||||
);
|
||||
|
||||
logic [WIDTH-1:0] data1;
|
||||
|
||||
ffenr #(WIDTH) data_ff (
|
||||
clk,
|
||||
rst,
|
||||
data,
|
||||
en,
|
||||
data1
|
||||
);
|
||||
|
||||
assign bdata = en ? data : data1;
|
||||
endmodule
|
||||
|
||||
module buffer #(
|
||||
parameter WIDTH = 8
|
||||
) (
|
||||
input clk,
|
||||
input rst,
|
||||
input logic prev_valid,
|
||||
input logic [WIDTH-1:0] prev_data,
|
||||
input logic next_en,
|
||||
output logic next_valid,
|
||||
output logic [WIDTH-1:0] next_data
|
||||
);
|
||||
|
||||
logic valid;
|
||||
logic [WIDTH-1:0] data;
|
||||
|
||||
ffenr #(1) valid_ff (
|
||||
clk,
|
||||
rst,
|
||||
prev_valid,
|
||||
prev_valid ^ next_en,
|
||||
valid
|
||||
);
|
||||
ffen #(WIDTH) data_ff (
|
||||
clk,
|
||||
prev_data,
|
||||
prev_valid,
|
||||
data
|
||||
);
|
||||
|
||||
assign next_valid = valid | prev_valid;
|
||||
assign next_data = valid ? data : prev_data;
|
||||
endmodule
|
||||
12
src/Gadgets/extender.sv
Normal file
12
src/Gadgets/extender.sv
Normal file
@ -0,0 +1,12 @@
|
||||
module extender #(
|
||||
parameter OWIDTH = 8,
|
||||
parameter IWIDTH = 8
|
||||
) (
|
||||
input logic [IWIDTH-1:0] d,
|
||||
input logic s,
|
||||
output logic [OWIDTH-1:0] q
|
||||
);
|
||||
|
||||
assign q = {{(OWIDTH - IWIDTH) {s & d[IWIDTH-1]}}, d};
|
||||
|
||||
endmodule
|
||||
11
src/Gadgets/ffen.sv
Normal file
11
src/Gadgets/ffen.sv
Normal file
@ -0,0 +1,11 @@
|
||||
module ffen #(
|
||||
parameter WIDTH = 8
|
||||
) (
|
||||
input logic clk,
|
||||
input logic [WIDTH-1:0] d,
|
||||
input logic en,
|
||||
output logic [WIDTH-1:0] q
|
||||
);
|
||||
|
||||
always_ff @(posedge clk) if (en) q <= d;
|
||||
endmodule
|
||||
14
src/Gadgets/ffenr.sv
Normal file
14
src/Gadgets/ffenr.sv
Normal file
@ -0,0 +1,14 @@
|
||||
module ffenr #(
|
||||
parameter WIDTH = 8
|
||||
) (
|
||||
input logic clk,
|
||||
input logic rst,
|
||||
input logic [WIDTH-1:0] d,
|
||||
input logic en,
|
||||
output logic [WIDTH-1:0] q
|
||||
);
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (rst) q <= {WIDTH{1'b0}};
|
||||
else if (en) q <= d;
|
||||
endmodule
|
||||
15
src/Gadgets/ffenrc.sv
Normal file
15
src/Gadgets/ffenrc.sv
Normal file
@ -0,0 +1,15 @@
|
||||
module ffenrc #(
|
||||
parameter WIDTH = 8
|
||||
) (
|
||||
input logic clk,
|
||||
input logic rst,
|
||||
input logic [WIDTH-1:0] d,
|
||||
input logic en,
|
||||
input logic c,
|
||||
output logic [WIDTH-1:0] q
|
||||
);
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (rst) q <= {WIDTH{1'b0}};
|
||||
else if (en) q <= c ? {WIDTH{1'b0}} : d;
|
||||
endmodule
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user