From b2a7bbf7fa0eee0dcf75feb41a78f5adfe0ec3e2 Mon Sep 17 00:00:00 2001 From: Paul Pan Date: Thu, 5 Jan 2023 17:17:36 +0800 Subject: [PATCH] sync --- resources/top/mycpu_block.xdc | 81 ++++++++++++++++ resources/top/mycpu_top_verilog.v | 91 +++++++++++++++++ src/CP0/CP0.sv | 8 +- src/Core/Datapath.sv | 46 +-------- src/Core/RF.sv | 12 +-- src/IP/DCData_bram/DCData_bram.xci | 88 ++++++++++++++++- src/IP/DCTag_bram/DCTag_bram.xci | 88 ++++++++++++++++- src/IP/ICData_bram/ICData_bram.xci | 88 ++++++++++++++++- src/IP/ICTag_bram/ICTag_bram.xci | 88 ++++++++++++++++- src/IP/div_signed/div_signed.xci | 140 +++++++++++++++++++++++++-- src/IP/div_unsigned/div_unsigned.xci | 140 +++++++++++++++++++++++++-- src/IP/mul_signed/mul_signed.xci | 92 +++++++++++++++++- src/IP/mul_unsigned/mul_unsigned.xci | 92 +++++++++++++++++- 13 files changed, 963 insertions(+), 91 deletions(-) create mode 100644 resources/top/mycpu_block.xdc create mode 100644 resources/top/mycpu_top_verilog.v diff --git a/resources/top/mycpu_block.xdc b/resources/top/mycpu_block.xdc new file mode 100644 index 0000000..a5fbf83 --- /dev/null +++ b/resources/top/mycpu_block.xdc @@ -0,0 +1,81 @@ +#set_property SEVERITY {Warning} [get_drc_checks RTSTAT-2] +#时钟信号连接 +#create_clock -period 10.000 [get_ports clk] +set_property PACKAGE_PIN AC19 [get_ports clk] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk] +create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk] + +#reset +set_property PACKAGE_PIN Y3 [get_ports resetn_rtl_0] + +#SPI flash +set_property PACKAGE_PIN P20 [get_ports spi_rtl_0_sck_io] +set_property PACKAGE_PIN R20 [get_ports {spi_rtl_0_ss_io[0]}] +set_property PACKAGE_PIN P19 [get_ports spi_rtl_0_io1_io] +set_property PACKAGE_PIN N18 [get_ports spi_rtl_0_io0_io] + +#mac phy connect +set_property PACKAGE_PIN AB21 [get_ports mii_rtl_0_tx_clk] +set_property PACKAGE_PIN AA19 [get_ports mii_rtl_0_rx_clk] +set_property PACKAGE_PIN AA15 [get_ports mii_rtl_0_tx_en] +set_property PACKAGE_PIN AF18 [get_ports {mii_rtl_0_txd[0]}] +set_property PACKAGE_PIN AE18 [get_ports {mii_rtl_0_txd[1]}] +set_property PACKAGE_PIN W15 [get_ports {mii_rtl_0_txd[2]}] +set_property PACKAGE_PIN W14 [get_ports {mii_rtl_0_txd[3]}] +set_property PACKAGE_PIN AE22 [get_ports mii_rtl_0_rx_dv] +set_property PACKAGE_PIN V1 [get_ports {mii_rtl_0_rxd[0]}] +set_property PACKAGE_PIN V4 [get_ports {mii_rtl_0_rxd[1]}] +set_property PACKAGE_PIN V2 [get_ports {mii_rtl_0_rxd[2]}] +set_property PACKAGE_PIN V3 [get_ports {mii_rtl_0_rxd[3]}] +set_property PACKAGE_PIN W16 [get_ports mii_rtl_0_rx_er] +set_property PACKAGE_PIN Y15 [get_ports mii_rtl_0_col] +set_property PACKAGE_PIN AF20 [get_ports mii_rtl_0_crs] +set_property PACKAGE_PIN W3 [get_ports mdio_rtl_0_mdc] +set_property PACKAGE_PIN W1 [get_ports mdio_rtl_0_mdio_io] +set_property PACKAGE_PIN AE26 [get_ports mii_rtl_0_rst_n] + +#uart +set_property PACKAGE_PIN F23 [get_ports uart_rtl_0_rxd] +set_property PACKAGE_PIN H19 [get_ports uart_rtl_0_txd] +set_property PACKAGE_PIN E23 [get_ports uart_rtl_0_cts] +set_property PACKAGE_PIN G20 [get_ports uart_rtl_0_dcd] +set_property PACKAGE_PIN K6 [get_ports uart_rtl_0_dsr] +set_property PACKAGE_PIN F25 [get_ports uart_rtl_0_dtr] +set_property PACKAGE_PIN K7 [get_ports uart_rtl_0_ri] +set_property PACKAGE_PIN F24 [get_ports uart_rtl_0_rts] + +set_property IOSTANDARD LVCMOS33 [get_ports clk] +set_property IOSTANDARD LVCMOS33 [get_ports resetn_rtl_0] + +set_property IOSTANDARD LVCMOS33 [get_ports spi_rtl_0_io0_io] +set_property IOSTANDARD LVCMOS33 [get_ports spi_rtl_0_io1_io] +set_property IOSTANDARD LVCMOS33 [get_ports {spi_rtl_0_ss_io[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports spi_rtl_0_sck_io] + +set_property IOSTANDARD LVCMOS33 [get_ports {mii_rtl_0_rxd[*]}] +set_property IOSTANDARD LVCMOS33 [get_ports {mii_rtl_0_txd[*]}] +set_property IOSTANDARD LVCMOS33 [get_ports mii_rtl_0_rst_n] +set_property IOSTANDARD LVCMOS33 [get_ports mii_rtl_0_tx_en] +set_property IOSTANDARD LVCMOS33 [get_ports mii_rtl_0_tx_clk] +set_property IOSTANDARD LVCMOS33 [get_ports mii_rtl_0_rx_er] +set_property IOSTANDARD LVCMOS33 [get_ports mii_rtl_0_col] +set_property IOSTANDARD LVCMOS33 [get_ports mii_rtl_0_crs] +set_property IOSTANDARD LVCMOS33 [get_ports mdio_rtl_0_mdc] +set_property IOSTANDARD LVCMOS33 [get_ports mdio_rtl_0_mdio_io] +set_property IOSTANDARD LVCMOS33 [get_ports mii_rtl_0_rx_clk] +set_property IOSTANDARD LVCMOS33 [get_ports mii_rtl_0_rx_dv] + +set_property IOSTANDARD LVCMOS33 [get_ports uart_rtl_0_rxd] +set_property IOSTANDARD LVCMOS33 [get_ports uart_rtl_0_txd] +set_property IOSTANDARD LVCMOS33 [get_ports uart_rtl_0_cts] +set_property IOSTANDARD LVCMOS33 [get_ports uart_rtl_0_dcd] +set_property IOSTANDARD LVCMOS33 [get_ports uart_rtl_0_dsr] +set_property IOSTANDARD LVCMOS33 [get_ports uart_rtl_0_dtr] +set_property IOSTANDARD LVCMOS33 [get_ports uart_rtl_0_ri] +set_property IOSTANDARD LVCMOS33 [get_ports uart_rtl_0_rts] + +create_clock -period 40.000 -name mii_rtl_0_rx_clk -waveform {0.000 20.000} [get_ports mii_rtl_0_rx_clk] +create_clock -period 40.000 -name mii_rtl_0_tx_clk -waveform {0.000 20.000} [get_ports mii_rtl_0_tx_clk] + + + diff --git a/resources/top/mycpu_top_verilog.v b/resources/top/mycpu_top_verilog.v new file mode 100644 index 0000000..1369389 --- /dev/null +++ b/resources/top/mycpu_top_verilog.v @@ -0,0 +1,91 @@ +module mycpu_top_verilog ( + input wire [5:0] ext_int, //high active + + input wire aclk, + input wire aresetn, //low active + + output wire [ 3:0] arid, + output wire [31:0] araddr, + output wire [ 3:0] arlen, + output wire [ 2:0] arsize, + output wire [ 1:0] arburst, + output wire [ 1:0] arlock, + output wire [ 3:0] arcache, + output wire [ 2:0] arprot, + output wire arvalid, + input wire arready, + + input wire [ 3:0] rid, + input wire [31:0] rdata, + input wire [ 1:0] rresp, + input wire rlast, + input wire rvalid, + output wire rready, + + output wire [ 3:0] awid, + output wire [31:0] awaddr, + output wire [ 3:0] awlen, + output wire [ 2:0] awsize, + output wire [ 1:0] awburst, + output wire [ 1:0] awlock, + output wire [ 3:0] awcache, + output wire [ 2:0] awprot, + output wire awvalid, + input wire awready, + + output wire [ 3:0] wid, + output wire [31:0] wdata, + output wire [ 3:0] wstrb, + output wire wlast, + output wire wvalid, + input wire wready, + + input wire [3:0] bid, + input wire [1:0] bresp, + input wire bvalid, + output wire bready +); + + mycpu_top cpu( + .ext_int(ext_int), + .aclk (aclk), + .aresetn(aresetn), + .arid (arid), + .araddr (araddr), + .arlen (arlen), + .arsize (arsize), + .arburst(arburst), + .arlock (arlock), + .arcache(arcache), + .arprot (arprot), + .arvalid(arvalid), + .arready(arready), + .rid (rid), + .rdata (rdata), + .rresp (rresp), + .rlast (rlast), + .rvalid (rvalid), + .rready (rready), + .awid (awid), + .awaddr (awaddr), + .awlen (awlen), + .awsize (awsize), + .awburst(awburst), + .awlock (awlock), + .awcache(awcache), + .awprot (awprot), + .awvalid(awvalid), + .awready(awready), + .wid (wid), + .wdata (wdata), + .wstrb (wstrb), + .wlast (wlast), + .wvalid (wvalid), + .wready (wready), + .bid (bid), + .bresp (bresp), + .bvalid (bvalid), + .bready (bready) + ); + +endmodule diff --git a/src/CP0/CP0.sv b/src/CP0/CP0.sv index 557fb9a..4f38b7a 100644 --- a/src/CP0/CP0.sv +++ b/src/CP0/CP0.sv @@ -40,10 +40,10 @@ module CP0 ( CP0_REGS_t rf_cp0; logic count_lo; - (*mark_debug = "true"*) word_t ila_cp0_count; - (*mark_debug = "true"*) word_t ila_cp0_compare; - (*mark_debug = "true"*) word_t ila_cp0_cause; - (*mark_debug = "true"*) word_t ila_cp0_status; + word_t ila_cp0_count; + word_t ila_cp0_compare; + word_t ila_cp0_cause; + word_t ila_cp0_status; assign ila_cp0_count = rf_cp0.Count; assign ila_cp0_compare = rf_cp0.Compare; assign ila_cp0_cause = rf_cp0.Cause; diff --git a/src/Core/Datapath.sv b/src/Core/Datapath.sv index 141c007..0d2c401 100644 --- a/src/Core/Datapath.sv +++ b/src/Core/Datapath.sv @@ -31,7 +31,7 @@ module Datapath ( input word_t C0_rdata, output logic C0_we, output word_t C0_wdata, - (*mark_debug = "true"*) output EXCEPTION_t C0_exception, + output EXCEPTION_t C0_exception, input word_t C0_ERETPC, input logic C0_EXL, input logic C0_Bev, @@ -124,8 +124,8 @@ module Datapath ( logic D_IB_FT_W_I1; word_t D_IB_ForwardT; - (*mark_debug = "true"*) logic D_IA_valid; - (*mark_debug = "true"*) logic D_IB_valid; + logic D_IA_valid; + logic D_IB_valid; logic D_IA_ri; logic D_IB_ri; logic D_IA_cpu; @@ -295,31 +295,6 @@ module Datapath ( word_t HI; word_t LO; - (*mark_debug = "true"*) word_t ila_D_IA_PC; - (*mark_debug = "true"*) word_t ila_D_IB_PC; - (*mark_debug = "true"*) word_t ila_E_I1_PC; - assign ila_D_IA_PC = D.IA_pc; - assign ila_D_IB_PC = D.IB_pc; - assign ila_E_I1_PC = E.I1.pc; - (*mark_debug = "true"*) word_t ila_D_IA_inst; - (*mark_debug = "true"*) word_t ila_D_IB_inst; - assign ila_D_IA_inst = D.IA_inst; - assign ila_D_IB_inst = D.IB_inst; - - (*mark_debug = "true"*) word_t ila_addr; - (*mark_debug = "true"*) word_t ila_wdata; - (*mark_debug = "true"*) word_t ila_rdata; - (*mark_debug = "true"*) logic ila_req; - (*mark_debug = "true"*) logic ila_wr; - (*mark_debug = "true"*) logic ila_addr_ok; - (*mark_debug = "true"*) logic ila_data_ok; - assign ila_addr = mem_i.addr; - assign ila_wdata = mem_i.wdata; - assign ila_rdata = mem_i.rdata; - assign ila_req = mem_i.req; - assign ila_wr = mem_i.wr; - assign ila_addr_ok = mem_i.addr_ok; - assign ila_data_ok = mem_i.data_ok; //---------------------------------------------------------------------------// // Pre Fetch // @@ -1537,20 +1512,5 @@ module Datapath ( assign W.en = 1'b1; - word_t magic_target1; - word_t magic_target2; - (*mark_debug = "true"*) word_t magic_counter; - - assign magic_target1 = 32'h87cc0620; - assign magic_target2 = 32'h87cc0624; - - always_ff@(posedge clk) begin - if (rst) magic_counter <= 0; - else begin - if (mem_i.req & mem_i.addr_ok & (mem_i.addr == magic_target1 | mem_i.addr == magic_target2)) begin - magic_counter <= magic_counter + 1; - end - end - end endmodule diff --git a/src/Core/RF.sv b/src/Core/RF.sv index 00c1f08..49b2ad4 100644 --- a/src/Core/RF.sv +++ b/src/Core/RF.sv @@ -7,12 +7,12 @@ module RF ( input logic [4:0] raddr2, input logic [4:0] raddr3, input logic [4:0] raddr4, - (*mark_debug = "true"*) input logic we1, - (*mark_debug = "true"*) input logic we2, - (*mark_debug = "true"*) input logic [4:0] waddr1, - (*mark_debug = "true"*) input logic [4:0] waddr2, - (*mark_debug = "true"*) input word_t wdata1, - (*mark_debug = "true"*) input word_t wdata2, + input logic we1, + input logic we2, + input logic [4:0] waddr1, + input logic [4:0] waddr2, + input word_t wdata1, + input word_t wdata2, output word_t rdata1, output word_t rdata2, output word_t rdata3, diff --git a/src/IP/DCData_bram/DCData_bram.xci b/src/IP/DCData_bram/DCData_bram.xci index 901f86c..c6e84f9 100644 --- a/src/IP/DCData_bram/DCData_bram.xci +++ b/src/IP/DCData_bram/DCData_bram.xci @@ -33,7 +33,7 @@ 1 1 1 - 0.000 + 0.0 AXI4LITE READ_WRITE 0 @@ -64,7 +64,7 @@ 1 1 1 - 0.000 + 0.0 AXI4LITE READ_WRITE 0 @@ -84,10 +84,12 @@ 32 1 + 100000000 + 0 0 - 0.000 + 0.0 0 7 7 @@ -250,12 +252,12 @@ TRUE TRUE IP_Flow - 4 + 5 TRUE . . - 2019.2 + 2022.1 OUT_OF_CONTEXT @@ -304,6 +306,82 @@ + + + diff --git a/src/IP/DCTag_bram/DCTag_bram.xci b/src/IP/DCTag_bram/DCTag_bram.xci index 782c2ad..3d59877 100644 --- a/src/IP/DCTag_bram/DCTag_bram.xci +++ b/src/IP/DCTag_bram/DCTag_bram.xci @@ -33,7 +33,7 @@ 1 1 1 - 0.000 + 0.0 AXI4LITE READ_WRITE 0 @@ -64,7 +64,7 @@ 1 1 1 - 0.000 + 0.0 AXI4LITE READ_WRITE 0 @@ -84,10 +84,12 @@ 32 1 + 100000000 + 0 0 - 0.000 + 0.0 0 7 7 @@ -250,12 +252,12 @@ TRUE TRUE IP_Flow - 4 + 5 TRUE . . - 2019.2 + 2022.1 OUT_OF_CONTEXT @@ -304,6 +306,82 @@ + + + diff --git a/src/IP/ICData_bram/ICData_bram.xci b/src/IP/ICData_bram/ICData_bram.xci index 3714074..998162c 100644 --- a/src/IP/ICData_bram/ICData_bram.xci +++ b/src/IP/ICData_bram/ICData_bram.xci @@ -33,7 +33,7 @@ 1 1 1 - 0.000 + 0.0 AXI4LITE READ_WRITE 0 @@ -64,7 +64,7 @@ 1 1 1 - 0.000 + 0.0 AXI4LITE READ_WRITE 0 @@ -84,10 +84,12 @@ 32 1 + 100000000 + 0 0 - 0.000 + 0.0 0 6 6 @@ -250,12 +252,12 @@ TRUE TRUE IP_Flow - 4 + 5 TRUE . . - 2019.2 + 2022.1 OUT_OF_CONTEXT @@ -304,6 +306,82 @@ + + + diff --git a/src/IP/ICTag_bram/ICTag_bram.xci b/src/IP/ICTag_bram/ICTag_bram.xci index 603ae22..ce3007a 100644 --- a/src/IP/ICTag_bram/ICTag_bram.xci +++ b/src/IP/ICTag_bram/ICTag_bram.xci @@ -33,7 +33,7 @@ 1 1 1 - 0.000 + 0.0 AXI4LITE READ_WRITE 0 @@ -64,7 +64,7 @@ 1 1 1 - 0.000 + 0.0 AXI4LITE READ_WRITE 0 @@ -84,10 +84,12 @@ 32 1 + 100000000 + 0 0 - 0.000 + 0.0 0 6 6 @@ -250,12 +252,12 @@ TRUE TRUE IP_Flow - 4 + 5 TRUE . . - 2019.2 + 2022.1 OUT_OF_CONTEXT @@ -304,6 +306,82 @@ + + + diff --git a/src/IP/div_signed/div_signed.xci b/src/IP/div_signed/div_signed.xci index 70127da..89ce9c3 100644 --- a/src/IP/div_signed/div_signed.xci +++ b/src/IP/div_signed/div_signed.xci @@ -9,10 +9,12 @@ div_signed + 1000000 + 0 0 - 0.000 + 0.0 0 100000000 @@ -22,7 +24,7 @@ 0 0 undef - 0.000 + 0.0 8 0 0 @@ -35,7 +37,7 @@ 0 0 undef - 0.000 + 0.0 4 0 0 @@ -48,7 +50,7 @@ 0 0 undef - 0.000 + 0.0 4 0 0 @@ -114,12 +116,12 @@ TRUE TRUE IP_Flow - 16 + 19 TRUE . . - 2019.2 + 2022.1 OUT_OF_CONTEXT @@ -154,6 +156,132 @@ + + + diff --git a/src/IP/div_unsigned/div_unsigned.xci b/src/IP/div_unsigned/div_unsigned.xci index 41ca748..da1c51f 100644 --- a/src/IP/div_unsigned/div_unsigned.xci +++ b/src/IP/div_unsigned/div_unsigned.xci @@ -9,10 +9,12 @@ div_unsigned + 1000000 + 0 0 - 0.000 + 0.0 0 100000000 @@ -22,7 +24,7 @@ 0 0 undef - 0.000 + 0.0 8 0 0 @@ -35,7 +37,7 @@ 0 0 undef - 0.000 + 0.0 4 0 0 @@ -48,7 +50,7 @@ 0 0 undef - 0.000 + 0.0 4 0 0 @@ -114,12 +116,12 @@ TRUE TRUE IP_Flow - 16 + 19 TRUE . . - 2019.2 + 2022.1 OUT_OF_CONTEXT @@ -151,6 +153,132 @@ + + + diff --git a/src/IP/mul_signed/mul_signed.xci b/src/IP/mul_signed/mul_signed.xci index f6f3cc1..43b082f 100644 --- a/src/IP/mul_signed/mul_signed.xci +++ b/src/IP/mul_signed/mul_signed.xci @@ -11,10 +11,12 @@ undef undef + 10000000 + 0 0 - 0.000 + 0.0 undef 0 0 @@ -72,12 +74,12 @@ TRUE TRUE IP_Flow - 16 + 18 TRUE . . - 2019.2 + 2022.1 OUT_OF_CONTEXT @@ -89,6 +91,90 @@ + + + diff --git a/src/IP/mul_unsigned/mul_unsigned.xci b/src/IP/mul_unsigned/mul_unsigned.xci index 8669a8b..3eb2d1a 100644 --- a/src/IP/mul_unsigned/mul_unsigned.xci +++ b/src/IP/mul_unsigned/mul_unsigned.xci @@ -11,10 +11,12 @@ undef undef + 10000000 + 0 0 - 0.000 + 0.0 undef 0 1 @@ -72,12 +74,12 @@ TRUE TRUE IP_Flow - 16 + 18 TRUE . . - 2019.2 + 2022.1 OUT_OF_CONTEXT @@ -91,6 +93,90 @@ + + +