From af73d410f22ee0f0db6a91d72d87400203851b79 Mon Sep 17 00:00:00 2001 From: Hooo1941 Date: Fri, 9 Jul 2021 10:11:48 +0800 Subject: [PATCH] [Core] add mul --- src/Core/mul.sv | 44 +++++++++++++ src/IP/mul_signed/mul_signed.xci | 96 +++++++++++++++++++++++++++ src/IP/mul_unsigned/mul_unsigned.xci | 98 ++++++++++++++++++++++++++++ 3 files changed, 238 insertions(+) create mode 100644 src/Core/mul.sv create mode 100644 src/IP/mul_signed/mul_signed.xci create mode 100644 src/IP/mul_unsigned/mul_unsigned.xci diff --git a/src/Core/mul.sv b/src/Core/mul.sv new file mode 100644 index 0000000..cbcd35c --- /dev/null +++ b/src/Core/mul.sv @@ -0,0 +1,44 @@ +`timescale 1ns / 1ps +module mul( +input logic clk, rst, +input logic [31:0] a, +input logic [31:0] b, +input logic valid_i, +input logic issigned, +output logic [31:0] hi, +output logic [31:0] lo, +output logic valid_o +); + +wire valid_t, signed_t, issigned_o; +wire [63:0] signed_o, unsigned_o; +ffenr #(2) stage1( + .clk(clk), + .rst(rst), + .d({valid_i, issigned}), + .en(1'b1), + .q({valid_t, signed_t}) +); +ffenr #(2) stage2( + .clk(clk), + .rst(rst), + .d({valid_t, signed_t}), + .en(1'b1), + .q({valid_o, issigned_o}) +); +mul_signed mul_signed( + .CLK(clk), + .A(a), + .B(b), + .P(signed_o) +); +mul_unsigned mul_unsigned( + .CLK(clk), + .A(a), + .B(b), + .P(unsigned_o) +); +assign hi = issigned_o ? signed_o[63:32] : unsigned_o[63:32]; +assign lo = issigned_o ? signed_o[31:0] : unsigned_o[31:0]; + +endmodule diff --git a/src/IP/mul_signed/mul_signed.xci b/src/IP/mul_signed/mul_signed.xci new file mode 100644 index 0000000..a202660 --- /dev/null +++ b/src/IP/mul_signed/mul_signed.xci @@ -0,0 +1,96 @@ + + + xilinx.com + xci + unknown + 1.0 + + + mul_signed + + + undef + undef + + 10000000 + 0 + 0.000 + undef + 0 + 0 + 32 + 0 + 10000001 + 32 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 1 + 1 + 63 + 0 + 0 + 0 + 0 + artix7 + Distributed_Memory + false + mul_signed + 129 + 0 + Parallel_Multiplier + Use_Mults + Speed + 63 + 0 + 2 + Signed + 32 + Signed + 32 + 0 + SCLR_Overrides_CE + false + false + false + false + artix7 + + + xc7a200t + fbg676 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 16 + TRUE + . + + . + 2019.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + diff --git a/src/IP/mul_unsigned/mul_unsigned.xci b/src/IP/mul_unsigned/mul_unsigned.xci new file mode 100644 index 0000000..309d013 --- /dev/null +++ b/src/IP/mul_unsigned/mul_unsigned.xci @@ -0,0 +1,98 @@ + + + xilinx.com + xci + unknown + 1.0 + + + mul_unsigned + + + undef + undef + + 10000000 + 0 + 0.000 + undef + 0 + 1 + 32 + 1 + 10000001 + 32 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 1 + 1 + 63 + 0 + 0 + 0 + 0 + artix7 + Distributed_Memory + false + mul_unsigned + 129 + 0 + Parallel_Multiplier + Use_Mults + Speed + 63 + 0 + 2 + Unsigned + 32 + Unsigned + 32 + 0 + SCLR_Overrides_CE + false + false + false + false + artix7 + + + xc7a200t + fbg676 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 16 + TRUE + . + + . + 2019.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + +