diff --git a/src/AXI/AXI.sv b/src/AXI/AXI.sv
index c888023..cae3071 100644
--- a/src/AXI/AXI.sv
+++ b/src/AXI/AXI.sv
@@ -18,7 +18,7 @@ module AXI (
SRAM_RO_AXI_i.slave rdata,
// DCache Write
- SRAM_W_AXI_i.slave wdata
+ SRAM_W_AXI_i.master wdata
);
// ==============================
@@ -63,7 +63,7 @@ module AXI (
// 据情况修改的东西
AXIRead.AXIReadAddr.arid = 4'b0; // ICache(0) DCache(1)
- AXIRead.AXIReadAddr.arport = 3'b101; // ICache(101) DCache(001)
+ AXIRead.AXIReadAddr.arprot = 3'b101; // ICache(101) DCache(001)
AXIRead.AXIReadAddr.araddr = 32'b0;
AXIRead.AXIReadAddr.rready = 1'b1;
@@ -71,14 +71,14 @@ module AXI (
if (AXIRead.AXIReadData.arready) begin
if (rdata.req) begin
AXIRead.AXIReadAddr.arid = 4'b0001;
- AXIRead.AXIReadAddr.arport = 3'b001;
+ AXIRead.AXIReadAddr.arprot = 3'b001;
AXIRead.AXIReadAddr.araddr = rdata.addr;
AXIRead.AXIReadAddr.arlen = {2'b0, rdata.size};
rdata.addr_ok = 1'b1;
inst.addr_ok = 1'b0;
end else if (inst.req) begin
AXIRead.AXIReadAddr.arid = 4'b0000;
- AXIRead.AXIReadAddr.arport = 3'b101;
+ AXIRead.AXIReadAddr.arprot = 3'b101;
AXIRead.AXIReadAddr.araddr = inst.addr;
AXIRead.AXIReadAddr.arlen = {2'b0, inst.size};
inst.addr_ok = 1'b1;
@@ -126,7 +126,7 @@ module AXI (
AXIWrite.AXIWriteAddr.awburst = 2'b01; // Incr
AXIWrite.AXIWriteAddr.awid = 4'b1; // ICache(0) DCache(1)
- AXIWrite.AXIWriteAddr.awport = 3'b001; // ICache(101) DCache(001)
+ AXIWrite.AXIWriteAddr.awprot = 3'b001; // ICache(101) DCache(001)
AXIWrite.AXIWriteAddr.awaddr = 32'b0;
AXIWrite.AXIWriteAddr.awvalid = 1'b0;
AXIWrite.AXIWriteAddr.bready = 1'b1;
diff --git a/src/Cache/DCache.sv b/src/Cache/DCache.sv
index 2740487..8a1a4e1 100644
--- a/src/Cache/DCache.sv
+++ b/src/Cache/DCache.sv
@@ -53,7 +53,6 @@ module DCache (
logic [5:0] baddr;
logic bwe1, bwe2; // bwe1: Lookup -> Write, bwe2: Replace -> Lookup
- word_t wdata;
DCData_t wdata1[4], wdata2[4];
// ===========================
@@ -159,6 +158,7 @@ module DCache (
| (hitWay[3] ? dataOut[3] : `DC_DATA_LENGTH'b0);
assign port.hit = hit;
+ assign port.row = cacheLine;
assign nowLRU = LRU[index];
@@ -180,10 +180,10 @@ module DCache (
nowLRU[2] == 0 ? 2'b10 :
nowLRU[3] == 0 ? 2'b11 :
2'b11;
- assign wen[0] = (victim == 0);
- assign wen[1] = (victim == 1);
- assign wen[2] = (victim == 2);
- assign wen[3] = (victim == 3);
+ assign wen[0] = hit ? hitWay[0] : (victim == 0);
+ assign wen[1] = hit ? hitWay[1] : (victim == 1);
+ assign wen[2] = hit ? hitWay[2] : (victim == 2);
+ assign wen[3] = hit ? hitWay[3] : (victim == 3);
assign port.dirt_valid = (state == LOOKUP) & tagV[victim] & tagOut[victim].dirty;
assign port.dirt_addr = {tagOut[victim].tag, index, 4'b0};
@@ -192,34 +192,6 @@ module DCache (
// Update LRU
always_comb begin
nextLRU = nowLRU;
-
- // Hit
-
- if (hitWay[0]) begin
- casez (nowLRU)
- 4'b111?: nextLRU = 4'b0001;
- default: nextLRU[0] = 1'b1;
- endcase
- end else if (hitWay[1]) begin
- casez (nowLRU)
- 4'b11?1: nextLRU = 4'b0010;
- default: nextLRU[1] = 1'b1;
- endcase
- end else if (hitWay[2]) begin
- casez (nowLRU)
- 4'b1?11: nextLRU = 4'b0100;
- default: nextLRU[2] = 1'b1;
- endcase
- end else if (hitWay[3]) begin
- casez (nowLRU)
- 4'b?111: nextLRU = 4'b1000;
- default: nextLRU[3] = 1'b1;
- endcase
- end
-
- // Not Hit
-
- else
if (wen[0]) begin
casez (nowLRU)
4'b111?: nextLRU = 4'b0001;
@@ -270,10 +242,10 @@ module DCache (
assign DataRAM2.addr = baddr;
assign DataRAM3.addr = baddr;
// 写使能
- assign TagRAM0.wen = (bwe1 & wen[0]) | (bwe2 & replaceWen[0]);
- assign TagRAM1.wen = (bwe1 & wen[1]) | (bwe2 & replaceWen[1]);
- assign TagRAM2.wen = (bwe1 & wen[2]) | (bwe2 & replaceWen[2]);
- assign TagRAM3.wen = (bwe1 & wen[3]) | (bwe2 & replaceWen[3]);
+ assign TagRAM0.wen = (bwe1 & wen[0]) | (bwe2 & replaceWen[0]);
+ assign TagRAM1.wen = (bwe1 & wen[1]) | (bwe2 & replaceWen[1]);
+ assign TagRAM2.wen = (bwe1 & wen[2]) | (bwe2 & replaceWen[2]);
+ assign TagRAM3.wen = (bwe1 & wen[3]) | (bwe2 & replaceWen[3]);
assign DataRAM0.wen = (bwe1 & wen[0]) | (bwe2 & replaceWen[0]);
assign DataRAM1.wen = (bwe1 & wen[1]) | (bwe2 & replaceWen[1]);
assign DataRAM2.wen = (bwe1 & wen[2]) | (bwe2 & replaceWen[2]);
@@ -681,28 +653,28 @@ module DCache (
endcase
end
- cache_tag_bram tag_ram0 (
+ cache_tagd_bram tag_ram0 (
.addra(TagRAM0.addr),
.clka (clk),
.dina (TagRAM0.wdata),
.douta(TagRAM0.rdata),
.wea (TagRAM0.wen)
);
- cache_tag_bram tag_ram1 (
+ cache_tagd_bram tag_ram1 (
.addra(TagRAM1.addr),
.clka (clk),
.dina (TagRAM1.wdata),
.douta(TagRAM1.rdata),
.wea (TagRAM1.wen)
);
- cache_tag_bram tag_ram2 (
+ cache_tagd_bram tag_ram2 (
.addra(TagRAM2.addr),
.clka (clk),
.dina (TagRAM2.wdata),
.douta(TagRAM2.rdata),
.wea (TagRAM2.wen)
);
- cache_tag_bram tag_ram3 (
+ cache_tagd_bram tag_ram3 (
.addra(TagRAM3.addr),
.clka (clk),
.dina (TagRAM3.wdata),
diff --git a/src/IP/.gitignore b/src/IP/.gitignore
new file mode 100644
index 0000000..2823b7a
--- /dev/null
+++ b/src/IP/.gitignore
@@ -0,0 +1,4 @@
+*
+!*/
+!.gitignore
+!*.xci
diff --git a/src/IP/cache_data_bram/cache_data_bram.xci b/src/IP/cache_data_bram/cache_data_bram.xci
index 6c5e2bc..d94bb28 100644
--- a/src/IP/cache_data_bram/cache_data_bram.xci
+++ b/src/IP/cache_data_bram/cache_data_bram.xci
@@ -151,7 +151,7 @@
0
0
0
- 0
+ 1
0
0
0
@@ -187,7 +187,7 @@
Always_Enabled
Always_Enabled
Single_Bit_Error_Injection
- false
+ true
Native
false
no_mem_loaded
@@ -296,6 +296,7 @@
+
diff --git a/src/IP/cache_tag_bram/cache_tag_bram.xci b/src/IP/cache_tag_bram/cache_tag_bram.xci
index 463b0cb..d76262f 100644
--- a/src/IP/cache_tag_bram/cache_tag_bram.xci
+++ b/src/IP/cache_tag_bram/cache_tag_bram.xci
@@ -151,7 +151,7 @@
0
0
0
- 0
+ 1
0
0
0
@@ -187,7 +187,7 @@
Always_Enabled
Always_Enabled
Single_Bit_Error_Injection
- false
+ true
Native
false
no_mem_loaded
@@ -296,6 +296,7 @@
+
diff --git a/src/IP/cache_tagd_bram/cache_tagd_bram.xci b/src/IP/cache_tagd_bram/cache_tagd_bram.xci
new file mode 100644
index 0000000..55b94ba
--- /dev/null
+++ b/src/IP/cache_tagd_bram/cache_tagd_bram.xci
@@ -0,0 +1,311 @@
+
+
+ xilinx.com
+ xci
+ unknown
+ 1.0
+
+
+ cache_tagd_bram
+
+
+ 4096
+ 1
+ 0
+ 0
+ 0
+
+ 1
+ 100000000
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0.000
+ AXI4LITE
+ READ_WRITE
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+
+ 1
+ 100000000
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0.000
+ AXI4LITE
+ READ_WRITE
+ 0
+ 0
+ 0
+ 0
+ 0
+ OTHER
+ NONE
+ 8192
+ 32
+ 1
+
+ OTHER
+ NONE
+ 8192
+ 32
+ 1
+
+
+ 100000000
+ 0
+ 0.000
+ 0
+ 6
+ 6
+ 1
+ 4
+ 0
+ 1
+ 9
+ 0
+ 1
+ 0
+ NONE
+ 0
+ 0
+ 0
+ ./
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ Estimated Power for IP : 3.20565 mW
+ artix7
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ cache_tagd_bram.mem
+ no_coe_file_loaded
+ 0
+ 0
+ 0
+ 0
+ 1
+ 64
+ 64
+ 1
+ 1
+ 24
+ 24
+ 0
+ 0
+ CE
+ CE
+ ALL
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 1
+ 1
+ 64
+ 64
+ WRITE_FIRST
+ WRITE_FIRST
+ 24
+ 24
+ artix7
+ 4
+ Memory_Slave
+ AXI4_Full
+ false
+ Minimum_Area
+ false
+ 9
+ NONE
+ no_coe_file_loaded
+ ALL
+ cache_tagd_bram
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ Always_Enabled
+ Always_Enabled
+ Single_Bit_Error_Injection
+ true
+ Native
+ false
+ no_mem_loaded
+ Single_Port_RAM
+ WRITE_FIRST
+ WRITE_FIRST
+ 0
+ 0
+ BRAM
+ 0
+ 100
+ 100
+ 50
+ 0
+ 0
+ 0
+ 8kx2
+ false
+ false
+ 1
+ 1
+ 24
+ 24
+ false
+ false
+ false
+ false
+ 0
+ false
+ false
+ CE
+ CE
+ SYNC
+ false
+ false
+ false
+ false
+ false
+ false
+ false
+ 64
+ 24
+ 24
+ No_ECC
+ false
+ false
+ false
+ Stand_Alone
+ artix7
+
+
+ xc7a200t
+ fbg676
+ VERILOG
+
+ MIXED
+ -2
+
+
+ TRUE
+ TRUE
+ IP_Flow
+ 4
+ TRUE
+ .
+
+ .
+ 2019.2
+ OUT_OF_CONTEXT
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/src/IP/mul_signed/mul_signed.xci b/src/IP/mul_signed/mul_signed.xci
deleted file mode 100644
index a202660..0000000
--- a/src/IP/mul_signed/mul_signed.xci
+++ /dev/null
@@ -1,96 +0,0 @@
-
-
- xilinx.com
- xci
- unknown
- 1.0
-
-
- mul_signed
-
-
- undef
- undef
-
- 10000000
- 0
- 0.000
- undef
- 0
- 0
- 32
- 0
- 10000001
- 32
- 0
- 0
- 0
- 0
- 0
- 2
- 0
- 1
- 1
- 63
- 0
- 0
- 0
- 0
- artix7
- Distributed_Memory
- false
- mul_signed
- 129
- 0
- Parallel_Multiplier
- Use_Mults
- Speed
- 63
- 0
- 2
- Signed
- 32
- Signed
- 32
- 0
- SCLR_Overrides_CE
- false
- false
- false
- false
- artix7
-
-
- xc7a200t
- fbg676
- VERILOG
-
- MIXED
- -1
-
-
- TRUE
- TRUE
- IP_Flow
- 16
- TRUE
- .
-
- .
- 2019.2
- OUT_OF_CONTEXT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/src/IP/mul_unsigned/mul_unsigned.xci b/src/IP/mul_unsigned/mul_unsigned.xci
deleted file mode 100644
index 309d013..0000000
--- a/src/IP/mul_unsigned/mul_unsigned.xci
+++ /dev/null
@@ -1,98 +0,0 @@
-
-
- xilinx.com
- xci
- unknown
- 1.0
-
-
- mul_unsigned
-
-
- undef
- undef
-
- 10000000
- 0
- 0.000
- undef
- 0
- 1
- 32
- 1
- 10000001
- 32
- 0
- 0
- 0
- 0
- 0
- 2
- 0
- 1
- 1
- 63
- 0
- 0
- 0
- 0
- artix7
- Distributed_Memory
- false
- mul_unsigned
- 129
- 0
- Parallel_Multiplier
- Use_Mults
- Speed
- 63
- 0
- 2
- Unsigned
- 32
- Unsigned
- 32
- 0
- SCLR_Overrides_CE
- false
- false
- false
- false
- artix7
-
-
- xc7a200t
- fbg676
- VERILOG
-
- MIXED
- -1
-
-
- TRUE
- TRUE
- IP_Flow
- 16
- TRUE
- .
-
- .
- 2019.2
- OUT_OF_CONTEXT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/src/MMU/MMU.sv b/src/MMU/MMU.sv
index ce6fbda..cce9b85 100644
--- a/src/MMU/MMU.sv
+++ b/src/MMU/MMU.sv
@@ -186,6 +186,10 @@ module MMU (
word_t drD1, drD2, drD3;
logic wdata_ok;
+ word_t ddAddr1;
+ logic [127:0] ddData1;
+ logic ddValid1;
+
// ============================
// ======== dFlip-Flop ========
// ============================
@@ -209,26 +213,23 @@ module MMU (
dEn,
dPA1
);
- ffenr #(1) dwr_ff (
+ ffen #(1) dwr_ff (
clk,
- rst,
data.wr,
dEn,
- dwr1,
+ dwr1
);
- ffenr #(1) dwstrb_ff (
+ ffen #(4) dwstrb_ff (
clk,
- rst,
data.wstrb,
dEn,
- dWstrb1,
+ dWstrb1
);
- ffenr #(1) dwdata_ff (
+ ffen #(32) dwdata_ff (
clk,
- rst,
data.wdata,
dEn,
- dWdata1,
+ dWdata1
);
// ================================
@@ -262,8 +263,7 @@ module MMU (
dEn = 0;
drNextState = drState;
data.data_ok = 0;
- dc.rvalid = 0;
- data.req = 0;
+ rdata_axi.req = 0;
case (drState)
DR_IDLE: begin
if (~dValid1) dEn = 1;
@@ -348,7 +348,9 @@ module MMU (
// ================================
assign data.addr_ok = dEn;
- assign data.rdata = rdata_axi.rdata;
+ assign data.rdata = rdata_axi.rvalid ? rdata_axi.rdata
+ : dPA1[3] ? dPA1[2] ? dc.row[127:96] : dc.row[95:64]
+ : dPA1[2] ? dc.row[ 63:32] : dc.row[31: 0];
assign dc.valid = data.req & dEn & dCached;
assign dc.addr = dPA;
@@ -388,15 +390,17 @@ module MMU (
end
always_comb begin
- dwEn = 0;
- dwNextState = dwState;
+ dwNextState = dwState;
wdata_axi.req = 0;
+ wdata_axi.addr = 0;
wdata_axi.wdata = 0;
wdata_axi.wstrb = 0;
wdata_axi.wvalid = 0;
wdata_axi.wlast = 0;
+ wdata_ok = 0;
+
case (dwState)
DW_IDLE: begin
if (~dCached1 & dwr1 | dCached1 & dc.dirt_valid) begin
@@ -460,7 +464,7 @@ module MMU (
// TODO: goto IDLE on failure
wdata_ok = 1'b1;
if (drState == DR_REFILL) dwNextState = DW_IDLE;
- else dwNextState = DW_REFILL;
+ else dwNextState = DW_WAITR;
end
end
DW_WAITR: begin
@@ -470,6 +474,11 @@ module MMU (
endcase
end
+ // typedef enum [2:0] {
+ // DWA_WA
+ // } dwastate_t;
+
+
// =============================
// ======== dwFlip-Flop ========
// =============================
@@ -480,7 +489,7 @@ module MMU (
dc.dirt_valid,
ddAddr1
);
- ffen #(128) ddvalid_ff (
+ ffen #(128) dddata_ff (
clk,
dc.dirt_data,
dc.dirt_valid,
@@ -498,6 +507,9 @@ module MMU (
// ================================
assign wdata_axi.size = dCached1 ? 2'b11 : 2'b00;
+ assign dc.wvalid = dValid1 & dwr1 & (drState != DR_REFILL);
+ assign dc.wdata = dWdata1;
+ assign dc.wstrb = dWstrb1;
// ==============================
// ========== VA -> PA ==========
diff --git a/src/include/AXI.svh b/src/include/AXI.svh
index 8f8f23f..70877f6 100644
--- a/src/include/AXI.svh
+++ b/src/include/AXI.svh
@@ -9,7 +9,7 @@ typedef struct packed {
logic [1:0] arburst; // Burst type
logic [1:0] arlock; // Lock type
logic [3:0] arcache; // Cache type
- logic [2:0] arport; // Protection type
+ logic [2:0] arprot; // Protection type
logic arvalid; // Read address valid
logic rready; // Read ready
@@ -41,7 +41,7 @@ typedef struct packed {
logic [1:0] awburst; // Burst type
logic [1:0] awlock; // Lock type
logic [3:0] awcache; // Cache type
- logic [2:0] awport; // Protection type
+ logic [2:0] awprot; // Protection type
logic awvalid; // Write address valid
logic [3:0] wid; // Write ID tag
diff --git a/src/include/DCache.svh b/src/include/DCache.svh
index 7a7ca0c..6dc6295 100644
--- a/src/include/DCache.svh
+++ b/src/include/DCache.svh
@@ -40,16 +40,17 @@ interface DCache_i;
word_t wdata;
logic [3:0] wstrb;
logic dirt_valid;
- word dirt_addr;
+ word_t dirt_addr;
DCData_t dirt_data;
+ logic [127:0] row;
modport cache(
input valid, addr, rvalid, rdata, wvalid, wdata, wstrb,
- output hit, dirt_valid, dirt_addr, dirt_data
+ output hit, dirt_valid, dirt_addr, dirt_data, row
);
modport mmu(
output valid, addr, rvalid, rdata, wvalid, wdata, wstrb,
- input hit, dirt_valid, dirt_addr, dirt_data
+ input hit, dirt_valid, dirt_addr, dirt_data, row
);
endinterface //DCache_i
diff --git a/src/testbench/MMU/axi_wrap.v b/src/testbench/MMU/axi_wrap.v
new file mode 100644
index 0000000..e6c7d53
--- /dev/null
+++ b/src/testbench/MMU/axi_wrap.v
@@ -0,0 +1,166 @@
+/*------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+Copyright (c) 2016, Loongson Technology Corporation Limited.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice,
+this list of conditions and the following disclaimer in the documentation and/or
+other materials provided with the distribution.
+
+3. Neither the name of Loongson Technology Corporation Limited nor the names of
+its contributors may be used to endorse or promote products derived from this
+software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
+TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--------------------------------------------------------------------------------
+------------------------------------------------------------------------------*/
+
+module axi_wrap(
+ input m_aclk,
+ input m_aresetn,
+ //ar
+ input [3 :0] m_arid ,
+ input [31:0] m_araddr ,
+ input [3 :0] m_arlen ,
+ input [2 :0] m_arsize ,
+ input [1 :0] m_arburst,
+ input [1 :0] m_arlock ,
+ input [3 :0] m_arcache,
+ input [2 :0] m_arprot ,
+ input m_arvalid,
+ output m_arready,
+ //r
+ output [3 :0] m_rid ,
+ output [31:0] m_rdata ,
+ output [1 :0] m_rresp ,
+ output m_rlast ,
+ output m_rvalid ,
+ input m_rready ,
+ //aw
+ input [3 :0] m_awid ,
+ input [31:0] m_awaddr ,
+ input [3 :0] m_awlen ,
+ input [2 :0] m_awsize ,
+ input [1 :0] m_awburst,
+ input [1 :0] m_awlock ,
+ input [3 :0] m_awcache,
+ input [2 :0] m_awprot ,
+ input m_awvalid,
+ output m_awready,
+ //w
+ input [3 :0] m_wid ,
+ input [31:0] m_wdata ,
+ input [3 :0] m_wstrb ,
+ input m_wlast ,
+ input m_wvalid ,
+ output m_wready ,
+ //b
+ output [3 :0] m_bid ,
+ output [1 :0] m_bresp ,
+ output m_bvalid ,
+ input m_bready ,
+
+ output s_aclk,
+ output s_aresetn,
+ //ar
+ output [3 :0] s_arid ,
+ output [31:0] s_araddr ,
+ output [3 :0] s_arlen ,
+ output [2 :0] s_arsize ,
+ output [1 :0] s_arburst,
+ output [1 :0] s_arlock ,
+ output [3 :0] s_arcache,
+ output [2 :0] s_arprot ,
+ output s_arvalid,
+ input s_arready,
+ //r
+ input [3 :0] s_rid ,
+ input [31:0] s_rdata ,
+ input [1 :0] s_rresp ,
+ input s_rlast ,
+ input s_rvalid ,
+ output s_rready ,
+ //aw
+ output [3 :0] s_awid ,
+ output [31:0] s_awaddr ,
+ output [3 :0] s_awlen ,
+ output [2 :0] s_awsize ,
+ output [1 :0] s_awburst,
+ output [1 :0] s_awlock ,
+ output [3 :0] s_awcache,
+ output [2 :0] s_awprot ,
+ output s_awvalid,
+ input s_awready,
+ //w
+ output [3 :0] s_wid ,
+ output [31:0] s_wdata ,
+ output [3 :0] s_wstrb ,
+ output s_wlast ,
+ output s_wvalid ,
+ input s_wready ,
+ //b
+ input [3 :0] s_bid ,
+ input [1 :0] s_bresp ,
+ input s_bvalid ,
+ output s_bready
+);
+assign s_aclk = m_aclk ;
+assign s_aresetn = m_aresetn;
+//ar
+assign s_arid = m_arid ;
+assign s_araddr = m_araddr ;
+assign s_arlen = m_arlen ;
+assign s_arsize = m_arsize ;
+assign s_arburst = m_arburst;
+assign s_arlock = m_arlock ;
+assign s_arcache = m_arcache;
+assign s_arprot = m_arprot ;
+assign s_arvalid = m_arvalid;
+assign m_arready = s_arready;
+//r
+assign m_rid = m_rvalid ? s_rid : 4'd0 ;
+assign m_rdata = m_rvalid ? s_rdata : 32'd0 ;
+assign m_rresp = m_rvalid ? s_rresp : 2'd0 ;
+assign m_rlast = m_rvalid ? s_rlast : 1'd0 ;
+assign m_rvalid = s_rvalid;
+assign s_rready = m_rready;
+//aw
+assign s_awid = m_awid ;
+assign s_awaddr = m_awaddr ;
+assign s_awlen = m_awlen ;
+assign s_awsize = m_awsize ;
+assign s_awburst = m_awburst;
+assign s_awlock = m_awlock ;
+assign s_awcache = m_awcache;
+assign s_awprot = m_awprot ;
+assign s_awvalid = m_awvalid;
+assign m_awready = s_awready;
+//w
+assign s_wid = m_wid ;
+assign s_wdata = m_wdata ;
+assign s_wstrb = m_wstrb ;
+assign s_wlast = m_wlast ;
+assign s_wvalid = m_wvalid ;
+assign m_wready = s_wready ;
+//b
+assign m_bid = m_bvalid ? s_bid : 4'd0 ;
+assign m_bresp = m_bvalid ? s_bresp : 2'd0 ;
+assign m_bvalid = s_bvalid ;
+assign s_bready = m_bready ;
+endmodule
diff --git a/src/testbench/MMU/axi_wrap_ram.v b/src/testbench/MMU/axi_wrap_ram.v
new file mode 100644
index 0000000..7639a60
--- /dev/null
+++ b/src/testbench/MMU/axi_wrap_ram.v
@@ -0,0 +1,293 @@
+/*------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+Copyright (c) 2016, Loongson Technology Corporation Limited.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice,
+this list of conditions and the following disclaimer in the documentation and/or
+other materials provided with the distribution.
+
+3. Neither the name of Loongson Technology Corporation Limited nor the names of
+its contributors may be used to endorse or promote products derived from this
+software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
+TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--------------------------------------------------------------------------------
+------------------------------------------------------------------------------*/
+//for func test, no define RUN_PERF_TEST
+`define _RUN_PERF_TEST
+`define _RUN_PERF_NO_DELAY
+
+module axi_wrap_ram(
+ input aclk,
+ input aresetn,
+ //ar
+ input [3 :0] axi_arid ,
+ input [31:0] axi_araddr ,
+ input [7 :0] axi_arlen ,
+ input [2 :0] axi_arsize ,
+ input [1 :0] axi_arburst,
+ input [1 :0] axi_arlock ,
+ input [3 :0] axi_arcache,
+ input [2 :0] axi_arprot ,
+ input axi_arvalid,
+ output axi_arready,
+ //r
+ output [3 :0] axi_rid ,
+ output [31:0] axi_rdata ,
+ output [1 :0] axi_rresp ,
+ output axi_rlast ,
+ output axi_rvalid ,
+ input axi_rready ,
+ //aw
+ input [3 :0] axi_awid ,
+ input [31:0] axi_awaddr ,
+ input [7 :0] axi_awlen ,
+ input [2 :0] axi_awsize ,
+ input [1 :0] axi_awburst,
+ input [1 :0] axi_awlock ,
+ input [3 :0] axi_awcache,
+ input [2 :0] axi_awprot ,
+ input axi_awvalid,
+ output axi_awready,
+ //w
+ input [3 :0] axi_wid ,
+ input [31:0] axi_wdata ,
+ input [3 :0] axi_wstrb ,
+ input axi_wlast ,
+ input axi_wvalid ,
+ output axi_wready ,
+ //b
+ output [3 :0] axi_bid ,
+ output [1 :0] axi_bresp ,
+ output axi_bvalid ,
+ input axi_bready ,
+
+ //from confreg
+ input [4 :0] ram_random_mask
+);
+wire axi_arvalid_m_masked;
+wire axi_rready_m_masked;
+wire axi_awvalid_m_masked;
+wire axi_wvalid_m_masked;
+wire axi_bready_m_masked;
+
+wire axi_arready_s_unmasked;
+wire axi_rvalid_s_unmasked;
+wire axi_awready_s_unmasked;
+wire axi_wready_s_unmasked;
+wire axi_bvalid_s_unmasked;
+
+wire ar_and;
+wire r_and;
+wire aw_and;
+wire w_and;
+wire b_and;
+reg ar_nomask;
+reg aw_nomask;
+reg w_nomask;
+reg [4:0] pf_r2r;
+reg [1:0] pf_b2b;
+wire pf_r2r_nomask= pf_r2r==5'd0;
+wire pf_b2b_nomask= pf_b2b==2'd0;
+
+//mask
+`ifdef RUN_PERF_TEST
+ assign ar_and = 1'b1;
+ assign aw_and = 1'b1;
+ assign w_and = 1'b1;
+ `ifdef RUN_PERF_NO_DELAY
+ assign r_and = 1'b1;
+ assign b_and = 1'b1;
+ `else
+ assign r_and = pf_r2r_nomask;
+ assign b_and = pf_b2b_nomask;
+ `endif
+`else
+ assign ar_and = ram_random_mask[4] | ar_nomask;
+ assign r_and = ram_random_mask[3] ;
+ assign aw_and = ram_random_mask[2] | aw_nomask;
+ assign w_and = ram_random_mask[1] | w_nomask;
+ assign b_and = ram_random_mask[0] ;
+`endif
+always @(posedge aclk)
+begin
+ //for func test, random mask
+ ar_nomask <= !aresetn ? 1'b0 :
+ axi_arvalid_m_masked&&axi_arready ? 1'b0 :
+ axi_arvalid_m_masked ? 1'b1 : ar_nomask;
+
+ aw_nomask <= !aresetn ? 1'b0 :
+ axi_awvalid_m_masked&&axi_awready ? 1'b0 :
+ axi_awvalid_m_masked ? 1'b1 : aw_nomask;
+
+ w_nomask <= !aresetn ? 1'b0 :
+ axi_wvalid_m_masked&&axi_wready ? 1'b0 :
+ axi_wvalid_m_masked ? 1'b1 : w_nomask;
+ //for perf test
+ pf_r2r <= !aresetn ? 5'd0 :
+ axi_arvalid_m_masked&&axi_arready ? 5'd25 :
+ !pf_r2r_nomask ? pf_r2r-1'b1 : pf_r2r;
+ pf_b2b <= !aresetn ? 2'd0 :
+ axi_awvalid_m_masked&&axi_awready ? 2'd3 :
+ !pf_b2b_nomask ? pf_b2b-1'b1 : pf_b2b;
+end
+
+
+//-----{master -> slave}-----
+assign axi_arvalid_m_masked = axi_arvalid & ar_and;
+assign axi_rready_m_masked = axi_rready & r_and;
+assign axi_awvalid_m_masked = axi_awvalid & aw_and;
+assign axi_wvalid_m_masked = axi_wvalid & w_and;
+assign axi_bready_m_masked = axi_bready & b_and;
+
+//-----{slave -> master}-----
+assign axi_arready = axi_arready_s_unmasked & ar_and;
+assign axi_rvalid = axi_rvalid_s_unmasked & r_and;
+assign axi_awready = axi_awready_s_unmasked & aw_and;
+assign axi_wready = axi_wready_s_unmasked & w_and;
+assign axi_bvalid = axi_bvalid_s_unmasked & b_and;
+
+//ram axi
+//ar
+wire [3 :0] ram_arid ;
+wire [31:0] ram_araddr ;
+wire [7 :0] ram_arlen ;
+wire [2 :0] ram_arsize ;
+wire [1 :0] ram_arburst;
+wire [1 :0] ram_arlock ;
+wire [3 :0] ram_arcache;
+wire [2 :0] ram_arprot ;
+wire ram_arvalid;
+wire ram_arready;
+//r
+wire [3 :0] ram_rid ;
+wire [31:0] ram_rdata ;
+wire [1 :0] ram_rresp ;
+wire ram_rlast ;
+wire ram_rvalid ;
+wire ram_rready ;
+//aw
+wire [3 :0] ram_awid ;
+wire [31:0] ram_awaddr ;
+wire [7 :0] ram_awlen ;
+wire [2 :0] ram_awsize ;
+wire [1 :0] ram_awburst;
+wire [1 :0] ram_awlock ;
+wire [3 :0] ram_awcache;
+wire [2 :0] ram_awprot ;
+wire ram_awvalid;
+wire ram_awready;
+//w
+wire [3 :0] ram_wid ;
+wire [31:0] ram_wdata ;
+wire [3 :0] ram_wstrb ;
+wire ram_wlast ;
+wire ram_wvalid ;
+wire ram_wready ;
+//b
+wire [3 :0] ram_bid ;
+wire [1 :0] ram_bresp ;
+wire ram_bvalid ;
+wire ram_bready ;
+
+
+// inst ram axi
+axi_ram ram(
+ .s_aclk (aclk ),
+ .s_aresetn (aresetn ),
+
+ //ar
+ .s_axi_arid (ram_arid ),
+ .s_axi_araddr (ram_araddr ),
+ .s_axi_arlen (ram_arlen ),
+ .s_axi_arsize (ram_arsize ),
+ .s_axi_arburst (ram_arburst ),
+ .s_axi_arvalid (ram_arvalid ),
+ .s_axi_arready (ram_arready ),
+ //r
+ .s_axi_rid (ram_rid ),
+ .s_axi_rdata (ram_rdata ),
+ .s_axi_rresp (ram_rresp ),
+ .s_axi_rlast (ram_rlast ),
+ .s_axi_rvalid (ram_rvalid ),
+ .s_axi_rready (ram_rready ),
+ //aw
+ .s_axi_awid (ram_awid ),
+ .s_axi_awaddr (ram_awaddr ),
+ .s_axi_awlen (ram_awlen ),
+ .s_axi_awsize (ram_awsize ),
+ .s_axi_awburst (ram_awburst ),
+ .s_axi_awvalid (ram_awvalid ),
+ .s_axi_awready (ram_awready ),
+ //w
+ .s_axi_wdata (ram_wdata ),
+ .s_axi_wstrb (ram_wstrb ),
+ .s_axi_wlast (ram_wlast ),
+ .s_axi_wvalid (ram_wvalid ),
+ .s_axi_wready (ram_wready ),
+ //b
+ .s_axi_bid (ram_bid ),
+ .s_axi_bresp (ram_bresp ),
+ .s_axi_bvalid (ram_bvalid ),
+ .s_axi_bready (ram_bready )
+);
+
+//ar
+assign ram_arid = axi_arid ;
+assign ram_araddr = axi_araddr ;
+assign ram_arlen = axi_arlen ;
+assign ram_arsize = axi_arsize ;
+assign ram_arburst = axi_arburst;
+assign ram_arlock = axi_arlock ;
+assign ram_arcache = axi_arcache;
+assign ram_arprot = axi_arprot ;
+assign ram_arvalid = axi_arvalid_m_masked;
+assign axi_arready_s_unmasked = ram_arready;
+//r
+assign axi_rid = axi_rvalid ? ram_rid : 4'd0 ;
+assign axi_rdata = axi_rvalid ? ram_rdata : 32'd0 ;
+assign axi_rresp = axi_rvalid ? ram_rresp : 2'd0 ;
+assign axi_rlast = axi_rvalid ? ram_rlast : 1'd0 ;
+assign axi_rvalid_s_unmasked = ram_rvalid;
+assign ram_rready = axi_rready_m_masked;
+//aw
+assign ram_awid = axi_awid ;
+assign ram_awaddr = axi_awaddr ;
+assign ram_awlen = axi_awlen ;
+assign ram_awsize = axi_awsize ;
+assign ram_awburst = axi_awburst;
+assign ram_awlock = axi_awlock ;
+assign ram_awcache = axi_awcache;
+assign ram_awprot = axi_awprot ;
+assign ram_awvalid = axi_awvalid_m_masked;
+assign axi_awready_s_unmasked = ram_awready;
+//w
+assign ram_wid = axi_wid ;
+assign ram_wdata = axi_wdata ;
+assign ram_wstrb = axi_wstrb ;
+assign ram_wlast = axi_wlast ;
+assign ram_wvalid = axi_wvalid_m_masked;
+assign axi_wready_s_unmasked = ram_wready ;
+//b
+assign axi_bid = axi_bvalid ? ram_bid : 4'd0 ;
+assign axi_bresp = axi_bvalid ? ram_bresp : 2'd0 ;
+assign axi_bvalid_s_unmasked = ram_bvalid ;
+assign ram_bready = axi_bready_m_masked;
+endmodule
diff --git a/src/testbench/MMU/confreg.v b/src/testbench/MMU/confreg.v
new file mode 100644
index 0000000..1581413
--- /dev/null
+++ b/src/testbench/MMU/confreg.v
@@ -0,0 +1,837 @@
+/*------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+Copyright (c) 2016, Loongson Technology Corporation Limited.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice,
+this list of conditions and the following disclaimer in the documentation and/or
+other materials provided with the distribution.
+
+3. Neither the name of Loongson Technology Corporation Limited nor the names of
+its contributors may be used to endorse or promote products derived from this
+software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
+TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--------------------------------------------------------------------------------
+------------------------------------------------------------------------------*/
+
+//*************************************************************************
+// > File Name : confreg.v
+// > Description : Control module of
+// 16 red leds, 2 green/red leds,
+// 7-segment display,
+// switchs,
+// key board,
+// bottom STEP,
+// timer.
+//
+// > Author : LOONGSON
+// > Date : 2017-08-04
+//*************************************************************************
+`define RANDOM_SEED {7'b1010101,16'h00FF}
+
+`define CR0_ADDR 16'h8000 //32'hbfaf_8000
+`define CR1_ADDR 16'h8004 //32'hbfaf_8004
+`define CR2_ADDR 16'h8008 //32'hbfaf_8008
+`define CR3_ADDR 16'h800c //32'hbfaf_800c
+`define CR4_ADDR 16'h8010 //32'hbfaf_8010
+`define CR5_ADDR 16'h8014 //32'hbfaf_8014
+`define CR6_ADDR 16'h8018 //32'hbfaf_8018
+`define CR7_ADDR 16'h801c //32'hbfaf_801c
+
+`define LED_ADDR 16'hf000 //32'hbfaf_f000
+`define LED_RG0_ADDR 16'hf004 //32'hbfaf_f004
+`define LED_RG1_ADDR 16'hf008 //32'hbfaf_f008
+`define NUM_ADDR 16'hf010 //32'hbfaf_f010
+`define SWITCH_ADDR 16'hf020 //32'hbfaf_f020
+`define BTN_KEY_ADDR 16'hf024 //32'hbfaf_f024
+`define BTN_STEP_ADDR 16'hf028 //32'hbfaf_f028
+`define SW_INTER_ADDR 16'hf02c //32'hbfaf_f02c
+`define TIMER_ADDR 16'he000 //32'hbfaf_e000
+
+`define IO_SIMU_ADDR 16'hffec //32'hbfaf_ffec
+`define VIRTUAL_UART_ADDR 16'hfff0 //32'hbfaf_fff0
+`define SIMU_FLAG_ADDR 16'hfff4 //32'hbfaf_fff4
+`define OPEN_TRACE_ADDR 16'hfff8 //32'hbfaf_fff8
+`define NUM_MONITOR_ADDR 16'hfffc //32'hbfaf_fffc
+module confreg
+#(parameter SIMULATION=1'b0)
+(
+ input aclk,
+ input timer_clk,
+ input aresetn,
+ // read and write from cpu
+ //ar
+ input [3 :0] arid ,
+ input [31:0] araddr ,
+ input [7 :0] arlen ,
+ input [2 :0] arsize ,
+ input [1 :0] arburst,
+ input [1 :0] arlock ,
+ input [3 :0] arcache,
+ input [2 :0] arprot ,
+ input arvalid,
+ output arready,
+ //r
+ output [3 :0] rid ,
+ output [31:0] rdata ,
+ output [1 :0] rresp ,
+ output rlast ,
+ output rvalid ,
+ input rready ,
+ //aw
+ input [3 :0] awid ,
+ input [31:0] awaddr ,
+ input [7 :0] awlen ,
+ input [2 :0] awsize ,
+ input [1 :0] awburst,
+ input [1 :0] awlock ,
+ input [3 :0] awcache,
+ input [2 :0] awprot ,
+ input awvalid,
+ output awready,
+ //w
+ input [3 :0] wid ,
+ input [31:0] wdata ,
+ input [3 :0] wstrb ,
+ input wlast ,
+ input wvalid ,
+ output wready ,
+ //b
+ output [3 :0] bid ,
+ output [1 :0] bresp ,
+ output bvalid ,
+ input bready ,
+
+ //for lab6
+ output [4 :0] ram_random_mask ,
+
+ // read and write to device on board
+ output [15:0] led,
+ output [1 :0] led_rg0,
+ output [1 :0] led_rg1,
+ output reg [7 :0] num_csn,
+ output reg [6 :0] num_a_g,
+ input [7 :0] switch,
+ output [3 :0] btn_key_col,
+ input [3 :0] btn_key_row,
+ input [1 :0] btn_step
+);
+ reg [31:0] cr0;
+ reg [31:0] cr1;
+ reg [31:0] cr2;
+ reg [31:0] cr3;
+ reg [31:0] cr4;
+ reg [31:0] cr5;
+ reg [31:0] cr6;
+ reg [31:0] cr7;
+
+ reg [31:0] led_data;
+ reg [31:0] led_rg0_data;
+ reg [31:0] led_rg1_data;
+ reg [31:0] num_data;
+ wire [31:0] switch_data;
+ wire [31:0] sw_inter_data; //switch interleave
+ wire [31:0] btn_key_data;
+ wire [31:0] btn_step_data;
+ reg [31:0] timer_r2;
+ reg [31:0] simu_flag;
+ reg [31:0] io_simu;
+ reg [7 :0] virtual_uart_data;
+ reg open_trace;
+ reg num_monitor;
+
+//--------------------------{axi interface}begin-------------------------//
+ reg busy,write,R_or_W;
+ reg s_wready;
+
+ wire ar_enter = arvalid & arready;
+ wire r_retire = rvalid & rready & rlast;
+ wire aw_enter = awvalid & awready;
+ wire w_enter = wvalid & wready & wlast;
+ wire b_retire = bvalid & bready;
+
+ assign arready = ~busy & (!R_or_W| !awvalid);
+ assign awready = ~busy & ( R_or_W| !arvalid);
+
+ reg [3 :0] buf_id;
+ reg [31:0] buf_addr;
+ reg [7 :0] buf_len;
+ reg [2 :0] buf_size;
+
+ always @(posedge aclk)
+ begin
+ if(~aresetn) busy <= 1'b0;
+ else if(ar_enter|aw_enter) busy <= 1'b1;
+ else if(r_retire|b_retire) busy <= 1'b0;
+ end
+
+ always @(posedge aclk)
+ begin
+ if(~aresetn)
+ begin
+ R_or_W <= 1'b0;
+ buf_id <= 4'b0;
+ buf_addr <= 32'b0;
+ buf_len <= 8'b0;
+ buf_size <= 3'b0;
+ end
+ else
+ if(ar_enter | aw_enter)
+ begin
+ R_or_W <= ar_enter;
+ buf_id <= ar_enter ? arid : awid ;
+ buf_addr <= ar_enter ? araddr : awaddr ;
+ buf_len <= ar_enter ? arlen : awlen ;
+ buf_size <= ar_enter ? arsize : awsize ;
+ end
+ end
+
+ reg conf_wready_reg;
+ assign wready = conf_wready_reg;
+ always@(posedge aclk)
+ begin
+ if (~aresetn ) conf_wready_reg <= 1'b0;
+ else if(aw_enter ) conf_wready_reg <= 1'b1;
+ else if(w_enter & wlast) conf_wready_reg <= 1'b0;
+ end
+
+ // read data has one cycle delay
+ reg [31:0] conf_rdata_reg;
+ reg conf_rvalid_reg;
+ reg conf_rlast_reg;
+ assign rdata = conf_rdata_reg;
+ assign rvalid = conf_rvalid_reg;
+ assign rlast = conf_rlast_reg;
+ always @(posedge aclk)
+ begin
+ if(~aresetn)
+ begin
+ conf_rdata_reg <= 32'd0;
+ conf_rvalid_reg <= 1'd0;
+ conf_rlast_reg <= 1'd0;
+ end
+ else if(busy & R_or_W & !r_retire)
+ begin
+ conf_rvalid_reg <= 1'd1;
+ conf_rlast_reg <= 1'd1;
+ case (buf_addr[15:0])
+ `CR0_ADDR : conf_rdata_reg <= cr0 ;
+ `CR1_ADDR : conf_rdata_reg <= cr1 ;
+ `CR2_ADDR : conf_rdata_reg <= cr2 ;
+ `CR3_ADDR : conf_rdata_reg <= cr3 ;
+ `CR4_ADDR : conf_rdata_reg <= cr4 ;
+ `CR5_ADDR : conf_rdata_reg <= cr5 ;
+ `CR6_ADDR : conf_rdata_reg <= cr6 ;
+ `CR7_ADDR : conf_rdata_reg <= cr7 ;
+ `LED_ADDR : conf_rdata_reg <= led_data ;
+ `LED_RG0_ADDR : conf_rdata_reg <= led_rg0_data ;
+ `LED_RG1_ADDR : conf_rdata_reg <= led_rg1_data ;
+ `NUM_ADDR : conf_rdata_reg <= num_data ;
+ `SWITCH_ADDR : conf_rdata_reg <= switch_data ;
+ `BTN_KEY_ADDR : conf_rdata_reg <= btn_key_data ;
+ `BTN_STEP_ADDR : conf_rdata_reg <= btn_step_data;
+ `SW_INTER_ADDR : conf_rdata_reg <= sw_inter_data;
+ `TIMER_ADDR : conf_rdata_reg <= timer_r2 ;
+ `SIMU_FLAG_ADDR: conf_rdata_reg <= simu_flag ;
+ `IO_SIMU_ADDR : conf_rdata_reg <= io_simu ;
+ `VIRTUAL_UART_ADDR : conf_rdata_reg <= {24'd0,virtual_uart_data} ;
+ `OPEN_TRACE_ADDR : conf_rdata_reg <= {31'd0,open_trace} ;
+ `NUM_MONITOR_ADDR: conf_rdata_reg <= {31'd0,num_monitor} ;
+ default : conf_rdata_reg <= 32'd0;
+ endcase
+ end
+ else if(r_retire)
+ begin
+ conf_rvalid_reg <= 1'b0;
+ end
+ end
+
+ //conf write, only support a word write
+ wire conf_we;
+ wire [31:0] conf_addr;
+ wire [31:0] conf_wdata;
+ assign conf_we = w_enter;
+ assign conf_addr = buf_addr;
+ assign conf_wdata= wdata;
+
+ reg conf_bvalid_reg;
+ assign bvalid = conf_bvalid_reg;
+ always @(posedge aclk)
+ begin
+ if (~aresetn) conf_bvalid_reg <= 1'b0;
+ else if(w_enter ) conf_bvalid_reg <= 1'b1;
+ else if(b_retire) conf_bvalid_reg <= 1'b0;
+ end
+
+ assign rid = buf_id;
+ assign bid = buf_id;
+ assign bresp = 2'b0;
+ assign rresp = 2'b0;
+//---------------------------{axi interface}end--------------------------//
+
+//-------------------------{confreg register}begin-----------------------//
+wire write_cr0 = conf_we & (conf_addr[15:0]==`CR0_ADDR);
+wire write_cr1 = conf_we & (conf_addr[15:0]==`CR1_ADDR);
+wire write_cr2 = conf_we & (conf_addr[15:0]==`CR2_ADDR);
+wire write_cr3 = conf_we & (conf_addr[15:0]==`CR3_ADDR);
+wire write_cr4 = conf_we & (conf_addr[15:0]==`CR4_ADDR);
+wire write_cr5 = conf_we & (conf_addr[15:0]==`CR5_ADDR);
+wire write_cr6 = conf_we & (conf_addr[15:0]==`CR6_ADDR);
+wire write_cr7 = conf_we & (conf_addr[15:0]==`CR7_ADDR);
+always @(posedge aclk)
+begin
+ cr0 <= !aresetn ? 32'd0 :
+ write_cr0 ? conf_wdata : cr0;
+ cr1 <= !aresetn ? 32'd0 :
+ write_cr1 ? conf_wdata : cr1;
+ cr2 <= !aresetn ? 32'd0 :
+ write_cr2 ? conf_wdata : cr2;
+ cr3 <= !aresetn ? 32'd0 :
+ write_cr3 ? conf_wdata : cr3;
+ cr4 <= !aresetn ? 32'd0 :
+ write_cr4 ? conf_wdata : cr4;
+ cr5 <= !aresetn ? 32'd0 :
+ write_cr5 ? conf_wdata : cr5;
+ cr6 <= !aresetn ? 32'd0 :
+ write_cr6 ? conf_wdata : cr6;
+ cr7 <= !aresetn ? 32'd0 :
+ write_cr7 ? conf_wdata : cr7;
+end
+//--------------------------{confreg register}end------------------------//
+
+//-------------------------------{timer}begin----------------------------//
+reg write_timer_begin,write_timer_begin_r1, write_timer_begin_r2,write_timer_begin_r3;
+reg write_timer_end_r1, write_timer_end_r2;
+reg [31:0] conf_wdata_r, conf_wdata_r1,conf_wdata_r2;
+
+reg [31:0] timer_r1;
+reg [31:0] timer;
+
+wire write_timer = conf_we & (conf_addr[15:0]==`TIMER_ADDR);
+always @(posedge aclk)
+begin
+ if (!aresetn)
+ begin
+ write_timer_begin <= 1'b0;
+ end
+ else if (write_timer)
+ begin
+ write_timer_begin <= 1'b1;
+ conf_wdata_r <= conf_wdata;
+ end
+ else if (write_timer_end_r2)
+ begin
+ write_timer_begin <= 1'b0;
+ end
+
+ write_timer_end_r1 <= write_timer_begin_r2;
+ write_timer_end_r2 <= write_timer_end_r1;
+end
+
+always @(posedge timer_clk)
+begin
+ write_timer_begin_r1 <= write_timer_begin;
+ write_timer_begin_r2 <= write_timer_begin_r1;
+ write_timer_begin_r3 <= write_timer_begin_r2;
+ conf_wdata_r1 <= conf_wdata_r;
+ conf_wdata_r2 <= conf_wdata_r1;
+
+ if(!aresetn)
+ begin
+ timer <= 32'd0;
+ end
+ else if (write_timer_begin_r2 && !write_timer_begin_r3)
+ begin
+ timer <= conf_wdata_r2[31:0];
+ end
+ else
+ begin
+ timer <= timer + 1'b1;
+ end
+end
+
+always @(posedge aclk)
+begin
+ timer_r1 <= timer;
+ timer_r2 <= timer_r1;
+end
+//--------------------------------{timer}end-----------------------------//
+
+//--------------------------{simulation flag}begin-----------------------//
+always @(posedge aclk)
+begin
+ if(!aresetn)
+ begin
+ simu_flag <= {32{SIMULATION}};
+ end
+end
+//---------------------------{simulation flag}end------------------------//
+
+//---------------------------{io simulation}begin------------------------//
+wire write_io_simu = conf_we & (conf_addr[15:0]==`IO_SIMU_ADDR);
+always @(posedge aclk)
+begin
+ if(!aresetn)
+ begin
+ io_simu <= 32'd0;
+ end
+ else if(write_io_simu)
+ begin
+ io_simu <= {conf_wdata[15:0],conf_wdata[31:16]};
+ end
+end
+//----------------------------{io simulation}end-------------------------//
+
+//-----------------------------{open trace}begin-------------------------//
+wire write_open_trace = conf_we & (conf_addr[15:0]==`OPEN_TRACE_ADDR);
+always @(posedge aclk)
+begin
+ if(!aresetn)
+ begin
+ open_trace <= 1'b1;
+ end
+ else if(write_open_trace)
+ begin
+ open_trace <= |conf_wdata;
+ end
+end
+//-----------------------------{open trace}end---------------------------//
+
+//----------------------------{num monitor}begin-------------------------//
+wire write_num_monitor = conf_we & (conf_addr[15:0]==`NUM_MONITOR_ADDR);
+always @(posedge aclk)
+begin
+ if(!aresetn)
+ begin
+ num_monitor <= 1'b1;
+ end
+ else if(write_num_monitor)
+ begin
+ num_monitor <= conf_wdata[0];
+ end
+end
+//----------------------------{num monitor}end---------------------------//
+
+//---------------------------{virtual uart}begin-------------------------//
+wire [7:0] write_uart_data;
+wire write_uart_valid = conf_we & (conf_addr[15:0]==`VIRTUAL_UART_ADDR);
+assign write_uart_data = conf_wdata[7:0];
+always @(posedge aclk)
+begin
+ if(!aresetn)
+ begin
+ virtual_uart_data <= 8'd0;
+ end
+ else if(write_uart_valid)
+ begin
+ virtual_uart_data <= write_uart_data;
+ end
+end
+//----------------------------{virtual uart}end--------------------------//
+
+//--------------------------{axirandom mask}begin------------------------//
+wire [15:0] switch_led;
+wire [15:0] led_r_n;
+assign led_r_n = ~switch_led;
+
+reg [22:0] pseudo_random_23;
+reg no_mask; //if led_r_n is all 1, no mask
+reg short_delay; //memory long delay
+always @ (posedge aclk)
+begin
+ if (!aresetn)
+ pseudo_random_23 <= simu_flag[0] ? `RANDOM_SEED : {7'b1010101,led_r_n};
+ else
+ pseudo_random_23 <= {pseudo_random_23[21:0],pseudo_random_23[22] ^ pseudo_random_23[17]};
+
+ if(!aresetn)
+ no_mask <= pseudo_random_23[15:0]==16'h00FF;
+
+ if(!aresetn)
+ short_delay <= pseudo_random_23[7:0]==8'hFF;
+end
+assign ram_random_mask[0] = (pseudo_random_23[10]&pseudo_random_23[20]) & (short_delay|(pseudo_random_23[11]^pseudo_random_23[5]))
+ | no_mask;
+assign ram_random_mask[1] = (pseudo_random_23[ 9]&pseudo_random_23[17]) & (short_delay|(pseudo_random_23[12]^pseudo_random_23[4]))
+ | no_mask;
+assign ram_random_mask[2] = (pseudo_random_23[ 8]^pseudo_random_23[22]) & (short_delay|(pseudo_random_23[13]^pseudo_random_23[3]))
+ | no_mask;
+assign ram_random_mask[3] = (pseudo_random_23[ 7]&pseudo_random_23[19]) & (short_delay|(pseudo_random_23[14]^pseudo_random_23[2]))
+ | no_mask;
+assign ram_random_mask[4] = (pseudo_random_23[ 6]^pseudo_random_23[16]) & (short_delay|(pseudo_random_23[15]^pseudo_random_23[1]))
+ | no_mask;
+
+//---------------------------{axirandom mask}end-------------------------//
+
+//--------------------------------{led}begin-----------------------------//
+//led display
+//led_data[31:0]
+wire write_led = conf_we & (conf_addr[15:0]==`LED_ADDR);
+
+assign led = led_data[15:0];
+
+assign switch_led = {{2{switch[7]}},{2{switch[6]}},{2{switch[5]}},{2{switch[4]}},
+ {2{switch[3]}},{2{switch[2]}},{2{switch[1]}},{2{switch[0]}}};
+always @(posedge aclk)
+begin
+ if(!aresetn)
+ begin
+ led_data <= {16'h0,switch_led};
+ end
+ else if(write_led)
+ begin
+ led_data <= conf_wdata[31:0];
+ end
+end
+//---------------------------------{led}end------------------------------//
+
+//-------------------------------{switch}begin---------------------------//
+//switch data
+//switch_data[7:0]
+assign switch_data = {24'd0,switch};
+assign sw_inter_data = {16'd0,
+ switch[7],1'b0,switch[6],1'b0,
+ switch[5],1'b0,switch[4],1'b0,
+ switch[3],1'b0,switch[2],1'b0,
+ switch[1],1'b0,switch[0],1'b0};
+//--------------------------------{switch}end----------------------------//
+
+//------------------------------{btn key}begin---------------------------//
+//btn key data
+reg [15:0] btn_key_r;
+assign btn_key_data = {16'd0,btn_key_r};
+
+//state machine
+reg [2:0] state;
+wire [2:0] next_state;
+
+//eliminate jitter
+reg key_flag;
+reg [19:0] key_count;
+reg [ 3:0] state_count;
+wire key_start = (state==3'b000) && !(&btn_key_row);
+wire key_end = (state==3'b111) && (&btn_key_row);
+wire key_sample= key_count[19];
+always @(posedge aclk)
+begin
+ if(!aresetn)
+ begin
+ key_flag <= 1'd0;
+ end
+ else if (key_sample && state_count[3])
+ begin
+ key_flag <= 1'b0;
+ end
+ else if( key_start || key_end )
+ begin
+ key_flag <= 1'b1;
+ end
+
+ if(!aresetn || !key_flag)
+ begin
+ key_count <= 20'd0;
+ end
+ else
+ begin
+ key_count <= key_count + 1'b1;
+ end
+end
+
+always @(posedge aclk)
+begin
+ if(!aresetn || state_count[3])
+ begin
+ state_count <= 4'd0;
+ end
+ else
+ begin
+ state_count <= state_count + 1'b1;
+ end
+end
+
+always @(posedge aclk)
+begin
+ if(!aresetn)
+ begin
+ state <= 3'b000;
+ end
+ else if (state_count[3])
+ begin
+ state <= next_state;
+ end
+end
+
+assign next_state = (state == 3'b000) ? ( (key_sample && !(&btn_key_row)) ? 3'b001 : 3'b000 ) :
+ (state == 3'b001) ? ( !(&btn_key_row) ? 3'b111 : 3'b010 ) :
+ (state == 3'b010) ? ( !(&btn_key_row) ? 3'b111 : 3'b011 ) :
+ (state == 3'b011) ? ( !(&btn_key_row) ? 3'b111 : 3'b100 ) :
+ (state == 3'b100) ? ( !(&btn_key_row) ? 3'b111 : 3'b000 ) :
+ (state == 3'b111) ? ( (key_sample && (&btn_key_row)) ? 3'b000 : 3'b111 ) :
+ 3'b000;
+assign btn_key_col = (state == 3'b000) ? 4'b0000:
+ (state == 3'b001) ? 4'b1110:
+ (state == 3'b010) ? 4'b1101:
+ (state == 3'b011) ? 4'b1011:
+ (state == 3'b100) ? 4'b0111:
+ 4'b0000;
+wire [15:0] btn_key_tmp;
+always @(posedge aclk) begin
+ if(!aresetn) begin
+ btn_key_r <= 16'd0;
+ end
+ else if(next_state==3'b000)
+ begin
+ btn_key_r <=16'd0;
+ end
+ else if(next_state == 3'b111 && state != 3'b111) begin
+ btn_key_r <= btn_key_tmp;
+ end
+end
+
+assign btn_key_tmp = (state == 3'b001)&(btn_key_row == 4'b1110) ? 16'h0001:
+ (state == 3'b001)&(btn_key_row == 4'b1101) ? 16'h0010:
+ (state == 3'b001)&(btn_key_row == 4'b1011) ? 16'h0100:
+ (state == 3'b001)&(btn_key_row == 4'b0111) ? 16'h1000:
+ (state == 3'b010)&(btn_key_row == 4'b1110) ? 16'h0002:
+ (state == 3'b010)&(btn_key_row == 4'b1101) ? 16'h0020:
+ (state == 3'b010)&(btn_key_row == 4'b1011) ? 16'h0200:
+ (state == 3'b010)&(btn_key_row == 4'b0111) ? 16'h2000:
+ (state == 3'b011)&(btn_key_row == 4'b1110) ? 16'h0004:
+ (state == 3'b011)&(btn_key_row == 4'b1101) ? 16'h0040:
+ (state == 3'b011)&(btn_key_row == 4'b1011) ? 16'h0400:
+ (state == 3'b011)&(btn_key_row == 4'b0111) ? 16'h4000:
+ (state == 3'b100)&(btn_key_row == 4'b1110) ? 16'h0008:
+ (state == 3'b100)&(btn_key_row == 4'b1101) ? 16'h0080:
+ (state == 3'b100)&(btn_key_row == 4'b1011) ? 16'h0800:
+ (state == 3'b100)&(btn_key_row == 4'b0111) ? 16'h8000:16'h0000;
+//-------------------------------{btn key}end----------------------------//
+
+//-----------------------------{btn step}begin---------------------------//
+//btn step data
+reg btn_step0_r; //0:press
+reg btn_step1_r; //0:press
+assign btn_step_data = {30'd0,~btn_step0_r,~btn_step1_r}; //1:press
+
+//-----step0
+//eliminate jitter
+reg step0_flag;
+reg [19:0] step0_count;
+wire step0_start = btn_step0_r && !btn_step[0];
+wire step0_end = !btn_step0_r && btn_step[0];
+wire step0_sample= step0_count[19];
+always @(posedge aclk)
+begin
+ if(!aresetn)
+ begin
+ step0_flag <= 1'd0;
+ end
+ else if (step0_sample)
+ begin
+ step0_flag <= 1'b0;
+ end
+ else if( step0_start || step0_end )
+ begin
+ step0_flag <= 1'b1;
+ end
+
+ if(!aresetn || !step0_flag)
+ begin
+ step0_count <= 20'd0;
+ end
+ else
+ begin
+ step0_count <= step0_count + 1'b1;
+ end
+
+ if(!aresetn)
+ begin
+ btn_step0_r <= 1'b1;
+ end
+ else if(step0_sample)
+ begin
+ btn_step0_r <= btn_step[0];
+ end
+end
+
+//-----step1
+//eliminate jitter
+reg step1_flag;
+reg [19:0] step1_count;
+wire step1_start = btn_step1_r && !btn_step[1];
+wire step1_end = !btn_step1_r && btn_step[1];
+wire step1_sample= step1_count[19];
+always @(posedge aclk)
+begin
+ if(!aresetn)
+ begin
+ step1_flag <= 1'd0;
+ end
+ else if (step1_sample)
+ begin
+ step1_flag <= 1'b0;
+ end
+ else if( step1_start || step1_end )
+ begin
+ step1_flag <= 1'b1;
+ end
+
+ if(!aresetn || !step1_flag)
+ begin
+ step1_count <= 20'd0;
+ end
+ else
+ begin
+ step1_count <= step1_count + 1'b1;
+ end
+
+ if(!aresetn)
+ begin
+ btn_step1_r <= 1'b1;
+ end
+ else if(step1_sample)
+ begin
+ btn_step1_r <= btn_step[1];
+ end
+end
+//------------------------------{btn step}end----------------------------//
+
+//-------------------------------{led rg}begin---------------------------//
+//led_rg0_data[31:0] led_rg0_data[31:0]
+//bfd0_f010 bfd0_f014
+wire write_led_rg0 = conf_we & (conf_addr[15:0]==`LED_RG0_ADDR);
+wire write_led_rg1 = conf_we & (conf_addr[15:0]==`LED_RG1_ADDR);
+assign led_rg0 = led_rg0_data[1:0];
+assign led_rg1 = led_rg1_data[1:0];
+always @(posedge aclk)
+begin
+ if(!aresetn)
+ begin
+ led_rg0_data <= 32'h0;
+ end
+ else if(write_led_rg0)
+ begin
+ led_rg0_data <= conf_wdata[31:0];
+ end
+
+ if(!aresetn)
+ begin
+ led_rg1_data <= 32'h0;
+ end
+ else if(write_led_rg1)
+ begin
+ led_rg1_data <= conf_wdata[31:0];
+ end
+end
+//--------------------------------{led rg}end----------------------------//
+
+//---------------------------{digital number}begin-----------------------//
+//digital number display
+//num_data[31:0]
+wire write_num = conf_we & (conf_addr[15:0]==`NUM_ADDR);
+always @(posedge aclk)
+begin
+ if(!aresetn)
+ begin
+ num_data <= 32'h0;
+ end
+ else if(write_num)
+ begin
+ num_data <= conf_wdata[31:0];
+ end
+end
+
+
+reg [19:0] count;
+always @(posedge aclk)
+begin
+ if(!aresetn)
+ begin
+ count <= 20'd0;
+ end
+ else
+ begin
+ count <= count + 1'b1;
+ end
+end
+//scan data
+reg [3:0] scan_data;
+always @ ( posedge aclk )
+begin
+ if ( !aresetn )
+ begin
+ scan_data <= 32'd0;
+ num_csn <= 8'b1111_1111;
+ end
+ else
+ begin
+ case(count[19:17])
+ 3'b000 : scan_data <= num_data[31:28];
+ 3'b001 : scan_data <= num_data[27:24];
+ 3'b010 : scan_data <= num_data[23:20];
+ 3'b011 : scan_data <= num_data[19:16];
+ 3'b100 : scan_data <= num_data[15:12];
+ 3'b101 : scan_data <= num_data[11: 8];
+ 3'b110 : scan_data <= num_data[7 : 4];
+ 3'b111 : scan_data <= num_data[3 : 0];
+ endcase
+
+ case(count[19:17])
+ 3'b000 : num_csn <= 8'b0111_1111;
+ 3'b001 : num_csn <= 8'b1011_1111;
+ 3'b010 : num_csn <= 8'b1101_1111;
+ 3'b011 : num_csn <= 8'b1110_1111;
+ 3'b100 : num_csn <= 8'b1111_0111;
+ 3'b101 : num_csn <= 8'b1111_1011;
+ 3'b110 : num_csn <= 8'b1111_1101;
+ 3'b111 : num_csn <= 8'b1111_1110;
+ endcase
+ end
+end
+
+always @(posedge aclk)
+begin
+ if ( !aresetn )
+ begin
+ num_a_g <= 7'b0000000;
+ end
+ else
+ begin
+ case ( scan_data )
+ 4'd0 : num_a_g <= 7'b1111110; //0
+ 4'd1 : num_a_g <= 7'b0110000; //1
+ 4'd2 : num_a_g <= 7'b1101101; //2
+ 4'd3 : num_a_g <= 7'b1111001; //3
+ 4'd4 : num_a_g <= 7'b0110011; //4
+ 4'd5 : num_a_g <= 7'b1011011; //5
+ 4'd6 : num_a_g <= 7'b1011111; //6
+ 4'd7 : num_a_g <= 7'b1110000; //7
+ 4'd8 : num_a_g <= 7'b1111111; //8
+ 4'd9 : num_a_g <= 7'b1111011; //9
+ 4'd10: num_a_g <= 7'b1110111; //a
+ 4'd11: num_a_g <= 7'b0011111; //b
+ 4'd12: num_a_g <= 7'b1001110; //c
+ 4'd13: num_a_g <= 7'b0111101; //d
+ 4'd14: num_a_g <= 7'b1001111; //e
+ 4'd15: num_a_g <= 7'b1000111; //f
+ endcase
+ end
+end
+//----------------------------{digital number}end------------------------//
+endmodule
diff --git a/src/testbench/MMU/soc_lite_top.v b/src/testbench/MMU/soc_lite_top.v
new file mode 100644
index 0000000..9f96433
--- /dev/null
+++ b/src/testbench/MMU/soc_lite_top.v
@@ -0,0 +1,728 @@
+/*------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+Copyright (c) 2016, Loongson Technology Corporation Limited.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice,
+this list of conditions and the following disclaimer in the documentation and/or
+other materials provided with the distribution.
+
+3. Neither the name of Loongson Technology Corporation Limited nor the names of
+its contributors may be used to endorse or promote products derived from this
+software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
+TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--------------------------------------------------------------------------------
+------------------------------------------------------------------------------*/
+`timescale 1ns / 1ps
+//*************************************************************************
+// > File Name : soc_top.v
+// > Description : SoC, included cpu, 2 x 3 bridge,
+// inst ram, confreg, data ram
+//
+// -------------------------
+// | cpu |
+// -------------------------
+// | axi
+// |
+// ---------------------
+// | 1 x 2 bridge |
+// ---------------------
+// | |
+// | |
+// ----------- -----------
+// | axi ram | | confreg |
+// ----------- -----------
+//
+// > Author : LOONGSON
+// > Date : 2017-08-04
+//*************************************************************************
+
+//for simulation:
+//1. if define SIMU_USE_PLL = 1, will use clk_pll to generate cpu_clk/sys_clk,
+// and simulation will be very slow.
+//2. usually, please define SIMU_USE_PLL=0 to speed up simulation by assign
+// cpu_clk=clk, sys_clk = clk.
+// at this time, frequency of cpu_clk is 91MHz.
+`define SIMU_USE_PLL 0 //set 0 to speed up simulation
+
+module soc_axi_lite_top;
+
+wire resetn;
+wire clk;
+
+wire [15:0] led;
+wire [1 :0] led_rg0;
+wire [1 :0] led_rg1;
+wire [7 :0] num_csn;
+wire [6 :0] num_a_g;
+wire [7 :0] switch;
+wire [3 :0] btn_key_col;
+wire [3 :0] btn_key_row;
+wire [1 :0] btn_step;
+
+//debug signals
+wire [31:0] debug_wb_pc;
+wire [3 :0] debug_wb_rf_wen;
+wire [4 :0] debug_wb_rf_wnum;
+wire [31:0] debug_wb_rf_wdata;
+
+//clk and resetn
+wire cpu_clk;
+wire sys_clk;
+reg cpu_resetn_t, cpu_resetn;
+reg sys_resetn_t, sys_resetn;
+always @(posedge cpu_clk)
+begin
+ cpu_resetn_t <= resetn;
+ cpu_resetn <= cpu_resetn_t;
+end
+always @(posedge sys_clk)
+begin
+ sys_resetn_t <= resetn;
+ sys_resetn <= sys_resetn_t;
+end
+//simulation clk.
+reg clk_91m;
+initial
+begin
+ clk_91m = 1'b0;
+end
+always #5.5 clk_91m = ~clk_91m;
+
+assign cpu_clk = clk_91m;
+assign sys_clk = clk;
+
+
+//cpu axi
+wire [3 :0] cpu_arid ;
+wire [31:0] cpu_araddr ;
+wire [3 :0] cpu_arlen ;
+wire [2 :0] cpu_arsize ;
+wire [1 :0] cpu_arburst;
+wire [1 :0] cpu_arlock ;
+wire [3 :0] cpu_arcache;
+wire [2 :0] cpu_arprot ;
+wire cpu_arvalid;
+wire cpu_arready;
+wire [3 :0] cpu_rid ;
+wire [31:0] cpu_rdata ;
+wire [1 :0] cpu_rresp ;
+wire cpu_rlast ;
+wire cpu_rvalid ;
+wire cpu_rready ;
+wire [3 :0] cpu_awid ;
+wire [31:0] cpu_awaddr ;
+wire [3 :0] cpu_awlen ;
+wire [2 :0] cpu_awsize ;
+wire [1 :0] cpu_awburst;
+wire [1 :0] cpu_awlock ;
+wire [3 :0] cpu_awcache;
+wire [2 :0] cpu_awprot ;
+wire cpu_awvalid;
+wire cpu_awready;
+wire [3 :0] cpu_wid ;
+wire [31:0] cpu_wdata ;
+wire [3 :0] cpu_wstrb ;
+wire cpu_wlast ;
+wire cpu_wvalid ;
+wire cpu_wready ;
+wire [3 :0] cpu_bid ;
+wire [1 :0] cpu_bresp ;
+wire cpu_bvalid ;
+wire cpu_bready ;
+
+//cpu axi wrap
+wire cpu_wrap_aclk ;
+wire cpu_wrap_aresetn;
+wire [3 :0] cpu_wrap_arid ;
+wire [31:0] cpu_wrap_araddr ;
+wire [3 :0] cpu_wrap_arlen ;
+wire [2 :0] cpu_wrap_arsize ;
+wire [1 :0] cpu_wrap_arburst;
+wire [1 :0] cpu_wrap_arlock ;
+wire [3 :0] cpu_wrap_arcache;
+wire [2 :0] cpu_wrap_arprot ;
+wire cpu_wrap_arvalid;
+wire cpu_wrap_arready;
+wire [3 :0] cpu_wrap_rid ;
+wire [31:0] cpu_wrap_rdata ;
+wire [1 :0] cpu_wrap_rresp ;
+wire cpu_wrap_rlast ;
+wire cpu_wrap_rvalid ;
+wire cpu_wrap_rready ;
+wire [3 :0] cpu_wrap_awid ;
+wire [31:0] cpu_wrap_awaddr ;
+wire [3 :0] cpu_wrap_awlen ;
+wire [2 :0] cpu_wrap_awsize ;
+wire [1 :0] cpu_wrap_awburst;
+wire [1 :0] cpu_wrap_awlock ;
+wire [3 :0] cpu_wrap_awcache;
+wire [2 :0] cpu_wrap_awprot ;
+wire cpu_wrap_awvalid;
+wire cpu_wrap_awready;
+wire [3 :0] cpu_wrap_wid ;
+wire [31:0] cpu_wrap_wdata ;
+wire [3 :0] cpu_wrap_wstrb ;
+wire cpu_wrap_wlast ;
+wire cpu_wrap_wvalid ;
+wire cpu_wrap_wready ;
+wire [3 :0] cpu_wrap_bid ;
+wire [1 :0] cpu_wrap_bresp ;
+wire cpu_wrap_bvalid ;
+wire cpu_wrap_bready ;
+//cpu axi sync
+wire [3 :0] cpu_sync_arid ;
+wire [31:0] cpu_sync_araddr ;
+wire [3 :0] cpu_sync_arlen ;
+wire [2 :0] cpu_sync_arsize ;
+wire [1 :0] cpu_sync_arburst;
+wire [1 :0] cpu_sync_arlock ;
+wire [3 :0] cpu_sync_arcache;
+wire [2 :0] cpu_sync_arprot ;
+wire cpu_sync_arvalid;
+wire cpu_sync_arready;
+wire [3 :0] cpu_sync_rid ;
+wire [31:0] cpu_sync_rdata ;
+wire [1 :0] cpu_sync_rresp ;
+wire cpu_sync_rlast ;
+wire cpu_sync_rvalid ;
+wire cpu_sync_rready ;
+wire [3 :0] cpu_sync_awid ;
+wire [31:0] cpu_sync_awaddr ;
+wire [3 :0] cpu_sync_awlen ;
+wire [2 :0] cpu_sync_awsize ;
+wire [1 :0] cpu_sync_awburst;
+wire [1 :0] cpu_sync_awlock ;
+wire [3 :0] cpu_sync_awcache;
+wire [2 :0] cpu_sync_awprot ;
+wire cpu_sync_awvalid;
+wire cpu_sync_awready;
+wire [3 :0] cpu_sync_wid ;
+wire [31:0] cpu_sync_wdata ;
+wire [3 :0] cpu_sync_wstrb ;
+wire cpu_sync_wlast ;
+wire cpu_sync_wvalid ;
+wire cpu_sync_wready ;
+wire [3 :0] cpu_sync_bid ;
+wire [1 :0] cpu_sync_bresp ;
+wire cpu_sync_bvalid ;
+wire cpu_sync_bready ;
+//axi ram
+wire [3 :0] ram_arid ;
+wire [31:0] ram_araddr ;
+wire [3 :0] ram_arlen ;
+wire [2 :0] ram_arsize ;
+wire [1 :0] ram_arburst;
+wire [1 :0] ram_arlock ;
+wire [3 :0] ram_arcache;
+wire [2 :0] ram_arprot ;
+wire ram_arvalid;
+wire ram_arready;
+wire [3 :0] ram_rid ;
+wire [31:0] ram_rdata ;
+wire [1 :0] ram_rresp ;
+wire ram_rlast ;
+wire ram_rvalid ;
+wire ram_rready ;
+wire [3 :0] ram_awid ;
+wire [31:0] ram_awaddr ;
+wire [3 :0] ram_awlen ;
+wire [2 :0] ram_awsize ;
+wire [1 :0] ram_awburst;
+wire [1 :0] ram_awlock ;
+wire [3 :0] ram_awcache;
+wire [2 :0] ram_awprot ;
+wire ram_awvalid;
+wire ram_awready;
+wire [3 :0] ram_wid ;
+wire [31:0] ram_wdata ;
+wire [3 :0] ram_wstrb ;
+wire ram_wlast ;
+wire ram_wvalid ;
+wire ram_wready ;
+wire [3 :0] ram_bid ;
+wire [1 :0] ram_bresp ;
+wire ram_bvalid ;
+wire ram_bready ;
+//conf
+wire [3 :0] conf_arid ;
+wire [31:0] conf_araddr ;
+wire [3 :0] conf_arlen ;
+wire [2 :0] conf_arsize ;
+wire [1 :0] conf_arburst;
+wire [1 :0] conf_arlock ;
+wire [3 :0] conf_arcache;
+wire [2 :0] conf_arprot ;
+wire conf_arvalid;
+wire conf_arready;
+wire [3 :0] conf_rid ;
+wire [31:0] conf_rdata ;
+wire [1 :0] conf_rresp ;
+wire conf_rlast ;
+wire conf_rvalid ;
+wire conf_rready ;
+wire [3 :0] conf_awid ;
+wire [31:0] conf_awaddr ;
+wire [3 :0] conf_awlen ;
+wire [2 :0] conf_awsize ;
+wire [1 :0] conf_awburst;
+wire [1 :0] conf_awlock ;
+wire [3 :0] conf_awcache;
+wire [2 :0] conf_awprot ;
+wire conf_awvalid;
+wire conf_awready;
+wire [3 :0] conf_wid ;
+wire [31:0] conf_wdata ;
+wire [3 :0] conf_wstrb ;
+wire conf_wlast ;
+wire conf_wvalid ;
+wire conf_wready ;
+wire [3 :0] conf_bid ;
+wire [1 :0] conf_bresp ;
+wire conf_bvalid ;
+wire conf_bready ;
+
+//for lab6
+wire [4 :0] ram_random_mask;
+
+//cpu axi
+//debug_*
+mycpu_top u_cpu(
+ .ext_int (6'd0 ), //high active
+
+ .aclk (cpu_clk ),
+ .aresetn (cpu_resetn ), //low active
+
+ .arid (cpu_arid ),
+ .araddr (cpu_araddr ),
+ .arlen (cpu_arlen ),
+ .arsize (cpu_arsize ),
+ .arburst (cpu_arburst ),
+ .arlock (cpu_arlock ),
+ .arcache (cpu_arcache ),
+ .arprot (cpu_arprot ),
+ .arvalid (cpu_arvalid ),
+ .arready (cpu_arready ),
+
+ .rid (cpu_rid ),
+ .rdata (cpu_rdata ),
+ .rresp (cpu_rresp ),
+ .rlast (cpu_rlast ),
+ .rvalid (cpu_rvalid ),
+ .rready (cpu_rready ),
+
+ .awid (cpu_awid ),
+ .awaddr (cpu_awaddr ),
+ .awlen (cpu_awlen ),
+ .awsize (cpu_awsize ),
+ .awburst (cpu_awburst ),
+ .awlock (cpu_awlock ),
+ .awcache (cpu_awcache ),
+ .awprot (cpu_awprot ),
+ .awvalid (cpu_awvalid ),
+ .awready (cpu_awready ),
+
+ .wid (cpu_wid ),
+ .wdata (cpu_wdata ),
+ .wstrb (cpu_wstrb ),
+ .wlast (cpu_wlast ),
+ .wvalid (cpu_wvalid ),
+ .wready (cpu_wready ),
+
+ .bid (cpu_bid ),
+ .bresp (cpu_bresp ),
+ .bvalid (cpu_bvalid ),
+ .bready (cpu_bready ),
+
+ //debug interface
+ .debug_wb_pc (debug_wb_pc ),
+ .debug_wb_rf_wen (debug_wb_rf_wen ),
+ .debug_wb_rf_wnum (debug_wb_rf_wnum ),
+ .debug_wb_rf_wdata(debug_wb_rf_wdata)
+);
+//cpu axi wrap
+axi_wrap u_cpu_axi_wrap(
+ .m_aclk ( cpu_clk ),
+ .m_aresetn ( cpu_resetn ),
+ //ar
+ .m_arid ( cpu_arid ),
+ .m_araddr ( cpu_araddr ),
+ .m_arlen ( cpu_arlen ),
+ .m_arsize ( cpu_arsize ),
+ .m_arburst ( cpu_arburst ),
+ .m_arlock ( cpu_arlock ),
+ .m_arcache ( cpu_arcache ),
+ .m_arprot ( cpu_arprot ),
+ .m_arvalid ( cpu_arvalid ),
+ .m_arready ( cpu_arready ),
+ //r
+ .m_rid ( cpu_rid ),
+ .m_rdata ( cpu_rdata ),
+ .m_rresp ( cpu_rresp ),
+ .m_rlast ( cpu_rlast ),
+ .m_rvalid ( cpu_rvalid ),
+ .m_rready ( cpu_rready ),
+ //aw
+ .m_awid ( cpu_awid ),
+ .m_awaddr ( cpu_awaddr ),
+ .m_awlen ( cpu_awlen ),
+ .m_awsize ( cpu_awsize ),
+ .m_awburst ( cpu_awburst ),
+ .m_awlock ( cpu_awlock ),
+ .m_awcache ( cpu_awcache ),
+ .m_awprot ( cpu_awprot ),
+ .m_awvalid ( cpu_awvalid ),
+ .m_awready ( cpu_awready ),
+ //w
+ .m_wid ( cpu_wid ),
+ .m_wdata ( cpu_wdata ),
+ .m_wstrb ( cpu_wstrb ),
+ .m_wlast ( cpu_wlast ),
+ .m_wvalid ( cpu_wvalid ),
+ .m_wready ( cpu_wready ),
+ //b
+ .m_bid ( cpu_bid ),
+ .m_bresp ( cpu_bresp ),
+ .m_bvalid ( cpu_bvalid ),
+ .m_bready ( cpu_bready ),
+
+ .s_aclk ( cpu_wrap_aclk ),
+ .s_aresetn ( cpu_wrap_aresetn ),
+ //ar
+ .s_arid ( cpu_wrap_arid ),
+ .s_araddr ( cpu_wrap_araddr ),
+ .s_arlen ( cpu_wrap_arlen ),
+ .s_arsize ( cpu_wrap_arsize ),
+ .s_arburst ( cpu_wrap_arburst ),
+ .s_arlock ( cpu_wrap_arlock ),
+ .s_arcache ( cpu_wrap_arcache ),
+ .s_arprot ( cpu_wrap_arprot ),
+ .s_arvalid ( cpu_wrap_arvalid ),
+ .s_arready ( cpu_wrap_arready ),
+ //r
+ .s_rid ( cpu_wrap_rid ),
+ .s_rdata ( cpu_wrap_rdata ),
+ .s_rresp ( cpu_wrap_rresp ),
+ .s_rlast ( cpu_wrap_rlast ),
+ .s_rvalid ( cpu_wrap_rvalid ),
+ .s_rready ( cpu_wrap_rready ),
+ //aw
+ .s_awid ( cpu_wrap_awid ),
+ .s_awaddr ( cpu_wrap_awaddr ),
+ .s_awlen ( cpu_wrap_awlen ),
+ .s_awsize ( cpu_wrap_awsize ),
+ .s_awburst ( cpu_wrap_awburst ),
+ .s_awlock ( cpu_wrap_awlock ),
+ .s_awcache ( cpu_wrap_awcache ),
+ .s_awprot ( cpu_wrap_awprot ),
+ .s_awvalid ( cpu_wrap_awvalid ),
+ .s_awready ( cpu_wrap_awready ),
+ //w
+ .s_wid ( cpu_wrap_wid ),
+ .s_wdata ( cpu_wrap_wdata ),
+ .s_wstrb ( cpu_wrap_wstrb ),
+ .s_wlast ( cpu_wrap_wlast ),
+ .s_wvalid ( cpu_wrap_wvalid ),
+ .s_wready ( cpu_wrap_wready ),
+ //b
+ .s_bid ( cpu_wrap_bid ),
+ .s_bresp ( cpu_wrap_bresp ),
+ .s_bvalid ( cpu_wrap_bvalid ),
+ .s_bready ( cpu_wrap_bready )
+);
+
+//clock sync: from CPU to AXI_Crossbar
+axi_clock_converter u_axi_clock_sync(
+ .s_axi_aclk (cpu_clk ),
+ .s_axi_aresetn (cpu_resetn ),
+ .s_axi_awid (cpu_wrap_awid ),
+ .s_axi_awaddr (cpu_wrap_awaddr ),
+ .s_axi_awlen (cpu_wrap_awlen ),
+ .s_axi_awsize (cpu_wrap_awsize ),
+ .s_axi_awburst (cpu_wrap_awburst ),
+ .s_axi_awlock (cpu_wrap_awlock ),
+ .s_axi_awcache (cpu_wrap_awcache ),
+ .s_axi_awprot (cpu_wrap_awprot ),
+ .s_axi_awqos (4'd0 ),
+ .s_axi_awvalid (cpu_wrap_awvalid ),
+ .s_axi_awready (cpu_wrap_awready ),
+ .s_axi_wid (cpu_wrap_wid ),
+ .s_axi_wdata (cpu_wrap_wdata ),
+ .s_axi_wstrb (cpu_wrap_wstrb ),
+ .s_axi_wlast (cpu_wrap_wlast ),
+ .s_axi_wvalid (cpu_wrap_wvalid ),
+ .s_axi_wready (cpu_wrap_wready ),
+ .s_axi_bid (cpu_wrap_bid ),
+ .s_axi_bresp (cpu_wrap_bresp ),
+ .s_axi_bvalid (cpu_wrap_bvalid ),
+ .s_axi_bready (cpu_wrap_bready ),
+ .s_axi_arid (cpu_wrap_arid ),
+ .s_axi_araddr (cpu_wrap_araddr ),
+ .s_axi_arlen (cpu_wrap_arlen ),
+ .s_axi_arsize (cpu_wrap_arsize ),
+ .s_axi_arburst (cpu_wrap_arburst ),
+ .s_axi_arlock (cpu_wrap_arlock ),
+ .s_axi_arcache (cpu_wrap_arcache ),
+ .s_axi_arprot (cpu_wrap_arprot ),
+ .s_axi_arqos (4'd0 ),
+ .s_axi_arvalid (cpu_wrap_arvalid ),
+ .s_axi_arready (cpu_wrap_arready ),
+ .s_axi_rid (cpu_wrap_rid ),
+ .s_axi_rdata (cpu_wrap_rdata ),
+ .s_axi_rresp (cpu_wrap_rresp ),
+ .s_axi_rlast (cpu_wrap_rlast ),
+ .s_axi_rvalid (cpu_wrap_rvalid ),
+ .s_axi_rready (cpu_wrap_rready ),
+ .m_axi_aclk (sys_clk ),
+ .m_axi_aresetn (sys_resetn ),
+ .m_axi_awid (cpu_sync_awid ),
+ .m_axi_awaddr (cpu_sync_awaddr ),
+ .m_axi_awlen (cpu_sync_awlen ),
+ .m_axi_awsize (cpu_sync_awsize ),
+ .m_axi_awburst (cpu_sync_awburst ),
+ .m_axi_awlock (cpu_sync_awlock ),
+ .m_axi_awcache (cpu_sync_awcache ),
+ .m_axi_awprot (cpu_sync_awprot ),
+ .m_axi_awqos ( ),
+ .m_axi_awvalid (cpu_sync_awvalid ),
+ .m_axi_awready (cpu_sync_awready ),
+ .m_axi_wid (cpu_sync_wid ),
+ .m_axi_wdata (cpu_sync_wdata ),
+ .m_axi_wstrb (cpu_sync_wstrb ),
+ .m_axi_wlast (cpu_sync_wlast ),
+ .m_axi_wvalid (cpu_sync_wvalid ),
+ .m_axi_wready (cpu_sync_wready ),
+ .m_axi_bid (cpu_sync_bid ),
+ .m_axi_bresp (cpu_sync_bresp ),
+ .m_axi_bvalid (cpu_sync_bvalid ),
+ .m_axi_bready (cpu_sync_bready ),
+ .m_axi_arid (cpu_sync_arid ),
+ .m_axi_araddr (cpu_sync_araddr ),
+ .m_axi_arlen (cpu_sync_arlen ),
+ .m_axi_arsize (cpu_sync_arsize ),
+ .m_axi_arburst (cpu_sync_arburst ),
+ .m_axi_arlock (cpu_sync_arlock ),
+ .m_axi_arcache (cpu_sync_arcache ),
+ .m_axi_arprot (cpu_sync_arprot ),
+ .m_axi_arqos ( ),
+ .m_axi_arvalid (cpu_sync_arvalid ),
+ .m_axi_arready (cpu_sync_arready ),
+ .m_axi_rid (cpu_sync_rid ),
+ .m_axi_rdata (cpu_sync_rdata ),
+ .m_axi_rresp (cpu_sync_rresp ),
+ .m_axi_rlast (cpu_sync_rlast ),
+ .m_axi_rvalid (cpu_sync_rvalid ),
+ .m_axi_rready (cpu_sync_rready )
+);
+
+
+axi_crossbar_1x2 u_axi_crossbar_1x2(
+ .aclk ( sys_clk ), // i, 1
+ .aresetn ( sys_resetn ), // i, 1
+
+ .s_axi_arid ( cpu_sync_arid ),
+ .s_axi_araddr ( cpu_sync_araddr ),
+ .s_axi_arlen ( cpu_sync_arlen[3:0] ),
+ .s_axi_arsize ( cpu_sync_arsize ),
+ .s_axi_arburst ( cpu_sync_arburst ),
+ .s_axi_arlock ( cpu_sync_arlock ),
+ .s_axi_arcache ( cpu_sync_arcache ),
+ .s_axi_arprot ( cpu_sync_arprot ),
+ .s_axi_arqos ( 4'd0 ),
+ .s_axi_arvalid ( cpu_sync_arvalid ),
+ .s_axi_arready ( cpu_sync_arready ),
+ .s_axi_rid ( cpu_sync_rid ),
+ .s_axi_rdata ( cpu_sync_rdata ),
+ .s_axi_rresp ( cpu_sync_rresp ),
+ .s_axi_rlast ( cpu_sync_rlast ),
+ .s_axi_rvalid ( cpu_sync_rvalid ),
+ .s_axi_rready ( cpu_sync_rready ),
+ .s_axi_awid ( cpu_sync_awid ),
+ .s_axi_awaddr ( cpu_sync_awaddr ),
+ .s_axi_awlen ( cpu_sync_awlen[3:0] ),
+ .s_axi_awsize ( cpu_sync_awsize ),
+ .s_axi_awburst ( cpu_sync_awburst ),
+ .s_axi_awlock ( cpu_sync_awlock ),
+ .s_axi_awcache ( cpu_sync_awcache ),
+ .s_axi_awprot ( cpu_sync_awprot ),
+ .s_axi_awqos ( 4'd0 ),
+ .s_axi_awvalid ( cpu_sync_awvalid ),
+ .s_axi_awready ( cpu_sync_awready ),
+ .s_axi_wid ( cpu_sync_wid ),
+ .s_axi_wdata ( cpu_sync_wdata ),
+ .s_axi_wstrb ( cpu_sync_wstrb ),
+ .s_axi_wlast ( cpu_sync_wlast ),
+ .s_axi_wvalid ( cpu_sync_wvalid ),
+ .s_axi_wready ( cpu_sync_wready ),
+ .s_axi_bid ( cpu_sync_bid ),
+ .s_axi_bresp ( cpu_sync_bresp ),
+ .s_axi_bvalid ( cpu_sync_bvalid ),
+ .s_axi_bready ( cpu_sync_bready ),
+
+ .m_axi_arid ( {ram_arid ,conf_arid } ),
+ .m_axi_araddr ( {ram_araddr ,conf_araddr } ),
+ .m_axi_arlen ( {ram_arlen ,conf_arlen } ),
+ .m_axi_arsize ( {ram_arsize ,conf_arsize } ),
+ .m_axi_arburst ( {ram_arburst,conf_arburst} ),
+ .m_axi_arlock ( {ram_arlock ,conf_arlock } ),
+ .m_axi_arcache ( {ram_arcache,conf_arcache} ),
+ .m_axi_arprot ( {ram_arprot ,conf_arprot } ),
+ .m_axi_arqos ( ),
+ .m_axi_arvalid ( {ram_arvalid,conf_arvalid} ),
+ .m_axi_arready ( {ram_arready,conf_arready} ),
+ .m_axi_rid ( {ram_rid ,conf_rid } ),
+ .m_axi_rdata ( {ram_rdata ,conf_rdata } ),
+ .m_axi_rresp ( {ram_rresp ,conf_rresp } ),
+ .m_axi_rlast ( {ram_rlast ,conf_rlast } ),
+ .m_axi_rvalid ( {ram_rvalid ,conf_rvalid } ),
+ .m_axi_rready ( {ram_rready ,conf_rready } ),
+ .m_axi_awid ( {ram_awid ,conf_awid } ),
+ .m_axi_awaddr ( {ram_awaddr ,conf_awaddr } ),
+ .m_axi_awlen ( {ram_awlen ,conf_awlen } ),
+ .m_axi_awsize ( {ram_awsize ,conf_awsize } ),
+ .m_axi_awburst ( {ram_awburst,conf_awburst} ),
+ .m_axi_awlock ( {ram_awlock ,conf_awlock } ),
+ .m_axi_awcache ( {ram_awcache,conf_awcache} ),
+ .m_axi_awprot ( {ram_awprot ,conf_awprot } ),
+ .m_axi_awqos ( ),
+ .m_axi_awvalid ( {ram_awvalid,conf_awvalid} ),
+ .m_axi_awready ( {ram_awready,conf_awready} ),
+ .m_axi_wid ( {ram_wid ,conf_wid } ),
+ .m_axi_wdata ( {ram_wdata ,conf_wdata } ),
+ .m_axi_wstrb ( {ram_wstrb ,conf_wstrb } ),
+ .m_axi_wlast ( {ram_wlast ,conf_wlast } ),
+ .m_axi_wvalid ( {ram_wvalid ,conf_wvalid } ),
+ .m_axi_wready ( {ram_wready ,conf_wready } ),
+ .m_axi_bid ( {ram_bid ,conf_bid } ),
+ .m_axi_bresp ( {ram_bresp ,conf_bresp } ),
+ .m_axi_bvalid ( {ram_bvalid ,conf_bvalid } ),
+ .m_axi_bready ( {ram_bready ,conf_bready } )
+
+ );
+
+//axi ram
+axi_wrap_ram u_axi_ram
+(
+ .aclk ( sys_clk ),
+ .aresetn ( sys_resetn ),
+ //ar
+ .axi_arid ( ram_arid ),
+ .axi_araddr ( ram_araddr ),
+ .axi_arlen ( {4'd0,ram_arlen} ),
+ .axi_arsize ( ram_arsize ),
+ .axi_arburst ( ram_arburst ),
+ .axi_arlock ( ram_arlock ),
+ .axi_arcache ( ram_arcache ),
+ .axi_arprot ( ram_arprot ),
+ .axi_arvalid ( ram_arvalid ),
+ .axi_arready ( ram_arready ),
+ //r
+ .axi_rid ( ram_rid ),
+ .axi_rdata ( ram_rdata ),
+ .axi_rresp ( ram_rresp ),
+ .axi_rlast ( ram_rlast ),
+ .axi_rvalid ( ram_rvalid ),
+ .axi_rready ( ram_rready ),
+ //aw
+ .axi_awid ( ram_awid ),
+ .axi_awaddr ( ram_awaddr ),
+ .axi_awlen ( {4'd0,ram_awlen[3:0]} ),
+ .axi_awsize ( ram_awsize ),
+ .axi_awburst ( ram_awburst ),
+ .axi_awlock ( ram_awlock ),
+ .axi_awcache ( ram_awcache ),
+ .axi_awprot ( ram_awprot ),
+ .axi_awvalid ( ram_awvalid ),
+ .axi_awready ( ram_awready ),
+ //w
+ .axi_wid ( ram_wid ),
+ .axi_wdata ( ram_wdata ),
+ .axi_wstrb ( ram_wstrb ),
+ .axi_wlast ( ram_wlast ),
+ .axi_wvalid ( ram_wvalid ),
+ .axi_wready ( ram_wready ),
+ //b ram
+ .axi_bid ( ram_bid ),
+ .axi_bresp ( ram_bresp ),
+ .axi_bvalid ( ram_bvalid ),
+ .axi_bready ( ram_bready ),
+
+ //random mask
+ .ram_random_mask ( ram_random_mask )
+);
+
+//confreg
+confreg #(.SIMULATION(SIMULATION)) u_confreg
+(
+ .timer_clk ( sys_clk ), // i, 1
+ .aclk ( sys_clk ), // i, 1
+ .aresetn ( sys_resetn ), // i, 1
+
+ .arid (conf_arid ),
+ .araddr (conf_araddr ),
+ .arlen (conf_arlen ),
+ .arsize (conf_arsize ),
+ .arburst (conf_arburst ),
+ .arlock (conf_arlock ),
+ .arcache (conf_arcache ),
+ .arprot (conf_arprot ),
+ .arvalid (conf_arvalid ),
+ .arready (conf_arready ),
+ .rid (conf_rid ),
+ .rdata (conf_rdata ),
+ .rresp (conf_rresp ),
+ .rlast (conf_rlast ),
+ .rvalid (conf_rvalid ),
+ .rready (conf_rready ),
+ .awid (conf_awid ),
+ .awaddr (conf_awaddr ),
+ .awlen (conf_awlen ),
+ .awsize (conf_awsize ),
+ .awburst (conf_awburst ),
+ .awlock (conf_awlock ),
+ .awcache (conf_awcache ),
+ .awprot (conf_awprot ),
+ .awvalid (conf_awvalid ),
+ .awready (conf_awready ),
+ .wid (conf_wid ),
+ .wdata (conf_wdata ),
+ .wstrb (conf_wstrb ),
+ .wlast (conf_wlast ),
+ .wvalid (conf_wvalid ),
+ .wready (conf_wready ),
+ .bid (conf_bid ),
+ .bresp (conf_bresp ),
+ .bvalid (conf_bvalid ),
+ .bready (conf_bready ),
+
+ .ram_random_mask ( ram_random_mask ),
+ .led ( led ), // o, 16
+ .led_rg0 ( led_rg0 ), // o, 2
+ .led_rg1 ( led_rg1 ), // o, 2
+ .num_csn ( num_csn ), // o, 8
+ .num_a_g ( num_a_g ), // o, 7
+ .switch ( switch ), // i, 8
+ .btn_key_col ( btn_key_col), // o, 4
+ .btn_key_row ( btn_key_row), // i, 4
+ .btn_step ( btn_step ) // i, 2
+);
+
+endmodule
+
diff --git a/src/testbench/MMU/test_MMU.sv b/src/testbench/MMU/test_MMU.sv
index cfe44eb..3020a6e 100644
--- a/src/testbench/MMU/test_MMU.sv
+++ b/src/testbench/MMU/test_MMU.sv
@@ -71,102 +71,129 @@ module test_MMU ();
.s_aresetn(~rst)
);
- ICache_i ic();
- sramro_i inst();
- sram_i data();
- SRAM_RO_AXI_i inst_axi();
+ ICache_i ic ();
+ DCache_i dc ();
+ sramro_i inst ();
+ sram_i data ();
+ SRAM_RO_AXI_i inst_axi ();
AXIRead_i fake_axi_read ();
- AXIWrite_i fake_axi_write();
- SRAM_RO_AXI_i data_rdata();
- SRAM_W_AXI_i data_wdata();
+ AXIWrite_i fake_axi_write ();
+ SRAM_RO_AXI_i data_rdata ();
+ SRAM_W_AXI_i data_wdata ();
- assign fake_axi_read.AXIReadData.arready = arready;
- assign fake_axi_read.AXIReadData.rid = rid;
- assign fake_axi_read.AXIReadData.rdata = rdata;
- assign fake_axi_read.AXIReadData.rresp = rresp;
- assign fake_axi_read.AXIReadData.rlast = rlast;
- assign fake_axi_read.AXIReadData.rvalid = rvalid;
+ assign fake_axi_read.AXIReadData.arready = arready;
+ assign fake_axi_read.AXIReadData.rid = rid;
+ assign fake_axi_read.AXIReadData.rdata = rdata;
+ assign fake_axi_read.AXIReadData.rresp = rresp;
+ assign fake_axi_read.AXIReadData.rlast = rlast;
+ assign fake_axi_read.AXIReadData.rvalid = rvalid;
- assign arid = fake_axi_read.AXIReadAddr.arid;
- assign araddr = fake_axi_read.AXIReadAddr.araddr;
- assign arlen[3:0] = fake_axi_read.AXIReadAddr.arlen;
- assign arlen[7:4] = 0;
- assign arsize = fake_axi_read.AXIReadAddr.arsize;
- assign arburst = fake_axi_read.AXIReadAddr.arburst;
- assign arvalid = fake_axi_read.AXIReadAddr.arvalid;
- assign rready = fake_axi_read.AXIReadAddr.rready;
+ assign arid = fake_axi_read.AXIReadAddr.arid;
+ assign araddr = fake_axi_read.AXIReadAddr.araddr;
+ assign arlen[3:0] = fake_axi_read.AXIReadAddr.arlen;
+ assign arlen[7:4] = 0;
+ assign arsize = fake_axi_read.AXIReadAddr.arsize;
+ assign arburst = fake_axi_read.AXIReadAddr.arburst;
+ assign arvalid = fake_axi_read.AXIReadAddr.arvalid;
+ assign rready = fake_axi_read.AXIReadAddr.rready;
+ assign fake_axi_write.AXIWriteData.awready = awready;
+ assign fake_axi_write.AXIWriteData.wready = wready;
+ assign fake_axi_write.AXIWriteData.bid = bid;
+ assign fake_axi_write.AXIWriteData.bresp = bresp;
+ assign fake_axi_write.AXIWriteData.bvalid = bvalid;
- AXI axi(
- .clk(clk),
- .rst(rst),
- .AXIRead(fake_axi_read.master),
- .AXIWrite(fake_axi_write.master),
- .inst(inst_axi.slave),
- .rdata(data_rdata.slave),
- .wdata(data_wdata.slave)
+ assign awid = fake_axi_write.AXIWriteAddr.awid;
+ assign awaddr = fake_axi_write.AXIWriteAddr.awaddr;
+ assign awlen[3:0] = fake_axi_write.AXIWriteAddr.awlen;
+ assign awlen[7:4] = 0;
+ assign awsize = fake_axi_write.AXIWriteAddr.awsize;
+ assign awburst = fake_axi_write.AXIWriteAddr.awburst;
+ assign awlock = fake_axi_write.AXIWriteAddr.awlock;
+ assign awcache = fake_axi_write.AXIWriteAddr.awcache;
+ assign awprot = fake_axi_write.AXIWriteAddr.awprot;
+ assign awvalid = fake_axi_write.AXIWriteAddr.awvalid;
+ assign wid = fake_axi_write.AXIWriteAddr.wid;
+ assign wdata = fake_axi_write.AXIWriteAddr.wdata;
+ assign wstrb = fake_axi_write.AXIWriteAddr.wstrb;
+ assign wlast = fake_axi_write.AXIWriteAddr.wlast;
+ assign wvalid = fake_axi_write.AXIWriteAddr.wvalid;
+ assign bready = fake_axi_write.AXIWriteAddr.bready;
+
+ AXI axi (
+ .clk(clk),
+ .rst(rst),
+ .AXIRead(fake_axi_read.master),
+ .AXIWrite(fake_axi_write.master),
+ .inst(inst_axi.slave),
+ .rdata(data_rdata.slave),
+ .wdata(data_wdata.master)
);
- assign data_rdata.req = 0;
- assign data_wdata.req = 0;
-
-
- MMU mmu(
- .clk(clk),
- .rst(rst),
- .K0(2'b11),
- .ic(ic.mmu),
- .inst(inst.slave),
- .data(data.slave),
- .inst_axi(inst_axi.master)
+ MMU mmu (
+ .clk(clk),
+ .rst(rst),
+ .K0(2'b11),
+ .ic(ic.mmu),
+ .dc(dc.mmu),
+ .inst(inst.slave),
+ .data(data.slave),
+ .inst_axi(inst_axi.master),
+ .rdata_axi(data_rdata.master),
+ .wdata_axi(data_wdata.slave)
);
- assign data.req = 0;
-
- ICache icache(
- .clk(clk),
- .rst(rst),
- .port(ic.cache)
+ ICache icache (
+ .clk (clk),
+ .rst (rst),
+ .port(ic.cache)
);
+ DCache dcache (
+ .clk (clk),
+ .rst (rst),
+ .port(dc.cache)
+ );
- reg [29:0] addr, queue[$];
- reg cached;
- reg [29:0] cacheAddrOffset = 'h2000_0000;
+ typedef struct packed {
+ logic req;
+ word_t addr;
+ } iq_t;
- assign inst.req = 1;
- assign inst.addr = {addr[29:1], 3'b0};
- always @(posedge clk) begin
- cached = ~cached; // one cached and one uncached kuseg <-> kseg0
+ typedef struct packed {
+ logic req;
+ logic wr;
+ word_t addr;
+ logic [3:0] wstrb;
+ word_t wdata;
+ } dq_t;
- // next addr
- if (inst.addr_ok) begin
- // tmp.coe have 4096 rows of data
- if (cached) addr = addr < 4095 ? addr + cacheAddrOffset + 1 : cacheAddrOffset;
- else addr = (addr - cacheAddrOffset) < 4095 ? (addr - cacheAddrOffset) + 1 : 0;
- queue.push_back(addr);
- end else addr = addr;
-
- // post pipeline
- if (inst.data_ok) begin
- reg [11:0] front;
- front = queue.pop_front();
- if (inst.rdata0 != (front & 'hFFFF_FFFE) && inst.rdata1 != (front & 'hFFFF_FFFE) + 1) begin
- $display("ERROR OCCURED! addr=0x%8h, rdata0=0x%8h, rdata1=0x%8h", (front << 2),
- inst.rdata0, inst.rdata1);
- end
- end
-
- end
+ iq_t iqueue[$];
+ dq_t dqueue[$];
+ integer counter;
+ `define C_B 32'h8000_0000
+ `define U_B 32'h0000_0000
initial begin
$dumpfile("dump.vcd");
$dumpvars();
- cached = 1;
- addr = 0;
- queue.push_back(addr);
+ // req wr addr wstrb wdata
+ dqueue.push_back({1'b1, 1'b1, `C_B | 32'd0, 4'b1111, 32'h12345678});
+ dqueue.push_back({1'b1, 1'b1, `C_B | 32'd0, 4'b1100, 32'hABCDEFAB});
+ dqueue.push_back({1'b1, 1'b0, `C_B | 32'd0, 4'b1111, 32'h12345678});
+ dqueue.push_back({1'b1, 1'b0, `C_B | 32'd0, 4'b0011, 32'hABCDEFAB});
+ dqueue.push_back({1'b1, 1'b1, `U_B | 32'd0, 4'b1111, 32'hABCDEFAB});
+ dqueue.push_back({1'b1, 1'b0, `U_B | 32'd0, 4'b1111, 32'hABCDEFAB});
+
+ // req, addr
+ iqueue.push_back({1'b0, `C_B + 0});
+ iqueue.push_back({1'b0, `C_B + 0});
+ iqueue.push_back({1'b0, `C_B + 0});
+ iqueue.push_back({1'b0, `U_B + 0});
+ iqueue.push_back({1'b0, `U_B + 0});
+ iqueue.push_back({1'b0, `U_B + 0});
rst = 1;
#5;
@@ -180,4 +207,22 @@ module test_MMU ();
end
end
+ always_ff @(posedge clk) begin
+ if (rst) begin
+ counter = 0;
+ {inst.req, inst.addr} = 0;
+ {data.req, data.wr, data.addr, data.wstrb, data.wdata} = 0;
+ end else begin
+ if (inst.addr_ok & iqueue.size() > 0) begin
+ {inst.req, inst.addr} = iqueue.pop_front();
+ $display("[%d]inst: %d 0x%h", counter, inst.req, inst.addr);
+ end
+ if (data.addr_ok & dqueue.size() > 0)
+ {data.req, data.wr, data.addr, data.wstrb, data.wdata} = dqueue.pop_front();
+ $display("[%d]data: %d %d 0x%h 0x%h 0x%h", counter, data.req, data.wr, data.addr, data.wstrb, data.wdata);
+ end
+
+ counter = counter + 1;
+
+ end
endmodule
diff --git a/src/testbench/happy/cache_tagd_bram.sv b/src/testbench/happy/cache_tagd_bram.sv
new file mode 100644
index 0000000..aaf8db8
--- /dev/null
+++ b/src/testbench/happy/cache_tagd_bram.sv
@@ -0,0 +1,26 @@
+// Make Linter Happy
+
+`include "ICache.svh"
+`include "sram.svh"
+
+module cache_tagd_bram (
+ input [5:0] addra,
+ input clka,
+ input [`IC_TAG_LENGTH+1-1:0] dina,
+ output [`IC_TAG_LENGTH+1-1:0] douta,
+ input wea
+);
+ logic [`IC_TAG_LENGTH+1-1:0] tmp;
+ assign douta = tmp;
+
+ initial begin
+ tmp = 0;
+ end
+
+ always_ff @(posedge clka) begin
+ tmp <= {{(`IC_TAG_LENGTH+1 - 6) {1'b0}}, addra};
+ end
+endmodule
+
+
+
diff --git a/src/testbench/happy/happy.sv b/src/testbench/happy/happy.sv
index 689160e..eabdaf6 100644
--- a/src/testbench/happy/happy.sv
+++ b/src/testbench/happy/happy.sv
@@ -5,7 +5,7 @@
`include "AXI.svh"
module happy ();
- logic clk, rst;
+ logic clk, rst;
wire [31:0] araddr;
wire [1:0] arburst;
@@ -36,72 +36,128 @@ module happy ();
wire [3:0] wstrb;
wire wvalid;
- AXIRead_i fake_axi ();
- AXIWrite_i fake_axi_w ();
- sramro_i fake_sram ();
- sram_i fake_sram2 ();
- HandShake fake_hs ();
- SRAM_RO_AXI_i fake_ic ();
- SRAM_W_AXI_i fake_dc ();
- ICache_i fake_ici ();
- DCache_i fake_dci ();
-
- wire [31:0] ICacheAddress;
- wire ICacheLineOK;
- wire [`IC_DATA_LENGTH-1:0] ICacheLine;
-
- ICache ic (
- .clk (clk),
- .rst (rst),
- .port(fake_ici.cache)
+ blk_mem_gen_0 memory (
+ .s_axi_araddr(araddr),
+ .s_axi_arburst(arburst),
+ .s_axi_arid(arid),
+ .s_axi_arlen(arlen),
+ .s_axi_arready(arready),
+ .s_axi_arsize(arsize),
+ .s_axi_arvalid(arvalid),
+ .s_axi_awaddr(awaddr),
+ .s_axi_awburst(awburst),
+ .s_axi_awid(awid),
+ .s_axi_awlen(awlen),
+ .s_axi_awready(awready),
+ .s_axi_awsize(awsize),
+ .s_axi_awvalid(awvalid),
+ .s_axi_bid(bid),
+ .s_axi_bready(bready),
+ .s_axi_bresp(bresp),
+ .s_axi_bvalid(bvalid),
+ .s_axi_rdata(rdata),
+ .s_axi_rid(rid),
+ .s_axi_rlast(rlast),
+ .s_axi_rready(rready),
+ .s_axi_rresp(rresp),
+ .s_axi_rvalid(rvalid),
+ .s_axi_wdata(wdata),
+ .s_axi_wlast(wlast),
+ .s_axi_wready(wready),
+ .s_axi_wstrb(wstrb),
+ .s_axi_wvalid(wvalid),
+ .s_aclk(clk),
+ .s_aresetn(~rst)
);
- DCache dc (
- .clk (clk),
- .rst (rst),
- .port(fake_dci.cache)
- );
+ ICache_i ic ();
+ DCache_i dc ();
+ sramro_i inst ();
+ sram_i data ();
+ SRAM_RO_AXI_i inst_axi ();
+ AXIRead_i fake_axi_read ();
+ AXIWrite_i fake_axi_write ();
+ SRAM_RO_AXI_i data_rdata ();
+ SRAM_W_AXI_i data_wdata ();
- AXI AXI (
+ assign fake_axi_read.AXIReadData.arready = arready;
+ assign fake_axi_read.AXIReadData.rid = rid;
+ assign fake_axi_read.AXIReadData.rdata = rdata;
+ assign fake_axi_read.AXIReadData.rresp = rresp;
+ assign fake_axi_read.AXIReadData.rlast = rlast;
+ assign fake_axi_read.AXIReadData.rvalid = rvalid;
+
+ assign arid = fake_axi_read.AXIReadAddr.arid;
+ assign araddr = fake_axi_read.AXIReadAddr.araddr;
+ assign arlen[3:0] = fake_axi_read.AXIReadAddr.arlen;
+ assign arlen[7:4] = 0;
+ assign arsize = fake_axi_read.AXIReadAddr.arsize;
+ assign arburst = fake_axi_read.AXIReadAddr.arburst;
+ assign arvalid = fake_axi_read.AXIReadAddr.arvalid;
+ assign rready = fake_axi_read.AXIReadAddr.rready;
+
+ assign fake_axi_write.AXIWriteData.awready = awready;
+ assign fake_axi_write.AXIWriteData.wready = wready;
+ assign fake_axi_write.AXIWriteData.bid = bid;
+ assign fake_axi_write.AXIWriteData.bresp = bresp;
+ assign fake_axi_write.AXIWriteData.bvalid = bvalid;
+
+ assign awid = fake_axi_write.AXIWriteAddr.awid;
+ assign awaddr = fake_axi_write.AXIWriteAddr.awaddr;
+ assign awlen[3:0] = fake_axi_write.AXIWriteAddr.awlen;
+ assign awlen[7:4] = 0;
+ assign awsize = fake_axi_write.AXIWriteAddr.awsize;
+ assign awburst = fake_axi_write.AXIWriteAddr.awburst;
+ assign awlock = fake_axi_write.AXIWriteAddr.awlock;
+ assign awcache = fake_axi_write.AXIWriteAddr.awcache;
+ assign awport = fake_axi_write.AXIWriteAddr.awport;
+ assign awvalid = fake_axi_write.AXIWriteAddr.awvalid;
+ assign wid = fake_axi_write.AXIWriteAddr.wid;
+ assign wdata = fake_axi_write.AXIWriteAddr.wdata;
+ assign wstrb = fake_axi_write.AXIWriteAddr.wstrb;
+ assign wlast = fake_axi_write.AXIWriteAddr.wlast;
+ assign wvalid = fake_axi_write.AXIWriteAddr.wvalid;
+ assign bready = fake_axi_write.AXIWriteAddr.bready;
+
+ AXI axi (
.clk(clk),
.rst(rst),
- .AXIRead(fake_axi.master),
- .AXIWrite(fake_axi_w.master),
- .inst(fake_ic),
- .rdata(fake_ic),
- .wdata(fake_dc)
+ .AXIRead(fake_axi_read.master),
+ .AXIWrite(fake_axi_write.master),
+ .inst(inst_axi.slave),
+ .rdata(data_rdata.slave),
+ .wdata(data_wdata.master)
);
- assign fake_axi.AXIReadData.arready = arready;
- assign fake_axi.AXIReadData.rid = rid;
- assign fake_axi.AXIReadData.rdata = rdata;
- assign fake_axi.AXIReadData.rresp = rresp;
- assign fake_axi.AXIReadData.rlast = rlast;
- assign fake_axi.AXIReadData.rvalid = rvalid;
-
- assign arid = fake_axi.AXIReadAddr.arid;
- assign araddr = fake_axi.AXIReadAddr.araddr;
- assign arlen[3:0] = fake_axi.AXIReadAddr.arlen;
- assign arlen[7:4] = 0;
- assign arsize = fake_axi.AXIReadAddr.arsize;
- assign arburst = fake_axi.AXIReadAddr.arburst;
- assign arvalid = fake_axi.AXIReadAddr.arvalid;
- assign rready = fake_axi.AXIReadAddr.rready;
-
MMU mmu (
- clk, rst,
- 2'b00,
- fake_ici.mmu,
- // fake_dci.mmu,
- fake_sram.slave,
- fake_sram2.slave,
- fake_ic.master
-);
+ .clk(clk),
+ .rst(rst),
+ .K0(2'b11),
+ .ic(ic.mmu),
+ .dc(dc.mmu),
+ .inst(inst.slave),
+ .data(data.slave),
+ .inst_axi(inst_axi.master),
+ .rdata_axi(data_rdata.master),
+ .wdata_axi(data_wdata.slave)
+ );
+
+ ICache icache (
+ .clk (clk),
+ .rst (rst),
+ .port(ic.cache)
+ );
+
+ DCache dcache (
+ .clk (clk),
+ .rst (rst),
+ .port(dc.cache)
+ );
Issue issue (
.clk(clk),
.rst(rst),
- .fetch_i(fake_sram)
+ .fetch_i(inst)
);
HandShake fake_hs1 ();