Update InstrQueue.sv
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@ -41,7 +41,7 @@ readygo to valid
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1out: out1<-instr1 instr1<-instr2 instr2<-instr3 instr3<-in1
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2out: out1<-instr1 out2<-instr2 instr1<-instr3 instr3<-instr4 instr4<-in1
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æ— ç›´é€?
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无直通
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0:
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0out: instr1<-in1, instr2<-in2
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1out: instr1<-in1, instr2<-in2
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@ -65,18 +65,20 @@ readygo to valid
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*/
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parameter DEPTH = 2, MAX_COUNT = 2'b11;
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word_t di1, di2, di3, di4, qi1, qi2, qi3, qi4;
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logic dv1, dv2, dv3, dv4, qv1, qv2, qv3, qv4;
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word_t dp1, dp2, dp3, dp4, qp1, qp2, qp3, qp4;
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// wire [5:0] judge = {qv4, qv3, qv2, qv1, HandShake_out1.allowin, HandShake_out2.allowin};
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wire word_t di1, di2, di3, di4, qi1, qi2, qi3, qi4;
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wire logic dv1, dv2, dv3, dv4, qv1, qv2, qv3, qv4;
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wire word_t dp1, dp2, dp3, dp4, qp1, qp2, qp3, qp4;
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wire logic en1, en2, en3, en4;
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wire logic [5:0] judge = {qv4, qv3, qv2, qv1, HandShake_out1.allowin, HandShake_out2.allowin};
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// ffen #(6) ffj (
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// clk,
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// {qv4, qv3, qv2, qv1, HandShake_out1.allowin, HandShake_out2.allowin},
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// 1'b1,
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// judge
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// );
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logic [5:0] judge;
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always_ff @(negedge clk) judge <= {qv4, qv3, qv2, qv1, HandShake_out1.allowin, HandShake_out2.allowin};
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// logic [5:0] judge;
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// always_ff @(negedge clk) judge <= {qv4, qv3, qv2, qv1, HandShake_out1.allowin, HandShake_out2.allowin};
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assign HandShake_out1.readygo = judge[1] & judge[2];
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assign HandShake_out2.readygo = judge[0] & judge[3];
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assign out1 = qi1;
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