Update InstrQueue.sv
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Hooo1941
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@ -1,5 +1,4 @@
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`include "defines.svh"
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module InstrQueue (
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input logic clk,
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input logic rst,
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@ -41,7 +40,7 @@ readygo to valid
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1out: out1<-instr1 instr1<-instr2 instr2<-instr3 instr3<-in1
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2out: out1<-instr1 out2<-instr2 instr1<-instr3 instr3<-instr4 instr4<-in1
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æ— ç›´é€?
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无直<EFBFBD>?
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0:
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0out: instr1<-in1, instr2<-in2
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1out: instr1<-in1, instr2<-in2
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@ -67,130 +66,179 @@ readygo to valid
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parameter DEPTH = 2, MAX_COUNT = 2'b11;
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word_t di1, di2, di3, di4, qi1, qi2, qi3, qi4;
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logic dv1, dv2, dv3, dv4, qv1, qv2, qv3, qv4;
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logic en1, en2, en3, en4;
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word_t dp1, dp2, dp3, dp4, qp1, qp2, qp3, qp4;
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// wire [5:0] judge = {qv4, qv3, qv2, qv1, HandShake_out1.allowin, HandShake_out2.allowin};
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// ffen #(6) ffj (
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// clk,
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// {qv4, qv3, qv2, qv1, HandShake_out1.allowin, HandShake_out2.allowin},
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// 1'b1,
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// judge
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// );
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logic [5:0] judge;
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always_ff @(negedge clk) judge <= {qv4, qv3, qv2, qv1, HandShake_out1.allowin, HandShake_out2.allowin};
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wire [5:0] judge = {qv4, qv3, qv2, qv1, HandShake_out1.allowin, HandShake_out2.allowin};
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assign HandShake_out1.readygo = judge[1] & judge[2];
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assign HandShake_out2.readygo = judge[0] & judge[3];
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assign out1 = qi1;
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assign out2 = qi2;
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assign out1 = qi1;
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assign out2 = qi2;
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assign pout1 = qp1;
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assign pout2 = qp2;
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assign HandShake_in1.allowin = ~judge[5] | judge[1];
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assign HandShake_in2.allowin = (~judge[4] | judge[1] & (~judge[5] | judge[0]));
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assign en1 = ~judge[2] | judge[1];
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assign en2 = ~judge[3] | judge[1];
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assign en3 = (~judge[3] & ~judge[1] & judge[2] | judge[3] & (~judge[1] & ~judge[4] | judge[1] & (~judge[4] & ~judge[0] | judge[4])));
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assign en4 = (~judge[4] & judge[3] & ~judge[1] | judge[4] & (~judge[1] & ~judge[5] | judge[1] & (~judge[5] & ~judge[0] | judge[5])));
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always_ff @(posedge clk) begin
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if (rst) begin
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{qv1, qv2, qv3, qv4} = 4'b0;
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end else begin
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HandShake_in1.allowin = ~judge[5] | judge[1];
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HandShake_in2.allowin = (~judge[4] | judge[1] & (~judge[5] | judge[0]));
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en1 = ~judge[2] | judge[1];
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en2 = ~judge[3] | judge[1];
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en3 = (~judge[3] & ~judge[1] & judge[2] | judge[3] & (~judge[1] & ~judge[4] | judge[1] & (~judge[4] & ~judge[0] | judge[4])));
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en4 = (~judge[4] & judge[3] & ~judge[1] | judge[4] & (~judge[1] & ~judge[5] | judge[1] & (~judge[5] & ~judge[0] | judge[5])));
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di4 = (judge[4] & ~judge[0] & (~judge[1] | judge[5])) ? in1 : in2;
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dv4 = ((judge[4] & ~judge[0] & (~judge[1] | judge[5])) ? HandShake_in1.readygo : HandShake_in2.readygo);
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dp4 = (judge[4] & ~judge[0] & (~judge[1] | judge[5])) ? pin1 : pin2;
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if (judge[3] & ~judge[0]) {di1, dv1, dp1} = {qi2, qv2, qp2};
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else if (judge[3] & judge[0] & judge[4]) {di1, dv1, dp1} = {qi3, qv3, qp3};
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mux3 #(65) mux3_d1 (
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{in1, HandShake_in1.readygo, pin1},
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{qi3, qv3, qp3},
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{qi2, qv2, qp2},
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(judge[3] & ~judge[0]) ? 2'b10 : ((judge[3] & judge[0] & judge[4]) ? 2'b01 : 2'b00),
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{di1, dv1, dp1}
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);
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mux4 #(65) mux4_d2 (
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{in2, HandShake_in2.readygo, pin2},
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{in1, HandShake_in1.readygo, pin1},
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{qi4, qv4, qp4},
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{qi3, qv3, qp3},
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(judge[4] & ~judge[0]) ? 2'b11 : ((judge[4] & judge[0] & judge[5]) ? 2'b10 : ((~judge[4] & (~judge[2] | (~judge[3] & judge[1] | judge[0]))) ? 2'b00 : 2'b01)),
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{di2, dv2, dp2}
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);
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mux3 #(65) mux3_d3 (
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{in1, HandShake_in1.readygo, pin1},
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{in2, HandShake_in2.readygo, pin2},
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{qi4, qv4, qp4},
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(judge[5] & ~judge[0]) ? 2'b10 : ((~judge[5] & (~judge[3] | ~judge[4] & judge[1] | judge[0])) ? 2'b01 : 2'b00),
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{di3, dv3, dp3}
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);
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assign di4 = (judge[4] & ~judge[0] & (~judge[1] | judge[5])) ? in1 : in2;
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assign dv4 = ((judge[4] & ~judge[0] & (~judge[1] | judge[5])) ? HandShake_in1.readygo : HandShake_in2.readygo);
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assign dp4 = (judge[4] & ~judge[0] & (~judge[1] | judge[5])) ? pin1 : pin2;
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else {di1, dv1, dp1} = {in1, HandShake_in1.readygo, pin1};
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if (judge[4] & ~judge[0]) {di2, dv2, dp2} = {qi3, qv3, qp3};
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else if (judge[4] & judge[0] & judge[5]) {di2, dv2, dp2} = {qi4, qv4, qp4};
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else if (~judge[4] & (~judge[2] | (~judge[3] & judge[1] | judge[0])))
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{di2, dv2, dp2} = {in2, HandShake_in2.readygo, pin2};
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else {di2, dv2, dp2} = {in1, HandShake_in1.readygo, pin1};
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ffen #(32) pc1 (
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clk,
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dp1,
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en1,
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qp1
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);
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ffen #(32) pc2 (
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clk,
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dp2,
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en2,
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qp2
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);
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ffen #(32) pc3 (
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clk,
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dp3,
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en3,
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qp3
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);
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ffen #(32) pc4 (
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clk,
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dp4,
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en4,
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qp4
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);
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ffen #(32) instr1 (
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clk,
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di1,
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en1,
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qi1
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);
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ffen #(32) instr2 (
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clk,
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di2,
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en2,
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qi2
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);
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ffen #(32) instr3 (
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clk,
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di3,
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en3,
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qi3
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);
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ffen #(32) instr4 (
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clk,
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di4,
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en4,
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qi4
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);
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ffenr #(1) valid1 (
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clk,
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rst,
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dv1,
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en1,
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qv1
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);
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ffenr #(1) valid2 (
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clk,
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rst,
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dv2,
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en2,
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qv2
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);
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ffenr #(1) valid3 (
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clk,
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rst,
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dv3,
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en3,
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qv3
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);
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ffenr #(1) valid4 (
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clk,
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rst,
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dv4,
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en4,
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qv4
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);
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if (judge[5] & ~judge[0]) {di3, dv3, dp3} = {qi4, qv4, qp4};
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else if (~judge[5] & (~judge[3] | ~judge[4] & judge[1] | judge[0]))
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{di3, dv3, dp3} = {in2, HandShake_in2.readygo, pin2};
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else {di3, dv3, dp3} = {in1, HandShake_in1.readygo, pin1};
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di4 = (judge[4] & ~judge[0] & (~judge[1] | judge[5])) ? in1 : in2;
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dv4 = ((judge[4] & ~judge[0] & (~judge[1] | judge[5])) ? HandShake_in1.readygo : HandShake_in2.readygo);
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dp4 = (judge[4] & ~judge[0] & (~judge[1] | judge[5])) ? pin1 : pin2;
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if (en1) begin
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qi1 = di1;
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qv1 = dv1;
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qp1 = dp1;
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end
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if (en2) begin
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qi2 = di2;
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qv2 = dv2;
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qp2 = dp2;
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end
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if (en3) begin
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qi3 = di3;
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qv3 = dv3;
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qp3 = dp3;
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end
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if (en4) begin
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qi4 = di4;
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qv4 = dv4;
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qp4 = dp4;
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end
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end
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end
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//assign HandShake_out1.readygo = judge[1] & judge[2];
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//assign HandShake_out2.readygo = judge[0] & judge[3];
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//assign HandShake_in1.allowin = ~judge[5] | judge[1];
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//assign HandShake_in2.allowin = (~judge[4] | judge[1] & (~judge[5] | judge[0]));
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//assign en1 = ~judge[2] | judge[1];
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//assign en2 = ~judge[3] | judge[1];
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//assign en3 = (~judge[3] & ~judge[1] & judge[2] | judge[3] & (~judge[1] & ~judge[4] | judge[1] & (~judge[4] & ~judge[0] | judge[4])));
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//assign en4 = (~judge[4] & judge[3] & ~judge[1] | judge[4] & (~judge[1] & ~judge[5] | judge[1] & (~judge[5] & ~judge[0] | judge[5])));
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// mux3 #(65) mux3_d1 (
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// {in1, HandShake_in1.readygo, pin1},
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// {qi3, qv3, qp3},
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// {qi2, qv2, qp2},
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// (judge[3] & ~judge[0]) ? 2'b10 : ((judge[3] & judge[0] & judge[4]) ? 2'b01 : 2'b00),
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// {di1, dv1, dp1}
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// );
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// mux4 #(65) mux4_d2 (
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// {in2, HandShake_in2.readygo, pin2},
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// {in1, HandShake_in1.readygo, pin1},
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// {qi4, qv4, qp4},
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// {qi3, qv3, qp3},
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// (judge[4] & ~judge[0]) ? 2'b11 : ((judge[4] & judge[0] & judge[5]) ? 2'b10 : ((~judge[4] & (~judge[2] | (~judge[3] & judge[1] | judge[0]))) ? 2'b00 : 2'b01)),
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// {di2, dv2, dp2}
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// );
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// mux3 #(65) mux3_d3 (
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// {in1, HandShake_in1.readygo, pin1},
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// {in2, HandShake_in2.readygo, pin2},
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// {qi4, qv4, qp4},
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// (judge[5] & ~judge[0]) ? 2'b10 : ((~judge[5] & (~judge[3] | ~judge[4] & judge[1] | judge[0])) ? 2'b01 : 2'b00),
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// {di3, dv3, dp3}
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// );
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// assign di4 = (judge[4] & ~judge[0] & (~judge[1] | judge[5])) ? in1 : in2;
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// assign dv4 = ((judge[4] & ~judge[0] & (~judge[1] | judge[5])) ? HandShake_in1.readygo : HandShake_in2.readygo);
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// assign dp4 = (judge[4] & ~judge[0] & (~judge[1] | judge[5])) ? pin1 : pin2;
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// ffen #(32) pc1 (
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// clk,
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// dp1,
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// en1,
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// qp1
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// );
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// ffen #(32) pc2 (
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// clk,
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// dp2,
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// en2,
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// qp2
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// );
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// ffen #(32) pc3 (
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// clk,
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// dp3,
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// en3,
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// qp3
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// );
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// ffen #(32) pc4 (
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// clk,
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// dp4,
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// en4,
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// qp4
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// );
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// ffen #(32) instr1 (
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// clk,
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// di1,
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// en1,
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// qi1
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// );
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// ffen #(32) instr2 (
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// clk,
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// di2,
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// en2,
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// qi2
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// );
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// ffen #(32) instr3 (
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// clk,
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// di3,
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// en3,
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// qi3
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// );
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// ffen #(32) instr4 (
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// clk,
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// di4,
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// en4,
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// qi4
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// );
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// ffenr #(1) valid1 (
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// clk,
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// rst,
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// dv1,
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// en1,
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// qv1
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// );
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// ffenr #(1) valid2 (
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// clk,
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// rst,
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// dv2,
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// en2,
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// qv2
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// );
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// ffenr #(1) valid3 (
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// clk,
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// rst,
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// dv3,
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// en3,
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// qv3
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// );
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// ffenr #(1) valid4 (
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// clk,
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// rst,
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// dv4,
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// en4,
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// qv4
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// );
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endmodule
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