From a2f8fdae9b03ad8286dcdc8ce7225ca6cdd74735 Mon Sep 17 00:00:00 2001 From: Paul Pan Date: Thu, 14 Oct 2021 22:31:25 +0800 Subject: [PATCH] clean up --- .vscode/c_cpp_properties.json | 18 - .vscode/settings.json | 71 - README.md | 64 +- model/DCData_bram.v | 17 - model/DCTag_bram.v | 17 - model/ICData_bram.v | 16 - model/ICTag_bram.v | 17 - model/div_signed.v | 30 - model/div_unsigned.v | 30 - model/mul_signed.sv | 22 - model/mul_unsigned.sv | 22 - resources/soc/rtl/AMBA/axi2apb.v | 542 - resources/soc/rtl/AMBA/axi_mux.v | 1102 - resources/soc/rtl/APB_DEV/NAND/nand.v | 1430 - resources/soc/rtl/APB_DEV/URT/raminfr.v | 62 - resources/soc/rtl/APB_DEV/URT/uart_defines.h | 119 - resources/soc/rtl/APB_DEV/URT/uart_receiver.v | 288 - resources/soc/rtl/APB_DEV/URT/uart_regs.v | 711 - resources/soc/rtl/APB_DEV/URT/uart_rfifo.v | 193 - .../soc/rtl/APB_DEV/URT/uart_sync_flops.v | 76 - resources/soc/rtl/APB_DEV/URT/uart_tfifo.v | 129 - resources/soc/rtl/APB_DEV/URT/uart_top.v | 107 - .../soc/rtl/APB_DEV/URT/uart_transmitter.v | 281 - resources/soc/rtl/APB_DEV/apb_dev_top.v | 416 - resources/soc/rtl/APB_DEV/apb_mux2.v | 203 - resources/soc/rtl/APB_DEV/nand_module.v | 140 - resources/soc/rtl/CONFREG/confreg.v | 695 - resources/soc/rtl/DMA/dma.v | 778 - resources/soc/rtl/MAC/bd.v | 372 - resources/soc/rtl/MAC/csr.v | 2530 -- resources/soc/rtl/MAC/dma.v | 646 - resources/soc/rtl/MAC/ethernet_top.v | 368 - resources/soc/rtl/MAC/mac.v | 862 - resources/soc/rtl/MAC/mac2axi.v | 355 - resources/soc/rtl/MAC/mac_axi.v | 522 - resources/soc/rtl/MAC/mac_top.v | 445 - resources/soc/rtl/MAC/maccsr2axi.v | 291 - resources/soc/rtl/MAC/macdata2axi.v | 248 - resources/soc/rtl/MAC/rc.v | 1749 -- resources/soc/rtl/MAC/rfifo.v | 439 - resources/soc/rtl/MAC/rlsm.v | 1328 - resources/soc/rtl/MAC/rstc.v | 158 - resources/soc/rtl/MAC/tc.v | 1296 - resources/soc/rtl/MAC/tfifo.v | 815 - resources/soc/rtl/MAC/tlsm.v | 2197 -- resources/soc/rtl/MAC/utility.v | 282 - resources/soc/rtl/SPI/godson_sbridge_spi.v | 896 - resources/soc/rtl/TOP/config.h | 98 - resources/soc/rtl/TOP/soc_up_top.v | 1493 -- ...理器gs232源码，目前缺少，请联系龙芯开源获得.txt | 7 - resources/soc/simu/run/run_func/lib.list | 82 - resources/soc/simu/run/run_func/ncompile | 3 - resources/soc/simu/run/run_func/rtl.list | 117 - resources/soc/simu/run/run_func/run.f | 28 - resources/soc/simu/run/run_func/sys.list | 11 - resources/soc/simu/soft/func/Makefile | 48 - resources/soc/simu/soft/func/config.h | 179 - resources/soc/simu/soft/func/convert.c | 29 - .../soc/simu/soft/func/include/Calendar.h | 12 - .../soc/simu/soft/func/include/Infrare.h | 1 - .../soc/simu/soft/func/include/Interrupt.h | 9 - .../soc/simu/soft/func/include/MonthData.h | 23 - .../soc/simu/soft/func/include/SystemInit.h | 4 - resources/soc/simu/soft/func/include/adc.h | 2 - .../simu/soft/func/include/asm/interrupt.h | 287 - .../soc/simu/soft/func/include/asm/mipsregs.h | 38 - .../soc/simu/soft/func/include/asm/ns16550.h | 135 - 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resources/soc/simu/soft/func/lib/putchar.c | 5 - resources/soc/simu/soft/func/lib/puts.c | 13 - resources/soc/simu/soft/func/lib/strcat.c | 48 - resources/soc/simu/soft/func/lib/strchr.c | 44 - resources/soc/simu/soft/func/lib/strcmp.c | 11 - resources/soc/simu/soft/func/lib/strcspn.c | 48 - resources/soc/simu/soft/func/lib/strspn.c | 51 - resources/soc/simu/soft/func/lib/strtok.c | 51 - resources/soc/simu/soft/func/lib/udelay.c | 13 - resources/soc/simu/soft/func/main.c | 7 - resources/soc/simu/soft/func/nand_test.S | 284 - .../soc/simu/soft/func/source/Calendar.c | 154 - resources/soc/simu/soft/func/source/Infrare.c | 33 - .../soc/simu/soft/func/source/Interrupt.c | 6 - .../soc/simu/soft/func/source/MonthData.c | 62 - .../soc/simu/soft/func/source/SystemInit.c | 118 - resources/soc/simu/soft/func/source/adc.c | 49 - resources/soc/simu/soft/func/source/battery.c | 148 - resources/soc/simu/soft/func/source/cmdline.c | 326 - resources/soc/simu/soft/func/source/common.c | 125 - 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resources/soc/simu/testbench/vmac/mac_top.v | 13548 ---------- resources/soc/simu/testbench/vmac/ram.vlog | 22018 ---------------- .../soc/simu/testbench/vmac/virtual_mac.v | 406 - .../project_1/project_1/project_1.xpr | 1154 - .../axi_interconnect_0/axi_interconnect_0.xci | 1520 -- .../xilinx_ip/clk_pll_33/clk_pll_33.xci | 716 - .../xilinx_ip/clk_wiz_0/clk_wiz_0.xci | 716 - .../xilinx_ip/dpram_512x32/dpram_512x32.xci | 315 - .../project_1/xilinx_ip/mig_axi_32/mig_a.prj | 131 - .../xilinx_ip/mig_axi_32/mig_axi_32.xci | 2647 -- .../project_1/xilinx_ip/mig_axi_32/mig_b.prj | 131 - .../xilinx_ip/sram_128x22/sram_128x22.xci | 309 - .../xilinx_ip/sram_128x32/sram_128x32.xci | 309 - .../xilinx_ip/sram_128x64/sram_128x64.xci | 311 - .../xilinx_ip/sram_32x52bit/sram_32x52bit.xci | 309 - resources/soc/vivado_xpr/soc_up.xdc | 200 - resources/tft-lcd/LCD.sv | 28 - sim/.gitignore | 2 - sim/Makefile | 60 - sim/sim_main.cpp | 47 - 146 files changed, 6 insertions(+), 90462 deletions(-) delete mode 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100644 index 6c78102..0000000 --- a/.vscode/c_cpp_properties.json +++ /dev/null @@ -1,18 +0,0 @@ -{ - "configurations": [ - { - "name": "Linux", - "includePath": [ - "${workspaceFolder}/**", - "${workspaceFolder}/sim/obj_dir", - "/usr/share/verilator/include" - ], - "defines": [], - "compilerPath": "/usr/sbin/clang", - "cStandard": "c17", - "cppStandard": "c++14", - "intelliSenseMode": "linux-clang-x64" - } - ], - "version": 4 -} \ No newline at end of file diff --git a/.vscode/settings.json b/.vscode/settings.json deleted file mode 100644 index 7630cf2..0000000 --- a/.vscode/settings.json +++ /dev/null @@ -1,71 +0,0 @@ -{ - "files.associations": { - "cctype": "cpp", - "clocale": "cpp", - "cmath": "cpp", - "cstdarg": "cpp", - "cstddef": "cpp", - "cstdio": "cpp", - "cstdlib": "cpp", - "cstring": "cpp", - "ctime": "cpp", - "cwchar": "cpp", - "cwctype": "cpp", - "array": "cpp", - "atomic": "cpp", - "bit": "cpp", - "*.tcc": "cpp", - "bitset": "cpp", - "chrono": "cpp", - "compare": "cpp", - "concepts": "cpp", - "condition_variable": "cpp", - "cstdint": "cpp", - "deque": "cpp", - "list": "cpp", - "map": "cpp", - "set": "cpp", - "string": "cpp", - "unordered_map": "cpp", - "unordered_set": "cpp", - "vector": "cpp", - "exception": "cpp", - "algorithm": "cpp", - "functional": "cpp", - "iterator": "cpp", - "memory": "cpp", - "memory_resource": "cpp", - "numeric": "cpp", - "random": "cpp", - "ratio": "cpp", - "string_view": "cpp", - "system_error": "cpp", - "tuple": "cpp", - "type_traits": "cpp", - "utility": "cpp", - "fstream": "cpp", - "initializer_list": "cpp", - "iosfwd": "cpp", - "iostream": "cpp", - "istream": "cpp", - "limits": "cpp", - "mutex": "cpp", - "new": "cpp", - "numbers": "cpp", - "ostream": "cpp", - "semaphore": "cpp", - "sstream": "cpp", - "stdexcept": "cpp", - "stop_token": "cpp", - "streambuf": "cpp", - "thread": "cpp", - "cinttypes": "cpp", - "typeinfo": "cpp", - "iomanip": "cpp" - }, - "editor.defaultFormatter": "bmpenuelas.systemverilog-formatter-vscode", - "verilog.linting.linter": "verilator", - "verilog.linting.verilator.useWSL": true, - "verilog.linting.verilator.arguments": "-x-assign 0 -Wall --assert -Wno-UNOPT -Wno-UNOPTFLAT -Wno-BLKSEQ -DSIMULATION_PC -I./src/AXI/ -I./src/Cache/ -I./src/Core/ -I./src/CP0/ -I./src/Gadgets/ -I./src/include/ -I./src/IP/ -I./src/MMU/ -I./src/Core/Gadgets/ -I./src/IP/DCData_bram/ -I./src/IP/DCTag_bram/ -I./src/IP/div_signed/ -I./src/IP/div_unsigned/ -I./src/IP/ICData_bram/ -I./src/IP/ICTag_bram/ -I./src/IP/mul_signed/ -I./src/IP/mul_unsigned/ ./model/DCData_bram.v ./model/DCTag_bram.v ./model/div_signed.v ./model/div_unsigned.v ./model/ICData_bram.v ./model/ICTag_bram.v ./model/mul_signed.sv ./model/mul_unsigned.sv ./src/mycpu_top.sv ./src/AXI/AXIRead_i.sv ./src/AXI/AXI.sv ./src/AXI/AXIWrite_i.sv ./src/Cache/DCache_i.sv ./src/Cache/DCache.sv ./src/Cache/ICache_i.sv ./src/Cache/ICache.sv ./src/Core/ALU.sv ./src/Core/Controller.sv ./src/Core/Datapath.sv ./src/Core/Queue.sv ./src/Core/RF.sv ./src/CP0/CP0.sv ./src/Gadgets/extender.sv ./src/Gadgets/ffenrc.sv ./src/Gadgets/ffenr.sv ./src/Gadgets/ffen.sv ./src/Gadgets/mux2.sv ./src/Gadgets/mux3.sv ./src/Gadgets/mux4.sv ./src/Gadgets/mux5.sv ./src/Gadgets/mux6.sv ./src/Gadgets/myBuffer0.sv ./src/Gadgets/myBuffer.sv ./src/Gadgets/onehot_bin16.sv ./src/Gadgets/onehot_bin32.sv ./src/Gadgets/onehot_bin4.sv ./src/Gadgets/onehot_bin8.sv ./src/Gadgets/prio_mux4.sv ./src/Gadgets/prio_mux5.sv ./src/MMU/MMU.sv ./src/MMU/sram_i.sv ./src/MMU/SRAM_RO_AXI_i.sv ./src/MMU/sramro_i.sv ./src/MMU/SRAM_W_AXI_i.sv ./src/MMU/TLB_Lookup.sv ./src/MMU/TLB.sv -top mycpu_top", - "files.trimTrailingWhitespace": true -} diff --git a/README.md b/README.md index 8182e82..95b9b90 100644 --- a/README.md +++ b/README.md @@ -1,74 +1,22 @@ Magically Improved Pipeline Stages === -Our awesome `MIPS` CPU written in `SystemVerilog` for Loongson Cup +Our awesome `MIPS` CPU written in `SystemVerilog` for Loongson Cup 2021 ``` . -├── model <-- IP行为模型 -├── resources <-- 资源包 +├── resources <-- 资源 +│ ├── 2021 <-- 2021 资源包 +│ ├── ping-pong-mips32 <-- 决赛项目 ping pong +│ └── system_top <-- 决赛项目 ping pong 用的外围顶层 ├── src <-- CPU设计代码 │ ├── AXI <-- AXI总线交互 │ ├── Cache <-- Cache │ ├── Core <-- CPU核心 +│ ├── CP0 <-- CP0 协处理器 │ ├── Gadgets <-- 小部件 -│ ├── CP0 <-- CP0协处理器 │ ├── include <-- 头文件 │ ├── IP <-- 用到的IP │ └── MMU <-- 地址转换单元 └── tools <-- 控制信号生成器 ``` - -## Progress - -- [x] 特权模式 - - [x] `CP0`寄存器`Status.UM` :heavy_check_mark: - - [x] 访存异常(考虑`in_kernel`状态切换带来的冒险) :heavy_check_mark: - - [x] 特权指令异常 :heavy_check_mark: -- [ ] 浮点运算单元 - - [ ] ~~做一个真的`FPU`~~ :x: - - [ ] 浮点运算指令报`Coprocessor Unusable`，同时`CP0`中新增`Cause.CE` :clock3: -- [x] 新增指令 -- [ ] `Cache`指令修正 - - [x] 完善 Test Cases - - [ ] 重新阻止流水线结构 （`TLB`转换） - -## `Cache`指令 - -预计实现以下`7`条操作 - -```verilog -32'b101111?????00000???????????????? // I-Cache Index Invalid -32'b101111?????01000???????????????? // I-Cache Index Store Tag -32'b101111?????10000???????????????? // I-Cache Hit Invalid -32'b101111?????00001???????????????? // D-Cache Index Writeback Invalid -32'b101111?????01001???????????????? // D-Cache Index Store Tag -32'b101111?????10001???????????????? // D-Cache Hit Invalid -32'b101111?????10101???????????????? // D-Cache Hit Writeback Invalid -``` - -其中，`Index Store Tag`中使用到了`TagLo`和`TagHi`寄存器。考虑到地址最多`32`位，故不实现`TagHi`寄存器(恒`0`)；同时，由于`TagLo`和`TagHi`寄存器定义与具体处理器实现相关，在应用上用于将`Cache`的`Tag`清零（可以魔改内核），故也不实现`TagLo`寄存器(恒`0`)。所以`Index Store Tag`指令在实现上变为不写回的`Index Invalid` - -对于上述操作，具体实现： - -``` -Cache -> VIPT -Index Invalid : VA -> Index -> (Write Back) -> Write Zero -Index Store Tag : VA -> Index -> Write Zero -Hit Invalid : VA -> Lookup -> Hit? -> Write Zero -Hit Writeback Invalid : VA -> Lookup -> Hit? -> (Write Back) -> Write Zero -``` - -控制信号： - -| `CacheOp[2]` | `CacheOp[1]` | `CacheOp[0]` | Name | -| :------------------------: | :---------------------: | :----------------------------: | :---: | -| 0 | 0 | 0 | `NOP` | -| 0 | 0 | 1 | | -| 0 | 1 | ? | | -| 1 | 0 | 0 | | -| 1 | 0 | 1 | | -| 1 | 1 | 0 | | -| 1 | 1 | 1 | | -| `I-Cache(0) or D-Cache(1)` | `Lookup(0) or Index(1)` | `WriteBack(0) or WriteOnly(1)` | | - diff --git a/model/DCData_bram.v b/model/DCData_bram.v deleted file mode 100644 index 0c69fff..0000000 --- a/model/DCData_bram.v +++ /dev/null @@ -1,17 +0,0 @@ -module DCData_bram ( - input [ 6:0] addra, - input clka, - input [127:0] dina, - output reg [127:0] douta, - input wea -); - - reg [127:0] ram [0:127]; - always @(posedge clka) begin - if(wea) begin - ram[addra] <= dina; - end - douta <= ~wea ? ram[addra] : {4{$random}}; - end - -endmodule diff --git a/model/DCTag_bram.v b/model/DCTag_bram.v deleted file mode 100644 index d3e148d..0000000 --- a/model/DCTag_bram.v +++ /dev/null @@ -1,17 +0,0 @@ -module DCTag_bram ( - input [ 6:0] addra, - input clka, - input [22:0] dina, - output reg [22:0] douta, - input wea -); - - reg [22:0] ram [0:127]; - always @(posedge clka) begin - if(wea) begin - ram[addra] <= dina; - end - douta <= ~wea ? ram[addra] : {$random}[22:0]; - end - -endmodule diff --git a/model/ICData_bram.v b/model/ICData_bram.v deleted file mode 100644 index bea4730..0000000 --- a/model/ICData_bram.v +++ /dev/null @@ -1,16 +0,0 @@ -module ICData_bram ( - input [ 5:0] addra, - input clka, - input [255:0] dina, - output reg [255:0] douta, - input wea -); - reg [255:0] ram [0:63]; - always @(posedge clka) begin - if(wea) begin - ram[addra] <= dina; - end - douta <= ~wea ? ram[addra] : {8{$random}}; - end - -endmodule diff --git a/model/ICTag_bram.v b/model/ICTag_bram.v deleted file mode 100644 index c9cc324..0000000 --- a/model/ICTag_bram.v +++ /dev/null @@ -1,17 +0,0 @@ -module ICTag_bram ( - input [ 5:0] addra, - input clka, - input [21:0] dina, - output reg [21:0] douta, - input wea -); - - reg [21:0] ram [0:63]; - always @(posedge clka) begin - if(wea) begin - ram[addra] <= dina; - end - douta <= ~wea ? ram[addra] : {$random}[21:0]; - end - -endmodule diff --git a/model/div_signed.v b/model/div_signed.v deleted file mode 100644 index 2e3ec9c..0000000 --- a/model/div_signed.v +++ /dev/null @@ -1,30 +0,0 @@ -module div_signed( - input aclk, - input s_axis_dividend_tvalid, - input [31:0] s_axis_dividend_tdata, - input s_axis_divisor_tvalid, - input [31:0] s_axis_divisor_tdata, - output m_axis_dout_tvalid, - output [63:0] m_axis_dout_tdata -); - - reg valid, nxtValid; - reg [63:0] data, nxtData; - - assign m_axis_dout_tvalid = nxtValid; - assign m_axis_dout_tdata = nxtData; - - always @(posedge aclk) begin - nxtValid <= valid; - nxtData <= data; - if (s_axis_dividend_tvalid & s_axis_divisor_tvalid) begin - valid <= 1'b1; - data <= { - $signed(s_axis_divisor_tdata) % $signed(s_axis_dividend_tdata), - $signed(s_axis_divisor_tdata) / $signed(s_axis_dividend_tdata) - }; - end - end - - -endmodule diff --git a/model/div_unsigned.v b/model/div_unsigned.v deleted file mode 100644 index c434387..0000000 --- a/model/div_unsigned.v +++ /dev/null @@ -1,30 +0,0 @@ -module div_unsigned( - input aclk, - input s_axis_dividend_tvalid, - input [31:0] s_axis_dividend_tdata, - input s_axis_divisor_tvalid, - input [31:0] s_axis_divisor_tdata, - output m_axis_dout_tvalid, - output [63:0] m_axis_dout_tdata -); - - reg valid, nxtValid; - reg [63:0] data, nxtData; - - assign m_axis_dout_tvalid = nxtValid; - assign m_axis_dout_tdata = nxtData; - - always @(posedge aclk) begin - nxtValid <= valid; - nxtData <= data; - if (s_axis_dividend_tvalid & s_axis_divisor_tvalid) begin - valid <= 1'b1; - data <= { - $unsigned(s_axis_divisor_tdata) % $unsigned(s_axis_dividend_tdata), - $unsigned(s_axis_divisor_tdata) / $unsigned(s_axis_dividend_tdata) - }; - end - end - - -endmodule diff --git a/model/mul_signed.sv b/model/mul_signed.sv deleted file mode 100644 index 388871a..0000000 --- a/model/mul_signed.sv +++ /dev/null @@ -1,22 +0,0 @@ -`include "defines.svh" - -module mul_signed( - input logic CLK, - input word_t A, - input word_t B, - output logic [63:0] P -); - - word_t A1, A2, A3, A4, A5, A6; - word_t B1, B2, B3, B4, B5, B6; - - ffen #(64) ff_1 (CLK, { A, B}, 1'b1, {A1, B1}); - ffen #(64) ff_2 (CLK, {A1, B1}, 1'b1, {A2, B2}); - ffen #(64) ff_3 (CLK, {A2, B2}, 1'b1, {A3, B3}); - ffen #(64) ff_4 (CLK, {A3, B3}, 1'b1, {A4, B4}); - ffen #(64) ff_5 (CLK, {A4, B4}, 1'b1, {A5, B5}); - ffen #(64) ff_6 (CLK, {A5, B5}, 1'b1, {A6, B6}); - - assign P = $signed(A) * $signed(B); - -endmodule diff --git a/model/mul_unsigned.sv b/model/mul_unsigned.sv deleted file mode 100644 index 5a062ef..0000000 --- a/model/mul_unsigned.sv +++ /dev/null @@ -1,22 +0,0 @@ -`include "defines.svh" - -module mul_unsigned( - input logic CLK, - input word_t A, - input word_t B, - output logic [63:0] P -); - - word_t A1, A2, A3, A4, A5, A6; - word_t B1, B2, B3, B4, B5, B6; - - ffen #(64) ff_1 (CLK, { A, B}, 1'b1, {A1, B1}); - ffen #(64) ff_2 (CLK, {A1, B1}, 1'b1, {A2, B2}); - ffen #(64) ff_3 (CLK, {A2, B2}, 1'b1, {A3, B3}); - ffen #(64) ff_4 (CLK, {A3, B3}, 1'b1, {A4, B4}); - ffen #(64) ff_5 (CLK, {A4, B4}, 1'b1, {A5, B5}); - ffen #(64) ff_6 (CLK, {A5, B5}, 1'b1, {A6, B6}); - - assign P = $unsigned(A) * $unsigned(B); - -endmodule diff --git a/resources/soc/rtl/AMBA/axi2apb.v b/resources/soc/rtl/AMBA/axi2apb.v deleted file mode 100644 index 79c32a6..0000000 --- a/resources/soc/rtl/AMBA/axi2apb.v +++ /dev/null @@ -1,542 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -`include "config.h" - -module axi2apb_bridge( -clk, -rst_n, -axi_s_awid, -axi_s_awaddr, -axi_s_awlen, -axi_s_awsize, -axi_s_awburst, -axi_s_awlock, -axi_s_awcache, -axi_s_awprot, -axi_s_awvalid, -axi_s_awready, -axi_s_wid, -axi_s_wdata, -axi_s_wstrb, -axi_s_wlast, -axi_s_wvalid, -axi_s_wready, -axi_s_bid, -axi_s_bresp, -axi_s_bvalid, -axi_s_bready, -axi_s_arid, -axi_s_araddr, -axi_s_arlen, -axi_s_arsize, -axi_s_arburst, -axi_s_arlock, -axi_s_arcache, -axi_s_arprot, -axi_s_arvalid, -axi_s_arready, -axi_s_rid, -axi_s_rdata, -axi_s_rresp, -axi_s_rlast, -axi_s_rvalid, -axi_s_rready, - -apb_valid_cpu, -cpu_grant, -apb_word_trans, -apb_high_24b_rd, -apb_high_24b_wr, -apb_clk, -apb_reset_n, -reg_psel, -reg_enable, -reg_rw, -reg_addr, -reg_datai, -reg_ready_1, -reg_datao -); -parameter L_ADDR_APB = 20; - -input clk; -input rst_n; - -input [`LID -1 :0] axi_s_awid; -input [`Lawaddr -1 :0] axi_s_awaddr; -input [`Lawlen -1 :0] axi_s_awlen; -input [`Lawsize -1 :0] axi_s_awsize; -input [`Lawburst -1 :0] axi_s_awburst; -input [`Lawlock -1 :0] axi_s_awlock; -input [`Lawcache -1 :0] axi_s_awcache; -input [`Lawprot -1 :0] axi_s_awprot; -input axi_s_awvalid; -output axi_s_awready; -input [`LID -1 :0] axi_s_wid; -input [`Lwdata -1 :0] axi_s_wdata; -input [`Lwstrb -1 :0] axi_s_wstrb; -input axi_s_wlast; -input axi_s_wvalid; -output axi_s_wready; -output [`LID -1 :0] axi_s_bid; -output [`Lbresp -1 :0] axi_s_bresp; -output axi_s_bvalid; -input axi_s_bready; -input [`LID -1 :0] axi_s_arid; -input [`Laraddr -1 :0] axi_s_araddr; -input [`Larlen -1 :0] axi_s_arlen; -input [`Larsize -1 :0] axi_s_arsize; -input [`Larburst -1 :0] axi_s_arburst; -input [`Larlock -1 :0] axi_s_arlock; -input [`Larcache -1 :0] axi_s_arcache; -input [`Larprot -1 :0] axi_s_arprot; -input axi_s_arvalid; -output axi_s_arready; -output [`LID -1 :0] axi_s_rid; -output [`Lrdata -1 :0] axi_s_rdata; -output [`Lrresp -1 :0] axi_s_rresp; -output axi_s_rlast; -output axi_s_rvalid; -input axi_s_rready; -input apb_word_trans; -input cpu_grant; -output apb_valid_cpu; -input [23:0] apb_high_24b_rd; -output [23:0] apb_high_24b_wr; -output apb_clk; -output apb_reset_n; -output reg_psel; -output reg_enable; -output reg_rw; -output[L_ADDR_APB-1:0] reg_addr; -output[7:0] reg_datai; -input [7:0] reg_datao; -input reg_ready_1; - -wire csr_rw_send_axi_rsp_done; -wire reg_ready; - -parameter CSR_RW_SM_IDLE = 4'b0001, - CSR_RW_SM_GET_AXI_ADDR = 4'b0010, - CSR_RW_SM_SEND_AXI_RSP = 4'b1000; - -reg reg_psel; -reg reg_enable; -reg axi_s_sel_rd; -reg axi_s_sel_wr; -reg[3:0] csr_rw_sm; -reg[3:0] csr_rw_sm_nxt; -reg[L_ADDR_APB-1:0] axi_s_req_addr; -reg[`LID-1:0] axi_s_w_id; -reg[`LID-1:0] axi_s_r_id; -reg[23:0] apb_high_24b_wr; - -assign apb_clk = clk; -assign apb_reset_n = rst_n; -assign reg_rw = axi_s_sel_wr; -assign reg_addr = axi_s_req_addr; -assign reg_ready = reg_enable & reg_ready_1; -assign apb_valid_cpu = axi_s_sel_wr | axi_s_sel_rd | axi_s_awvalid | axi_s_arvalid; -reg axi_s_rlast; -reg axi_s_rvalid; -reg axi_s_wready; -reg axi_s_awready; -reg axi_s_arready; - -reg [1:0]axi_s_rstrb; -reg [3:0]apb_s_wstrb; -reg [31:0]reg_datai_32; -reg [31:0]reg_datao_32; -reg [2:0] rd_count; -reg [2:0] apb_rd_size; -reg [2:0] apb_wr_size; -reg [7:0] reg_datai; -reg axi_s_bvalid; - -always@(posedge clk) -begin - if(!rst_n) - begin - reg_datai_32 <= 32'h0; - reg_datao_32 <= 32'h0; - axi_s_req_addr <= 20'h0; - apb_s_wstrb <= 4'b0; - axi_s_rstrb <= 2'b0; - axi_s_wready <= 1'b0; - reg_enable <= 1'b0; - reg_psel <= 1'b0; - rd_count <= 3'b0; - apb_rd_size <= 3'b0; - apb_wr_size <= 3'b0; - axi_s_rlast <= 1'b0; - axi_s_rvalid <= 1'b0; - reg_datai <= 8'b0; - axi_s_awready <= 1'b0; - axi_s_arready <= 1'b0; - axi_s_bvalid <= 1'b0; - axi_s_sel_wr <= 1'b0; - axi_s_sel_rd <= 1'b0; - axi_s_w_id <= 'h0; - axi_s_r_id <= 'h0; - apb_high_24b_wr <= 24'h0; - end - else begin - if(axi_s_awvalid & ~axi_s_bvalid & ~axi_s_sel_rd & (csr_rw_sm == CSR_RW_SM_IDLE) &cpu_grant) begin - axi_s_req_addr <= axi_s_awaddr[L_ADDR_APB-1:0]; - axi_s_awready <= 1'b1; - axi_s_sel_wr <= 1'b1; - apb_wr_size <= axi_s_awsize; - end - else if(axi_s_sel_wr) begin - axi_s_awready <= 1'b0; - if(axi_s_wvalid && ~axi_s_wready) begin - axi_s_req_addr <= (axi_s_wstrb[3:0]==4'h2)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h1): - (axi_s_wstrb[3:0]==4'h4)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h2): - (axi_s_wstrb[3:0]==4'h8)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h3): - (axi_s_wstrb[3:0]==4'h6)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h1): - (axi_s_wstrb[3:0]==4'hc)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h2): axi_s_req_addr ; - axi_s_wready <= 1'b1; - reg_psel <= 1'b0; - reg_enable <= 1'b0; - axi_s_w_id <= axi_s_wid; - case({axi_s_req_addr[1:0]}) - 2'b00: begin apb_s_wstrb <= axi_s_wstrb[3:0]; reg_datai_32 <=axi_s_wdata[31:0]; end - 2'b01: begin apb_s_wstrb <= {1'b0,axi_s_wstrb[3:1]}; reg_datai_32 <={8'h0,axi_s_wdata[31:8]}; end - 2'b10: begin apb_s_wstrb <= {2'b0,axi_s_wstrb[3:2]}; reg_datai_32 <={16'b0,axi_s_wdata[31:16]}; end - 2'b11: begin apb_s_wstrb <= {3'b0,axi_s_wstrb[3]}; reg_datai_32 <={24'b0,axi_s_wdata[31:24]}; end - default: begin apb_s_wstrb <= 4'b0; reg_datai_32 <=32'h0; end - endcase - end - else if((~reg_psel) && (apb_s_wstrb!=4'h0) ) begin - reg_psel <= 1'b1; - reg_enable <= 1'b0; - reg_datai <= (apb_s_wstrb == 4'h1) ? reg_datai_32[7:0]: - (apb_s_wstrb == 4'h2) ? reg_datai_32[15:8]: - (apb_s_wstrb == 4'h6) ? reg_datai_32[15:8]: - (apb_s_wstrb == 4'h4) ? reg_datai_32[23:16]: - (apb_s_wstrb == 4'h8) ? reg_datai_32[31:24]: reg_datai_32[7:0]; - apb_high_24b_wr <= reg_datai_32[31:8]; - if(axi_s_bready) axi_s_bvalid <= 1'b0; - end - else if(apb_word_trans & apb_s_wstrb==4'hf ) begin - if(~reg_ready)begin - reg_psel <= 1'b1; - reg_enable <= 1'b1; - end - else begin - reg_psel <= 1'b0; - reg_enable <= 1'b0; - axi_s_sel_wr <= 1'b0; - axi_s_bvalid <= 1'b1; - apb_s_wstrb <= 4'b0; - end - reg_datai <= reg_datai_32[7:0]; - apb_high_24b_wr <= reg_datai_32[31:8]; - axi_s_wready <= 1'b0; - end - else if(apb_s_wstrb[0]) begin - if(~reg_ready)begin - reg_psel <= 1'b1; - reg_enable <= 1'b1; - reg_datai <= reg_datai_32[7:0]; - end - else begin - if(apb_s_wstrb[3:1] ==3'b0) - begin - reg_psel <= 1'b0; - axi_s_sel_wr<= 1'b0; - axi_s_bvalid <= 1'b1; - end - else - reg_psel <= 1'b1; - reg_enable <= 1'b0; - apb_s_wstrb[0] <= 1'b0; - axi_s_req_addr <= axi_s_req_addr +1'b1; - reg_datai <= reg_datai_32[15:8]; - end - axi_s_wready <= 1'b0; - end - else if (apb_s_wstrb[1]) begin - if(~reg_ready)begin - reg_psel <= 1'b1; - reg_enable <= 1'b1; - end - else begin - if(apb_s_wstrb[3:2] ==2'b0) - begin - reg_psel <= 1'b0; - axi_s_sel_wr <= 1'b0; - axi_s_bvalid <= 1'b1; - end - else - reg_psel <= 1'b1; - reg_enable <= 1'b0; - apb_s_wstrb[1] <= 1'b0; - axi_s_req_addr <= axi_s_req_addr +1'b1; - reg_datai <= reg_datai_32[23:16]; - end - axi_s_wready <= 1'b0; - end - else if (apb_s_wstrb[2]) begin - if(~reg_ready)begin - reg_psel <= 1'b1; - reg_enable <= 1'b1; - end - else begin - if(apb_s_wstrb[3] ==1'b0) - begin - reg_psel <= 1'b0; - axi_s_sel_wr <= 1'b0; - axi_s_bvalid <= 1'b1; - end - else - reg_psel <= 1'b1; - reg_enable <= 1'b0; - apb_s_wstrb[2] <= 1'b0; - axi_s_req_addr <= axi_s_req_addr +1'b1; - reg_datai <= reg_datai_32[31:24]; - end - axi_s_wready <= 1'b0; - end - else if (apb_s_wstrb[3]) begin - if(~reg_ready)begin - reg_psel <= 1'b1; - reg_enable <= 1'b1; - end - else begin - reg_psel <= 1'b0; - reg_enable <= 1'b0; - axi_s_sel_wr <= 1'b0; - axi_s_bvalid <= 1'b1; - apb_s_wstrb[3] <= 1'b0; - end - axi_s_wready <= 1'b0; - end - else begin - reg_psel <= 1'b0; - reg_enable <= 1'b0; - reg_datai <= 8'h0; - apb_s_wstrb <= 4'h0; - axi_s_wready <= 1'b0; - if(csr_rw_sm == CSR_RW_SM_IDLE) axi_s_sel_wr <= 1'b0; - end - end - else if(axi_s_arvalid & ~axi_s_arready & ~axi_s_bvalid & (csr_rw_sm == CSR_RW_SM_IDLE)&cpu_grant) - begin - reg_enable <= 1'b0; - reg_psel <= 1'b1; - axi_s_arready <= 1'b1; - axi_s_sel_rd <= 1'b1; - axi_s_r_id <= axi_s_arid; - apb_rd_size <= axi_s_arsize; - axi_s_req_addr <= axi_s_araddr[L_ADDR_APB-1:0]; - axi_s_rstrb <= axi_s_araddr[1:0]; - if(axi_s_arsize==3'b010) - rd_count<= 3'h4; - else if(axi_s_arsize==3'b01) - rd_count<= 3'h2; - else if(axi_s_arsize==3'b0) - rd_count<= 3'h1; - end - else if(axi_s_sel_rd) - begin - axi_s_arready <= 1'b0; - if(apb_word_trans) - begin - if(reg_ready) - begin - reg_psel <= rd_count==3'b10; - reg_enable <= 1'b0; - rd_count <= rd_count-3'b1; - axi_s_rlast <= apb_rd_size==3'h2|rd_count==2'b1; - axi_s_rvalid <= apb_rd_size==3'h2|rd_count==2'b1; - axi_s_sel_rd <= rd_count==3'b10; - reg_datao_32 <= {apb_high_24b_rd,reg_datao}; - end - else begin - reg_psel <= 1'b1; - reg_enable <= 1'b1; - end - end - else if(rd_count==3'h4) - begin - if(reg_ready) - begin - reg_psel <= 1'b1; - reg_enable <= 1'b0; - rd_count <= rd_count-3'h1; - reg_datao_32[7:0] <= reg_datao; - axi_s_req_addr <= axi_s_req_addr +1'b1; - end - else begin - reg_psel <= 1'b1; - reg_enable <= 1'b1; - end - end - else if(rd_count==3'h3) - begin - if(reg_ready) - begin - reg_psel <= 1'b1; - reg_enable <= 1'b0; - rd_count <= rd_count-3'h1; - reg_datao_32[15:8] <= reg_datao; - axi_s_req_addr <= axi_s_req_addr +1'b1; - end - else begin - reg_psel <= 1'b1; - reg_enable <= 1'b1; - end - end - else if(rd_count==3'h2) - begin - if(reg_ready) - begin - reg_psel <= 1'b1; - reg_enable <= 1'b0; - rd_count <= rd_count-3'h1; - axi_s_req_addr <= axi_s_req_addr +1'b1; - if(apb_rd_size==3'h2 ) - reg_datao_32[23:16] <= reg_datao; - else if(apb_rd_size==3'h1) - reg_datao_32[7:0] <= reg_datao; - end - else begin - reg_psel <= 1'b1; - reg_enable <= 1'b1; - end - end - else if(rd_count==3'h1) - begin - if(reg_ready) - begin - reg_psel <= 1'b0; - reg_enable <= 1'b0; - axi_s_rlast <= 1'b1; - axi_s_rvalid <= 1'b1; - axi_s_sel_rd <= 1'b0; - if(apb_rd_size==3'h2 ) - reg_datao_32[31:24] <= reg_datao; - else if(apb_rd_size==3'h1) - reg_datao_32[15:8] <= reg_datao; - else if(apb_rd_size==3'h0) - reg_datao_32[7:0] <= reg_datao; - end - else begin - reg_psel <= 1'b1; - reg_enable <= 1'b1; - end - end// end if(rd_count) - else begin - axi_s_arready <= 1'b0; - axi_s_rlast <= 1'b1; - axi_s_rvalid <= 1'b1; - reg_psel <= 1'b0; - reg_enable <= 1'b0; - if(axi_s_rvalid && axi_s_rready) - begin - reg_datao_32 <= 32'h0; - axi_s_rlast <= 1'b0; - axi_s_rvalid <= 1'b0; - end - if(csr_rw_sm == CSR_RW_SM_IDLE) axi_s_sel_rd <= 1'b0; - if(axi_s_bready) axi_s_bvalid <= 1'b0; - end - end//end if(axi_s_sel_rd) - else begin - reg_psel <= 1'b0; - reg_enable <= 1'b0; - axi_s_sel_wr <= 1'b0; - axi_s_sel_rd <= 1'b0; - axi_s_wready <= 1'b0; - axi_s_arready <= 1'b0; - axi_s_req_addr <= 32'h0; - reg_datai_32 <= 32'h0; - if(axi_s_bready) axi_s_bvalid <= 1'b0; - if(axi_s_rvalid && axi_s_rready) - begin - reg_datao_32 <= 32'h0; - axi_s_rlast <= 1'b0; - axi_s_rvalid <= 1'b0; - end - end - end//end if(rst_n) -end//end always - -assign csr_rw_send_axi_rsp_done = csr_rw_sm == CSR_RW_SM_SEND_AXI_RSP && axi_s_rlast && axi_s_rready || axi_s_bvalid && axi_s_bready; - -assign axi_s_bid = axi_s_w_id; -assign axi_s_rid = axi_s_r_id; -assign axi_s_bresp = 2'b00; -assign axi_s_rresp = 2'b00; - -assign axi_s_rdata= ( axi_s_rstrb == 2'h0) ? { reg_datao_32 } : - ( axi_s_rstrb == 2'h1) ? {reg_datao_32[23:0], 8'h0} : - ( axi_s_rstrb == 2'h2) ? {reg_datao_32[15:0],16'h0} : - ( axi_s_rstrb == 2'h3) ? {reg_datao_32[7:0], 24'h0} : 32'h0; - -always@(csr_rw_sm or axi_s_awvalid or axi_s_arvalid or axi_s_sel_rd or axi_s_sel_wr or - axi_s_wready or csr_rw_send_axi_rsp_done or cpu_grant) begin - case(csr_rw_sm) - CSR_RW_SM_IDLE: - if((axi_s_awvalid || axi_s_arvalid)&&~(axi_s_sel_wr||axi_s_sel_rd)&cpu_grant) - csr_rw_sm_nxt = CSR_RW_SM_GET_AXI_ADDR; - else - csr_rw_sm_nxt = CSR_RW_SM_IDLE; - CSR_RW_SM_GET_AXI_ADDR: - if(axi_s_sel_wr) - csr_rw_sm_nxt = CSR_RW_SM_SEND_AXI_RSP; - else if(axi_s_sel_rd) - csr_rw_sm_nxt = CSR_RW_SM_SEND_AXI_RSP; - else - csr_rw_sm_nxt = CSR_RW_SM_GET_AXI_ADDR; - CSR_RW_SM_SEND_AXI_RSP: - if(csr_rw_send_axi_rsp_done) - csr_rw_sm_nxt = CSR_RW_SM_IDLE; - else - csr_rw_sm_nxt = CSR_RW_SM_SEND_AXI_RSP; - default: - csr_rw_sm_nxt = CSR_RW_SM_IDLE; - endcase -end - -always@(posedge clk) begin - if(!rst_n) - csr_rw_sm <= CSR_RW_SM_IDLE; - else - csr_rw_sm <= csr_rw_sm_nxt; -end - -endmodule - diff --git a/resources/soc/rtl/AMBA/axi_mux.v b/resources/soc/rtl/AMBA/axi_mux.v deleted file mode 100644 index 6e965f4..0000000 --- a/resources/soc/rtl/AMBA/axi_mux.v +++ /dev/null @@ -1,1102 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -`define SLV_MUX_5 -`define SLV_MUX_NUM 5 -`include "config.h" -module axi_slave_mux( -spi_boot, -axi_s_aclk, -axi_s_awid, -axi_s_awaddr, -axi_s_awlen, -axi_s_awsize, -axi_s_awburst, -axi_s_awlock, -axi_s_awcache, -axi_s_awprot, -axi_s_awvalid, -axi_s_awready, -axi_s_wready, -axi_s_wid, -axi_s_wdata, -axi_s_wstrb, -axi_s_wlast, -axi_s_wvalid, -axi_s_bid, -axi_s_bresp, -axi_s_bvalid, -axi_s_bready, -axi_s_arid, -axi_s_araddr, -axi_s_arlen, -axi_s_arsize, -axi_s_arburst, -axi_s_arlock, -axi_s_arcache, -axi_s_arprot, -axi_s_arvalid, -axi_s_arready, -axi_s_rready, -axi_s_rid, -axi_s_rdata, -axi_s_rresp, -axi_s_rlast, -axi_s_rvalid, - -s0_awid, -s0_awaddr, -s0_awlen, -s0_awsize, -s0_awburst, -s0_awlock, -s0_awcache, -s0_awprot, -s0_awvalid, -s0_awready, -s0_wid, -s0_wdata, -s0_wstrb, -s0_wlast, -s0_wvalid, -s0_wready, -s0_bid, -s0_bresp, -s0_bvalid, -s0_bready, -s0_arid, -s0_araddr, -s0_arlen, -s0_arsize, -s0_arburst, -s0_arlock, -s0_arcache, -s0_arprot, -s0_arvalid, -s0_arready, -s0_rid, -s0_rdata, -s0_rresp, -s0_rlast, -s0_rvalid, -s0_rready, - -s1_awid, -s1_awaddr, -s1_awlen, -s1_awsize, -s1_awburst, -s1_awlock, -s1_awcache, -s1_awprot, -s1_awvalid, -s1_awready, -s1_wid, -s1_wdata, -s1_wstrb, -s1_wlast, -s1_wvalid, -s1_wready, -s1_bid, -s1_bresp, -s1_bvalid, -s1_bready, -s1_arid, -s1_araddr, -s1_arlen, -s1_arsize, -s1_arburst, -s1_arlock, -s1_arcache, -s1_arprot, -s1_arvalid, -s1_arready, -s1_rid, -s1_rdata, -s1_rresp, -s1_rlast, -s1_rvalid, -s1_rready, - -s2_awid, -s2_awaddr, -s2_awlen, -s2_awsize, -s2_awburst, -s2_awlock, -s2_awcache, -s2_awprot, -s2_awvalid, -s2_awready, -s2_wid, -s2_wdata, -s2_wstrb, -s2_wlast, -s2_wvalid, -s2_wready, -s2_bid, -s2_bresp, -s2_bvalid, -s2_bready, -s2_arid, -s2_araddr, -s2_arlen, -s2_arsize, -s2_arburst, -s2_arlock, -s2_arcache, -s2_arprot, -s2_arvalid, -s2_arready, -s2_rid, -s2_rdata, -s2_rresp, -s2_rlast, -s2_rvalid, -s2_rready, -s3_awid, -s3_awaddr, -s3_awlen, -s3_awsize, -s3_awburst, -s3_awlock, -s3_awcache, -s3_awprot, -s3_awvalid, -s3_awready, -s3_wid, -s3_wdata, -s3_wstrb, -s3_wlast, -s3_wvalid, -s3_wready, -s3_bid, -s3_bresp, -s3_bvalid, -s3_bready, -s3_arid, -s3_araddr, -s3_arlen, -s3_arsize, -s3_arburst, -s3_arlock, -s3_arcache, -s3_arprot, -s3_arvalid, -s3_arready, -s3_rid, -s3_rdata, -s3_rresp, -s3_rlast, -s3_rvalid, -s3_rready, -s4_awid, -s4_awaddr, -s4_awlen, -s4_awsize, -s4_awburst, -s4_awlock, -s4_awcache, -s4_awprot, -s4_awvalid, -s4_awready, -s4_wid, -s4_wdata, -s4_wstrb, -s4_wlast, -s4_wvalid, -s4_wready, -s4_bid, -s4_bresp, -s4_bvalid, -s4_bready, -s4_arid, -s4_araddr, -s4_arlen, -s4_arsize, -s4_arburst, -s4_arlock, -s4_arcache, -s4_arprot, -s4_arvalid, -s4_arready, -s4_rid, -s4_rdata, -s4_rresp, -s4_rlast, -s4_rvalid, -s4_rready, - -axi_s_aresetn -); - -input spi_boot; -input axi_s_aclk; -input axi_s_aresetn; - -input [`LID -1 :0] axi_s_awid; -input [`Lawaddr -1 :0] axi_s_awaddr; -input [`Lawlen -1 :0] axi_s_awlen; -input [`Lawsize -1 :0] axi_s_awsize; -input [`Lawburst -1 :0] axi_s_awburst; -input [`Lawlock -1 :0] axi_s_awlock; -input [`Lawcache -1 :0] axi_s_awcache; -input [`Lawprot -1 :0] axi_s_awprot; -input axi_s_awvalid; -output axi_s_awready; -input [`LID -1 :0] axi_s_wid; -input [`Lwdata -1 :0] axi_s_wdata; -input [`Lwstrb -1 :0] axi_s_wstrb; -input axi_s_wlast; -input axi_s_wvalid; -output axi_s_wready; -output [`LID -1 :0] axi_s_bid; -output [`Lbresp -1 :0] axi_s_bresp; -output axi_s_bvalid; -input axi_s_bready; -input [`LID -1 :0] axi_s_arid; -input [`Laraddr -1 :0] axi_s_araddr; -input [`Larlen -1 :0] axi_s_arlen; -input [`Larsize -1 :0] axi_s_arsize; -input [`Larburst -1 :0] axi_s_arburst; -input [`Larlock -1 :0] axi_s_arlock; -input [`Larcache -1 :0] axi_s_arcache; -input [`Larprot -1 :0] axi_s_arprot; -input axi_s_arvalid; -output axi_s_arready; -output [`LID -1 :0] axi_s_rid; -output [`Lrdata -1 :0] axi_s_rdata; -output [`Lrresp -1 :0] axi_s_rresp; -output axi_s_rlast; -output axi_s_rvalid; -input axi_s_rready; - - - - -output [`LID -1 :0] s0_awid; -output [`Lawaddr -1 :0] s0_awaddr; -output [`Lawlen -1 :0] s0_awlen; -output [`Lawsize -1 :0] s0_awsize; -output [`Lawburst -1 :0] s0_awburst; -output [`Lawlock -1 :0] s0_awlock; -output [`Lawcache -1 :0] s0_awcache; -output [`Lawprot -1 :0] s0_awprot; -output s0_awvalid; -input s0_awready; -output [`LID -1 :0] s0_wid; -output [`Lwdata -1 :0] s0_wdata; -output [`Lwstrb -1 :0] s0_wstrb; -output s0_wlast; -output s0_wvalid; -input s0_wready; -input [`LID -1 :0] s0_bid; -input [`Lbresp -1 :0] s0_bresp; -input s0_bvalid; -output s0_bready; -output [`LID -1 :0] s0_arid; -output [`Laraddr -1 :0] s0_araddr; -output [`Larlen -1 :0] s0_arlen; -output [`Larsize -1 :0] s0_arsize; -output [`Larburst -1 :0] s0_arburst; -output [`Larlock -1 :0] s0_arlock; -output [`Larcache -1 :0] s0_arcache; -output [`Larprot -1 :0] s0_arprot; -output s0_arvalid; -input s0_arready; -input [`LID -1 :0] s0_rid; -input [`Lrdata -1 :0] s0_rdata; -input [`Lrresp -1 :0] s0_rresp; -input s0_rlast; -input s0_rvalid; -output s0_rready; - -output [`LID -1 :0] s1_awid; -output [`Lawaddr -1 :0] s1_awaddr; -output [`Lawlen -1 :0] s1_awlen; -output [`Lawsize -1 :0] s1_awsize; -output [`Lawburst -1 :0] s1_awburst; -output [`Lawlock -1 :0] s1_awlock; -output [`Lawcache -1 :0] s1_awcache; -output [`Lawprot -1 :0] s1_awprot; -output s1_awvalid; -input s1_awready; -output [`LID -1 :0] s1_wid; -output [`Lwdata -1 :0] s1_wdata; -output [`Lwstrb -1 :0] s1_wstrb; -output s1_wlast; -output s1_wvalid; -input s1_wready; -input [`LID -1 :0] s1_bid; -input [`Lbresp -1 :0] s1_bresp; -input s1_bvalid; -output s1_bready; -output [`LID -1 :0] s1_arid; -output [`Laraddr -1 :0] s1_araddr; -output [`Larlen -1 :0] s1_arlen; -output [`Larsize -1 :0] s1_arsize; -output [`Larburst -1 :0] s1_arburst; -output [`Larlock -1 :0] s1_arlock; -output [`Larcache -1 :0] s1_arcache; -output [`Larprot -1 :0] s1_arprot; -output s1_arvalid; -input s1_arready; -input [`LID -1 :0] s1_rid; -input [`Lrdata -1 :0] s1_rdata; -input [`Lrresp -1 :0] s1_rresp; -input s1_rlast; -input s1_rvalid; -output s1_rready; - - -output [`LID -1 :0] s2_awid; -output [`Lawaddr -1 :0] s2_awaddr; -output [`Lawlen -1 :0] s2_awlen; -output [`Lawsize -1 :0] s2_awsize; -output [`Lawburst -1 :0] s2_awburst; -output [`Lawlock -1 :0] s2_awlock; -output [`Lawcache -1 :0] s2_awcache; -output [`Lawprot -1 :0] s2_awprot; -output s2_awvalid; -input s2_awready; -output [`LID -1 :0] s2_wid; -output [`Lwdata -1 :0] s2_wdata; -output [`Lwstrb -1 :0] s2_wstrb; -output s2_wlast; -output s2_wvalid; -input s2_wready; -input [`LID -1 :0] s2_bid; -input [`Lbresp -1 :0] s2_bresp; -input s2_bvalid; -output s2_bready; -output [`LID -1 :0] s2_arid; -output [`Laraddr -1 :0] s2_araddr; -output [`Larlen -1 :0] s2_arlen; -output [`Larsize -1 :0] s2_arsize; -output [`Larburst -1 :0] s2_arburst; -output [`Larlock -1 :0] s2_arlock; -output [`Larcache -1 :0] s2_arcache; -output [`Larprot -1 :0] s2_arprot; -output s2_arvalid; -input s2_arready; -input [`LID -1 :0] s2_rid; -input [`Lrdata -1 :0] s2_rdata; -input [`Lrresp -1 :0] s2_rresp; -input s2_rlast; -input s2_rvalid; -output s2_rready; - -output [`LID -1 :0] s3_awid; -output [`Lawaddr -1 :0] s3_awaddr; -output [`Lawlen -1 :0] s3_awlen; -output [`Lawsize -1 :0] s3_awsize; -output [`Lawburst -1 :0] s3_awburst; -output [`Lawlock -1 :0] s3_awlock; -output [`Lawcache -1 :0] s3_awcache; -output [`Lawprot -1 :0] s3_awprot; -output s3_awvalid; -input s3_awready; -output [`LID -1 :0] s3_wid; -output [`Lwdata -1 :0] s3_wdata; -output [`Lwstrb -1 :0] s3_wstrb; -output s3_wlast; -output s3_wvalid; -input s3_wready; -input [`LID -1 :0] s3_bid; -input [`Lbresp -1 :0] s3_bresp; -input s3_bvalid; -output s3_bready; -output [`LID -1 :0] s3_arid; -output [`Laraddr -1 :0] s3_araddr; -output [`Larlen -1 :0] s3_arlen; -output [`Larsize -1 :0] s3_arsize; -output [`Larburst -1 :0] s3_arburst; -output [`Larlock -1 :0] s3_arlock; -output [`Larcache -1 :0] s3_arcache; -output [`Larprot -1 :0] s3_arprot; -output s3_arvalid; -input s3_arready; -input [`LID -1 :0] s3_rid; -input [`Lrdata -1 :0] s3_rdata; -input [`Lrresp -1 :0] s3_rresp; -input s3_rlast; -input s3_rvalid; -output s3_rready; - - -output [`LID -1 :0] s4_awid; -output [`Lawaddr -1 :0] s4_awaddr; -output [`Lawlen -1 :0] s4_awlen; -output [`Lawsize -1 :0] s4_awsize; -output [`Lawburst -1 :0] s4_awburst; -output [`Lawlock -1 :0] s4_awlock; -output [`Lawcache -1 :0] s4_awcache; -output [`Lawprot -1 :0] s4_awprot; -output s4_awvalid; -input s4_awready; -output [`LID -1 :0] s4_wid; -output [`Lwdata -1 :0] s4_wdata; -output [`Lwstrb -1 :0] s4_wstrb; -output s4_wlast; -output s4_wvalid; -input s4_wready; -input [`LID -1 :0] s4_bid; -input [`Lbresp -1 :0] s4_bresp; -input s4_bvalid; -output s4_bready; -output [`LID -1 :0] s4_arid; -output [`Laraddr -1 :0] s4_araddr; -output [`Larlen -1 :0] s4_arlen; -output [`Larsize -1 :0] s4_arsize; -output [`Larburst -1 :0] s4_arburst; -output [`Larlock -1 :0] s4_arlock; -output [`Larcache -1 :0] s4_arcache; -output [`Larprot -1 :0] s4_arprot; -output s4_arvalid; -input s4_arready; -input [`LID -1 :0] s4_rid; -input [`Lrdata -1 :0] s4_rdata; -input [`Lrresp -1 :0] s4_rresp; -input s4_rlast; -input s4_rvalid; -output s4_rready; - -wire clk; -wire rst_n; - - -reg [`LID -1:0] axi_s_rid; -reg [`Lrdata-1:0]axi_s_rdata; -reg [1:0]axi_s_rresp; -reg axi_s_rlast; -reg axi_s_rvalid; -reg axi_s_arready; - -reg [`SLV_MUX_NUM-1:0]wr_data_s_hit; - -wire [`SLV_MUX_NUM-1:0]rd_addr_hit; -wire [`SLV_MUX_NUM-1:0]wr_addr_hit; -reg [`SLV_MUX_NUM-1:0]wr_resp_s_hit ; - -wire [`SLV_MUX_NUM-1:0]s_awready ; -wire [`SLV_MUX_NUM-1:0]s_wready ; -wire [`SLV_MUX_NUM-1:0]s_bvalid ; -wire [`SLV_MUX_NUM-1:0]s_arready ; -wire [`SLV_MUX_NUM-1:0]s_rlast ; -wire [`SLV_MUX_NUM-1:0]s_rvalid ; - -wire [`LID -1:0] s_bid [`SLV_MUX_NUM-1:0]; -wire [1:0] s_bresp [`SLV_MUX_NUM-1:0]; -wire [`LID -1:0] s_rid [`SLV_MUX_NUM-1:0]; -wire [`Lrdata-1:0] s_rdata [`SLV_MUX_NUM-1:0]; -wire [1:0] s_rresp [`SLV_MUX_NUM-1:0]; - -wire s0_awvalid ; -wire s0_wvalid ; -wire s0_bready ; -wire s0_arvalid ; -wire s0_rready ; - - -assign s0_awid = axi_s_awid; -assign s0_awaddr = axi_s_awaddr; -assign s0_awlen = axi_s_awlen; -assign s0_awsize = axi_s_awsize; -assign s0_awburst = axi_s_awburst; -assign s0_awlock = axi_s_awlock; -assign s0_awcache = axi_s_awcache; -assign s0_awprot = axi_s_awprot; -assign s0_wid = axi_s_wid; -assign s0_wdata = axi_s_wdata; -assign s0_wstrb = axi_s_wstrb; -assign s0_wlast = axi_s_wlast; -assign s0_arid = axi_s_arid; -assign s0_araddr = axi_s_araddr; -assign s0_arlen = axi_s_arlen; -assign s0_arsize = axi_s_arsize; -assign s0_arburst = axi_s_arburst; -assign s0_arlock = axi_s_arlock; -assign s0_arcache = axi_s_arcache; -assign s0_arprot = axi_s_arprot; - -wire s1_awvalid ; -wire s1_wvalid ; -wire s1_bready ; -wire s1_arvalid ; -wire s1_rready ; - -assign s1_awid = axi_s_awid; -assign s1_awaddr = axi_s_awaddr; -assign s1_awlen = axi_s_awlen; -assign s1_awsize = axi_s_awsize; -assign s1_awburst = axi_s_awburst; -assign s1_awlock = axi_s_awlock; -assign s1_awcache = axi_s_awcache; -assign s1_awprot = axi_s_awprot; -assign s1_wid = axi_s_wid; -assign s1_wdata = axi_s_wdata; -assign s1_wstrb = axi_s_wstrb; -assign s1_wlast = axi_s_wlast; -assign s1_arid = axi_s_arid; -assign s1_araddr = axi_s_araddr; -assign s1_arlen = axi_s_arlen; -assign s1_arsize = axi_s_arsize; -assign s1_arburst = axi_s_arburst; -assign s1_arlock = axi_s_arlock; -assign s1_arcache = axi_s_arcache; -assign s1_arprot = axi_s_arprot; - -wire s2_awvalid ; -wire s2_wvalid ; -wire s2_bready ; -wire s2_arvalid ; -wire s2_rready ; -assign s2_awid = axi_s_awid; -assign s2_awaddr = axi_s_awaddr; -assign s2_awlen = axi_s_awlen; -assign s2_awsize = axi_s_awsize; -assign s2_awburst = axi_s_awburst; -assign s2_awlock = axi_s_awlock; -assign s2_awcache = axi_s_awcache; -assign s2_awprot = axi_s_awprot; -assign s2_wid = axi_s_wid; -assign s2_wdata = axi_s_wdata; -assign s2_wstrb = axi_s_wstrb; -assign s2_wlast = axi_s_wlast; -assign s2_arid = axi_s_arid; -assign s2_araddr = axi_s_araddr; -assign s2_arlen = axi_s_arlen; -assign s2_arsize = axi_s_arsize; -assign s2_arburst = axi_s_arburst; -assign s2_arlock = axi_s_arlock; -assign s2_arcache = axi_s_arcache; -assign s2_arprot = axi_s_arprot; -wire s3_awvalid ; -wire s3_wvalid ; -wire s3_bready ; -wire s3_arvalid ; -wire s3_rready ; -assign s3_awid = axi_s_awid; -assign s3_awaddr = axi_s_awaddr; -assign s3_awlen = axi_s_awlen; -assign s3_awsize = axi_s_awsize; -assign s3_awburst = axi_s_awburst; -assign s3_awlock = axi_s_awlock; -assign s3_awcache = axi_s_awcache; -assign s3_awprot = axi_s_awprot; -assign s3_wid = axi_s_wid; -assign s3_wdata = axi_s_wdata; -assign s3_wstrb = axi_s_wstrb; -assign s3_wlast = axi_s_wlast; -assign s3_arid = axi_s_arid; -assign s3_araddr = axi_s_araddr; -assign s3_arlen = axi_s_arlen; -assign s3_arsize = axi_s_arsize; -assign s3_arburst = axi_s_arburst; -assign s3_arlock = axi_s_arlock; -assign s3_arcache = axi_s_arcache; -assign s3_arprot = axi_s_arprot; -wire s4_awvalid ; -wire s4_wvalid ; -wire s4_bready ; -wire s4_arvalid ; -wire s4_rready ; -assign s4_awid = axi_s_awid; -assign s4_awaddr = axi_s_awaddr; -assign s4_awlen = axi_s_awlen; -assign s4_awsize = axi_s_awsize; -assign s4_awburst = axi_s_awburst; -assign s4_awlock = axi_s_awlock; -assign s4_awcache = axi_s_awcache; -assign s4_awprot = axi_s_awprot; -assign s4_wid = axi_s_wid; -assign s4_wdata = axi_s_wdata; -assign s4_wstrb = axi_s_wstrb; -assign s4_wlast = axi_s_wlast; -assign s4_arid = axi_s_arid; -assign s4_araddr = axi_s_araddr; -assign s4_arlen = axi_s_arlen; -assign s4_arsize = axi_s_arsize; -assign s4_arburst = axi_s_arburst; -assign s4_arlock = axi_s_arlock; -assign s4_arcache = axi_s_arcache; -assign s4_arprot = axi_s_arprot; - -reg [`SLV_MUX_NUM-1:0] s_awvalid; -reg [`SLV_MUX_NUM-1:0] s_wvalid ; -reg [`SLV_MUX_NUM-1:0] s_bready ; -reg [`SLV_MUX_NUM-1:0] s_arvalid; -reg [`SLV_MUX_NUM-1:0] s_rready ; - -assign s0_awvalid = s_awvalid[0] ; -assign s0_wvalid = s_wvalid [0] ; -assign s0_bready = s_bready [0] ; -assign s0_arvalid = s_arvalid[0] ; -assign s0_rready = s_rready [0] ; - -assign s1_awvalid = s_awvalid[1] ; -assign s1_wvalid = s_wvalid [1] ; -assign s1_bready = s_bready [1] ; -assign s1_arvalid = s_arvalid[1] ; -assign s1_rready = s_rready [1] ; - -assign s2_awvalid = s_awvalid[2] ; -assign s2_wvalid = s_wvalid [2] ; -assign s2_bready = s_bready [2] ; -assign s2_arvalid = s_arvalid[2] ; -assign s2_rready = s_rready [2] ; -assign s3_awvalid = s_awvalid[3] ; -assign s3_wvalid = s_wvalid [3] ; -assign s3_bready = s_bready [3] ; -assign s3_arvalid = s_arvalid[3] ; -assign s3_rready = s_rready [3] ; -assign s4_awvalid = s_awvalid[4] ; -assign s4_wvalid = s_wvalid [4] ; -assign s4_bready = s_bready [4] ; -assign s4_arvalid = s_arvalid[4] ; -assign s4_rready = s_rready [4] ; - -assign s_awready[0] = s0_awready ; -assign s_wready[0] = s0_wready ; -assign s_bid[0] = s0_bid ; -assign s_bresp[0] = s0_bresp ; -assign s_bvalid[0] = s0_bvalid ; -assign s_arready[0] = s0_arready ; -assign s_rid[0] = s0_rid ; -assign s_rdata[0] = s0_rdata ; -assign s_rresp[0] = s0_rresp ; -assign s_rlast[0] = s0_rlast ; -assign s_rvalid[0] = s0_rvalid ; -assign s_awready[1] = s1_awready ; -assign s_wready[1] = s1_wready ; -assign s_bid[1] = s1_bid ; -assign s_bresp[1] = s1_bresp ; -assign s_bvalid[1] = s1_bvalid ; -assign s_arready[1] = s1_arready ; -assign s_rid[1] = s1_rid ; -assign s_rdata[1] = s1_rdata ; -assign s_rresp[1] = s1_rresp ; -assign s_rlast[1] = s1_rlast ; -assign s_rvalid[1] = s1_rvalid ; - -assign s_awready[2] = s2_awready ; -assign s_wready[2] = s2_wready ; -assign s_bid[2] = s2_bid ; -assign s_bresp[2] = s2_bresp ; -assign s_bvalid[2] = s2_bvalid ; -assign s_arready[2] = s2_arready ; -assign s_rid[2] = s2_rid ; -assign s_rdata[2] = s2_rdata ; -assign s_rresp[2] = s2_rresp ; -assign s_rlast[2] = s2_rlast ; -assign s_rvalid[2] = s2_rvalid ; -assign s_awready[3] = s3_awready ; -assign s_wready[3] = s3_wready ; -assign s_bid[3] = s3_bid ; -assign s_bresp[3] = s3_bresp ; -assign s_bvalid[3] = s3_bvalid ; -assign s_arready[3] = s3_arready ; -assign s_rid[3] = s3_rid ; -assign s_rdata[3] = s3_rdata ; -assign s_rresp[3] = s3_rresp ; -assign s_rlast[3] = s3_rlast ; -assign s_rvalid[3] = s3_rvalid ; -assign s_awready[4] = s4_awready ; -assign s_wready[4] = s4_wready ; -assign s_bid[4] = s4_bid ; -assign s_bresp[4] = s4_bresp ; -assign s_bvalid[4] = s4_bvalid ; -assign s_arready[4] = s4_arready ; -assign s_rid[4] = s4_rid ; -assign s_rdata[4] = s4_rdata ; -assign s_rresp[4] = s4_rresp ; -assign s_rlast[4] = s4_rlast ; -assign s_rvalid[4] = s4_rvalid ; - -wire [4:0]BASE_ADDR [`SLV_MUX_NUM-1:0]; -wire [2:0]wr_sel_group_0; -wire [2:0]wr_sel_group_1; -wire [2:0]bvalid_group_0; -wire [2:0]bvalid_group_1; - -wire [2:0]rd_sel_group_0; -wire [2:0]rd_sel_group_1; -wire [2:0]rd_valid_group_0; -wire [2:0]rd_valid_group_1; - -assign bvalid_group_0 = s_bvalid[2:0]; -assign bvalid_group_1 = {1'b0,s_bvalid[4:3]}; -assign rd_valid_group_0 = s_rvalid[2:0]; -assign rd_valid_group_1 = {1'b0,s_rvalid[4:3]}; - -wire wr_fifo_empty; -wire wr_fifo_full; -wire rd_fifo_empty; -wire rd_fifo_full; - -assign clk = axi_s_aclk; -assign rst_n = axi_s_aresetn; - -reg axi_s_awready ; -reg axi_s_wready ; -reg axi_s_bvalid; -reg [`LID -1:0] axi_s_bid; -reg [1:0] axi_s_bresp; -wire wr_dir_ins; -wire wr_dir_del; -wire [2:0] wr_data_dir; -reg [2:0] wr_addr_dir; -reg [2:0] wr_resp_pre_sel; -reg wr_resp_prog; -reg [2:0] wr_resp_sel_reg; -wire [2:0] wr_resp_sel; - -integer axi_s_awready_int; -always @(s_awready or wr_fifo_full or wr_addr_hit) -begin - axi_s_awready = 1'b0; - for(axi_s_awready_int= 0 ; axi_s_awready_int< `SLV_MUX_NUM ;axi_s_awready_int=axi_s_awready_int+ 1) - begin - if(!wr_fifo_full & wr_addr_hit[axi_s_awready_int]) - axi_s_awready = s_awready[axi_s_awready_int]; - end -end - -integer awvlid_int; -always @(axi_s_awvalid or wr_fifo_full or wr_addr_hit) -begin - for(awvlid_int= 0 ; awvlid_int< `SLV_MUX_NUM ;awvlid_int=awvlid_int+ 1) - s_awvalid [awvlid_int] = !wr_fifo_full && wr_addr_hit[awvlid_int] && axi_s_awvalid; -end - -integer resp_int; -always @(wr_resp_prog or wr_resp_sel or wr_resp_sel_reg ) -begin - for(resp_int= 0 ; resp_int< `SLV_MUX_NUM ;resp_int= resp_int+ 1) - wr_resp_s_hit [resp_int] = !wr_resp_prog && wr_resp_sel == resp_int|| wr_resp_prog && wr_resp_sel_reg == resp_int; -end - -assign wr_sel_group_0=get_num(bvalid_group_0,wr_resp_pre_sel,2'h0); -assign wr_sel_group_1=get_num(bvalid_group_1,wr_resp_pre_sel,2'h3); -assign wr_resp_sel= ((wr_sel_group_0== 3'h7) && (wr_sel_group_1== 3'h7) ) ? 3'h7: - ((wr_sel_group_0!= 3'h7) && (wr_sel_group_1== 3'h7) ) ?wr_sel_group_0: - ((wr_sel_group_0== 3'h7) && (wr_sel_group_1!= 3'h7) ) ?wr_sel_group_1: - (wr_resp_pre_sel > 2'h2) ? wr_sel_group_0 : wr_sel_group_1; - -integer axi_s_resp_int; -always @(*) -begin - axi_s_bid =8'h0; - axi_s_bresp =2'h0; - axi_s_bvalid =1'h0; - for(axi_s_resp_int= 0 ; axi_s_resp_int< `SLV_MUX_NUM ;axi_s_resp_int=axi_s_resp_int+ 1) - begin - s_bready [axi_s_resp_int] = 1'b0; - if(wr_resp_s_hit[axi_s_resp_int]) - begin - axi_s_bid = s_bid[axi_s_resp_int]; - axi_s_bresp = s_bresp[axi_s_resp_int]; - axi_s_bvalid = s_bvalid[axi_s_resp_int]; - s_bready [axi_s_resp_int] = axi_s_bready; - end - end -end - -assign wr_dir_ins = !wr_fifo_full && axi_s_awvalid && axi_s_awready; -assign wr_dir_del = !wr_fifo_empty && axi_s_wvalid && axi_s_wready && axi_s_wlast; - -integer w_addr_dir_int; -always @(wr_addr_hit) -begin - wr_addr_dir = 3'b0; - for(w_addr_dir_int= 0 ; w_addr_dir_int< `SLV_MUX_NUM ;w_addr_dir_int= w_addr_dir_int+ 1) - if(wr_addr_hit[w_addr_dir_int]) - wr_addr_dir =w_addr_dir_int; -end - -integer w_ad_int; -always @(wr_fifo_empty or wr_data_dir ) -begin - for(w_ad_int = 0 ; w_ad_int < `SLV_MUX_NUM ;w_ad_int = w_ad_int + 1) - wr_data_s_hit[w_ad_int] = (!wr_fifo_empty && wr_data_dir == w_ad_int); -end - -assign wr_addr_hit[1] = axi_s_awaddr[31:20]==12'h1fc || - axi_s_awaddr[31:16]==16'h1fe8; //SPI -assign wr_addr_hit[2] = axi_s_awaddr[31:16]==16'h1fe4 || - axi_s_awaddr[31:16]==16'h1fe7 ; //APB: uart and nand -assign wr_addr_hit[3] = axi_s_awaddr[31:16]==16'h1fd0; //CONF -assign wr_addr_hit[4] = axi_s_awaddr[31:16]==16'h1ff0; //MAC -assign wr_addr_hit[0] = ~|wr_addr_hit[4:1]; //DDR3 - -nb_sync_fifo_mux wr_fifo -( -.clk(clk), -.rst_n(rst_n), - -.empty(wr_fifo_empty), -.full(wr_fifo_full), - -.shift_in(wr_dir_ins), -.data_in(wr_addr_dir), - -.shift_out(wr_dir_del), -.data_out(wr_data_dir) -); - -always@(posedge clk) begin - if(!rst_n) - wr_resp_pre_sel <= 3'b0; - else if(axi_s_bvalid && axi_s_bready) - wr_resp_pre_sel <= wr_resp_sel; -end - - -always@(posedge clk) begin - if(!rst_n || axi_s_bvalid && axi_s_bready) - wr_resp_prog <= 1'b0; - else if(!wr_resp_prog && (|s_bvalid) ) - wr_resp_prog <= 1'b1; -end - -always@(posedge clk) begin - if(!rst_n) - wr_resp_sel_reg <= 3'b0; - else if(!wr_resp_prog && (|s_bvalid) ) - wr_resp_sel_reg <= wr_resp_sel; -end - -integer axi_s_wready_int; -always @(s_wready or wr_data_s_hit) -begin - axi_s_wready = 1'b0; - for(axi_s_wready_int= 0 ; axi_s_wready_int< `SLV_MUX_NUM ;axi_s_wready_int=axi_s_wready_int+ 1) - begin - if(wr_data_s_hit[axi_s_wready_int]) - begin - axi_s_wready = s_wready [axi_s_wready_int]; - end - end -end - -integer wvalid_int; -always @(wr_data_s_hit or axi_s_wvalid ) -begin - for(wvalid_int= 0 ; wvalid_int< `SLV_MUX_NUM ;wvalid_int= wvalid_int+ 1) - s_wvalid[wvalid_int] = axi_s_wvalid && wr_data_s_hit[wvalid_int]; -end - - -wire [2:0] rd_data_sel; -wire rd_dir_ins; -wire rd_dir_del; -wire [2:0] rd_data_dir; -reg [2:0] rd_addr_dir; -reg [2:0] rd_data_pre_sel; -integer rd_arready_int; -integer rd_arvalid_int; -integer rd_addr_hit_int; - -always @(s_arready or rd_fifo_full or rd_addr_hit) -begin - axi_s_arready ='h0; - for(rd_arready_int= 0 ; rd_arready_int< `SLV_MUX_NUM ;rd_arready_int=rd_arready_int+ 1) - if(!rd_fifo_full && rd_addr_hit[rd_arready_int]) - begin - axi_s_arready =s_arready[rd_arready_int]; - end -end - -always @(axi_s_arvalid or rd_fifo_full or rd_addr_hit) -begin - for(rd_arvalid_int= 0 ; rd_arvalid_int< `SLV_MUX_NUM ;rd_arvalid_int=rd_arvalid_int+ 1) - s_arvalid [rd_arvalid_int] = !rd_fifo_full && rd_addr_hit[rd_arvalid_int] && axi_s_arvalid; -end - -assign rd_addr_hit[1] = ((axi_s_araddr[31:16]) ==16'h1fe8) || ((axi_s_araddr[31:20])==12'h1fc); //SPI -assign rd_addr_hit[2] = (axi_s_araddr[31:16]) ==16'h1fe4 || - (axi_s_araddr[31:16]) ==16'h1fe7 ;//APB:uart and nand -assign rd_addr_hit[3] = (axi_s_araddr[31:16]) ==16'h1fd0; //CONF -assign rd_addr_hit[4] = (axi_s_araddr[31:16]) == 16'h1ff0; //MAC -assign rd_addr_hit[0] = ~|rd_addr_hit[4:1]; //DDR3 - -integer rd_addr_dir_int; -always @(rd_addr_hit) -begin - rd_addr_dir = 3'b0; - for(rd_addr_dir_int= 0 ; rd_addr_dir_int< `SLV_MUX_NUM ;rd_addr_dir_int= rd_addr_dir_int+ 1) - if(rd_addr_hit[rd_addr_dir_int]) - rd_addr_dir =rd_addr_dir_int; -end - -integer axi_rd_data_int; -always @(*) -begin - axi_s_rid =8'h0; - axi_s_rdata =128'h0; - axi_s_rresp =2'h0; - axi_s_rlast =1'h0; - axi_s_rvalid =1'h0; - for(axi_rd_data_int= 0 ; axi_rd_data_int< `SLV_MUX_NUM ;axi_rd_data_int=axi_rd_data_int+ 1) - begin - s_rready [axi_rd_data_int] = 1'b0; - if(rd_data_sel==axi_rd_data_int) begin - s_rready [axi_rd_data_int] = axi_s_rready; - axi_s_rid =s_rid [axi_rd_data_int]; - axi_s_rdata =s_rdata [axi_rd_data_int]; - axi_s_rresp =s_rresp [axi_rd_data_int]; - axi_s_rlast =s_rlast [axi_rd_data_int]; - axi_s_rvalid =s_rvalid [axi_rd_data_int]; - end - end -end - -always@(posedge clk) begin - if(!rst_n) - begin - rd_data_pre_sel<= 3'b0; - end - else if(axi_s_rvalid && axi_s_rready) - begin - rd_data_pre_sel <= rd_data_sel; - end -end - -assign rd_data_sel =rd_data_dir; - -nb_sync_fifo_mux rd_fifo -( -.clk(clk), -.rst_n(rst_n), - -.empty(rd_fifo_empty), -.full(rd_fifo_full), - -.shift_in(rd_dir_ins), -.data_in(rd_addr_dir), - -.shift_out(rd_dir_del), -.data_out(rd_data_dir) -); - -assign rd_dir_ins = !rd_fifo_full && axi_s_arvalid && axi_s_arready; -assign rd_dir_del = !rd_fifo_empty && axi_s_rvalid && axi_s_rready && axi_s_rlast; - -function [2:0] get_num; -input [2:0] valid; -input [2:0] pre_num; -input [1:0] group; -begin -get_num=(valid == 3'b001)? (3'h0+group) : - (valid == 3'b010)? (3'h1+group) : - (valid == 3'b100)? (3'h2+group) : - (valid == 3'b011)? (pre_num!=(3'h0+group))?(3'h0+group):(3'h1+group) : - (valid == 3'b110)? (pre_num!=(3'h1+group))?(3'h1+group):(3'h2+group) : - (valid == 3'b101)? (pre_num!=(3'h2+group))?(3'h2+group):(3'h0+group) : - (valid == 3'b111)?((pre_num==(3'h0+group))?(3'h1+group):(pre_num==(3'h1+group))?(3'h2+group):(3'h0+group)):3'h7; -end -endfunction -endmodule - -`undef SLV_MUX_5 -`undef SLV_MUX_NUM - -module nb_sync_fifo_mux -( -clk, -rst_n, - -empty, -full, - -shift_in, -data_in, - -shift_out, -data_out -); -parameter FIFO_WIDTH = 3; - -input clk; -input rst_n; - -output empty; -output full; - -input shift_in; -input [FIFO_WIDTH-1:0] data_in; - -input shift_out; -output[FIFO_WIDTH-1:0] data_out; - - -reg [FIFO_WIDTH-1:0] fifo_ram [1:0]; -reg [1:0] wr_ptr; -reg [1:0] rd_ptr; - -wire [0:0] mem_wr_pos; -wire [0:0] mem_rd_pos; - -always@(posedge clk) begin - if(!rst_n) - wr_ptr <= 2'h0; - else if(~full && shift_in) - wr_ptr <= wr_ptr + 2'h1; -end - -always@(posedge clk) begin - if(!rst_n) - rd_ptr <= 2'h0; - else if(~empty && shift_out) - rd_ptr <= rd_ptr + 2'h1; -end - -assign full = wr_ptr == {~rd_ptr[1],rd_ptr[0]}; -assign empty = wr_ptr == rd_ptr; - -assign mem_wr_pos = wr_ptr[0:0]; -assign mem_rd_pos = rd_ptr[0:0]; - -assign data_out = fifo_ram[mem_rd_pos]; - -integer i; - -always@(posedge clk) begin - if(!rst_n) - for(i=0;i<2;i=i+1) - fifo_ram[i] <= 2'b0; - else if(shift_in && ~full) - fifo_ram[mem_wr_pos] <= data_in; -end - -endmodule diff --git a/resources/soc/rtl/APB_DEV/NAND/nand.v b/resources/soc/rtl/APB_DEV/NAND/nand.v deleted file mode 100644 index f17408f..0000000 --- a/resources/soc/rtl/APB_DEV/NAND/nand.v +++ /dev/null @@ -1,1430 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -module NAND_top( - nand_type, - - pclk, - prst_, - psel, - penable, - pwrite, - ADDR, - DAT_I, - DAT_O, - - NAND_CE_o, - NAND_REQ, - NAND_I, - NAND_O, - NAND_EN_, - NAND_ALE, - NAND_CLE, - NAND_WR_, - NAND_RD_, - NAND_IORDY_i, - - nand_int -); -input [1:0]nand_type; - -input pclk; -input prst_; -input pwrite; -input psel; -input penable; -input [10:0]ADDR; -input [31:0]DAT_I; -output [31:0]DAT_O; - -output [3:0]NAND_CE_o; -output NAND_REQ; -input [7:0]NAND_I; -output [7:0]NAND_O; -output NAND_EN_; -output NAND_ALE; -output NAND_CLE; -output NAND_WR_; -output NAND_RD_; -input [3:0]NAND_IORDY_i; -output nand_int; - -/************************************************************/ - -reg [31:0]REG_DAT_T; -reg [13:0]nand_addr_c; -reg [24:0]nand_addr_r; -reg [31:0]nand_op_num; -reg [31:0]nand_parameter; -reg [31:0]nand_ce_map0; -reg [31:0]nand_ce_map1; -reg [31:0]nand_rdy_map0; -reg [31:0]nand_rdy_map1; -reg [31:0]nand_command; -reg [15:0] nand_timing; -reg [37:0] addr_in_die; -reg [4:0] NAND_STATE; -reg [31:0] NAND_OP_NUM; -reg [13:0] WRITE_MAX_COUNT; -reg [13:0] READ_MAX_COUNT; -reg nand_clr_ack; -reg NAND_DONE; -reg NAND_CE_; -reg nand_int; - -wire [13:0] op_scope; -wire [2:0] nand_id_num; -wire [3:0] nand_size; -wire main_op; -wire spare_op; -wire nand_int_en; -wire nand_dma_ack_i; -wire NANDtag; -wire NAND_IORDY; - - -wire HIT0 =psel & ADDR[10:0] == 11'h00; -wire HIT1 =psel & ADDR[10:0] == 11'h04; -wire HIT2 =psel & ADDR[10:0] == 11'h08; -wire HIT3 =psel & ADDR[10:0] == 11'h0c; -wire HIT4 =psel & ADDR[10:0] == 11'h10; -wire HIT5 =psel & ADDR[10:0] == 11'h14; -wire HIT6 =psel & ADDR[10:0] == 11'h18; -wire HIT7 =psel & ADDR[10:0] == 11'h1c; -wire HIT8 =psel & ADDR[10:0] == 11'h20; -wire HIT9 =psel & ADDR[10:0] == 11'h24; -wire HIT10=psel & ADDR[10:0] == 11'h28; -wire HIT11=psel & ADDR[10:0] == 11'h2c; -wire NAND_HIT =penable & ADDR[10:0] == 11'h40; -assign nand_dma_ack_i=psel & ADDR[10:0] == 11'h40; - -assign DAT_O = REG_DAT_T; -reg NAND_DMA_REQ; -reg nand_cmd_valid; - -always @(posedge pclk) -begin - if(~prst_) - begin - nand_int <= 1'b0; - end - else - begin - nand_int <= NAND_DONE&nand_int_en; - end -end - - - -always @(posedge pclk) -begin - if(~prst_) - begin - nand_clr_ack <= 1'b1; - nand_command <= {1'b0,1'b0,1'b0,1'b0,9'b0,1'b0,NANDtag}; - nand_timing <= {8'h4,8'h12}; - nand_op_num <= 2048; - nand_addr_c <= 14'h0; - nand_addr_r <= 25'h0; - nand_parameter<= (nand_type==2'h3) ? 32'h800_5100: - (nand_type==2'h2) ? 32'h800_5000: //2'h2 means 1Gbit - (nand_type==2'h1) ? 32'h200_4b00:32'h200_4c00; - nand_ce_map0 <= 32'h0; - nand_ce_map1 <= 32'h0; - nand_rdy_map0 <= 32'h0; - nand_rdy_map1 <= 32'h0; - nand_cmd_valid<=nand_command[0]; - end - else - begin - nand_cmd_valid<=nand_command[0]; - if(pwrite& HIT0) begin - nand_command[15:0] <= DAT_I[15:0]; - end - else if(NAND_DONE && nand_command[0]) begin - nand_command [0] <= 1'b0; - nand_command [10] <= 1'b1; - nand_clr_ack <= 1'b1; - end - else begin - nand_command[31:16] <={NAND_DMA_REQ,1'b0,1'b0,NAND_STATE,NAND_CE_o,NAND_IORDY_i}; - if(~NAND_DONE) nand_clr_ack <= 1'b0; - end - - if(pwrite& HIT1) nand_addr_c <= DAT_I[13:0]; - if(pwrite& HIT2) nand_addr_r <= DAT_I[24:0]; - if(pwrite& HIT3) begin - nand_timing[7:0] <= (DAT_I[7:0]<5) ? 8'h5: DAT_I[7:0]; - nand_timing[15:8] <= (DAT_I[15:8]<2) ? 8'h2: DAT_I[15:8]; - end - if(pwrite& HIT6) nand_parameter<= DAT_I; - if(pwrite& HIT7) nand_op_num <= DAT_I; - if(pwrite& HIT8) nand_ce_map0 <= DAT_I; - if(pwrite& HIT9) nand_ce_map1 <= DAT_I; - else nand_ce_map1 <= {READ_MAX_COUNT,NAND_OP_NUM[15:0]}; - if(pwrite& HIT10) nand_rdy_map0 <= DAT_I; - if(pwrite& HIT11) nand_rdy_map1 <= DAT_I; - else nand_rdy_map1 <= {WRITE_MAX_COUNT,NAND_OP_NUM[15:0]}; - end -end - - -assign NANDtag = ~prst_ ? 1'b0 : nand_cmd_valid; -assign op_scope = nand_parameter[29:16]; -assign nand_id_num = nand_parameter[14:12]; -assign nand_size = nand_parameter[11:8]; -assign main_op = nand_command[8]; -assign spare_op = nand_command[9]; -assign nand_int_en = nand_command[13]; - -reg [7:0] status; -reg [1:0] nand_number; -reg [47:0] ID_INFORM; -reg [31:0] NAND_DAT_O_RD; -wire [3:0] NAND_CE_pre_o; -wire [3:0] NAND_IORDY_post_i; - -always @(posedge pclk) -begin - if(~prst_) - begin - addr_in_die <= 38'h0; - nand_number <= 2'h0; - end - else begin - case(nand_size) - 4'h0: begin - nand_number <= nand_addr_r[17:16]; // 1Gb in a single die , page 2048 - addr_in_die <= {9'h0,nand_addr_r[15:0],4'b0,nand_addr_c[11:0]}; - end - 4'h1: begin - nand_number <= nand_addr_r[18:17]; - addr_in_die <= {5'h0,nand_addr_r[16:0],4'b0,nand_addr_c[11:0]}; - end - 4'h2: begin - nand_number <= nand_addr_r[19:18]; - addr_in_die <= {4'h0,nand_addr_r[17:0],4'b0,nand_addr_c[11:0]}; - end - 4'h3: begin - nand_number <= nand_addr_r[20:19]; - addr_in_die <= {3'h0,nand_addr_r[18:0],4'b0,nand_addr_c[11:0]}; - end - 4'h4: begin - nand_number <= nand_addr_r[20:19]; - addr_in_die <= {3'h0,nand_addr_r[18:0],3'b0,nand_addr_c[12:0]}; - end - 4'h5: begin - nand_number <= nand_addr_r[20:19]; - addr_in_die <= {3'h0,nand_addr_r[18:0],2'b0,nand_addr_c[13:0]}; - end - 4'h6: begin - nand_number <= nand_addr_r[21:20]; - addr_in_die <= {2'h0,nand_addr_r[19:0],2'b0,nand_addr_c[13:0]}; - end - 4'h7: begin - nand_number <= nand_addr_r[22:21]; - addr_in_die <= {1'h0,nand_addr_r[20:0],2'b0,nand_addr_c[13:0]}; - end - 4'h9: begin - nand_number <= nand_addr_r[15:14]; - addr_in_die <= {15'h0,nand_addr_r[13:0],nand_addr_c[8:0]}; - end - 4'ha: begin - nand_number <= nand_addr_r[16:15]; - addr_in_die <= {14'h0,nand_addr_r[14:0],nand_addr_c[8:0]}; - end - 4'hb: begin - nand_number <= nand_addr_r[17:16]; - addr_in_die <= {13'h0,nand_addr_r[15:0],nand_addr_c[8:0]}; - end - 4'hc: begin - nand_number <= nand_addr_r[18:17]; - addr_in_die <= {12'h0,nand_addr_r[16:0],nand_addr_c[8:0]}; - end - 4'hd: begin - nand_number <= nand_addr_r[19:18]; - addr_in_die <= {11'h0,nand_addr_r[17:0],nand_addr_c[8:0]}; - end - default: begin - nand_number <= 2'b0; - addr_in_die <= 38'b0; - end - endcase - end -end - -assign NAND_CE_pre_o[0] = (nand_number ==4'h0) ? NAND_CE_ : 1'b1; -assign NAND_CE_pre_o[1] = (nand_number ==4'h1) ? NAND_CE_ : 1'b1; -assign NAND_CE_pre_o[2] = (nand_number ==4'h2) ? NAND_CE_ : 1'b1; -assign NAND_CE_pre_o[3] = (nand_number ==4'h3) ? NAND_CE_ : 1'b1; -assign NAND_IORDY = (nand_number ==4'h0) ? NAND_IORDY_post_i[0]: - (nand_number ==4'h1) ? NAND_IORDY_post_i[1]: - (nand_number ==4'h2) ? NAND_IORDY_post_i[2]: - (nand_number ==4'h3) ? NAND_IORDY_post_i[3]:1'b1; - -assign NAND_CE_o[0] = NAND_CE_pre_o[0]; -assign NAND_IORDY_post_i[0] = NAND_IORDY_i[0]; -assign NAND_CE_o[1] = nand_ce_map0[8 ] ? NAND_CE_pre_o[0]: - nand_ce_map0[9 ] ? NAND_CE_pre_o[1]: - nand_ce_map0[10] ? NAND_CE_pre_o[2]: - nand_ce_map0[11] ? NAND_CE_pre_o[3]:1'b1; - - -assign NAND_IORDY_post_i[1] = nand_ce_map0[12] ? NAND_IORDY_i[0]: - nand_ce_map0[13] ? NAND_IORDY_i[1]: - nand_ce_map0[14] ? NAND_IORDY_i[2]: - nand_ce_map0[15] ? NAND_IORDY_i[3]:1'b1; - -assign NAND_CE_o[2] = nand_ce_map0[16] ? NAND_CE_pre_o[0]: - nand_ce_map0[17] ? NAND_CE_pre_o[1]: - nand_ce_map0[18] ? NAND_CE_pre_o[2]: - nand_ce_map0[19] ? NAND_CE_pre_o[3]:1'b1; - -assign NAND_IORDY_post_i[2] = nand_ce_map0[20] ? NAND_IORDY_i[0]: - nand_ce_map0[21] ? NAND_IORDY_i[1]: - nand_ce_map0[22] ? NAND_IORDY_i[2]: - nand_ce_map0[23] ? NAND_IORDY_i[3]:1'b1; - -assign NAND_CE_o[3] = nand_ce_map0[24] ? NAND_CE_pre_o[0]: - nand_ce_map0[25] ? NAND_CE_pre_o[1]: - nand_ce_map0[26] ? NAND_CE_pre_o[2]: - nand_ce_map0[27] ? NAND_CE_pre_o[3]:1'b1; - -assign NAND_IORDY_post_i[3] = nand_ce_map0[28] ? NAND_IORDY_i[0]: - nand_ce_map0[29] ? NAND_IORDY_i[1]: - nand_ce_map0[30] ? NAND_IORDY_i[2]: - nand_ce_map0[31] ? NAND_IORDY_i[3]:1'b1; - -always @(pwrite or penable or NAND_HIT or - HIT0 or HIT1 or HIT2 or HIT3 or - HIT4 or HIT5 or HIT6 or HIT7 or - HIT8 or HIT9 or HIT10 or HIT11 or - nand_command or nand_op_num or nand_addr_c or nand_addr_r or - nand_ce_map0 or nand_ce_map1 or nand_rdy_map0 or nand_rdy_map1 or - nand_timing or nand_parameter or status or ID_INFORM or NAND_DAT_O_RD) -begin - if(~pwrite & HIT0 &penable) - REG_DAT_T = nand_command; - else if(~pwrite & HIT1&penable) - REG_DAT_T = {20'b0,nand_addr_c}; - else if(~pwrite & HIT2&penable) - REG_DAT_T = {7'b0,nand_addr_r}; - else if(~pwrite & HIT3&penable) - REG_DAT_T = nand_timing; - else if(~pwrite & HIT4&penable) - REG_DAT_T = ID_INFORM[31:0]; - else if(~pwrite & HIT5&penable) - REG_DAT_T = {status,ID_INFORM[47:32]}; - else if(~pwrite & HIT6&penable) - REG_DAT_T = nand_parameter; - else if(~pwrite & HIT7&penable) - REG_DAT_T = nand_op_num; - else if(~pwrite & HIT8&penable) - REG_DAT_T = nand_ce_map0 ; - else if(~pwrite & HIT9&penable) - REG_DAT_T = nand_ce_map1; - else if(~pwrite & HIT10&penable) - REG_DAT_T = nand_rdy_map0 ; - else if(~pwrite & HIT11&penable) - REG_DAT_T = nand_rdy_map1 ; - else if(~pwrite & NAND_HIT &penable) - REG_DAT_T = NAND_DAT_O_RD; - else REG_DAT_T = 0; -end - -reg [1:0] ADDR_pointer; -reg [7:0] NAND_O; -reg [2:0] NAND_ADDR_COUNT; -reg [7:0] WAIT_NUM; -reg [7:0] HOLD_NUM; -reg [7:0] COMMAND; -reg [4:0] PRE_STATE; -reg [2:0] READ_ID_NUM; -reg [13:0] data_count; -reg [37:0] NAND_ADDR; -reg [31:0] NAND_DAT_I_WR; - -reg NAND_WR_; -reg NAND_RD_; -reg NAND_CLE; -reg NAND_ALE; -reg NAND_GO; -reg NAND_ACK; -reg DMA_OP_DONE; -reg ERASE_SERIAL; -reg NAND_EN_; - -reg now_up_half; -reg now_oob; -assign NAND_REQ =NAND_DMA_REQ; - -parameter - NAND_IDLE = 5'b00000, - COMMAND_IN = 5'b00001, - - ADDR_4_RD_WR = 5'b00010, - ADDR_4_ERASE_ID = 5'b01010, - - READ_START = 5'b00011, - READ_WAIT = 5'b00100, - READ_WAIT_2 = 5'b00110, - READ_TRANSFER = 5'b00111, - - WRITE_START = 5'b10000, - WRITE_DATA = 5'b10001, - PROGRAM = 5'b10010, - PROGRAM_FAIL = 5'b10011, - - READ_ID = 5'b10100, - READ_STATUS = 5'b10101, - ID_TO_STATUS = 5'b10110, - - ERASE = 5'b10111, - WAIT_ERASE = 5'b11000, - ERASE_FAIL = 5'b11001, - - RESET = 5'b11010, - WAIT_RESET = 5'b11011; -always @(posedge pclk) -begin - if (~prst_||~NANDtag) - begin - now_up_half <= 1'b0; - now_oob <= 1'b0; - NAND_ACK <= 1'b0; - NAND_CLE <= 1'b0; - NAND_ALE <= 1'b0; - NAND_CE_ <= 1'b1; - NAND_WR_ <= 1'b1; - NAND_RD_ <= 1'b1; - NAND_O <= 8'b0; - COMMAND <= 8'h55; - data_count <= 14'b0; - NAND_ADDR <= 38'b0; - NAND_DONE <= 1'b0; - NAND_GO <= 1'b0; - if(~prst_) status <= 8'b0; - if(~prst_) ID_INFORM <= 48'h0; - WAIT_NUM <= 8'h14; - HOLD_NUM <= 8'h4; - PRE_STATE <= 5'b0; - ADDR_pointer <= 2'b0; - NAND_DMA_REQ <= 1'b0; - ERASE_SERIAL <= 1'b0; - NAND_OP_NUM <= 32'h0; - NAND_EN_ <= 1'b0; - NAND_ADDR_COUNT <= 3'b0; - READ_MAX_COUNT <= 14'b0; - WRITE_MAX_COUNT <= 14'b0; - DMA_OP_DONE <= 1'b0; - NAND_DAT_I_WR <= 32'b0; - NAND_DAT_O_RD <= 32'h12345678; - READ_ID_NUM <= 3'b100; - NAND_STATE <= NAND_IDLE; - end - else - begin - case(NAND_STATE) - NAND_IDLE: - begin - HOLD_NUM <= nand_timing[15:8]; - if(nand_command[0]) - begin - DMA_OP_DONE <= 1'b0; - if(nand_clr_ack) - NAND_DONE <= 1'b0; - if(NAND_OP_NUM==32'b0) begin - NAND_ADDR <= addr_in_die; - NAND_OP_NUM <= nand_op_num; - end - if(nand_command[1] &&NAND_GO && ~NAND_DONE&& (nand_size[3])&&(~main_op||main_op&&NAND_ADDR[8]&&now_up_half)&&spare_op) - begin - COMMAND <= 8'h50; - NAND_EN_ <= 1'b0; - NAND_GO <= 1'b0; - now_oob <= 1'b1; - now_up_half <= 1'b0; - end - else if(nand_command[1] && NAND_ADDR[8]&&nand_size[3]&&NAND_GO && ~NAND_DONE) - begin - COMMAND <= 8'h01; - NAND_EN_ <= 1'b0; - NAND_GO <= 1'b0; - now_oob <= 1'b0; - now_up_half <= main_op&spare_op; - end - else if(nand_command[1] && NAND_GO && ~NAND_DONE) - begin - COMMAND <= 8'h00; - NAND_EN_ <= 1'b0; - NAND_GO <= 1'b0; - now_oob <= 1'b0; - now_up_half <= 1'b0; - end - else if(nand_command[2]&&NAND_GO && ~NAND_DONE&& nand_size[3]&&(~main_op||main_op&&NAND_ADDR[8]&&now_up_half)&&spare_op) - begin - COMMAND <= 8'h50; - NAND_GO <= 1'b0; - now_oob <= 1'b1; - now_up_half <= 1'b0; - end - else if(nand_command[2]&&NAND_GO && ~NAND_DONE&& nand_size[3]&&NAND_ADDR[8]) - begin - COMMAND <= 8'h01; - NAND_GO <= 1'b0; - now_oob <= 1'b0; - now_up_half <= main_op&spare_op; - end - else if(nand_command[2]&&NAND_GO && ~NAND_DONE&& nand_size[3]&&~NAND_ADDR[8]) - begin - COMMAND <= 8'h0; - NAND_GO <= 1'b0; - now_oob <= 1'b0; - now_up_half <= 1'b0; - end - else if(nand_command[2]&&NAND_GO && ~NAND_DONE) - begin - COMMAND <= 8'h80; - NAND_GO <= 1'b0; - end - else if(nand_command[3]&&NAND_GO&& ~NAND_DONE ) - begin - COMMAND <= 8'h60; - NAND_GO <= 1'b0; - ERASE_SERIAL <= nand_command[4]; - end - else if(nand_command[5]&&NAND_GO&& ~NAND_DONE) - begin - COMMAND <= 8'h90; - NAND_GO <= 1'b0; - end - else if(nand_command[6]&&NAND_GO&& ~NAND_DONE) - begin - COMMAND <= 8'hFF; - NAND_GO <= 1'b0; - end - else if(nand_command[7]&&NAND_GO&& ~NAND_DONE) - begin - COMMAND <= 8'h70; - NAND_GO <= 1'b0; - end - else if((COMMAND==8'h00 || COMMAND==8'h70 || COMMAND==8'h80 || COMMAND==8'h01 || COMMAND==8'h50 || - COMMAND==8'h60 || COMMAND==8'h90 || COMMAND==8'hFF)&& ~NAND_DONE) begin - NAND_STATE<= COMMAND_IN; - PRE_STATE <= NAND_IDLE; - WAIT_NUM <= nand_timing[7:0]; - NAND_CE_ <= 1'b0; - NAND_CLE <= 1'b0; - NAND_ALE <= 1'b0; - NAND_WR_ <= 1'b1; - NAND_RD_ <= 1'b1; - NAND_EN_ <= 1'b0; - end - else begin - COMMAND <= 8'h55; - NAND_GO <= ~NAND_DONE & nand_command[0]; - if (~nand_command[0]) NAND_DONE <=1'b0; - end - end else begin - COMMAND <= 8'h55; - NAND_CE_ <= 1'b1; - NAND_WR_ <= 1'b1; - NAND_RD_ <= 1'b1; - NAND_STATE <= NAND_IDLE; - NAND_GO <= ~NAND_DONE&nand_command[0]; - if(~NAND_GO) begin - NAND_ADDR <= nand_command[0] ? addr_in_die : 38'h3f_ffff_ffff; - NAND_OP_NUM <= nand_command[0] ? nand_op_num : 32'b0; - end - if(nand_clr_ack) - NAND_DONE <= 1'b0; - end - end - COMMAND_IN: - begin - if(WAIT_NUM == nand_timing[7:0]) begin - NAND_CLE <= 1'b0; - NAND_WR_ <= 1'b1; - WAIT_NUM <= WAIT_NUM - 1'b1; - end - else if(WAIT_NUM == (nand_timing[7:0]-1)) begin - NAND_CLE <= 1'b1; - NAND_WR_ <= 1'b1; - WAIT_NUM <= WAIT_NUM - 1'b1; - end - else if(WAIT_NUM < nand_timing[7:0] && WAIT_NUM>HOLD_NUM) begin - NAND_O <= COMMAND; - NAND_CLE <= 1'b1; - NAND_WR_ <= 1'b0; - WAIT_NUM <= WAIT_NUM - 1'b1; - end - else if(WAIT_NUM<=HOLD_NUM && WAIT_NUM) begin - NAND_CLE <= 1'b1; - NAND_WR_ <= 1'b1; - WAIT_NUM <= WAIT_NUM - 1'b1; - end - else - begin - if(PRE_STATE==NAND_IDLE) begin - NAND_CE_ <= 1'b0; - NAND_CLE <= 1'b0; - NAND_WR_ <= 1'b1; - NAND_ALE <= 1'b0; - NAND_DONE <= 1'b0; - NAND_O <= 8'b0; - PRE_STATE <= COMMAND_IN; - if((nand_command[1]||nand_command[2])&&(COMMAND==8'h00||COMMAND==8'h01||COMMAND==8'h50)) begin - NAND_STATE <= nand_command[1] ? READ_START:WRITE_START; - WAIT_NUM <= nand_timing[7:0]; - end - else if(nand_command[2]&&(COMMAND==8'h80)) begin - NAND_STATE <= WRITE_START; - WAIT_NUM <= nand_timing[7:0]; - end - else if((COMMAND==8'h60)) begin - NAND_STATE <= ERASE; - PRE_STATE <= COMMAND_IN; - WAIT_NUM <= nand_timing[7:0]+2'b11; - end - else if((COMMAND==8'h70)) begin - NAND_STATE <= READ_STATUS; - WAIT_NUM <= nand_timing[7:0]+2'b11; - end - else if((COMMAND==8'h90)) begin - NAND_STATE <= READ_ID; - WAIT_NUM <= nand_timing[7:0]+2'b11; - end - else if((COMMAND==8'hFF)) begin - NAND_STATE <= RESET; - WAIT_NUM <= nand_timing[7:0]+2'b11; - end - else begin - NAND_STATE <= NAND_IDLE; - NAND_OP_NUM <= 32'b0; - NAND_CE_ <= 1'b1; - NAND_DONE <= 1'b1; - end - end - else - begin - NAND_CLE <= 1'b0; - NAND_ALE <= 1'b0; - NAND_WR_ <= 1'b1; - NAND_GO <= 1'b1; - NAND_STATE <= PRE_STATE; - PRE_STATE <= COMMAND_IN; - WAIT_NUM <= nand_timing[7:0]; - end - end - end - ADDR_4_ERASE_ID: - begin - if(NAND_ADDR_COUNT != 3'b0) - begin - if(WAIT_NUM > (nand_timing[7:0] - HOLD_NUM+1'b1)) - begin - NAND_ALE <= 1'b0; - NAND_WR_ <= 1'b1; - WAIT_NUM <= WAIT_NUM - 1'b1; - end - else if(WAIT_NUM > (nand_timing[7:0] - HOLD_NUM)) - begin - NAND_ALE <= 1'b1; - NAND_WR_ <= 1'b1; - WAIT_NUM <= WAIT_NUM - 1'b1; - end - else if(WAIT_NUM>=HOLD_NUM) - begin - NAND_ALE <= 1'b1; - NAND_WR_ <= 1'b0; - WAIT_NUM <= WAIT_NUM - 1'b1; - if(NAND_ADDR_COUNT == 2'b11) begin - if(nand_size==4'hc||nand_size==4'hd) NAND_O <= NAND_ADDR[16:9]; - else NAND_O <= NAND_ADDR[23:16]; - end - else if(NAND_ADDR_COUNT==2'b10) begin - if(nand_size==4'h9||nand_size==4'ha||nand_size==4'hb) NAND_O <= NAND_ADDR[16:9]; - else if(nand_size==4'hc||nand_size==4'hd) NAND_O <= NAND_ADDR[24:17]; - else if(nand_size==4'h0) NAND_O <= NAND_ADDR[23:16]; - else NAND_O <= NAND_ADDR[31:24]; - end - else if(NAND_ADDR_COUNT==3'b001) begin - if(PRE_STATE == READ_ID) - NAND_O <= NAND_ADDR[7:0]; - else - if(nand_size==4'h9||nand_size==4'ha||nand_size==4'hb) NAND_O <= NAND_ADDR[24:17]; - else if(nand_size==4'hc||nand_size==4'hd) NAND_O <= NAND_ADDR[32:25]; - else if(nand_size==4'h0) NAND_O <= NAND_ADDR[31:24]; - else NAND_O <= NAND_ADDR[35:32]; - end - end - else if((WAIT_NUM (nand_timing[7:0] - HOLD_NUM + 1'b1)) begin - NAND_ALE <= 1'b0; - NAND_WR_ <= 1'b1; - WAIT_NUM <= WAIT_NUM - 1'b1; - end - else if(WAIT_NUM > (nand_timing[7:0]- HOLD_NUM)) begin - NAND_ALE <= 1'b1; - NAND_WR_ <= 1'b1; - WAIT_NUM <= WAIT_NUM - 1'b1; - end - else if(WAIT_NUM>=HOLD_NUM) begin - NAND_ALE <= 1'b1; - NAND_WR_ <= 1'b0; - WAIT_NUM <= WAIT_NUM - 1'b1; - if(NAND_ADDR_COUNT==3'b101) - NAND_O <= NAND_ADDR[7:0]; - else if(NAND_ADDR_COUNT==3'b100) begin - if(nand_size==4'hc||nand_size==4'hd) NAND_O <= NAND_ADDR[7:0]; - else if(nand_size==4'h0) NAND_O <= NAND_ADDR[7:0]; - else NAND_O <= NAND_ADDR[15:8]; - end - else if(NAND_ADDR_COUNT==3'b11) begin - if(nand_size==4'h9||nand_size==4'ha||nand_size==4'hb) NAND_O <= NAND_ADDR[7:0]; - else if(nand_size==4'hc||nand_size==4'hd) NAND_O <= NAND_ADDR[16:9]; - else if(nand_size==4'h0) NAND_O <= NAND_ADDR[15:8]; - else NAND_O <= NAND_ADDR[23:16]; - end - else if(NAND_ADDR_COUNT==3'b10)begin - if(nand_size==4'h9||nand_size==4'ha||nand_size==4'hb) NAND_O <= NAND_ADDR[16:9]; - else if(nand_size==4'hc||nand_size==4'hd) NAND_O <= NAND_ADDR[24:17]; - else if(nand_size==4'h0) NAND_O <= NAND_ADDR[23:16]; - else NAND_O <= NAND_ADDR[31:24]; - end - else if(NAND_ADDR_COUNT==3'b1) begin - if(nand_size==4'h9||nand_size==4'ha||nand_size==4'hb) NAND_O <= NAND_ADDR[24:17]; - else if(nand_size==4'hc||nand_size==4'hd) NAND_O <= NAND_ADDR[32:25]; - else if(nand_size==4'h0) NAND_O <= NAND_ADDR[31:24]; - else NAND_O <= NAND_ADDR[37:32]; - end - end - else if((WAIT_NUM(256-NAND_ADDR[7:0]))? (256-NAND_ADDR[7:0]) : NAND_OP_NUM; - else if(now_oob) - READ_MAX_COUNT <= (NAND_OP_NUM>(16-NAND_ADDR[3:0]))? (16-NAND_ADDR[3:0]) : NAND_OP_NUM; - else - READ_MAX_COUNT <= (NAND_OP_NUM>(256-NAND_ADDR[7:0]))? (256-NAND_ADDR[7:0]) : NAND_OP_NUM; - end - - 4'h0, - 4'h1, - 4'h2, - 4'h3: begin - NAND_ADDR[10:0] <= 11'h0; - NAND_ADDR[11] <= spare_op&(~main_op); - NAND_ADDR[35:16] <= NAND_ADDR[35:16] +1'b1; - if(spare_op && main_op) - READ_MAX_COUNT <= (NAND_OP_NUM>(op_scope-NAND_ADDR[11:0]))? (op_scope-NAND_ADDR[11:0]) : NAND_OP_NUM; - else if(spare_op) - READ_MAX_COUNT <= (NAND_OP_NUM>(op_scope-NAND_ADDR[5:0])) ? (op_scope-NAND_ADDR[5:0]) : NAND_OP_NUM; - else - READ_MAX_COUNT <= (NAND_OP_NUM>(op_scope-NAND_ADDR[10:0]))? (op_scope-NAND_ADDR[10:0]) : NAND_OP_NUM; - end - 4'h4: begin - NAND_ADDR[11:0] <= 12'h0; - NAND_ADDR[12] <= spare_op&(~main_op); - NAND_ADDR[35:16] <= NAND_ADDR[35:16] +1'b1; - if(spare_op && main_op) - READ_MAX_COUNT <= (NAND_OP_NUM>(op_scope-NAND_ADDR[12:0]))? (op_scope-NAND_ADDR[12:0]) : NAND_OP_NUM; - else if(spare_op) - READ_MAX_COUNT <= (NAND_OP_NUM>(op_scope-NAND_ADDR[6:0])) ? (op_scope-NAND_ADDR[6:0]) : NAND_OP_NUM; - else - READ_MAX_COUNT <= (NAND_OP_NUM>(op_scope-NAND_ADDR[11:0]))? (op_scope-NAND_ADDR[11:0]) : NAND_OP_NUM; - end - 4'h5, - 4'h6, - 4'h7: begin - NAND_ADDR[12:0] <= 13'h0; - NAND_ADDR[13] <= spare_op&(~main_op); - NAND_ADDR[35:16] <= NAND_ADDR[35:16] +1'b1; - if(spare_op && main_op) - READ_MAX_COUNT <= (NAND_OP_NUM>(op_scope-NAND_ADDR[13:0]))? (op_scope-NAND_ADDR[13:0]) : NAND_OP_NUM; - else if(spare_op) - READ_MAX_COUNT <= (NAND_OP_NUM>(op_scope-NAND_ADDR[7:0])) ? (op_scope-NAND_ADDR[7:0]) : NAND_OP_NUM; - else - READ_MAX_COUNT <= (NAND_OP_NUM>(op_scope-NAND_ADDR[12:0]))? (op_scope-NAND_ADDR[12:0]) : NAND_OP_NUM; - end - default: begin end - endcase - end - - READ_TRANSFER: - begin - if(~NAND_IORDY) - begin - if (~DMA_OP_DONE && ~NAND_HIT) - begin - NAND_DMA_REQ <= 1'b1; - end - else if(NAND_DMA_REQ && NAND_HIT) - begin - NAND_DMA_REQ <= 1'b0; - DMA_OP_DONE <= 1'b1; - ADDR_pointer <= 2'b0; - WAIT_NUM <= nand_timing[7:0]; - end - end - else if((data_count != READ_MAX_COUNT) && ~NAND_CE_) - begin - if ((~DMA_OP_DONE||DMA_OP_DONE &&ADDR_pointer==2'h3&&WAIT_NUM==2&&(data_count < (READ_MAX_COUNT-3'h4))) && ~NAND_HIT ) - begin - NAND_DMA_REQ <= 1'b1; - end - else if(NAND_HIT && NAND_DMA_REQ) begin - NAND_DMA_REQ <= 1'b0; - DMA_OP_DONE <= 1'b1; - if(data_count == READ_MAX_COUNT -1'b1) begin - data_count <= READ_MAX_COUNT; - end - end - - if ((WAIT_NUM > (nand_timing[7:0]-HOLD_NUM+1'b1))&&(DMA_OP_DONE||NAND_HIT)) begin - NAND_RD_ <= 1'b1; - WAIT_NUM <= WAIT_NUM - 1'b1; - end - else if ((WAIT_NUM > 1) && (DMA_OP_DONE&&~NAND_DMA_REQ) ) - begin - NAND_RD_ <= 1'b0; - WAIT_NUM <= WAIT_NUM - 1'b1; - end - else if((WAIT_NUM==1)&& (DMA_OP_DONE)) - begin - NAND_RD_ <= 1'b1; - WAIT_NUM <= nand_timing[7:0]; - ADDR_pointer <= ADDR_pointer + 1'b1; - if(data_count!=READ_MAX_COUNT -1'b1) data_count <= data_count + 1'b1; - if(NAND_OP_NUM!=32'b0) NAND_OP_NUM <= NAND_OP_NUM - 1'b1; - if(ADDR_pointer==2'b0) NAND_DAT_O_RD[7:0] <= NAND_I; - else if(ADDR_pointer==2'b01) NAND_DAT_O_RD[15:8] <= NAND_I; - else if(ADDR_pointer==2'b10) NAND_DAT_O_RD[23:16] <= NAND_I; - else if(ADDR_pointer==2'b11) begin - NAND_DAT_O_RD[31:24] <= NAND_I; - DMA_OP_DONE <= 1'b0; - end - end - end - else - begin - NAND_DMA_REQ <= 1'b0; - data_count <= 14'b0; - NAND_STATE <= NAND_IDLE; - WAIT_NUM <= nand_timing[7:0]; - if(NAND_OP_NUM==32'b0) begin - NAND_GO <= 1'b0; - NAND_DONE <= 1'b1; - NAND_CE_ <= 1'b1; - end - else begin - NAND_GO <= 1'b1; - NAND_DONE <= 1'b0; - NAND_CE_ <= 1'b0; - end - end - end - - WRITE_START: begin - if(PRE_STATE == COMMAND_IN&&COMMAND!=8'h80) begin - NAND_CE_ <= 1'b0; - NAND_CLE <= 1'b0; - NAND_ALE <= 1'b0; - NAND_WR_ <= 1'b1; - WAIT_NUM <= nand_timing[7:0]; - PRE_STATE <= WRITE_START; - NAND_STATE<= COMMAND_IN; - COMMAND <= 8'h80; - end - else if(PRE_STATE == COMMAND_IN) begin - NAND_CE_ <= 1'b0; - NAND_CLE <= 1'b0; - NAND_ALE <= 1'b0; - NAND_WR_ <= 1'b1; - WAIT_NUM <= nand_timing[7:0]; - PRE_STATE <= WRITE_START; - NAND_STATE<= ADDR_4_RD_WR; - NAND_ADDR_COUNT <= (nand_size==4'h9||nand_size==4'ha||nand_size==4'hb) ? 3'b011 : (nand_size==4'h0||nand_size==4'hc||nand_size==4'hd) ? 3'b100:3'b101; - end - else if(PRE_STATE==ADDR_4_RD_WR) begin - NAND_CE_ <= 1'b0; - NAND_CLE <= 1'b0; - NAND_ALE <= 1'b0; - NAND_WR_ <= 1'b1; - ADDR_pointer<= 2'b0; - data_count <= 14'h0; - WAIT_NUM <= nand_timing[7:0]; - NAND_STATE <= WRITE_DATA; - case(nand_size) - 4'h9, - 4'ha, - 4'hb, - 4'hc, - 4'hd: - begin - NAND_ADDR[7:0] <= 8'h0; - NAND_ADDR[30:8] <= spare_op&& (~main_op)? (NAND_ADDR[30:8] +2'b10) : now_up_half ? NAND_ADDR[30:8] : (NAND_ADDR[30:8] +1'b1); - if(spare_op && main_op&&~now_oob) - WRITE_MAX_COUNT <= (NAND_OP_NUM>(256-NAND_ADDR[7:0]))? (256-NAND_ADDR[7:0]) : NAND_OP_NUM; - else if(now_oob) - WRITE_MAX_COUNT <= (NAND_OP_NUM>(16-NAND_ADDR[3:0])) ? (16-NAND_ADDR[3:0]) : NAND_OP_NUM; - else - WRITE_MAX_COUNT <= (NAND_OP_NUM>(256-NAND_ADDR[7:0]))? (256-NAND_ADDR[7:0]) : NAND_OP_NUM; - end - - 4'h0, - 4'h1, - 4'h2, - 4'h3: begin - NAND_ADDR[10:0] <= 11'h0; - NAND_ADDR[11] <= spare_op&(~main_op); - NAND_ADDR[35:16] <= NAND_ADDR[35:16] +1'b1; - if(spare_op && main_op) - WRITE_MAX_COUNT <= (NAND_OP_NUM>(op_scope-NAND_ADDR[11:0]))? (op_scope-NAND_ADDR[11:0]) : NAND_OP_NUM; - else if(spare_op) - WRITE_MAX_COUNT <= (NAND_OP_NUM>(op_scope-NAND_ADDR[5:0])) ? (op_scope-NAND_ADDR[5:0]) : NAND_OP_NUM; - else - WRITE_MAX_COUNT <= (NAND_OP_NUM>(op_scope-NAND_ADDR[10:0]))? (op_scope-NAND_ADDR[10:0]) : NAND_OP_NUM; - end - 4'h4: begin - NAND_ADDR[11:0] <= 12'h0; - NAND_ADDR[12] <= spare_op&(~main_op); - NAND_ADDR[35:16] <= NAND_ADDR[35:16] +1'b1; - if(spare_op && main_op) - WRITE_MAX_COUNT <= (NAND_OP_NUM>(op_scope-NAND_ADDR[12:0]))? (op_scope-NAND_ADDR[12:0]) : NAND_OP_NUM; - else if(spare_op) - WRITE_MAX_COUNT <= (NAND_OP_NUM>(op_scope-NAND_ADDR[6:0])) ? (op_scope-NAND_ADDR[6:0]) : NAND_OP_NUM; - else - WRITE_MAX_COUNT <= (NAND_OP_NUM>(op_scope-NAND_ADDR[11:0]))? (op_scope-NAND_ADDR[11:0]) : NAND_OP_NUM; - end - 4'h5, - 4'h6, - 4'h7: begin - NAND_ADDR[12:0] <= 13'h0; - NAND_ADDR[13] <= spare_op&(~main_op); - NAND_ADDR[35:16] <= NAND_ADDR[35:16] +1'b1; - if(spare_op && main_op) - WRITE_MAX_COUNT <= (NAND_OP_NUM>(op_scope-NAND_ADDR[13:0]))? (op_scope-NAND_ADDR[13:0]) : NAND_OP_NUM; - else if(spare_op) - WRITE_MAX_COUNT <= (NAND_OP_NUM>(op_scope-NAND_ADDR[7:0])) ? (op_scope-NAND_ADDR[7:0]) : NAND_OP_NUM; - else - WRITE_MAX_COUNT <= (NAND_OP_NUM>(op_scope-NAND_ADDR[12:0]))? (op_scope-NAND_ADDR[12:0]) : NAND_OP_NUM; - end - default: begin end - endcase - - end - end - - WRITE_DATA: - begin - if(data_count != WRITE_MAX_COUNT ) - begin - if(~DMA_OP_DONE&&~NAND_HIT) - NAND_DMA_REQ <= 1'b1; - else if(DMA_OP_DONE&&~NAND_HIT&&ADDR_pointer==2'h3&&WAIT_NUM==2&&(data_count < (WRITE_MAX_COUNT-3'h4))) - NAND_DMA_REQ <= 1'b1; - else if(NAND_DMA_REQ && NAND_HIT) begin - NAND_DMA_REQ <= 1'b0; - ADDR_pointer <= 2'b0; - DMA_OP_DONE <= 1'b1; - NAND_DAT_I_WR <= DAT_I; - end - - if ((WAIT_NUM > (nand_timing[7:0]-HOLD_NUM+1'b1))&&(DMA_OP_DONE||NAND_HIT)) begin - NAND_WR_ <= 1'b1; - WAIT_NUM <= WAIT_NUM - 1'b1; - end - else if ((WAIT_NUM > 1'b1) && DMA_OP_DONE) begin - NAND_WR_ <= 1'b0; - WAIT_NUM <= WAIT_NUM - 1'b1; - if (ADDR_pointer ==2'b0) - NAND_O <= NAND_DAT_I_WR[7:0]; - else if (ADDR_pointer ==2'b1) - NAND_O <= NAND_DAT_I_WR[15:8]; - else if (ADDR_pointer ==2'b10) - NAND_O<= NAND_DAT_I_WR[23:16]; - else if (ADDR_pointer ==2'b11) - begin - NAND_O <= NAND_DAT_I_WR[31:24]; - end - end - else if((WAIT_NUM == 1'b1)&&DMA_OP_DONE) begin - NAND_WR_ <= 1'b1; - WAIT_NUM <= nand_timing[7:0]; - ADDR_pointer <= ADDR_pointer + 1'b1; - if(ADDR_pointer ==2'b11) begin - DMA_OP_DONE <= 1'b0; - if(NAND_OP_NUM >=32'h4) - NAND_OP_NUM <= NAND_OP_NUM - 3'b100; - else - NAND_OP_NUM <= 32'h0; - if(NAND_OP_NUM == 32'h4) - data_count <= WRITE_MAX_COUNT; - else - data_count <= data_count + 3'b100; - end - end - end - else if(PRE_STATE != COMMAND_IN && COMMAND==8'h80) - begin - NAND_CE_ <= 1'b0; - NAND_CLE <= 1'b0; - NAND_ALE <= 1'b0; - NAND_WR_ <= 1'b1; - NAND_STATE <= COMMAND_IN; - PRE_STATE <= WRITE_DATA; - COMMAND <= 8'h10; - DMA_OP_DONE <= 1'b0; - WAIT_NUM <= nand_timing[7:0]; - end - else if(PRE_STATE == COMMAND_IN && COMMAND==8'h10) begin - NAND_CE_ <= 1'b0; - NAND_STATE <= NAND_IORDY ? WRITE_DATA:PROGRAM; - end - else if(PRE_STATE == PROGRAM && COMMAND==8'h10) begin - NAND_STATE <= COMMAND_IN; - PRE_STATE <= WRITE_DATA; - COMMAND <= 8'h70; - WAIT_NUM <= nand_timing[7:0]; - NAND_CE_ <= 1'b0; - end - else if(PRE_STATE == COMMAND_IN && COMMAND==8'h70) begin - NAND_CE_ <= 1'b0; - NAND_CLE <= 1'b0; - NAND_ALE <= 1'b0; - NAND_WR_ <= 1'b1; - NAND_RD_ <= 1'b1; - NAND_STATE<= READ_STATUS; - PRE_STATE <= WRITE_DATA; - WAIT_NUM <= nand_timing[7:0]+2'b11; - NAND_EN_ <= 1'b1; - end - else if(PRE_STATE == READ_STATUS) - begin - if(status[0]==0 && NAND_OP_NUM ==32'b0) - begin - NAND_STATE <= NAND_IDLE; - NAND_DONE <= 1'b1; - NAND_DMA_REQ <= 1'b0; - end - else if(status[0]==0) - begin - NAND_STATE <= NAND_IDLE; - NAND_DONE <= 1'b0; - end - else - begin - NAND_STATE <= PROGRAM_FAIL; - NAND_DONE <= 1'b1; - NAND_DMA_REQ<= 1'b0; - end - end - else - begin - NAND_STATE <= NAND_IDLE; - NAND_DONE <=1; - NAND_DMA_REQ <= 1'b0; - end - end - PROGRAM: - begin - if(NAND_IORDY==1'b0) begin - NAND_STATE <= PROGRAM; - end - else begin - PRE_STATE <= PROGRAM; - NAND_STATE <= WRITE_DATA; - DMA_OP_DONE <= 1'b0; - end - end - RESET: - begin - if(NAND_IORDY==1'b1) begin - NAND_STATE <= RESET; - end - else begin - NAND_STATE <= WAIT_RESET; - PRE_STATE <= RESET; - end - end - WAIT_RESET: - begin - if(NAND_IORDY) begin - NAND_STATE <= NAND_IDLE; - PRE_STATE <= WAIT_RESET; - NAND_CE_ <= 1'b1; - NAND_DONE <= 1'b1; - NAND_GO <= 1'b0; - end - else - NAND_STATE <= WAIT_RESET; - end - - READ_STATUS: - begin - if(WAIT_NUM >= (nand_timing[7:0]- HOLD_NUM+1'b1)) begin - WAIT_NUM <= WAIT_NUM - 1'b1; - NAND_STATE <= READ_STATUS; - NAND_RD_ <= 1'b1; - NAND_EN_ <= 1'b1; - end - else if(WAIT_NUM && WAIT_NUM >1 ) begin - WAIT_NUM <= WAIT_NUM - 1'b1; - NAND_STATE <= READ_STATUS; - NAND_RD_ <= 1'b0; - NAND_EN_ <= 1'b1; - end - else if(WAIT_NUM == 1) begin - WAIT_NUM <= WAIT_NUM - 1'b1; - NAND_STATE <= READ_STATUS; - status <= NAND_I; - NAND_RD_ <= 1'b1; - NAND_EN_ <= 1'b1; - end - else if(WAIT_NUM==8'b0) begin - NAND_RD_ <= 1'b1; - NAND_CE_ <= 1'b0; - PRE_STATE <= READ_STATUS; - NAND_STATE <= PRE_STATE; - WAIT_NUM <= nand_timing[7:0]; - if(PRE_STATE == 5'h1) - NAND_DONE <= 1'b1; - end - else begin - WAIT_NUM <= WAIT_NUM - 1'b1; - NAND_STATE <= READ_STATUS; - NAND_RD_ <= 1'b1; - NAND_EN_ <= 1'b1; - end - end - - PROGRAM_FAIL,ERASE_FAIL: - begin - NAND_STATE <= NAND_IDLE; - NAND_CE_ <= 1'b1; - NAND_DONE <= 1'b1; - end - ERASE: - begin - if( (PRE_STATE != ADDR_4_ERASE_ID) && (COMMAND == 8'h60) ) - begin - NAND_STATE <= ADDR_4_ERASE_ID; - PRE_STATE <= ERASE; - WAIT_NUM <= nand_timing[7:0]; - NAND_ADDR_COUNT <= (nand_size==4'h9||nand_size==4'ha||nand_size==4'hb||nand_size==4'h0) ? 3'b10:3'b011; - end - else if( (PRE_STATE != COMMAND_IN) && (COMMAND == 8'h60) ) - begin - NAND_STATE <= COMMAND_IN; - PRE_STATE <= ERASE; - COMMAND <= 8'hD0; - WAIT_NUM <= nand_timing[7:0]; - end - else if(PRE_STATE==COMMAND_IN && COMMAND== 8'hd0) - begin - NAND_STATE <= NAND_IORDY ? ERASE : WAIT_ERASE; - end - end - WAIT_ERASE: - begin - if(NAND_IORDY==1'b0) begin - NAND_STATE <= WAIT_ERASE; - end - else if(NAND_IORDY && PRE_STATE == COMMAND_IN && COMMAND == 8'h60) - begin - NAND_STATE <= ERASE; - PRE_STATE <= WAIT_ERASE; - end - else if(NAND_IORDY && COMMAND ==8'hd0 ) - begin - NAND_OP_NUM <= NAND_OP_NUM - 1'b1; - NAND_STATE <= COMMAND_IN; - PRE_STATE <= WAIT_ERASE; - COMMAND <= 8'h70; - WAIT_NUM <= nand_timing[7:0]; - NAND_CE_ <= 1'b0; - end - else if(NAND_IORDY && PRE_STATE == COMMAND_IN && COMMAND==8'h70) - begin - NAND_CE_ <= 1'b0; - NAND_CLE <= 1'b0; - NAND_ALE <= 1'b0; - NAND_WR_ <= 1'b1; - NAND_RD_ <= 1'b1; - NAND_STATE<= READ_STATUS; - PRE_STATE <= WAIT_ERASE; - WAIT_NUM <= nand_timing[7:0]+2'b11; - NAND_EN_ <= 1'b1; - end - else if(NAND_IORDY && PRE_STATE == READ_STATUS) - begin - if(status[0]==1'b0 && (NAND_OP_NUM==32'b0 || ERASE_SERIAL == 1'b0) ) - begin - NAND_STATE <= NAND_IDLE; - NAND_CE_ <= 1'b1; - NAND_DONE <= 1'b1; - NAND_ADDR <= 36'h0; - ERASE_SERIAL<= 1'b0; - end - else if(status[0]== 1'b0 && NAND_OP_NUM!=32'b0) - begin - NAND_STATE <= COMMAND_IN; - PRE_STATE <= WAIT_ERASE; - COMMAND <= 8'h60; - NAND_DONE <= 1'b0; - WAIT_NUM <= nand_timing[7:0]; - NAND_CE_ <= 1'b0; - NAND_EN_ <= 1'b0; - if(nand_size[3]) NAND_ADDR[27:14] <= NAND_ADDR[27:14] + 1'b1; - else if(nand_size==4'h1||nand_size==4'h2||nand_size==4'h3) NAND_ADDR[35:22] <= NAND_ADDR[35:22] + 1'b1; - else if(nand_size==4'h4) NAND_ADDR[33:22] <= NAND_ADDR[33:22] + 1'b1; - else if(nand_size==4'h5) NAND_ADDR[33:24] <= NAND_ADDR[33:24] + 1'b1; - else NAND_ADDR[35:25] <= NAND_ADDR[35:25] + 1'b1; - end - else - begin - NAND_STATE <= ERASE_FAIL; - NAND_DONE <= 1'b1; - end - end - else begin - NAND_STATE <= NAND_IDLE; - NAND_CE_ <= 1'b1; - NAND_DONE <= 1'b1; - end - end - READ_ID: - begin - if((PRE_STATE != ADDR_4_ERASE_ID) && COMMAND == 8'h90) - begin - NAND_STATE <= ADDR_4_ERASE_ID; - PRE_STATE <= READ_ID; - WAIT_NUM <= nand_timing[7:0]+1'b1; - READ_ID_NUM <= nand_id_num; - NAND_ADDR_COUNT <= 3'b1; - end - else if (COMMAND != 8'h70) - begin - if (READ_ID_NUM!=3'b0) - begin - NAND_EN_ <= 1'b1; - if(WAIT_NUM>(nand_timing[7:0]+1'b1-HOLD_NUM)) - begin - NAND_RD_ <= 1'b1; - WAIT_NUM <= WAIT_NUM - 1'b1; - NAND_STATE<= READ_ID; - end - else if (WAIT_NUM > 1) - begin - WAIT_NUM <= WAIT_NUM - 1'b1; - NAND_RD_ <= 1'b0; - NAND_STATE<= READ_ID; - end - else if(WAIT_NUM==1) - begin - NAND_STATE <= READ_ID; - NAND_RD_ <= 1'b1; - WAIT_NUM <= nand_timing[7:0]; - READ_ID_NUM <= READ_ID_NUM - 2'b1; - if (READ_ID_NUM==3'b01) - ID_INFORM[7:0] <= NAND_I; - else if (READ_ID_NUM==3'b10) - ID_INFORM[15:8] <= NAND_I; - else if (READ_ID_NUM==3'b11) - ID_INFORM[23:16] <= NAND_I; - else if (READ_ID_NUM==3'b100) - ID_INFORM[31:24] <= NAND_I; - else if (READ_ID_NUM==3'b101) - ID_INFORM[39:32] <= NAND_I; - else if (READ_ID_NUM==3'b110) - ID_INFORM[47:40] <= NAND_I; - end - end - else - begin - NAND_STATE <= COMMAND_IN; - PRE_STATE <= READ_ID; - COMMAND <= 8'h70; - WAIT_NUM <= nand_timing[7:0]; - NAND_CE_ <= 1'b0; - NAND_EN_ <= 1'b0; - end - end - else - begin - NAND_STATE <= ID_TO_STATUS; - PRE_STATE <= READ_ID; - NAND_EN_ <= 1'b1; - COMMAND <= 8'h70; - end - end - ID_TO_STATUS: - begin - if(PRE_STATE != READ_STATUS) - begin - NAND_CE_ <= 1'b0; - NAND_CLE <= 1'b0; - NAND_ALE <= 1'b0; - NAND_WR_ <= 1'b1; - NAND_RD_ <= 1'b1; - NAND_STATE<= READ_STATUS; - PRE_STATE <= ID_TO_STATUS; - WAIT_NUM <= nand_timing[7:0]+2'b11; - NAND_EN_ <= 1'b1; - end - else - begin - NAND_DONE <= 1'b1; - NAND_GO <= 1'b0; - NAND_STATE <= NAND_IDLE; - NAND_CE_ <= 1'b1; - end - end - default : - begin - NAND_STATE <= NAND_IDLE; - NAND_CE_ <= 1'b1; - NAND_GO <= 1'b0; - NAND_DONE <= 1'b0; - NAND_DMA_REQ <= 1'b0; - end - endcase - end -end -endmodule diff --git a/resources/soc/rtl/APB_DEV/URT/raminfr.v b/resources/soc/rtl/APB_DEV/URT/raminfr.v deleted file mode 100644 index ddb6ae5..0000000 --- a/resources/soc/rtl/APB_DEV/URT/raminfr.v +++ /dev/null @@ -1,62 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -module raminfr(clk, we, a, dpra, di, dpo); - -parameter addr_width = 4; -parameter data_width = 8; -parameter depth = 16; - -input clk; -input we; -input [addr_width-1:0] a; -input [addr_width-1:0] dpra; -input [data_width-1:0] di; -output [data_width-1:0] dpo; -reg [data_width-1:0] ram [depth-1:0]; - -wire [data_width-1:0] di; -wire [addr_width-1:0] a; -wire [addr_width-1:0] dpra; - -always @(posedge clk) begin - if (we) - ram[a] <= di; -end -reg [data_width-1:0] dpo; - -always @(posedge clk) - dpo <= ram[dpra]; - -endmodule - diff --git a/resources/soc/rtl/APB_DEV/URT/uart_defines.h b/resources/soc/rtl/APB_DEV/URT/uart_defines.h deleted file mode 100644 index 76cd1dd..0000000 --- a/resources/soc/rtl/APB_DEV/URT/uart_defines.h +++ /dev/null @@ -1,119 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -`define UART_ADDR_WIDTH 3 -`define UART_DATA_WIDTH 8 - -// Register addresses -`define UART_REG_RB `UART_ADDR_WIDTH'd0 // receiver buffer -`define UART_REG_TR `UART_ADDR_WIDTH'd0 // transmitter -`define UART_REG_IE `UART_ADDR_WIDTH'd1 // Interrupt enable -`define UART_REG_II `UART_ADDR_WIDTH'd2 // Interrupt identification -`define UART_REG_FC `UART_ADDR_WIDTH'd2 // FIFO control -`define UART_REG_LC `UART_ADDR_WIDTH'd3 // Line Control -`define UART_REG_MC `UART_ADDR_WIDTH'd4 // Modem control -`define UART_REG_LS `UART_ADDR_WIDTH'd5 // Line status -`define UART_REG_MS `UART_ADDR_WIDTH'd6 // Modem status -`define UART_REG_SR `UART_ADDR_WIDTH'd7 // Scratch register -`define UART_REG_DL1 `UART_ADDR_WIDTH'd0 // Divisor latch bytes (1-2) -`define UART_REG_DL2 `UART_ADDR_WIDTH'd1 - -// Interrupt Enable register bits -`define UART_IE_RDA 0 // Received Data available interrupt -`define UART_IE_THRE 1 // Transmitter Holding Register empty interrupt -`define UART_IE_RLS 2 // Receiver Line Status Interrupt -`define UART_IE_MS 3 // Modem Status Interrupt - -// Interrupt Identification register bits -`define UART_II_IP 0 // Interrupt pending when 0 -`define UART_II_II 3:1 // Interrupt identification - -// Interrupt identification values for bits 3:1 -`define UART_II_RLS 3'b011 // Receiver Line Status -`define UART_II_RDA 3'b010 // Receiver Data available -`define UART_II_TI 3'b110 // Timeout Indication -`define UART_II_THRE 3'b001 // Transmitter Holding Register empty -`define UART_II_MS 3'b000 // Modem Status - -// FIFO Control Register bits -`define UART_FC_TL 1:0 // Trigger level - -// FIFO trigger level values -`define UART_FC_1 2'b00 -`define UART_FC_4 2'b01 -`define UART_FC_8 2'b10 -`define UART_FC_14 2'b11 - -// Line Control register bits -`define UART_LC_BITS 1:0 // bits in character -`define UART_LC_SB 2 // stop bits -`define UART_LC_PE 3 // parity enable -`define UART_LC_EP 4 // even parity -`define UART_LC_SP 5 // stick parity -`define UART_LC_BC 6 // Break control -`define UART_LC_DL 7 // Divisor Latch access bit - -// Modem Control register bits -`define UART_MC_DTR 0 -`define UART_MC_RTS 1 -`define UART_MC_OUT1 2 -`define UART_MC_OUT2 3 -`define UART_MC_LB 4 // Loopback mode - -// Line Status Register bits -`define UART_LS_DR 0 // Data ready -`define UART_LS_OE 1 // Overrun Error -`define UART_LS_PE 2 // Parity Error -`define UART_LS_FE 3 // Framing Error -`define UART_LS_BI 4 // Break interrupt -`define UART_LS_TFE 5 // Transmit FIFO is empty -`define UART_LS_TE 6 // Transmitter Empty indicator -`define UART_LS_EI 7 // Error indicator - -// Modem Status Register bits -`define UART_MS_DCTS 0 // Delta signals -`define UART_MS_DDSR 1 -`define UART_MS_TERI 2 -`define UART_MS_DDCD 3 -`define UART_MS_CCTS 4 // Complement signals -`define UART_MS_CDSR 5 -`define UART_MS_CRI 6 -`define UART_MS_CDCD 7 - -// FIFO parameter defines - -`define UART_FIFO_WIDTH 8 -`define UART_FIFO_DEPTH 16 -`define UART_FIFO_POINTER_W 4 -`define UART_FIFO_COUNTER_W 5 -`define UART_FIFO_REC_WIDTH 11 diff --git a/resources/soc/rtl/APB_DEV/URT/uart_receiver.v b/resources/soc/rtl/APB_DEV/URT/uart_receiver.v deleted file mode 100644 index e09d50d..0000000 --- a/resources/soc/rtl/APB_DEV/URT/uart_receiver.v +++ /dev/null @@ -1,288 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -`include "uart_defines.h" - -module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable, - counter_t, rf_count, rf_data_out, rf_error_bit, - rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse); - -input clk; -input wb_rst_i; -input [7:0] lcr; -input rf_pop; -input srx_pad_i; -input enable; -input rx_reset; -input lsr_mask; - -output [9:0] counter_t; -output [`UART_FIFO_COUNTER_W-1:0] rf_count; -output [`UART_FIFO_REC_WIDTH-1:0] rf_data_out; -output rf_overrun; -output rf_error_bit; -output [3:0] rstate; -output rf_push_pulse; - -reg [3:0] rstate; -reg [3:0] rcounter16; -reg [2:0] rbit_counter; -reg [7:0] rshift; -reg rparity; -reg rparity_error; -reg rframing_error; -reg rbit_in; -reg rparity_xor; -reg [7:0] counter_b; -reg rf_push_q; - -reg [`UART_FIFO_REC_WIDTH-1:0] rf_data_in; -wire[`UART_FIFO_REC_WIDTH-1:0] rf_data_out; -wire rf_push_pulse; -reg rf_push; -wire rf_pop; -wire rf_overrun; -wire[`UART_FIFO_COUNTER_W-1:0] rf_count; -wire rf_error_bit; -wire break_error = (counter_b == 0); - -uart_rfifo #(`UART_FIFO_REC_WIDTH) fifo_rx( - .clk ( clk ), - .wb_rst_i ( wb_rst_i ), - .data_in ( rf_data_in ), - .data_out ( rf_data_out ), - .push ( rf_push_pulse), - .pop ( rf_pop ), - .overrun ( rf_overrun ), - .count ( rf_count ), - .error_bit ( rf_error_bit ), - .fifo_reset ( rx_reset ), - .reset_status( lsr_mask ) -); - -wire rcounter16_eq_7 = (rcounter16 == 4'd7); -wire rcounter16_eq_0 = (rcounter16 == 4'd0); -wire rcounter16_eq_1 = (rcounter16 == 4'd1); - -wire [3:0] rcounter16_minus_1 = rcounter16 - 1'b1; - -parameter sr_idle = 4'd0; -parameter sr_rec_start = 4'd1; -parameter sr_rec_bit = 4'd2; -parameter sr_rec_parity = 4'd3; -parameter sr_rec_stop = 4'd4; -parameter sr_check_parity = 4'd5; -parameter sr_rec_prepare = 4'd6; -parameter sr_end_bit = 4'd7; -parameter sr_ca_lc_parity = 4'd8; -parameter sr_wait1 = 4'd9; -parameter sr_push = 4'd10; - - -always @(posedge clk ) begin - if (wb_rst_i) begin - rstate <= sr_idle; - rbit_in <= 1'b0; - rcounter16 <= 0; - rbit_counter <= 0; - rparity_xor <= 1'b0; - rframing_error <= 1'b0; - rparity_error <= 1'b0; - rparity <= 1'b0; - rshift <= 0; - rf_push <= 1'b0; - rf_data_in <= 0; - end - else if (enable) begin - case (rstate) - sr_idle : begin - rf_push <= 1'b0; - rf_data_in <= 0; - rcounter16 <= 4'b1110; - if (srx_pad_i==1'b0 & ~break_error) begin - rstate <= sr_rec_start; - end - end - sr_rec_start : begin - rf_push <= 1'b0; - if (rcounter16_eq_7) - if (srx_pad_i==1'b1) - rstate <= sr_idle; - else - rstate <= sr_rec_prepare; - else rstate<=rstate; - rcounter16 <= rcounter16_minus_1; - end - sr_rec_prepare: begin - case (lcr[1:0]) - 2'b00 : rbit_counter <= 3'b100; - 2'b01 : rbit_counter <= 3'b101; - 2'b10 : rbit_counter <= 3'b110; - 2'b11 : rbit_counter <= 3'b111; - endcase - if (rcounter16_eq_0) begin - rstate <= sr_rec_bit; - rcounter16 <= 4'b1110; - rshift <= 0; - end - else - rstate <= sr_rec_prepare; - rcounter16 <= rcounter16_minus_1; - end - sr_rec_bit : begin - if (rcounter16_eq_0) rstate <= sr_end_bit; - if (rcounter16_eq_7) - case (lcr[1:0]) - 2'b00 : rshift[4:0] <= {srx_pad_i, rshift[4:1]}; - 2'b01 : rshift[5:0] <= {srx_pad_i, rshift[5:1]}; - 2'b10 : rshift[6:0] <= {srx_pad_i, rshift[6:1]}; - 2'b11 : rshift[7:0] <= {srx_pad_i, rshift[7:1]}; - endcase - rcounter16 <= rcounter16_minus_1; - end - sr_end_bit : begin - if (rbit_counter==3'b0) - if (lcr[`UART_LC_PE]) - rstate <= sr_rec_parity; - else begin - rstate <= sr_rec_stop; - rparity_error<= 1'b0; - end - else begin - rstate <= sr_rec_bit; - rbit_counter <= rbit_counter - 1'b1; - end - rcounter16 <= 4'b1110; - end - sr_rec_parity : begin - if (rcounter16_eq_7) begin - rparity <= srx_pad_i; - rstate <= sr_ca_lc_parity; - end - rcounter16 <= rcounter16_minus_1; - end - sr_ca_lc_parity:begin - rcounter16 <= rcounter16_minus_1; - rparity_xor <= ^{rshift,rparity}; - rstate <= sr_check_parity; - end - sr_check_parity: begin - case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]}) - 2'b00: rparity_error <= rparity_xor == 0; - 2'b01: rparity_error <= ~rparity; - 2'b10: rparity_error <= rparity_xor == 1; - 2'b11: rparity_error <= rparity; - endcase - rcounter16 <= rcounter16_minus_1; - rstate <= sr_wait1; - end - sr_wait1 : - if (rcounter16_eq_0) begin - rstate <= sr_rec_stop; - rcounter16 <= 4'b1110; - end - else rcounter16 <= rcounter16_minus_1; - sr_rec_stop : begin - if (rcounter16_eq_7) begin - rframing_error <= !srx_pad_i; - rstate <= sr_push; - end - rcounter16 <= rcounter16_minus_1; - end - sr_push : begin - if(srx_pad_i | break_error) begin - if(break_error) - rf_data_in <= {8'b0, 3'b100}; - else - rf_data_in <= {rshift, 1'b0, rparity_error, rframing_error}; - rf_push <= 1'b1; - rstate <= sr_idle; - end - else if(~rframing_error) begin - rf_data_in <= {rshift, 1'b0, rparity_error, rframing_error}; - rf_push <= 1'b1; - rcounter16 <= 4'b1110; - rstate <= sr_rec_start; - end - - end - default : rstate <= sr_idle; - endcase - end -end - -always @ (posedge clk ) begin - if(wb_rst_i) rf_push_q <= 0; - else rf_push_q <= rf_push; -end - -assign rf_push_pulse = rf_push & ~rf_push_q; - - -reg [9:0] toc_value; - -always @(lcr) - case (lcr[3:0]) - 4'b0000 : toc_value = 447; - 4'b0100 : toc_value = 479; - 4'b0001, 4'b1000 : toc_value = 511; - 4'b1100 : toc_value = 543; - 4'b0010, 4'b0101, 4'b1001 : toc_value = 575; - 4'b0011, 4'b0110, 4'b1010, 4'b1101 : toc_value = 639; - 4'b0111, 4'b1011, 4'b1110 : toc_value = 703; - 4'b1111 : toc_value = 767; - endcase - -wire [7:0] brc_value; -assign brc_value = toc_value[9:2]; - -always @(posedge clk ) begin - if (wb_rst_i) counter_b <= 8'd159; - else if (srx_pad_i) counter_b <= brc_value; - else if (enable & counter_b != 8'b0) - counter_b <= counter_b - 1; -end - - -reg [9:0] counter_t; - -always @(posedge clk ) begin - if (wb_rst_i) counter_t <= 10'd639; - else if(rf_push_pulse || rf_pop || rf_count == 0) - counter_t <= toc_value; - else if (enable && counter_t != 10'b0) - counter_t <= counter_t - 1; -end - -endmodule - diff --git a/resources/soc/rtl/APB_DEV/URT/uart_regs.v b/resources/soc/rtl/APB_DEV/URT/uart_regs.v deleted file mode 100644 index 63757cd..0000000 --- a/resources/soc/rtl/APB_DEV/URT/uart_regs.v +++ /dev/null @@ -1,711 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -`include "uart_defines.h" - -`define UART_DL1 7:0 -`define UART_DL2 15:8 -`define UART_DL3 23:16 -module uart_regs (clk, rst, clk_carrier, - addr, dat_i, dat_o, we, re, - - modem_inputs, - rts_pad_o, dtr_pad_o, - stx_pad_o,TXD_i,srx_pad_i,RXD_o, - int_o, - usart_mode, - rx_en, - tx2rx_en -); -input clk; -input rst ; -input clk_carrier; -input [2:0] addr; -input [7:0] dat_i; -output [7:0] dat_o; -input we; -input re; - -output stx_pad_o; -input srx_pad_i; -input TXD_i; -output RXD_o; - -input [3:0] modem_inputs; -output rts_pad_o; -output dtr_pad_o; -output int_o; - -output usart_mode; -output tx2rx_en; -output rx_en; - -wire [3:0] modem_inputs; -reg enable; - -wire stx_pad_o; -wire srx_pad_i; -wire srx_pad; - -reg [7:0] dat_o; - -wire [2:0] addr; -wire [7:0] dat_i; - -reg [3:0] ier; -reg [3:0] iir; -reg [1:0] fcr; -reg [4:0] mcr; -reg infrared; -reg rx_pol; -reg [7:0] lcr; -reg [7:0] msr; -reg [23:0] dl; -reg start_dlc; -reg lsr_mask_d; -reg msi_reset; - -reg [15:0] dlc; -reg int_o; - -reg [3:0] trigger_level; -reg rx_reset; -reg tx_reset; -wire dlab; - -wire usart_mode; -wire usart_rx_en; -wire usart_tx_en; -wire tx2rx_en; -reg sclk_reg; -reg sclk_en_reg; -reg [7:0] mode_reg; -reg [7:0] fi_di_reg; -reg [7:0] sclk_count; -reg [2:0] repeat_reg; - -wire usart_normal; -wire usart_irda; -wire usart_t0; -wire usart_t1; -wire rx_en; -wire tx_en; -wire sclk_por; - -assign usart_normal = mode_reg[1:0]==2'h0; -assign usart_irda = mode_reg[1:0]==2'h1; -assign usart_t0 = mode_reg[1:0]==2'h2; -assign usart_t1 = mode_reg[1:0]==2'h3; -assign usart_tx_en = mode_reg[2]==1'b0; -assign usart_rx_en = mode_reg[2]==1'b1; -assign sclk_por = mode_reg[3]; -assign RXD_o = sclk_reg^sclk_por; - -assign usart_mode = usart_t0 || usart_t1; -assign rx_en = usart_normal || usart_irda || usart_mode && usart_rx_en; -assign tx_en = usart_normal || usart_irda || usart_mode && usart_tx_en; - - -always @(posedge clk ) -begin - if (rst) begin - mode_reg <= 8'h0; - fi_di_reg <= 8'h0; - repeat_reg<= 3'h4; - sclk_en_reg<= 1'b0; - end - else if (we && addr==`UART_REG_SR)begin - if(dlab) - fi_di_reg <= dat_i; - else - mode_reg <= dat_i; - end - else begin - if(enable) sclk_en_reg <= mode_reg[4]; - repeat_reg <= mode_reg[7:5]; - end -end - -always @(posedge clk) -begin - if(rst) begin - sclk_count <= 8'b0; - sclk_reg <=1'b0; - end - else if(usart_mode&&(fi_di_reg>8'h1)&&sclk_en_reg) begin - if(sclk_count == fi_di_reg[7:1]) begin - sclk_reg <= 1'b1; - sclk_count <= sclk_count + 1'b1; - end - else if(sclk_count == fi_di_reg) begin - sclk_reg <= 1'b0; - sclk_count <= 8'b0; - end - else begin - sclk_count <= sclk_count + 1'b1; - end - end - else begin - sclk_reg <=1'b0; - sclk_count <= 8'b0; - end -end - -wire cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i; -wire loopback; -wire cts, dsr, ri, dcd; -wire cts_c, dsr_c, ri_c, dcd_c; -wire rts_pad_o, dtr_pad_o; - -wire [7:0] lsr; -wire lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7; -reg lsr0r, lsr1r, lsr2r, lsr3r, lsr4r, lsr5r, lsr6r, lsr7r; -wire lsr_mask; - -assign lsr[7:0] = { lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r }; - -assign {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs; -assign {cts, dsr, ri, dcd} = ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i}; - -assign {cts_c, dsr_c, ri_c, dcd_c} = loopback ? {mcr[`UART_MC_RTS],mcr[`UART_MC_DTR],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]} - : {cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i}; - -assign dlab = lcr[`UART_LC_DL]; -assign loopback = mcr[4]; - -assign rts_pad_o = mcr[`UART_MC_RTS]; -assign dtr_pad_o = mcr[`UART_MC_DTR]; - -wire rls_int; -wire rda_int; -wire ti_int; -wire thre_int; -wire ms_int; - -wire tf_push; -reg rf_pop; -wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out; -wire rf_error_bit; -wire [`UART_FIFO_COUNTER_W-1:0] rf_count; -wire [`UART_FIFO_COUNTER_W-1:0] tf_count; -wire [2:0] tstate; -wire [3:0] rstate; -wire [9:0] counter_t; - -wire thre_set_en; -reg [7:0] block_cnt; -reg [7:0] block_value; -wire current_finish; -wire max_repeat_time; - -wire serial_out; -wire serial_out_modulated = ~ (clk_carrier & serial_out); - -uart_transmitter transmitter(.clk(clk), .wb_rst_i(rst), .lcr(lcr), .tf_push(tf_push), .wb_dat_i(dat_i), - - .tx2rx_en (tx2rx_en), - .usart_mode(usart_mode), - .srx_pad_i(TXD_i), - .enable (enable && tx_en), - .usart_t0(usart_t0), - .repeat_time(repeat_reg ), - .current_finish(current_finish), - .max_repeat_time(max_repeat_time), - - .stx_pad_o(serial_out), .tstate(tstate), .tf_count(tf_count), - .tx_reset(tx_reset), .lsr_mask(lsr_mask)); -wire rcv_pad_i; -assign rcv_pad_i = ~usart_mode ? srx_pad_i : (rx_en ? TXD_i : 1'b1); - -uart_sync_flops i_uart_sync_flops( - .rst_i (rst), - .clk_i (clk), - .stage1_rst_i (1'b0), - .stage1_clk_en_i (1'b1), - .async_dat_i (rcv_pad_i), - .sync_dat_o (srx_pad) - ); - - defparam i_uart_sync_flops.width = 1; - defparam i_uart_sync_flops.init_value = 1'b1; -wire serial_in = loopback ? serial_out : rx_pol ? ~srx_pad : srx_pad; -assign stx_pad_o = loopback ? 1'b1 : infrared ? serial_out_modulated : serial_out; - -wire rf_overrun; -wire rf_push_pulse; -uart_receiver receiver(.clk(clk), .wb_rst_i(rst), .lcr(lcr), .rf_pop(rf_pop), .srx_pad_i(serial_in), - .enable(enable && rx_en), - .counter_t(counter_t), .rf_count(rf_count), .rf_data_out(rf_data_out), .rf_error_bit(rf_error_bit), - .rf_overrun(rf_overrun), .rx_reset(rx_reset), .lsr_mask(lsr_mask), .rstate(rstate), .rf_push_pulse(rf_push_pulse)); - - -always @(dl or dlab or ier or iir or fi_di_reg or mode_reg - or lcr or lsr or msr or rf_data_out or addr ) -begin - case (addr) - `UART_REG_RB : dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3]; - `UART_REG_IE : dat_o = dlab ? dl[`UART_DL2] : ier; - `UART_REG_II : dat_o = dlab ? dl[`UART_DL3] : {4'b1100,iir}; - `UART_REG_LC : dat_o = lcr; - `UART_REG_LS : dat_o = lsr; - `UART_REG_MS : dat_o = msr; - `UART_REG_SR : dat_o = dlab ? fi_di_reg : mode_reg; - default : dat_o = 8'b0; - endcase -end - -always @(posedge clk ) -begin - if (rst) - rf_pop <= 0; - else - if (rf_pop) - rf_pop <= 0; - else - if (re && addr == `UART_REG_RB && !dlab) - rf_pop <= 1; -end - -wire lsr_mask_condition; -wire iir_read; -wire msr_read; -wire fifo_read; -wire fifo_write; - -assign lsr_mask_condition = (re && addr == `UART_REG_LS && !dlab); -assign iir_read = (re && addr == `UART_REG_II && !dlab); -assign msr_read = (re && addr == `UART_REG_MS && !dlab); -assign fifo_read = (re && addr == `UART_REG_RB && !dlab); -assign fifo_write = (we && addr == `UART_REG_TR && !dlab); - -always @(posedge clk ) -begin - if (rst) - lsr_mask_d <= 0; - else - lsr_mask_d <= lsr_mask_condition; -end - -assign lsr_mask = lsr_mask_condition && ~lsr_mask_d; - -always @(posedge clk ) -begin - if (rst) - msi_reset <= 1; - else - if (msi_reset) - msi_reset <= 0; - else - if (msr_read) - msi_reset <= 1; -end - -always @(posedge clk ) - if (rst) - lcr <= 8'b00000011; - else - if (we && addr==`UART_REG_LC) - lcr <= dat_i; - -always @(posedge clk ) - if (rst) - begin - ier <= 4'b0000; - dl[`UART_DL2] <= 8'b0; - end - else - if (we && addr==`UART_REG_IE) - if (dlab) - begin - dl[`UART_DL2] <= dat_i; - end - else - ier <= dat_i[3:0]; - else - ier<= ier; - -always @(posedge clk ) - if (rst) begin - fcr <= 2'b11; - rx_reset <= 0; - tx_reset <= 0; - dl[`UART_DL3] <= 8'h0; - end else - if (we && addr==`UART_REG_FC) begin - if(dlab) dl[`UART_DL3] <= dat_i; - else begin - fcr <= dat_i[7:6]; - rx_reset <= dat_i[1]; - tx_reset <= dat_i[2]; - end - end else begin - rx_reset <= 0; - tx_reset <= 0; - end - -always @(posedge clk ) - if (rst) begin - mcr <= 5'b0; - infrared <= 1'b0; - rx_pol <= 1'b0; end - else - if(we && addr==`UART_REG_MC) begin - mcr <= dat_i[4:0]; - infrared <= dat_i[7]; - rx_pol <= dat_i[6]; end - -assign tf_push = we & addr==`UART_REG_TR & !dlab; -always @(posedge clk ) - if (rst) - begin - dl[`UART_DL1] <= 8'b0; - start_dlc <= 1'b0; - end - else - if (we && addr==`UART_REG_TR) - if (dlab) - begin - dl[`UART_DL1] <= dat_i; - start_dlc <= 1'b1; - end - else - begin - start_dlc <= 1'b0; - end - else - begin - start_dlc <= 1'b0; - end - -always @(fcr) - case (fcr[`UART_FC_TL]) - 2'b00 : trigger_level = 1; - 2'b01 : trigger_level = 4; - 2'b10 : trigger_level = 8; - 2'b11 : trigger_level = 14; - endcase - -reg [3:0] delayed_modem_signals; -always @(posedge clk ) -begin - if (rst) - begin - msr <= 0; - delayed_modem_signals[3:0] <= 0; - end - else begin - msr[`UART_MS_DDCD:`UART_MS_DCTS] <= msi_reset ? 4'b0 : - msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ delayed_modem_signals[3:0]); - msr[`UART_MS_CDCD:`UART_MS_CCTS] <= {dcd_c, ri_c, dsr_c, cts_c}; - delayed_modem_signals[3:0] <= {dcd, ri, dsr, cts}; - end -end - -assign lsr0 = (rf_count==0 && rf_push_pulse); -assign lsr1 = rf_overrun; -assign lsr2 = rf_data_out[1]; -assign lsr3 = rf_data_out[0]; -assign lsr4 = rf_data_out[2]; -assign lsr5 = current_finish && (tf_count==5'b0 && thre_set_en); -assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == 3'd0)); -assign lsr7 = rf_error_bit | rf_overrun; - -reg lsr0_d; - -always @(posedge clk ) - if (rst) lsr0_d <= 0; - else lsr0_d <= lsr0; - -always @(posedge clk ) - if (rst) lsr0r <= 0; - else lsr0r <= (rf_count==1 && rf_pop && !rf_push_pulse || rx_reset) ? 0 : - lsr0r || (lsr0 && ~lsr0_d); - -reg lsr1_d; - -always @(posedge clk ) - if (rst) lsr1_d <= 0; - else lsr1_d <= lsr1; - -always @(posedge clk ) - if (rst) lsr1r <= 0; - else lsr1r <= lsr_mask ? 0 : lsr1r || (lsr1 && ~lsr1_d); - -reg lsr2_d; - -always @(posedge clk ) - if (rst) lsr2_d <= 0; - else lsr2_d <= lsr2; - -always @(posedge clk ) - if (rst) lsr2r <= 0; - else lsr2r <= lsr_mask ? 0 : lsr2r || (lsr2 && ~lsr2_d); - -reg lsr3_d; - -always @(posedge clk ) - if (rst) lsr3_d <= 0; - else lsr3_d <= lsr3; - -always @(posedge clk ) - if (rst) lsr3r <= 0; - else lsr3r <= lsr_mask ? 0 : lsr3r || (lsr3 && ~lsr3_d); - -reg lsr4_d; - -always @(posedge clk ) - if (rst) lsr4_d <= 0; - else lsr4_d <= lsr4; - -always @(posedge clk ) - if (rst) lsr4r <= 0; - else lsr4r <= lsr_mask ? 0 : lsr4r || (lsr4 && ~lsr4_d); - -reg lsr5_d; -always @(posedge clk ) - if (rst) lsr5_d <= 1; - else lsr5_d <= lsr5; - -always @(posedge clk ) - if (rst) lsr5r <= 1; - else lsr5r <= (fifo_write) ? 0 : lsr5r || (lsr5 && ~lsr5_d); - -reg lsr6_d; - -always @(posedge clk ) - if (rst) lsr6_d <= 1; - else lsr6_d <= lsr6; - -always @(posedge clk ) - if (rst) lsr6r <= 1; - else lsr6r <= (fifo_write) ? 0 : lsr6r || (lsr6 && ~lsr6_d); - -reg lsr7_d; - -always @(posedge clk ) - if (rst) lsr7_d <= 0; - else lsr7_d <= lsr7; - -always @(posedge clk ) - if (rst) lsr7r <= 0; - else lsr7r <= lsr_mask ? 0 : lsr7r || (lsr7 && ~lsr7_d); - -reg [8:0] M_cnt; -wire [8:0] M_next = M_cnt + dl[`UART_DL3]; -wire M_toggle = M_cnt[8] ^ M_next[8]; - -always @(posedge clk ) -begin - if (rst) begin - dlc <= 0; - M_cnt <= 8'h0; - end - else if (start_dlc | ~ (|dlc)) begin - dlc <= dl - 1 + M_toggle; - M_cnt <= M_next; - end - else - dlc <= dlc - 1; -end - -always @(posedge clk ) -begin - if (rst) - enable <= 1'b0; - else if (|dl & ~(|dlc)) - enable <= 1'b1; - else - enable <= 1'b0; -end - -always @(lcr) - case (lcr[3:0]) - 4'b0000 : block_value = 95; - 4'b0100 : block_value = 103; - 4'b0001, 4'b1000 : block_value = 111; - 4'b1100 : block_value = 119; - 4'b0010, 4'b0101, 4'b1001 : block_value = 127; - 4'b0011, 4'b0110, 4'b1010, 4'b1101 : block_value = 143; - 4'b0111, 4'b1011, 4'b1110 : block_value = 159; - 4'b1111 : block_value = 175; - endcase - -always @(posedge clk ) -begin - if (rst) - block_cnt <= 8'd0; - else - if(lsr5r & fifo_write) - block_cnt <= usart_t0 ? (block_value + 8'h16) : block_value; - else - if (enable & block_cnt != 8'b0) - block_cnt <= block_cnt - 1; -end - -assign thre_set_en = ~(|block_cnt); - -assign rls_int = ier[`UART_IE_RLS] && (lsr[`UART_LS_OE] || lsr[`UART_LS_PE] || lsr[`UART_LS_FE] || lsr[`UART_LS_BI]); -assign rda_int = ier[`UART_IE_RDA] && (rf_count >= {1'b0,trigger_level}); -assign thre_int = ier[`UART_IE_THRE]&& lsr[`UART_LS_TFE]; -assign ms_int = ier[`UART_IE_MS] && (usart_t0 ? max_repeat_time : (| msr[3:0])); -assign ti_int = ier[`UART_IE_RDA] && (counter_t == 10'b0) && (|rf_count); - -reg rls_int_d; -reg thre_int_d; -reg ms_int_d; -reg ti_int_d; -reg rda_int_d; - -always @(posedge clk ) - if (rst) rls_int_d <= 0; - else rls_int_d <= rls_int; - -always @(posedge clk ) - if (rst) rda_int_d <= 0; - else rda_int_d <= rda_int; - -always @(posedge clk ) - if (rst) thre_int_d <= 0; - else thre_int_d <= thre_int; - -always @(posedge clk ) - if (rst) ms_int_d <= 0; - else ms_int_d <= ms_int; - -always @(posedge clk ) - if (rst) ti_int_d <= 0; - else ti_int_d <= ti_int; - - -wire rls_int_rise; -wire thre_int_rise; -wire ms_int_rise; -wire ti_int_rise; -wire rda_int_rise; - -assign rda_int_rise = rda_int & ~rda_int_d; -assign rls_int_rise = rls_int & ~rls_int_d; -assign thre_int_rise = thre_int & ~thre_int_d; -assign ms_int_rise = ms_int & ~ms_int_d; -assign ti_int_rise = ti_int & ~ti_int_d; - -reg rls_int_pnd; -reg rda_int_pnd; -reg thre_int_pnd; -reg ms_int_pnd; -reg ti_int_pnd; - -always @(posedge clk ) - if (rst) rls_int_pnd <= 0; - else - rls_int_pnd <= lsr_mask ? 0 : - rls_int_rise ? 1 : - rls_int_pnd && ier[`UART_IE_RLS]; - -reg d1_fifo_read; -always @( posedge clk ) d1_fifo_read <= fifo_read; - -always @(posedge clk) - if (rst) rda_int_pnd <= 0; - else rda_int_pnd <= ((rf_count == {1'b0,trigger_level}) && d1_fifo_read) ? 0 : - rda_int_rise ? 1 : - rda_int_pnd && ier[`UART_IE_RDA]; - -always @(posedge clk ) - if (rst) thre_int_pnd <= 0; - else - thre_int_pnd <= fifo_write || (iir_read & ~iir[`UART_II_IP] & iir[`UART_II_II] == `UART_II_THRE)? 0 : - thre_int_rise ? 1 : - thre_int_pnd && ier[`UART_IE_THRE]; - -always @(posedge clk ) - if (rst) ms_int_pnd <= 0; - else - ms_int_pnd <= msr_read ? 0 : ms_int_rise ? 1 : - ms_int_pnd && ier[`UART_IE_MS]; - -always @(posedge clk ) - if (rst) ti_int_pnd <= 0; - else - ti_int_pnd <= fifo_read ? 0 : ti_int_rise ? 1 : - ti_int_pnd && ier[`UART_IE_RDA]; - -always @(posedge clk ) -begin - if (rst) int_o <= 1'b0; - else int_o <= rls_int_pnd ? ~lsr_mask : - rda_int_pnd ? 1 : - ti_int_pnd ? ~fifo_read: - thre_int_pnd? !(fifo_write & iir_read) : - ms_int_pnd ? ~msr_read : - 0; -end - - -always @(posedge clk ) -begin - if (rst) - iir <= 1; - else - if (rls_int_pnd) - begin - iir[`UART_II_II] <= `UART_II_RLS; - iir[`UART_II_IP] <= 1'b0; - end else - if (rda_int_pnd) - begin - iir[`UART_II_II] <= `UART_II_RDA; - iir[`UART_II_IP] <= 1'b0; - end - else if (ti_int_pnd) - begin - iir[`UART_II_II] <= `UART_II_TI; - iir[`UART_II_IP] <= 1'b0; - end - else if (thre_int_pnd) - begin - iir[`UART_II_II] <= `UART_II_THRE; - iir[`UART_II_IP] <= 1'b0; - end - else if (ms_int_pnd) - begin - iir[`UART_II_II] <= `UART_II_MS; - iir[`UART_II_IP] <= 1'b0; - end else - begin - iir[`UART_II_II] <= 0; - iir[`UART_II_IP] <= 1'b1; - end -end - -endmodule diff --git a/resources/soc/rtl/APB_DEV/URT/uart_rfifo.v b/resources/soc/rtl/APB_DEV/URT/uart_rfifo.v deleted file mode 100644 index ba5dcb9..0000000 --- a/resources/soc/rtl/APB_DEV/URT/uart_rfifo.v +++ /dev/null @@ -1,193 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -`include "uart_defines.h" - -module uart_rfifo (clk, - wb_rst_i, data_in, data_out, - push, - pop, - overrun, - count, - error_bit, - fifo_reset, - reset_status -); - -parameter fifo_width = `UART_FIFO_WIDTH; -parameter fifo_depth = `UART_FIFO_DEPTH; -parameter fifo_pointer_w = `UART_FIFO_POINTER_W; -parameter fifo_counter_w = `UART_FIFO_COUNTER_W; - -input clk; -input wb_rst_i; -input push; -input pop; -input [fifo_width-1:0] data_in; -input fifo_reset; -input reset_status; - -output [fifo_width-1:0] data_out; -output overrun; -output [fifo_counter_w-1:0] count; -output error_bit; - -wire [fifo_width-1:0] data_out; -wire [7:0] data8_out; -reg [2:0] fifo[fifo_depth-1:0]; - -reg [fifo_pointer_w-1:0] top; -reg [fifo_pointer_w-1:0] bottom; - -reg [fifo_counter_w-1:0] count; -reg overrun; - -wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1; - -raminfr #(fifo_pointer_w,8,fifo_depth) rfifo (.clk(clk), - .we(push), - .a(top), - .dpra(bottom), - .di(data_in[fifo_width-1:fifo_width-8]), - .dpo(data8_out) -); - -always @(posedge clk) -begin - if (wb_rst_i) - begin - top <= 0; - bottom <= 1'b0; - count <= 0; - fifo[0] <= 0; - fifo[1] <= 0; - fifo[2] <= 0; - fifo[3] <= 0; - fifo[4] <= 0; - fifo[5] <= 0; - fifo[6] <= 0; - fifo[7] <= 0; - fifo[8] <= 0; - fifo[9] <= 0; - fifo[10]<= 0; - fifo[11]<= 0; - fifo[12]<= 0; - fifo[13]<= 0; - fifo[14]<= 0; - fifo[15]<= 0; - end - else - if (fifo_reset) begin - top <= 0; - bottom <= 1'b0; - count <= 0; - fifo[0] <= 0; - fifo[1] <= 0; - fifo[2] <= 0; - fifo[3] <= 0; - fifo[4] <= 0; - fifo[5] <= 0; - fifo[6] <= 0; - fifo[7] <= 0; - fifo[8] <= 0; - fifo[9] <= 0; - fifo[10]<= 0; - fifo[11]<= 0; - fifo[12]<= 0; - fifo[13]<= 0; - fifo[14]<= 0; - fifo[15]<= 0; - end - else - begin - case ({push, pop}) - 2'b10 : if (count0) - begin - fifo[bottom] <= 0; - bottom <= bottom + 1'b1; - count <= count - 1'b1; - end - 2'b11 : begin - bottom <= bottom + 1'b1; - top <= top_plus_1; - fifo[top] <= data_in[2:0]; - end - default: ; - endcase - end -end - -always @(posedge clk) -begin - if (wb_rst_i) - overrun <= 1'b0; - else - if(fifo_reset | reset_status) - overrun <= 1'b0; - else - if(push & ~pop & (count==fifo_depth)) - overrun <= 1'b1; -end - -assign data_out = {data8_out,fifo[bottom]}; - -wire [2:0] word0 = fifo[0]; -wire [2:0] word1 = fifo[1]; -wire [2:0] word2 = fifo[2]; -wire [2:0] word3 = fifo[3]; -wire [2:0] word4 = fifo[4]; -wire [2:0] word5 = fifo[5]; -wire [2:0] word6 = fifo[6]; -wire [2:0] word7 = fifo[7]; - -wire [2:0] word8 = fifo[8]; -wire [2:0] word9 = fifo[9]; -wire [2:0] word10 = fifo[10]; -wire [2:0] word11 = fifo[11]; -wire [2:0] word12 = fifo[12]; -wire [2:0] word13 = fifo[13]; -wire [2:0] word14 = fifo[14]; -wire [2:0] word15 = fifo[15]; - -assign error_bit = |(word0[2:0] | word1[2:0] | word2[2:0] | word3[2:0] | - word4[2:0] | word5[2:0] | word6[2:0] | word7[2:0] | - word8[2:0] | word9[2:0] | word10[2:0] | word11[2:0] | - word12[2:0] | word13[2:0] | word14[2:0] | word15[2:0] ); - -endmodule diff --git a/resources/soc/rtl/APB_DEV/URT/uart_sync_flops.v b/resources/soc/rtl/APB_DEV/URT/uart_sync_flops.v deleted file mode 100644 index 12d87b6..0000000 --- a/resources/soc/rtl/APB_DEV/URT/uart_sync_flops.v +++ /dev/null @@ -1,76 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -module uart_sync_flops -( - rst_i, - clk_i, - stage1_rst_i, - stage1_clk_en_i, - async_dat_i, - sync_dat_o -); - -parameter Tp = 1; -parameter width = 1; -parameter init_value = 1'b0; - -input rst_i; -input clk_i; -input stage1_rst_i; -input stage1_clk_en_i; -input [width-1:0] async_dat_i; -output [width-1:0] sync_dat_o; - -reg [width-1:0] sync_dat_o; -reg [width-1:0] flop_0; - -always @ (posedge clk_i) -begin - if (rst_i) - flop_0 <= {width{init_value}}; - else - flop_0 <= async_dat_i; -end - -always @ (posedge clk_i) -begin - if (rst_i) - sync_dat_o <= {width{init_value}}; - else if (stage1_rst_i) - sync_dat_o <= {width{init_value}}; - else if (stage1_clk_en_i) - sync_dat_o <= flop_0; -end - -endmodule diff --git a/resources/soc/rtl/APB_DEV/URT/uart_tfifo.v b/resources/soc/rtl/APB_DEV/URT/uart_tfifo.v deleted file mode 100644 index ce658a7..0000000 --- a/resources/soc/rtl/APB_DEV/URT/uart_tfifo.v +++ /dev/null @@ -1,129 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -`include "uart_defines.h" - -module uart_tfifo (clk, - wb_rst_i, data_in, data_out, - push, - pop, - overrun, - count, - fifo_reset, - reset_status -); - -parameter fifo_width = `UART_FIFO_WIDTH; -parameter fifo_depth = `UART_FIFO_DEPTH; -parameter fifo_pointer_w = `UART_FIFO_POINTER_W; -parameter fifo_counter_w = `UART_FIFO_COUNTER_W; - -input clk; -input wb_rst_i; -input push; -input pop; -input [fifo_width-1:0] data_in; -input fifo_reset; -input reset_status; - -output [fifo_width-1:0] data_out; -output overrun; -output [fifo_counter_w-1:0] count; - -wire [fifo_width-1:0] data_out; - -reg [fifo_pointer_w-1:0] top; -reg [fifo_pointer_w-1:0] bottom; - -reg [fifo_counter_w-1:0] count; -reg overrun; -wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1; - -raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo (.clk(clk), - .we(push), - .a(top), - .dpra(bottom), - .di(data_in), - .dpo(data_out) -); - - -always @(posedge clk) -begin - if (wb_rst_i) - begin - top <= 0; - bottom <= 1'b0; - count <= 0; - end - else - if (fifo_reset) begin - top <= 0; - bottom <= 1'b0; - count <= 0; - end - else - begin - case ({push, pop}) - 2'b10 : if (count0) - begin - bottom <= bottom + 1'b1; - count <= count - 1'b1; - end - 2'b11 : begin - bottom <= bottom + 1'b1; - top <= top_plus_1; - end - default: ; - endcase - end -end - -always @(posedge clk) -begin - if (wb_rst_i) - overrun <= 1'b0; - else - if(fifo_reset | reset_status) - overrun <= 1'b0; - else - if(push & (count==fifo_depth)) - overrun <= 1'b1; -end - -endmodule diff --git a/resources/soc/rtl/APB_DEV/URT/uart_top.v b/resources/soc/rtl/APB_DEV/URT/uart_top.v deleted file mode 100644 index 2d1237f..0000000 --- a/resources/soc/rtl/APB_DEV/URT/uart_top.v +++ /dev/null @@ -1,107 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -`include "uart_defines.h" - -module UART_TOP( - PCLK, PRST_, - PSEL, PENABLE, PADDR, PWRITE, - PWDATA, URT_PRDATA, - - INT, clk_carrier, - - TXD_i, TXD_o, TXD_oe, - RXD_i, RXD_o, RXD_oe, - - RTS, CTS, DSR, - DCD, DTR, RI - ); - -input PCLK, PRST_; -input PSEL, PENABLE, PWRITE; -input [7:0] PADDR; -input [7:0] PWDATA; -output [7:0] URT_PRDATA; - -output INT; -input clk_carrier; - -input TXD_i; -output TXD_o; -output TXD_oe; -input RXD_i; -output RXD_o; -output RXD_oe; - -output RTS; -input CTS, DSR, DCD; -output DTR; -input RI; - -wire prst = !PRST_; -wire we = PSEL & PENABLE & PWRITE; -wire re = PSEL & PENABLE & !PWRITE; - -wire rx_en; -wire tx2rx_en; -wire isomode; - -assign TXD_oe = isomode&&(rx_en||tx2rx_en) ? 1'b1:1'b0; -assign RXD_oe =~isomode; - -uart_regs regs( - .clk (PCLK ), - .rst (prst ), - .clk_carrier (clk_carrier), - .addr (PADDR[2:0] ), - .dat_i (PWDATA ), - .dat_o (URT_PRDATA ), - .we (we ), - .re (re ), - - .modem_inputs({ CTS, DSR, RI, DCD } ), - .rts_pad_o (RTS ), - .dtr_pad_o (DTR ), - .stx_pad_o (TXD_o ), - .TXD_i (TXD_i ), - .srx_pad_i (RXD_i ), - .RXD_o (RXD_o ), - .int_o ( INT ), - .tx2rx_en (tx2rx_en ), - .rx_en (rx_en ), - .usart_mode (isomode ) - -); - - -endmodule diff --git a/resources/soc/rtl/APB_DEV/URT/uart_transmitter.v b/resources/soc/rtl/APB_DEV/URT/uart_transmitter.v deleted file mode 100644 index 000cc4b..0000000 --- a/resources/soc/rtl/APB_DEV/URT/uart_transmitter.v +++ /dev/null @@ -1,281 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -`include "uart_defines.h" - -module uart_transmitter (clk, wb_rst_i, lcr, tf_push, wb_dat_i, - enable,stx_pad_o, tstate, tf_count, tx_reset, lsr_mask, - usart_t0,srx_pad_i,repeat_time,max_repeat_time,current_finish, - usart_mode,tx2rx_en); - -input clk; -input wb_rst_i; -input [7:0] lcr; -input tf_push; -input [7:0] wb_dat_i; -input enable; -input tx_reset; -input lsr_mask; -input usart_mode; -input usart_t0,srx_pad_i; -input [2:0] repeat_time; -output current_finish; -output max_repeat_time; - -output tx2rx_en; -reg tx2rx_en; -output stx_pad_o; -output [2:0] tstate; -output [`UART_FIFO_COUNTER_W-1:0] tf_count; - -reg [2:0] tstate; -reg [4:0] counter; -reg [2:0] bit_counter; -reg [6:0] shift_out; -reg stx_o_tmp; -reg parity_xor; -reg tf_pop; -reg bit_out; -reg tx_error; -reg [2:0] error_time; - -wire [`UART_FIFO_WIDTH-1:0] tf_data_in; -wire [`UART_FIFO_WIDTH-1:0] tf_data_out; -wire tf_push; -wire tf_overrun; -wire [`UART_FIFO_COUNTER_W-1:0]tf_count; - -assign tf_data_in = wb_dat_i; - -uart_tfifo fifo_tx( - .clk ( clk ), - .wb_rst_i( wb_rst_i ), - .data_in ( tf_data_in ), - .data_out( tf_data_out ), - .push ( tf_push ), - .pop ( tf_pop ), - .overrun ( tf_overrun ), - .count ( tf_count ), - .fifo_reset ( tx_reset), - .reset_status(lsr_mask ) -); - -parameter s_idle = 3'd0; -parameter s_send_start = 3'd1; -parameter s_send_byte = 3'd2; -parameter s_send_parity = 3'd3; -parameter s_send_stop = 3'd4; -parameter s_pop_byte = 3'd5; -parameter s_send_guard1 = 3'd6; -reg [7:0]tf_data_bak; - -wire max_repeat_time = (error_time==(repeat_time+1'b1)) & usart_mode & usart_t0; - -always @(posedge clk ) -begin - if (wb_rst_i) - begin - tx_error <= 1'b0; - error_time <= 3'b0; - tstate <= s_idle; - stx_o_tmp <= 1'b1; - counter <= 5'b0; - shift_out <= 7'b0; - bit_out <= 1'b0; - parity_xor <= 1'b0; - tf_pop <= 1'b0; - bit_counter <= 3'b0; - tx2rx_en <= 1'b0; - tf_data_bak <= 8'h0; - end - else - if (enable) - begin - case (tstate) - s_idle :if ((~|tf_count)&(error_time==(repeat_time+1'b1)||~tx_error||~usart_mode)) - begin - tstate <= s_idle; - stx_o_tmp <= 1'b1; - tx_error <= 1'b0; - end - else begin - tf_pop <= 1'b0; - stx_o_tmp <= 1'b1; - tstate <= s_pop_byte; - end - s_pop_byte : begin - - if(tx_error&(error_time !=(repeat_time+1'b1))) - begin - tf_pop <= 1'b0; - case (lcr[1:0]) - 2'b00 : begin - bit_counter <= 3'b100; - parity_xor <= ^tf_data_bak[4:0]; - end - 2'b01 : begin - bit_counter <= 3'b101; - parity_xor <= ^tf_data_bak[5:0]; - end - 2'b10 : begin - bit_counter <= 3'b110; - parity_xor <= ^tf_data_bak[6:0]; - end - 2'b11 : begin - bit_counter <= 3'b111; - parity_xor <= ^tf_data_bak[7:0]; - end - endcase - {shift_out[6:0], bit_out} <= tf_data_bak; - end - else begin - tf_pop <= 1'b1; - error_time <= 3'h0; - case (lcr[1:0]) - 2'b00 : begin - bit_counter <= 3'b100; - parity_xor <= ^tf_data_out[4:0]; - end - 2'b01 : begin - bit_counter <= 3'b101; - parity_xor <= ^tf_data_out[5:0]; - end - 2'b10 : begin - bit_counter <= 3'b110; - parity_xor <= ^tf_data_out[6:0]; - end - 2'b11 : begin - bit_counter <= 3'b111; - parity_xor <= ^tf_data_out[7:0]; - end - endcase - {shift_out[6:0], bit_out} <= tf_data_out; - tf_data_bak <= tf_data_out; - end - tstate <= s_send_start; - end - s_send_start : begin - tf_pop <= 1'b0; - if (~|counter) - counter <= 5'b01111; - else if (counter == 5'b00001) - begin - counter <= 0; - tstate <= s_send_byte; - end - else - counter <= counter - 1'b1; - stx_o_tmp <= 1'b0; - end - s_send_byte : begin - if (~|counter) - counter <= 5'b01111; - else if (counter == 5'b00001) - begin - if (bit_counter > 3'b0) begin - bit_counter <= bit_counter - 1'b1; - {shift_out[5:0],bit_out } <= {shift_out[6:1], shift_out[0]}; - tstate <= s_send_byte; - end - else - if (~lcr[`UART_LC_PE]) begin - tstate <= s_send_stop; - end - else begin - case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]}) - 2'b00: bit_out <= ~parity_xor; - 2'b01: bit_out <= 1'b1; - 2'b10: bit_out <= parity_xor; - 2'b11: bit_out <= 1'b0; - endcase - tstate <= s_send_parity; - end - counter <= 0; - end - else counter <= counter - 1'b1; - stx_o_tmp <= bit_out; - end - s_send_parity : begin - if (~|counter) counter <= 5'b01111; - else if (counter == 5'b00001) begin - counter <= 4'b0; - tstate <= usart_mode ? s_send_guard1 : s_send_stop; - end - else counter <= counter - 1'b1; - stx_o_tmp <= bit_out; - end - s_send_stop : begin - if (~|counter) begin - if(usart_t0) - counter <= tx_error ? 5'b11101 : 5'b01101; - else - casex ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]}) - 3'b0xx: counter <= 5'b01101; - 3'b100: counter <= 5'b10101; - default: counter <= 5'b11101; - endcase - end - else if (counter == 5'b00001) begin - counter <= 5'b0; - tx2rx_en<= 1'b0; - tstate <= s_idle; - end - else counter <= counter - 1'b1; - stx_o_tmp <= 1'b1; - end - s_send_guard1:begin - if (~|counter) begin - tx2rx_en <= 1'b1; - counter <= usart_t0 ? 5'b01111:5'b01101; - end - else if (counter == 5'b00001) begin - counter <= 5'b0; - tx_error <= !srx_pad_i; - error_time<= error_time + !srx_pad_i; - tx2rx_en <= usart_t0 ? 1'b1 : 1'b0; - tstate <= usart_t0 ? s_send_stop : s_idle; - end - else counter <= counter - 1'b1; - stx_o_tmp <= 1'b1; - end - default : - tstate <= s_idle; - endcase - end - else tf_pop <= 1'b0; -end - -assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp; -assign current_finish = usart_mode ? ( (tstate==3'b0)&(tx_error & (error_time ==repeat_time+1'b1) |~tx_error) ) : 1'b1; - -endmodule diff --git a/resources/soc/rtl/APB_DEV/apb_dev_top.v b/resources/soc/rtl/APB_DEV/apb_dev_top.v deleted file mode 100644 index 213f014..0000000 --- a/resources/soc/rtl/APB_DEV/apb_dev_top.v +++ /dev/null @@ -1,416 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -`include "config.h" - -module axi2apb_misc -( -clk, -rst_n, - -axi_s_awid, -axi_s_awaddr, -axi_s_awlen, -axi_s_awsize, -axi_s_awburst, -axi_s_awlock, -axi_s_awcache, -axi_s_awprot, -axi_s_awvalid, -axi_s_awready, -axi_s_wid, -axi_s_wdata, -axi_s_wstrb, -axi_s_wlast, -axi_s_wvalid, -axi_s_wready, -axi_s_bid, -axi_s_bresp, -axi_s_bvalid, -axi_s_bready, -axi_s_arid, -axi_s_araddr, -axi_s_arlen, -axi_s_arsize, -axi_s_arburst, -axi_s_arlock, -axi_s_arcache, -axi_s_arprot, -axi_s_arvalid, -axi_s_arready, -axi_s_rid, -axi_s_rdata, -axi_s_rresp, -axi_s_rlast, -axi_s_rvalid, -axi_s_rready, - -apb_rw_dma, -apb_psel_dma, -apb_enab_dma, -apb_addr_dma, -apb_valid_dma, -apb_wdata_dma, -apb_rdata_dma, -apb_ready_dma, -dma_grant, - -dma_req_o, -dma_ack_i, - -uart0_txd_i, -uart0_txd_o, -uart0_txd_oe, -uart0_rxd_i, -uart0_rxd_o, -uart0_rxd_oe, -uart0_rts_o, -uart0_dtr_o, -uart0_cts_i, -uart0_dsr_i, -uart0_dcd_i, -uart0_ri_i, - -uart0_int, -nand_int, - -nand_type, -nand_cle , -nand_ale , -nand_rdy , -nand_rd , -nand_ce, -nand_wr , -nand_dat_i , -nand_dat_o , -nand_dat_oe -); - -parameter ADDR_APB = 20, - DATA_APB = 8, - L_ADDR = 64, - L_ID = 8, - L_DATA = 128, - L_MASK = 16; - -input clk; -input rst_n; - -input [`LID -1 :0] axi_s_awid; -input [`Lawaddr -1 :0] axi_s_awaddr; -input [`Lawlen -1 :0] axi_s_awlen; -input [`Lawsize -1 :0] axi_s_awsize; -input [`Lawburst -1 :0] axi_s_awburst; -input [`Lawlock -1 :0] axi_s_awlock; -input [`Lawcache -1 :0] axi_s_awcache; -input [`Lawprot -1 :0] axi_s_awprot; -input axi_s_awvalid; -output axi_s_awready; -input [`LID -1 :0] axi_s_wid; -input [`Lwdata -1 :0] axi_s_wdata; -input [`Lwstrb -1 :0] axi_s_wstrb; -input axi_s_wlast; -input axi_s_wvalid; -output axi_s_wready; -output [`LID -1 :0] axi_s_bid; -output [`Lbresp -1 :0] axi_s_bresp; -output axi_s_bvalid; -input axi_s_bready; -input [`LID -1 :0] axi_s_arid; -input [`Laraddr -1 :0] axi_s_araddr; -input [`Larlen -1 :0] axi_s_arlen; -input [`Larsize -1 :0] axi_s_arsize; -input [`Larburst -1 :0] axi_s_arburst; -input [`Larlock -1 :0] axi_s_arlock; -input [`Larcache -1 :0] axi_s_arcache; -input [`Larprot -1 :0] axi_s_arprot; -input axi_s_arvalid; -output axi_s_arready; -output [`LID -1 :0] axi_s_rid; -output [`Lrdata -1 :0] axi_s_rdata; -output [`Lrresp -1 :0] axi_s_rresp; -output axi_s_rlast; -output axi_s_rvalid; -input axi_s_rready; - -output apb_ready_dma; -input apb_rw_dma; -input apb_psel_dma; -input apb_enab_dma; -input [ADDR_APB-1:0] apb_addr_dma; -input [31:0] apb_wdata_dma; -output[31:0] apb_rdata_dma; -input apb_valid_dma; -output dma_grant; - -output dma_req_o; -input dma_ack_i; - -input uart0_txd_i; -output uart0_txd_o; -output uart0_txd_oe; -input uart0_rxd_i; -output uart0_rxd_o; -output uart0_rxd_oe; -output uart0_rts_o; -output uart0_dtr_o; -input uart0_cts_i; -input uart0_dsr_i; -input uart0_dcd_i; -input uart0_ri_i; - -input [3:0]nand_rdy; -output [3:0]nand_ce; -output nand_cle; -output nand_ale; -output nand_rd; -output nand_wr; -output nand_dat_oe; -input [7:0]nand_dat_i ; -output [7:0]nand_dat_o ; - -output uart0_int; -output nand_int; -input [1:0]nand_type; - -wire nand_dma_req_o; -assign dma_req_o = nand_dma_req_o; -assign nand_dma_ack_i = dma_ack_i; - -wire apb_ready_cpu; -wire apb_rw_cpu; -wire apb_psel_cpu; -wire apb_enab_cpu; -wire [ADDR_APB-1 :0] apb_addr_cpu; -wire [DATA_APB-1:0] apb_datai_cpu; -wire [DATA_APB-1:0] apb_datao_cpu; -wire apb_clk_cpu; -wire apb_reset_n_cpu; -wire apb_word_trans_cpu; -wire apb_valid_cpu; -wire dma_grant; -wire [23:0] apb_high_24b_rd; -wire [23:0] apb_high_24b_wr; - -wire apb_rw_dma; -wire apb_psel_dma; -wire apb_enab_dma; -wire [31:0] apb_wdata_dma; -wire [31:0] apb_rdata_dma; -wire apb_clk_dma; -wire apb_reset_n_dma; - -wire apb_uart0_req; -wire apb_uart0_ack; -wire apb_uart0_rw; -wire apb_uart0_enab; -wire apb_uart0_psel; -wire [ADDR_APB -1:0] apb_uart0_addr; -wire [DATA_APB -1:0] apb_uart0_datai; -wire [DATA_APB -1:0] apb_uart0_datao; - -wire apb_nand_req; -wire apb_nand_ack; -wire apb_nand_rw; -wire apb_nand_enab; -wire apb_nand_psel; -wire [ADDR_APB -1:0] apb_nand_addr; -wire [31:0] apb_nand_datai; -wire [31:0] apb_nand_datao; - -axi2apb_bridge AA_axi2apb_bridge_cpu -( -.clk (clk ), -.rst_n (rst_n ), -.axi_s_awid (axi_s_awid ), -.axi_s_awaddr (axi_s_awaddr ), -.axi_s_awlen (axi_s_awlen ), -.axi_s_awsize (axi_s_awsize ), -.axi_s_awburst (axi_s_awburst ), -.axi_s_awlock (axi_s_awlock ), -.axi_s_awcache (axi_s_awcache ), -.axi_s_awprot (axi_s_awprot ), -.axi_s_awvalid (axi_s_awvalid ), -.axi_s_awready (axi_s_awready ), -.axi_s_wid (axi_s_wid ), -.axi_s_wdata (axi_s_wdata ), -.axi_s_wstrb (axi_s_wstrb ), -.axi_s_wlast (axi_s_wlast ), -.axi_s_wvalid (axi_s_wvalid ), -.axi_s_wready (axi_s_wready ), -.axi_s_bid (axi_s_bid ), -.axi_s_bresp (axi_s_bresp ), -.axi_s_bvalid (axi_s_bvalid ), -.axi_s_bready (axi_s_bready ), -.axi_s_arid (axi_s_arid ), -.axi_s_araddr (axi_s_araddr ), -.axi_s_arlen (axi_s_arlen ), -.axi_s_arsize (axi_s_arsize ), -.axi_s_arburst (axi_s_arburst ), -.axi_s_arlock (axi_s_arlock ), -.axi_s_arcache (axi_s_arcache ), -.axi_s_arprot (axi_s_arprot ), -.axi_s_arvalid (axi_s_arvalid ), -.axi_s_arready (axi_s_arready ), -.axi_s_rid (axi_s_rid ), -.axi_s_rdata (axi_s_rdata ), -.axi_s_rresp (axi_s_rresp ), -.axi_s_rlast (axi_s_rlast ), -.axi_s_rvalid (axi_s_rvalid ), -.axi_s_rready (axi_s_rready ), - -.apb_word_trans (apb_word_trans_cpu ), -.apb_high_24b_rd (apb_high_24b_rd ), -.apb_high_24b_wr (apb_high_24b_wr ), -.apb_valid_cpu (apb_valid_cpu ), -.cpu_grant (~dma_grant ), - -.apb_clk (apb_clk_cpu ), -.apb_reset_n (apb_reset_n_cpu ), -.reg_psel (apb_psel_cpu ), -.reg_enable (apb_enab_cpu ), -.reg_rw (apb_rw_cpu ), -.reg_addr (apb_addr_cpu ), -.reg_datai (apb_datai_cpu ), -.reg_datao (apb_datao_cpu ), -.reg_ready_1 (apb_ready_cpu ) -); - -apb_mux2 AA_apb_mux16 -( -.clk (clk ), -.rst_n (rst_n ), -.apb_ready_dma (apb_ready_dma ), -.apb_rw_dma (apb_rw_dma ), -.apb_addr_dma (apb_addr_dma ), -.apb_psel_dma (apb_psel_dma ), -.apb_enab_dma (apb_enab_dma ), -.apb_wdata_dma (apb_wdata_dma ), -.apb_rdata_dma (apb_rdata_dma ), -.apb_valid_dma (apb_valid_dma ), -.apb_valid_cpu (apb_valid_cpu ), -.dma_grant (dma_grant ), - -.apb_ack_cpu (apb_ready_cpu ), -.apb_rw_cpu (apb_rw_cpu ), -.apb_addr_cpu (apb_addr_cpu ), -.apb_psel_cpu (apb_psel_cpu ), -.apb_enab_cpu (apb_enab_cpu ), -.apb_datai_cpu (apb_datai_cpu ), -.apb_datao_cpu (apb_datao_cpu ), -.apb_high_24b_rd (apb_high_24b_rd), -.apb_high_24b_wr (apb_high_24b_wr), -.apb_word_trans_cpu (apb_word_trans_cpu ), - -.apb0_req (apb_uart0_req ), -.apb0_ack (apb_uart0_ack ), -.apb0_rw (apb_uart0_rw ), -.apb0_psel (apb_uart0_psel ), -.apb0_enab (apb_uart0_enab ), -.apb0_addr (apb_uart0_addr ), -.apb0_datai (apb_uart0_datai ), -.apb0_datao (apb_uart0_datao ), - -.apb1_req (apb_nand_req ), -.apb1_ack (apb_nand_ack ), -.apb1_rw (apb_nand_rw ), -.apb1_enab (apb_nand_enab ), -.apb1_psel (apb_nand_psel ), -.apb1_addr (apb_nand_addr ), -.apb1_datai (apb_nand_datai ), -.apb1_datao (apb_nand_datao ) - -); - -//uart0 -assign apb_uart0_ack = apb_uart0_enab; -UART_TOP uart0 -( -.PCLK (clk ), -.clk_carrier (1'b0 ), -.PRST_ (rst_n ), -.PSEL (apb_uart0_psel ), -.PENABLE (apb_uart0_enab ), -.PADDR (apb_uart0_addr[7:0] ), -.PWRITE (apb_uart0_rw ), -.PWDATA (apb_uart0_datai ), -.URT_PRDATA (apb_uart0_datao ), -.INT (uart0_int ), -.TXD_o (uart0_txd_o ), -.TXD_i (uart0_txd_i ), -.TXD_oe (uart0_txd_oe ), -.RXD_o (uart0_rxd_o ), -.RXD_i (uart0_rxd_i ), -.RXD_oe (uart0_rxd_oe ), -.RTS (uart0_rts_o ), -.CTS (uart0_cts_i ), -.DSR (uart0_dsr_i ), -.DCD (uart0_dcd_i ), -.DTR (uart0_dtr_o ), -.RI (uart0_ri_i ) -); - -//NAND -nand_module nand_module -( -.nand_type (nand_type ), - -.clk (clk ), -.rst_n (rst_n ), - -.apb_psel (apb_nand_psel ), -.apb_enab (apb_nand_enab ), -.apb_rw (apb_nand_rw ), -.apb_addr (apb_nand_addr ), -.apb_datai (apb_nand_datai ), -.apb_datao (apb_nand_datao ), -.apb_ack (apb_nand_ack ), - -.nand_dma_req_o (nand_dma_req_o ), -.nand_dma_ack_i (nand_dma_ack_i ), - -.nand_ce (nand_ce ), -.nand_dat_i (nand_dat_i ), -.nand_dat_o (nand_dat_o ), -.nand_dat_oe (nand_dat_oe ), -.nand_ale (nand_ale ), -.nand_cle (nand_cle ), -.nand_wr (nand_wr ), -.nand_rd (nand_rd ), -.nand_rdy (nand_rdy ), -.nand_int (nand_int ) -); - -endmodule - - diff --git a/resources/soc/rtl/APB_DEV/apb_mux2.v b/resources/soc/rtl/APB_DEV/apb_mux2.v deleted file mode 100644 index 38ce4dd..0000000 --- a/resources/soc/rtl/APB_DEV/apb_mux2.v +++ /dev/null @@ -1,203 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -`define APB_DEV0 6'h10 -`define APB_DEV1 6'h1e -module apb_mux2 ( -clk, -rst_n, -apb_ack_cpu, -apb_rw_cpu, -apb_psel_cpu, -apb_enab_cpu, -apb_addr_cpu, -apb_datai_cpu, -apb_datao_cpu, -apb_high_24b_rd, -apb_high_24b_wr, -apb_word_trans_cpu, - -apb_ready_dma, -apb_rw_dma, -apb_psel_dma, -apb_enab_dma, -apb_addr_dma, -apb_wdata_dma, -apb_rdata_dma, -apb_valid_dma, -apb_valid_cpu, -dma_grant, - -apb0_req, -apb0_ack, -apb0_rw, -apb0_psel, -apb0_enab, -apb0_addr, -apb0_datai, -apb0_datao, - -apb1_req, -apb1_ack, -apb1_rw, -apb1_psel, -apb1_enab, -apb1_addr, -apb1_datai, -apb1_datao -); - -parameter ADDR_APB = 20, - DATA_APB = 8, - DATA_APB_32 = 32; -input clk,rst_n; -output apb_ready_dma; -input apb_rw_dma; -input apb_psel_dma; -input apb_enab_dma; -input [ADDR_APB-1:0] apb_addr_dma; -input [31:0] apb_wdata_dma; -output[31:0] apb_rdata_dma; -output dma_grant; -input apb_valid_dma; -input apb_valid_cpu; - -output apb_ack_cpu; -input apb_rw_cpu; -input apb_psel_cpu; -input apb_enab_cpu; -input [ADDR_APB-1:0] apb_addr_cpu; -input [DATA_APB-1:0] apb_datai_cpu; -output[DATA_APB-1:0] apb_datao_cpu; -output [23:0] apb_high_24b_rd; -input [23:0] apb_high_24b_wr; - -output apb_word_trans_cpu; -output apb0_req; -input apb0_ack; -output apb0_rw; -output apb0_psel; -output apb0_enab; -output[ADDR_APB-1:0] apb0_addr; -output[DATA_APB-1:0] apb0_datai; -input [DATA_APB-1:0] apb0_datao; - -output apb1_req; -input apb1_ack; -output apb1_rw; -output apb1_psel; -output apb1_enab; -output[ADDR_APB-1:0] apb1_addr; -output[31:0] apb1_datai; -input [31:0] apb1_datao; - -wire apb_ack; -wire apb_rw; -wire apb_psel; -wire apb_enab; -wire [ADDR_APB-1:0] apb_addr; -wire [DATA_APB-1:0] apb_datai; -wire [23:0]high_24b_wr; -wire [23:0]high_24b_rd; -wire [7:0]apb_datao ; -wire dma_grant; - -arb_2_1 arb_2_1(.clk(clk), .rst_n(rst_n), .valid0(apb_valid_cpu), .valid1(apb_valid_dma), .dma_grant(dma_grant)); - -assign apb_addr = dma_grant ? apb_addr_dma:apb_addr_cpu; -assign apb_rw = dma_grant ? apb_rw_dma:apb_rw_cpu; -assign apb_psel = dma_grant ? apb_psel_dma:apb_psel_cpu; -assign apb_enab = dma_grant ? apb_enab_dma:apb_enab_cpu; -assign apb_datai = dma_grant ? apb_wdata_dma[7:0]:apb_datai_cpu; -assign high_24b_wr = dma_grant ? apb_wdata_dma[31:8]:apb_high_24b_wr; -assign high_24b_rd = apb1_req ? apb1_datao[31:8] : 24'h0; - -assign apb_word_trans_cpu = dma_grant ? 1'h0: apb1_req; - -assign apb_high_24b_rd = dma_grant ? 24'h0: high_24b_rd; -assign apb_datao_cpu = dma_grant ? 8'h0: apb_datao; -assign apb_rdata_dma = dma_grant ? {high_24b_rd,apb_datao }:32'h0; -assign apb_ack_cpu = ~dma_grant & apb_ack; -assign apb_ready_dma = dma_grant & apb_ack; - -assign apb0_req = (apb_addr[ADDR_APB-1:14] ==`APB_DEV0); -assign apb1_req = (apb_addr[ADDR_APB-1:14] ==`APB_DEV1); - -assign apb0_psel = apb_psel && apb0_req ; -assign apb1_psel = apb_psel && apb1_req; - -assign apb0_enab = apb_enab && apb0_req ; -assign apb1_enab = apb_enab && apb1_req; - -assign apb_ack = apb0_req ? apb0_ack : - apb1_req ? apb1_ack : - 1'b0; - -assign apb_datao = apb0_req ? apb0_datao : - apb1_req ? apb1_datao[7:0] : - 8'b0; - - - -assign apb0_addr = apb_addr; -assign apb0_datai = apb_datai; -assign apb0_rw = apb_rw; - -assign apb1_addr = apb_addr; -assign apb1_datai = {high_24b_wr,apb_datai}; -assign apb1_rw = apb_rw; - -endmodule - -module arb_2_1( clk, rst_n, valid0, valid1, dma_grant); -input clk; -input rst_n; -input valid0; -input valid1; -output dma_grant; -reg dma_grant; - -always @(posedge clk) - if(~rst_n) - dma_grant<= 1'b0; - else if(valid0&&~valid1) - dma_grant<= 1'b0; - else if(valid1&&~valid0) - dma_grant<= 1'b1; - else if(valid0&&valid1&&~dma_grant) - dma_grant<= 1'b0; - else if(valid0&&valid1&&dma_grant) - dma_grant<= 1'b1; - else dma_grant<= 1'b0; - -endmodule diff --git a/resources/soc/rtl/APB_DEV/nand_module.v b/resources/soc/rtl/APB_DEV/nand_module.v deleted file mode 100644 index be6cc5d..0000000 --- a/resources/soc/rtl/APB_DEV/nand_module.v +++ /dev/null @@ -1,140 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -module nand_module -( -nand_type , - -clk, -rst_n, - -apb_psel, -apb_enab, -apb_rw, -apb_addr, -apb_datai, -apb_datao, -apb_ack, - -nand_dma_req_o, -nand_dma_ack_i, - -nand_ce , -nand_dat_i , -nand_dat_o , -nand_dat_oe, -nand_ale , -nand_cle , -nand_wr , -nand_rd , -nand_rdy , - -nand_int - -); -input [1:0]nand_type; -input clk; -input rst_n; -input apb_psel; -input apb_enab; -input apb_rw; -input [19:0] apb_addr; -input [31:0] apb_datai; -output[31:0] apb_datao; -output apb_ack; - -output nand_dma_req_o; -input nand_dma_ack_i; - -output [3:0] nand_ce; -input [7:0] nand_dat_i ; -output [7:0] nand_dat_o ; -output nand_dat_oe; -output nand_ale; -output nand_cle; -output nand_wr; -output nand_rd; -input [3:0] nand_rdy; -output nand_int; - -wire psel; -wire penable; -wire [10:0] paddr; -wire pwr; -assign apb_ack = apb_enab; -assign psel = apb_psel; -assign penable = apb_enab; -assign paddr = apb_addr[10:0]; -assign pwr = apb_rw; - -reg [3:0] nand_iordy_r0; -reg [3:0] nand_iordy_r1; -always @(posedge clk) begin - nand_iordy_r0 <= nand_rdy; - nand_iordy_r1 <= nand_iordy_r0; -end -reg [1:0] nand_type_r1; -reg [1:0] nand_type_r2; - -always @(posedge clk) -if(~rst_n)begin - nand_type_r1 <= nand_type; - nand_type_r2 <= nand_type_r1; -end - -NAND_top NAND -( -.nand_type (nand_type_r2 ), -.pclk (clk ), -.prst_ (rst_n ), -.psel (psel ), -.penable (penable ), -.pwrite (pwr ), -.ADDR (paddr ), -.DAT_I (apb_datai ), -.DAT_O (apb_datao ), - -.NAND_CE_o (nand_ce ), -.NAND_REQ (nand_dma_req_o ), -.NAND_I (nand_dat_i ), -.NAND_O (nand_dat_o ), -.NAND_EN_ (nand_dat_oe ), -.NAND_ALE (nand_ale ), -.NAND_CLE (nand_cle ), -.NAND_RD_ (nand_rd ), -.NAND_WR_ (nand_wr ), -.NAND_IORDY_i (nand_iordy_r1 ), - -.nand_int (nand_int ) -); -endmodule diff --git a/resources/soc/rtl/CONFREG/confreg.v b/resources/soc/rtl/CONFREG/confreg.v deleted file mode 100644 index 5b2745a..0000000 --- a/resources/soc/rtl/CONFREG/confreg.v +++ /dev/null @@ -1,695 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -`define ORDER_REG_ADDR 16'h1160 //32'hbfd0_1160 -`define LED_ADDR 16'hf000 //32'hbfd0_f000 -`define LED_RG0_ADDR 16'hf004 //32'hbfd0_f004 -`define LED_RG1_ADDR 16'hf008 //32'hbfd0_f008 -`define NUM_ADDR 16'hf010 //32'hbfd0_f010 -`define SWITCH_ADDR 16'hf020 //32'hbfd0_f020 -`define BTN_KEY_ADDR 16'hf024 //32'hbfd0_f024 -`define BTN_STEP_ADDR 16'hf028 //32'hbfd0_f028 -`define TIMER_ADDR 16'he000 //32'hbfd0_e000 -module confreg( - aclk, - aresetn, - - s_awid, - s_awaddr, - s_awlen, - s_awsize, - s_awburst, - s_awlock, - s_awcache, - s_awprot, - s_awvalid, - s_awready, - s_wid, - s_wdata, - s_wstrb, - s_wlast, - s_wvalid, - s_wready, - s_bid, - s_bresp, - s_bvalid, - s_bready, - s_arid, - s_araddr, - s_arlen, - s_arsize, - s_arburst, - s_arlock, - s_arcache, - s_arprot, - s_arvalid, - s_arready, - s_rid, - s_rdata, - s_rresp, - s_rlast, - s_rvalid, - s_rready, - - order_addr_reg, - finish_read_order, - write_dma_end, - - cr00, - cr01, - cr02, - cr03, - cr04, - cr05, - cr06, - cr07, - - led, - led_rg0, - led_rg1, - num_csn, - num_a_g, - switch, - btn_key_col, - btn_key_row, - btn_step -); - input aclk; - input aresetn; - - input [3 :0] s_awid; - input [31:0] s_awaddr; - input [7 :0] s_awlen; - input [2 :0] s_awsize; - input [1 :0] s_awburst; - input s_awlock; - input [3 :0] s_awcache; - input [2 :0] s_awprot; - input s_awvalid; - output s_awready; - input [3 :0] s_wid; - input [31:0] s_wdata; - input [3 :0] s_wstrb; - input s_wlast; - input s_wvalid; - output s_wready; - output [3 :0] s_bid; - output [1 :0] s_bresp; - output s_bvalid; - input s_bready; - input [3 :0] s_arid; - input [31:0] s_araddr; - input [7 :0] s_arlen; - input [2 :0] s_arsize; - input [1 :0] s_arburst; - input s_arlock; - input [3 :0] s_arcache; - input [2 :0] s_arprot; - input s_arvalid; - output s_arready; - output [3 :0] s_rid; - output [31:0] s_rdata; - output [1 :0] s_rresp; - output s_rlast; - output s_rvalid; - input s_rready; - - output reg [31:0] order_addr_reg; - input finish_read_order; - input write_dma_end; - - output [31:0] cr00; - output [31:0] cr01; - output [31:0] cr02; - output [31:0] cr03; - output [31:0] cr04; - output [31:0] cr05; - output [31:0] cr06; - output [31:0] cr07; - - output [15:0] led; - output [1 :0] led_rg0; - output [1 :0] led_rg1; - output reg [7 :0] num_csn; - output reg [6 :0] num_a_g; - input [7 :0] switch; - output [3 :0] btn_key_col; - input [3 :0] btn_key_row; - input [1 :0] btn_step; - -// -reg [31:0] led_data; -reg [31:0] led_rg0_data; -reg [31:0] led_rg1_data; -reg [31:0] num_data; -wire [31:0] switch_data; -wire [31:0] btn_key_data; -wire [31:0] btn_step_data; -reg [31:0] timer; - -reg [31:0] cr00,cr01,cr02,cr03,cr04,cr05,cr06,cr07; -reg busy,write,R_or_W; -reg s_wready; - -wire ar_enter = s_arvalid & s_arready; -wire r_retire = s_rvalid & s_rready & s_rlast; -wire aw_enter = s_awvalid & s_awready; -wire w_enter = s_wvalid & s_wready & s_wlast; -wire b_retire = s_bvalid & s_bready; - -wire s_arready = ~busy & (!R_or_W| !s_awvalid); -wire s_awready = ~busy & ( R_or_W| !s_arvalid); - -always@(posedge aclk) - if(~aresetn) busy <= 1'b0; - else if(ar_enter|aw_enter) busy <= 1'b1; - else if(r_retire|b_retire) busy <= 1'b0; - -reg [3 :0] buf_id; -reg [31:0] buf_addr; -reg [7 :0] buf_len; -reg [2 :0] buf_size; -reg [1 :0] buf_burst; -reg buf_lock; -reg [3 :0] buf_cache; -reg [2 :0] buf_prot; - -always@(posedge aclk) - if(~aresetn) begin - R_or_W <= 1'b0; - buf_id <= 'b0; - buf_addr <= 'b0; - buf_len <= 'b0; - buf_size <= 'b0; - buf_burst <= 'b0; - buf_lock <= 'b0; - buf_cache <= 'b0; - buf_prot <= 'b0; - end - else - if(ar_enter | aw_enter) begin - R_or_W <= ar_enter; - buf_id <= ar_enter ? s_arid : s_awid ; - buf_addr <= ar_enter ? s_araddr : s_awaddr ; - buf_len <= ar_enter ? s_arlen : s_awlen ; - buf_size <= ar_enter ? s_arsize : s_awsize ; - buf_burst <= ar_enter ? s_arburst: s_awburst; - buf_lock <= ar_enter ? s_arlock : s_awlock ; - buf_cache <= ar_enter ? s_arcache: s_awcache; - buf_prot <= ar_enter ? s_arprot : s_awprot ; - end - -always@(posedge aclk) - if(~aresetn) write <= 1'b0; - else if(aw_enter) write <= 1'b1; - else if(ar_enter) write <= 1'b0; - -always@(posedge aclk) - if(~aresetn) s_wready <= 1'b0; - else if(aw_enter) s_wready <= 1'b1; - else if(w_enter & s_wlast) s_wready <= 1'b0; - -always@(posedge aclk) - if(~aresetn) begin - cr00 <= 32'd0; - cr01 <= 32'd0; - cr02 <= 32'd0; - cr03 <= 32'd0; - cr04 <= 32'd0; - cr05 <= 32'd0; - cr06 <= 32'd0; - cr07 <= 32'd0; - end - else if(w_enter) begin - case (buf_addr[15:2]) - 14'd0: cr00 <= s_wdata; - 14'd1: cr01 <= s_wdata; - 14'd2: cr02 <= s_wdata; - 14'd3: cr03 <= s_wdata; - 14'd4: cr04 <= s_wdata; - 14'd5: cr05 <= s_wdata; - 14'd6: cr06 <= s_wdata; - 14'd7: cr07 <= s_wdata; - endcase - end - -reg [31:0] s_rdata; -reg s_rvalid,s_rlast; -wire [31:0] rdata_d = buf_addr[15:2] == 14'd0 ? cr00 : - buf_addr[15:2] == 14'd1 ? cr01 : - buf_addr[15:2] == 14'd2 ? cr02 : - buf_addr[15:2] == 14'd3 ? cr03 : - buf_addr[15:2] == 14'd4 ? cr04 : - buf_addr[15:2] == 14'd5 ? cr05 : - buf_addr[15:2] == 14'd6 ? cr06 : - buf_addr[15:2] == 14'd7 ? cr07 : - buf_addr[15:0] == `ORDER_REG_ADDR ? order_addr_reg : - buf_addr[15:0] == `LED_ADDR ? led_data : - buf_addr[15:0] == `LED_RG0_ADDR ? led_rg0_data : - buf_addr[15:0] == `LED_RG1_ADDR ? led_rg1_data : - buf_addr[15:0] == `NUM_ADDR ? num_data : - buf_addr[15:0] == `SWITCH_ADDR ? switch_data : - buf_addr[15:0] == `BTN_KEY_ADDR ? btn_key_data : - buf_addr[15:0] == `BTN_STEP_ADDR ? btn_step_data : - buf_addr[15:0] == `TIMER_ADDR ? timer : 32'd0; - -always@(posedge aclk) - if(~aresetn) begin - s_rdata <= 'b0; - s_rvalid <= 1'b0; - s_rlast <= 1'b0; - end - else if(busy & !write & !r_retire) - begin - s_rdata <= rdata_d; - s_rvalid <= 1'b1; - s_rlast <= 1'b1; - end - else if(r_retire) - begin - s_rvalid <= 1'b0; - end - -reg s_bvalid; -always@(posedge aclk) - if(~aresetn) s_bvalid <= 1'b0; - else if(w_enter) s_bvalid <= 1'b1; - else if(b_retire) s_bvalid <= 1'b0; - -assign s_rid = buf_id; -assign s_bid = buf_id; -assign s_bresp = 2'b0; -assign s_rresp = 2'b0; - -wire write_order_reg = w_enter & (buf_addr[15:0]==`ORDER_REG_ADDR); -always @(posedge aclk) -begin - if(!aresetn) - begin - order_addr_reg <= 32'h0; - end - else if(write_order_reg) - begin - order_addr_reg <= s_wdata[31:0]; - end - else if(write_dma_end | finish_read_order) - begin - order_addr_reg[2] <= write_dma_end ? 1'b0 : order_addr_reg[2]; - order_addr_reg[3] <= finish_read_order ? 1'b0 : order_addr_reg[3]; - end -end -//-------------------------------{timer}begin----------------------------// -wire write_timer = w_enter & (buf_addr[15:0]==`TIMER_ADDR); -always @(posedge aclk) -begin - if(!aresetn) - begin - timer <= 32'd0; - end - else if (write_timer) - begin - timer <= s_wdata[31:0]; - end - else - begin - timer <= timer + 1'b1; - end -end -//--------------------------------{timer}end-----------------------------// - -//--------------------------------{led}begin-----------------------------// -//led display -//led_data[31:0] -wire write_led = w_enter & (buf_addr[15:0]==`LED_ADDR); -assign led = led_data[15:0]; -always @(posedge aclk) -begin - if(!aresetn) - begin - led_data <= 32'h0; - end - else if(write_led) - begin - led_data <= s_wdata[31:0]; - end -end -//---------------------------------{led}end------------------------------// - -//-------------------------------{switch}begin---------------------------// -//switch data -//switch_data[7:0] -assign switch_data = {24'd0,switch}; -//--------------------------------{switch}end----------------------------// - -//------------------------------{btn key}begin---------------------------// -//btn key data -reg [15:0] btn_key_r; -assign btn_key_data = {16'd0,btn_key_r}; - -//state machine -reg [2:0] state; -wire [2:0] next_state; - -//eliminate jitter -reg key_flag; -reg [19:0] key_count; -reg [3:0] state_count; -wire key_start = (state==3'b000) && !(&btn_key_row); -wire key_end = (state==3'b111) && (&btn_key_row); -wire key_sample= key_count[19]; -always @(posedge aclk) -begin - if(!aresetn) - begin - key_flag <= 1'd0; - end - else if (key_sample && state_count[3]) - begin - key_flag <= 1'b0; - end - else if( key_start || key_end ) - begin - key_flag <= 1'b1; - end - - if(!aresetn || !key_flag) - begin - key_count <= 20'd0; - end - else - begin - key_count <= key_count + 1'b1; - end -end - -always @(posedge aclk) -begin - if(!aresetn || state_count[3]) - begin - state_count <= 4'd0; - end - else - begin - state_count <= state_count + 1'b1; - end -end - -always @(posedge aclk) -begin - if(!aresetn) - begin - state <= 3'b000; - end - else if (state_count[3]) - begin - state <= next_state; - end -end - -assign next_state = (state == 3'b000) ? ( (key_sample && !(&btn_key_row)) ? 3'b001 : 3'b000 ) : - (state == 3'b001) ? ( !(&btn_key_row) ? 3'b111 : 3'b010 ) : - (state == 3'b010) ? ( !(&btn_key_row) ? 3'b111 : 3'b011 ) : - (state == 3'b011) ? ( !(&btn_key_row) ? 3'b111 : 3'b100 ) : - (state == 3'b100) ? ( !(&btn_key_row) ? 3'b111 : 3'b000 ) : - (state == 3'b111) ? ( (key_sample && (&btn_key_row)) ? 3'b000 : 3'b111 ) : - 3'b000; -assign btn_key_col = (state == 3'b000) ? 4'b0000: - (state == 3'b001) ? 4'b1110: - (state == 3'b010) ? 4'b1101: - (state == 3'b011) ? 4'b1011: - (state == 3'b100) ? 4'b0111: - 4'b0000; -wire [15:0] btn_key_tmp; -always @(posedge aclk) begin - if(!aresetn) begin - btn_key_r <= 16'd0; - end - else if(next_state==3'b000) - begin - btn_key_r <=16'd0; - end - else if(next_state == 3'b111 && state != 3'b111) begin - btn_key_r <= btn_key_tmp; - end -end - -assign btn_key_tmp = (state == 3'b001)&(btn_key_row == 4'b1110) ? 16'h0001: - (state == 3'b001)&(btn_key_row == 4'b1101) ? 16'h0010: - (state == 3'b001)&(btn_key_row == 4'b1011) ? 16'h0100: - (state == 3'b001)&(btn_key_row == 4'b0111) ? 16'h1000: - (state == 3'b010)&(btn_key_row == 4'b1110) ? 16'h0002: - (state == 3'b010)&(btn_key_row == 4'b1101) ? 16'h0020: - (state == 3'b010)&(btn_key_row == 4'b1011) ? 16'h0200: - (state == 3'b010)&(btn_key_row == 4'b0111) ? 16'h2000: - (state == 3'b011)&(btn_key_row == 4'b1110) ? 16'h0004: - (state == 3'b011)&(btn_key_row == 4'b1101) ? 16'h0040: - (state == 3'b011)&(btn_key_row == 4'b1011) ? 16'h0400: - (state == 3'b011)&(btn_key_row == 4'b0111) ? 16'h4000: - (state == 3'b100)&(btn_key_row == 4'b1110) ? 16'h0008: - (state == 3'b100)&(btn_key_row == 4'b1101) ? 16'h0080: - (state == 3'b100)&(btn_key_row == 4'b1011) ? 16'h0800: - (state == 3'b100)&(btn_key_row == 4'b0111) ? 16'h8000:16'h0000; -//-------------------------------{btn key}end----------------------------// - -//-----------------------------{btn step}begin---------------------------// -//btn step data -reg btn_step0_r; //0:press -reg btn_step1_r; //0:press -assign btn_step_data = {30'd0,~btn_step0_r,~btn_step1_r}; //1:press - -//-----step0 -//eliminate jitter -reg step0_flag; -reg [19:0] step0_count; -wire step0_start = btn_step0_r && !btn_step[0]; -wire step0_end = !btn_step0_r && btn_step[0]; -wire step0_sample= step0_count[19]; -always @(posedge aclk) -begin - if(!aresetn) - begin - step0_flag <= 1'd0; - end - else if (step0_sample) - begin - step0_flag <= 1'b0; - end - else if( step0_start || step0_end ) - begin - step0_flag <= 1'b1; - end - - if(!aresetn || !step0_flag) - begin - step0_count <= 20'd0; - end - else - begin - step0_count <= step0_count + 1'b1; - end - - if(!aresetn) - begin - btn_step0_r <= 1'b1; - end - else if(step0_sample) - begin - btn_step0_r <= btn_step[0]; - end -end - -//-----step1 -//eliminate jitter -reg step1_flag; -reg [19:0] step1_count; -wire step1_start = btn_step1_r && !btn_step[1]; -wire step1_end = !btn_step1_r && btn_step[1]; -wire step1_sample= step1_count[19]; -always @(posedge aclk) -begin - if(!aresetn) - begin - step1_flag <= 1'd0; - end - else if (step1_sample) - begin - step1_flag <= 1'b0; - end - else if( step1_start || step1_end ) - begin - step1_flag <= 1'b1; - end - - if(!aresetn || !step1_flag) - begin - step1_count <= 20'd0; - end - else - begin - step1_count <= step1_count + 1'b1; - end - - if(!aresetn) - begin - btn_step1_r <= 1'b1; - end - else if(step1_sample) - begin - btn_step1_r <= btn_step[1]; - end -end -//------------------------------{btn step}end----------------------------// - -//-------------------------------{led rg}begin---------------------------// -//led_rg0_data[31:0] led_rg0_data[31:0] -//bfd0_f010 bfd0_f014 -wire write_led_rg0 = w_enter & (buf_addr[15:0]==`LED_RG0_ADDR); -wire write_led_rg1 = w_enter & (buf_addr[15:0]==`LED_RG1_ADDR); -assign led_rg0 = led_rg0_data[1:0]; -assign led_rg1 = led_rg1_data[1:0]; -always @(posedge aclk) -begin - if(!aresetn) - begin - led_rg0_data <= 32'h0; - end - else if(write_led_rg0) - begin - led_rg0_data <= s_wdata[31:0]; - end - - if(!aresetn) - begin - led_rg1_data <= 32'h0; - end - else if(write_led_rg1) - begin - led_rg1_data <= s_wdata[31:0]; - end -end -//--------------------------------{led rg}end----------------------------// - -//---------------------------{digital number}begin-----------------------// -//digital number display -//num_data[31:0] -wire write_num = w_enter & (buf_addr[15:0]==`NUM_ADDR); -always @(posedge aclk) -begin - if(!aresetn) - begin - num_data <= 32'h0; - end - else if(write_num) - begin - num_data <= s_wdata[31:0]; - end -end - - -reg [19:0] count; -always @(posedge aclk) -begin - if(!aresetn) - begin - count <= 20'd0; - end - else - begin - count <= count + 1'b1; - end -end -//scan data -reg [3:0] scan_data; -always @ ( posedge aclk ) -begin - if ( !aresetn ) - begin - scan_data <= 32'd0; - num_csn <= 8'b1111_1111; - end - else - begin - case(count[19:17]) - 3'b000 : scan_data <= num_data[31:28]; - 3'b001 : scan_data <= num_data[27:24]; - 3'b010 : scan_data <= num_data[23:20]; - 3'b011 : scan_data <= num_data[19:16]; - 3'b100 : scan_data <= num_data[15:12]; - 3'b101 : scan_data <= num_data[11: 8]; - 3'b110 : scan_data <= num_data[7 : 4]; - 3'b111 : scan_data <= num_data[3 : 0]; - endcase - - case(count[19:17]) - 3'b000 : num_csn <= 8'b0111_1111; - 3'b001 : num_csn <= 8'b1011_1111; - 3'b010 : num_csn <= 8'b1101_1111; - 3'b011 : num_csn <= 8'b1110_1111; - 3'b100 : num_csn <= 8'b1111_0111; - 3'b101 : num_csn <= 8'b1111_1011; - 3'b110 : num_csn <= 8'b1111_1101; - 3'b111 : num_csn <= 8'b1111_1110; - endcase - end -end - -always @(posedge aclk) -begin - if ( !aresetn ) - begin - num_a_g <= 7'b0000000; - end - else - begin - case ( scan_data ) - 4'd0 : num_a_g <= 7'b1111110; //0 - 4'd1 : num_a_g <= 7'b0110000; //1 - 4'd2 : num_a_g <= 7'b1101101; //2 - 4'd3 : num_a_g <= 7'b1111001; //3 - 4'd4 : num_a_g <= 7'b0110011; //4 - 4'd5 : num_a_g <= 7'b1011011; //5 - 4'd6 : num_a_g <= 7'b1011111; //6 - 4'd7 : num_a_g <= 7'b1110000; //7 - 4'd8 : num_a_g <= 7'b1111111; //8 - 4'd9 : num_a_g <= 7'b1111011; //9 - 4'd10: num_a_g <= 7'b1110111; //a - 4'd11: num_a_g <= 7'b0011111; //b - 4'd12: num_a_g <= 7'b1001110; //c - 4'd13: num_a_g <= 7'b0111101; //d - 4'd14: num_a_g <= 7'b1001111; //e - 4'd15: num_a_g <= 7'b1000111; //f - endcase - end -end -//----------------------------{digital number}end------------------------// -endmodule diff --git a/resources/soc/rtl/DMA/dma.v b/resources/soc/rtl/DMA/dma.v deleted file mode 100644 index 04ec940..0000000 --- a/resources/soc/rtl/DMA/dma.v +++ /dev/null @@ -1,778 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -`define DMA_ORDERSIZE 32 -`define DMA_WORDSIZE 32 -`include "config.h" -`define WRITE_LENGTH 16 -`define READ_LENGTH 16 -module dma_master( - clk, - rst_n, - arid, araddr, arlen ,arsize, arburst, arlock, arcache, arprot, arvalid, arready, - rid , rdata , rresp ,rlast , rvalid , rready, - awid, awaddr, awlen ,awsize, awburst, awlock, awcache, awprot, awvalid, awready, - wid , wdata , wstrb ,wlast , wvalid , wready, - bid , bresp , bvalid,bready, - dma_int, order_addr_in,dma_req_in,dma_ack_out, - finish_read_order, write_dma_end,dma_gnt, - apb_valid_req,apb_psel, apb_penable, apb_rw, apb_addr,apb_rdata,apb_wdata - ); -input clk; -input rst_n; -input dma_gnt; - -output [`LID -1 :0] awid; -output [`Lawaddr -1 :0] awaddr; -output [`Lawlen -1 :0] awlen; -output [`Lawsize -1 :0] awsize; -output [`Lawburst -1 :0] awburst; -output [`Lawlock -1 :0] awlock; -output [`Lawcache -1 :0] awcache; -output [`Lawprot -1 :0] awprot; -output awvalid; -input awready; -output [`LID -1 :0] wid; -output [64 -1 :0] wdata; -output [8 -1 :0] wstrb; -output wlast; -output wvalid; -input wready; -input [`LID -1 :0] bid; -input [`Lbresp -1 :0] bresp; -input bvalid; -output bready; -output [`LID -1 :0] arid; -output [`Laraddr -1 :0] araddr; -output [`Larlen -1 :0] arlen; -output [`Larsize -1 :0] arsize; -output [`Larburst -1 :0] arburst; -output [`Larlock -1 :0] arlock; -output [`Larcache -1 :0] arcache; -output [`Larprot -1 :0] arprot; -output arvalid; -input arready; -input [`LID -1 :0] rid; -input [64 -1 :0] rdata; -input [`Lrresp -1 :0] rresp; -input rlast; -input rvalid; -output rready; - -output dma_int; -output dma_ack_out; -input [31:0] order_addr_in; -input dma_req_in; -output finish_read_order; -output write_dma_end; - -output apb_psel; -output apb_valid_req; -output apb_penable; -output apb_rw; -output [31:0] apb_addr; -input [31:0] apb_rdata; -output [31:0] apb_wdata; - -wire read_idle; -wire read_ready; -wire get_order; -wire read_order; -wire finish_read_order; -wire r_ddr_wait; -wire read_ddr; -wire read_ddr_end; -wire read_dev; -wire read_dev_end; -wire read_step_end; -wire write_idle; -wire write_ready; -wire w_ddr_wait; -wire write_ddr; -wire write_ddr_end; -wire w_dma_wait; -wire write_dma; -wire write_dma_end ; -wire write_step_end; -wire rresp_ok = (rresp==2'h0); -wire bresp_ok = (bresp==2'h0); - -wire dma_start; -wire dma_stop; -wire ask_valid; -wire [31:0] ask_addr; -wire [ 1:0] device_num_tmp; -assign device_num_tmp = order_addr_in[1:0]; -assign ask_valid = order_addr_in[2] ; -assign dma_start = order_addr_in[3] ; -assign dma_stop = order_addr_in[4] & - (read_ddr_end | read_dev_end | read_step_end | read_idle ) & - (write_ddr_end | write_dma_end | write_step_end | write_idle); -assign ask_addr = {order_addr_in[31:5], 5'h0}; - -reg [ 3:0] dma_read_state; -reg [ 3:0] dma_write_state; -reg [31:0] count_length; -reg [ 4:0] count_fifo_r; -reg [ 4:0] count_fifo_w; -reg [ 5:0] count_fifo; -reg [31:0] mem [31:0]; -reg dma_r_w; -reg [31:0] dma_order_addr; -reg [31:0] dma_mem_addr; -reg [31:0] dma_dev_addr; -reg [31:0] dma_length; -reg [31:0] dma_step_length; -reg [31:0] dma_step_times; -reg [31:0] dma_state_reg; -reg dma_get_order; - -wire [31:0]mem0 = mem[0]; -wire [31:0]mem1 = mem[1]; -wire [31:0]mem2 = mem[2]; -wire [31:0]mem3 = mem[3]; -wire [31:0]mem4 = mem[4]; -wire [31:0]mem5 = mem[5]; -wire [31:0]mem6 = mem[6]; -wire [31:0]mem7 = mem[7]; -wire [31:0]mem8 = mem[8]; -wire [31:0]mem9 = mem[9]; -wire [31:0]mem10 = mem[10]; -wire [31:0]mem11 = mem[11]; -wire [31:0]mem12 = mem[12]; -wire [31:0]mem13 = mem[13]; -wire [31:0]mem14 = mem[14]; -wire [31:0]mem15 = mem[15]; -wire [31:0]mem16 = mem[16]; -wire [31:0]mem17 = mem[17]; -wire [31:0]mem18 = mem[18]; -wire [31:0]mem19 = mem[19]; -wire [31:0]mem20 = mem[20]; -wire [31:0]mem21 = mem[21]; -wire [31:0]mem22 = mem[22]; -wire [31:0]mem23 = mem[23]; -wire [31:0]mem24 = mem[24]; -wire [31:0]mem25 = mem[25]; -wire [31:0]mem26 = mem[26]; -wire [31:0]mem27 = mem[27]; -wire [31:0]mem28 = mem[28]; -wire [31:0]mem29 = mem[29]; -wire [31:0]mem30 = mem[30]; -wire [31:0]mem31 = mem[31]; - -wire dma_order_en; -wire[ 3:0] dma_next_read_state; -wire[ 3:0] dma_next_write_state; -wire[31:0] count_obj; -wire dma_single_trans_over; -wire dma_trans_over; -wire dma_state_change_en; -wire dma_int_mask; - -assign dma_int_mask = dma_state_reg[0]; -assign dma_int = dma_state_reg[1]; -assign dma_order_en = dma_order_addr[0]; - -reg dma_req_in_reg_1, dma_req_in_reg_2; -reg dma_req_r; -reg dma_req; -always @(posedge clk)begin - if (~rst_n) begin - dma_req_in_reg_1 <= 1'b0; - dma_req_in_reg_2 <= 1'b0; - end else begin - dma_req_in_reg_1 <= dma_req_in; - dma_req_in_reg_2 <= dma_req_in_reg_1; - end -end -always @(posedge clk)begin - if (~rst_n) - dma_req_r <= 1'b0; - else - dma_req_r <= dma_req_in_reg_2; -end -always @(posedge clk)begin - if (~rst_n) - dma_req <= 1'b0; - else if (dma_ack_out | !dma_req_in_reg_2) - dma_req <= 1'b0; - else if (~dma_req_r & dma_req_in_reg_2) - dma_req <= 1'b1; -end - -parameter READ_IDLE = 4'h0; -parameter READ_READY = 4'h1; -parameter GET_ORDER = 4'h2; -parameter READ_ORDER = 4'h3; -parameter FINISH_READ_ORDER = 4'h4; -parameter R_DDR_WAIT = 4'h5; -parameter READ_DDR = 4'h6; -parameter READ_DDR_END = 4'h7; -parameter READ_DEV = 4'h8; -parameter READ_DEV_END = 4'h9; -parameter READ_STEP_END = 4'ha; - -assign read_idle = dma_read_state==READ_IDLE; -assign read_ready = dma_read_state==READ_READY; -assign get_order = dma_read_state==GET_ORDER; -assign read_order = dma_read_state==READ_ORDER; -assign finish_read_order = dma_read_state==FINISH_READ_ORDER; -assign r_ddr_wait = dma_read_state==R_DDR_WAIT; -assign read_ddr = dma_read_state==READ_DDR; -assign read_ddr_end = dma_read_state==READ_DDR_END; -assign read_dev = dma_read_state==READ_DEV; -assign read_dev_end = dma_read_state==READ_DEV_END; -assign read_step_end = dma_read_state==READ_STEP_END; - -assign dma_single_trans_over = (write_step_end | read_step_end & (count_fifo==0)) & (count_length==32'b0) & (dma_step_times==32'b1) ? 1'b1 : 1'b0; -assign dma_trans_over = dma_single_trans_over & !dma_order_en; -reg dma_trans_over_reg; -always @(posedge clk)begin - if(!rst_n) - dma_trans_over_reg <= 1'b0; - else if(dma_trans_over) - dma_trans_over_reg <= 1'b1; - else if((read_idle & write_idle) & dma_start) - dma_trans_over_reg <= 1'b0; -end - -wire [5:0] num_fifo; -wire read_ddr_again = !dma_get_order & dma_r_w & (count_fifo <= `READ_LENGTH) & (count_length!=0) & (num_fifo >6'h0); -wire read_dev_again = !dma_get_order & !dma_r_w & dma_req & (count_fifo < 6'h20); - -assign dma_next_read_state = read_idle ? (dma_start ? READ_READY : READ_IDLE) : - read_ready ? (dma_get_order ? GET_ORDER : read_ddr_again ? R_DDR_WAIT : read_dev_again ? READ_DEV : READ_READY) : - get_order ? (arready ? READ_ORDER : GET_ORDER) : - read_order ? (rvalid & rlast & rready & rresp_ok ? FINISH_READ_ORDER : READ_ORDER) : - finish_read_order ? READ_READY : - r_ddr_wait ? (arready ? READ_DDR : R_DDR_WAIT) : - read_ddr ? (rvalid & rready & rlast & rresp_ok ? READ_DDR_END : READ_DDR) : - read_ddr_end ? ((count_length==0) ? READ_STEP_END : read_ddr_again ? R_DDR_WAIT : READ_DDR_END) : - read_step_end ? ((dma_trans_over | dma_stop) ? READ_IDLE : dma_get_order ? GET_ORDER : read_ddr_again ? R_DDR_WAIT : READ_STEP_END) : - read_dev ? ((dma_trans_over | dma_stop) ? READ_IDLE : dma_get_order ? GET_ORDER : apb_penable ? READ_DEV_END : READ_DEV) : - read_dev_end ? ((dma_trans_over | dma_stop) ? READ_IDLE : dma_get_order ? GET_ORDER : read_dev_again ? READ_DEV : READ_DEV_END) : READ_IDLE; - - -reg [1:0]arb_write_op; -wire aw_empty = (arb_write_op==2'b01) & write_ddr_end || (arb_write_op==2'b00) & write_dma_end || (arb_write_op==2'b11); -wire write_ddr_ok = ((count_fifo >= `WRITE_LENGTH) | (count_fifo >= count_length)) & (count_length!=0); -always @(posedge clk)begin - if(!rst_n | dma_stop) - arb_write_op <= 2'b11; - else if(ask_valid & aw_empty & (arb_write_op!=0)) - arb_write_op <= 2'b00; - else if(!dma_r_w & write_ddr_ok & aw_empty) - arb_write_op <= 2'b01; - else if(aw_empty) - arb_write_op <= 2'b11; -end - -wire write_ddr_again = !dma_get_order & (arb_write_op==2'b01) & write_ddr_ok; -wire write_dma_again = !dma_get_order & (arb_write_op==2'b00); - -parameter WRITE_IDLE = 4'h0; -parameter W_DDR_WAIT = 4'h1; -parameter WRITE_DDR = 4'h2; -parameter WRITE_DDR_END = 4'h3; -parameter W_DMA_WAIT = 4'h4; -parameter WRITE_DMA = 4'h5; -parameter WRITE_DMA_END = 4'h6; -parameter WRITE_STEP_END = 4'h7; -assign write_idle = dma_write_state==WRITE_IDLE; -assign w_ddr_wait = dma_write_state==W_DDR_WAIT; -assign write_ddr = dma_write_state==WRITE_DDR; -assign write_ddr_end = dma_write_state==WRITE_DDR_END; -assign w_dma_wait = dma_write_state==W_DMA_WAIT; -assign write_dma = dma_write_state==WRITE_DMA; -assign write_dma_end = dma_write_state==WRITE_DMA_END; -assign write_step_end = dma_write_state==WRITE_STEP_END; -reg awvalid_dma; -assign dma_next_write_state = write_idle ? (write_dma_again ? W_DMA_WAIT : write_ddr_again ? W_DDR_WAIT : WRITE_IDLE) : - w_ddr_wait ? (awready ? WRITE_DDR : W_DDR_WAIT) : - write_ddr ? (bvalid & bresp_ok & bready ? WRITE_DDR_END : WRITE_DDR) : - write_ddr_end ? (write_dma_again ? W_DMA_WAIT : (count_length==0) ? WRITE_STEP_END : write_ddr_again ? W_DDR_WAIT : WRITE_DDR_END): - w_dma_wait ? (awvalid_dma & awready ? WRITE_DMA : W_DMA_WAIT) : - write_dma ? (bvalid & bresp_ok & bready ? WRITE_DMA_END : WRITE_DMA) : - write_dma_end ? (dma_r_w ? WRITE_IDLE : (count_length==0) ? WRITE_STEP_END : write_ddr_again ? W_DDR_WAIT : WRITE_DMA_END) : - write_step_end ? ((dma_trans_over | dma_stop | (count_length==0)&(dma_step_times==32'h1)) ? WRITE_IDLE : - write_dma_again ? W_DMA_WAIT : write_ddr_again ? W_DDR_WAIT : WRITE_STEP_END) : WRITE_IDLE; - -wire [1:0] ac97_mod = dma_dev_addr[29:28]; -wire byte_mod = (ac97_mod == 2'b00); -wire half_mod = (ac97_mod == 2'b01); -wire word_mod = (ac97_mod == 2'b10); -wire [31:0] mem_0 = mem[count_fifo_w]; -wire [31:0] mem_1 = mem[count_fifo_w+1]; -wire [31:0] wdata_tmp0_tmp = byte_mod ? {mem_1[23:16], mem_1[7 :0], mem_0[23:16], mem_0[7 :0]} : half_mod ? {mem_1[15: 0], mem_0[15: 0]} : mem_0; -wire [31:0] wdata_tmp1_tmp = byte_mod ? {mem_1[31:24], mem_1[15:8], mem_0[31:24], mem_0[15:8]} : half_mod ? {mem_1[31:16], mem_0[31:16]} : mem_1; -wire [31:0] wdata_tmp0 = dma_dev_addr[30] ? wdata_tmp0_tmp : mem_0; -wire [31:0] wdata_tmp1 = dma_dev_addr[30] ? wdata_tmp1_tmp : mem_0; -reg [32:0] reg_ac97; -wire write_dev_ok = ((dma_dev_addr[31:30]==2'b11) ? (reg_ac97[32] | (count_fifo>=6'h2)) : (count_fifo>=6'h1)) & dma_req & dma_r_w; -always@(posedge clk)begin - if(!rst_n) - reg_ac97 <= 33'h0; - else if(apb_penable & dma_dev_addr[31] & !reg_ac97[32]) - reg_ac97 <= {1'b1, wdata_tmp1}; - else if(apb_penable & reg_ac97[32]) - reg_ac97[32] <= 1'b0; -end - -reg arvalid_dev; -always @(posedge clk)begin - if(!rst_n) - arvalid_dev <= 1'b0; - else if(arvalid_dev & apb_penable) - arvalid_dev <= 1'b0; - else if((read_dev & !dma_get_order | read_dev_end) & read_dev_again) - arvalid_dev <= 1'b1; -end - -reg awvalid_dev; -always @(posedge clk)begin - if(!rst_n) - awvalid_dev <= 1'b0; - else if(awvalid_dev & apb_penable) - awvalid_dev <= 1'b0; - else if(write_dev_ok) - awvalid_dev <= 1'b1; -end -assign dma_ack_out = apb_psel; - -assign dma_state_change_en = (dma_read_state !=dma_next_read_state) | (dma_write_state!=dma_next_write_state); -always@(posedge clk)begin - if(!rst_n | dma_trans_over | dma_stop)begin - dma_read_state <= READ_IDLE; - dma_write_state <= WRITE_IDLE; - end else if(dma_state_change_en)begin - dma_read_state <= dma_next_read_state; - dma_write_state <= dma_next_write_state; - end -end - -always@(posedge clk)begin - if(~rst_n | finish_read_order | dma_stop) - dma_get_order <= 1'b0; - else if((read_idle & write_idle) & dma_start | dma_single_trans_over & dma_order_en) - dma_get_order <= 1'b1; -end - -wire [2:0] size_tmp = read_ddr ? arsize : awsize; -wire [1:0] read_size = read_dev ? 2'h1 : (arsize==3'h3) ? 2'h2 : 2'h1; -wire [1:0] write_size = awvalid_dev ? (((dma_dev_addr[31:30]==2'b11) & (count_fifo>32'h1)) ? 2'h2 : 2'h1) : (awsize==3'h3) ? 2'h2 : 2'h1; - -always@(posedge clk)begin - if(~rst_n) - count_length <= 32'b0; - else if (dma_stop) - count_length <= 32'b0; - else if(finish_read_order) - count_length <= dma_length; - else if(dma_get_order) - count_length <= `DMA_ORDERSIZE; - else if(((read_ddr_end | write_ddr_end) & count_length==32'b0) & (dma_step_times > 32'h1)) - count_length <= dma_length; - else if(read_ddr & rvalid & rready & rresp_ok | write_ddr & wvalid & wready) - count_length <= count_length - ((size_tmp==3'h3) ? 2'h2 : 2'h1); -end - -reg [4:0] read_num; -reg [4:0] write_num; -always@(posedge clk)begin - if(~rst_n | dma_single_trans_over | dma_stop)begin - count_fifo_r <= 5'h0; - read_num <= 5'h0; - end else if(read_ddr & rvalid & rready & rresp_ok | read_dev & apb_penable)begin - count_fifo_r <= count_fifo_r + read_size; - read_num <= read_ddr ? (rlast ? 5'h0 : read_num + 1'b1) : read_num; - end -end -always@(posedge clk)begin - if(~rst_n | dma_single_trans_over | dma_stop)begin - count_fifo_w <= 5'h0; - write_num <= 5'h0; - end else if(write_ddr & wvalid & wready | awvalid_dev & apb_penable & !reg_ac97[32])begin - count_fifo_w <= count_fifo_w + write_size; - write_num <= write_ddr ? (wlast ? 5'h0 : write_num + 1'b1) : write_num; - end -end - -reg write_dma_to_ddr; -reg [1:0]dma_num; - -always@(posedge clk)begin - if(~rst_n)begin - dma_num <= 2'h0; - write_dma_to_ddr <= 1'h0; -end - else if(write_dma & wvalid & wready)begin - dma_num <= dma_num + 1'b1; - write_dma_to_ddr <= !write_dma_to_ddr; -end -end - -wire [1:0] fifo_read_add = {2{(read_ddr & rvalid & rready | read_dev & apb_penable)}} & read_size; -wire [1:0] fifo_write_sum = {2{(write_ddr & wvalid & wready | awvalid_dev & apb_penable & !reg_ac97[32])}} & write_size; -always@(posedge clk)begin - if(~rst_n | dma_single_trans_over | dma_stop) - count_fifo <= 6'h0; - else - count_fifo <= count_fifo + fifo_read_add - fifo_write_sum; -end - -reg arvalid_dma; -wire [31:0] araddr_dma; -wire [3 :0] arlen_dma; -wire [2 :0] arsize_dma; -reg getting_dma; -always @(posedge clk)begin - if(!rst_n)begin - arvalid_dma <= 1'b0; - getting_dma <= 1'b0; - end else if(arvalid_dma & arready) - arvalid_dma <= 1'b0; - else if(dma_get_order & !getting_dma)begin - arvalid_dma <= 1'b1; - getting_dma <= 1'b1; - end else if(finish_read_order | dma_stop) - getting_dma <= 1'b0; -end -assign araddr_dma = (dma_start & dma_get_order) ? ask_addr : {dma_order_addr[31:5], 5'h0}; -assign arlen_dma = 4'h3; -assign arsize_dma = 3'h3; - -wire [2:0] arsize_ddr_tmp; -wire [3:0] arlen_ddr_tmp; -wire [5:0] left_fifo = `DMA_WORDSIZE - count_fifo; -wire enough_8; -assign num_fifo = (count_length >= left_fifo) ? left_fifo : count_length; -wire [3:0] arlen_tmp = (num_fifo >= 6'h10) ? 4'hf : (num_fifo-1'b1); -assign enough_8 = (num_fifo >= 6'h2); -assign arsize_ddr_tmp = (dma_mem_addr[2:0]==3'h0) & enough_8 ? 3'h3 : 3'h2; -assign arlen_ddr_tmp = (dma_mem_addr[2:0]==3'h0) & enough_8 ? (num_fifo[5] ? 4'hf : (num_fifo[5:1]-1'b1)): arlen_tmp; - -reg arvalid_ddr; -reg [31:0] araddr_ddr; -reg [3 :0] arlen_ddr; -reg [2: 0] arsize_ddr; -always @(posedge clk)begin - if(!rst_n) - arvalid_ddr <= 1'b0; - else if(arready & arvalid_ddr) - arvalid_ddr <= 1'b0; - else if((read_ready & !dma_get_order | read_ddr_end | read_step_end) & read_ddr_again & !dma_stop) - arvalid_ddr <= 1'b1; -end - -always @(posedge clk)begin - if(!rst_n) - begin - araddr_ddr <= 32'b0; - arsize_ddr <= 3'b0; - arlen_ddr <= 4'b0; - end - else if((read_ready & !dma_get_order | read_ddr_end | read_step_end) & read_ddr_again)begin - araddr_ddr <= dma_mem_addr; - arsize_ddr <= arsize_ddr_tmp; - arlen_ddr <= arlen_ddr_tmp; - end -end - -assign arvalid = dma_get_order ? arvalid_dma : dma_r_w ? arvalid_ddr : 1'b0; -assign araddr = dma_get_order ? {32'h0, araddr_dma} : {32'h0, araddr_ddr}; -assign arsize = dma_get_order ? arsize_dma : arsize_ddr; -assign arlen = dma_get_order ? arlen_dma : arlen_ddr; -assign arid = dma_get_order ? {4'h0, 4'h1} : {4'h0, 4'h2}; -assign arburst = 2'h1; -assign arlock = 2'h0; -assign arprot = 3'h0; -assign arcache = 4'h0; -assign rready = 1'h1; - -wire[31:0] count_sou; -assign count_sou = araddr_ddr + {read_num, 2'h0}; -wire [31:0]read_data_word = !count_sou[2] ? rdata[31:0] : rdata[63:32]; - -integer i; -always@(posedge clk) -begin - if(~rst_n | dma_stop | dma_single_trans_over) - begin - for(i=0;i<=31;i=i+1) mem[i] <= 32'b0; - end - else if(read_ddr & rvalid & rready & rresp_ok & arsize==3'h2) - mem[count_fifo_r] <= read_data_word; - else if(read_ddr & rvalid & rready & rresp_ok & arsize==3'h3) - {mem[count_fifo_r+1], mem[count_fifo_r]} <= rdata; - else if(read_dev & apb_penable) - mem[count_fifo_r] <= apb_rdata; -end - -reg [1:0]reg_num; -always@(posedge clk)begin - if(~rst_n | dma_stop)begin - dma_r_w <= 1'b0; - dma_order_addr <= 32'b0; - dma_mem_addr <= 32'b0; - dma_dev_addr <= 32'b0; - dma_length <= 32'b0; - dma_step_length<= 32'b0; - dma_step_times <= 32'b0; - reg_num <= 2'b0; - end - else begin - if(read_ddr & rvalid & rready & rresp_ok | write_ddr & wvalid & wready) - dma_mem_addr <= dma_mem_addr + ((size_tmp==3'h3) ? 4'h8 : 3'h4); - else if((write_ddr_end | read_ddr_end) & (count_length==32'b0) & dma_step_times>32'b1)begin - dma_step_times <= dma_step_times - 1; - dma_mem_addr <= dma_mem_addr + {dma_step_length, 2'h0}; - end else if(read_order & rvalid & rready & rresp_ok & (reg_num==2'h0))begin - dma_order_addr <= rdata[31 : 0]; - dma_mem_addr <= rdata[63 :32]; - reg_num <= reg_num + 1'b1; - end else if(read_order & rvalid & rready & rresp_ok & (reg_num==2'h1))begin - dma_dev_addr <= rdata[31 : 0]; - dma_length <= rdata[63 :32]; - reg_num <= reg_num + 1'b1; - end else if(read_order & rvalid & rready & rresp_ok & (reg_num==2'h2))begin - dma_step_length<= rdata[31: 0]; - dma_step_times <= rdata[63:32]; - reg_num <= reg_num + 1'b1; - end else if(read_order & rvalid & rready & rresp_ok & rlast)begin - dma_r_w <= rdata[12]; - reg_num <= 2'b0; - end - end -end - -reg dma_int_en; -reg dma_int_i; -always@(posedge clk)begin - if(~rst_n) - dma_state_reg <= 32'b0; - else if(read_order & rvalid & rready & rresp_ok & rlast) - dma_state_reg <= rdata[31:0]; - else if(dma_start == 1'b1) - dma_state_reg[1] <= 1'b0; - else if(dma_int_i & dma_int_en) - dma_state_reg[1] <= 1'b1; - else if(dma_state_reg[1]) - dma_state_reg[1] <= 1'b0; -end - -reg dma_int_tmp; -always@(posedge clk) -begin - if(!rst_n) - dma_int_i <= 1'b0; - else if(dma_single_trans_over & dma_int_mask & !dma_int_i) - dma_int_i <= 1'b1; - else if(dma_int_i & dma_int_en) - dma_int_i <= 1'b0; -end - -always@(posedge clk) -begin - if(!rst_n) - dma_int_tmp <= 1'b0; - else - dma_int_tmp <= dma_int_i; -end -always@(posedge clk) -begin - if(!rst_n) - dma_int_en <= 1'b1; - else if(dma_int_tmp & dma_int_en) - dma_int_en <= 1'b0; - else if(!dma_int_i) - dma_int_en <= 1'b1; -end - -wire [5:0] write_length; -wire enough_8_1; -wire [2:0] awsize_ddr_tmp; -wire [3:0] awlen_ddr_tmp; -wire [3:0] awlen_tmp; -assign write_length = (count_fifo >= count_length) ? count_length[5:0] : count_fifo; -assign enough_8_1 = (write_length >= 3'h2); -assign awlen_tmp = (write_length >= 5'h10) ? 4'hf : (write_length - 1'b1); -assign awsize_ddr_tmp = (dma_mem_addr[2:0]==3'h0) & enough_8_1 ? 3'h3 : 3'h2; -assign awlen_ddr_tmp = (dma_mem_addr[2:0]==3'h0) & enough_8_1 ? (write_length[5]? 4'hf : (write_length[5:1] - 1'b1)) : awlen_tmp; -reg awvalid_ddr; -reg [31:0] awaddr_ddr; -reg [3 :0] awlen_ddr; -reg [2 :0] awsize_ddr; -reg wvalid_ddr; -always @(posedge clk)begin - if(!rst_n) - awvalid_ddr <= 1'b0; - else if(awvalid_ddr & awready) - awvalid_ddr <= 1'b0; - else if(write_ddr_again & !write_dma_again & (write_idle | write_ddr_end | write_dma_end | write_step_end) & !dma_stop) - awvalid_ddr <= 1'b1; -end -always @(posedge clk)begin - if(!rst_n) - begin - awaddr_ddr <= 32'b0; - awsize_ddr <= 3'b0; - awlen_ddr <= 4'b0; - end - else if(write_ddr)begin - awaddr_ddr <= awaddr_ddr; - awsize_ddr <= awsize_ddr; - awlen_ddr <= awlen_ddr; - end else if(write_ddr_again & !write_dma_again & (write_idle | write_ddr_end | write_dma_end | write_step_end))begin - awaddr_ddr <= dma_mem_addr; - awsize_ddr <= awsize_ddr_tmp; - awlen_ddr <= awlen_ddr_tmp; - end -end -always @(posedge clk)begin - if(!rst_n) - wvalid_ddr <= 1'b0; - else if (awvalid_ddr & awready)begin - wvalid_ddr <= 1'b1; - end - else if(write_ddr & wvalid & wready)begin - wvalid_ddr <= !wlast; - end -end -assign count_obj = awaddr_ddr + {write_num, 2'h0}; -wire [63:0] wdata_word = !count_obj[2] ? {32'h0, mem[count_fifo_w]} : {mem[count_fifo_w], 32'h0}; -wire [7 :0] wstrb_word = !count_obj[2] ? 8'h0f : 8'hf0; -wire [63:0] wdata_64 = {mem[count_fifo_w+1], mem[count_fifo_w]}; -wire [63:0] wdata_ddr; -wire [15:0] wstrb_ddr; -wire wlast_ddr; -assign wdata_ddr = (awsize_ddr==3'h2) ? wdata_word : wdata_64; -assign wstrb_ddr = (awsize_ddr==3'h2) ? wstrb_word : 8'hff; -assign wlast_ddr = (write_num==awlen_ddr); - -reg wvalid_dma; -wire [31:0] awaddr_dma; -wire [3 :0] awlen_dma; -wire [2 :0] awsize_dma; -wire [63:0] wdata_dma; -wire [15 :0] wstrb_dma; -wire wlast_dma; -always @(posedge clk)begin - if(!rst_n) - awvalid_dma <= 1'b0; - else if(awvalid_dma & awready) - awvalid_dma <= 1'b0; - else if(write_dma_again & !dma_stop & w_dma_wait) - awvalid_dma <= 1'b1; -end -always @(posedge clk)begin - if(!rst_n) - wvalid_dma <= 1'b0; - else if (awvalid_dma & awready) - wvalid_dma <= 1'b1; - else if(write_dma & wvalid & wready) - wvalid_dma <= !wlast; -end - -wire [63:0] dma_data0; -wire [63:0] dma_data1; -wire [63:0] dma_data2; -wire [63:0] dma_data3; -wire [31:0] dma_state_tmp = {19'h0, dma_r_w, dma_write_state, dma_read_state, dma_trans_over_reg, - dma_single_trans_over, dma_int, dma_int_mask}; - -assign dma_data0 = {dma_mem_addr, dma_order_addr }; -assign dma_data1 = {dma_length, dma_dev_addr }; -assign dma_data2 = {dma_step_times, dma_step_length}; -assign dma_data3 = {32'h0, dma_state_tmp }; - -assign awaddr_dma = ask_addr; -assign awlen_dma = 4'h3; -assign awsize_dma = 3'h3; - -assign wlast_dma = (dma_num== 2'h3); -assign wdata_dma = (dma_num==2'h0) ? dma_data0 : (dma_num==2'h1) ? dma_data1 : (dma_num==2'h2) ? dma_data2 : dma_data3; -assign wstrb_dma = (dma_num!=2'h3) ? 8'hff : 8'h0f; - -assign awvalid = awvalid_dma | awvalid_ddr ; -assign awaddr = awvalid_dma ? {32'h0, awaddr_dma} : {32'h0, awaddr_ddr}; -assign awlen = awvalid_dma ? awlen_dma : awlen_ddr; -assign awsize = awvalid_dma ? awsize_dma : awsize_ddr; -assign awid = awvalid_dma ? {4'h0, 4'h1} : {4'h0, 4'h2}; -assign awburst = 2'h1; -assign awlock = 2'h0; -assign awprot = 3'h0; -assign awcache = 4'h0; -assign wvalid = wvalid_dma | wvalid_ddr ; -assign wid = wvalid_dma ? {4'h0, 4'h1} : {4'h0, 4'h2}; -assign wdata = wvalid_dma ? wdata_dma : wdata_ddr; -assign wstrb = wvalid_dma ? wstrb_dma : wstrb_ddr; -assign wlast = wvalid_dma ? wlast_dma : wlast_ddr; -assign bready = 1'b1; - -wire apb_valid_req; -reg apb_psel; -reg apb_penable; -reg apb_rw; -wire [31:0]apb_addr; -wire [31:0]apb_wdata; -assign apb_valid_req = arvalid_dev || awvalid_dev ; -assign apb_addr = dma_dev_addr[31] ? (reg_ac97[32] ? {24'h1fe600, dma_dev_addr[15:8]} :{24'h1fe600, dma_dev_addr[7:0]}) : dma_dev_addr; -assign apb_wdata= reg_ac97[32] ? reg_ac97[31:0] : wdata_tmp0; -always@(posedge clk) -begin - if(~rst_n)begin - apb_psel<= 1'b0; - apb_penable <= 1'b0; - apb_rw <= 1'b0; - end - else begin - if(dma_gnt) begin - if(apb_penable)begin - apb_psel <= 1'b0; - apb_rw <= 1'b0; - apb_penable <= 1'b0; - end else if(arvalid_dev | awvalid_dev) begin - apb_psel <= 1'b1; - apb_rw <= awvalid_dev ; - apb_penable <= apb_psel; - end else - apb_penable <= apb_psel; - end else begin - apb_psel<= 1'b0; - apb_penable <= 1'b0; - apb_rw <= 1'b0; - end - end -end - -endmodule diff --git a/resources/soc/rtl/MAC/bd.v b/resources/soc/rtl/MAC/bd.v deleted file mode 100644 index 2a4146f..0000000 --- a/resources/soc/rtl/MAC/bd.v +++ /dev/null @@ -1,372 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -module BD ( - clk, - rst, - col, - crs, - fdp, - tprog, - preamble, - tpend, - winp, - tiack, - coll, - carrier, - bkoff, - lc, - lo, - nc, - ec, - cc - ); - - `include "utility.v" - - input clk; - input rst; - - input col; - input crs; - - input fdp; - - input tprog; - input preamble; - input tpend; - output winp; - wire winp; - input tiack; - output coll; - wire coll; - output carrier; - wire carrier; - output bkoff; - wire bkoff; - output lc; - wire lc; - output lo; - reg lo; - output nc; - wire nc; - output ec; - reg ec; - output [3:0] cc; - wire [3:0] cc; - - - reg crs_r; - reg inc; - - reg ibkoff; - reg ibkoff_r; - reg icoll; - reg ilc; - reg [3:0] ccnt; - reg [9:0] bkcnt; - reg [8:0] slcnt; - reg [9:0] bkrel_c; - wire [9:0] p_rand; - reg [31:0] lfsr; - reg [31:0] lfsr_c; - reg iwinp; - - always @(posedge clk) - begin : crs_reg_proc - if (rst) - begin - crs_r <= 1'b0 ; - lo <= 1'b0 ; - inc <= 1'b0 ; - end - else - begin - if (fdp) - begin - crs_r <= 1'b0 ; - end - else - begin - crs_r <= crs ; - end - - if (tprog & !inc & !crs_r) - begin - lo <= 1'b1 ; - end - else if(!tpend & !tprog) - begin - lo <= 1'b0 ; - end - - if (tprog & crs_r) - begin - inc <= 1'b0 ; - end - else if (!tpend & !tprog) - begin - inc <= 1'b1 ; - end - end - end - - assign nc = inc ; - - always @(ccnt or p_rand) - begin : bkrel_proc - case (ccnt) - 4'b0000 : - begin - bkrel_c <= {9'b000000000, p_rand[0]} ; - end - 4'b0001 : - begin - bkrel_c <= {8'b00000000, p_rand[1:0]} ; - end - 4'b0010 : - begin - bkrel_c <= {7'b0000000, p_rand[2:0]} ; - end - 4'b0011 : - begin - bkrel_c <= {6'b000000, p_rand[3:0]} ; - end - 4'b0100 : - begin - bkrel_c <= {5'b00000, p_rand[4:0]} ; - end - 4'b0101 : - begin - bkrel_c <= {4'b0000, p_rand[5:0]} ; - end - 4'b0110 : - begin - bkrel_c <= {3'b000, p_rand[6:0]} ; - end - 4'b0111 : - begin - bkrel_c <= {2'b00, p_rand[7:0]} ; - end - 4'b1000 : - begin - bkrel_c <= {1'b0, p_rand[8:0]} ; - end - default : - begin - bkrel_c <= p_rand[9:0] ; - end - endcase - end - - always @(posedge clk) - begin : slcnt_reg_proc - if (rst) - begin - slcnt <= {9{1'b1}} ; - end - else - begin - if (tprog & !preamble & !icoll) - begin - if (slcnt != 9'b000000000) - begin - slcnt <= slcnt - 1 ; - end - end - else if (ibkoff) - begin - if (slcnt == 9'b000000000 | icoll) - begin - slcnt <= SLOT_TIME ; - end - else - begin - slcnt <= slcnt - 1 ; - end - end - else - begin - slcnt <= SLOT_TIME ; - end - end - end - - always @(posedge clk) - begin : bkcnt_reg_proc - if (rst) - begin - bkcnt <= {10{1'b1}} ; - end - else - begin - if (icoll & !ibkoff) - begin - bkcnt <= bkrel_c ; - end - else if (slcnt == 9'b000000000) - begin - bkcnt <= bkcnt - 1 ; - end - end - end - - always @(posedge clk) - begin : rand_reg_proc - if (rst) - begin - lfsr <= {31{1'b1}}; - end - else - begin - lfsr <= lfsr_c; - end - end - - always @(lfsr) - begin : lfsr_drv - - reg [31:0] lfsr_n; - - integer i; - for(i=0; i<=30; i=i+1) - begin - lfsr_n[i] = lfsr[i+1]; - end - - lfsr_n[31] = 1'b0; - if(lfsr[0]==1'b1) - begin - lfsr_n = lfsr_n ^ 32'b10000000000000000000111010100110; - end - - lfsr_c <= lfsr_n; - - end - - assign p_rand = lfsr[9:0] ; - - - always @(posedge clk) - begin : ibkoff_reg_proc - if (rst) - begin - ibkoff <= 1'b0 ; - ibkoff_r <= 1'b0 ; - end - else - begin - ibkoff_r <= ibkoff ; - if(icoll & ccnt!=4'b1111 & !iwinp & !ilc) - begin - ibkoff <= 1'b1 ; - end - else if (bkcnt == 10'b0000000000) - begin - ibkoff <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : coll_reg_proc - if (rst) - begin - icoll <= 1'b0 ; - ilc <= 1'b0 ; - ec <= 1'b0 ; - iwinp <= 1'b1 ; - ccnt <= 4'b0000 ; - end - else - begin - if ((preamble | tprog) & col & !fdp) - begin - icoll <= 1'b1 ; - end - else if (!tprog & !preamble) - begin - icoll <= 1'b0 ; - end - - if (tiack) - begin - ilc <= 1'b0 ; - end - else if (tprog & icoll & iwinp) - begin - ilc <= 1'b1 ; - end - - if (tiack) - begin - ec <= 1'b0 ; - end - else if (icoll & ccnt == 4'b1111 & tprog) - begin - ec <= 1'b1 ; - end - - if (slcnt == 9'b000000000 | !tprog) - begin - iwinp <= 1'b1 ; - end - else - begin - iwinp <= 1'b0 ; - end - - if (!tpend & !tprog) - begin - ccnt <= 4'b0000 ; - end - else if (ibkoff & !ibkoff_r) - begin - ccnt <= ccnt + 4'b0001 ; - end - end - end - - assign winp = iwinp ; - - assign lc = ilc; - - assign carrier = crs_r ; - - assign coll = icoll ; - - assign bkoff = ibkoff ; - - assign cc = ccnt ; - -endmodule diff --git a/resources/soc/rtl/MAC/csr.v b/resources/soc/rtl/MAC/csr.v deleted file mode 100644 index 46b8e77..0000000 --- a/resources/soc/rtl/MAC/csr.v +++ /dev/null @@ -1,2530 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -module CSR ( - clk, - rst, - interrupt, - csrreq, - csrrw, - csrbe, - csraddr, - csrdatai, - csrack, - csrdatao, - rstsofto, - tprog, - tireq, - unf, - tcsreq, - tiack, - tcsack, - fd, - ic, - etireq, - etiack, - tm, - sf, - tset, - tdes, - tbuf, - tstat, - tu, - tpollack, - ft, - tpoll, - tdbadc, - tdbad, - rcsreq, - rprog, - rcsack, - ren, - ra, - pm, - pr, - pb, - rif, - ho, - hp, - foclack, - mfclack, - oco, - mfo, - focg, - mfcg, - focl, - mfcl, - rireq, - erireq, - ru, - rpollack, - rdes, - rbuf, - rstat, - riack, - eriack, - rpoll, - rdbadc, - rdbad, - ble, - dbo, - dma_priority, - pbl, - dsl, - stoptc, - stoptlsm, - stoptfifo, - stopt, - tps, - stoprc, - stoprlsm, - stopr, - rps, - sdi, - sclk, - scs, - sdo, - mdi, - mdc, - mdo, - mden, - - insert_en_o - ); - - parameter CSRWIDTH = 32; - parameter DATAWIDTH = 32; - parameter DATADEPTH = 32; - parameter RFIFODEPTH = 9; - parameter RCDEPTH = 2; - - `include "utility.v" - - input clk; - input rst; - output interrupt; - wire interrupt; - - input csrreq; - input csrrw; - input [CSRWIDTH / 8 - 1:0] csrbe; - input [CSRDEPTH - 1:0] csraddr; - input [CSRWIDTH - 1:0] csrdatai; - output csrack; - wire csrack; - output [CSRWIDTH - 1:0] csrdatao; - reg [CSRWIDTH - 1:0] csrdatao; - - output rstsofto; - reg rstsofto; - - input tprog; - input tireq; - input unf; - input tcsreq; - output tiack; - wire tiack; - output tcsack; - wire tcsack; - output fd; - wire fd; - - input ic; - input etireq; - output etiack; - wire etiack; - output [2:0] tm; - wire [2:0] tm; - output sf; - wire sf; - - input tset; - input tdes; - input tbuf; - input tstat; - input tu; - input tpollack; - input [1:0] ft; - output tpoll; - wire tpoll; - output tdbadc; - reg tdbadc; - output [DATADEPTH - 1:0] tdbad; - wire [DATADEPTH - 1:0] tdbad; - - input rcsreq; - input rprog; - output rcsack; - wire rcsack; - output ren; - wire ren; - output ra; - wire ra; - output pm; - wire pm; - output pr; - wire pr; - output pb; - wire pb; - output rif; - wire rif; - output ho; - wire ho; - output hp; - wire hp; - - input foclack; - input mfclack; - input oco; - input mfo; - input [10:0] focg; - input [15:0] mfcg; - output focl; - reg focl; - output mfcl; - reg mfcl; - - input rireq; - input erireq; - input ru; - input rpollack; - input rdes; - input rbuf; - input rstat; - output riack; - wire riack; - output eriack; - wire eriack; - output rpoll; - reg rpoll; - output rdbadc; - reg rdbadc; - output [DATADEPTH - 1:0] rdbad; - wire [DATADEPTH - 1:0] rdbad; - - output ble; - wire ble; - output dbo; - wire dbo; - output [1:0] dma_priority; - wire [1:0] dma_priority; - output [5:0] pbl; - wire [5:0] pbl; - output [4:0] dsl; - wire [4:0] dsl; - - input stoptc; - input stoptlsm; - input stoptfifo; - output stopt; - wire stopt; - output tps; - reg tps; - - input stoprc; - input stoprlsm; - output stopr; - wire stopr; - output rps; - reg rps; - - input sdi; - output sclk; - wire sclk; - output scs; - wire scs; - output sdo; - wire sdo; - - input mdi; - output mdc; - wire mdc; - output mdo; - wire mdo; - output mden; - wire mden; - - - output insert_en_o; - wire insert_en_o; - - reg [31:0] csrdata_c; - reg [3:0] csrdbe_c; - wire [1:0] csraddr10; - wire [5:0] csraddr72; - wire [1:0] csrbe10; - wire [31:0] csr0; - wire [31:0] csr5; - wire [31:0] csr6; - wire [31:0] csr7; - wire [31:0] csr8; - wire [31:0] csr9; - wire [31:0] csr10; - wire [31:0] csr11; - - reg csr0_dbo; - reg [2:0] csr0_tap; - reg [5:0] csr0_pbl; - reg csr0_ble; - reg [4:0] csr0_dsl; - reg csr0_bar; - reg csr0_swr; - - reg [31:0] csr3; - - reg [31:0] csr4; - - reg [2:0] csr5_ts; - reg [2:0] csr5_rs; - reg csr5_nis; - reg csr5_ais; - reg csr5_eri; - reg csr5_gte; - reg csr5_eti; - reg csr5_rps; - reg csr5_ru; - reg csr5_ri; - reg csr5_unf; - reg csr5_tu; - reg csr5_tps; - reg csr5_ti; - - reg csr6_ra; - reg csr6_ttm; - reg csr6_sf; - reg [1:0] csr6_tr; - reg csr6_st; - reg csr6_fd; - reg csr6_pm; - reg csr6_pr; - reg csr6_if; - reg csr6_pb; - reg csr6_ho; - reg csr6_sr; - reg csr6_hp; - - reg csr7_nie; - reg csr7_aie; - reg csr7_ere; - reg csr7_gte; - reg csr7_ete; - reg csr7_rse; - reg csr7_rue; - reg csr7_rie; - reg csr7_une; - reg csr7_tue; - reg csr7_tse; - reg csr7_tie; - - reg [10:0] csr8_foc; - reg csr8_oco; - reg [15:0] csr8_mfc; - reg csr8_mfo; - reg csr8read; - - reg csr9_mdi; - reg csr9_mii; - reg csr9_mdo; - reg csr9_mdc; - reg csr9_sdi; - reg csr9_sclk; - reg csr9_scs; - reg csr9_sdo; - - reg csr10_insert_en; - - reg csr11_cs; - reg [3:0] csr11_tt; - reg [2:0] csr11_ntp; - reg [3:0] csr11_rt; - reg [2:0] csr11_nrp; - reg csr11_con; - reg [15:0] csr11_tim; - reg csr11wr; - - reg tapwr; - reg tpollcmd; - reg itpoll; - reg [2:0] tapcnt; - - reg [1:0] tpsm_c; - reg [1:0] tpsm; - reg tstopcmd; - reg tstartcmd; - reg stoptc_r; - reg stoptlsm_r; - reg stoptfifo_r; - wire [2:0] ts_c; - - reg [1:0] rpsm_c; - reg [1:0] rpsm; - reg rstopcmd; - reg rstartcmd; - reg stoprc_r; - reg stoprlsm_r; - wire [2:0] rs_c; - - reg rpollcmd; - - wire csr5wr_c; - reg csr5wr; - reg gte; - reg iint; - reg rireq_r; - reg rireq_r2; - reg eri; - reg erireq_r; - reg erireq_r2; - reg tireq_r; - reg tireq_r2; - reg eti; - reg etireq_r; - reg etireq_r2; - reg unfi; - reg unf_r; - reg unf_r2; - reg tui; - reg tu_r; - reg tu_r2; - reg rui; - reg ru_r; - reg ru_r2; - reg iic; - - reg rcsreq_r; - reg rcsreq_r1; - reg rimprog; - reg [3:0] rcscnt; - reg rcs2048; - reg rcs128; - reg [3:0] rtcnt; - reg [2:0] rcnt; - reg rimex; - - reg timprog; - reg [7:0] ttcnt; - reg [2:0] tcnt; - reg timex; - reg tcsreq_r1; - reg tcsreq_r2; - reg [3:0] tcscnt; - reg tcs2048; - reg tcs128; - - reg [10:0] foc_c; - reg [15:0] mfc_c; - reg [10:0] focg_r; - reg [15:0] mfcg_r; - - reg gstart; - reg gstart_r; - reg [15:0] gcnt; - wire [CSRWIDTH_MAX + 1:0] csrdatai_max; - wire [CSRWIDTH_MAX + 1:0] czero_max; - wire [CSRWIDTH_MAX/8 + 1:0] csrbe_max; - - assign csraddr10 = csraddr[1:0] ; - - assign csraddr72 = csraddr[7:2] ; - - assign csrbe10 = (CSRWIDTH == 16) ? csrbe_max[1:0] : {2{1'b1}} ; - - always @(csrdatai_max or csrbe_max or csraddr or csraddr10 or csrbe10) - begin : csrdata_proc - csrdata_c <= {32{1'b1}} ; - csrdbe_c <= {4{1'b1}} ; - case (CSRWIDTH) - 8 : - begin - if (csrbe_max[0]) - begin - case (csraddr10) - 2'b00 : - begin - csrdata_c[7:0] <= csrdatai_max[CSRWIDTH-1:0] ; - csrdbe_c <= 4'b0001 ; - end - 2'b01 : - begin - csrdata_c[15:8] <= csrdatai_max[CSRWIDTH-1:0] ; - csrdbe_c <= 4'b0010 ; - end - 2'b10 : - begin - csrdata_c[23:16] <= csrdatai_max[CSRWIDTH-1:0] ; - csrdbe_c <= 4'b0100 ; - end - default : - begin - csrdata_c[31:24] <= csrdatai_max[CSRWIDTH-1:0] ; - csrdbe_c <= 4'b1000 ; - end - endcase - end - else - begin - csrdbe_c <= 4'b0000 ; - end - end - 16 : - begin - case (csrbe10) - 2'b11 : - begin - if (csraddr[1]) - begin - csrdata_c[31:16] <= csrdatai_max[CSRWIDTH-1:0] ; - csrdbe_c <= 4'b1100 ; - end - else - begin - csrdata_c[15:0] <= csrdatai_max[CSRWIDTH-1:0] ; - csrdbe_c <= 4'b0011 ; - end - end - 2'b10 : - begin - if (csraddr[1]) - begin - csrdata_c[31:24] <= - csrdatai_max[CSRWIDTH - 1:CSRWIDTH / 2] ; - csrdbe_c <= 4'b1000 ; - end - else - begin - csrdata_c[15: 8] <= - csrdatai_max[CSRWIDTH - 1:CSRWIDTH / 2] ; - csrdbe_c <= 4'b0010 ; - end - end - 2'b01 : - begin - if (csraddr[1]) - begin - csrdata_c[23:16] <= csrdatai_max[7:0] ; - csrdbe_c <= 4'b0100 ; - end - else - begin - csrdata_c[7:0] <= csrdatai_max[7:0] ; - csrdbe_c <= 4'b0001 ; - end - end - default : - begin - csrdbe_c <= 4'b0000 ; - end - endcase - end - default : - begin - csrdata_c <= csrdatai_max[31:0] ; - csrdbe_c <= csrbe_max[3:0] ; - end - endcase - end - - always @(posedge clk) - begin : csr0_reg_proc - if (rst) - begin - csr0_dbo <= CSR0_RV[20] ; - csr0_tap <= CSR0_RV[19:17] ; - csr0_pbl <= CSR0_RV[13:8] ; - csr0_ble <= CSR0_RV[7] ; - csr0_dsl <= CSR0_RV[6:2] ; - csr0_bar <= CSR0_RV[1] ; - csr0_swr <= CSR0_RV[0] ; - tapwr <= 1'b0 ; - end - else - begin - if (!csrrw & csrreq & csraddr72 == CSR0_ID) - begin - if (csrdbe_c[2]) - begin - csr0_dbo <= csrdata_c[20] ; - csr0_tap <= csrdata_c[19:17] ; - tapwr <= 1'b1 ; - end - else - begin - tapwr <= 1'b0 ; - end - if (csrdbe_c[1]) - begin - csr0_pbl <= csrdata_c[13:8] ; - end - if (csrdbe_c[0]) - begin - csr0_ble <= csrdata_c[7] ; - csr0_dsl <= csrdata_c[6:2] ; - csr0_bar <= csrdata_c[1] ; - csr0_swr <= csrdata_c[0] ; - end - end - else - begin - tapwr <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : tpoolcmd_reg_proc - if (rst) - begin - tpollcmd <= 1'b0 ; - end - else - begin - if (!csrrw & csrreq & csraddr72 == CSR1_ID) - begin - tpollcmd <= 1'b1 ; - end - else - begin - tpollcmd <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : rpoolcmd_reg_proc - if (rst) - begin - rpollcmd <= 1'b0 ; - end - else - begin - if (!csrrw & csrreq & csraddr72 == CSR2_ID) - begin - rpollcmd <= 1'b1 ; - end - else - begin - rpollcmd <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : csr3_reg_proc - if (rst) - begin - csr3 <= CSR3_RV ; - end - else - begin - if (!csrrw & csrreq & csraddr72 == CSR3_ID) - begin - if (csrdbe_c[0]) - begin - csr3[7:0] <= csrdata_c[7:0] ; - end - if (csrdbe_c[1]) - begin - csr3[15:8] <= csrdata_c[15:8] ; - end - if (csrdbe_c[2]) - begin - csr3[23:16] <= csrdata_c[23:16] ; - end - if (csrdbe_c[3]) - begin - csr3[31:24] <= csrdata_c[31:24] ; - end - end - end - end - - assign rdbad = csr3[DATADEPTH - 1:0] ; - - always @(posedge clk) - begin : rdbadc_reg_proc - if (rst) - begin - rdbadc <= 1'b1 ; - end - else - begin - if (!csrrw & csrreq & csraddr72 == CSR3_ID & rpsm == PSM_STOP) - begin - rdbadc <= 1'b1 ; - end - else if (rpsm == PSM_RUN) - begin - rdbadc <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : csr4_reg_proc - if (rst) - begin - csr4 <= CSR4_RV ; - end - else - begin - if (!csrrw & csrreq & csraddr72 == CSR4_ID) - begin - if (csrdbe_c[0]) - begin - csr4[7:0] <= csrdata_c[7:0] ; - end - if (csrdbe_c[1]) - begin - csr4[15:8] <= csrdata_c[15:8] ; - end - if (csrdbe_c[2]) - begin - csr4[23:16] <= csrdata_c[23:16] ; - end - if (csrdbe_c[3]) - begin - csr4[31:24] <= csrdata_c[31:24] ; - end - end - end - end - - always @(posedge clk) - begin : tdbadc_reg_proc - if (rst) - begin - tdbadc <= 1'b1 ; - end - else - begin - if (!csrrw & csrreq & csraddr72 == CSR4_ID) - begin - tdbadc <= 1'b1 ; - end - else if (tpsm == PSM_RUN) - begin - tdbadc <= 1'b0 ; - end - end - end - - assign csr5wr_c = (!csrrw & csrreq & csraddr72 == CSR5_ID) ? 1'b1 : - 1'b0 ; - - always @(posedge clk) - begin : csr5wr_reg_proc - if (rst) - begin - csr5wr <= 1'b0 ; - end - else - begin - csr5wr <= csr5wr_c ; - end - end - - always @(posedge clk) - begin : csr5_reg_proc - if (rst) - begin - csr5_ts <= CSR5_RV[22:20] ; - csr5_rs <= CSR5_RV[19:17] ; - csr5_nis <= CSR5_RV[16] ; - csr5_ais <= CSR5_RV[15] ; - csr5_eri <= CSR5_RV[14] ; - csr5_gte <= CSR5_RV[11] ; - csr5_eti <= CSR5_RV[10] ; - csr5_rps <= CSR5_RV[8] ; - csr5_ru <= CSR5_RV[7] ; - csr5_ri <= CSR5_RV[6] ; - csr5_unf <= CSR5_RV[5] ; - csr5_tu <= CSR5_RV[2] ; - csr5_tps <= CSR5_RV[1] ; - csr5_ti <= CSR5_RV[0] ; - end - else - begin - if (csr5wr_c) - begin - if (csrdbe_c[2]) - begin - csr5_nis <= ~csrdata_c[16] & csr5_nis ; - end - if (csrdbe_c[1]) - begin - csr5_ais <= ~csrdata_c[15] & csr5_ais ; - csr5_eri <= ~csrdata_c[14] & csr5_eri ; - csr5_gte <= ~csrdata_c[11] & csr5_gte ; - csr5_eti <= ~csrdata_c[10] & csr5_eti ; - csr5_rps <= ~csrdata_c[8] & csr5_rps ; - end - if (csrdbe_c[0]) - begin - csr5_ru <= ~csrdata_c[7] & csr5_ru ; - csr5_ri <= ~csrdata_c[6] & csr5_ri ; - csr5_unf <= ~csrdata_c[5] & csr5_unf ; - csr5_tu <= ~csrdata_c[2] & csr5_tu ; - csr5_tps <= ~csrdata_c[1] & csr5_tps ; - csr5_ti <= ~csrdata_c[0] & csr5_ti ; - end - end - else - begin - if (timex) - begin - csr5_ti <= 1'b1 ; - end - if (rimex) - begin - csr5_ri <= 1'b1 ; - end - if (eti) - begin - csr5_eti <= 1'b1 ; - end - if (eri) - begin - csr5_eri <= 1'b1 ; - end - if (gte) - begin - csr5_gte <= 1'b1 ; - end - if (tpsm_c == PSM_STOP & - (tpsm == PSM_RUN | tpsm == PSM_SUSPEND)) - begin - csr5_tps <= 1'b1 ; - end - if (rpsm_c == PSM_STOP & - (rpsm == PSM_RUN | rpsm == PSM_SUSPEND)) - begin - csr5_rps <= 1'b1 ; - end - if (rui) - begin - csr5_ru <= 1'b1 ; - end - if (tui) - begin - csr5_tu <= 1'b1 ; - end - if (unfi) - begin - csr5_unf <= 1'b1 ; - end - if ((csr5_ri & csr7_rie) | - (csr5_ti & csr7_tie) | - (csr5_eri & csr7_ere) | - (csr5_tu & csr7_tue) | - (csr5_gte & csr7_gte)) - begin - csr5_nis <= 1'b1 ; - end - else - begin - csr5_nis <= 1'b0 ; - end - if ((csr5_eti & csr7_ete) | - (csr5_rps & csr7_rse) | - (csr5_ru & csr7_rue) | - (csr5_unf & csr7_une) | - (csr5_tps & csr7_tse)) - begin - csr5_ais <= 1'b1 ; - end - else - begin - csr5_ais <= 1'b0 ; - end - csr5_ts <= ts_c ; - csr5_rs <= rs_c ; - end - end - end - - always @(posedge clk) - begin : csr6_reg_proc - if (rst) - begin - csr6_ra <= CSR6_RV[30] ; - csr6_ttm <= CSR6_RV[22] ; - csr6_sf <= CSR6_RV[21] ; - csr6_tr <= CSR6_RV[15:14] ; - csr6_st <= CSR6_RV[13] ; - csr6_fd <= CSR6_RV[9] ; - csr6_pm <= CSR6_RV[7] ; - csr6_pr <= CSR6_RV[6] ; - csr6_if <= CSR6_RV[4] ; - csr6_pb <= CSR6_RV[3] ; - csr6_ho <= CSR6_RV[2] ; - csr6_sr <= CSR6_RV[1] ; - csr6_hp <= CSR6_RV[0] ; - end - else - begin - if (!csrrw & csrreq & csraddr72 == CSR6_ID) - begin - if (csrdbe_c[3]) - begin - csr6_ra <= csrdata_c[30] ; - end - if (csrdbe_c[2]) - begin - csr6_ttm <= csrdata_c[22] ; - if (tpsm == PSM_STOP) - begin - csr6_sf <= csrdata_c[21] ; - end - end - if (csrdbe_c[1]) - begin - csr6_tr <= csrdata_c[15:14] ; - csr6_st <= csrdata_c[13] ; - csr6_fd <= csrdata_c[9] ; - end - if (csrdbe_c[0]) - begin - csr6_pm <= csrdata_c[7] ; - csr6_pr <= csrdata_c[6] ; - csr6_pb <= csrdata_c[3] ; - csr6_sr <= csrdata_c[1] ; - end - end - case (ft) - FT_PERFECT : - begin - csr6_ho <= 1'b0 ; - csr6_if <= 1'b0 ; - csr6_hp <= 1'b0 ; - end - FT_HASH : - begin - csr6_ho <= 1'b0 ; - csr6_if <= 1'b0 ; - csr6_hp <= 1'b1 ; - end - FT_INVERSE : - begin - csr6_ho <= 1'b0 ; - csr6_if <= 1'b1 ; - csr6_hp <= 1'b0 ; - end - default : - begin - csr6_ho <= 1'b1 ; - csr6_if <= 1'b0 ; - csr6_hp <= 1'b1 ; - end - endcase - end - end - - always @(posedge clk) - begin : csr7_reg_proc - if (rst) - begin - csr7_nie <= CSR7_RV[16] ; - csr7_aie <= CSR7_RV[15] ; - csr7_ere <= CSR7_RV[14] ; - csr7_gte <= CSR7_RV[11] ; - csr7_ete <= CSR7_RV[10] ; - csr7_rse <= CSR7_RV[8] ; - csr7_rue <= CSR7_RV[7] ; - csr7_rie <= CSR7_RV[6] ; - csr7_une <= CSR7_RV[5] ; - csr7_tue <= CSR7_RV[2] ; - csr7_tse <= CSR7_RV[1] ; - csr7_tie <= CSR7_RV[0] ; - end - else - begin - if (!csrrw & csrreq & csraddr72 == CSR7_ID) - begin - if (csrdbe_c[2]) - begin - csr7_nie <= csrdata_c[16] ; - end - if (csrdbe_c[1]) - begin - csr7_aie <= csrdata_c[15] ; - csr7_ere <= csrdata_c[14] ; - csr7_gte <= csrdata_c[11] ; - csr7_ete <= csrdata_c[10] ; - csr7_rse <= csrdata_c[8] ; - end - if (csrdbe_c[0]) - begin - csr7_rue <= csrdata_c[7] ; - csr7_rie <= csrdata_c[6] ; - csr7_une <= csrdata_c[5] ; - csr7_tue <= csrdata_c[2] ; - csr7_tse <= csrdata_c[1] ; - csr7_tie <= csrdata_c[0] ; - end - end - end - end - - always @(posedge clk) - begin : csr8_reg_proc - if (rst) - begin - csr8_oco <= 1'b0 ; - csr8_mfo <= 1'b0 ; - csr8_foc <= {11{1'b0}} ; - csr8_mfc <= {16{1'b0}} ; - end - else - begin - if (!(csrrw & csrreq & csraddr72 == CSR8_ID)) - begin - if (!csr8read) - begin - csr8_foc <= foc_c ; - csr8_mfc <= mfc_c ; - csr8_oco <= oco ; - csr8_mfo <= mfo ; - end - end - end - end - - always @(posedge clk) - begin : csr8read_reg_proc - if (rst) - begin - csr8read <= 1'b0 ; - end - else - begin - if (csrrw & csrreq & csraddr72 == CSR8_ID) - begin - csr8read <= csrdbe_c[3] ; - end - else - begin - csr8read <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : csr9_reg_proc - if (rst) - begin - csr9_mdi <= CSR9_RV[19] ; - csr9_mii <= CSR9_RV[18] ; - csr9_mdo <= CSR9_RV[17] ; - csr9_mdc <= CSR9_RV[16] ; - csr9_sdi <= CSR9_RV[2] ; - csr9_sclk <= CSR9_RV[1] ; - csr9_scs <= CSR9_RV[0] ; - csr9_sdo <= CSR9_RV[3] ; - end - else - begin - if (!csrrw & csrreq & csraddr72 == CSR9_ID) - begin - if (csrdbe_c[0]) - begin - csr9_sclk <= csrdata_c[1] ; - csr9_scs <= csrdata_c[0] ; - csr9_sdo <= csrdata_c[3] ; - end - if (csrdbe_c[2]) - begin - csr9_mii <= csrdata_c[18] ; - csr9_mdo <= csrdata_c[17] ; - csr9_mdc <= csrdata_c[16] ; - end - end - csr9_mdi <= mdi ; - csr9_sdi <= sdi ; - end - end - - always @(posedge clk) - begin : csr10_reg_proc - if (rst) - begin - csr10_insert_en <= CSR10_RV[0]; - end - else - begin - if (!csrrw & csrreq & csraddr72 == CSR10_ID) - begin - csr10_insert_en <= csrdata_c[0]; - end - end - end - - always @(posedge clk) - begin : csr11_reg_proc - if (rst) - begin - csr11_cs <= CSR11_RV[31] ; - csr11_tt <= CSR11_RV[30:27] ; - csr11_ntp <= CSR11_RV[26:24] ; - csr11_rt <= CSR11_RV[23:20] ; - csr11_nrp <= CSR11_RV[19:17] ; - csr11_con <= CSR11_RV[16] ; - csr11_tim <= CSR11_RV[15:0] ; - end - else - begin - if (!csrrw & csrreq & csraddr72 == CSR11_ID) - begin - if (csrdbe_c[3]) - begin - csr11_cs <= csrdata_c[31] ; - csr11_tt <= csrdata_c[30:27] ; - csr11_ntp <= csrdata_c[26:24] ; - end - if (csrdbe_c[2]) - begin - csr11_rt <= csrdata_c[23:20] ; - csr11_nrp <= csrdata_c[19:17] ; - csr11_con <= csrdata_c[16] ; - end - if (csrdbe_c[1]) - begin - csr11_tim[15:8] <= csrdata_c[15:8] ; - end - if (csrdbe_c[0]) - begin - csr11_tim[7:0] <= csrdata_c[7:0] ; - end - end - end - end - - always @(posedge clk) - begin : csr11wr_reg_proc - if (rst) - begin - csr11wr <= 1'b0 ; - end - else - begin - if (!csrrw & csrreq & csraddr72 == CSR11_ID) - begin - csr11wr <= 1'b1 ; - end - else - begin - csr11wr <= 1'b0 ; - end - end - end - - assign csr0 = {CSR0_RV[31:26], CSR0_RV[25:21], csr0_dbo, csr0_tap, - CSR0_RV[16:14], csr0_pbl, csr0_ble, - csr0_dsl, csr0_bar, (rst | csr0_swr)} ; - - assign csr5 = {CSR5_RV[31:23], csr5_ts, csr5_rs, csr5_nis, - csr5_ais, csr5_eri, CSR5_RV[13:12], csr5_gte, csr5_eti, - CSR5_RV[9], csr5_rps, csr5_ru, csr5_ri, csr5_unf, - CSR5_RV[4:3], csr5_tu, csr5_tps, csr5_ti} ; - - assign csr6 = {CSR6_RV[31], csr6_ra, CSR6_RV[29:26], - CSR6_RV[25:23], csr6_ttm, csr6_sf, CSR6_RV[20], - CSR6_RV[19], CSR6_RV[18], CSR6_RV[17], CSR6_RV[16], - csr6_tr, csr6_st, CSR6_RV[13], CSR6_RV[12:11], - csr6_fd, CSR6_RV[8], csr6_pm, csr6_pr, CSR6_RV[5], - csr6_if, csr6_pb, csr6_ho, csr6_sr, csr6_hp} ; - - assign csr7 = {CSR7_RV[31:17], csr7_nie, csr7_aie, csr7_ere, - CSR7_RV[13:12], csr7_gte, csr7_ete, CSR6_RV[9], - csr7_rse, csr7_rue, csr7_rie, csr7_une, - CSR7_RV[4:3], csr7_tue, csr7_tse, csr7_tie} ; - - assign csr8 = {CSR8_RV[31:29], csr8_oco, csr8_foc, - csr8_mfo, csr8_mfc} ; - - assign csr9 = {CSR9_RV[31:20], csr9_mdi, csr9_mii, csr9_mdo, - csr9_mdc, CSR9_RV[15:4], csr9_sdo, csr9_sdi, - csr9_sclk, csr9_scs} ; - - assign csr10 = {CSR10_RV[31:1], csr10_insert_en}; - - assign csr11 = {csr11_cs, ttcnt[7:4], tcnt[2:0], rtcnt[3:0], - rcnt[2:0], csr11_con, gcnt} ; - - always @(csr0 or - csr3 or - csr4 or - csr5 or - csr6 or - csr7 or - csr8 or - csr9 or - csr10 or - csr11 or - csraddr or - csraddr72 or - csraddr10) - begin : csrmux_proc - case (CSRWIDTH) - 8 : - begin - case (csraddr10) - 2'b00 : - begin - case (csraddr72) - CSR0_ID : - begin - csrdatao <= csr0[7:0] ; - end - CSR3_ID : - begin - csrdatao <= csr3[7:0] ; - end - CSR4_ID : - begin - csrdatao <= csr4[7:0] ; - end - CSR5_ID : - begin - csrdatao <= csr5[7:0] ; - end - CSR6_ID : - begin - csrdatao <= csr6[7:0] ; - end - CSR7_ID : - begin - csrdatao <= csr7[7:0] ; - end - CSR8_ID : - begin - csrdatao <= csr8[7:0] ; - end - CSR9_ID : - begin - csrdatao <= csr9[7:0] ; - end - CSR10_ID : - begin - csrdatao <= csr10[7:0] ; - end - CSR11_ID : - begin - csrdatao <= csr11[7:0] ; - end - default : - begin - csrdatao <= {CSRWIDTH{1'b0}} ; - end - endcase - end - 2'b01 : - begin - case (csraddr72) - CSR0_ID : - begin - csrdatao <= csr0[15:8] ; - end - CSR3_ID : - begin - csrdatao <= csr3[15:8] ; - end - CSR4_ID : - begin - csrdatao <= csr4[15:8] ; - end - CSR5_ID : - begin - csrdatao <= csr5[15:8] ; - end - CSR6_ID : - begin - csrdatao <= csr6[15:8] ; - end - CSR7_ID : - begin - csrdatao <= csr7[15:8] ; - end - CSR8_ID : - begin - csrdatao <= csr8[15:8] ; - end - CSR9_ID : - begin - csrdatao <= csr9[15:8] ; - end - CSR10_ID : - begin - csrdatao <= csr10[15:8] ; - end - CSR11_ID : - begin - csrdatao <= csr11[15:8] ; - end - default : - begin - csrdatao <= {CSRWIDTH{1'b0}} ; - end - endcase - end - 2'b10 : - begin - case (csraddr72) - CSR0_ID : - begin - csrdatao <= csr0[23:16] ; - end - CSR3_ID : - begin - csrdatao <= csr3[23:16] ; - end - CSR4_ID : - begin - csrdatao <= csr4[23:16] ; - end - CSR5_ID : - begin - csrdatao <= csr5[23:16] ; - end - CSR6_ID : - begin - csrdatao <= csr6[23:16] ; - end - CSR7_ID : - begin - csrdatao <= csr7[23:16] ; - end - CSR8_ID : - begin - csrdatao <= csr8[23:16] ; - end - CSR9_ID : - begin - csrdatao <= csr9[23:16] ; - end - CSR10_ID : - begin - csrdatao <= csr10[23:16] ; - end - CSR11_ID : - begin - csrdatao <= csr11[23:16] ; - end - default : - begin - csrdatao <= {CSRWIDTH{1'b0}} ; - end - endcase - end - 2'b11 : - begin - case (csraddr72) - CSR0_ID : - begin - csrdatao <= csr0[31:24] ; - end - CSR3_ID : - begin - csrdatao <= csr3[31:24] ; - end - CSR4_ID : - begin - csrdatao <= csr4[31:24] ; - end - CSR5_ID : - begin - csrdatao <= csr5[31:24] ; - end - CSR6_ID : - begin - csrdatao <= csr6[31:24] ; - end - CSR7_ID : - begin - csrdatao <= csr7[31:24] ; - end - CSR8_ID : - begin - csrdatao <= csr8[31:24] ; - end - CSR9_ID : - begin - csrdatao <= csr9[31:24] ; - end - CSR10_ID : - begin - csrdatao <= csr10[31:24] ; - end - CSR11_ID : - begin - csrdatao <= csr11[31:24] ; - end - default : - begin - csrdatao <= {CSRWIDTH{1'b0}} ; - end - endcase - end - default : - begin - csrdatao <= {CSRWIDTH{1'b0}} ; - end - endcase - end - 16 : - begin - case (csraddr[1]) - 1'b0 : - begin - case (csraddr72) - CSR0_ID : - begin - csrdatao <= csr0[15:0] ; - end - CSR3_ID : - begin - csrdatao <= csr3[15:0] ; - end - CSR4_ID : - begin - csrdatao <= csr4[15:0] ; - end - CSR5_ID : - begin - csrdatao <= csr5[15:0] ; - end - CSR6_ID : - begin - csrdatao <= csr6[15:0] ; - end - CSR7_ID : - begin - csrdatao <= csr7[15:0] ; - end - CSR8_ID : - begin - csrdatao <= csr8[15:0] ; - end - CSR9_ID : - begin - csrdatao <= csr9[15:0] ; - end - CSR10_ID : - begin - csrdatao <= csr10[15:0] ; - end - CSR11_ID : - begin - csrdatao <= csr11[15:0] ; - end - default : - begin - csrdatao <= {CSRWIDTH{1'b0}} ; - end - endcase - end - 1'b1 : - begin - case (csraddr72) - CSR0_ID : - begin - csrdatao <= csr0[31:16] ; - end - CSR3_ID : - begin - csrdatao <= csr3[31:16] ; - end - CSR4_ID : - begin - csrdatao <= csr4[31:16] ; - end - CSR5_ID : - begin - csrdatao <= csr5[31:16] ; - end - CSR6_ID : - begin - csrdatao <= csr6[31:16] ; - end - CSR7_ID : - begin - csrdatao <= csr7[31:16] ; - end - CSR8_ID : - begin - csrdatao <= csr8[31:16] ; - end - CSR9_ID : - begin - csrdatao <= csr9[31:16] ; - end - CSR10_ID : - begin - csrdatao <= csr10[31:16] ; - end - CSR11_ID : - begin - csrdatao <= csr11[31:16] ; - end - default : - begin - csrdatao <= {CSRWIDTH{1'b0}} ; - end - endcase - end - default : - begin - csrdatao <= {CSRWIDTH{1'b0}} ; - end - endcase - end - default : - begin - case (csraddr72) - CSR0_ID : - begin - csrdatao <= csr0 ; - end - CSR3_ID : - begin - csrdatao <= csr3 ; - end - CSR4_ID : - begin - csrdatao <= csr4 ; - end - CSR5_ID : - begin - csrdatao <= csr5 ; - end - CSR6_ID : - begin - csrdatao <= csr6 ; - end - CSR7_ID : - begin - csrdatao <= csr7 ; - end - CSR8_ID : - begin - csrdatao <= csr8 ; - end - CSR9_ID : - begin - csrdatao <= csr9 ; - end - CSR10_ID : - begin - csrdatao <= csr10 ; - end - CSR11_ID : - begin - csrdatao <= csr11 ; - end - default : - begin - csrdatao <= {CSRWIDTH{1'b0}} ; - end - endcase - end - endcase - end - - assign csrack = 1'b1 ; - - assign dma_priority = (csr0_bar & !tprog) ? 2'b01 : - (csr0_bar & tprog) ? 2'b10 : - 2'b00 ; - - assign dbo = csr0_dbo ; - - assign pbl = csr0_pbl ; - - assign dsl = csr0_dsl ; - - assign ble = csr0_ble ; - - assign tdbad = csr4[DATADEPTH - 1:0] ; - - always @(posedge clk) - begin : itpoll_reg_proc - if (rst) - begin - itpoll <= 1'b0 ; - end - else - begin - if (((((csr0_tap == 3'b001 | - csr0_tap == 3'b010 | - csr0_tap == 3'b011) & tcs2048) | - ((csr0_tap == 3'b100 | - csr0_tap == 3'b101 | - csr0_tap == 3'b110 | - csr0_tap == 3'b111) & tcs128)) & - tapcnt == 3'b000 & tpsm == PSM_SUSPEND) | - tpollcmd | tstartcmd) - begin - itpoll <= 1'b1 ; - end - else if (tpollack) - begin - itpoll <= 1'b0 ; - end - end - end - - assign tpoll = itpoll ; - - always @(posedge clk) - begin : tap_reg_proc - if (rst) - begin - tapcnt <= {3{1'b1}} ; - end - else - begin - if (((csr0_tap == 3'b001 | - csr0_tap == 3'b010 | - csr0_tap == 3'b011) & (tcs2048 | tapwr)) | - ((csr0_tap == 3'b100 | - csr0_tap == 3'b101 | - csr0_tap == 3'b110 | - csr0_tap == 3'b111) & (tcs128 | tapwr))) - begin - if (tapcnt == 3'b000 | tapwr) - begin - case (csr0_tap) - 3'b001 : - begin - tapcnt <= 3'b000 ; - end - 3'b010 : - begin - tapcnt <= 3'b010 ; - end - 3'b011 : - begin - tapcnt <= 3'b110 ; - end - 3'b100 : - begin - tapcnt <= 3'b000 ; - end - 3'b101 : - begin - tapcnt <= 3'b001 ; - end - 3'b110 : - begin - tapcnt <= 3'b010 ; - end - default : - begin - tapcnt <= 3'b111 ; - end - endcase - end - else - begin - tapcnt <= tapcnt - 1 ; - end - end - end - end - - assign tm = {csr6_ttm, csr6_tr} ; - - assign sf = csr6_sf ; - - always @(posedge clk) - begin : tim_reg_proc - if (rst) - begin - timprog <= 1'b0 ; - timex <= 1'b0 ; - ttcnt <= {8{1'b1}} ; - tcnt <= {3{1'b1}} ; - end - else - begin - if (csr5_ti) - begin - timprog <= 1'b0 ; - end - else if (tireq_r & !tireq_r2) - begin - timprog <= 1'b1 ; - end - - if (csr5_ti) - begin - timex <= 1'b0 ; - end - else if (timprog & - ((ttcnt == 8'b00000000 & csr11_tt != 4'b0000) | - (tcnt == 3'b000 & csr11_ntp != 3'b000) | - (iic) | - (csr11_tt == 4'b0000 & csr11_ntp == 3'b000))) - begin - timex <= 1'b1 ; - end - - if ((tireq_r & !tireq_r2) | csr5_ti | csr11wr) - begin - ttcnt <= {csr11_tt, 4'b0000} ; - end - else if (((tcs128 & csr11_cs) | - (tcs2048 & !csr11_cs)) & - ttcnt != 8'b00000000 & timprog) - begin - ttcnt <= ttcnt - 1 ; - end - - if (csr5_ti | csr11wr) - begin - tcnt <= csr11_ntp ; - end - else if (tireq_r & !tireq_r2 & - tcnt != 3'b000 & csr11_ntp != 3'b000) - begin - tcnt <= tcnt - 1 ; - end - end - end - - always @(posedge clk) - begin : tcscnt_reg_proc - if (rst) - begin - tcsreq_r1 <= 1'b0 ; - tcsreq_r2 <= 1'b0 ; - tcs2048 <= 1'b0 ; - tcs128 <= 1'b0 ; - tcscnt <= {4{1'b1}} ; - end - else - begin - tcsreq_r1 <= tcsreq ; - tcsreq_r2 <= tcsreq_r1 ; - - if (tcs128) - begin - if (tcscnt == 4'b0000) - begin - tcscnt <= 4'b1111 ; - end - else - begin - tcscnt <= tcscnt - 1 ; - end - end - - if (tcsreq_r1 & !tcsreq_r2) - begin - tcs128 <= 1'b1 ; - end - else - begin - tcs128 <= 1'b0 ; - end - - if (tcscnt == 4'b0000 & tcs128) - begin - tcs2048 <= 1'b1 ; - end - else - begin - tcs2048 <= 1'b0 ; - end - - end - end - - assign tcsack = tcsreq_r2 ; - - always @(posedge clk) - begin : st_reg_proc - if (rst) - begin - tstopcmd <= 1'b1 ; - tstartcmd <= 1'b0 ; - end - else - begin - if (tstartcmd) - begin - tstopcmd <= 1'b0 ; - end - else if (!csrrw & csrreq & !(csrdata_c[13]) & - csraddr72 == CSR6_ID & (csrdbe_c[1])) - begin - tstopcmd <= 1'b1 ; - end - - if (tpsm == PSM_RUN | tpsm == PSM_SUSPEND) - begin - tstartcmd <= 1'b0 ; - end - else if (!csrrw & csrreq & (csrdata_c[13]) & - csraddr72 == CSR6_ID & (csrdbe_c[1])) - begin - tstartcmd <= 1'b1 ; - end - - end - end - - assign ts_c = (tpsm == PSM_STOP) ? 3'b000 : - (tpsm == PSM_SUSPEND) ? 3'b110 : - (tstat) ? 3'b111 : - (tdes) ? 3'b001 : - (tset) ? 3'b101 : - (tbuf) ? 3'b011 : - (tprog) ? 3'b010 : - csr5_ts ; - - always @(posedge clk) - begin : tpsack_reg_proc - if (rst) - begin - stoptc_r <= 1'b0 ; - stoptlsm_r <= 1'b0 ; - stoptfifo_r <= 1'b0 ; - end - else - begin - stoptc_r <= stoptc ; - stoptlsm_r <= stoptlsm ; - stoptfifo_r <= stoptfifo ; - end - end - - always @(tpsm or - tstartcmd or - tstopcmd or - tu_r or - stoptc_r or - stoptlsm_r or - stoptfifo_r) - begin : tpsm_proc - case (tpsm) - PSM_STOP : - begin - if (tstartcmd & !stoptc_r & !stoptlsm_r & !stoptfifo_r) - begin - tpsm_c <= PSM_RUN ; - end - else - begin - tpsm_c <= PSM_STOP ; - end - end - PSM_SUSPEND : - begin - if (tstopcmd & stoptc_r & stoptlsm_r & stoptfifo_r) - begin - tpsm_c <= PSM_STOP ; - end - else if (!tu_r) - begin - tpsm_c <= PSM_RUN ; - end - else - begin - tpsm_c <= PSM_SUSPEND ; - end - end - default : - begin - if (tstopcmd & stoptc_r & stoptlsm_r & stoptfifo_r) - begin - tpsm_c <= PSM_STOP ; - end - else if (tu_r) - begin - tpsm_c <= PSM_SUSPEND ; - end - else - begin - tpsm_c <= PSM_RUN ; - end - end - endcase - end - - always @(posedge clk) - begin : tpsm_reg_proc - if (rst) - begin - tpsm <= PSM_STOP ; - end - else - begin - tpsm <= tpsm_c ; - end - end - - always @(posedge clk) - begin : tps_reg_proc - if (rst) - begin - tps <= 1'b0 ; - end - else - begin - if (tstartcmd) - begin - tps <= 1'b0 ; - end - else if (tpsm == PSM_STOP) - begin - tps <= 1'b1 ; - end - end - end - - assign stopt = tstopcmd ; - - assign ren = csr6_sr ; - - assign fd = csr6_fd ; - - assign ra = csr6_ra ; - - assign pm = csr6_pm ; - - assign pr = csr6_pr ; - - assign rif = csr6_if ; - - assign pb = csr6_pb ; - - assign ho = csr6_ho ; - - assign hp = csr6_hp ; - - always @(posedge clk) - begin : rpoll_reg_proc - if (rst) - begin - rpoll <= 1'b0 ; - end - else - begin - if (rpollcmd | rstartcmd) - begin - rpoll <= 1'b1 ; - end - else if (rpollack) - begin - rpoll <= 1'b0 ; - end - end - end - - assign rs_c = (rpsm == PSM_STOP) ? 3'b000 : - (rpsm == PSM_SUSPEND) ? 3'b100 : - (rstat) ? 3'b101 : - (rdes) ? 3'b001 : - (rbuf) ? 3'b111 : - (rprog) ? 3'b010 : - 3'b011 ; - - always @(posedge clk) - begin : rpsack_reg_proc - if (rst) - begin - stoprc_r <= 1'b0 ; - stoprlsm_r <= 1'b0 ; - end - else - begin - stoprc_r <= stoprc ; - stoprlsm_r <= stoprlsm ; - end - end - - always @(rpsm or - rstartcmd or - rstopcmd or - rui or - ru_r or - stoprc_r or - stoprlsm_r) - begin : rpsm_proc - case (rpsm) - PSM_STOP : - begin - if (rstartcmd & !stoprc_r & !stoprlsm_r) - begin - rpsm_c <= PSM_RUN ; - end - else - begin - rpsm_c <= PSM_STOP ; - end - end - PSM_SUSPEND : - begin - if (rstopcmd & stoprc_r & stoprlsm_r) - begin - rpsm_c <= PSM_STOP ; - end - else if (!ru_r) - begin - rpsm_c <= PSM_RUN ; - end - else - begin - rpsm_c <= PSM_SUSPEND ; - end - end - default : - begin - if (rstopcmd & stoprc_r & stoprlsm_r) - begin - rpsm_c <= PSM_STOP ; - end - else if (rui) - begin - rpsm_c <= PSM_SUSPEND ; - end - else - begin - rpsm_c <= PSM_RUN ; - end - end - endcase - end - - always @(posedge clk) - begin : rpsm_reg_proc - if (rst) - begin - rpsm <= PSM_STOP ; - end - else - begin - rpsm <= rpsm_c ; - end - end - - always @(posedge clk) - begin : rps_reg_proc - if (rst) - begin - rps <= 1'b0 ; - end - else - begin - if (rstartcmd) - begin - rps <= 1'b0 ; - end - else if (rpsm == PSM_STOP) - begin - rps <= 1'b1 ; - end - end - end - - always @(posedge clk) - begin : rstartcmd_reg_proc - if (rst) - begin - rstartcmd <= 1'b0 ; - rstopcmd <= 1'b0 ; - end - else - begin - if (rpsm == PSM_RUN) - begin - rstartcmd <= 1'b0 ; - end - else if (!csrrw & csrreq & (csrdata_c[1]) & - csraddr72 == CSR6_ID & (csrdbe_c[0])) - begin - rstartcmd <= 1'b1 ; - end - - if (rpsm == PSM_STOP) - begin - rstopcmd <= 1'b0 ; - end - else if (!csrrw & csrreq & !(csrdata_c[1]) & - csraddr72 == CSR6_ID & (csrdbe_c[0])) - begin - rstopcmd <= 1'b1 ; - end - end - end - - assign stopr = rstopcmd ; - - always @(posedge clk) - begin : rim_reg_proc - if (rst) - begin - rimex <= 1'b0 ; - rimprog <= 1'b0 ; - rtcnt <= {4{1'b1}} ; - rcnt <= {3{1'b1}} ; - end - else - begin - if (csr5_ri) - begin - rimex <= 1'b0 ; - end - else if (rimprog & - ((rtcnt == 4'b0000 & csr11_rt != 4'b0000) | - (rcnt == 3'b000 & csr11_nrp != 3'b000) | - (csr11_rt == 4'b0000 & csr11_nrp == 3'b000))) - begin - rimex <= 1'b1 ; - end - - if (csr5_ri) - begin - rimprog <= 1'b0 ; - end - else if (rireq_r & !rireq_r2) - begin - rimprog <= 1'b1 ; - end - - if ((rireq_r & !rireq_r2) | csr5_ri) - begin - rtcnt <= csr11_rt ; - end - else if (((rcs128 & csr11_cs) | - (rcs2048 & !csr11_cs)) & - rtcnt != 4'b0000 & rimprog) - begin - rtcnt <= rtcnt - 1 ; - end - - if (csr5_ri | csr11wr) - begin - rcnt <= csr11_nrp ; - end - else if (rireq_r & !rireq_r2 & - rcnt != 3'b000 & csr11_nrp != 3'b000) - begin - rcnt <= rcnt - 1 ; - end - - end - end - - always @(posedge clk) - begin : rcscnt_reg_proc - if (rst) - begin - rcsreq_r <= 1'b0 ; - rcsreq_r1 <= 1'b0 ; - rcscnt <= {4{1'b1}} ; - rcs128 <= 1'b0 ; - rcs2048 <= 1'b0 ; - end - else - begin - - rcsreq_r <= rcsreq ; - rcsreq_r1 <= rcsreq_r ; - - if (rcs128) - begin - if (rcscnt == 4'b0000) - begin - rcscnt <= 4'b1111 ; - end - else - begin - rcscnt <= rcscnt - 1 ; - end - end - - if (rcsreq_r & !rcsreq_r1) - begin - rcs128 <= 1'b1 ; - end - else - begin - rcs128 <= 1'b0 ; - end - - if (rcscnt == 4'b0000 & rcs128) - begin - rcs2048 <= 1'b1 ; - end - else - begin - rcs2048 <= 1'b0 ; - end - end - end - - assign rcsack = rcsreq_r ; - - always @(posedge clk) - begin : ireq_reg_proc - if (rst) - begin - rireq_r <= 1'b0 ; - rireq_r2 <= 1'b0 ; - erireq_r <= 1'b0 ; - erireq_r2 <= 1'b0 ; - tireq_r <= 1'b0 ; - tireq_r2 <= 1'b0 ; - etireq_r <= 1'b0 ; - etireq_r2 <= 1'b0 ; - unf_r <= 1'b0 ; - unf_r2 <= 1'b0 ; - tu_r <= 1'b0 ; - tu_r2 <= 1'b0 ; - ru_r <= 1'b0 ; - ru_r2 <= 1'b0 ; - end - else - begin - rireq_r <= rireq ; - rireq_r2 <= rireq_r ; - erireq_r <= erireq ; - erireq_r2 <= erireq_r ; - tireq_r <= tireq ; - tireq_r2 <= tireq_r ; - etireq_r <= etireq ; - etireq_r2 <= etireq_r ; - unf_r <= unf ; - unf_r2 <= unf_r ; - tu_r <= tu ; - tu_r2 <= tu_r ; - ru_r <= ru ; - ru_r2 <= ru_r ; - end - end - - always @(posedge clk) - begin : iic_reg_proc - if (rst) - begin - iic <= 1'b0 ; - end - else - begin - if (tireq_r & !tireq_r2) - begin - if (!ic & !iint) - begin - iic <= 1'b0 ; - end - else - begin - iic <= 1'b1 ; - end - end - end - end - - always @(posedge clk) - begin : eti_reg_proc - if (rst) - begin - eti <= 1'b0 ; - end - else - begin - if (etireq_r & !etireq_r2) - begin - eti <= 1'b1 ; - end - else if (!csr5wr_c) - begin - eti <= 1'b0 ; - end - end - end - - assign etiack = etireq_r2 ; - - always @(posedge clk) - begin : eri_reg_proc - if (rst) - begin - eri <= 1'b0 ; - end - else - begin - if (erireq_r & !erireq_r2) - begin - eri <= 1'b1 ; - end - else if (!csr5wr_c) - begin - eri <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : unfi_reg_proc - if (rst) - begin - unfi <= 1'b0 ; - end - else - begin - if (unf_r & !unf_r2) - begin - unfi <= 1'b1 ; - end - else if (!csr5wr_c) - begin - unfi <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : tui_reg_proc - if (rst) - begin - tui <= 1'b0 ; - end - else - begin - if (tu_r & !tu_r2) - begin - tui <= 1'b1 ; - end - else if (!csr5wr_c) - begin - tui <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : rui_reg_proc - if (rst) - begin - rui <= 1'b0 ; - end - else - begin - if (ru_r & !ru_r2) - begin - rui <= 1'b1 ; - end - else if (!csr5wr_c) - begin - rui <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : iint_reg_proc - if (rst) - begin - iint <= 1'b0 ; - end - else - begin - iint <= ((csr5_nis && csr7_nie) || - (csr5_ais && csr7_aie)) && ~csr5wr; - end - end - - assign interrupt = iint ; - - assign riack = rireq_r2 ; - - assign eriack = erireq_r2 ; - - assign tiack = tireq_r2 ; - - always @(focg_r) - begin : foc_proc - reg [10:0] foc_v; - - foc_v[10] = focg_r[10] ; - begin : foc_loop - integer i; - for(i = 9; i >= 0; i = i - 1) - begin - foc_v[i] = foc_v[i + 1] ^ focg_r[i] ; - end - end - foc_c = foc_v; - end - - always @(mfcg_r) - begin : mfc_proc - reg [15:0] mfc_v; - - mfc_v[15] = mfcg_r[10] ; - begin : mfc_loop - integer i; - for(i = 14; i >= 0; i = i - 1) - begin - mfc_v[i] = mfc_v[i + 1] ^ mfcg_r[i] ; - end - end - mfc_c = mfc_v; - end - - always @(posedge clk) - begin : sc_reg_proc - if (rst) - begin - focl <= 1'b0 ; - mfcl <= 1'b0 ; - focg_r <= {11{1'b0}} ; - mfcg_r <= {16{1'b0}} ; - end - else - begin - if (csr8read) - begin - focl <= 1'b1 ; - end - else if (foclack) - begin - focl <= 1'b0 ; - end - - if (csr8read) - begin - mfcl <= 1'b1 ; - end - else if (mfclack) - begin - mfcl <= 1'b0 ; - end - - mfcg_r <= mfcg ; - - focg_r <= focg ; - - end - end - - assign mdo = csr9_mdo ; - - assign mden = csr9_mii ; - - assign mdc = csr9_mdc ; - - assign sclk = csr9_sclk ; - - assign scs = csr9_scs ; - - assign sdo = csr9_sdo ; - - - assign insert_en_o = csr10_insert_en; - - always @(posedge clk) - begin : gpt_reg_proc - if (rst) - begin - gstart <= 1'b0 ; - gstart_r <= 1'b0 ; - gcnt <= {16{1'b0}} ; - gte <= 1'b0 ; - end - else - begin - if (!csrrw & csrreq & (csrdbe_c[3]) & csraddr72 == CSR11_ID) - begin - gstart <= 1'b1 ; - end - else if ((!csr11_con & gte) | - csr11_tim == 16'b0000000000000000) - begin - gstart <= 1'b0 ; - end - - if(csr11_tim != 16'b0000000000000000) - begin - gstart_r <= gstart ; - end - else - begin - gstart_r <= 1'b0 ; - end - - if (gstart & !gstart_r) - begin - gcnt <= csr11_tim ; - end - else if (gcnt == 16'b0000000000000000) - begin - if (csr11_con) - begin - gcnt <= csr11_tim ; - end - end - else if (tcs2048) - begin - gcnt <= gcnt - 1 ; - end - - if (csr5wr_c) - begin - gte <= 1'b0 ; - end - else if (gstart_r & gcnt == 16'b0000000000000000 & - csr11_tim != 16'b0000000000000000) - begin - gte <= 1'b1 ; - end - - end - end - - always @(posedge clk) - begin : rstsofto_reg_proc - rstsofto <= csr0_swr; - end - - assign czero_max = {CSRWIDTH_MAX{1'b0}} ; - - assign csrdatai_max = {czero_max[CSRWIDTH_MAX+1:CSRWIDTH], - csrdatai}; - - assign csrbe_max = {czero_max[CSRWIDTH_MAX/8+1:CSRWIDTH/8], - csrbe}; - -endmodule diff --git a/resources/soc/rtl/MAC/dma.v b/resources/soc/rtl/MAC/dma.v deleted file mode 100644 index 62292bb..0000000 --- a/resources/soc/rtl/MAC/dma.v +++ /dev/null @@ -1,646 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -module DMA ( - clk, - rst, - dma_priority, - ble, - dbo, - rdes, - rbuf, - rstat, - tdes, - tbuf, - tstat, - dataack, - datai, - datareq, - datareqc, - datarw, - dataeob, - dataeobc, - datao, - dataaddr, - idataaddr, - req1, - write1, - tcnt1, - addr1, - datai1, - ack1, - eob1, - datao1, - req2, - write2, - tcnt2, - addr2, - datai2, - ack2, - eob2, - datao2); - - parameter DATAWIDTH = 32; - parameter DATADEPTH = 32; - - `include "utility.v" - - input clk; - input rst; - - input [1:0] dma_priority; - input ble; - input dbo; - input rdes; - input rbuf; - input rstat; - input tdes; - input tbuf; - input tstat; - - - input dataack; - input [DATAWIDTH - 1:0] datai; - output datareq; - wire datareq; - output datareqc; - wire datareqc; - output datarw; - reg datarw; - output dataeob; - wire dataeob; - output dataeobc; - wire dataeobc; - output [DATAWIDTH - 1:0] datao; - wire [DATAWIDTH - 1:0] datao; - output [DATADEPTH - 1:0] dataaddr; - wire [DATADEPTH - 1:0] dataaddr; - output [DATADEPTH - 1:0] idataaddr; - wire [DATADEPTH - 1:0] idataaddr; - - input req1; - input write1; - input [FIFODEPTH_MAX - 1:0] tcnt1; - input [DATADEPTH - 1:0] addr1; - input [DATAWIDTH - 1:0] datai1; - output ack1; - wire ack1; - output eob1; - wire eob1; - output [DATAWIDTH - 1:0] datao1; - wire [DATAWIDTH - 1:0] datao1; - - input req2; - input write2; - input [FIFODEPTH_MAX - 1:0] tcnt2; - input [DATADEPTH - 1:0] addr2; - input [DATAWIDTH - 1:0] datai2; - output ack2; - wire ack2; - output eob2; - wire eob2; - output [DATAWIDTH - 1:0] datao2; - wire [DATAWIDTH - 1:0] datao2; - - - reg [1:0] dsm_c; - reg [1:0] dsm; - reg hist1; - reg hist2; - wire [1:0] dmareq; - reg [FIFODEPTH_MAX - 1:0] msmbcnt; - reg idatareq; - reg idatareqc; - reg eob; - reg eobc; - reg [DATADEPTH - 1:0] addr_c; - reg [DATADEPTH - 1:0] addr; - reg blesel_c; - reg [DATAWIDTH - 1:0] dataible_c; - reg [DATAWIDTH - 1:0] dataoble_c; - wire [DATAWIDTH_MAX + 1:0] datai_max; - reg req_c; - reg write_c; - reg [FIFODEPTH_MAX - 1:0] tcnt_c; - reg [DATADEPTH - 1:0] saddr_c; - reg [DATAWIDTH_MAX - 1:0] datai_c; - wire [DATAWIDTH_MAX + 1:0] datai_max_c; - wire [FIFODEPTH_MAX - 1:0] fzero; - wire [DATAWIDTH_MAX + 1:0] dzero; - - assign dmareq = {req2, req1} ; - - always @(dsm or - dmareq or - hist1 or - hist2 or - dma_priority or - eob or - dataack) - begin : dsm_proc - case (dsm) - DSM_IDLE : - begin - case (dmareq) - 2'b11 : - begin - case (dma_priority) - 2'b01 : - begin - if (!hist1 & !hist2) - begin - dsm_c <= DSM_CH2 ; - end - else - begin - dsm_c <= DSM_CH1 ; - end - end - 2'b10 : - begin - if (hist1 & hist2) - begin - dsm_c <= DSM_CH1 ; - end - else - begin - dsm_c <= DSM_CH2 ; - end - end - default : - begin - if (hist1) - begin - dsm_c <= DSM_CH1 ; - end - else - begin - dsm_c <= DSM_CH2 ; - end - end - endcase - end - 2'b01 : - begin - dsm_c <= DSM_CH1 ; - end - 2'b10 : - begin - dsm_c <= DSM_CH2 ; - end - default : - begin - dsm_c <= DSM_IDLE ; - end - endcase - end - DSM_CH1 : - begin - if (eob & dataack) - begin - dsm_c <= DSM_IDLE ; - end - else - begin - dsm_c <= DSM_CH1 ; - end - end - default : - begin - if (eob & dataack) - begin - dsm_c <= DSM_IDLE ; - end - else - begin - dsm_c <= DSM_CH2 ; - end - end - endcase - end - - always @(posedge clk) - begin : dsm_reg_proc - if (rst) - begin - dsm <= DSM_IDLE ; - end - else - begin - dsm <= dsm_c ; - end - end - - always @(posedge clk) - begin : hist_reg_proc - if (rst) - begin - hist1 <= 1'b1 ; - hist2 <= 1'b1 ; - end - else - begin - if (eob) - begin - case (dsm) - DSM_CH1 : - begin - hist1 <= 1'b1 ; - end - DSM_CH2 : - begin - hist1 <= 1'b0 ; - end - default : - begin - hist1 <= hist1 ; - end - endcase - end - hist2 <= hist1 ; - end - end - - always @(dbo or - ble or - dsm_c or - dsm or - tdes or - tbuf or - tstat or - rdes or - rbuf or - rstat) - begin : blesel_proc - if (dsm_c == DSM_CH1 | dsm == DSM_CH1) - begin - if ((tbuf & ble) | - ((tdes | tstat) & dbo)) - begin - blesel_c <= 1'b1 ; - end - else - begin - blesel_c <= 1'b0 ; - end - end - else - begin - if ((rbuf & ble) | - ((rdes | rstat) & dbo)) - begin - blesel_c <= 1'b1 ; - end - else - begin - blesel_c <= 1'b0 ; - end - end - end - - always @(dsm_c or - dsm or - req1 or - write1 or - tcnt1 or - addr1 or - datai1 or - req2 or - write2 or - tcnt2 or - addr2 or - datai2) - begin : chmux_proc - if (dsm_c == DSM_CH1 | dsm == DSM_CH1) - begin - req_c <= req1 ; - write_c <= write1 ; - tcnt_c <= tcnt1 ; - saddr_c <= addr1 ; - datai_c <= {{((DATAWIDTH_MAX+1)-DATAWIDTH){1'b0}},datai1} ; - end - else - begin - req_c <= req2 ; - write_c <= write2 ; - tcnt_c <= tcnt2 ; - saddr_c <= addr2 ; - datai_c <= {{((DATAWIDTH_MAX+1)-DATAWIDTH){1'b0}},datai2} ; - end - end - - assign datai_max_c = {dzero[DATAWIDTH_MAX+1:DATAWIDTH],datai_c}; - - always @(datai_max_c or blesel_c) - begin : dataoble_proc - case (DATAWIDTH) - 32 : - begin - if (blesel_c) - begin - dataoble_c <= {datai_max_c[ 7: 0], - datai_max_c[15: 8], - datai_max_c[23:16], - datai_max_c[31:24]}; - end - else - begin - dataoble_c <= datai_max_c[31:0]; - end - end - 16 : - begin - if (blesel_c) - begin - dataoble_c <= {datai_max_c[7 :0], - datai_max_c[15:8]}; - end - else - begin - dataoble_c <= datai_max_c[15:0]; - end - end - default : - begin - dataoble_c <= datai_max_c[7:0]; - end - endcase - end - - assign datai_max = {dzero[DATAWIDTH_MAX+1:DATAWIDTH],datai}; - - always @(datai_max or blesel_c) - begin : dataible_proc - case (DATAWIDTH) - 32 : - begin - if (blesel_c) - begin - dataible_c <= {datai_max[ 7: 0], - datai_max[15: 8], - datai_max[23:16], - datai_max[31:24]}; - end - else - begin - dataible_c <= datai_max[31:0]; - end - end - 16 : - begin - if (blesel_c) - begin - dataible_c <= {datai_max[7 :0], - datai_max[15:8]}; - end - else - begin - dataible_c <= datai_max[15:0]; - end - end - default : - begin - dataible_c <= datai_max[7:0]; - end - endcase - end - - always @(posedge clk) - begin : msmbcnt_reg_proc - if (rst) - begin - msmbcnt <= {FIFODEPTH_MAX{1'b0}} ; - end - else - begin - if (!idatareq) - begin - msmbcnt <= tcnt_c ; - end - else if (dataack & idatareq) - begin - msmbcnt <= msmbcnt - 1 ; - end - end - end - - always @(posedge clk) - begin : datarw_reg_proc - if (rst) - begin - datarw <= 1'b1 ; - end - else - begin - if (req_c) - begin - datarw <= ~write_c ; - end - end - end - - always @(posedge clk) - begin : idatareq_reg_proc - if (rst) - begin - idatareq <= 1'b0 ; - end - else - begin - if (eob & dataack & idatareq) - begin - idatareq <= 1'b0 ; - end - else if (req1 | req2) - begin - idatareq <= 1'b1 ; - end - end - end - - assign datareq = idatareq ; - - always @(idatareq or - dataack or - req1 or - req2 or - eob - ) - begin : idatareqc_comb_proc - if (eob & dataack & idatareq) - begin - idatareqc <= 1'b0 ; - end - else if (req1 | req2) - begin - idatareqc <= 1'b1 ; - end - else - begin - idatareqc <= idatareq ; - end - end - - assign datareqc = idatareqc ; - - assign dataeob = eob ; - - assign dataeobc = eobc ; - - assign datao1 = dataible_c ; - - assign datao2 = dataible_c ; - - assign datao = dataoble_c ; - - always @(dataack or - idatareq or - addr or - saddr_c or - req_c or - dsm) - begin : addr_proc - if (dataack & idatareq) - begin - case (DATAWIDTH) - 8 : - begin - addr_c <= addr + 1 ; - end - 16 : - begin - addr_c <= {addr[DATADEPTH - 1:1] + 1, 1'b0} ; - end - default : - begin - addr_c <= {addr[DATADEPTH - 1:2] + 1, 2'b00} ; - end - endcase - end - else if (req_c & dsm == DSM_IDLE) - begin - addr_c <= saddr_c ; - end - else - begin - addr_c <= addr ; - end - end - - always @(posedge clk) - begin : addr_reg_proc - if (rst) - begin - addr <= {DATADEPTH{1'b1}} ; - end - else - begin - addr <= addr_c ; - end - end - - assign dataaddr = addr ; - - assign idataaddr = addr ; - - assign ack1 = (dataack & dsm == DSM_CH1) ? 1'b1 : 1'b0 ; - - assign ack2 = (dataack & dsm == DSM_CH2) ? 1'b1 : 1'b0 ; - - always @(posedge clk) - begin : eob_reg_proc - if (rst) - begin - eob <= 1'b0 ; - end - else if (req_c | idatareq) - begin - if ((idatareq & - (msmbcnt == fzero | - msmbcnt == {fzero[FIFODEPTH_MAX-1:1], 1'b1} | - (msmbcnt == {fzero[FIFODEPTH_MAX-1:2], 2'b10} & dataack))) - | - (!idatareq & - (tcnt_c == fzero | - tcnt_c == {fzero[FIFODEPTH_MAX-1:1], 1'b1}))) - begin - eob <= 1'b1 ; - end - else - begin - eob <= 1'b0 ; - end - end - end - - always @(req_c or - idatareq or - msmbcnt or - dataack or - tcnt_c or - fzero or - eob) - begin : eob_comb_proc - if (req_c | idatareq) - begin - if ((idatareq & - (msmbcnt == fzero | - msmbcnt == {fzero[FIFODEPTH_MAX-1:1], 1'b1} | - (msmbcnt == {fzero[FIFODEPTH_MAX-1:2], 2'b10} & dataack))) - | - (!idatareq & - (tcnt_c == fzero | - tcnt_c == {fzero[FIFODEPTH_MAX-1:1], 1'b1}))) - begin - eobc <= 1'b1 ; - end - else - begin - eobc <= 1'b0 ; - end - end - else - begin - eobc <= eob; - end - end - - assign eob1 = eob ; - - assign eob2 = eob ; - - assign fzero = {FIFODEPTH_MAX{1'b0}} ; - - assign dzero = {(DATAWIDTH_MAX+1){1'b0}} ; - -endmodule diff --git a/resources/soc/rtl/MAC/ethernet_top.v b/resources/soc/rtl/MAC/ethernet_top.v deleted file mode 100644 index 6239f5f..0000000 --- a/resources/soc/rtl/MAC/ethernet_top.v +++ /dev/null @@ -1,368 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -module ethernet_top -( - hclk, - hrst_, - mawid_o , - mawaddr_o , - mawlen_o , - mawsize_o , - mawburst_o , - mawlock_o , - mawcache_o , - mawprot_o , - mawvalid_o , - mawready_i , - mwid_o , - mwdata_o , - mwstrb_o , - mwlast_o , - mwvalid_o , - mwready_i , - mbid_i , - mbresp_i , - mbvalid_i , - mbready_o , - marid_o , - maraddr_o , - marlen_o , - marsize_o , - marburst_o , - marlock_o , - marcache_o , - marprot_o , - marvalid_o , - marready_i , - mrid_i , - mrdata_i , - mrresp_i , - mrlast_i , - mrvalid_i , - mrready_o , - sawid_i , - sawaddr_i , - sawlen_i , - sawsize_i , - sawburst_i , - sawlock_i , - sawcache_i , - sawprot_i , - sawvalid_i , - sawready_o , - swid_i , - swdata_i , - swstrb_i , - swlast_i , - swvalid_i , - swready_o , - sbid_o , - sbresp_o , - sbvalid_o , - sbready_i , - sarid_i , - saraddr_i , - sarlen_i , - sarsize_i , - sarburst_i , - sarlock_i , - sarcache_i , - sarprot_i , - sarvalid_i , - sarready_o , - srid_o , - srdata_o , - srresp_o , - srlast_o , - srvalid_o , - srready_i , - - interrupt_0, - - mtxclk_0, - mtxen_0, - mtxd_0, - mtxerr_0, - mrxclk_0, - mrxdv_0, - mrxd_0, - mrxerr_0, - mcoll_0, - mcrs_0, - mdc_0, - md_i_0, - md_o_0, - md_oe_0 -); - -input hclk; -input hrst_; - - output [ 3:0] mawid_o ; - output [ 31:0] mawaddr_o ; - output [ 3:0] mawlen_o ; - output [ 2:0] mawsize_o ; - output [ 1:0] mawburst_o ; - output [ 1:0] mawlock_o ; - output [ 3:0] mawcache_o ; - output [ 2:0] mawprot_o ; - output mawvalid_o ; - input mawready_i ; - output [ 3:0] mwid_o ; - output [ 31:0] mwdata_o ; - output [ 3:0] mwstrb_o ; - output mwlast_o ; - output mwvalid_o ; - input mwready_i ; - input [ 3:0] mbid_i ; - input [ 1:0] mbresp_i ; - input mbvalid_i ; - output mbready_o ; - output [ 3:0] marid_o ; - output [ 31:0] maraddr_o ; - output [ 3:0] marlen_o ; - output [ 2:0] marsize_o ; - output [ 1:0] marburst_o ; - output [ 1:0] marlock_o ; - output [ 3:0] marcache_o ; - output [ 2:0] marprot_o ; - output marvalid_o ; - input marready_i ; - input [ 3:0] mrid_i ; - input [ 31:0] mrdata_i ; - input [ 1:0] mrresp_i ; - input mrlast_i ; - input mrvalid_i ; - output mrready_o ; - - input [ 3:0] sawid_i ; - input [ 31:0] sawaddr_i ; - input [ 3:0] sawlen_i ; - input [ 2:0] sawsize_i ; - input [ 1:0] sawburst_i ; - input [ 1:0] sawlock_i ; - input [ 3:0] sawcache_i ; - input [ 2:0] sawprot_i ; - input sawvalid_i ; - output sawready_o ; - input [ 3:0] swid_i ; - input [ 31:0] swdata_i ; - input [ 3:0] swstrb_i ; - input swlast_i ; - input swvalid_i ; - output swready_o ; - output [ 3:0] sbid_o ; - output [ 1:0] sbresp_o ; - output sbvalid_o ; - input sbready_i ; - input [ 3:0] sarid_i ; - input [ 31:0] saraddr_i ; - input [ 3:0] sarlen_i ; - input [ 2:0] sarsize_i ; - input [ 1:0] sarburst_i ; - input [ 1:0] sarlock_i ; - input [ 3:0] sarcache_i ; - input [ 2:0] sarprot_i ; - input sarvalid_i ; - output sarready_o ; - output [ 3:0] srid_o ; - output [ 31:0] srdata_o ; - output [ 1:0] srresp_o ; - output srlast_o ; - output srvalid_o ; - input srready_i ; - -input mtxclk_0; -output [3:0] mtxd_0; -output mtxen_0; -output mtxerr_0; - -input mrxclk_0; -input [3:0] mrxd_0; -input mrxdv_0; -input mrxerr_0; - -input mcoll_0; -input mcrs_0; - -input md_i_0; -output mdc_0; -output md_o_0; -output md_oe_0; - -output interrupt_0; - - -`define MAHBDATAWIDTH 32 -`define TFIFODEPTH 9 -`define RFIFODEPTH 9 -`define ADDRDEPTH 6 - -wire [`MAHBDATAWIDTH - 1:0] trdata_0; -wire twe_0; -wire [`TFIFODEPTH - 1:0] twaddr_0; -wire [`TFIFODEPTH - 1:0] traddr_0; -wire [`MAHBDATAWIDTH - 1:0] twdata_0; - -wire [`MAHBDATAWIDTH - 1:0] rrdata_0; -wire rwe_0; -wire [`RFIFODEPTH - 1:0] rwaddr_0; -wire [`RFIFODEPTH - 1:0] rraddr_0; -wire [`MAHBDATAWIDTH - 1:0] rwdata_0; - - -mac_top u_mac_top_0 -( - .hclk(hclk), - .hrst_(hrst_), - - .mawid_o (mawid_o ), - .mawaddr_o (mawaddr_o ), - .mawlen_o (mawlen_o ), - .mawsize_o (mawsize_o ), - .mawburst_o (mawburst_o ), - .mawlock_o (mawlock_o ), - .mawcache_o (mawcache_o ), - .mawprot_o (mawprot_o ), - .mawvalid_o (mawvalid_o ), - .mawready_i (mawready_i ), - .mwid_o (mwid_o ), - .mwdata_o (mwdata_o ), - .mwstrb_o (mwstrb_o ), - .mwlast_o (mwlast_o ), - .mwvalid_o (mwvalid_o ), - .mwready_i (mwready_i ), - .mbid_i (mbid_i ), - .mbresp_i (mbresp_i ), - .mbvalid_i (mbvalid_i ), - .mbready_o (mbready_o ), - .marid_o (marid_o ), - .maraddr_o (maraddr_o ), - .marlen_o (marlen_o ), - .marsize_o (marsize_o ), - .marburst_o (marburst_o ), - .marlock_o (marlock_o ), - .marcache_o (marcache_o ), - .marprot_o (marprot_o ), - .marvalid_o (marvalid_o ), - .marready_i (marready_i ), - .mrid_i (mrid_i ), - .mrdata_i (mrdata_i ), - .mrresp_i (mrresp_i ), - .mrlast_i (mrlast_i ), - .mrvalid_i (mrvalid_i ), - .mrready_o (mrready_o ), - .sawid_i (sawid_i ), - .sawaddr_i (sawaddr_i ), - .sawlen_i (sawlen_i ), - .sawsize_i (sawsize_i ), - .sawburst_i (sawburst_i ), - .sawlock_i (sawlock_i ), - .sawcache_i (sawcache_i ), - .sawprot_i (sawprot_i ), - .sawvalid_i (sawvalid_i ), - .sawready_o (sawready_o ), - .swid_i (swid_i ), - .swdata_i (swdata_i ), - .swstrb_i (swstrb_i ), - .swlast_i (swlast_i ), - .swvalid_i (swvalid_i ), - .swready_o (swready_o ), - .sbid_o (sbid_o ), - .sbresp_o (sbresp_o ), - .sbvalid_o (sbvalid_o ), - .sbready_i (sbready_i ), - .sarid_i (sarid_i ), - .saraddr_i (saraddr_i ), - .sarlen_i (sarlen_i ), - .sarsize_i (sarsize_i ), - .sarburst_i (sarburst_i ), - .sarlock_i (sarlock_i ), - .sarcache_i (sarcache_i ), - .sarprot_i (sarprot_i ), - .sarvalid_i (sarvalid_i ), - .sarready_o (sarready_o ), - .srid_o (srid_o ), - .srdata_o (srdata_o ), - .srresp_o (srresp_o ), - .srlast_o (srlast_o ), - .srvalid_o (srvalid_o ), - .srready_i (srready_i ), - - .interrupt(interrupt_0), - - .mtxclk(mtxclk_0), .mtxen(mtxen_0), .mtxd(mtxd_0), .mtxerr(mtxerr_0), - .mrxclk(mrxclk_0), .mrxdv(mrxdv_0), .mrxd(mrxd_0), .mrxerr(mrxerr_0), - .mcoll(mcoll_0), .mcrs(mcrs_0), - .mdc(mdc_0), .md_i(md_i_0), .md_o(md_o_0), .md_oe(md_oe_0), - - .trdata(trdata_0), - .twe(twe_0), - .twaddr(twaddr_0), - .traddr(traddr_0), - .twdata(twdata_0), - - .rrdata(rrdata_0), - .rwe(rwe_0), - .rwaddr(rwaddr_0), - .rraddr(rraddr_0), - .rwdata(rwdata_0) -); - -wire [31:0] douta_nc; -dpram_512x32 dpram_512x32_tx( - .clka (hclk ), - .ena (twe_0 ), - .wea (twe_0 ), - .addra (twaddr_0), - .dina (twdata_0), - .clkb (mtxclk_0), - .addrb (traddr_0), - .doutb (trdata_0) -); - -wire [31:0] doutb_nc; -dpram_512x32 dpram_512x32_rx( - .clka (mrxclk_0), - .ena (rwe_0 ), - .wea (rwe_0 ), - .addra (rwaddr_0), - .dina (rwdata_0), - .clkb (hclk ), - .addrb (rraddr_0), - .doutb (rrdata_0) -); - -endmodule - diff --git a/resources/soc/rtl/MAC/mac.v b/resources/soc/rtl/MAC/mac.v deleted file mode 100644 index 278bf28..0000000 --- a/resources/soc/rtl/MAC/mac.v +++ /dev/null @@ -1,862 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -module MAC ( - clkdma, - clkcsr, - rstcsr, - clkt, - clkr, - rsttco, - rstrco, - interrupt, - tps, - rps, - csrreq, - csrrw, - csrbe, - csrdatai, - csraddr, - csrack, - csrdatao, - dataack, - datareq, - datareqc, - datarw, - dataeob, - dataeobc, - datai, - dataaddr, - datao, - trdata, - twe, - twaddr, - traddr, - twdata, - rrdata, - rwe, - rwaddr, - rraddr, - rwdata, - frdata, - fwe, - fwaddr, - fraddr, - fwdata, - match, - matchval, - matchen, - matchdata, - sdi, - sclk, - scs, - sdo, - rxer, - rxdv, - col, - crs, - rxd, - txen, - txer, - txd, - mdc, - mdi, - mdo, - mden - ); - - parameter CSRWIDTH = 32; - parameter DATAWIDTH = 32; - parameter DATADEPTH = 32; - parameter TFIFODEPTH = 9; - parameter RFIFODEPTH = 9; - parameter TCDEPTH = 1; - parameter RCDEPTH = 2; - - `include "utility.v" - - input clkdma; - input clkcsr; - input rstcsr; - input clkt; - input clkr; - output rsttco; - wire rsttco; - output rstrco; - wire rstrco; - - output interrupt; - wire interrupt; - - output tps; - wire tps; - output rps; - wire rps; - - input csrreq; - input csrrw; - input [CSRWIDTH / 8 - 1:0] csrbe; - input [CSRWIDTH - 1:0] csrdatai; - input [7:0] csraddr; - output csrack; - wire csrack; - output [CSRWIDTH - 1:0] csrdatao; - wire [CSRWIDTH - 1:0] csrdatao; - - input dataack; - output datareq; - wire datareq; - output datareqc; - wire datareqc; - output datarw; - wire datarw; - output dataeob; - wire dataeob; - output dataeobc; - wire dataeobc; - input [DATAWIDTH - 1:0] datai; - output [DATADEPTH - 1:0] dataaddr; - wire [DATADEPTH - 1:0] dataaddr; - output [DATAWIDTH - 1:0] datao; - wire [DATAWIDTH - 1:0] datao; - - input [DATAWIDTH - 1:0] trdata; - output twe; - wire twe; - output [TFIFODEPTH - 1:0] twaddr; - wire [TFIFODEPTH - 1:0] twaddr; - output [TFIFODEPTH - 1:0] traddr; - wire [TFIFODEPTH - 1:0] traddr; - output [DATAWIDTH - 1:0] twdata; - wire [DATAWIDTH - 1:0] twdata; - - input [DATAWIDTH - 1:0] rrdata; - output rwe; - wire rwe; - output [RFIFODEPTH - 1:0] rwaddr; - wire [RFIFODEPTH - 1:0] rwaddr; - output [RFIFODEPTH - 1:0] rraddr; - wire [RFIFODEPTH - 1:0] rraddr; - output [DATAWIDTH - 1:0] rwdata; - wire [DATAWIDTH - 1:0] rwdata; - - input [15:0] frdata; - output fwe; - wire fwe; - output [ADDRDEPTH - 1:0] fwaddr; - wire [ADDRDEPTH - 1:0] fwaddr; - output [ADDRDEPTH - 1:0] fraddr; - wire [ADDRDEPTH - 1:0] fraddr; - output [15:0] fwdata; - wire [15:0] fwdata; - - input match; - input matchval; - output matchen; - wire matchen; - output [47:0] matchdata; - wire [47:0] matchdata; - - input sdi; - output sclk; - wire sclk; - output scs; - wire scs; - output sdo; - wire sdo; - - input rxer; - input rxdv; - input col; - input crs; - input [MIIWIDTH - 1:0] rxd; - output txen; - wire txen; - output txer; - wire txer; - output [MIIWIDTH - 1:0] txd; - wire [MIIWIDTH - 1:0] txd; - output mdc; - wire mdc; - input mdi; - output mdo; - wire mdo; - output mden; - wire mden; - - - wire rstsoft; - wire rsttc; - wire rstrc; - wire rstdmao; - wire rstcsro; - - wire [5:0] pbl; - wire ac; - wire dpd; - wire [4:0] dsl; - wire tpoll; - wire [DATADEPTH - 1:0] tdbad; - wire sf; - wire [2:0] tm; - wire fd; - wire ble; - wire dbo; - wire ra; - wire pm; - wire pr; - wire pb; - wire rif; - wire ho; - wire hp; - wire rpoll; - wire rpollack; - wire [DATADEPTH - 1:0] rdbad; - - wire insert_en; - - wire tdes; - wire tbuf; - wire tset; - wire tstat; - wire tu; - wire [1:0] ft; - wire rdes; - wire rstat; - wire ru; - wire rcomp; - wire rcompack; - wire tcomp; - wire tcompack; - - wire [1:0] dma_priority; - wire treq; - wire twrite; - wire [FIFODEPTH_MAX - 1:0] tcnt; - wire [DATADEPTH - 1:0] taddr; - wire [DATAWIDTH - 1:0] tdatai; - wire tack; - wire teob; - wire [DATAWIDTH - 1:0] tdatao; - wire rreq; - wire rwrite; - wire [FIFODEPTH_MAX - 1:0] rcnt; - wire [DATADEPTH - 1:0] raddr; - wire [DATAWIDTH - 1:0] rdatai; - wire rack; - wire reob; - wire [DATAWIDTH - 1:0] rdatao; - wire [DATADEPTH - 1:0] idataaddr; - - wire tfifonf; - wire tfifocnf; - wire tfifoval; - wire tfifowe; - wire tfifoeof; - wire [DATAWIDTH / 8 - 1:0] tfifobe; - wire [DATAWIDTH - 1:0] tfifodata; - wire [TFIFODEPTH - 1:0] tfifolev; - wire [TFIFODEPTH - 1:0] tradg; - - wire etiack; - wire etireq; - wire tcsne; - wire tcachere; - wire ic; - wire ici; - wire aci; - wire dpdi; - wire lo_o; - wire nc_o; - wire lc_o; - wire ec_o; - wire de_o; - wire ur_o; - wire [3:0] cc_o; - wire lo_i; - wire nc_i; - wire lc_i; - wire ec_i; - wire de_i; - wire ur_i; - wire [3:0] cc_i; - - wire tpollack; - wire tdbadc; - wire [DATADEPTH - 1:0] statado; - wire [DATADEPTH - 1:0] statadi; - - wire sofreq; - wire eofreq; - wire [DATAWIDTH / 8 - 1:0] be; - wire [TFIFODEPTH - 1:0] eofad; - wire [TFIFODEPTH - 1:0] twadg; - wire tireq; - wire tiack; - wire winp; - - wire coll; - wire carrier; - wire bkoff; - wire tpend; - wire tprog; - wire preamble; - - wire tcsreq; - wire tcsack; - - wire stopt; - wire stoptc; - wire stoptfifo; - wire stoptlsm; - - wire [RFIFODEPTH - 1:0] rradg; - wire [RFIFODEPTH - 1:0] rwadg; - wire rfifore; - wire [DATAWIDTH - 1:0] rfifodata; - wire rcachere; - wire rcachene; - wire rcachenf; - wire [DATAWIDTH - 1:0] irwdata; - wire irwe; - - wire riack; - wire ren; - wire rireq; - wire ff; - wire rf; - wire mf; - wire db; - wire re; - wire ce; - wire tl; - wire ftp; - wire ov; - wire cs; - wire [13:0] length; - wire rprog; - wire rcpoll; - - - wire ff_o; - wire rf_o; - wire mf_o; - wire tl_o; - wire re_o; - wire db_o; - wire ce_o; - wire ov_o; - wire cs_o; - wire [13:0] fl_o; - - wire rdbadc; - wire erireq; - wire eriack; - wire rbuf; - - wire foclack; - wire mfclack; - wire oco; - wire mfo; - wire [10:0] focg; - wire [15:0] mfcg; - wire focl; - wire mfcl; - - wire stopr; - wire stoprc; - wire stoprfifo; - wire stoprlsm; - - wire rcsack; - wire rcsreq; - - DMA #(DATAWIDTH, DATADEPTH) U_DMA( - .clk (clkdma), - .rst (rstdmao), - .dma_priority (dma_priority), - .ble (ble), - .dbo (dbo), - .rdes (rdes), - .rbuf (rbuf), - .rstat (rstat), - .tdes (tdes), - .tbuf (tbuf), - .tstat (tstat), - .dataack (dataack), - .datai (datai), - .datareq (datareq), - .datareqc (datareqc), - .datarw (datarw), - .dataeob (dataeob), - .dataeobc (dataeobc), - .datao (datao), - .dataaddr (dataaddr), - .idataaddr (idataaddr), - .req1 (treq), - .write1 (twrite), - .tcnt1 (tcnt), - .addr1 (taddr), - .datai1 (tdatao), - .ack1 (tack), - .eob1 (teob), - .datao1 (tdatai), - .req2 (rreq), - .write2 (rwrite), - .tcnt2 (rcnt), - .addr2 (raddr), - .datai2 (rdatao), - .ack2 (rack), - .eob2 (reob), - .datao2 (rdatai) - ); - - TLSM #(DATAWIDTH, DATADEPTH, TFIFODEPTH) U_TLSM( - .clk (clkdma), - .rst (rstdmao), - .fifonf (tfifonf), - .fifocnf (tfifocnf), - .fifoval (tfifoval), - .fifowe (tfifowe), - .fifoeof (tfifoeof), - .fifobe (tfifobe), - .fifodata (tfifodata), - .fifolev (tfifolev), - .ic (ici), - .ac (aci), - .dpd (dpdi), - .statado (statadi), - .csne (tcsne), - .lo (lo_i), - .nc (nc_i), - .lc (lc_i), - .ec (ec_i), - .de (de_i), - .ur (ur_i), - .cc (cc_i), - .cachere (tcachere), - .statadi (statado), - .dmaack (tack), - .dmaeob (teob), - .dmadatai (tdatai), - .dmaaddr (idataaddr), - .dmareq (treq), - .dmawr (twrite), - .dmacnt (tcnt), - .dmaaddro (taddr), - .dmadatao (tdatao), - .fwe (fwe), - .fdata (fwdata), - .faddr (fwaddr), - .dsl (dsl), - .pbl (pbl), - .poll (tpoll), - .dbadc (tdbadc), - .dbad (tdbad), - .pollack (tpollack), - .tcompack (tcompack), - .tcomp (tcomp), - .des (tdes), - .fbuf (tbuf), - .stat (tstat), - .setp (tset), - .tu (tu), - .ft (ft), - .stopi (stopt), - .stopo (stoptlsm) - ); - - TFIFO #(DATAWIDTH, DATADEPTH, TFIFODEPTH, TCDEPTH) U_TFIFO( - .clk (clkdma), - .rst (rstdmao), - .ramwe (twe), - .ramaddr (twaddr), - .ramdata (twdata), - .fifowe (tfifowe), - .fifoeof (tfifoeof), - .fifobe (tfifobe), - .fifodata (tfifodata), - .fifonf (tfifonf), - .fifocnf (tfifocnf), - .fifoval (tfifoval), - .flev (tfifolev), - .ici (ici), - .dpdi (dpdi), - .aci (aci), - .statadi (statadi), - .cachere (tcachere), - .deo (de_i), - .lco (lc_i), - .loo (lo_i), - .nco (nc_i), - .eco (ec_i), - .ico (ic), - .uro (ur_i), - .csne (tcsne), - .cco (cc_i), - .statado (statado), - .sofreq (sofreq), - .eofreq (eofreq), - .dpdo (dpd), - .aco (ac), - .beo (be), - .eofad (eofad), - .wadg (twadg), - .tireq (tireq), - .winp (winp), - .dei (de_o), - .lci (lc_o), - .loi (lo_o), - .nci (nc_o), - .eci (ec_o), - .uri (ur_o), - .cci (cc_o), - .radg (tradg), - .tiack (tiack), - .sf (sf), - .fdp (fd), - .tm (tm), - .pbl (pbl), - .etiack (etiack), - .etireq (etireq), - .stopi (stopt), - .stopo (stoptfifo) - ); - - TC #(TFIFODEPTH, DATAWIDTH) U_TC( - .clk (clkt), - .rst (rsttc), - .txen (txen), - .txer (txer), - .txd (txd), - .ramdata (trdata), - .ramaddr (traddr), - .wadg (twadg), - .radg (tradg), - .dpd (dpd), - .ac (ac), - .sofreq (sofreq), - .eofreq (eofreq), - .tiack (tiack), - .lastbe (be), - .eofadg (eofad), - .tireq (tireq), - .ur (ur_o), - .de (de_o), - .coll (coll), - .carrier (carrier), - .bkoff (bkoff), - .tpend (tpend), - .tprog (tprog), - .preamble (preamble), - .stopi (stopt), - .stopo (stoptc), - .tcsack (tcsack), - .tcsreq (tcsreq) - ); - - BD U_BD( - .clk (clkt), - .rst (rsttc), - .col (col), - .crs (crs), - .fdp (fd), - .tprog (tprog), - .preamble (preamble), - .tpend (tpend), - .winp (winp), - .tiack (tiack), - .coll (coll), - .carrier (carrier), - .bkoff (bkoff), - .lc (lc_o), - .lo (lo_o), - .nc (nc_o), - .ec (ec_o), - .cc (cc_o) - ); - - - RC #(RFIFODEPTH, DATAWIDTH) U_RC( - .clk (clkr), - .rst (rstrc), - .col (col), - .rxdv (rxdv), - .rxer (rxer), - .rxd (rxd), - .ramwe (irwe), - .ramaddr (rwaddr), - .ramdata (irwdata), - .fdata (frdata), - .faddr (fraddr), - .cachenf (rcachenf), - .radg (rradg), - .wadg (rwadg), - .rprog (rprog), - .rcpoll (rcpoll), - .riack (riack), - .ren (ren), - .ra (ra), - .pm (pm), - .pr (pr), - .pb (pb), - .rif (rif), - .ho (ho), - .hp (hp), - .rireq (rireq), - .ff (ff), - .rf (rf), - .mf (mf), - .db (db), - .re (re), - .ce (ce), - .tl (tl), - .ftp (ftp), - .ov (ov), - .cs (cs), - .length (length), - .match (match), - .matchval (matchval), - .matchen (matchen), - .matchdata (matchdata), - .focl (focl), - .foclack (foclack), - .oco (oco), - .focg (focg), - .mfcl (mfcl), - .mfclack (mfclack), - .mfo (mfo), - .mfcg (mfcg), - .stopi (stopr), - .stopo (stoprc), - .rcsack (rcsack), - .rcsreq (rcsreq), - .insert_en_i (insert_en) - ); - - RFIFO #(DATAWIDTH, DATADEPTH, RFIFODEPTH, RCDEPTH) U_RFIFO( - .clk (clkdma), - .rst (rstdmao), - .ramdata (rrdata), - .ramaddr (rraddr), - .fifore (rfifore), - .ffo (ff_o), - .rfo (rf_o), - .mfo (mf_o), - .tlo (tl_o), - .reo (re_o), - .dbo (db_o), - .ceo (ce_o), - .ovo (ov_o), - .cso (cs_o), - .flo (fl_o), - .fifodata (rfifodata), - .cachere (rcachere), - .cachene (rcachene), - .cachenf (rcachenf), - .radg (rradg), - .rireq (rireq), - .ffi (ff), - .rfi (rf), - .mfi (mf), - .tli (tl), - .rei (re), - .dbi (db), - .cei (ce), - .ovi (ov), - .csi (cs), - .fli (length), - .wadg (rwadg), - .riack (riack) - ); - - RLSM #(DATAWIDTH, DATADEPTH, RFIFODEPTH) U_RLSM( - .clk (clkdma), - .rst (rstdmao), - .fifodata (rfifodata), - .fifore (rfifore), - .cachere (rcachere), - .dmaack (rack), - .dmaeob (reob), - .dmadatai (rdatai), - .dmaaddr (idataaddr), - .dmareq (rreq), - .dmawr (rwrite), - .dmacnt (rcnt), - .dmaaddro (raddr), - .dmadatao (rdatao), - .rprog (rprog), - .rcpoll (rcpoll), - .fifocne (rcachene), - .ff (ff_o), - .rf (rf_o), - .mf (mf_o), - .db (db_o), - .re (re_o), - .ce (ce_o), - .tl (tl_o), - .ftp (ftp), - .ov (ov_o), - .cs (cs_o), - .length (fl_o), - .pbl (pbl), - .dsl (dsl), - .rpoll (rpoll), - .rdbadc (rdbadc), - .rdbad (rdbad), - .rpollack (rpollack), - .bufack (eriack), - .rcompack (rcompack), - .des (rdes), - .fbuf (rbuf), - .stat (rstat), - .ru (ru), - .rcomp (rcomp), - .bufcomp (erireq), - .stopi (stopr), - .stopo (stoprlsm), - .insert_en_i (insert_en) - ); - - CSR #(CSRWIDTH, DATAWIDTH, DATADEPTH, RFIFODEPTH, RCDEPTH) U_CSR( - .clk (clkcsr), - .rst (rstcsro), - .interrupt (interrupt), - .rstsofto (rstsoft), - .csrreq (csrreq), - .csrrw (csrrw), - .csrbe (csrbe), - .csraddr (csraddr), - .csrdatai (csrdatai), - .csrack (csrack), - .csrdatao (csrdatao), - .tprog (tprog), - .tireq (tcomp), - .unf (ur_i), - .tiack (tcompack), - .tcsreq (tcsreq), - .tcsack (tcsack), - .fd (fd), - .ic (ic), - .etireq (etireq), - .etiack (etiack), - .tm (tm), - .sf (sf), - .tset (tset), - .tdes (tdes), - .tbuf (tbuf), - .tstat (tstat), - .tu (tu), - .tpollack (tpollack), - .ft (ft), - .tpoll (tpoll), - .tdbadc (tdbadc), - .tdbad (tdbad), - .rireq (rcomp), - .rcsreq (rcsreq), - .rprog (rprog), - .riack (rcompack), - .rcsack (rcsack), - .ren (ren), - .ra (ra), - .pm (pm), - .pr (pr), - .pb (pb), - .rif (rif), - .ho (ho), - .hp (hp), - .foclack (foclack), - .mfclack (mfclack), - .oco (oco), - .mfo (mfo), - .focg (focg), - .mfcg (mfcg), - .focl (focl), - .mfcl (mfcl), - .erireq (erireq), - .ru (ru), - .rpollack (rpollack), - .rdes (rdes), - .rbuf (rbuf), - .rstat (rstat), - .eriack (eriack), - .rpoll (rpoll), - .rdbadc (rdbadc), - .rdbad (rdbad), - .ble (ble), - .dbo (dbo), - .dma_priority (dma_priority), - .pbl (pbl), - .dsl (dsl), - .stoptc (stoptc), - .stoptlsm (stoptlsm), - .stoptfifo (stoptfifo), - .stopt (stopt), - .tps (tps), - .stoprc (stoprc), - .stoprlsm (stoprlsm), - .stopr (stopr), - .rps (rps), - .sdi (sdi), - .sclk (sclk), - .scs (scs), - .sdo (sdo), - .mdi (mdi), - .mdc (mdc), - .mdo (mdo), - .mden (mden), - .insert_en_o (insert_en) - ); - - RSTC U_RSTC ( - .clkdma(clkdma), - .clkcsr(clkcsr), - .clkt(clkt), - .clkr(clkr), - .rstcsr(rstcsr), - .rstsoft(rstsoft), - .rsttc(rsttc), - .rstrc(rstrc), - .rstdmao(rstdmao), - .rstcsro(rstcsro) - ); - - assign rwe = irwe ; - - assign rwdata = irwdata ; - - assign rsttco = rsttc ; - - assign rstrco = rstrc ; - -endmodule diff --git a/resources/soc/rtl/MAC/mac2axi.v b/resources/soc/rtl/MAC/mac2axi.v deleted file mode 100644 index 9754451..0000000 --- a/resources/soc/rtl/MAC/mac2axi.v +++ /dev/null @@ -1,355 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -module MAC2AXI ( - mhclk, - mhresetn, - shclk, - shresetn, - - mawid_o , - mawaddr_o , - mawlen_o , - mawsize_o , - mawburst_o , - mawlock_o , - mawcache_o , - mawprot_o , - mawvalid_o , - mawready_i , - mwid_o , - mwdata_o , - mwstrb_o , - mwlast_o , - mwvalid_o , - mwready_i , - mbid_i , - mbresp_i , - mbvalid_i , - mbready_o , - marid_o , - maraddr_o , - marlen_o , - marsize_o , - marburst_o , - marlock_o , - marcache_o , - marprot_o , - marvalid_o , - marready_i , - mrid_i , - mrdata_i , - mrresp_i , - mrlast_i , - mrvalid_i , - mrready_o , - - sawid_i , - sawaddr_i , - sawlen_i , - sawsize_i , - sawburst_i , - sawlock_i , - sawcache_i , - sawprot_i , - sawvalid_i , - sawready_o , - swid_i , - swdata_i , - swstrb_i , - swlast_i , - swvalid_i , - swready_o , - sbid_o , - sbresp_o , - sbvalid_o , - sbready_i , - sarid_i , - saraddr_i , - sarlen_i , - sarsize_i , - sarburst_i , - sarlock_i , - sarcache_i , - sarprot_i , - sarvalid_i , - sarready_o , - srid_o , - srdata_o , - srresp_o , - srlast_o , - srvalid_o , - srready_i , - - datareq, - datareqc, - datarw, - dataeob, - dataeobc, - dataaddr, - datao, - dataack, - datai, - rstcsr, - csrack, - csrdatao, - csrreq, - csrrw, - csrbe, - csrdatai, - csraddr - ); - - parameter MAXIDATAWIDTH = 32; - parameter MAXIADDRESSWIDTH = 32; - - parameter SAXIDATAWIDTH = 32; - parameter SAXIADDRESSWIDTH = 32; - - parameter MACDATAWIDTH = 32; - parameter MACADDRESSWIDTH = 32; - - parameter CSRDATAWIDTH = 32; - parameter CSRADDRESSWIDTH = 8; - - - input mhclk; - input mhresetn; - output [ 3:0] mawid_o ; - output [ 31:0] mawaddr_o ; - output [ 3:0] mawlen_o ; - output [ 2:0] mawsize_o ; - output [ 1:0] mawburst_o ; - output [ 1:0] mawlock_o ; - output [ 3:0] mawcache_o ; - output [ 2:0] mawprot_o ; - output mawvalid_o ; - input mawready_i ; - output [ 3:0] mwid_o ; - output [ 31:0] mwdata_o ; - output [ 3:0] mwstrb_o ; - output mwlast_o ; - output mwvalid_o ; - input mwready_i ; - input [ 3:0] mbid_i ; - input [ 1:0] mbresp_i ; - input mbvalid_i ; - output mbready_o ; - output [ 3:0] marid_o ; - output [ 31:0] maraddr_o ; - output [ 3:0] marlen_o ; - output [ 2:0] marsize_o ; - output [ 1:0] marburst_o ; - output [ 1:0] marlock_o ; - output [ 3:0] marcache_o ; - output [ 2:0] marprot_o ; - output marvalid_o ; - input marready_i ; - input [ 3:0] mrid_i ; - input [ 31:0] mrdata_i ; - input [ 1:0] mrresp_i ; - input mrlast_i ; - input mrvalid_i ; - output mrready_o ; - - input shclk; - input shresetn; - - input [ 3:0] sawid_i ; - input [ 31:0] sawaddr_i ; - input [ 3:0] sawlen_i ; - input [ 2:0] sawsize_i ; - input [ 1:0] sawburst_i ; - input [ 1:0] sawlock_i ; - input [ 3:0] sawcache_i ; - input [ 2:0] sawprot_i ; - input sawvalid_i ; - output sawready_o ; - input [ 3:0] swid_i ; - input [ 31:0] swdata_i ; - input [ 3:0] swstrb_i ; - input swlast_i ; - input swvalid_i ; - output swready_o ; - output [ 3:0] sbid_o ; - output [ 1:0] sbresp_o ; - output sbvalid_o ; - input sbready_i ; - input [ 3:0] sarid_i ; - input [ 31:0] saraddr_i ; - input [ 3:0] sarlen_i ; - input [ 2:0] sarsize_i ; - input [ 1:0] sarburst_i ; - input [ 1:0] sarlock_i ; - input [ 3:0] sarcache_i ; - input [ 2:0] sarprot_i ; - input sarvalid_i ; - output sarready_o ; - output [ 3:0] srid_o ; - output [ 31:0] srdata_o ; - output [ 1:0] srresp_o ; - output srlast_o ; - output srvalid_o ; - input srready_i ; - input datareq; - input datareqc; - input datarw; - input dataeob; - input dataeobc; - input [MACADDRESSWIDTH - 1:0] dataaddr; - input [MACDATAWIDTH - 1:0] datao; - output dataack; - wire dataack; - output [MACDATAWIDTH - 1:0] datai; - wire [MACDATAWIDTH - 1:0] datai; - - - output rstcsr; - wire rstcsr; - input csrack; - input [CSRDATAWIDTH - 1:0] csrdatao; - output csrreq; - wire csrreq; - output csrrw; - wire csrrw; - output [CSRDATAWIDTH / 8 - 1:0] csrbe; - wire [CSRDATAWIDTH / 8 - 1:0] csrbe; - output [CSRDATAWIDTH - 1:0] csrdatai; - wire [CSRDATAWIDTH - 1:0] csrdatai; - output [CSRADDRESSWIDTH - 1:0] csraddr; - wire [CSRADDRESSWIDTH - 1:0] csraddr; - - - MACDATA2AXI - #(MAXIDATAWIDTH, MAXIADDRESSWIDTH, MACDATAWIDTH, MACADDRESSWIDTH) - U_MACDATA2AXI ( - .maclk (mhclk ), - .maresetn (mhresetn ), - .awid_o (mawid_o ), - .awaddr_o (mawaddr_o ), - .awlen_o (mawlen_o ), - .awsize_o (mawsize_o ), - .awburst_o (mawburst_o ), - .awlock_o (mawlock_o ), - .awcache_o (mawcache_o ), - .awprot_o (mawprot_o ), - .awvalid_o (mawvalid_o ), - .awready_i (mawready_i ), - .wid_o (mwid_o ), - .wdata_o (mwdata_o ), - .wstrb_o (mwstrb_o ), - .wlast_o (mwlast_o ), - .wvalid_o (mwvalid_o ), - .wready_i (mwready_i ), - .bid_i (mbid_i ), - .bresp_i (mbresp_i ), - .bvalid_i (mbvalid_i ), - .bready_o (mbready_o ), - .arid_o (marid_o ), - .araddr_o (maraddr_o ), - .arlen_o (marlen_o ), - .arsize_o (marsize_o ), - .arburst_o (marburst_o ), - .arlock_o (marlock_o ), - .arcache_o (marcache_o ), - .arprot_o (marprot_o ), - .arvalid_o (marvalid_o ), - .arready_i (marready_i ), - .rid_i (mrid_i ), - .rdata_i (mrdata_i ), - .rresp_i (mrresp_i ), - .rlast_i (mrlast_i ), - .rvalid_i (mrvalid_i ), - .rready_o (mrready_o ), - .datareq (datareq ), - .datareqc (datareqc ), - .datarw (datarw ), - .dataeob (dataeob ), - .dataeobc (dataeobc ), - .dataaddr (dataaddr ), - .datao (datao ), - .dataack (dataack ), - .datai (datai ) - ); - MACCSR2AXI - #(SAXIDATAWIDTH, SAXIADDRESSWIDTH, CSRDATAWIDTH, CSRADDRESSWIDTH) - U_MACCSR2AXI( - .saclk (shclk ), - .saresetn (shresetn ), - .awid_i (sawid_i ), - .awaddr_i (sawaddr_i ), - .awlen_i (sawlen_i ), - .awsize_i (sawsize_i ), - .awburst_i (sawburst_i), - .awlock_i (sawlock_i ), - .awcache_i (sawcache_i), - .awprot_i (sawprot_i ), - .awvalid_i (sawvalid_i), - .awready_o (sawready_o), - .wid_i (swid_i ), - .wdata_i (swdata_i ), - .wstrb_i (swstrb_i ), - .wlast_i (swlast_i ), - .wvalid_i (swvalid_i ), - .wready_o (swready_o ), - .bid_o (sbid_o ), - .bresp_o (sbresp_o ), - .bvalid_o (sbvalid_o ), - .bready_i (sbready_i ), - .arid_i (sarid_i ), - .araddr_i (saraddr_i ), - .arlen_i (sarlen_i ), - .arsize_i (sarsize_i ), - .arburst_i (sarburst_i), - .arlock_i (sarlock_i ), - .arcache_i (sarcache_i), - .arprot_i (sarprot_i ), - .arvalid_i (sarvalid_i), - .arready_o (sarready_o), - .rid_o (srid_o ), - .rdata_o (srdata_o ), - .rresp_o (srresp_o ), - .rlast_o (srlast_o ), - .rvalid_o (srvalid_o ), - .rready_i (srready_i ), - .rstcsr (rstcsr ) , - .csrack (csrack ) , - .csrdatao (csrdatao ) , - .csrreq (csrreq ) , - .csrrw (csrrw ) , - .csrbe (csrbe ) , - .csrdatai (csrdatai ) , - .csraddr (csraddr ) - ); - -endmodule diff --git a/resources/soc/rtl/MAC/mac_axi.v b/resources/soc/rtl/MAC/mac_axi.v deleted file mode 100644 index 3023ec8..0000000 --- a/resources/soc/rtl/MAC/mac_axi.v +++ /dev/null @@ -1,522 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -module MAC_AXI ( - clkt, - clkr, - rsttco, - rstrco, - interrupt, - tps, - rps, - mhclk, - mhresetn, - mawid_o , - mawaddr_o , - mawlen_o , - mawsize_o , - mawburst_o , - mawlock_o , - mawcache_o , - mawprot_o , - mawvalid_o , - mawready_i , - mwid_o , - mwdata_o , - mwstrb_o , - mwlast_o , - mwvalid_o , - mwready_i , - mbid_i , - mbresp_i , - mbvalid_i , - mbready_o , - marid_o , - maraddr_o , - marlen_o , - marsize_o , - marburst_o , - marlock_o , - marcache_o , - marprot_o , - marvalid_o , - marready_i , - mrid_i , - mrdata_i , - mrresp_i , - mrlast_i , - mrvalid_i , - mrready_o , - shclk, - shresetn, - sawid_i , - sawaddr_i , - sawlen_i , - sawsize_i , - sawburst_i , - sawlock_i , - sawcache_i , - sawprot_i , - sawvalid_i , - sawready_o , - swid_i , - swdata_i , - swstrb_i , - swlast_i , - swvalid_i , - swready_o , - sbid_o , - sbresp_o , - sbvalid_o , - sbready_i , - sarid_i , - saraddr_i , - sarlen_i , - sarsize_i , - sarburst_i , - sarlock_i , - sarcache_i , - sarprot_i , - sarvalid_i , - sarready_o , - srid_o , - srdata_o , - srresp_o , - srlast_o , - srvalid_o , - srready_i , - trdata, - twe, - twaddr, - traddr, - twdata, - rrdata, - rwe, - rwaddr, - rraddr, - rwdata, - frdata, - fwe, - fwaddr, - fraddr, - fwdata, - match, - matchval, - matchen, - matchdata, - sdi, - sclk, - scs, - sdo, - rxer, - rxdv, - col, - crs, - rxd, - txen, - txer, - txd, - mdc, - mdi, - mdo, - mden - ); - - parameter MAXIADDRESSWIDTH = 32; - parameter SAXIADDRESSWIDTH = 32; - parameter TFIFODEPTH = 9; - parameter RFIFODEPTH = 9; - parameter TCDEPTH = 1; - parameter RCDEPTH = 2; - parameter MAXIDATAWIDTH = 32; - parameter SAXIDATAWIDTH = 32; - `include "utility.v" - - - input clkt; - input clkr; - output rsttco; - wire rsttco; - output rstrco; - wire rstrco; - - - output interrupt; - wire interrupt; - - output tps; - wire tps; - output rps; - wire rps; - - input mhclk; - input mhresetn; - output [ 3:0] mawid_o ; - output [ 31:0] mawaddr_o ; - output [ 3:0] mawlen_o ; - output [ 2:0] mawsize_o ; - output [ 1:0] mawburst_o ; - output [ 1:0] mawlock_o ; - output [ 3:0] mawcache_o ; - output [ 2:0] mawprot_o ; - output mawvalid_o ; - input mawready_i ; - output [ 3:0] mwid_o ; - output [ 31:0] mwdata_o ; - output [ 3:0] mwstrb_o ; - output mwlast_o ; - output mwvalid_o ; - input mwready_i ; - input [ 3:0] mbid_i ; - input [ 1:0] mbresp_i ; - input mbvalid_i ; - output mbready_o ; - output [ 3:0] marid_o ; - output [ 31:0] maraddr_o ; - output [ 3:0] marlen_o ; - output [ 2:0] marsize_o ; - output [ 1:0] marburst_o ; - output [ 1:0] marlock_o ; - output [ 3:0] marcache_o ; - output [ 2:0] marprot_o ; - output marvalid_o ; - input marready_i ; - input [ 3:0] mrid_i ; - input [ 31:0] mrdata_i ; - input [ 1:0] mrresp_i ; - input mrlast_i ; - input mrvalid_i ; - output mrready_o ; - input shclk; - input shresetn; - - input [ 3:0] sawid_i ; - input [ 31:0] sawaddr_i ; - input [ 3:0] sawlen_i ; - input [ 2:0] sawsize_i ; - input [ 1:0] sawburst_i ; - input [ 1:0] sawlock_i ; - input [ 3:0] sawcache_i ; - input [ 2:0] sawprot_i ; - input sawvalid_i ; - output sawready_o ; - input [ 3:0] swid_i ; - input [ 31:0] swdata_i ; - input [ 3:0] swstrb_i ; - input swlast_i ; - input swvalid_i ; - output swready_o ; - output [ 3:0] sbid_o ; - output [ 1:0] sbresp_o ; - output sbvalid_o ; - input sbready_i ; - input [ 3:0] sarid_i ; - input [ 31:0] saraddr_i ; - input [ 3:0] sarlen_i ; - input [ 2:0] sarsize_i ; - input [ 1:0] sarburst_i ; - input [ 1:0] sarlock_i ; - input [ 3:0] sarcache_i ; - input [ 2:0] sarprot_i ; - input sarvalid_i ; - output sarready_o ; - output [ 3:0] srid_o ; - output [ 31:0] srdata_o ; - output [ 1:0] srresp_o ; - output srlast_o ; - output srvalid_o ; - input srready_i ; - input [MAXIDATAWIDTH - 1:0] trdata; - output twe; - wire twe; - output [TFIFODEPTH - 1:0] twaddr; - wire [TFIFODEPTH - 1:0] twaddr; - output [TFIFODEPTH - 1:0] traddr; - wire [TFIFODEPTH - 1:0] traddr; - output [MAXIDATAWIDTH - 1:0] twdata; - wire [MAXIDATAWIDTH - 1:0] twdata; - - - input [MAXIDATAWIDTH - 1:0] rrdata; - output rwe; - wire rwe; - output [RFIFODEPTH - 1:0] rwaddr; - wire [RFIFODEPTH - 1:0] rwaddr; - output [RFIFODEPTH - 1:0] rraddr; - wire [RFIFODEPTH - 1:0] rraddr; - output [MAXIDATAWIDTH - 1:0] rwdata; - wire [MAXIDATAWIDTH - 1:0] rwdata; - - input [15:0] frdata; - output fwe; - wire fwe; - output [ADDRDEPTH - 1:0] fwaddr; - wire [ADDRDEPTH - 1:0] fwaddr; - output [ADDRDEPTH - 1:0] fraddr; - wire [ADDRDEPTH - 1:0] fraddr; - output [15:0] fwdata; - wire [15:0] fwdata; - - input match; - input matchval; - output matchen; - wire matchen; - output [47:0] matchdata; - wire [47:0] matchdata; - - input sdi; - output sclk; - wire sclk; - output scs; - wire scs; - output sdo; - wire sdo; - - input rxer; - input rxdv; - input col; - input crs; - input [MIIWIDTH - 1:0] rxd; - output txen; - wire txen; - output txer; - wire txer; - output [MIIWIDTH - 1:0] txd; - wire [MIIWIDTH - 1:0] txd; - output mdc; - wire mdc; - input mdi; - output mdo; - wire mdo; - output mden; - wire mden; - - - wire datareq; - wire datareqc; - wire datarw; - wire dataeob; - wire dataeobc; - wire [(MAXIADDRESSWIDTH - 1):0] dataaddr; - wire [(MAXIDATAWIDTH - 1):0] datao; - wire dataack; - wire [(MAXIDATAWIDTH - 1):0] datai; - - wire rstcsr; - wire csrack; - wire [SAXIDATAWIDTH - 1:0] csrdatao; - wire csrreq; - wire csrrw; - wire [SAXIDATAWIDTH / 8 - 1:0] csrbe; - wire [SAXIDATAWIDTH - 1:0] csrdatai; - wire [7:0] csraddr; - - MAC - #(SAXIDATAWIDTH, - MAXIDATAWIDTH, - MAXIADDRESSWIDTH, - TFIFODEPTH, - RFIFODEPTH, - TCDEPTH, - RCDEPTH) - U_MAC ( - .clkdma (mhclk), - .clkcsr (shclk), - .clkt (clkt), - .clkr (clkr), - .rstcsr (rstcsr), - .rsttco (rsttco), - .rstrco (rstrco), - .interrupt (interrupt), - .rps (rps), - .tps (tps), - .csrreq (csrreq), - .csrrw (csrrw), - .csrbe (csrbe), - .csrdatai (csrdatai), - .csrack (csrack), - .csraddr (csraddr), - .csrdatao (csrdatao), - .dataack (dataack), - .datareq (datareq), - .datareqc (datareqc), - .datarw (datarw), - .dataeob (dataeob), - .dataeobc (dataeobc), - .datai (datai), - .dataaddr (dataaddr), - .datao (datao), - .trdata (trdata), - .twe (twe), - .twaddr (twaddr), - .traddr (traddr), - .twdata (twdata), - .rrdata (rrdata), - .rwe (rwe), - .rwaddr (rwaddr), - .rraddr (rraddr), - .rwdata (rwdata), - .frdata (frdata), - .fwe (fwe), - .fraddr (fraddr), - .fwaddr (fwaddr), - .fwdata (fwdata), - .match (match), - .matchval (matchval), - .matchen (matchen), - .matchdata (matchdata), - .sdi (sdi), - .sclk (sclk), - .scs (scs), - .sdo (sdo), - .rxer (rxer), - .rxdv (rxdv), - .col (col), - .crs (crs), - .rxd (rxd), - .txen (txen), - .txer (txer), - .txd (txd), - .mdi (mdi), - .mdo (mdo), - .mden (mden), - .mdc (mdc) - ); - - MAC2AXI - #(MAXIDATAWIDTH, - MAXIADDRESSWIDTH, - SAXIDATAWIDTH, - SAXIADDRESSWIDTH, - MAXIDATAWIDTH, - MAXIADDRESSWIDTH, - SAXIDATAWIDTH, - 8) - U_MAC2AXI ( - - .mhclk (mhclk ), - .mhresetn (mhresetn ), - .shclk (shclk ), - .shresetn (shresetn ), - .mawid_o (mawid_o ), - .mawaddr_o (mawaddr_o ), - .mawlen_o (mawlen_o ), - .mawsize_o (mawsize_o ), - .mawburst_o (mawburst_o ), - .mawlock_o (mawlock_o ), - .mawcache_o (mawcache_o ), - .mawprot_o (mawprot_o ), - .mawvalid_o (mawvalid_o ), - .mawready_i (mawready_i ), - .mwid_o (mwid_o ), - .mwdata_o (mwdata_o ), - .mwstrb_o (mwstrb_o ), - .mwlast_o (mwlast_o ), - .mwvalid_o (mwvalid_o ), - .mwready_i (mwready_i ), - .mbid_i (mbid_i ), - .mbresp_i (mbresp_i ), - .mbvalid_i (mbvalid_i ), - .mbready_o (mbready_o ), - .marid_o (marid_o ), - .maraddr_o (maraddr_o ), - .marlen_o (marlen_o ), - .marsize_o (marsize_o ), - .marburst_o (marburst_o ), - .marlock_o (marlock_o ), - .marcache_o (marcache_o ), - .marprot_o (marprot_o ), - .marvalid_o (marvalid_o ), - .marready_i (marready_i ), - .mrid_i (mrid_i ), - .mrdata_i (mrdata_i ), - .mrresp_i (mrresp_i ), - .mrlast_i (mrlast_i ), - .mrvalid_i (mrvalid_i ), - .mrready_o (mrready_o ), - .sawid_i (sawid_i ), - .sawaddr_i (sawaddr_i ), - .sawlen_i (sawlen_i ), - .sawsize_i (sawsize_i ), - .sawburst_i (sawburst_i ), - .sawlock_i (sawlock_i ), - .sawcache_i (sawcache_i ), - .sawprot_i (sawprot_i ), - .sawvalid_i (sawvalid_i ), - .sawready_o (sawready_o ), - .swid_i (swid_i ), - .swdata_i (swdata_i ), - .swstrb_i (swstrb_i ), - .swlast_i (swlast_i ), - .swvalid_i (swvalid_i ), - .swready_o (swready_o ), - .sbid_o (sbid_o ), - .sbresp_o (sbresp_o ), - .sbvalid_o (sbvalid_o ), - .sbready_i (sbready_i ), - .sarid_i (sarid_i ), - .saraddr_i (saraddr_i ), - .sarlen_i (sarlen_i ), - .sarsize_i (sarsize_i ), - .sarburst_i (sarburst_i ), - .sarlock_i (sarlock_i ), - .sarcache_i (sarcache_i ), - .sarprot_i (sarprot_i ), - .sarvalid_i (sarvalid_i ), - .sarready_o (sarready_o ), - .srid_o (srid_o ), - .srdata_o (srdata_o ), - .srresp_o (srresp_o ), - .srlast_o (srlast_o ), - .srvalid_o (srvalid_o ), - .srready_i (srready_i ), - .datareq (datareq ), - .datareqc (datareqc ), - .datarw (datarw ), - .dataeob (dataeob ), - .dataeobc (dataeobc ), - .dataaddr (dataaddr ), - .datao (datao ), - .dataack (dataack ), - .datai (datai ), - .rstcsr (rstcsr ), - .csrack (csrack ), - .csrdatao (csrdatao ), - .csrreq (csrreq ), - .csrrw (csrrw ), - .csrbe (csrbe ), - .csrdatai (csrdatai ), - .csraddr (csraddr ) - ); - -endmodule diff --git a/resources/soc/rtl/MAC/mac_top.v b/resources/soc/rtl/MAC/mac_top.v deleted file mode 100644 index f20c1df..0000000 --- a/resources/soc/rtl/MAC/mac_top.v +++ /dev/null @@ -1,445 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -module mac_top -( - hclk, - hrst_, - - mawid_o , - mawaddr_o , - mawlen_o , - mawsize_o , - mawburst_o , - mawlock_o , - mawcache_o , - mawprot_o , - mawvalid_o , - mawready_i , - mwid_o , - mwdata_o , - mwstrb_o , - mwlast_o , - mwvalid_o , - mwready_i , - mbid_i , - mbresp_i , - mbvalid_i , - mbready_o , - marid_o , - maraddr_o , - marlen_o , - marsize_o , - marburst_o , - marlock_o , - marcache_o , - marprot_o , - marvalid_o , - marready_i , - mrid_i , - mrdata_i , - mrresp_i , - mrlast_i , - mrvalid_i , - mrready_o , - sawid_i , - sawaddr_i , - sawlen_i , - sawsize_i , - sawburst_i , - sawlock_i , - sawcache_i , - sawprot_i , - sawvalid_i , - sawready_o , - swid_i , - swdata_i , - swstrb_i , - swlast_i , - swvalid_i , - swready_o , - sbid_o , - sbresp_o , - sbvalid_o , - sbready_i , - sarid_i , - saraddr_i , - sarlen_i , - sarsize_i , - sarburst_i , - sarlock_i , - sarcache_i , - sarprot_i , - sarvalid_i , - sarready_o , - srid_o , - srdata_o , - srresp_o , - srlast_o , - srvalid_o , - srready_i , - - interrupt , - - mtxclk , - mtxen , - mtxd , - mtxerr , - mrxclk , - mrxdv , - mrxd , - mrxerr , - mcoll , - mcrs , - mdc , - md_i , - md_o , - md_oe , - - trdata , - twe , - twaddr , - traddr , - twdata , - - rrdata , - rwe , - rwaddr , - rraddr , - rwdata - -); - - -input hclk; -input hrst_; - output [ 3:0] mawid_o ; - output [ 31:0] mawaddr_o ; - output [ 3:0] mawlen_o ; - output [ 2:0] mawsize_o ; - output [ 1:0] mawburst_o ; - output [ 1:0] mawlock_o ; - output [ 3:0] mawcache_o ; - output [ 2:0] mawprot_o ; - output mawvalid_o ; - input mawready_i ; - output [ 3:0] mwid_o ; - output [ 31:0] mwdata_o ; - output [ 3:0] mwstrb_o ; - output mwlast_o ; - output mwvalid_o ; - input mwready_i ; - input [ 3:0] mbid_i ; - input [ 1:0] mbresp_i ; - input mbvalid_i ; - output mbready_o ; - output [ 3:0] marid_o ; - output [ 31:0] maraddr_o ; - output [ 3:0] marlen_o ; - output [ 2:0] marsize_o ; - output [ 1:0] marburst_o ; - output [ 1:0] marlock_o ; - output [ 3:0] marcache_o ; - output [ 2:0] marprot_o ; - output marvalid_o ; - input marready_i ; - input [ 3:0] mrid_i ; - input [ 31:0] mrdata_i ; - input [ 1:0] mrresp_i ; - input mrlast_i ; - input mrvalid_i ; - output mrready_o ; - - input [ 3:0] sawid_i ; - input [ 31:0] sawaddr_i ; - input [ 3:0] sawlen_i ; - input [ 2:0] sawsize_i ; - input [ 1:0] sawburst_i ; - input [ 1:0] sawlock_i ; - input [ 3:0] sawcache_i ; - input [ 2:0] sawprot_i ; - input sawvalid_i ; - output sawready_o ; - input [ 3:0] swid_i ; - input [ 31:0] swdata_i ; - input [ 3:0] swstrb_i ; - input swlast_i ; - input swvalid_i ; - output swready_o ; - output [ 3:0] sbid_o ; - output [ 1:0] sbresp_o ; - output sbvalid_o ; - input sbready_i ; - input [ 3:0] sarid_i ; - input [ 31:0] saraddr_i ; - input [ 3:0] sarlen_i ; - input [ 2:0] sarsize_i ; - input [ 1:0] sarburst_i ; - input [ 1:0] sarlock_i ; - input [ 3:0] sarcache_i ; - input [ 2:0] sarprot_i ; - input sarvalid_i ; - output sarready_o ; - output [ 3:0] srid_o ; - output [ 31:0] srdata_o ; - output [ 1:0] srresp_o ; - output srlast_o ; - output srvalid_o ; - input srready_i ; -input mtxclk; -output [3:0] mtxd; -output mtxen; -output mtxerr; - -input mrxclk; -input [3:0] mrxd; -input mrxdv; -input mrxerr; - -input mcoll; -input mcrs; - -input md_i; -output mdc; -output md_o; -output md_oe; - -output interrupt; - - -`define MAHBDATAWIDTH 32 -`define TFIFODEPTH 9 -`define RFIFODEPTH 9 -`define ADDRDEPTH 6 - -input [`MAHBDATAWIDTH - 1:0] trdata; -output twe; -wire twe; -output [`TFIFODEPTH - 1:0] twaddr; -wire [`TFIFODEPTH - 1:0] twaddr; -output [`TFIFODEPTH - 1:0] traddr; -wire [`TFIFODEPTH - 1:0] traddr; -output [`MAHBDATAWIDTH - 1:0] twdata; -wire [`MAHBDATAWIDTH - 1:0] twdata; - -input [`MAHBDATAWIDTH - 1:0] rrdata; -output rwe; -wire rwe; -output [`RFIFODEPTH - 1:0] rwaddr; -wire [`RFIFODEPTH - 1:0] rwaddr; -output [`RFIFODEPTH - 1:0] rraddr; -wire [`RFIFODEPTH - 1:0] rraddr; -output [`MAHBDATAWIDTH - 1:0] rwdata; -wire [`MAHBDATAWIDTH - 1:0] rwdata; - -wire tps,rps,rsttco,rstrco,sclk,scs,sdo; - -wire [15:0] frdata; -wire fwe; -wire [`ADDRDEPTH - 1:0] fwaddr; -wire [`ADDRDEPTH - 1:0] fraddr; -wire [15:0] fwdata; - -wire match; -wire matchval; -wire matchen; -wire [47:0] matchdata; - -assign match = 1'b0; -assign matchval = 1'b0; - -RegFile2_64x16 u_addr_ram -( -.CLKA(mrxclk), .CENA(1'b0), .AA(fraddr), .QA(frdata), -.CLKB(hclk), .CENB(!fwe), .AB(fwaddr), .DB(fwdata) -); - -MAC_AXI u_mac_axi ( - .clkt(mtxclk), - .clkr(mrxclk), - .rsttco(rsttco), - .rstrco(rstrco), - .interrupt(interrupt), - .tps(tps), - .rps(rps), - - .mhclk (hclk ), - .mhresetn (hrst_ ), - .mawid_o (mawid_o ), - .mawaddr_o (mawaddr_o ), - .mawlen_o (mawlen_o ), - .mawsize_o (mawsize_o ), - .mawburst_o (mawburst_o ), - .mawlock_o (mawlock_o ), - .mawcache_o (mawcache_o ), - .mawprot_o (mawprot_o ), - .mawvalid_o (mawvalid_o ), - .mawready_i (mawready_i ), - .mwid_o (mwid_o ), - .mwdata_o (mwdata_o ), - .mwstrb_o (mwstrb_o ), - .mwlast_o (mwlast_o ), - .mwvalid_o (mwvalid_o ), - .mwready_i (mwready_i ), - .mbid_i (mbid_i ), - .mbresp_i (mbresp_i ), - .mbvalid_i (mbvalid_i ), - .mbready_o (mbready_o ), - .marid_o (marid_o ), - .maraddr_o (maraddr_o ), - .marlen_o (marlen_o ), - .marsize_o (marsize_o ), - .marburst_o (marburst_o ), - .marlock_o (marlock_o ), - .marcache_o (marcache_o ), - .marprot_o (marprot_o ), - .marvalid_o (marvalid_o ), - .marready_i (marready_i ), - .mrid_i (mrid_i ), - .mrdata_i (mrdata_i ), - .mrresp_i (mrresp_i ), - .mrlast_i (mrlast_i ), - .mrvalid_i (mrvalid_i ), - .mrready_o (mrready_o ), - .shclk (hclk ), - .shresetn (hrst_ ), - .sawid_i (sawid_i ), - .sawaddr_i (sawaddr_i ), - .sawlen_i (sawlen_i ), - .sawsize_i (sawsize_i ), - .sawburst_i (sawburst_i ), - .sawlock_i (sawlock_i ), - .sawcache_i (sawcache_i ), - .sawprot_i (sawprot_i ), - .sawvalid_i (sawvalid_i ), - .sawready_o (sawready_o ), - .swid_i (swid_i ), - .swdata_i (swdata_i ), - .swstrb_i (swstrb_i ), - .swlast_i (swlast_i ), - .swvalid_i (swvalid_i ), - .swready_o (swready_o ), - .sbid_o (sbid_o ), - .sbresp_o (sbresp_o ), - .sbvalid_o (sbvalid_o ), - .sbready_i (sbready_i ), - .sarid_i (sarid_i ), - .saraddr_i (saraddr_i ), - .sarlen_i (sarlen_i ), - .sarsize_i (sarsize_i ), - .sarburst_i (sarburst_i ), - .sarlock_i (sarlock_i ), - .sarcache_i (sarcache_i ), - .sarprot_i (sarprot_i ), - .sarvalid_i (sarvalid_i ), - .sarready_o (sarready_o ), - .srid_o (srid_o ), - .srdata_o (srdata_o ), - .srresp_o (srresp_o ), - .srlast_o (srlast_o ), - .srvalid_o (srvalid_o ), - .srready_i (srready_i ), - .trdata(trdata), - .twe(twe), - .twaddr(twaddr), - .traddr(traddr), - .twdata(twdata), - .rrdata(rrdata), - .rwe(rwe), - .rwaddr(rwaddr), - .rraddr(rraddr), - .rwdata(rwdata), - .frdata(frdata), - .fwe(fwe), - .fwaddr(fwaddr), - .fraddr(fraddr), - .fwdata(fwdata), - .match(match), - .matchval(matchval), - .matchen(matchen), - .matchdata(matchdata), - .sdi(1'b0), - .sclk(sclk), - .scs(scs), - .sdo(sdo), - .rxer(mrxerr), - .rxdv(mrxdv), - .col(mcoll), - .crs(mcrs), - .rxd(mrxd), - .txen(mtxen), - .txer(mtxerr), - .txd(mtxd), - .mdc(mdc), - .mdi(md_i), - .mdo(md_o), - .mden(md_oe) - ); - -endmodule - -module RegFile2_64x16 ( - QA, - AA, - CLKA, - CENA, - AB, - DB, - CLKB, - CENB -); - parameter BITS = 16; - parameter word_depth = 64; - parameter addr_width = 6; - output [15:0] QA; - input [5:0] AA; - input CLKA; - input CENA; - input [5:0] AB; - input [15:0] DB; - input CLKB; - input CENB; - reg [15:0] QA; - - reg [BITS-1:0] mem [word_depth-1:0]; - - wire NOT_CENA; - wire NOT_CENB; - - not (NOT_CENA, CENA); - always @ ( posedge CLKA ) if ( NOT_CENA ) QA<=mem[AA]; - - not (NOT_CENB, CENB); - always @ ( posedge CLKB ) if ( NOT_CENB ) mem[AB]<=DB; - -endmodule diff --git a/resources/soc/rtl/MAC/maccsr2axi.v b/resources/soc/rtl/MAC/maccsr2axi.v deleted file mode 100644 index 15e9d7a..0000000 --- a/resources/soc/rtl/MAC/maccsr2axi.v +++ /dev/null @@ -1,291 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -module MACCSR2AXI ( - saclk , - saresetn , - awid_i , - awaddr_i , - awlen_i , - awsize_i , - awburst_i , - awlock_i , - awcache_i , - awprot_i , - awvalid_i , - awready_o , - wid_i , - wdata_i , - wstrb_i , - wlast_i , - wvalid_i , - wready_o , - bid_o , - bresp_o , - bvalid_o , - bready_i , - arid_i , - araddr_i , - arlen_i , - arsize_i , - arburst_i , - arlock_i , - arcache_i , - arprot_i , - arvalid_i , - arready_o , - rid_o , - rdata_o , - rresp_o , - rlast_o , - rvalid_o , - rready_i , - - rstcsr , - csrack , - csrdatao , - csrreq , - csrrw , - csrbe , - csrdatai , - csraddr - ); - - - parameter SAXIDATAWIDTH = 32; - parameter SAXIADDRESSWIDTH = 32; - parameter CSRDATAWIDTH = 32; - parameter CSRADDRESSWIDTH = 8; - - - - input saclk; - input saresetn; - input [ 3:0] awid_i ; - input [ 31:0] awaddr_i ; - input [ 3:0] awlen_i ; - input [ 2:0] awsize_i ; - input [ 1:0] awburst_i ; - input [ 1:0] awlock_i ; - input [ 3:0] awcache_i ; - input [ 2:0] awprot_i ; - input awvalid_i ; - output awready_o ; - input [ 3:0] wid_i ; - input [ 31:0] wdata_i ; - input [ 3:0] wstrb_i ; - input wlast_i ; - input wvalid_i ; - output wready_o ; - output [ 3:0] bid_o ; - output [ 1:0] bresp_o ; - output bvalid_o ; - input bready_i ; - input [ 3:0] arid_i ; - input [ 31:0] araddr_i ; - input [ 3:0] arlen_i ; - input [ 2:0] arsize_i ; - input [ 1:0] arburst_i ; - input [ 1:0] arlock_i ; - input [ 3:0] arcache_i ; - input [ 2:0] arprot_i ; - input arvalid_i ; - output arready_o ; - output [ 3:0] rid_o ; - output [ 31:0] rdata_o ; - output [ 1:0] rresp_o ; - output rlast_o ; - output rvalid_o ; - input rready_i ; - - - output rstcsr; - wire rstcsr; - input csrack; - input [CSRDATAWIDTH - 1:0] csrdatao; - output csrreq; - wire csrreq; - output csrrw; - wire csrrw; - output [CSRDATAWIDTH / 8 - 1:0] csrbe; - wire [CSRDATAWIDTH / 8 - 1:0] csrbe; - output [CSRDATAWIDTH - 1:0] csrdatai; - wire [CSRDATAWIDTH - 1:0] csrdatai; - output [CSRADDRESSWIDTH - 1:0] csraddr; - wire [CSRADDRESSWIDTH - 1:0] csraddr; - - -reg isWriting; -reg isReading; -wire awready; -wire arready; -wire wvalid; -wire wlast; -wire wready; -wire rvalid; -wire rlast; -wire rready; - -assign wvalid = wvalid_i; -assign wlast = wlast_i; - -always @(posedge saclk) -begin - if (!saresetn || (wlast && wvalid && wready)) - begin - isWriting <= 1'b0; - end - else if (awvalid_i && awready) - begin - isWriting <= 1'b1; - end -end -always @(posedge saclk) -begin - if (!saresetn || (rlast && rvalid && rready)) - begin - isReading <= 1'b0; - end - else if (arvalid_i && arready) - begin - isReading <= 1'b1; - end -end - -wire arvalid; -wire rd_valid; -wire [1:0] rresp; -wire [31:0] rdata; -reg [31:0] rd_addr; -reg [3:0] rid; -reg [2:0] rd_size; - - -assign arvalid = arvalid_i; -assign rd_valid = arvalid & arready; -assign rready = rready_i; -assign rresp = 2'b00; - -always @(posedge saclk) - if(rd_valid) begin - rid <= arid_i; - end - -always @(posedge saclk) -begin - if(!saresetn) begin - rd_addr <= 32'h0; - end - else if (rd_valid) begin - rd_addr <= araddr_i; - end -end - -assign arready = csrack & !isWriting & !isReading; -assign rvalid = csrrw & csrack; -assign rlast = 1'b1; -assign rdata = csrdatao; - -reg [31:0] wr_addr; -wire wr_valid; -wire [3:0] wr_strb; -wire awvalid; -wire bready; - -assign awvalid = awvalid_i; -assign awready = csrack & !isWriting & !isReading; -assign wready = !csrrw && csrack; -assign bready = bready_i; -assign wr_strb = {4{wvalid}} & wstrb_i; -assign wr_valid = awvalid & awready; - - -always @(posedge saclk) -begin - if(!saresetn) begin - wr_addr <= 32'h0; - end - else if (wr_valid) begin - wr_addr <= awaddr_i; - end -end - - -wire w_resp_valid; -reg w_resp_valid_r; -reg[3:0] bid_r; -assign w_resp_valid = wvalid & wlast & wready; -always @(posedge saclk) - if(!saresetn) begin - w_resp_valid_r <= 1'b0; - bid_r <= 4'b0; - end - else if(w_resp_valid) begin - w_resp_valid_r <= 1'b1; - bid_r <= wid_i; - end - else if(bready) begin - w_resp_valid_r <= 1'b0; - end - -wire [1:0] bresp = 2'b00; -wire [3:0] bid = bid_r; -wire bvalid = w_resp_valid_r; - -assign csrdatai = wdata_i; - -assign csrbe = wr_strb; - -assign csraddr = csrrw ? rd_addr[7:0]: wr_addr[7:0]; - -assign csrreq = isWriting | isReading; - -assign csrrw = isReading; - -assign rstcsr = ~saresetn; - -assign awready_o = awready; -assign wready_o = wready; - -assign bid_o = bid; -assign bresp_o = bresp; -assign bvalid_o = bvalid; - -assign arready_o = arready; -assign rid_o = rid; -assign rdata_o = rdata; -assign rresp_o = rresp; -assign rlast_o = rlast; -assign rvalid_o = rvalid; - -endmodule diff --git a/resources/soc/rtl/MAC/macdata2axi.v b/resources/soc/rtl/MAC/macdata2axi.v deleted file mode 100644 index ca70bea..0000000 --- a/resources/soc/rtl/MAC/macdata2axi.v +++ /dev/null @@ -1,248 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -module MACDATA2AXI ( - maclk , - maresetn , - - awid_o , - awaddr_o , - awlen_o , - awsize_o , - awburst_o , - awlock_o , - awcache_o , - awprot_o , - awvalid_o , - awready_i , - wid_o , - wdata_o , - wstrb_o , - wlast_o , - wvalid_o , - wready_i , - bid_i , - bresp_i , - bvalid_i , - bready_o , - arid_o , - araddr_o , - arlen_o , - arsize_o , - arburst_o , - arlock_o , - arcache_o , - arprot_o , - arvalid_o , - arready_i , - rid_i , - rdata_i , - rresp_i , - rlast_i , - rvalid_i , - rready_o , - datareq , - datareqc , - datarw , - dataeob , - dataeobc , - dataaddr , - datao , - dataack , - datai - ); - - parameter MAXIDATAWIDTH = 32; - parameter MAXIADDRESSWIDTH = 32; - parameter MACDATAWIDTH = 32; - parameter MACADDRESSWIDTH = 32; - - -input maclk; -input maresetn; -output [ 3:0] awid_o ; -output [ 31:0] awaddr_o ; -output [ 3:0] awlen_o ; -output [ 2:0] awsize_o ; -output [ 1:0] awburst_o ; -output [ 1:0] awlock_o ; -output [ 3:0] awcache_o ; -output [ 2:0] awprot_o ; -output awvalid_o ; -input awready_i ; -output [ 3:0] wid_o ; -output [ 31:0] wdata_o ; -output [ 3:0] wstrb_o ; -output wlast_o ; -output wvalid_o ; -input wready_i ; -input [ 3:0] bid_i ; -input [ 1:0] bresp_i ; -input bvalid_i ; -output bready_o ; -output [ 3:0] arid_o ; -output [ 31:0] araddr_o ; -output [ 3:0] arlen_o ; -output [ 2:0] arsize_o ; -output [ 1:0] arburst_o ; -output [ 1:0] arlock_o ; -output [ 3:0] arcache_o ; -output [ 2:0] arprot_o ; -output arvalid_o ; -input arready_i ; -input [ 3:0] rid_i ; -input [ 31:0] rdata_i ; -input [ 1:0] rresp_i ; -input rlast_i ; -input rvalid_i ; -output rready_o ; - - -input datareq; -input datareqc; -input datarw; -input dataeob; -input dataeobc; -input [MACADDRESSWIDTH - 1:0] dataaddr; -input [MACDATAWIDTH - 1:0] datao; -output dataack; -wire dataack; -output [MACDATAWIDTH - 1:0] datai; -wire [MACDATAWIDTH - 1:0] datai; - - -assign arid_o = 4'h1; -assign arsize_o = 3'b010; -assign arlen_o = 4'b0000; -assign arburst_o = 2'b01; -assign arlock_o = 2'b00; -assign arcache_o = 4'b0000; -assign arprot_o = 3'b110; - -reg isWriting; -reg isReading; - -always @(posedge maclk) -begin - if (!maresetn || (wlast_o && wvalid_o && wready_i)) - begin - isWriting <= 1'b0; - end - else if (awvalid_o && awready_i) - begin - isWriting <= 1'b1; - end -end - -always @(posedge maclk) -begin - if (!maresetn || (rlast_i && rvalid_i && rready_o)) - begin - isReading <= 1'b0; - end - else if (arvalid_o && arready_i) - begin - isReading <= 1'b1; - end -end - -reg [MACADDRESSWIDTH-1:0] dataAddr_c_r; -wire [MACADDRESSWIDTH-1:0] dataAddr_c; -wire dataAddr_sel; -reg dataReq_r; - -always @(posedge maclk) -begin - dataReq_r <= datareq; -end - -wire dataAddr_c_r_en; -assign dataAddr_c_r_en = (awvalid_o & awready_i) | - (arvalid_o & arready_i); -always @(posedge maclk) -begin - if (!maresetn) - begin - dataAddr_c_r <= 32'd0; - end - else if ( dataAddr_c_r_en) - begin - dataAddr_c_r <= dataAddr_c; - end -end - -assign dataAddr_sel = datareq & (~dataReq_r | dataeob); -assign dataAddr_c = dataAddr_sel ? dataaddr : dataAddr_c_r+3'b100; - -wire arvalid; -assign arvalid = datareq & datarw & ~isWriting & ~isReading; - -assign araddr_o = dataAddr_c; -assign arvalid_o = arvalid; - -assign rready_o = 1'b1; -assign datai = rdata_i; -wire readDataAck; -assign readDataAck = rvalid_i & rready_o; - -assign awid_o = 4'h1; -assign awsize_o = 3'b010; -assign awlen_o = 4'b0000; -assign awburst_o = 2'b01; -assign awlock_o = 2'b00; -assign awcache_o = 4'b0000; -assign awprot_o = 3'b110; - -wire awvalid; -assign awvalid = datareq & ~datarw & ~isWriting & ~isReading; - -assign awvalid_o = awvalid; -assign awaddr_o = dataAddr_c; - -wire wvalid; -assign wid_o = 4'h1; -assign wlast_o = 1'b1; -assign wdata_o = datao; -assign wstrb_o = 4'b1111; - -assign wvalid = (awvalid_o & awready_i) | isWriting; -assign wvalid_o = wvalid; - -wire writeDataAck; -assign writeDataAck = wvalid & wready_i; - -assign bready_o = 1'b1; - -assign dataack = readDataAck | writeDataAck; - -endmodule diff --git a/resources/soc/rtl/MAC/rc.v b/resources/soc/rtl/MAC/rc.v deleted file mode 100644 index 2e26c57..0000000 --- a/resources/soc/rtl/MAC/rc.v +++ /dev/null @@ -1,1749 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -module RC ( - clk, - rst, - rxdv, - rxer, - rxd, - col, - ramwe, - ramaddr, - ramdata, - fdata, - faddr, - cachenf, - radg, - wadg, - rprog, - rcpoll, - riack, - ren, - ra, - pm, - pr, - pb, - rif, - ho, - hp, - rireq, - ff, - rf, - mf, - db, - re, - ce, - tl, - ftp, - ov, - cs, - length, - match, - matchval, - matchen, - matchdata, - focl, - foclack, - oco, - focg, - mfcl, - mfclack, - mfo, - mfcg, - stopi, - stopo, - rcsack, - rcsreq, - insert_en_i -); - - parameter FIFODEPTH = 9; - parameter DATAWIDTH = 32; - - `include "utility.v" - - input clk; - input rst; - - input col; - input rxdv; - input rxer; - input [MIIWIDTH - 1:0] rxd; - - output ramwe; - wire ramwe; - output [FIFODEPTH - 1:0] ramaddr; - wire [FIFODEPTH - 1:0] ramaddr; - output [DATAWIDTH - 1:0] ramdata; - wire [DATAWIDTH - 1:0] ramdata; - - input [ADDRWIDTH - 1:0] fdata; - output [ADDRDEPTH - 1:0] faddr; - wire [ADDRDEPTH - 1:0] faddr; - - input cachenf; - input [FIFODEPTH - 1:0] radg; - output [FIFODEPTH - 1:0] wadg; - wire [FIFODEPTH - 1:0] wadg; - output rprog; - reg rprog; - output rcpoll; - wire rcpoll; - - input riack; - input ren; - input ra; - input pm; - input pr; - input pb; - input rif; - input ho; - input hp; - output rireq; - reg rireq; - output ff; - reg ff; - output rf; - reg rf; - output mf; - reg mf; - output db; - reg db; - output re; - reg re; - output ce; - reg ce; - output tl; - reg tl; - output ftp; - reg ftp; - output cs; - reg cs; - output ov; - reg ov; - output [13:0] length; - reg [13:0] length; - - input match; - input matchval; - output matchen; - reg matchen; - output [47:0] matchdata; - wire [47:0] matchdata; - - input focl; - output foclack; - wire foclack; - output oco; - reg oco; - output [10:0] focg; - reg [10:0] focg; - input mfcl; - output mfclack; - output mfo; - reg mfo; - output [15:0] mfcg; - reg [15:0] mfcg; - - input stopi; - output stopo; - reg stopo; - - input rcsack; - output rcsreq; - reg rcsreq; - - input insert_en_i; - - - reg insert_en_0_r; - reg insert_en_r; - - reg we; - reg full; - reg [FIFODEPTH - 1:0] wad; - reg [FIFODEPTH - 1:0] wadi; - reg [FIFODEPTH - 1:0] iwadg; - reg [FIFODEPTH - 1:0] wadig; - reg [FIFODEPTH - 1:0] radg_0_r; - reg [FIFODEPTH - 1:0] radg_r; - reg [FIFODEPTH - 1:0] isofad; - reg cachenf_r; - reg cachenf_2r; - reg fcfbci; - reg fcfbci_r; - reg eorfff; - - - reg col_r; - reg rxdv_r; - reg rxer_r; - reg [MIIWIDTH - 1:0] rxd_r; - wire [3:0] rxd_r4; - - reg [3:0] rsm_c; - reg [3:0] rsm; - reg [3:0] ncnt; - wire [1:0] ncnt10; - wire [2:0] ncnt20; - reg [DATAWIDTH - 1:0] data_c; - reg [DATAWIDTH - 1:0] data; - reg [31:0] crc_c; - reg [31:0] crc; - reg [6:0] bcnt; - wire [2:0] bcnt20; - reg bz; - reg winp; - wire iri_c; - reg iri; - reg riack_r; - reg [13:0] lcnt; - reg [15:0] lfield; - reg ren_r; - reg irprog; - - reg [2:0] fsm_c; - reg [2:0] fsm; - reg perfm_c; - reg perfm; - reg invm; - reg [8:0] crchash; - reg hash; - reg [47:0] dest; - reg [2:0] flcnt; - reg [ADDRDEPTH - 1:0] fa; - reg [15:0] fdata_r; - - reg rcs; - reg rcsack_r; - reg [7:0] rcscnt; - - reg [10:0] focnt; - reg focl_r; - reg [15:0] mfcnt; - reg mfcl_r; - - reg stop_r; - - wire [FIFODEPTH - 1:0] fzero; - wire [MIIWIDTH_MAX + 1:0] mzero_max; - wire [MIIWIDTH_MAX + 1:0] rxd_r_max; - - always @(posedge clk) - begin : mii_reg_proc - if (rst) - begin - col_r <= 1'b0; - rxdv_r <= 1'b0 ; - rxer_r <= 1'b0 ; - rxd_r <= {MIIWIDTH{1'b0}} ; - data <= {DATAWIDTH{1'b1}} ; - end - else - begin - col_r <= col ; - rxdv_r <= rxdv ; - rxer_r <= rxer ; - rxd_r <= rxd ; - data <= data_c ; - end - end - - assign rxd_r4 = rxd_r_max[MIIWIDTH-1:0]; - - assign ncnt10 = ncnt[1:0] ; - - assign ncnt20 = ncnt[2:0] ; - - wire [2:0] n_offset; - assign n_offset = (insert_en_r) ? ((ncnt20 + 3'b100) & 3'b111) : ncnt20; - - always @(ncnt or ncnt10 or n_offset or rxd_r_max or data) - begin : data_proc - reg[15:0] data16; - reg[31:0] data32; - case (DATAWIDTH) - 8 : - begin - data_c <= data ; - if (!(ncnt[0])) - begin - data_c[3:0] <= rxd_r_max[MIIWIDTH-1:0] ; - end - else - begin - data_c[7:4] <= rxd_r_max[MIIWIDTH-1:0] ; - end - end - 16 : - begin - data16 = data; - case (ncnt10) - 2'b00 : - begin - data16[3:0] = rxd_r_max[MIIWIDTH-1:0]; - end - 2'b01 : - begin - data16[7:4] = rxd_r_max[MIIWIDTH-1:0]; - end - 2'b10 : - begin - data16[11:8] = rxd_r_max[MIIWIDTH-1:0]; - end - default : - begin - data16[15:12] = rxd_r_max[MIIWIDTH-1:0]; - end - endcase - data_c <= data16 ; - end - default : - begin - data32 = data; - case (n_offset) - 3'b000 : - begin - data32[3:0] = rxd_r_max[MIIWIDTH-1:0]; - end - 3'b001 : - begin - data32[7:4] = rxd_r_max[MIIWIDTH-1:0]; - end - 3'b010 : - begin - data32[11:8] = rxd_r_max[MIIWIDTH-1:0]; - end - 3'b011 : - begin - data32[15:12] = rxd_r_max[MIIWIDTH-1:0]; - end - 3'b100 : - begin - data32[19:16] = rxd_r_max[MIIWIDTH-1:0]; - end - 3'b101 : - begin - data32[23:20] = rxd_r_max[MIIWIDTH-1:0]; - end - 3'b110 : - begin - data32[27:24] = rxd_r_max[MIIWIDTH-1:0]; - end - default : - begin - data32[31:28] = rxd_r_max[MIIWIDTH-1:0]; - end - endcase - data_c <= data32 ; - end - endcase - end - - always @(posedge clk) - begin : fifofull_reg_proc - if (rst) - begin - cachenf_r <= 1'b1 ; - cachenf_2r <= 1'b1 ; - full <= 1'b0 ; - end - else - begin - cachenf_r <= cachenf ; - - if(cachenf_2r | - ( - (!rxdv_r & cachenf_r) | - ( rxdv_r & cachenf_r & - (rsm==RSM_IDLE_RCSMT | rsm==RSM_SFD) - ) - ) - ) - begin - cachenf_2r <= cachenf ; - end - - if ((wadig == radg_r) | (iwadg == radg_r & full)) - begin - full <= 1'b1 ; - end - else - begin - full <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : addr_reg_proc - if (rst) - begin - wad <= {FIFODEPTH{1'b0}} ; - wadi <= {fzero[FIFODEPTH - 1:1], 1'b1} ; - iwadg <= {FIFODEPTH{1'b0}} ; - isofad <= {FIFODEPTH{1'b0}} ; - wadig <= {fzero[FIFODEPTH - 1:1],1'b1} ; - radg_0_r <= {FIFODEPTH{1'b0}} ; - radg_r <= {FIFODEPTH{1'b0}} ; - insert_en_0_r <= 1'b0; - insert_en_r <= 1'b0; - end - else - begin - if (rsm == RSM_BAD) - begin - wad <= isofad ; - end - else if (we) - begin - wad <= wad + 1 ; - end - - if (rsm == RSM_BAD) - begin - wadi <= isofad + 1 ; - end - else if (we) - begin - wadi <= wadi + 1 ; - end - - iwadg[FIFODEPTH - 1] <= wad[FIFODEPTH - 1] ; - begin : iwaddrg_loop - integer i; - for(i = FIFODEPTH - 2; i >= 0; i = i - 1) - begin - iwadg[i] <= wad[i + 1] ^ wad[i] ; - end - end - - wadig[FIFODEPTH - 1] <= wadi[FIFODEPTH - 1] ; - begin : waddrig_loop - integer i; - for(i = FIFODEPTH - 2; i >= 0; i = i - 1) - begin - wadig[i] <= wadi[i + 1] ^ wadi[i] ; - end - end - - if (rsm == RSM_IDLE_RCSMT) - begin - isofad <= wad ; - end - - radg_0_r <= radg ; - radg_r <= radg_0_r ; - - insert_en_0_r <= insert_en_i; - insert_en_r <= insert_en_0_r; - - end - end - - always @(posedge clk) - begin : we_reg_proc - if (rst) - begin - we <= 1'b0 ; - end - else - begin - if ((rsm == RSM_INFO | - rsm == RSM_DEST | - rsm == RSM_LENGTH | - rsm == RSM_SOURCE) & - ((rxdv_r & ((DATAWIDTH == 8 & (ncnt[0])) | - (DATAWIDTH == 16 & ncnt[1:0] == 2'b11) | - (DATAWIDTH == 32 & n_offset[2:0] == 3'b111))) | - (!rxdv_r & !we & - ( - (DATAWIDTH==32 & n_offset[2:1]!=2'b00) | - (DATAWIDTH==16 & ncnt[1] !=1'b0) - ) - ) | - (full & !we))) - begin - we <= 1'b1 ; - end - else - begin - we <= 1'b0 ; - end - end - end - - assign ramdata = data ; - - assign ramwe = we ; - - assign ramaddr = wad ; - - assign wadg = iwadg ; - - always @(rsm or - rxdv_r or - rxd_r_max or - rxd_r4 or - stop_r or - bz or - fsm or - ra or - pm or - pb or - dest or - riack_r or - full or - ren_r or - winp or - irprog or - cachenf_r) - begin : rsm_proc - case (rsm) - RSM_IDLE_RCSMT : - begin - if (rxdv_r & !stop_r & ren_r) - begin - if (rxd_r_max[MIIWIDTH-1:0] == 4'b0101) - begin - rsm_c <= RSM_SFD ; - end - else - begin - rsm_c <= RSM_IDLE_RCSMT ; - end - end - else - begin - rsm_c <= RSM_IDLE_RCSMT ; - end - end - RSM_SFD : - begin - if (rxdv_r & !full & cachenf_r) - begin - case (rxd_r4) - 4'b1101 : - begin - rsm_c <= RSM_DEST ; - end - 4'b0101 : - begin - rsm_c <= RSM_SFD ; - end - default : - begin - rsm_c <= RSM_IDLE_RCSMT ; - end - endcase - end - else if (full | !cachenf_r) - begin - rsm_c <= RSM_BAD ; - end - else - begin - rsm_c <= RSM_IDLE_RCSMT ; - end - end - RSM_DEST : - begin - if (!rxdv_r | full | !cachenf_r) - begin - rsm_c <= RSM_BAD ; - end - else if (bz) - begin - rsm_c <= RSM_SOURCE ; - end - else - begin - rsm_c <= RSM_DEST ; - end - end - RSM_SOURCE : - begin - if (!rxdv_r) - begin - if ((pb) & (fsm == FSM_MATCH | ra | (pm & (dest[0])))) - begin - rsm_c <= RSM_SUCC ; - end - else - begin - rsm_c <= RSM_BAD ; - end - end - else if (full | !cachenf_r) - begin - rsm_c <= RSM_BAD ; - end - else if (bz) - begin - rsm_c <= RSM_LENGTH ; - end - else - begin - rsm_c <= RSM_SOURCE ; - end - end - RSM_LENGTH : - begin - if (!rxdv_r) - begin - if ((pb) & (fsm == FSM_MATCH | ra | (pm & (dest[0])))) - begin - rsm_c <= RSM_SUCC ; - end - else - begin - rsm_c <= RSM_BAD ; - end - end - else if (full | !cachenf_r) - begin - rsm_c <= RSM_BAD ; - end - else if (bz) - begin - rsm_c <= RSM_INFO ; - end - else - begin - rsm_c <= RSM_LENGTH ; - end - end - RSM_INFO : - begin - if (!rxdv_r) - begin - if ((winp | pb) & - (fsm == FSM_MATCH | ra | (pm & (dest[0])))) - begin - rsm_c <= RSM_SUCC ; - end - else - begin - rsm_c <= RSM_BAD ; - end - end - else if (full | !cachenf_r) - begin - if (winp) - begin - rsm_c <= RSM_SUCC ; - end - else - begin - rsm_c <= RSM_BAD ; - end - end - else if (fsm == FSM_FAIL & !ra & ~(pm & (dest[0]))) - begin - rsm_c <= RSM_BAD ; - end - else - begin - rsm_c <= RSM_INFO ; - end - end - RSM_SUCC : - begin - rsm_c <= RSM_INT ; - end - RSM_INT : - begin - if (riack_r) - begin - rsm_c <= RSM_INT1 ; - end - else - begin - rsm_c <= RSM_INT ; - end - end - RSM_INT1 : - begin - if (!rxdv_r & !riack_r) - begin - rsm_c <= RSM_IDLE_RCSMT ; - end - else - begin - rsm_c <= RSM_INT1 ; - end - end - default : - begin - if (!rxdv_r & !riack_r & !irprog) - begin - rsm_c <= RSM_IDLE_RCSMT ; - end - else - begin - rsm_c <= RSM_BAD ; - end - end - endcase - end - - always @(posedge clk) - begin : rsm_reg_proc - if (rst) - begin - rsm <= RSM_IDLE_RCSMT ; - end - else - begin - rsm <= rsm_c ; - end - end - - always @(posedge clk) - begin : rprog_reg_proc - if (rst) - begin - irprog <= 1'b0 ; - rprog <= 1'b0 ; - end - else - begin - if (rsm == RSM_IDLE_RCSMT | - rsm == RSM_BAD | - rsm == RSM_INT | - rsm == RSM_INT1) - begin - irprog <= 1'b0 ; - end - else - begin - irprog <= 1'b1 ; - end - - if (winp & irprog) - begin - rprog <= 1'b1 ; - end - else - begin - rprog <= 1'b0 ; - end - end - end - - assign rcpoll = irprog ; - - always @(posedge clk) - begin : bncnt_reg_proc - if (rst) - begin - bcnt <= {7{1'b0}} ; - bz <= 1'b0 ; - ncnt <= 4'b0000 ; - end - else - begin - if(cachenf_r) - begin - if (bz | rsm == RSM_IDLE_RCSMT) - begin - case (rsm) - RSM_IDLE_RCSMT : - begin - bcnt <= 7'b0000101 ; - end - RSM_DEST : - begin - bcnt <= 7'b0000101 ; - end - RSM_SOURCE : - begin - bcnt <= 7'b0000001 ; - end - default : - begin - bcnt <= 7'b0110001 ; - end - endcase - end - else - begin - if (ncnt[0]) - begin - bcnt <= bcnt - 1 ; - end - end - end - else - begin - if(!fcfbci_r) - begin - bcnt <= 7'b0111110 ; - end - else - begin - if (!ncnt[0]) - begin - bcnt <= bcnt - 1 ; - end - end - end - - if (bcnt == 7'b0000000 & !ncnt[0]) - begin - bz <= 1'b1 ; - end - else - begin - bz <= 1'b0 ; - end - - if (rsm == RSM_SFD | rsm == RSM_IDLE_RCSMT) - begin - ncnt <= 4'b0000 ; - end - else - begin - ncnt <= ncnt + 1 ; - end - end - end - - always @(posedge clk) - begin : winp_reg_proc - if (rst) - begin - winp <= 1'b0 ; - end - else - begin - if (rsm == RSM_IDLE_RCSMT) - begin - winp <= 1'b0 ; - end - else if ((rsm == RSM_INFO & bz & cachenf_2r) | - (rsm == RSM_BAD & bz & !cachenf_2r)) - begin - winp <= 1'b1 ; - end - end - end - - always @(crc or rsm or rxd_r_max) - begin : crc_proc - case (rsm) - RSM_IDLE_RCSMT : - begin - crc_c <= {32{1'b1}} ; - end - RSM_DEST, RSM_SOURCE, RSM_LENGTH, RSM_INFO : - begin - crc_c[0] <= crc[28] ^ - rxd_r_max[3] ; - crc_c[1] <= crc[28] ^ crc[29] ^ - rxd_r_max[2] ^ rxd_r_max[3] ; - crc_c[2] <= crc[28] ^ crc[29] ^ crc[30] ^ - rxd_r_max[1] ^ rxd_r_max[2] ^ rxd_r_max[3] ; - crc_c[3] <= crc[29] ^ crc[30] ^ crc[31] ^ - rxd_r_max[0] ^ rxd_r_max[1] ^ rxd_r_max[2] ; - crc_c[4] <= crc[0] ^ crc[28] ^ crc[30] ^ crc[31] ^ - rxd_r_max[0] ^ rxd_r_max[1] ^ rxd_r_max[3] ; - crc_c[5] <= crc[1] ^ crc[28] ^ crc[29] ^ crc[31] ^ - rxd_r_max[0] ^ rxd_r_max[2] ^ rxd_r_max[3] ; - crc_c[6] <= crc[2] ^ crc[29] ^ crc[30] ^ - rxd_r_max[1] ^ rxd_r_max[2] ; - crc_c[7] <= crc[3] ^ crc[28] ^ crc[30] ^ crc[31] ^ - rxd_r_max[0] ^ rxd_r_max[1] ^ rxd_r_max[3] ; - crc_c[8] <= crc[4] ^ crc[28] ^ crc[29] ^ crc[31] ^ - rxd_r_max[0] ^ rxd_r_max[2] ^ rxd_r_max[3] ; - crc_c[9] <= crc[5] ^ crc[29] ^ crc[30] ^ - rxd_r_max[1] ^ rxd_r_max[2] ; - crc_c[10] <= crc[6] ^ crc[28] ^ crc[30] ^ crc[31] ^ - rxd_r_max[0] ^ rxd_r_max[1] ^ rxd_r_max[3] ; - crc_c[11] <= crc[7] ^ crc[28] ^ crc[29] ^ crc[31] ^ - rxd_r_max[0] ^ rxd_r_max[2] ^ rxd_r_max[3] ; - crc_c[12] <= crc[8] ^ crc[28] ^ crc[29] ^ crc[30] ^ - rxd_r_max[1] ^ rxd_r_max[2] ^ rxd_r_max[3] ; - crc_c[13] <= crc[9] ^ crc[29] ^ crc[30] ^ crc[31] ^ - rxd_r_max[0] ^ rxd_r_max[1] ^ rxd_r_max[2] ; - crc_c[14] <= crc[10] ^ crc[30] ^ crc[31] ^ - rxd_r_max[0] ^ rxd_r_max[1] ; - crc_c[15] <= crc[11] ^ crc[31] ^ - rxd_r_max[0] ; - crc_c[16] <= crc[12] ^ crc[28] ^ - rxd_r_max[3] ; - crc_c[17] <= crc[13] ^ crc[29] ^ - rxd_r_max[2] ; - crc_c[18] <= crc[14] ^ crc[30] ^ - rxd_r_max[1] ; - crc_c[19] <= crc[15] ^ crc[31] ^ - rxd_r_max[0] ; - crc_c[20] <= crc[16] ; - crc_c[21] <= crc[17] ; - crc_c[22] <= crc[18] ^ crc[28] ^ - rxd_r_max[3] ; - crc_c[23] <= crc[19] ^ crc[28] ^ crc[29] ^ - rxd_r_max[2] ^ rxd_r_max[3] ; - crc_c[24] <= crc[20] ^ crc[29] ^ crc[30] ^ - rxd_r_max[1] ^ rxd_r_max[2] ; - crc_c[25] <= crc[21] ^ crc[30] ^ crc[31] ^ - rxd_r_max[0] ^ rxd_r_max[1] ; - crc_c[26] <= crc[22] ^ crc[28] ^ crc[31] ^ - rxd_r_max[0] ^ rxd_r_max[3] ; - crc_c[27] <= crc[23] ^ crc[29] ^ - rxd_r_max[2] ; - crc_c[28] <= crc[24] ^ crc[30] ^ - rxd_r_max[1] ; - crc_c[29] <= crc[25] ^ crc[31] ^ - rxd_r_max[0] ; - crc_c[30] <= crc[26] ; - crc_c[31] <= crc[27] ; - end - default : - begin - crc_c <= crc ; - end - endcase - end - - always @(posedge clk) - begin : crc_reg_proc - if (rst) - begin - crc <= {32{1'b1}} ; - end - else - begin - crc <= crc_c ; - end - end - - assign iri_c = (rsm == RSM_INT) ? 1'b1 : 1'b0 ; - - always @(posedge clk) - begin : rint_reg_proc - if (rst) - begin - iri <= 1'b0 ; - riack_r <= 1'b0 ; - rireq <= 1'b0 ; - end - else - begin - iri <= iri_c ; - riack_r <= riack ; - rireq <= iri ; - end - end - - wire [13:0] new_lcnt; - assign new_lcnt = (insert_en_r) ? (lcnt + 2'b10) : lcnt; - - always @(posedge clk) - begin : length_reg_proc - if (rst) - begin - lcnt <= {14{1'b0}} ; - length <= {14{1'b0}} ; - end - else - begin - if ((rsm == RSM_IDLE_RCSMT && cachenf_2r) | - (!fcfbci && !cachenf_2r) | - rsm == RSM_INT1) - begin - lcnt <= {14{1'b0}} ; - end - else if (((rsm == RSM_INFO | - rsm == RSM_LENGTH | - rsm == RSM_DEST | - rsm == RSM_SOURCE) & rxdv_r) | - (fcfbci && !cachenf_2r)) - begin - if (ncnt[0]) - begin - lcnt <= lcnt + 1 ; - end - end - - length[13] <= new_lcnt[13] ; - begin : length_loop - integer i; - for(i = 12; i >= 0; i = i - 1) - begin - length[i] <= new_lcnt[i + 1] ^ new_lcnt[i] ; - end - end - end - end - - always @(posedge clk) - begin : fcfbci_reg_proc - if (rst) - begin - fcfbci <= 1'b0 ; - fcfbci_r <= 1'b0 ; - end - else - begin - - fcfbci_r <= fcfbci ; - - if(!cachenf_2r) - begin - if(rxdv_r && rxd_r4==4'b1101) - begin - fcfbci <= 1'b1 ; - end - else if(!rxdv_r) - begin - fcfbci <= 1'b0 ; - end - end - else - begin - fcfbci <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : eorfff_reg_proc - if (rst) - begin - eorfff <= 1'b0 ; - end - else - begin - if(rsm_c==RSM_IDLE_RCSMT && rsm==RSM_BAD && !cachenf_2r) - begin - eorfff <= 1'b1 ; - end - else - begin - eorfff <= 1'b0 ; - end - end - end - - - always @(posedge clk) - begin : stat_reg_proc - if (rst) - begin - lfield <= {16{1'b0}} ; - ftp <= 1'b0 ; - tl <= 1'b0 ; - ff <= 1'b0 ; - mf <= 1'b0 ; - re <= 1'b0 ; - ce <= 1'b0 ; - db <= 1'b0 ; - rf <= 1'b0 ; - ov <= 1'b0 ; - cs <= 1'b0 ; - end - else - begin - if (rsm == RSM_LENGTH) - begin - if (bcnt[1:0] == 2'b00) - begin - if (!(ncnt[0])) - begin - lfield[3:0] <= rxd_r_max[MIIWIDTH-1:0] ; - end - else - begin - lfield[7:4] <= rxd_r_max[MIIWIDTH-1:0] ; - end - end - else - begin - if (!(ncnt[0])) - begin - lfield[11:8] <= rxd_r_max[MIIWIDTH-1:0] ; - end - else - begin - lfield[15:12] <= rxd_r_max[MIIWIDTH-1:0] ; - end - end - end - - if (lfield > MAX_SIZE) - begin - ftp <= 1'b1 ; - end - else - begin - ftp <= 1'b0 ; - end - - if (lcnt == MAX_FRAME & !iri_c) - begin - tl <= 1'b1 ; - end - else if (rsm == RSM_IDLE_RCSMT) - begin - tl <= 1'b0 ; - end - - if (!iri_c) - begin - if (fsm == FSM_MATCH) - begin - ff <= 1'b0 ; - end - else - begin - ff <= 1'b1 ; - end - end - - if (!iri_c) - begin - mf <= dest[0] ; - end - - if (rxer_r & !iri_c) - begin - re <= 1'b1 ; - end - else if (rsm == RSM_IDLE_RCSMT) - begin - re <= 1'b0 ; - end - - if (rsm == RSM_INFO & !(ncnt[0])) - begin - if (crc == CRCVAL) - begin - ce <= 1'b0 ; - end - else - begin - ce <= 1'b1 ; - end - end - - if (rsm == RSM_INFO) - begin - if (!rxdv_r & (ncnt[0])) - begin - db <= 1'b1 ; - end - else - begin - db <= 1'b0 ; - end - end - - if (!winp & iri_c) - begin - rf <= 1'b1 ; - end - else if (rsm == RSM_IDLE_RCSMT) - begin - rf <= 1'b0 ; - end - - if (rsm == RSM_IDLE_RCSMT) - begin - ov <= 1'b0 ; - end - else if (full | !cachenf_r) - begin - ov <= 1'b1 ; - end - - if (col_r & !iri_c) - begin - cs <= 1'b1 ; - end - else if (rsm == RSM_IDLE_RCSMT) - begin - cs <= 1'b0 ; - end - - - end - end - - always @(posedge clk) - begin : ren_reg_proc - if (rst) - begin - ren_r <= 1'b0 ; - end - else - begin - if (rsm == RSM_IDLE_RCSMT) - begin - ren_r <= ren ; - end - end - end - - always @(fsm or - rsm or - ho or - hp or - dest or - lcnt or - ncnt or - flcnt or - perfm or - hash or - pr or - fa or - invm or - rif or - matchval or - match) - begin : fsm_proc - case (fsm) - FSM_IDLE : - begin - if (lcnt[2:0] == 3'b101 & (ncnt[0])) - begin - if (pr) - begin - fsm_c <= FSM_MATCH ; - end - else if (ho | (hp & (dest[0]))) - begin - fsm_c <= FSM_HASH ; - end - else if (!hp) - begin - fsm_c <= FSM_PERF16 ; - end - else - begin - fsm_c <= FSM_PERF1 ; - end - end - else - begin - fsm_c <= FSM_IDLE ; - end - end - FSM_PERF1 : - begin - if (fa == 6'b101100) - begin - if(perfm | - (matchval & match)) - begin - fsm_c <= FSM_MATCH ; - end - else - begin - fsm_c <= FSM_FAIL ; - end - end - else - begin - fsm_c <= FSM_PERF1 ; - end - end - FSM_PERF16 : - begin - if ((flcnt == 3'b010 & perfm & !rif) | - (fa == 6'b110010 & rif & invm) | - (matchval & match)) - begin - fsm_c <= FSM_MATCH ; - end - else if (fa == 6'b110010) - begin - fsm_c <= FSM_FAIL ; - end - else - begin - fsm_c <= FSM_PERF16 ; - end - end - FSM_HASH : - begin - if (matchval & match) - begin - fsm_c <= FSM_MATCH ; - end - else if (flcnt == 3'b101) - begin - if (hash) - begin - fsm_c <= FSM_MATCH ; - end - else - begin - fsm_c <= FSM_FAIL ; - end - end - else - begin - fsm_c <= FSM_HASH ; - end - end - FSM_MATCH : - begin - if (rsm == RSM_IDLE_RCSMT) - begin - fsm_c <= FSM_IDLE ; - end - else - begin - fsm_c <= FSM_MATCH ; - end - end - default : - begin - if (rsm == RSM_IDLE_RCSMT) - begin - fsm_c <= FSM_IDLE ; - end - else - begin - fsm_c <= FSM_FAIL ; - end - end - endcase - end - - always @(posedge clk) - begin : fsm_reg_proc - if (rst) - begin - fsm <= FSM_IDLE ; - end - else - begin - fsm <= fsm_c ; - end - end - - assign bcnt20 = bcnt[2:0] ; - - always @(posedge clk) - begin : dest_reg_proc - if (rst) - begin - dest <= {48{1'b0}} ; - end - else - begin - if (rsm == RSM_DEST) - begin - if (!(ncnt[0])) - begin - case (bcnt20) - 3'b101 : - begin - dest[3:0] <= rxd_r_max[MIIWIDTH-1:0] ; - end - 3'b100 : - begin - dest[11:8] <= rxd_r_max[MIIWIDTH-1:0] ; - end - 3'b011 : - begin - dest[19:16] <= rxd_r_max[MIIWIDTH-1:0] ; - end - 3'b010 : - begin - dest[27:24] <= rxd_r_max[MIIWIDTH-1:0] ; - end - 3'b001 : - begin - dest[35:32] <= rxd_r_max[MIIWIDTH-1:0] ; - end - default : - begin - dest[43:40] <= rxd_r_max[MIIWIDTH-1:0] ; - end - endcase - end - else - begin - case (bcnt20) - 3'b101 : - begin - dest[7:4] <= rxd_r_max[MIIWIDTH-1:0] ; - end - 3'b100 : - begin - dest[15:12] <= rxd_r_max[MIIWIDTH-1:0] ; - end - 3'b011 : - begin - dest[23:20] <= rxd_r_max[MIIWIDTH-1:0] ; - end - 3'b010 : - begin - dest[31:28] <= rxd_r_max[MIIWIDTH-1:0] ; - end - 3'b001 : - begin - dest[39:36] <= rxd_r_max[MIIWIDTH-1:0] ; - end - default : - begin - dest[47:44] <= rxd_r_max[MIIWIDTH-1:0] ; - end - endcase - end - end - end - end - - always @(posedge clk) - begin : hash_reg_proc - if (rst) - begin - crchash <= {9{1'b0}} ; - hash <= 1'b0 ; - fdata_r <= {16{1'b0}} ; - end - else - begin - if (fsm == FSM_HASH & flcnt == 3'b000) - begin - crchash <= {crc[23], crc[24], crc[25], crc[26], - crc[27], crc[28], crc[29], crc[30], crc[31]} ; - end - - hash <= fdata_r[crchash[3:0]] ; - - fdata_r <= fdata ; - end - end - - always @(perfm or flcnt or fsm or fdata_r or dest) - begin : perfm_proc - if ((flcnt == 3'b001 & fdata_r != dest[47:32]) | - (flcnt == 3'b000 & fdata_r != dest[31:16]) | - (flcnt == 3'b010 & fdata_r != dest[15:0]) | fsm == FSM_IDLE) - begin - perfm_c <= 1'b0 ; - end - else if (flcnt == 3'b010 & fdata_r == dest[15:0]) - begin - perfm_c <= 1'b1 ; - end - else - begin - perfm_c <= perfm ; - end - end - - always @(posedge clk) - begin : perfm_reg_proc - if (rst) - begin - invm <= 1'b0 ; - perfm <= 1'b0 ; - end - else - begin - perfm <= perfm_c ; - - if (fsm == FSM_IDLE) - begin - invm <= 1'b1 ; - end - else if (flcnt == 3'b001 & perfm_c) - begin - invm <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : fa_reg_proc - if (rst) - begin - flcnt <= {3{1'b0}} ; - fa <= {ADDRDEPTH{1'b0}} ; - end - else - begin - case (fsm) - FSM_PERF1, FSM_PERF16 : - begin - fa <= fa + 1 ; - end - FSM_HASH : - begin - fa[5:0] <= {1'b0, crchash[8:4]} ; - end - default : - begin - if (hp & !(dest[0])) - begin - fa <= PERF1_ADDR ; - end - else - begin - fa <= {ADDRDEPTH{1'b0}} ; - end - end - endcase - - if (fsm_c == FSM_IDLE | - (flcnt == 3'b010 & fsm_c == FSM_PERF16) | - (flcnt == 3'b010 & fsm_c == FSM_PERF1)) - begin - flcnt <= {3{1'b0}} ; - end - else if (fsm == FSM_PERF1 | - fsm == FSM_PERF16 | - fsm == FSM_HASH) - begin - flcnt <= flcnt + 1 ; - end - end - end - - assign faddr = fa ; - - assign matchdata = dest ; - - always @(posedge clk) - begin : matchen_reg_proc - if (rst) - begin - matchen <= 1'b0 ; - end - else - begin - if (fsm == FSM_PERF1 | fsm == FSM_HASH | fsm == FSM_PERF16) - begin - matchen <= 1'b1 ; - end - else - begin - matchen <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : stop_reg_proc - if (rst) - begin - stop_r <= 1'b0 ; - stopo <= 1'b0 ; - end - else - begin - stop_r <= stopi ; - - if (stop_r & rsm == RSM_IDLE_RCSMT) - begin - stopo <= 1'b1 ; - end - else - begin - stopo <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : rcscnt_reg_proc - if (rst) - begin - rcscnt <= {8{1'b0}} ; - rcs <= 1'b0 ; - rcsreq <= 1'b0 ; - rcsack_r <= 1'b0 ; - end - else - begin - if (rcscnt == 8'b00000000) - begin - rcscnt <= 8'b10000000 ; - end - else - begin - rcscnt <= rcscnt - 1 ; - end - - if (rcscnt == 8'b00000000) - begin - rcs <= 1'b1 ; - end - else if (rcsack_r) - begin - rcs <= 1'b0 ; - end - - if (rcs & !rcsack_r) - begin - rcsreq <= 1'b1 ; - end - else if (rcsack_r) - begin - rcsreq <= 1'b0 ; - end - - rcsack_r <= rcsack ; - end - end - - always @(posedge clk) - begin : focnt_reg_proc - if (rst) - begin - focnt <= {11{1'b0}} ; - oco <= 1'b0 ; - focl_r <= 1'b0 ; - focg <= {11{1'b0}} ; - end - else - begin - if (focl_r) - begin - focnt <= {11{1'b0}} ; - end - else if ((rsm == RSM_DEST | - rsm == RSM_SOURCE | - rsm == RSM_LENGTH | - rsm == RSM_INFO | - rsm == RSM_SFD) & - full) - begin - focnt <= focnt + 1 ; - end - - if (focl_r) - begin - oco <= 1'b0 ; - end - else if ((rsm == RSM_DEST | - rsm == RSM_SOURCE | - rsm == RSM_LENGTH | - rsm == RSM_INFO) & - focnt == 11'b11111111111 & - (full | !cachenf_r)) - begin - oco <= 1'b1 ; - end - - focl_r <= focl ; - - focg[10] <= focnt[10] ; - begin : focg_loop - integer i; - for(i = 9; i >= 0; i = i - 1) - begin - focg[i] <= focnt[i] ^ focnt[i + 1] ; - end - end - end - end - - assign foclack = focl_r ; - - always @(posedge clk) - begin : mfcnt_reg_proc - if (rst) - begin - mfcnt <= {16{1'b0}} ; - mfo <= 1'b0 ; - mfcl_r <= 1'b0 ; - mfcg <= {16{1'b0}} ; - end - else - begin - if (mfcl_r) - begin - mfcnt <= {16{1'b0}} ; - end - else if ( - eorfff && - (pb | winp) && - ( - fsm==FSM_MATCH | ra | - ( - pm && dest[0] - ) - ) - ) - begin - mfcnt <= mfcnt + 1'b1 ; - end - - if (mfcl_r) - begin - mfo <= 1'b0 ; - end - else if ( - mfcnt=={16{1'b1}} && pb && - ( - fsm==FSM_MATCH | ra | - ( - pm && dest[0] - ) - ) - ) - begin - mfo <= 1'b1 ; - end - - mfcl_r <= mfcl; - - begin : mfcg_reg_write - integer i; - mfcg[15] <= mfcnt[15]; - for(i = 14; i >= 0; i = i - 1) - begin - mfcg[i] <= mfcnt[i] ^ mfcnt[i + 1]; - end - end - end - end - - assign mfclack = mfcl_r ; - - assign fzero = {FIFODEPTH{1'b0}} ; - - assign mzero_max = {(MIIWIDTH_MAX + 1){1'b0}} ; - - assign rxd_r_max = {mzero_max[MIIWIDTH_MAX + 1:MIIWIDTH], - rxd_r}; - -endmodule diff --git a/resources/soc/rtl/MAC/rfifo.v b/resources/soc/rtl/MAC/rfifo.v deleted file mode 100644 index 631c9c2..0000000 --- a/resources/soc/rtl/MAC/rfifo.v +++ /dev/null @@ -1,439 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -module RFIFO ( - clk, - rst, - ramdata, - ramaddr, - fifore, - ffo, - rfo, - mfo, - tlo, - reo, - dbo, - ceo, - ovo, - cso, - flo, - fifodata, - cachere, - cachene, - cachenf, - radg, - rireq, - ffi, - rfi, - mfi, - tli, - rei, - dbi, - cei, - ovi, - csi, - fli, - wadg, - riack - ); - - parameter DATAWIDTH = 32; - parameter DATADEPTH = 32; - parameter FIFODEPTH = 9; - parameter CACHEDEPTH = 2; - - input clk; - input rst; - - input [DATAWIDTH - 1:0] ramdata; - output [FIFODEPTH - 1:0] ramaddr; - wire [FIFODEPTH - 1:0] ramaddr; - - input fifore; - output ffo; - wire ffo; - output rfo; - wire rfo; - output mfo; - wire mfo; - output tlo; - wire tlo; - output reo; - wire reo; - output dbo; - wire dbo; - output ceo; - wire ceo; - output ovo; - wire ovo; - output cso; - wire cso; - output [13:0] flo; - wire [13:0] flo; - output [DATAWIDTH - 1:0] fifodata; - wire [DATAWIDTH - 1:0] fifodata; - - input cachere; - output cachene; - wire cachene; - - output cachenf; - wire cachenf; - output [FIFODEPTH - 1:0] radg; - reg [FIFODEPTH - 1:0] radg; - - input rireq; - input ffi; - input rfi; - input mfi; - input tli; - input rei; - input dbi; - input cei; - input ovi; - input csi; - input [13:0] fli; - input [FIFODEPTH - 1:0] wadg; - output riack; - wire riack; - - - parameter CSWIDTH = 23; - reg [CSWIDTH - 1:0] csmem[(1'b1 << CACHEDEPTH) - 1:0]; - wire cswe; - wire csre; - reg csnf; - reg csne; - reg [CACHEDEPTH - 1:0] cswad; - reg [CACHEDEPTH - 1:0] cswadi; - reg [CACHEDEPTH - 1:0] csrad; - reg [CACHEDEPTH - 1:0] csrad_r; - wire [CSWIDTH - 1:0] csdi; - wire [CSWIDTH - 1:0] csdo; - - reg [FIFODEPTH - 1:0] stat; - reg [FIFODEPTH - 1:0] rad_c; - reg [FIFODEPTH - 1:0] rad; - reg [FIFODEPTH - 1:0] wad_c; - reg [FIFODEPTH - 1:0] wad; - reg [FIFODEPTH - 1:0] wadg_0_r; - reg [FIFODEPTH - 1:0] wadg_r; - reg [13:0] flibin_c; - reg [13:0] flibin; - reg [13:0] fli_r; - - reg rireq_r; - reg iriack; - - wire [FIFODEPTH - 1:0] fzero; - - always @(posedge clk) - begin : csmem_reg_proc - if (rst) - begin : csmem_reset - integer i; - for(i = ((1'b1 << CACHEDEPTH) - 1); i >= 0; i = i - 1) - begin - csmem[i] <= {CSWIDTH{1'b0}}; - end - csrad_r <= csrad ; - end - else - begin - csmem[cswad] <= csdi ; - csrad_r <= csrad ; - end - end - - always @(posedge clk) - begin : cswad_reg_proc - if (rst) - begin - cswad <= {CACHEDEPTH{1'b1}} ; - end - else - begin - if (cswe) - begin - cswad <= cswad + 1 ; - end - end - end - - always @(posedge clk) - begin : csrad_reg_proc - if (rst) - begin - csrad <= {CACHEDEPTH{1'b1}} ; - end - else - begin - if (csre) - begin - csrad <= csrad + 1 ; - end - end - end - - always @(posedge clk) - begin : csne_reg_proc - if (rst) - begin - csne <= 1'b0 ; - end - else - begin - if (cswad == csrad) - begin - csne <= 1'b0 ; - end - else - begin - csne <= 1'b1 ; - end - end - end - - always @(cswad) - begin : cswadi_drv - cswadi <= cswad + 1; - end - - always @(posedge clk) - begin : csnf_reg_proc - if (rst) - begin - csnf <= 1'b0 ; - end - else - begin - if (cswadi == csrad) - begin - csnf <= 1'b0 ; - end - else - begin - csnf <= 1'b1 ; - end - end - end - - always @(fli_r) - begin : flibin_proc - reg[13:0] flibin_v; - flibin_v[13] = fli_r[13]; - begin : flibin_loop - integer i; - for(i = 12; i >= 0; i = i - 1) - begin - flibin_v[i] = flibin_v[i + 1] ^ fli_r[i]; - end - end - flibin_c = flibin_v ; - end - - always @(posedge clk) - begin : flibin_reg_proc - if (rst) - begin - flibin <= {14{1'b0}} ; - fli_r <= {14{1'b0}} ; - end - else - begin - flibin <= flibin_c ; - fli_r <= fli ; - end - end - - assign cachene = csne ; - - assign cachenf = csnf ; - - assign cswe = rireq_r & ~iriack ; - - assign csdo = csmem[csrad_r] ; - - assign csdi = {ffi, rfi, mfi, tli, rei, dbi, cei, ovi, csi, flibin} ; - - assign ffo = csdo[CSWIDTH - 1] ; - - assign rfo = csdo[CSWIDTH - 2] ; - - assign mfo = csdo[CSWIDTH - 3] ; - - assign tlo = csdo[CSWIDTH - 4] ; - - assign reo = csdo[CSWIDTH - 5] ; - - assign dbo = csdo[CSWIDTH - 6] ; - - assign ceo = csdo[CSWIDTH - 7] ; - - assign ovo = csdo[CSWIDTH - 8] ; - - assign cso = csdo[CSWIDTH - 9]; - - assign flo = csdo[13:0] ; - - assign csre = cachere ; - - always @(posedge clk) - begin : rireq_reg_proc - if (rst) - begin - rireq_r <= 1'b0 ; - end - else - begin - rireq_r <= rireq ; - end - end - - always @(posedge clk) - begin : irecack_reg_proc - if (rst) - begin - iriack <= 1'b0 ; - end - else - begin - iriack <= rireq_r ; - end - end - - assign riack = iriack ; - - always @(rad or fifore) - begin : rad_proc - if (fifore) - begin - rad_c <= rad + 1 ; - end - else - begin - rad_c <= rad ; - end - end - - always @(posedge clk) - begin : rad_reg_proc - if (rst) - begin - rad <= {FIFODEPTH{1'b0}} ; - end - else - begin - rad <= rad_c ; - end - end - - always @(posedge clk) - begin : radg_reg_proc - if (rst) - begin - radg <= {FIFODEPTH{1'b0}} ; - end - else - begin - radg[FIFODEPTH - 1] <= rad[FIFODEPTH - 1] ; - begin : radg_loop - integer i; - for(i = FIFODEPTH - 2; i >= 0; i = i - 1) - begin - radg[i] <= rad[i] ^ rad[i + 1] ; - end - end - end - end - - always @(posedge clk) - begin : wadg_reg_proc - if (rst) - begin - wadg_0_r <= {FIFODEPTH{1'b0}} ; - wadg_r <= {FIFODEPTH{1'b0}} ; - end - else - begin - wadg_0_r <= wadg; - wadg_r <= wadg_0_r; - end - end - - always @(wadg_r) - begin : wad_proc - reg[FIFODEPTH - 1:0] wad_v; - wad_v[FIFODEPTH - 1] = wadg_r[FIFODEPTH - 1]; - begin : wad_loop - integer i; - for(i = FIFODEPTH - 2; i >= 0; i = i - 1) - begin - wad_v[i] = wad_v[i + 1] ^ wadg_r[i]; - end - end - wad_c = wad_v ; - end - - always @(posedge clk) - begin : ad_reg_proc - if (rst) - begin - wad <= {FIFODEPTH{1'b0}} ; - end - else - begin - wad <= wad_c ; - end - end - - always @(posedge clk) - begin : stat_reg_proc - if (rst) - begin - stat <= {FIFODEPTH{1'b0}} ; - end - else - begin - stat <= wad - rad ; - end - end - - assign ramaddr = rad_c ; - - assign fifodata = ramdata ; - - - assign fzero = {FIFODEPTH{1'b0}}; - -endmodule diff --git a/resources/soc/rtl/MAC/rlsm.v b/resources/soc/rtl/MAC/rlsm.v deleted file mode 100644 index 72bad4d..0000000 --- a/resources/soc/rtl/MAC/rlsm.v +++ /dev/null @@ -1,1328 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -module RLSM ( - clk, - rst, - fifodata, - fifore, - cachere, - dmaack, - dmaeob, - dmadatai, - dmaaddr, - dmareq, - dmawr, - dmacnt, - dmaaddro, - dmadatao, - rprog, - rcpoll, - fifocne, - ff, - rf, - mf, - db, - re, - ce, - tl, - ftp, - ov, - cs, - length, - pbl, - dsl, - rpoll, - rdbadc, - rdbad, - rpollack, - rcompack, - bufack, - des, - fbuf, - stat, - ru, - rcomp, - bufcomp, - stopi, - stopo, - insert_en_i - ); - - parameter DATAWIDTH = 32; - parameter DATADEPTH = 32; - parameter FIFODEPTH = 9; - - `include "utility.v" - - input clk; - input rst; - - input [DATAWIDTH - 1:0] fifodata; - output fifore; - wire fifore; - output cachere; - wire cachere; - - input dmaack; - input dmaeob; - input [DATAWIDTH - 1:0] dmadatai; - input [DATADEPTH - 1:0] dmaaddr; - output dmareq; - wire dmareq; - output dmawr; - wire dmawr; - output [FIFODEPTH_MAX - 1:0] dmacnt; - reg [FIFODEPTH_MAX - 1:0] dmacnt; - output [DATADEPTH - 1:0] dmaaddro; - reg [DATADEPTH - 1:0] dmaaddro; - output [DATAWIDTH - 1:0] dmadatao; - reg [DATAWIDTH - 1:0] dmadatao; - - input rprog; - input rcpoll; - input fifocne; - input ff; - input rf; - input mf; - input db; - input re; - input ce; - input tl; - input ftp; - input ov; - input cs; - input [13:0] length; - - input [5:0] pbl; - input [4:0] dsl; - input rpoll; - input rdbadc; - input [DATADEPTH - 1:0] rdbad; - output rpollack; - reg rpollack; - - input rcompack; - input bufack; - output des; - reg des; - output fbuf; - reg fbuf; - output stat; - reg stat; - output ru; - reg ru; - output rcomp; - reg rcomp; - output bufcomp; - reg bufcomp; - - input stopi; - output stopo; - reg stopo; - - input insert_en_i; - - - - reg [3:0] lsm_c; - reg [3:0] lsm; - reg [3:0] lsm_r; - reg own_c; - reg own; - reg rch; - reg rer; - reg rls; - reg rfs; - reg rde; - wire res_c; - reg [10:0] bs1; - reg [10:0] bs2; - - reg adwrite; - reg [DATADEPTH - 1:0] bad; - reg [DATADEPTH - 1:0] dad; - reg [10:0] bcnt; - reg [DATADEPTH - 1:0] statad; - reg [DATADEPTH - 1:0] tstatad; - reg dbadc_r; - - reg req_c; - reg req; - wire [2:0] dmaaddr20; - wire [1:0] addr10; - reg [DATADEPTH_MAX - 1:0] dataimax_r; - wire [31:0] fstat; - - reg rprog_r; - reg rcpoll_r; - reg rcpoll_r2; - reg whole; - - reg [13:0] fifolev_r; - reg [13:0] fbcnt; - reg [13:0] fbcnt_c; - reg [13:0] length_r; - wire ififore; - reg ififore_r; - reg icachere; - wire [FIFODEPTH_MAX - 1:0] bsmax; - wire [FIFODEPTH_MAX - 1:0] flmax; - wire [FIFODEPTH_MAX - 1:0] blmax; - reg fl_g_16; - reg fl_g_bs; - reg fl_g_bl; - reg bl_g_bs; - reg pblz; - - reg stop_r; - - wire [FIFODEPTH_MAX - 1:0] fzero_max; - wire [DATAWIDTH_MAX + 1:0] dmadatai_max; - wire [DATAWIDTH_MAX + 1:0] dzero_max; - - always @(posedge clk) - begin : dataimax_reg_proc - if (rst) - begin - dataimax_r <= {DATADEPTH_MAX{1'b1}} ; - end - else - begin - case (DATAWIDTH) - 8 : - begin - case (dmaaddr20) - 3'b000, 3'b100 : - begin - dataimax_r[7:0] <= dmadatai_max[DATAWIDTH-1:0] ; - end - 3'b001, 3'b101 : - begin - dataimax_r[15:8] <= dmadatai_max[DATAWIDTH-1:0] ; - end - 3'b010, 3'b110 : - begin - dataimax_r[23:16] <= dmadatai_max[DATAWIDTH-1:0] ; - end - default : - begin - dataimax_r[31:24] <= dmadatai_max[DATAWIDTH-1:0] ; - end - endcase - end - 16 : - begin - if (!(dmaaddr[1])) - begin - dataimax_r[15:0] <= dmadatai_max[DATAWIDTH-1:0] ; - end - else - begin - dataimax_r[31:16] <= dmadatai_max[DATAWIDTH-1:0] ; - end - end - default : - begin - dataimax_r <= dmadatai_max[31:0] ; - end - endcase - end - end - - always @(posedge clk) - begin : fifolev_reg_proc - if (rst) - begin - length_r <= {14{1'b0}} ; - fifolev_r <= {14{1'b0}} ; - fl_g_bs <= 1'b0 ; - fl_g_16 <= 1'b0 ; - fl_g_bl <= 1'b0 ; - bl_g_bs <= 1'b0 ; - pblz <= 1'b0 ; - end - else - begin - length_r <= length; - - fifolev_r <= length_r - fbcnt_c ; - - if (flmax >= bsmax) - begin - fl_g_bs <= 1'b1 ; - end - else - begin - fl_g_bs <= 1'b0 ; - end - - case (DATAWIDTH) - 8 : - begin - if (flmax > ({fzero_max[FIFODEPTH_MAX - 1:6], - 6'b111111})) - begin - fl_g_16 <= 1'b1 ; - end - else - begin - fl_g_16 <= 1'b0 ; - end - end - 16 : - begin - if (flmax > ({fzero_max[FIFODEPTH_MAX - 1:5], - 5'b11111})) - begin - fl_g_16 <= 1'b1 ; - end - else - begin - fl_g_16 <= 1'b0 ; - end - end - default : - begin - if (flmax > ({fzero_max[FIFODEPTH_MAX - 1:4], - 4'b1111})) - begin - fl_g_16 <= 1'b1 ; - end - else - begin - fl_g_16 <= 1'b0 ; - end - end - endcase - - if (flmax >= (blmax + 1'b1)) - begin - fl_g_bl <= 1'b1 ; - end - else - begin - fl_g_bl <= 1'b0 ; - end - - if (blmax >= bsmax) - begin - bl_g_bs <= 1'b1 ; - end - else - begin - bl_g_bs <= 1'b0 ; - end - - if (pbl == 6'b000000) - begin - pblz <= 1'b1 ; - end - else - begin - pblz <= 1'b0 ; - end - end - end - - assign flmax = (DATAWIDTH == 8) ? {fzero_max[FIFODEPTH_MAX - 1:14], - fifolev_r} : - (DATAWIDTH == 16) ? {fzero_max[FIFODEPTH_MAX - 1:13], - fifolev_r[13:1]} : - {fzero_max[FIFODEPTH_MAX - 1:12], - fifolev_r[13:2]} ; - - assign blmax = {fzero_max[FIFODEPTH_MAX - 1:6], pbl} ; - - assign bsmax = (DATAWIDTH == 8) ? {fzero_max[FIFODEPTH_MAX - 1:11], - bcnt} : - (DATAWIDTH == 16) ? {fzero_max[FIFODEPTH_MAX - 1:10], - bcnt[10:1]} : - {fzero_max[FIFODEPTH_MAX - 1:9], - bcnt[10:2]} ; - - always @(lsm or - fl_g_bs or - fl_g_bl or - bl_g_bs or - pblz or - blmax or - bsmax or - flmax or - fzero_max) - begin : dmacnt_proc - if (lsm == LSM_DES0 | - lsm == LSM_DES1 | - lsm == LSM_DES2 | - lsm == LSM_DES3 | - lsm == LSM_STAT | - lsm == LSM_FSTAT | - lsm == LSM_DES0P) - begin - case (DATAWIDTH) - 8 : - begin - dmacnt <= {fzero_max[FIFODEPTH_MAX - 1:3], 3'b100} ; - end - 16 : - begin - dmacnt <= {fzero_max[FIFODEPTH_MAX - 1:3], 3'b010} ; - end - default : - begin - dmacnt <= {fzero_max[FIFODEPTH_MAX - 1:3], 3'b001} ; - end - endcase - end - else - begin - if (pblz) - begin - if (fl_g_bs) - begin - dmacnt <= bsmax ; - end - else - begin - dmacnt <= flmax ; - end - end - else - begin - if (fl_g_bl) - begin - if (bl_g_bs) - begin - dmacnt <= bsmax ; - end - else - begin - dmacnt <= blmax ; - end - end - else - begin - if (fl_g_bs) - begin - dmacnt <= bsmax ; - end - else - begin - dmacnt <= flmax ; - end - end - end - end - end - - always @(req or - lsm or - lsm_c or - fifocne or - fl_g_bl or - fl_g_16 or - pblz or - whole or - rprog_r or - dmaack or - dmaeob or - flmax or - fzero_max) - begin : req_proc - case (lsm) - LSM_BUF1, LSM_BUF2 : - begin - if ((dmaack & dmaeob) | lsm_c==LSM_NXT) - begin - req_c <= 1'b0 ; - end - else if (fifocne | (rprog_r & ((fl_g_bl & !pblz) | - (fl_g_16 & pblz)))) - begin - req_c <= 1'b1 ; - end - else - begin - req_c <= req ; - end - end - LSM_DES0, LSM_DES1, LSM_DES2, - LSM_DES3, LSM_STAT, LSM_DES0P : - begin - if (dmaack) - begin - req_c <= 1'b0 ; - end - else - begin - req_c <= 1'b1 ; - end - end - LSM_FSTAT : - begin - if (dmaack | !whole | - (DATAWIDTH == 8 & flmax[1:0] != fzero_max[1:0]) - | - (DATAWIDTH == 16 & flmax[ 1] != fzero_max[1])) - begin - req_c <= 1'b0 ; - end - else - begin - req_c <= 1'b1 ; - end - end - default : - begin - req_c <= 1'b0 ; - end - endcase - end - - always @(posedge clk) - begin : req_reg_proc - if (rst) - begin - req <= 1'b0 ; - end - else - begin - req <= req_c ; - end - end - - always @(lsm or bad or dad or statad) - begin : dmaaddro_proc - case (lsm) - LSM_BUF1, LSM_BUF2 : - begin - dmaaddro <= bad ; - end - LSM_STAT, LSM_FSTAT : - begin - dmaaddro <= statad ; - end - default : - begin - dmaaddro <= dad ; - end - endcase - end - - wire [13:0] real_length; - assign real_length = (insert_en_i) ? (length - 2'b10) : length; - - assign fstat = {1'b0, ff, real_length, res_c, rde, - RDES0_RV[13:12], rf, mf, rfs, rls, tl, - cs, ftp, RDES0_RV[4], re, db, ce, ov} ; - - assign dmawr = (lsm == LSM_STAT | - lsm == LSM_FSTAT | - lsm == LSM_BUF1 | - lsm == LSM_BUF2) ? 1'b1 : 1'b0 ; - - always @(fifodata or lsm or addr10 or fstat) - begin : dmadatao_proc - if (lsm == LSM_BUF1 | lsm == LSM_BUF2) - begin - dmadatao <= fifodata ; - end - else - begin - case (DATAWIDTH) - 8 : - begin - case (addr10) - 2'b00 : - begin - dmadatao <= fstat[7:0] ; - end - 2'b01 : - begin - dmadatao <= fstat[15:8] ; - end - 2'b10 : - begin - dmadatao <= fstat[23:16] ; - end - default : - begin - dmadatao <= fstat[31:24] ; - end - endcase - end - 16 : - begin - if (addr10 == 2'b00) - begin - dmadatao <= fstat[15:0] ; - end - else - begin - dmadatao <= fstat[31:16] ; - end - end - default : - begin - dmadatao <= fstat ; - end - endcase - end - end - - assign dmareq = req ; - - always @(lsm or - rcpoll_r or - rcpoll_r2 or - rpoll or - dmaack or - dmaeob or - own_c or - bs1 or - bs2 or - whole or - rch or - stop_r or - own or - bcnt or - dbadc_r) - begin : lsm_proc - case (lsm) - LSM_IDLE : - begin - if (!dbadc_r & !stop_r & ((rcpoll_r & !rcpoll_r2) | rpoll)) - begin - lsm_c <= LSM_DES0 ; - end - else - begin - lsm_c <= LSM_IDLE ; - end - end - LSM_DES0 : - begin - if (dmaack & dmaeob) - begin - if (own_c) - begin - lsm_c <= LSM_DES1 ; - end - else - begin - lsm_c <= LSM_IDLE ; - end - end - else - begin - lsm_c <= LSM_DES0 ; - end - end - LSM_DES0P : - begin - if (dmaack & dmaeob) - begin - if (!own_c | whole) - begin - lsm_c <= LSM_FSTAT ; - end - else - begin - lsm_c <= LSM_STAT ; - end - end - else - begin - lsm_c <= LSM_DES0P ; - end - end - LSM_DES1 : - begin - if (dmaack & dmaeob) - begin - lsm_c <= LSM_DES2 ; - end - else - begin - lsm_c <= LSM_DES1 ; - end - end - LSM_DES2 : - begin - if (dmaack & dmaeob) - begin - if (bs1 == 11'b00000000000) - begin - lsm_c <= LSM_DES3 ; - end - else - begin - lsm_c <= LSM_BUF1 ; - end - end - else - begin - lsm_c <= LSM_DES2 ; - end - end - LSM_DES3 : - begin - if (dmaack & dmaeob) - begin - if (bs2 != 11'b00000000000 & !rch) - begin - lsm_c <= LSM_BUF2 ; - end - else - begin - lsm_c <= LSM_NXT ; - end - end - else - begin - lsm_c <= LSM_DES3 ; - end - end - LSM_BUF1 : - begin - if (whole | bcnt == 11'b00000000000) - begin - lsm_c <= LSM_DES3 ; - end - else if(dbadc_r) - begin - lsm_c <= LSM_IDLE ; - end - else - begin - lsm_c <= LSM_BUF1 ; - end - end - LSM_BUF2 : - begin - if (whole | bcnt == 11'b00000000000) - begin - lsm_c <= LSM_NXT ; - end - else if(dbadc_r) - begin - lsm_c <= LSM_IDLE ; - end - else - begin - lsm_c <= LSM_BUF2 ; - end - end - LSM_NXT : - begin - if (whole) - begin - if (stop_r) - begin - lsm_c <= LSM_FSTAT ; - end - else - begin - lsm_c <= LSM_DES0P ; - end - end - else - begin - lsm_c <= LSM_DES0P ; - end - end - LSM_STAT : - begin - if (dmaack & dmaeob) - begin - lsm_c <= LSM_DES1 ; - end - else - begin - lsm_c <= LSM_STAT ; - end - end - default : - begin - if (dmaack & dmaeob) - begin - if (own & !stop_r) - begin - lsm_c <= LSM_DES1 ; - end - else - begin - lsm_c <= LSM_IDLE ; - end - end - else - begin - lsm_c <= LSM_FSTAT ; - end - end - endcase - end - - always @(posedge clk) - begin : rlsm_reg_proc - if (rst) - begin - lsm <= LSM_IDLE ; - lsm_r <= LSM_IDLE ; - end - else - begin - lsm <= lsm_c ; - lsm_r <= lsm ; - end - end - - always @(posedge clk) - begin : rpollack_reg_proc - if (rst) - begin - rpollack <= 1'b0 ; - end - else - begin - if (rpoll & !dbadc_r) - begin - rpollack <= 1'b1 ; - end - else if (!rpoll) - begin - rpollack <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : bcnt_reg_proc - if (rst) - begin - bcnt <= {11{1'b1}} ; - end - else - begin - if (lsm == LSM_DES2) - begin - bcnt <= bs1 ; - end - else if (lsm == LSM_DES3) - begin - bcnt <= bs2 ; - end - else - begin - if (dmaack) - begin - case (DATAWIDTH) - 8 : - begin - bcnt <= bcnt - 1 ; - end - 16 : - begin - bcnt <= {(bcnt[10:1] - 1), 1'b0} ; - end - default : - begin - bcnt <= {(bcnt[10:2] - 1), 2'b00} ; - end - endcase - end - end - end - end - - always @(own or - dmaack or - dmaeob or - lsm or - dmadatai_max) - begin : own_proc - if (dmaack & dmaeob & (lsm == LSM_DES0 | lsm == LSM_DES0P)) - begin - own_c <= dmadatai_max[DATAWIDTH - 1] ; - end - else - begin - own_c <= own ; - end - end - - always @(posedge clk) - begin : des1_reg_proc - reg ft22; - if (rst) - begin - rer <= 1'b0 ; - rch <= 1'b0 ; - bs2 <= {11{1'b0}} ; - bs1 <= {11{1'b0}} ; - end - else - begin - if (lsm == LSM_DES1 & dmaack) - begin - case (DATAWIDTH) - 8 : - begin - case (dmaaddr20) - 3'b000, 3'b100 : - begin - bs1[7:0] <= dmadatai_max[7:0] ; - end - 3'b001, 3'b101 : - begin - bs1[10:8] <= dmadatai_max[2:0] ; - bs2[4:0] <= dmadatai_max[7:3] ; - end - 3'b010, 3'b110 : - begin - bs2[10:5] <= dmadatai_max[5:0] ; - end - default : - begin - rer <= dmadatai_max[1] ; - rch <= dmadatai_max[0] ; - end - endcase - end - 16 : - begin - case (dmaaddr20) - 3'b000, 3'b100 : - begin - bs1[10:0] <= dmadatai_max[10:0] ; - bs2[4:0] <= dmadatai_max[15:11] ; - end - default : - begin - bs2[10:5] <= dmadatai_max[5:0] ; - rer <= dmadatai_max[9] ; - rch <= dmadatai_max[8] ; - end - endcase - end - default : - begin - rer <= dmadatai_max[25] ; - rch <= dmadatai_max[24] ; - bs2 <= dmadatai_max[21:11] ; - bs1 <= dmadatai_max[10:0] ; - end - endcase - end - end - end - - always @(posedge clk) - begin : rdes_reg_proc - if (rst) - begin - own <= 1'b0 ; - rfs <= 1'b1 ; - rls <= 1'b0 ; - rde <= 1'b0 ; - end - else - begin - if (lsm == LSM_FSTAT & dmaack & dmaeob) - begin - rfs <= 1'b1 ; - end - else if (lsm == LSM_STAT & dmaack & dmaeob) - begin - rfs <= 1'b0 ; - end - - if (lsm == LSM_FSTAT) - begin - rls <= 1'b1 ; - end - else - begin - rls <= 1'b0 ; - end - - if (lsm == LSM_FSTAT & !whole) - begin - rde <= 1'b1 ; - end - else if (lsm == LSM_IDLE) - begin - rde <= 1'b0 ; - end - - own <= own_c ; - end - end - - assign res_c = rf | ce | rde | cs | tl ; - - always @(posedge clk) - begin : adwrite_reg_proc - if (rst) - begin - adwrite <= 1'b0 ; - dbadc_r <= 1'b0 ; - end - else - begin - if (dmaack & dmaeob) - begin - adwrite <= 1'b1 ; - end - else - begin - adwrite <= 1'b0 ; - end - - dbadc_r <= rdbadc ; - end - end - - always @(posedge clk) - begin : dad_reg_proc - if (rst) - begin - dad <= {DATADEPTH{1'b1}} ; - end - else - begin - if (dbadc_r) - begin - dad <= rdbad ; - end - else if (adwrite & lsm == LSM_NXT & rch) - begin - dad <= dataimax_r[DATADEPTH - 1:0] ; - end - else if (adwrite) - begin - case (lsm_r) - LSM_DES3 : - begin - if (rer) - begin - dad <= rdbad ; - end - else - begin - dad <= dmaaddr + ({dsl, 2'b00}) ; - end - end - LSM_DES0, LSM_DES0P : - begin - if (own) - begin - dad <= dmaaddr ; - end - end - LSM_DES2 : - begin - dad <= dmaaddr ; - end - LSM_DES1 : - begin - dad <= dmaaddr ; - end - default : - begin - dad <= dad ; - end - endcase - end - end - end - - always @(posedge clk) - begin : bad_reg_proc - if (rst) - begin - bad <= {DATADEPTH{1'b1}} ; - end - else - begin - if (adwrite) - begin - if (lsm_r == LSM_BUF1 | lsm_r == LSM_BUF2) - begin - bad <= dmaaddr ; - end - else - begin - bad <= dataimax_r[DATADEPTH - 1:0] ; - end - end - end - end - - always @(posedge clk) - begin : stataddr_reg_proc - if (rst) - begin - tstatad <= {DATADEPTH{1'b1}} ; - statad <= {DATADEPTH{1'b1}} ; - end - else - begin - if (lsm == LSM_DES1 & adwrite) - begin - statad <= tstatad ; - end - - if ((lsm == LSM_DES0 | lsm == LSM_DES0P) & dmaack & dmaeob) - begin - tstatad <= dad ; - end - end - end - - always @(fbcnt or icachere or ififore) - begin : fbcnt_proc - if (icachere) - begin - fbcnt_c <= {14{1'b0}} ; - end - else - begin - if (ififore) - begin - case (DATAWIDTH) - 8 : - begin - fbcnt_c <= fbcnt + 1 ; - end - 16 : - begin - fbcnt_c <= fbcnt + 2'b10 ; - end - default : - begin - fbcnt_c <= fbcnt + 3'b100 ; - end - endcase - end - else - begin - fbcnt_c <= fbcnt; - end - end - end - - always @(posedge clk) - begin : fbcnt_reg_proc - if(rst) - begin - fbcnt <= {14{1'b0}}; - end - else - begin - fbcnt <= fbcnt_c; - end - end - - always @(fbcnt or length or fifocne) - begin : whole_proc - if (fbcnt >= length & fifocne) - begin - whole <= 1'b1 ; - end - else - begin - whole <= 1'b0 ; - end - end - - assign ififore = (((lsm == LSM_BUF1 | lsm == LSM_BUF2) & dmaack) | - (lsm == LSM_FSTAT & !whole & - flmax != fzero_max[14:0] & !ififore_r) | - (lsm == LSM_FSTAT & !whole & - fifocne & !ififore_r)) ? 1'b1 : 1'b0 ; - - always @(posedge clk) - begin : ififore_reg_proc - if (rst) - begin - ififore_r <= 1'b0 ; - icachere <= 1'b0 ; - end - else - begin - ififore_r <= ififore ; - - if (lsm == LSM_FSTAT & dmaack & dmaeob) - begin - icachere <= 1'b1 ; - end - else - begin - icachere <= 1'b0 ; - end - end - end - - assign fifore = ififore ; - - assign cachere = icachere ; - - always @(posedge clk) - begin : rprog_reg_proc - if (rst) - begin - rprog_r <= 1'b0 ; - rcpoll_r <= 1'b0 ; - rcpoll_r2 <= 1'b0 ; - end - else - begin - rprog_r <= rprog ; - rcpoll_r <= rcpoll ; - if (lsm == LSM_IDLE) - begin - rcpoll_r2 <= rcpoll_r ; - end - end - end - - always @(posedge clk) - begin : stat_reg_drv - if (rst) - begin - des <= 1'b0 ; - fbuf <= 1'b0 ; - stat <= 1'b0 ; - rcomp <= 1'b0 ; - bufcomp <= 1'b0 ; - ru <= 1'b0 ; - end - else - begin - if (lsm == LSM_DES0 | - lsm == LSM_DES1 | - lsm == LSM_DES2 | - lsm == LSM_DES3 | - lsm == LSM_DES0P) - begin - des <= 1'b1 ; - end - else - begin - des <= 1'b0 ; - end - - if ((lsm == LSM_BUF1 | lsm == LSM_BUF2) & req) - begin - fbuf <= 1'b1 ; - end - else - begin - fbuf <= 1'b0 ; - end - - if (lsm == LSM_STAT | lsm == LSM_FSTAT) - begin - stat <= 1'b1 ; - end - else - begin - stat <= 1'b0 ; - end - - if (lsm == LSM_FSTAT & dmaack & dmaeob) - begin - rcomp <= 1'b1 ; - end - else if (rcompack) - begin - rcomp <= 1'b0 ; - end - - if (lsm == LSM_STAT & dmaack & dmaeob) - begin - bufcomp <= 1'b1 ; - end - else if (bufack) - begin - bufcomp <= 1'b0 ; - end - - if (own & !own_c) - begin - ru <= 1'b1 ; - end - else if (own) - begin - ru <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : stop_reg_proc - if (rst) - begin - stop_r <= 1'b1 ; - stopo <= 1'b1 ; - end - else - begin - stop_r <= stopi ; - - if (stop_r & (lsm == LSM_IDLE | - ((lsm == LSM_BUF1 | lsm == LSM_BUF2) & - !fifocne & !rprog_r))) - begin - stopo <= 1'b1 ; - end - else - begin - stopo <= 1'b0 ; - end - end - end - - assign dzero_max = {DATAWIDTH_MAX{1'b0}} ; - - assign fzero_max = {FIFODEPTH_MAX{1'b0}} ; - - assign dmadatai_max = {dzero_max[DATAWIDTH_MAX+1:DATAWIDTH], - dmadatai}; - - assign dmaaddr20 = dmaaddr[2:0] ; - - assign addr10 = dmaaddr[1:0] ; - -endmodule diff --git a/resources/soc/rtl/MAC/rstc.v b/resources/soc/rtl/MAC/rstc.v deleted file mode 100644 index 7bedc55..0000000 --- a/resources/soc/rtl/MAC/rstc.v +++ /dev/null @@ -1,158 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -module RSTC ( - clkdma, - clkcsr, - clkt, - clkr, - rstcsr, - rstsoft, - rsttc, - rstrc, - rstdmao, - rstcsro - ); - - input clkdma; - input clkcsr; - input clkt; - input clkr; - - input rstcsr; - input rstsoft; - output rsttc; - reg rsttc; - output rstrc; - reg rstrc; - output rstdmao; - reg rstdmao; - output rstcsro; - reg rstcsro; - - - reg rstsoft_rc1; - reg rstsoft_rc2; - reg rstsoft_rc3; - reg rstsoft_tc1; - reg rstsoft_tc2; - reg rstsoft_tc3; - reg rstsoft_dma1; - reg rstsoft_dma2; - reg rstsoft_dma3; - reg rstsoft_csr; - reg rstsoft_dma_csr1; - reg rstsoft_dma_csr2; - reg rstsoft_rc_csr1; - reg rstsoft_rc_csr2; - reg rstsoft_tc_csr1; - reg rstsoft_tc_csr2; - reg rstcsr_r1; - reg rstcsr_r2; - reg rstcsr_tc1; - reg rstcsr_tc2; - reg rstcsr_rc1; - reg rstcsr_rc2; - reg rstcsr_dma1; - reg rstcsr_dma2; - - - always @(posedge clkcsr) - begin : rstsoft_csr_reg_proc - if (rstcsr_r2) - begin - rstsoft_csr <= 1'b0 ; - rstsoft_dma_csr1 <= 1'b0 ; - rstsoft_dma_csr2 <= 1'b0 ; - rstsoft_tc_csr1 <= 1'b0 ; - rstsoft_tc_csr2 <= 1'b0 ; - rstsoft_rc_csr1 <= 1'b0 ; - rstsoft_rc_csr2 <= 1'b0 ; - end - else - begin - if (rstsoft) - begin - rstsoft_csr <= 1'b1 ; - end - else if (rstsoft_rc_csr2 & rstsoft_tc_csr2 & rstsoft_dma_csr2) - begin - rstsoft_csr <= 1'b0 ; - end - rstsoft_dma_csr1 <= rstsoft_dma3; - rstsoft_dma_csr2 <= rstsoft_dma_csr1; - rstsoft_tc_csr1 <= rstsoft_tc3; - rstsoft_tc_csr2 <= rstsoft_tc_csr1; - rstsoft_rc_csr1 <= rstsoft_rc3; - rstsoft_rc_csr2 <= rstsoft_rc_csr1; - end - end - - always @(posedge clkcsr) - begin : rstcsro_reg_proc - rstcsr_r1 <= rstcsr; - rstcsr_r2 <= rstcsr_r1; - rstcsro <= rstcsr_r2 | rstsoft_csr; - end - - always @(posedge clkr) - begin : rstrc_reg_proc - rstcsr_rc1 <= rstcsr; - rstcsr_rc2 <= rstcsr_rc1; - rstsoft_rc1 <= rstsoft_csr; - rstsoft_rc2 <= rstsoft_rc1; - rstsoft_rc3 <= rstsoft_rc2; - rstrc <= rstcsr_rc2 | rstsoft_rc2; - end - - always @(posedge clkt) - begin : rsttc_proc - rstcsr_tc1 <= rstcsr; - rstcsr_tc2 <= rstcsr_tc1; - rstsoft_tc1 <= rstsoft_csr; - rstsoft_tc2 <= rstsoft_tc1; - rstsoft_tc3 <= rstsoft_tc2; - rsttc <= rstcsr_tc2 | rstsoft_tc2; - end - - always @(posedge clkdma) - begin : rstdma_reg_proc - rstcsr_dma1 <= rstcsr; - rstcsr_dma2 <= rstcsr_dma1; - rstsoft_dma1 <= rstsoft_csr; - rstsoft_dma2 <= rstsoft_dma1; - rstsoft_dma3 <= rstsoft_dma2; - rstdmao <= rstcsr_dma2 | rstsoft_dma2; - end - -endmodule diff --git a/resources/soc/rtl/MAC/tc.v b/resources/soc/rtl/MAC/tc.v deleted file mode 100644 index 337157a..0000000 --- a/resources/soc/rtl/MAC/tc.v +++ /dev/null @@ -1,1296 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -module TC ( - clk, - rst, - txen, - txer, - txd, - ramdata, - ramaddr, - wadg, - radg, - dpd, - ac, - sofreq, - eofreq, - tiack, - lastbe, - eofadg, - tireq, - ur, - de, - coll, - carrier, - bkoff, - tpend, - tprog, - preamble, - stopi, - stopo, - tcsack, - tcsreq - ); - - parameter FIFODEPTH = 9; - parameter DATAWIDTH = 32; - - `include "utility.v" - - input clk; - input rst; - - output txen; - reg txen; - output txer; - wire txer; - output [MIIWIDTH - 1:0] txd; - reg [MIIWIDTH - 1:0] txd; - - input [DATAWIDTH - 1:0] ramdata; - output [FIFODEPTH - 1:0] ramaddr; - wire [FIFODEPTH - 1:0] ramaddr; - - input [FIFODEPTH - 1:0] wadg; - output [FIFODEPTH - 1:0] radg; - wire [FIFODEPTH - 1:0] radg; - - input dpd; - input ac; - input sofreq; - input eofreq; - input tiack; - input [DATAWIDTH / 8 - 1:0] lastbe; - input [FIFODEPTH - 1:0] eofadg; - output tireq; - reg tireq; - output ur; - wire ur; - output de; - reg de; - - input coll; - input carrier; - input bkoff; - output tpend; - wire tpend; - output tprog; - reg tprog; - output preamble; - reg preamble; - - input stopi; - output stopo; - reg stopo; - - input tcsack; - output tcsreq; - reg tcsreq; - - - reg re_c; - reg re; - reg empty_c; - reg empty; - reg [FIFODEPTH - 1:0] rad_r; - reg [FIFODEPTH - 1:0] rad; - reg [FIFODEPTH - 1:0] iradg; - reg [FIFODEPTH - 1:0] wadg_0_r; - reg [FIFODEPTH - 1:0] iwadg; - reg [FIFODEPTH - 1:0] iwad_c; - reg [FIFODEPTH - 1:0] iwad; - reg [FIFODEPTH - 1:0] sofad; - reg [FIFODEPTH - 1:0] eofadg_r; - reg sofreq_r; - reg eofreq_r; - reg whole; - reg eof; - reg [DATAWIDTH - 1:0] ramdata_r; - - reg [MIIWIDTH - 1:0] itxd0; - reg [DATAWIDTH - 1:0] pmux; - reg [DATAWIDTH - 1:0] datamux_c; - wire [DATAWIDTH_MAX + 1:0] datamux_c_max; - reg txen1; - reg txen_rise; - reg [MIIWIDTH - 1:0] txd_rise; - - reg [3:0] tsm_c; - reg [3:0] tsm; - reg nset; - reg [3:0] ncnt; - wire [1:0] ncnt10; - wire [2:0] ncnt20; - reg [6:0] brel; - reg bset; - reg [6:0] bcnt; - reg bz; - reg nopad; - reg crcgen; - reg crcsend; - reg [31:0] crc_c; - reg [31:0] crc; - reg [31:0] crcneg_c; - reg itprog; - reg itpend; - reg iur; - reg iti; - reg tiack_r; - reg [3:0] ifscnt; - - reg tcsack_r; - reg [7:0] tcscnt; - reg tcs; - - reg ifs1p; - reg ifs2p; - wire defer; - - reg bkoff_r; - - reg stop_r; - wire [3:0] hnibble; - wire [MIIWIDTH_MAX + 1:0] itxd0_max; - wire [MIIWIDTH_MAX + 1:0] itxd0zero_max; - wire [DATAWIDTH_MAX + 1:0] dzero_max; - - always @(posedge clk) - begin : faddr_reg_proc - if (rst) - begin - rad <= {FIFODEPTH{1'b0}} ; - rad_r <= {FIFODEPTH{1'b0}} ; - iradg <= {FIFODEPTH{1'b0}} ; - sofad <= {FIFODEPTH{1'b0}} ; - eofadg_r <= {FIFODEPTH{1'b0}} ; - iwad <= {FIFODEPTH{1'b0}} ; - wadg_0_r <= {FIFODEPTH{1'b0}} ; - iwadg <= {FIFODEPTH{1'b0}} ; - end - else - begin - if (bkoff_r) - begin - rad <= sofad ; - end - else if (re_c) - begin - rad <= rad + 1 ; - end - else if (eof & tsm == TSM_FLUSH) - begin - rad <= iwad ; - end - - rad_r <= rad ; - - iradg <= rad ^ {1'b0, rad[FIFODEPTH - 1:1]} ; - - if (tsm == TSM_IDLE_TCSMT) - begin - sofad <= rad_r ; - end - - eofadg_r <= eofadg ; - - iwad <= iwad_c ; - - wadg_0_r <= wadg; - if (eofreq_r) - begin - iwadg <= eofadg_r ; - end - else - begin - iwadg <= wadg_0_r ; - end - end - end - - always @(iwadg) - begin : iwad_proc - reg[FIFODEPTH - 1:0] wad_v; - wad_v[FIFODEPTH - 1] = iwadg[FIFODEPTH - 1]; - begin : iwad_loop - integer i; - for(i = FIFODEPTH - 2; i >= 0; i = i - 1) - begin - wad_v[i] = wad_v[i + 1] ^ iwadg[i]; - end - end - iwad_c = wad_v ; - end - - always @(rad or iwad) - begin : empty_proc - if (rad == iwad) - begin - empty_c <= 1'b1 ; - end - else - begin - empty_c <= 1'b0 ; - end - end - - always @(posedge clk) - begin : empty_reg_proc - if (rst) - begin - empty <= 1'b1 ; - end - else - begin - empty <= empty_c ; - end - end - - always @(tsm or empty_c or ncnt) - begin : re_proc - if ((tsm == TSM_INFO | - tsm == TSM_SFD | - tsm == TSM_FLUSH) & !empty_c & - ((DATAWIDTH == 8 & !(ncnt[0])) | - (DATAWIDTH == 16 & ncnt[1:0] == 2'b10) | - (DATAWIDTH == 32 & ncnt[2:0] == 3'b110))) - begin - re_c <= 1'b1 ; - end - else - begin - re_c <= 1'b0 ; - end - end - - always @(posedge clk) - begin : re_reg_proc - if (rst) - begin - re <= 1'b0 ; - end - else - begin - re <= re_c ; - end - end - - assign ramaddr = rad ; - - assign radg = iradg ; - - always @(posedge clk) - begin : whole_reg_proc - if (rst) - begin - whole <= 1'b0 ; - end - else - begin - if (iti) - begin - whole <= 1'b0 ; - end - else if (eofreq_r) - begin - whole <= 1'b1 ; - end - end - end - - always @(posedge clk) - begin : se_reg_proc - if (rst) - begin - sofreq_r <= 1'b0 ; - eofreq_r <= 1'b0 ; - end - else - begin - sofreq_r <= sofreq ; - eofreq_r <= eofreq ; - end - end - - always @(tsm or - itpend or - bkoff_r or - defer or bz or - ncnt or dpd or - iur or - hnibble or - ac or - empty or - whole or - tiack_r or - nopad or - coll or - eof) - begin : tsm_proc - case (tsm) - TSM_IDLE_TCSMT : - begin - if (itpend & !bkoff_r & !defer) - begin - tsm_c <= TSM_PREA ; - end - else - begin - tsm_c <= TSM_IDLE_TCSMT ; - end - end - TSM_PREA : - begin - if (bz & (ncnt[0])) - begin - tsm_c <= TSM_SFD ; - end - else - begin - tsm_c <= TSM_PREA ; - end - end - TSM_SFD : - begin - if (bz & (ncnt[0])) - begin - tsm_c <= TSM_INFO ; - end - else - begin - tsm_c <= TSM_SFD ; - end - end - TSM_INFO : - begin - if (coll) - begin - tsm_c <= TSM_JAM ; - end - else if (empty) - begin - if (!whole & ncnt == hnibble) - begin - tsm_c <= TSM_JAM ; - end - else if (eof & (nopad | dpd)) - begin - if (ac) - begin - tsm_c <= TSM_INT ; - end - else - begin - tsm_c <= TSM_CRC ; - end - end - else if (eof) - begin - tsm_c <= TSM_PAD ; - end - else - begin - tsm_c <= TSM_INFO ; - end - end - else - begin - tsm_c <= TSM_INFO ; - end - end - TSM_PAD : - begin - if (coll) - begin - tsm_c <= TSM_JAM ; - end - else if (nopad & (ncnt[0])) - begin - tsm_c <= TSM_CRC ; - end - else - begin - tsm_c <= TSM_PAD ; - end - end - TSM_CRC : - begin - if (coll) - begin - tsm_c <= TSM_JAM ; - end - else if (bz & (ncnt[0])) - begin - tsm_c <= TSM_INT ; - end - else - begin - tsm_c <= TSM_CRC ; - end - end - TSM_JAM : - begin - if (bz & (ncnt[0])) - begin - if (!bkoff_r | iur) - begin - tsm_c <= TSM_FLUSH ; - end - else - begin - tsm_c <= TSM_IDLE_TCSMT ; - end - end - else - begin - tsm_c <= TSM_JAM ; - end - end - TSM_FLUSH : - begin - if (whole & empty) - begin - tsm_c <= TSM_INT ; - end - else - begin - tsm_c <= TSM_FLUSH ; - end - end - default : - begin - if (tiack_r) - begin - tsm_c <= TSM_IDLE_TCSMT ; - end - else - begin - tsm_c <= TSM_INT ; - end - end - endcase - end - - always @(posedge clk) - begin : tsm_reg_proc - if (rst) - begin - tsm <= TSM_IDLE_TCSMT ; - end - else - begin - tsm <= tsm_c ; - end - end - - assign defer = ifs1p | ifs2p ; - - always @(posedge clk) - begin : ifs_reg_proc - if (rst) - begin - ifs1p <= 1'b0 ; - ifs2p <= 1'b0 ; - ifscnt <= IFS1_TIME ; - end - else - begin - if (!itprog & !ifs1p & !ifs2p & ifscnt != 4'b0000) - begin - ifs1p <= 1'b1 ; - end - else if (ifscnt == 4'b0000 | ifs2p) - begin - ifs1p <= 1'b0 ; - end - - if (ifs1p & ifscnt == 4'b0000) - begin - ifs2p <= 1'b1 ; - end - else if (ifs2p & ifscnt == 4'b0000) - begin - ifs2p <= 1'b0 ; - end - - if (itprog | - (carrier & ifs1p) | - (carrier & ifscnt == 4'b0000 & !itpend) | - (carrier & ifscnt == 4'b0000 & bkoff_r)) - begin - ifscnt <= IFS1_TIME ; - end - else if (ifs1p & ifscnt == 4'b0000) - begin - ifscnt <= IFS2_TIME ; - end - else if (ifscnt != 4'b0000) - begin - ifscnt <= ifscnt - 1 ; - end - end - end - - always @(posedge clk) - begin : de_reg_proc - if (rst) - begin - de <= 1'b0 ; - end - else - begin - if (ifs1p & itpend & carrier & tsm == TSM_IDLE_TCSMT) - begin - de <= 1'b1 ; - end - else if (tiack_r) - begin - de <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : eof_reg_proc - if (rst) - begin - eof <= 1'b0 ; - end - else - begin - case (DATAWIDTH) - 8 : - begin - if (whole & !(ncnt[0])) - begin - eof <= 1'b1 ; - end - else - begin - eof <= 1'b0 ; - end - end - 16 : - begin - if (whole & ((lastbe == 2'b11 & ncnt[1:0] == 2'b10) | - (lastbe == 2'b01 & ncnt[1:0] == 2'b00))) - begin - eof <= 1'b1 ; - end - else - begin - eof <= 1'b0 ; - end - end - default : - begin - if (whole & ((lastbe == 4'b1111 & ncnt[2:0] == 3'b110) | - (lastbe == 4'b0111 & ncnt[2:0] == 3'b100) | - (lastbe == 4'b0011 & ncnt[2:0] == 3'b010) | - (lastbe == 4'b0001 & ncnt[2:0] == 3'b000))) - begin - eof <= 1'b1 ; - end - else - begin - eof <= 1'b0 ; - end - end - endcase - end - end - - always @(coll or tsm or ncnt or bz or empty or eof or nopad) - begin : bset_reg_proc - if ((coll & (tsm == TSM_INFO | - tsm == TSM_PAD | - tsm == TSM_CRC)) | - (tsm == TSM_PAD & nopad & !(ncnt[0])) | - (tsm == TSM_PREA & bz & !(ncnt[0])) | - (tsm == TSM_SFD & (ncnt[0])) | - (tsm == TSM_INFO & empty & eof & nopad) | - (tsm == TSM_IDLE_TCSMT)) - begin - bset <= 1'b1 ; - end - else - begin - bset <= 1'b0 ; - end - end - - always @(posedge clk) - begin : bcnt_reg_proc - if (rst) - begin - bcnt <= {7{1'b1}} ; - brel <= 7'b0000110 ; - bz <= 1'b0 ; - end - else - begin - if (bset) - begin - if(coll & tsm==TSM_INFO) - begin - bcnt <= 7'b0000011; - end - else - begin - bcnt <= brel ; - end - end - else if ((ncnt[0]) & !bz) - begin - bcnt <= bcnt - 1 ; - end - - case (tsm) - TSM_IDLE_TCSMT : - begin - brel <= 7'b0000110 ; - end - TSM_PREA : - begin - brel <= 7'b0000000 ; - end - TSM_SFD : - begin - if (coll) - begin - brel <= 7'b0000011 ; - end - else - begin - brel <= MIN_FRAME - 1 ; - end - end - default : - begin - brel <= 7'b0000011 ; - end - endcase - - if (bset & brel != 7'b0000000) - begin - bz <= 1'b0 ; - end - else if (bcnt == 7'b0000001 & (ncnt[0]) & !bz) - begin - bz <= 1'b1 ; - end - end - end - - always @(posedge clk) - begin : nopad_reg_proc - if (rst) - begin - nopad <= 1'b0 ; - end - else - begin - if ((tsm == TSM_INFO & bcnt == 7'b0000100 & !ac) | - (tsm == TSM_INFO & bcnt == 7'b0000001 & ac) | - (tsm == TSM_PAD & bcnt == 7'b0000100) | (dpd & !ac)) - begin - nopad <= 1'b1 ; - end - else if (tsm == TSM_IDLE_TCSMT) - begin - nopad <= 1'b0 ; - end - end - end - - always @(tsm or - itpend or - bkoff_r or - defer or - ncnt or - eof or - empty or - nopad) - begin : nset_proc - if ((tsm == TSM_IDLE_TCSMT & ~(itpend & !bkoff_r & !defer)) | - (tsm == TSM_INFO & empty & eof) | - (tsm == TSM_PAD & nopad & (ncnt[0]))) - begin - nset <= 1'b1 ; - end - else - begin - nset <= 1'b0 ; - end - end - - always @(posedge clk) - begin : ncnt_reg_proc - if (rst) - begin - ncnt <= {4{1'b0}} ; - end - else - begin - if (nset) - begin - ncnt <= {4{1'b0}} ; - end - else if (tsm != TSM_IDLE_TCSMT) - begin - ncnt <= ncnt + 1 ; - end - end - end - - always @(tsm or crc or itxd0_max or crcgen) - begin : crc_proc - if (tsm == TSM_PREA) - begin - crc_c <= {32{1'b1}} ; - end - else if (crcgen) - begin - crc_c[0] <= crc[28] ^ - itxd0_max[3] ; - crc_c[1] <= crc[28] ^ crc[29] ^ - itxd0_max[2] ^ itxd0_max[3] ; - crc_c[2] <= crc[28] ^ crc[29] ^ crc[30] ^ - itxd0_max[1] ^ itxd0_max[2] ^ itxd0_max[3] ; - crc_c[3] <= crc[29] ^ crc[30] ^ crc[31] ^ - itxd0_max[0] ^ itxd0_max[1] ^ itxd0_max[2] ; - crc_c[4] <= crc[0] ^ crc[28] ^ crc[30] ^ crc[31] ^ - itxd0_max[0] ^ itxd0_max[1] ^ itxd0_max[3] ; - crc_c[5] <= crc[1] ^ crc[28] ^ crc[29] ^ crc[31] ^ - itxd0_max[0] ^ itxd0_max[2] ^ itxd0_max[3] ; - crc_c[6] <= crc[2] ^ crc[29] ^ crc[30] ^ - itxd0_max[1] ^ itxd0_max[2] ; - crc_c[7] <= crc[3] ^ crc[28] ^ crc[30] ^ crc[31] ^ - itxd0_max[0] ^ itxd0_max[1] ^ itxd0_max[3] ; - crc_c[8] <= crc[4] ^ crc[28] ^ crc[29] ^ crc[31] ^ - itxd0_max[0] ^ itxd0_max[2] ^ itxd0_max[3] ; - crc_c[9] <= crc[5] ^ crc[29] ^ crc[30] ^ - itxd0_max[1] ^ itxd0_max[2] ; - crc_c[10] <= crc[6] ^ crc[28] ^ crc[30] ^ crc[31] ^ - itxd0_max[0] ^ itxd0_max[1] ^ itxd0_max[3] ; - crc_c[11] <= crc[7] ^ crc[28] ^ crc[29] ^ crc[31] ^ - itxd0_max[0] ^ itxd0_max[2] ^ itxd0_max[3] ; - crc_c[12] <= crc[8] ^ crc[28] ^ crc[29] ^ crc[30] ^ - itxd0_max[1] ^ itxd0_max[2] ^ itxd0_max[3] ; - crc_c[13] <= crc[9] ^ crc[29] ^ crc[30] ^ crc[31] ^ - itxd0_max[0] ^ itxd0_max[1] ^ itxd0_max[2] ; - crc_c[14] <= crc[10] ^ crc[30] ^ crc[31] ^ - itxd0_max[0] ^ itxd0_max[1] ; - crc_c[15] <= crc[11] ^ crc[31] ^ - itxd0_max[0] ; - crc_c[16] <= crc[12] ^ crc[28] ^ - itxd0_max[3] ; - crc_c[17] <= crc[13] ^ crc[29] ^ - itxd0_max[2] ; - crc_c[18] <= crc[14] ^ crc[30] ^ - itxd0_max[1] ; - crc_c[19] <= crc[15] ^ crc[31] ^ - itxd0_max[0] ; - crc_c[20] <= crc[16] ; - crc_c[21] <= crc[17] ; - crc_c[22] <= crc[18] ^ crc[28] ^ - itxd0_max[3] ; - crc_c[23] <= crc[19] ^ crc[28] ^ crc[29] ^ - itxd0_max[2] ^ itxd0_max[3] ; - crc_c[24] <= crc[20] ^ crc[29] ^ crc[30] ^ - itxd0_max[1] ^ itxd0_max[2] ; - crc_c[25] <= crc[21] ^ crc[30] ^ crc[31] ^ - itxd0_max[0] ^ itxd0_max[1] ; - crc_c[26] <= crc[22] ^ crc[28] ^ crc[31] ^ - itxd0_max[0] ^ itxd0_max[3] ; - crc_c[27] <= crc[23] ^ crc[29] ^ - itxd0_max[2] ; - crc_c[28] <= crc[24] ^ crc[30] ^ - itxd0_max[1] ; - crc_c[29] <= crc[25] ^ crc[31] ^ - itxd0_max[0] ; - crc_c[30] <= crc[26] ; - crc_c[31] <= crc[27] ; - end - else - begin - crc_c <= crc ; - end - end - - always @(posedge clk) - begin : crc_reg_proc - if (rst) - begin - crcgen <= 1'b0 ; - crcsend <= 1'b0 ; - crc <= {32{1'b1}} ; - end - else - begin - crc <= crc_c ; - - if (tsm == TSM_INFO | tsm == TSM_PAD) - begin - crcgen <= 1'b1 ; - end - else - begin - crcgen <= 1'b0 ; - end - - if (tsm == TSM_CRC) - begin - crcsend <= 1'b1 ; - end - else - begin - crcsend <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : tstate_reg_proc - if (rst) - begin - itprog <= 1'b0 ; - itpend <= 1'b0 ; - tprog <= 1'b0 ; - preamble <= 1'b0 ; - end - else - begin - if (tsm == TSM_INFO | tsm == TSM_PAD | tsm == TSM_CRC | - tsm == TSM_JAM) - begin - itprog <= 1'b1 ; - end - else - begin - itprog <= 1'b0 ; - end - - if (sofreq_r) - begin - itpend <= 1'b1 ; - end - else - begin - itpend <= 1'b0 ; - end - - if (tsm == TSM_PREA | - tsm == TSM_SFD | - tsm == TSM_INFO | - tsm == TSM_PAD | - tsm == TSM_CRC | - tsm == TSM_JAM) - begin - tprog <= 1'b1 ; - end - else - begin - tprog <= 1'b0 ; - end - - if (tsm == TSM_PREA | tsm == TSM_SFD) - begin - preamble <= 1'b1 ; - end - else - begin - preamble <= 1'b0 ; - end - end - end - - assign tpend = itpend ; - - always @(posedge clk) - begin : iti_reg_proc - if (rst) - begin - iti <= 1'b0 ; - tireq <= 1'b0 ; - tiack_r <= 1'b0 ; - end - else - begin - if (tsm == TSM_INT) - begin - iti <= 1'b1 ; - end - else if (tiack) - begin - iti <= 1'b0 ; - end - - tireq <= iti ; - tiack_r <= tiack ; - end - end - - always @(posedge clk) - begin : iur_reg_proc - if (rst) - begin - iur <= 1'b0 ; - end - else - begin - if (itprog & empty & !whole) - begin - iur <= 1'b1 ; - end - else if (tiack_r) - begin - iur <= 1'b0 ; - end - end - end - - assign ur = iur ; - - always @(tsm or ramdata_r or pmux) - begin : datamux_proc - if (tsm == TSM_INFO) - begin - datamux_c <= ramdata_r ; - end - else - begin - datamux_c <= pmux ; - end - end - - assign ncnt10 = ncnt[1:0] ; - - assign ncnt20 = ncnt[2:0] ; - - assign datamux_c_max = {dzero_max[DATAWIDTH_MAX + 1:DATAWIDTH], - datamux_c}; - - always @(crc) - begin : crcneg_proc - begin : crcneg_loop - integer i; - for(i = 31; i >= 0; i = i - 1) - begin - crcneg_c[i] <= ~crc[31 - i] ; - end - end - end - - always @(posedge clk) - begin : txd_proc - if (rst) - begin - txd_rise <= {MIIWIDTH{1'b1}} ; - pmux <= {DATAWIDTH{1'b1}} ; - itxd0 <= {MIIWIDTH{1'b1}} ; - ramdata_r <= {DATAWIDTH{1'b0}} ; - end - else - begin - case (tsm_c) - TSM_PAD : - begin - pmux <= PAD_PATTERN[63:64 - DATAWIDTH] ; - end - TSM_JAM : - begin - pmux <= JAM_PATTERN[63:64 - DATAWIDTH] ; - end - TSM_PREA : - begin - pmux <= PRE_PATTERN[63:64 - DATAWIDTH] ; - end - TSM_SFD : - begin - pmux <= SFD_PATTERN[63:64 - DATAWIDTH] ; - end - default : - begin - pmux <= {DATAWIDTH{1'b1}} ; - end - endcase - - case (DATAWIDTH) - 32 : - begin - case (ncnt20) - 3'b000 : - begin - itxd0 <= datamux_c_max[3:0] ; - end - 3'b001 : - begin - itxd0 <= datamux_c_max[7:4] ; - end - 3'b010 : - begin - itxd0 <= datamux_c_max[11:8] ; - end - 3'b011 : - begin - itxd0 <= datamux_c_max[15:12] ; - end - 3'b100 : - begin - itxd0 <= datamux_c_max[19:16] ; - end - 3'b101 : - begin - itxd0 <= datamux_c_max[23:20] ; - end - 3'b110 : - begin - itxd0 <= datamux_c_max[27:24] ; - end - default : - begin - itxd0 <= datamux_c_max[31:28] ; - end - endcase - end - 16 : - begin - case (ncnt10) - 2'b00 : - begin - itxd0 <= datamux_c_max[3:0] ; - end - 2'b01 : - begin - itxd0 <= datamux_c_max[7:4] ; - end - 2'b10 : - begin - itxd0 <= datamux_c_max[11:8] ; - end - default : - begin - itxd0 <= datamux_c_max[15:12] ; - end - endcase - end - default : - begin - if (!(ncnt[0])) - begin - itxd0 <= datamux_c_max[3:0] ; - end - else - begin - itxd0 <= datamux_c_max[7:4] ; - end - end - endcase - - if (re) - begin - ramdata_r <= ramdata ; - end - - if (crcsend) - begin - case (ncnt) - 4'b0001 : - begin - txd_rise <= crcneg_c[3:0] ; - end - 4'b0010 : - begin - txd_rise <= crcneg_c[7:4] ; - end - 4'b0011 : - begin - txd_rise <= crcneg_c[11:8] ; - end - 4'b0100 : - begin - txd_rise <= crcneg_c[15:12] ; - end - 4'b0101 : - begin - txd_rise <= crcneg_c[19:16] ; - end - 4'b0110 : - begin - txd_rise <= crcneg_c[23:20] ; - end - 4'b0111 : - begin - txd_rise <= crcneg_c[27:24] ; - end - default : - begin - txd_rise <= crcneg_c[31:28] ; - end - endcase - end - else - begin - txd_rise <= itxd0 ; - end - end - end - - always @(posedge clk) - begin : txen_reg_proc - if (rst) - begin - txen1 <= 1'b0 ; - txen_rise <= 1'b0 ; - end - else - begin - txen_rise <= txen1 ; - if (tsm == TSM_IDLE_TCSMT | - tsm == TSM_INT | - tsm == TSM_FLUSH) - begin - txen1 <= 1'b0 ; - end - else - begin - txen1 <= 1'b1 ; - end - end - end - - always @(posedge clk) - begin : mii_fall_reg_proc - txen <= txen_rise ; - txd <= txd_rise; - end - - assign txer = 1'b0 ; - - always @(posedge clk) - begin : bkoff_reg_proc - if (rst) - begin - bkoff_r <= 1'b0 ; - end - else - begin - if (bkoff) - begin - bkoff_r <= 1'b1 ; - end - else if (tsm != TSM_JAM) - begin - bkoff_r <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : stopo_reg_proc - if (rst) - begin - stop_r <= 1'b0 ; - stopo <= 1'b0 ; - end - else - begin - stop_r <= stopi; - - if (stop_r & tsm == TSM_IDLE_TCSMT & !itpend) - begin - stopo <= 1'b1 ; - end - else - begin - stopo <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : cscnt_reg_proc - if (rst) - begin - tcscnt <= {8{1'b0}} ; - tcs <= 1'b0 ; - tcsreq <= 1'b0 ; - tcsack_r <= 1'b0 ; - end - else - begin - if (tcscnt == 8'b00000000) - begin - tcscnt <= 8'b10000000 ; - end - else - begin - tcscnt <= tcscnt - 1 ; - end - - if (tcscnt == 8'b00000000) - begin - tcs <= 1'b1 ; - end - else if (tcsack_r) - begin - tcs <= 1'b0 ; - end - - if (tcs & !tcsack_r) - begin - tcsreq <= 1'b1 ; - end - else if (tcsack_r) - begin - tcsreq <= 1'b0 ; - end - - tcsack_r <= tcsack ; - - end - end - - assign hnibble = (DATAWIDTH == 32) ? 4'b0111 : - (DATAWIDTH == 16) ? 4'b0011 : - 4'b0001 ; - - assign itxd0zero_max = {(MIIWIDTH_MAX + 1){1'b0}} ; - - assign itxd0_max = {itxd0zero_max[MIIWIDTH_MAX + 1:MIIWIDTH], - itxd0}; - - assign dzero_max = {(DATAWIDTH_MAX + 1){1'b0}} ; - -endmodule diff --git a/resources/soc/rtl/MAC/tfifo.v b/resources/soc/rtl/MAC/tfifo.v deleted file mode 100644 index dca5758..0000000 --- a/resources/soc/rtl/MAC/tfifo.v +++ /dev/null @@ -1,815 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -module TFIFO ( - clk, - rst, - ramwe, - ramaddr, - ramdata, - fifowe, - fifoeof, - fifobe, - fifodata, - fifonf, - fifocnf, - fifoval, - flev, - ici, - dpdi, - aci, - statadi, - cachere, - deo, - lco, - loo, - nco, - eco, - csne, - ico, - uro, - cco, - statado, - sofreq, - eofreq, - dpdo, - aco, - beo, - eofad, - wadg, - tireq, - winp, - dei, - lci, - loi, - nci, - eci, - uri, - cci, - radg, - tiack, - sf, - fdp, - tm, - pbl, - etiack, - etireq, - stopi, - stopo - ); - - parameter DATAWIDTH = 32; - parameter DATADEPTH = 32; - parameter FIFODEPTH = 9; - parameter CACHEDEPTH = 1; - - `include "utility.v" - - input clk; - input rst; - - output ramwe; - wire ramwe; - output [FIFODEPTH - 1:0] ramaddr; - wire [FIFODEPTH - 1:0] ramaddr; - output [DATAWIDTH - 1:0] ramdata; - wire [DATAWIDTH - 1:0] ramdata; - - input fifowe; - input fifoeof; - input [DATAWIDTH / 8 - 1:0] fifobe; - input [DATAWIDTH - 1:0] fifodata; - output fifonf; - reg fifonf; - output fifocnf; - wire fifocnf; - output fifoval; - reg fifoval; - output [FIFODEPTH - 1:0] flev; - wire [FIFODEPTH - 1:0] flev; - - input ici; - input dpdi; - input aci; - input [DATADEPTH - 1:0] statadi; - - input cachere; - output deo; - wire deo; - output lco; - wire lco; - output loo; - wire loo; - output nco; - wire nco; - output eco; - wire eco; - output csne; - wire csne; - output ico; - wire ico; - output uro; - wire uro; - output [3:0] cco; - wire [3:0] cco; - output [DATADEPTH - 1:0] statado; - wire [DATADEPTH - 1:0] statado; - - output sofreq; - wire sofreq; - output eofreq; - reg eofreq; - output dpdo; - wire dpdo; - output aco; - wire aco; - output [DATAWIDTH / 8 - 1:0] beo; - wire [DATAWIDTH / 8 - 1:0] beo; - output [FIFODEPTH - 1:0] eofad; - reg [FIFODEPTH - 1:0] eofad; - output [FIFODEPTH - 1:0] wadg; - reg [FIFODEPTH - 1:0] wadg; - - input tireq; - input winp; - input dei; - input lci; - input loi; - input nci; - input eci; - input uri; - input [3:0] cci; - input [FIFODEPTH - 1:0] radg; - output tiack; - wire tiack; - - input sf; - input fdp; - input [2:0] tm; - input [5:0] pbl; - - input etiack; - output etireq; - reg etireq; - - input stopi; - output stopo; - reg stopo; - - - parameter CCWIDTH = (3 + DATADEPTH + DATAWIDTH / 8 + FIFODEPTH); - reg [CCWIDTH - 1:0] ccmem[(1'b1 << CACHEDEPTH) - 1:0]; - wire ccwe; - wire ccre; - reg ccne; - reg iccnf; - wire [CACHEDEPTH - 1:0] ccwad_c; - reg [CACHEDEPTH - 1:0] ccwad; - reg [CACHEDEPTH - 1:0] ccrad; - reg [CACHEDEPTH - 1:0] ccrad_r; - wire [CCWIDTH - 1:0] ccdi; - wire [CCWIDTH - 1:0] ccdo; - - parameter CSWIDTH = (DATADEPTH + 11); - reg [CSWIDTH - 1:0] csmem[(1'b1 << CACHEDEPTH) - 1:0]; - wire cswe; - reg csre; - reg [CACHEDEPTH - 1:0] cswad; - wire [CACHEDEPTH - 1:0] csrad_c; - reg [CACHEDEPTH - 1:0] csrad; - reg [CACHEDEPTH - 1:0] csrad_r; - wire [CSWIDTH - 1:0] csdi; - wire [CSWIDTH - 1:0] csdo; - wire [DATADEPTH - 1:0] statad; - wire ic; - reg icsne; - - reg tprog; - reg tprog_r; - - reg winp_r; - reg [FIFODEPTH_MAX - 1:0] tlev_c; - reg tresh; - reg [FIFODEPTH - 1:0] stat; - reg [FIFODEPTH - 1:0] wad; - reg [FIFODEPTH - 1:0] rad_c; - reg [FIFODEPTH - 1:0] rad; - reg [FIFODEPTH - 1:0] radg_0_r; - reg [FIFODEPTH - 1:0] radg_r; - reg [FIFODEPTH - 1:0] sad; - wire [FIFODEPTH - 1:0] eofad_bin; - reg pblz; - reg [FIFODEPTH_MAX - 1:0] sflev_c; - - reg tireq_r; - reg tireq_r2; - - reg stop_r; - - wire [FIFODEPTH - 1:0] fone; - wire [FIFODEPTH - 1:0] fzero; - - always @(posedge clk) - begin : ccmem_reg_proc - if (rst) - begin : ccmem_reset - integer i; - for(i = ((1'b1 << CACHEDEPTH) - 1); i >= 0; i = i - 1) - begin - ccmem[i] <= {CCWIDTH{1'b0}}; - end - ccrad_r <= {CACHEDEPTH{1'b0}} ; - end - else - begin - if (fifowe | fifoeof) - begin - ccmem[ccwad] <= ccdi ; - end - ccrad_r <= ccrad ; - end - end - - assign ccwad_c = (fifoeof) ? ccwad + 1 : ccwad ; - - always @(posedge clk) - begin : ccaddr_reg_proc - if (rst) - begin - ccwad <= {CACHEDEPTH{1'b0}} ; - ccrad <= {CACHEDEPTH{1'b0}} ; - end - else - begin - ccwad <= ccwad_c ; - - if (ccre) - begin - ccrad <= ccrad + 1 ; - end - end - end - - always @(posedge clk) - begin : ccfe_reg_proc - if (rst) - begin - iccnf <= 1'b1 ; - ccne <= 1'b0 ; - end - else - begin - if ((ccwad_c == ccrad) & ccwe) - begin - iccnf <= 1'b0 ; - end - else if (ccre) - begin - iccnf <= 1'b1 ; - end - - if (ccwad == ccrad & iccnf) - begin - ccne <= 1'b0 ; - end - else - begin - ccne <= 1'b1 ; - end - end - end - - assign fifocnf = iccnf ; - - assign ccdo = ccmem[ccrad_r] ; - - assign ccdi = {ici, aci, dpdi, wad, fifobe, statadi} ; - - assign ccwe = fifoeof ; - - assign ccre = tireq_r & ~tireq_r2 ; - - assign ic = ccdo[CCWIDTH - 1] ; - - assign aco = ccdo[CCWIDTH - 2] ; - - assign dpdo = ccdo[CCWIDTH - 3] ; - - assign eofad_bin = ccdo[CCWIDTH - 4:CCWIDTH - 3 - FIFODEPTH] ; - - always @(posedge clk) - begin : eofad_reg_proc - if (rst) - begin - eofad <= {FIFODEPTH{1'b0}} ; - end - else - begin - eofad[FIFODEPTH - 1] <= eofad_bin[FIFODEPTH - 1] ; - begin : eofad_loop - integer i; - for(i = FIFODEPTH - 2; i >= 0; i = i - 1) - begin - eofad[i] <= eofad_bin[i] ^ eofad_bin[i + 1] ; - end - end - end - end - - assign beo = ccdo[DATADEPTH + DATAWIDTH / 8 - 1:DATADEPTH] ; - - assign statad = ccdo[DATADEPTH - 1:0] ; - - always @(posedge clk) - begin : csmem_reg_proc - if (rst) - begin : csmem_reset - integer i; - for(i = ((1'b1 << CACHEDEPTH) - 1); i >= 0; i = i - 1) - begin - csmem[i] <= {CSWIDTH{1'b0}}; - end - csrad_r <= {CACHEDEPTH{1'b0}}; - end - else - begin - csmem[cswad] <= csdi ; - csrad_r <= csrad ; - end - end - - always @(posedge clk) - begin : csaddr_reg_proc - if (rst) - begin - cswad <= {CACHEDEPTH{1'b0}} ; - csrad <= {CACHEDEPTH{1'b0}} ; - end - else - begin - if (cswe) - begin - cswad <= cswad + 1 ; - end - - csrad <= csrad_c ; - end - end - - assign csrad_c = (csre) ? csrad + 1 : csrad ; - - always @(posedge clk) - begin : icsne_reg_proc - if (rst) - begin - icsne <= 1'b0 ; - end - else - begin - if (cswad == csrad | (csre & cswad == csrad_c)) - begin - icsne <= 1'b0 ; - end - else - begin - icsne <= 1'b1 ; - end - end - end - - assign csne = icsne; - - assign csdo = csmem[csrad_r] ; - - assign csdi = {dei, lci, loi, nci, eci, ic, cci, uri, statad} ; - - assign deo = csdo[CSWIDTH - 1] ; - - assign lco = csdo[CSWIDTH - 2] ; - - assign loo = csdo[CSWIDTH - 3] ; - - assign nco = csdo[CSWIDTH - 4] ; - - assign eco = csdo[CSWIDTH - 5] ; - - assign ico = csdo[CSWIDTH - 6] ; - - assign cco = csdo[CSWIDTH - 7:CSWIDTH - 10] ; - - assign uro = csdo[CSWIDTH - 11] ; - - assign statado = csdo[DATADEPTH - 1:0] ; - - assign cswe = tireq_r & tprog ; - - always @(posedge clk) - begin : csre_reg_proc - if (rst) - begin - csre <= 1'b0 ; - end - else - begin - csre <= cachere ; - end - end - - always @(posedge clk) - begin : tprog_reg_proc - if (rst) - begin - tprog <= 1'b0 ; - tprog_r <= 1'b0 ; - end - else - begin - tprog_r <= tprog ; - if (tireq_r) - begin - tprog <= 1'b0 ; - end - else if ((!sf & !tprog & !tireq_r & tresh) | ccne) - begin - tprog <= 1'b1 ; - end - end - end - - always @(posedge clk) - begin : eofreq_reg_proc - if (rst) - begin - eofreq <= 1'b0 ; - end - else - begin - if (tprog & ccne) - begin - eofreq <= 1'b1 ; - end - else if (tireq_r) - begin - eofreq <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : tireq_reg_proc - if (rst) - begin - tireq_r <= 1'b0 ; - tireq_r2 <= 1'b0 ; - end - else - begin - tireq_r <= tireq ; - tireq_r2 <= tireq_r ; - end - end - - always @(posedge clk) - begin : etireq_reg_proc - if (rst) - begin - etireq <= 1'b0 ; - end - else - begin - if (fifoeof) - begin - etireq <= 1'b1 ; - end - else if (etiack) - begin - etireq <= 1'b0 ; - end - end - end - - assign tiack = tireq_r2 ; - - assign sofreq = tprog ; - - always @(posedge clk) - begin : addr_reg_proc - if (rst) - begin - wad <= {FIFODEPTH{1'b0}} ; - wadg <= {FIFODEPTH{1'b0}} ; - radg_0_r <= {FIFODEPTH{1'b0}} ; - radg_r <= {FIFODEPTH{1'b0}} ; - rad <= {FIFODEPTH{1'b0}} ; - sad <= {FIFODEPTH{1'b0}} ; - end - else - begin - if (fifowe) - begin - wad <= wad + 1 ; - end - - wadg[FIFODEPTH - 1] <= wad[FIFODEPTH - 1] ; - begin : wadg_loop - integer i; - for(i = FIFODEPTH - 2; i >= 0; i = i - 1) - begin - wadg[i] <= wad[i] ^ wad[i + 1] ; - end - end - - radg_0_r <= radg ; - radg_r <= radg_0_r ; - - rad <= rad_c ; - - if (!tprog & tprog_r) - begin - sad <= eofad_bin ; - end - end - end - - always @(radg_r) - begin : rad_proc - reg[FIFODEPTH - 1:0] rad_v; - rad_v[FIFODEPTH - 1] = radg_r[FIFODEPTH - 1]; - begin : rad_loop - integer i; - for(i = FIFODEPTH - 2; i >= 0; i = i - 1) - begin - rad_v[i] = rad_v[i + 1] ^ radg_r[i]; - end - end - rad_c = rad_v ; - end - - always @(posedge clk) - begin : stat_reg_proc - if (rst) - begin - stat <= {FIFODEPTH{1'b0}} ; - end - else - begin - if ((!winp_r & !fdp & tprog & !tireq_r) | !tprog_r) - begin - stat <= wad - sad ; - end - else - begin - stat <= wad - rad ; - end - end - end - - always @(posedge clk) - begin : winp_reg_proc - if (rst) - begin - winp_r <= 1'b0 ; - end - else - begin - winp_r <= winp ; - end - end - - always @(tm) - begin : tresh_proc - tlev_c <= {FIFODEPTH_MAX{1'b0}} ; - case (DATAWIDTH) - 8 : - begin - case (tm) - 3'b000, 3'b101, 3'b110 : - begin - tlev_c[10:0] <= 11'b00010000000 ; - end - 3'b001, 3'b111 : - begin - tlev_c[10:0] <= 11'b00100000000 ; - end - 3'b010 : - begin - tlev_c[10:0] <= 11'b01000000000 ; - end - 3'b011 : - begin - tlev_c[10:0] <= 11'b10000000000 ; - end - default : - begin - tlev_c[10:0] <= 11'b00001000000 ; - end - endcase - end - 16 : - begin - case (tm) - 3'b000, 3'b101, 3'b110 : - begin - tlev_c[10:0] <= 11'b00001000000 ; - end - 3'b001, 3'b111 : - begin - tlev_c[10:0] <= 11'b00010000000 ; - end - 3'b010 : - begin - tlev_c[10:0] <= 11'b00100000000 ; - end - 3'b011 : - begin - tlev_c[10:0] <= 11'b01000000000 ; - end - default : - begin - tlev_c[10:0] <= 11'b00000100000 ; - end - endcase - end - default : - begin - case (tm) - 3'b000, 3'b101, 3'b110 : - begin - tlev_c[10:0] <= 11'b00000100000 ; - end - 3'b001, 3'b111 : - begin - tlev_c[10:0] <= 11'b00001000000 ; - end - 3'b010 : - begin - tlev_c[10:0] <= 11'b00010000000 ; - end - 3'b011 : - begin - tlev_c[10:0] <= 11'b00100000000 ; - end - default : - begin - tlev_c[10:0] <= 11'b00000010000 ; - end - endcase - end - endcase - end - - always @(posedge clk) - begin : tresh_reg_proc - if (rst) - begin - tresh <= 1'b0 ; - end - else - begin - if (stat >= tlev_c[FIFODEPTH - 1:0]) - begin - tresh <= 1'b1 ; - end - else - begin - tresh <= 1'b0 ; - end - end - end - - always @(pbl or pblz) - begin : sflev_proc - sflev_c[FIFODEPTH_MAX - 1:6] <= {(FIFODEPTH_MAX-6){1'b1}} ; - if (pblz) - begin - sflev_c[5:0] <= 6'b000000 ; - end - else - begin - sflev_c[5:0] <= ~pbl ; - end - end - - always @(posedge clk) - begin : fifoval_reg_proc - if (rst) - begin - fifoval <= 1'b0 ; - end - else - begin - if (stat <= sflev_c[FIFODEPTH - 1:0]) - begin - fifoval <= 1'b1 ; - end - else - begin - fifoval <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : pblz_reg_proc - if (rst) - begin - pblz <= 1'b0 ; - end - else - begin - if (pbl == 6'b000000) - begin - pblz <= 1'b1 ; - end - else - begin - pblz <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : fifonf_reg_proc - if (rst) - begin - fifonf <= 1'b1 ; - end - else - begin - if ((stat == {fone[FIFODEPTH - 1:1], 1'b0} & fifowe) | - (stat == fone)) - begin - fifonf <= 1'b0 ; - end - else - begin - fifonf <= 1'b1 ; - end - end - end - - assign flev = stat ; - - assign ramaddr = wad ; - - assign ramdata = fifodata ; - - assign ramwe = fifowe ; - - always @(posedge clk) - begin : tstop_reg_proc - if (rst) - begin - stop_r <= 1'b1 ; - stopo <= 1'b0 ; - end - else - begin - stop_r <= stopi ; - - if (stop_r & !ccne & !icsne & stat == fzero & !tprog) - begin - stopo <= 1'b1 ; - end - else - begin - stopo <= 1'b0 ; - end - end - end - - assign fone = {FIFODEPTH{1'b1}} ; - - assign fzero = {FIFODEPTH{1'b0}} ; - -endmodule diff --git a/resources/soc/rtl/MAC/tlsm.v b/resources/soc/rtl/MAC/tlsm.v deleted file mode 100644 index c98093a..0000000 --- a/resources/soc/rtl/MAC/tlsm.v +++ /dev/null @@ -1,2197 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -module TLSM ( - clk, - rst, - fifonf, - fifocnf, - fifoval, - fifolev, - fifowe, - fifoeof, - fifobe, - fifodata, - ic, - ac, - dpd, - statado, - csne, - lo, - nc, - lc, - ec, - de, - ur, - cc, - statadi, - cachere, - dmaack, - dmaeob, - dmadatai, - dmaaddr, - dmareq, - dmawr, - dmacnt, - dmaaddro, - dmadatao, - fwe, - fdata, - faddr, - dsl, - pbl, - poll, - dbadc, - dbad, - pollack, - tcompack, - tcomp, - des, - fbuf, - stat, - setp, - tu, - ft, - stopi, - stopo - ); - - parameter DATAWIDTH = 32; - parameter DATADEPTH = 32; - parameter FIFODEPTH = 9; - - `include "utility.v" - - input clk; - input rst; - - input fifonf; - input fifocnf; - input fifoval; - input [FIFODEPTH - 1:0] fifolev; - output fifowe; - wire fifowe; - output fifoeof; - wire fifoeof; - output [DATAWIDTH / 8 - 1:0] fifobe; - reg [DATAWIDTH / 8 - 1:0] fifobe; - output [DATAWIDTH - 1:0] fifodata; - wire [DATAWIDTH - 1:0] fifodata; - - output ic; - reg ic; - output ac; - reg ac; - output dpd; - reg dpd; - output [DATADEPTH - 1:0] statado; - wire [DATADEPTH - 1:0] statado; - - input csne; - input lo; - input nc; - input lc; - input ec; - input de; - input ur; - input [3:0] cc; - input [DATADEPTH - 1:0] statadi; - output cachere; - wire cachere; - - input dmaack; - input dmaeob; - input [DATAWIDTH - 1:0] dmadatai; - input [DATADEPTH - 1:0] dmaaddr; - output dmareq; - wire dmareq; - output dmawr; - wire dmawr; - output [FIFODEPTH_MAX - 1:0] dmacnt; - wire [FIFODEPTH_MAX - 1:0] dmacnt; - output [DATADEPTH - 1:0] dmaaddro; - reg [DATADEPTH - 1:0] dmaaddro; - output [DATAWIDTH - 1:0] dmadatao; - reg [DATAWIDTH - 1:0] dmadatao; - - output fwe; - wire fwe; - output [ADDRWIDTH - 1:0] fdata; - wire [ADDRWIDTH - 1:0] fdata; - output [ADDRDEPTH - 1:0] faddr; - wire [ADDRDEPTH - 1:0] faddr; - - input [4:0] dsl; - input [5:0] pbl; - input poll; - input dbadc; - input [DATADEPTH - 1:0] dbad; - output pollack; - wire pollack; - - input tcompack; - output tcomp; - wire tcomp; - output des; - reg des; - output fbuf; - reg fbuf; - output stat; - reg stat; - output setp; - reg setp; - output tu; - reg tu; - output [1:0] ft; - reg [1:0] ft; - - input stopi; - output stopo; - reg stopo; - - - wire [DATAWIDTH_MAX + 1:0] dmadatai_max; - reg [DATAWIDTH_MAX - 1:0] dataimax_r; - wire [1:0] dataimax_r10; - wire [2:0] dmaaddr20; - reg req_c; - reg req; - reg [2:0] req_r; - - reg idmareq; - wire [31:0] datao32; - wire [FIFODEPTH_MAX - 1:0] bsmax; - wire [FIFODEPTH_MAX - 1:0] flmax; - wire [FIFODEPTH - 1:0] flmax_sub; - wire [FIFODEPTH_MAX - 1:0] blmax; - reg fl_g_bs; - reg fl_g_bl; - reg bl_g_bs; - reg pblz; - reg buffetch; - reg dmaack_r; - - reg [3:0] lsm_c; - reg [3:0] lsm; - reg [3:0] lsm_r; - reg [2:0] csm_c; - reg [2:0] csm; - reg [2:0] lsmcnt; - reg tsprog; - reg [DATADEPTH - 1:0] statad; - wire es_c; - reg own_c; - reg own; - reg tch; - reg ter; - reg set; - reg tls; - reg tfs; - wire [10:0] bs_c; - wire [1:0] bs_c10; - reg [10:0] bs1; - reg [10:0] bs2; - reg adwrite; - reg [DATADEPTH - 1:0] bad; - reg [DATADEPTH - 1:0] dad; - reg dbadc_r; - wire [31:0] tstat; - reg lastdma; - reg icachere; - reg poll_r; - reg [FIFODEPTH_MAX - 1:0] dmacnt_c; - reg [FIFODEPTH_MAX - 1:0] dmacnt_r; - - wire [1:0] addsel16; - wire [3:0] addsel32; - reg [3:0] addv_c; - reg [1:0] badd_c; - reg [11:0] bcnt; - reg ififowe; - wire bufwe; - wire firstb_c; - reg firstb; - reg [DATAWIDTH - 1:0] buf0_c; - reg [DATAWIDTH * 2 - 9:0] buf_c; - reg [DATAWIDTH * 2 - 9:0] buf_r; - reg [3:0] buflev_c; - reg [3:0] buflev; - reg [DATAWIDTH / 8 - 1:0] firstbe; - reg [DATAWIDTH / 8 - 1:0] lastbe; - reg [DATAWIDTH / 8 - 1:0] be; - wire [1:0] be10; - wire [3:0] be30; - - reg itcomp; - reg tcompack_r; - - reg ifwe; - reg [ADDRDEPTH - 1:0] ifaddr; - - reg stop_r; - - wire [FIFODEPTH_MAX - 1:0] fzero_max; - wire [DATAWIDTH_MAX + 1:0] dzero_max; - wire [DATAWIDTH_MAX * 2 - 7:0] buf_r_max; - wire [DATAWIDTH_MAX * 2 - 7:0] bufzero_max; - - - always @(posedge clk) - begin : idmareq_reg_proc - if (rst) - begin - idmareq <= 1'b0 ; - end - else - begin - if (req_c) - begin - idmareq <= 1'b1 ; - end - else if (dmaack & dmaeob) - begin - idmareq <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : cachere_reg_proc - if (rst) - begin - icachere <= 1'b0 ; - end - else - begin - if (itcomp & tcompack_r) - begin - icachere <= 1'b1 ; - end - else - begin - icachere <= 1'b0 ; - end - end - end - - assign cachere = icachere ; - - always @(lsm or - csm or - poll_r or - dmaack or - dmaeob or - own_c or - tch or - bs1 or - bs2 or - stop_r or - lsmcnt or - fifocnf or - tsprog or - lastdma or - dbadc_r) - begin : lsm_proc - case (lsm) - LSM_IDLE : - begin - if (!dbadc_r & !stop_r & fifocnf & (poll_r | (tsprog & dmaack & dmaeob))) - begin - lsm_c <= LSM_DES0 ; - end - else - begin - lsm_c <= LSM_IDLE ; - end - end - LSM_DES0 : - begin - if (dmaack & dmaeob & !tsprog) - begin - if (own_c) - begin - lsm_c <= LSM_DES1 ; - end - else - begin - lsm_c <= LSM_IDLE ; - end - end - else - begin - lsm_c <= LSM_DES0 ; - end - end - LSM_DES1 : - begin - if (dmaack & dmaeob & !tsprog) - begin - lsm_c <= LSM_DES2 ; - end - else - begin - lsm_c <= LSM_DES1 ; - end - end - LSM_DES2 : - begin - if (dmaack & dmaeob & !tsprog) - begin - if (bs1 == 11'b00000000000 | csm == CSM_IDLE) - begin - lsm_c <= LSM_DES3 ; - end - else - begin - lsm_c <= LSM_BUF1 ; - end - end - else - begin - lsm_c <= LSM_DES2 ; - end - end - LSM_DES3 : - begin - if (dmaack & dmaeob & !tsprog) - begin - if (bs2 == 11'b00000000000 | tch | csm == CSM_IDLE) - begin - lsm_c <= LSM_NXT ; - end - else - begin - lsm_c <= LSM_BUF2 ; - end - end - else - begin - lsm_c <= LSM_DES3 ; - end - end - LSM_BUF1 : - begin - if (!tsprog & dmaack & dmaeob & lastdma) - begin - lsm_c <= LSM_DES3 ; - end - else - begin - lsm_c <= LSM_BUF1 ; - end - end - LSM_BUF2 : - begin - if (!tsprog & dmaack & dmaeob & lastdma) - begin - lsm_c <= LSM_NXT ; - end - else - begin - lsm_c <= LSM_BUF2 ; - end - end - LSM_NXT : - begin - if (lsmcnt == 3'b000) - begin - if (csm == CSM_L | csm == CSM_FL) - begin - if (stop_r | !fifocnf) - begin - lsm_c <= LSM_IDLE ; - end - else - begin - lsm_c <= LSM_DES0 ; - end - end - else - begin - lsm_c <= LSM_STAT ; - end - end - else - begin - lsm_c <= LSM_NXT ; - end - end - default : - begin - if (dmaack & dmaeob & !tsprog) - begin - if (stop_r) - begin - lsm_c <= LSM_IDLE ; - end - else - begin - lsm_c <= LSM_DES0 ; - end - end - else - begin - lsm_c <= LSM_STAT ; - end - end - endcase - end - - always @(posedge clk) - begin : lsm_reg_proc - if (rst) - begin - lsm <= LSM_IDLE ; - lsm_r <= LSM_IDLE ; - end - else - begin - lsm <= lsm_c ; - lsm_r <= lsm ; - end - end - - always @(csm or lsm or tfs or tls or own or set or bs1 or bs2) - begin : csm_proc - case (csm) - CSM_IDLE : - begin - if (lsm == LSM_DES2) - begin - if (!set & tfs & tls) - begin - csm_c <= CSM_FL ; - end - else if (!set & tfs & !tls) - begin - csm_c <= CSM_F ; - end - else if (set & !tfs & !tls) - begin - csm_c <= CSM_SET ; - end - else - begin - csm_c <= CSM_IDLE ; - end - end - else - begin - csm_c <= CSM_IDLE ; - end - end - CSM_FL : - begin - if (lsm == LSM_DES0 | lsm == LSM_IDLE) - begin - csm_c <= CSM_IDLE ; - end - else if (lsm == LSM_DES2 & - bs1 == 11'b00000000000 & - bs2 == 11'b00000000000) - begin - csm_c <= CSM_BAD ; - end - else - begin - csm_c <= CSM_FL ; - end - end - CSM_F : - begin - if (tls) - begin - csm_c <= CSM_L ; - end - else if (lsm == LSM_DES1 & !tfs) - begin - csm_c <= CSM_I ; - end - else - begin - csm_c <= CSM_F ; - end - end - CSM_L : - begin - if (lsm == LSM_DES0 | lsm == LSM_IDLE) - begin - csm_c <= CSM_IDLE ; - end - else - begin - csm_c <= CSM_L ; - end - end - CSM_SET : - begin - if (lsm == LSM_DES0 | lsm == LSM_IDLE) - begin - csm_c <= CSM_IDLE ; - end - else - begin - csm_c <= CSM_SET ; - end - end - CSM_I : - begin - if (tls) - begin - csm_c <= CSM_L ; - end - else - begin - csm_c <= CSM_I ; - end - end - default : - begin - if (lsm == LSM_NXT) - begin - csm_c <= CSM_IDLE ; - end - else - begin - csm_c <= CSM_BAD ; - end - end - endcase - end - - always @(posedge clk) - begin : csm_reg_proc - if (rst) - begin - csm <= CSM_IDLE ; - end - else - begin - csm <= csm_c ; - end - end - - always @(posedge clk) - begin : lsmcnt_reg_proc - if (rst) - begin - lsmcnt <= {3{1'b1}} ; - end - else - begin - if (lsm == LSM_NXT) - begin - lsmcnt <= lsmcnt - 1 ; - end - else - begin - lsmcnt <= {3{1'b1}} ; - end - end - end - - always @(posedge clk) - begin : poll_reg_proc - if (rst) - begin - poll_r <= 1'b0 ; - end - else - begin - if (poll) - begin - poll_r <= 1'b1 ; - end - else if (!dbadc_r) - begin - poll_r <= 1'b0 ; - end - end - end - - assign pollack = poll_r ; - - always @(own or dmaack or dmaeob or lsm or dmadatai_max or tsprog) - begin : own_proc - if (dmaack & dmaeob & lsm == LSM_DES0 & !tsprog) - begin - own_c <= dmadatai_max[DATAWIDTH - 1] ; - end - else - begin - own_c <= own ; - end - end - - always @(posedge clk) - begin : own_reg_proc - if (rst) - begin - own <= 1'b1 ; - end - else - begin - own <= own_c ; - end - end - - always @(posedge clk) - begin : des1_reg_proc - reg ft22; - if (rst) - begin - ft22 = 1'b0; - tls <= 1'b0 ; - tfs <= 1'b0 ; - set <= 1'b0 ; - ac <= 1'b0 ; - ter <= 1'b0 ; - tch <= 1'b0 ; - dpd <= 1'b0 ; - ic <= 1'b0 ; - bs2 <= {11{1'b0}} ; - bs1 <= {11{1'b0}} ; - ft <= {2{1'b0}} ; - end - else - begin - if (lsm == LSM_DES1 & dmaack & !tsprog) - begin - case (DATAWIDTH) - 8 : - begin - case (dmaaddr20) - 3'b000, 3'b100 : - begin - bs1[7:0] <= dmadatai_max[7:0] ; - end - 3'b001, 3'b101 : - begin - bs1[10:8] <= dmadatai_max[2:0] ; - bs2[4:0] <= dmadatai_max[7:3] ; - end - 3'b010, 3'b110 : - begin - bs2[10:5] <= dmadatai_max[5:0] ; - dpd <= dmadatai_max[7] ; - ft22 = dmadatai_max[6]; - end - default : - begin - ic <= dmadatai_max[7] ; - tls <= dmadatai_max[6] ; - tfs <= dmadatai_max[5] ; - set <= dmadatai_max[3] ; - ac <= dmadatai_max[2] ; - ter <= dmadatai_max[1] ; - tch <= dmadatai_max[0] ; - if (dmadatai_max[3]) - begin - ft <= {dmadatai_max[4], ft22} ; - end - end - endcase - end - 16 : - begin - case (dmaaddr20) - 3'b000, 3'b100 : - begin - bs1[10:0] <= dmadatai_max[10:0] ; - bs2[4:0] <= dmadatai_max[15:11] ; - end - default : - begin - bs2[10:5] <= dmadatai_max[5:0] ; - ic <= dmadatai_max[15] ; - tls <= dmadatai_max[14] ; - tfs <= dmadatai_max[13] ; - set <= dmadatai_max[11] ; - ac <= dmadatai_max[10] ; - ter <= dmadatai_max[9] ; - tch <= dmadatai_max[8] ; - dpd <= dmadatai_max[7] ; - if (dmadatai_max[11]) - begin - ft <= {dmadatai_max[12], dmadatai_max[6]} ; - end - end - endcase - end - default : - begin - ic <= dmadatai_max[31] ; - tls <= dmadatai_max[30] ; - tfs <= dmadatai_max[29] ; - set <= dmadatai_max[27] ; - ac <= dmadatai_max[26] ; - ter <= dmadatai_max[25] ; - tch <= dmadatai_max[24] ; - dpd <= dmadatai_max[23] ; - bs2 <= dmadatai_max[21:11] ; - bs1 <= dmadatai_max[10:0] ; - if (dmadatai_max[27]) - begin - ft <= {dmadatai_max[28], dmadatai_max[22]} ; - end - end - endcase - end - end - end - - always @(posedge clk) - begin : adwrite_reg_proc - if (rst) - begin - adwrite <= 1'b0 ; - end - else - begin - if (dmaack & dmaeob & !tsprog) - begin - adwrite <= 1'b1 ; - end - else - begin - adwrite <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : dbadc_reg_proc - if (rst) - begin - dbadc_r <= 1'b0 ; - end - else - begin - dbadc_r <= dbadc ; - end - end - - always @(posedge clk) - begin : dad_reg_proc - if (rst) - begin - dad <= {DATADEPTH{1'b1}} ; - end - else - begin - if (dbadc_r) - begin - dad <= dbad ; - end - else if (adwrite) - begin - case (lsm_r) - LSM_DES3 : - begin - if (ter) - begin - dad <= dbad ; - end - else if (tch) - begin - dad <= dataimax_r[DATADEPTH - 1:0] ; - end - else - begin - dad <= dmaaddr + ({dsl, 2'b00}) ; - end - end - LSM_DES0 : - begin - if (own) - begin - dad <= dmaaddr ; - end - end - LSM_DES2 : - begin - dad <= dmaaddr ; - end - LSM_DES1 : - begin - dad <= dmaaddr ; - end - default : - begin - end - endcase - end - end - end - - always @(posedge clk) - begin : bad_reg_proc - if (rst) - begin - bad <= {DATADEPTH{1'b1}} ; - end - else - begin - if (adwrite) - begin - if (lsm_r == LSM_DES2 | lsm_r == LSM_DES3) - begin - case (DATAWIDTH) - 8 : - begin - bad <= dataimax_r[DATADEPTH - 1:0] ; - end - 16 : - begin - bad <= {dataimax_r[DATADEPTH - 1:1], 1'b0} ; - end - default : - begin - bad <= {dataimax_r[DATADEPTH - 1:2], 2'b00} ; - end - endcase - end - else - begin - bad <= dmaaddr ; - end - end - end - end - - always @(posedge clk) - begin : stataddr_reg_proc - if (rst) - begin - statad <= {DATADEPTH{1'b1}} ; - end - else - begin - if (lsm_r == LSM_DES0 & adwrite & own) - begin - statad <= dad ; - end - end - end - - assign statado = statad ; - - assign bs_c = (lsm_r == LSM_DES2) ? bs1 : bs2 ; - - assign addsel16 = {dataimax_r[0], bs_c[0]} ; - - assign addsel32 = {dataimax_r10, bs_c10} ; - - always @(addsel16 or addsel32) - begin : badd_proc - case (DATAWIDTH) - 8 : - begin - badd_c <= 2'b00 ; - end - 16 : - begin - if (addsel16 == 2'b01 | - addsel16 == 2'b10 | - addsel16 == 2'b11) - begin - badd_c <= 2'b01 ; - end - else - begin - badd_c <= 2'b00 ; - end - end - default : - begin - case (addsel32) - 4'b0000 : - begin - badd_c <= 2'b00 ; - end - 4'b1011, 4'b1110, 4'b1111 : - begin - badd_c <= 2'b10 ; - end - default : - begin - badd_c <= 2'b01 ; - end - endcase - end - endcase - end - - always @(posedge clk) - begin : bcnt_reg_proc - if (rst) - begin - bcnt <= {12{1'b1}} ; - end - else - begin - case (DATAWIDTH) - 8 : - begin - if (lsm_r == LSM_DES2 | lsm_r == LSM_DES3) - begin - bcnt <= {1'b0, bs_c} ; - end - else if (dmaack & !tsprog) - begin - bcnt <= bcnt - 1 ; - end - end - 16 : - begin - if (lsm_r == LSM_DES2 | lsm_r == LSM_DES3) - begin - bcnt <= {(({1'b0, bs_c[10:1]}) + badd_c), 1'b0} ; - end - else if (dmaack & !tsprog) - begin - bcnt <= {(bcnt[11:1] - 1), 1'b0} ; - end - end - default : - begin - if (lsm_r == LSM_DES2 | lsm_r == LSM_DES3) - begin - bcnt <= {(({1'b0, bs_c[10:2]}) + badd_c), 2'b00} ; - end - else if (dmaack & !tsprog) - begin - bcnt <= {(bcnt[11:2] - 1), 2'b00} ; - end - end - endcase - end - end - - - assign bs_c10 = bs_c[1:0] ; - - assign dataimax_r10 = dataimax_r[1:0] ; - - always @(posedge clk) - begin : firstbe_reg_proc - if (rst) - begin - firstbe <= {(DATAWIDTH/8){1'b1}} ; - end - else - begin - if (lsm_r == LSM_DES2 | lsm_r == LSM_DES3) - begin - case (DATAWIDTH) - 8 : - begin - firstbe <= 1'b1 ; - end - 16 : - begin - if (dataimax_r[0]) - begin - firstbe <= 2'b10 ; - end - else - begin - firstbe <= 2'b11 ; - end - end - default : - begin - case (dataimax_r10) - 2'b00 : - begin - firstbe <= 4'b1111 ; - end - 2'b01 : - begin - firstbe <= 4'b1110 ; - end - 2'b10 : - begin - firstbe <= 4'b1100 ; - end - default : - begin - firstbe <= 4'b1000 ; - end - endcase - end - endcase - end - end - end - - always @(posedge clk) - begin : lastbe_reg_proc - if (rst) - begin - lastbe <= {(DATAWIDTH/8){1'b1}} ; - end - else - begin - if (lsm_r == LSM_DES2 | lsm_r == LSM_DES3) - begin - case (DATAWIDTH) - 8 : - begin - lastbe <= 1'b1 ; - end - 16 : - begin - if ((!(dataimax_r[0]) & !(bs_c[0])) | - ((dataimax_r[0]) & (bs_c[0]))) - begin - lastbe <= 2'b11 ; - end - else - begin - lastbe <= 2'b01 ; - end - end - default : - begin - case (dataimax_r10) - 2'b00 : - begin - case (bs_c10) - 2'b00 : - begin - lastbe <= 4'b1111 ; - end - 2'b01 : - begin - lastbe <= 4'b0001 ; - end - 2'b10 : - begin - lastbe <= 4'b0011 ; - end - default : - begin - lastbe <= 4'b0111 ; - end - endcase - end - 2'b01 : - begin - case (bs_c10) - 2'b00 : - begin - lastbe <= 4'b0001 ; - end - 2'b01 : - begin - lastbe <= 4'b0011 ; - end - 2'b10 : - begin - lastbe <= 4'b0111 ; - end - default : - begin - lastbe <= 4'b1111 ; - end - endcase - end - 2'b10 : - begin - case (bs_c10) - 2'b00 : - begin - lastbe <= 4'b0011 ; - end - 2'b01 : - begin - lastbe <= 4'b0111 ; - end - 2'b10 : - begin - lastbe <= 4'b1111 ; - end - default : - begin - lastbe <= 4'b0001 ; - end - endcase - end - default : - begin - case (bs_c10) - 2'b00 : - begin - lastbe <= 4'b0111 ; - end - 2'b01 : - begin - lastbe <= 4'b1111 ; - end - 2'b10 : - begin - lastbe <= 4'b0001 ; - end - default : - begin - lastbe <= 4'b0011 ; - end - endcase - end - endcase - end - endcase - end - end - end - - always @(posedge clk) - begin : tfwe_reg_proc - if (rst) - begin - ififowe <= 1'b0 ; - end - else - begin - if (((DATAWIDTH == 8 & buflev_c >= 4'b0001 & bufwe) | - (DATAWIDTH ==16 & buflev_c >= 4'b0010 & bufwe) | - (DATAWIDTH ==32 & buflev_c >= 4'b0100 & bufwe) | - (buflev_c != 4'b0000 & lsm == LSM_NXT & - (csm == CSM_L | csm == CSM_FL))) & fifonf) - begin - ififowe <= 1'b1 ; - end - else - begin - ififowe <= 1'b0 ; - end - end - end - - assign fifoeof = ((csm == CSM_L | csm == CSM_FL) & - lsm == LSM_NXT & lsmcnt == 3'b001) ? 1'b1 : 1'b0 ; - - assign fifowe = ififowe ; - - assign firstb_c = (bufwe) ? 1'b0 : - (lsm == LSM_DES2 | lsm == LSM_DES3) ? 1'b1 : - firstb ; - - always @(firstb or firstbe or lastbe or dmaeob or lastdma) - begin : be_proc - if (dmaeob & lastdma) - begin - be <= lastbe ; - end - else if (firstb) - begin - be <= firstbe ; - end - else - begin - be <= {(DATAWIDTH/8){1'b1}} ; - end - end - - always @(be or be30 or dmadatai_max) - begin : tbuf0_proc - reg[15:0] buf0_16; - reg[31:0] buf0_32; - buf0_c <= {DATAWIDTH{1'b0}} ; - case (DATAWIDTH) - 8 : - begin - buf0_c <= dmadatai_max[7:0]; - end - 16 : - begin - buf0_16 = {16{1'b0}}; - if (be == 2'b10) - begin - buf0_16[7:0] = dmadatai_max[15:8]; - end - else - begin - buf0_16 = dmadatai_max[15:0]; - end - buf0_c <= buf0_16 ; - end - default : - begin - buf0_32 = {32{1'b0}}; - case (be30) - 4'b1110 : - begin - buf0_32[23:0] = dmadatai_max[31:8]; - end - 4'b1100 : - begin - buf0_32[15:0] = dmadatai_max[31:16]; - end - 4'b1000 : - begin - buf0_32[7:0] = dmadatai_max[31:24]; - end - default : - begin - buf0_32 = dmadatai_max[31:0]; - end - endcase - buf0_c <= buf0_32 ; - end - endcase - end - - always @(buflev or buf_r_max or buf0_c or bufwe or ififowe) - begin : tbuf_proc - reg[23:0] buf_16; - reg[55:0] buf_32; - case (DATAWIDTH) - 8 : - begin - buf_c <= buf0_c ; - end - 16 : - begin - buf_16 = buf_r_max[DATAWIDTH * 2 - 9:0]; - if (bufwe) - begin - case (buflev) - 4'b0000 : - begin - buf_16[15:0] = buf0_c; - end - 4'b0001 : - begin - buf_16[23:8] = buf0_c; - end - 4'b0010 : - begin - buf_16[15:0] = buf0_c; - end - default : - begin - buf_16[23:8] = buf0_c; - buf_16[7:0] = buf_r_max[23:16]; - end - endcase - end - else if (ififowe) - begin - buf_16 = {buf_r_max[23:8], buf_r_max[23:16]}; - end - buf_c <= buf_16 ; - end - default : - begin - buf_32 = buf_r_max[DATAWIDTH * 2 - 9:0]; - if (bufwe) - begin - case (buflev) - 4'b0000 : - begin - buf_32[31:0] = buf0_c; - end - 4'b0001 : - begin - buf_32[39:8] = buf0_c; - end - 4'b0010 : - begin - buf_32[47:16] = buf0_c; - end - 4'b0011 : - begin - buf_32[55:24] = buf0_c; - end - 4'b0100 : - begin - buf_32[31:0] = buf0_c; - end - 4'b0101 : - begin - buf_32[39:8] = buf0_c; - buf_32[7:0] = buf_r_max[39:32]; - end - 4'b0110 : - begin - buf_32[47:16] = buf0_c; - buf_32[15:0] = buf_r_max[47:32]; - end - default : - begin - buf_32[55:24] = buf0_c; - buf_32[23:0] = buf_r_max[55:32]; - end - endcase - end - else if (ififowe) - begin - buf_32 = {buf_r_max[55:24], buf_r_max[55:32]}; - end - buf_c <= buf_32 ; - end - endcase - end - - assign bufwe = (dmaack & !set & fifonf & !tsprog & - (lsm == LSM_BUF1 | lsm == LSM_BUF2)) ? 1'b1 : 1'b0 ; - - assign fifodata = buf_r_max[DATAWIDTH - 1:0] ; - - assign be10 = (DATAWIDTH == 16) ? be : {2{1'b1}} ; - - assign be30 = (DATAWIDTH == 32) ? be : {4{1'b1}} ; - - always @(be10 or be30) - begin : addv_proc - case (DATAWIDTH) - 8 : - begin - addv_c <= 4'b0000 ; - end - 16 : - begin - case (be10) - 2'b01, 2'b10 : - begin - addv_c <= 4'b0001 ; - end - default : - begin - addv_c <= 4'b0010 ; - end - endcase - end - default : - begin - case (be30) - 4'b0001, 4'b1000 : - begin - addv_c <= 4'b0001 ; - end - 4'b0011, 4'b1100 : - begin - addv_c <= 4'b0010 ; - end - 4'b0111, 4'b1110 : - begin - addv_c <= 4'b0011 ; - end - default : - begin - addv_c <= 4'b0100 ; - end - endcase - end - endcase - end - - always @(buflev or bufwe or ififowe or addv_c) - begin : buflev_proc - case (DATAWIDTH) - 8 : - begin - if (bufwe) - begin - buflev_c <= 4'b0001 ; - end - else if (ififowe) - begin - buflev_c <= 4'b0000 ; - end - else - begin - buflev_c <= buflev ; - end - end - 16 : - begin - if (bufwe) - begin - buflev_c <= ({buflev[3:2], 1'b0, buflev[0]}) + addv_c ; - end - else if (ififowe & (buflev[1])) - begin - buflev_c <= {buflev[3:2], 1'b0, buflev[0]} ; - end - else if (ififowe & !(buflev[1])) - begin - buflev_c <= {buflev[3:1], 1'b0} ; - end - else - begin - buflev_c <= buflev ; - end - end - default : - begin - if (bufwe) - begin - buflev_c <= ({buflev[3:3], 1'b0, buflev[1:0]}) + addv_c ; - end - else if (ififowe & (buflev[2])) - begin - buflev_c <= {buflev[3:3], 1'b0, buflev[1:0]} ; - end - else if (ififowe & !(buflev[2])) - begin - buflev_c <= {buflev[3:2], 2'b00} ; - end - else - begin - buflev_c <= buflev ; - end - end - endcase - end - - always @(posedge clk) - begin : buf_reg_proc - if (rst) - begin - buflev <= {4{1'b0}} ; - firstb <= 1'b1 ; - buf_r <= {(DATAWIDTH*2){1'b0}} ; - end - else - begin - buflev <= buflev_c ; - firstb <= firstb_c ; - buf_r <= buf_c ; - end - end - - always @(posedge clk) - begin : lbe_reg_proc - if (rst) - begin - fifobe <= {(DATAWIDTH/8){1'b1}} ; - end - else - begin - if (ififowe) - begin - case (DATAWIDTH) - 8 : - begin - fifobe <= 1'b1 ; - end - 16 : - begin - case (buflev) - 4'b0001 : - begin - fifobe <= 2'b01 ; - end - default : - begin - fifobe <= 2'b11 ; - end - endcase - end - default : - begin - case (buflev) - 4'b0001 : - begin - fifobe <= 4'b0001 ; - end - 4'b0010 : - begin - fifobe <= 4'b0011 ; - end - 4'b0011 : - begin - fifobe <= 4'b0111 ; - end - default : - begin - fifobe <= 4'b1111 ; - end - endcase - end - endcase - end - end - end - - assign es_c = ur | lc | lo | nc | ec ; - - assign tstat = {1'b0, TDES0_RV[30:16], - es_c, TDES0_RV[14:12], lo, nc, lc, - ec, TDES0_RV[7], - cc, TDES0_RV[2], ur, de}; - - assign datao32 = (tsprog) ? tstat : (set) ? SET0_RV : TDES0_RV ; - - always @(posedge clk) - begin : dataimax_reg_proc - if (rst) - begin - dataimax_r <= {DATADEPTH_MAX{1'b1}} ; - end - else - begin - case (DATAWIDTH) - 8 : - begin - case (dmaaddr20) - 3'b000, 3'b100 : - begin - dataimax_r[7:0] <= dmadatai_max[DATAWIDTH-1:0] ; - end - 3'b001, 3'b101 : - begin - dataimax_r[15:8] <= dmadatai_max[DATAWIDTH-1:0] ; - end - 3'b010, 3'b110 : - begin - dataimax_r[23:16] <= dmadatai_max[DATAWIDTH-1:0] ; - end - default : - begin - dataimax_r[31:24] <= dmadatai_max[DATAWIDTH-1:0] ; - end - endcase - end - 16 : - begin - if (!(dmaaddr[1])) - begin - dataimax_r[15:0] <= dmadatai_max[DATAWIDTH-1:0] ; - end - else - begin - dataimax_r[31:16] <= dmadatai_max[DATAWIDTH-1:0] ; - end - end - default : - begin - dataimax_r <= dmadatai_max[31:0] ; - end - endcase - end - end - - always @(datao32 or dmaaddr) - begin : datao_proc - reg[1:0] addr10; - addr10 = dmaaddr[1:0]; - case (DATAWIDTH) - 8 : - begin - case (addr10) - 2'b00 : - begin - dmadatao <= datao32[7:0] ; - end - 2'b01 : - begin - dmadatao <= datao32[15:8] ; - end - 2'b10 : - begin - dmadatao <= datao32[23:16] ; - end - default : - begin - dmadatao <= datao32[31:24] ; - end - endcase - end - 16 : - begin - if (!(addr10[1])) - begin - dmadatao <= datao32[15:0] ; - end - else - begin - dmadatao <= datao32[31:16] ; - end - end - default : - begin - dmadatao <= datao32 ; - end - endcase - end - - assign flmax_sub = fzero_max[FIFODEPTH - 1:0] - 1 - fifolev ; - - assign flmax = {fzero_max[FIFODEPTH_MAX - 1:FIFODEPTH], - flmax_sub} ; - - assign blmax = {fzero_max[FIFODEPTH_MAX - 1:6], pbl} ; - - assign bsmax = (DATAWIDTH == 8) ? {fzero_max[FIFODEPTH_MAX - 1:12], - bcnt} : - (DATAWIDTH ==16) ? {fzero_max[FIFODEPTH_MAX - 1:11], - bcnt[11:1]} : - {fzero_max[FIFODEPTH_MAX - 1:10], - bcnt[11:2]} ; - - always @(posedge clk) - begin : fifolev_reg_proc - if (rst) - begin - fl_g_bs <= 1'b0 ; - fl_g_bl <= 1'b0 ; - bl_g_bs <= 1'b0 ; - pblz <= 1'b0 ; - end - else - begin - if (flmax >= bsmax) - begin - fl_g_bs <= 1'b1 ; - end - else - begin - fl_g_bs <= 1'b0 ; - end - - if (flmax >= blmax) - begin - fl_g_bl <= 1'b1 ; - end - else - begin - fl_g_bl <= 1'b0 ; - end - - if (blmax >= bsmax) - begin - bl_g_bs <= 1'b1 ; - end - else - begin - bl_g_bs <= 1'b0 ; - end - - if (pbl == 6'b000000) - begin - pblz <= 1'b1 ; - end - else - begin - pblz <= 1'b0 ; - end - end - end - - always @(csm or - lsm or - pblz or - tsprog or - fl_g_bs or - fl_g_bl or - bl_g_bs or - blmax or - bsmax or - flmax or - fzero_max or - buffetch or - dmacnt_r) - begin : dmacnt_proc - if (lsm == LSM_DES0 | - lsm == LSM_DES1 | - lsm == LSM_DES2 | - lsm == LSM_DES3 | - lsm == LSM_STAT | tsprog) - begin - case (DATAWIDTH) - 8 : - begin - dmacnt_c <= {fzero_max[FIFODEPTH_MAX - 1:3], 3'b100} ; - end - 16 : - begin - dmacnt_c <= {fzero_max[FIFODEPTH_MAX - 1:3], 3'b010} ; - end - default : - begin - dmacnt_c <= {fzero_max[FIFODEPTH_MAX - 1:3], 3'b001} ; - end - endcase - end - else if(!buffetch) - begin - if (pblz) - begin - if (fl_g_bs | csm == CSM_SET) - begin - dmacnt_c <= bsmax ; - end - else - begin - dmacnt_c <= flmax ; - end - end - else - begin - if (fl_g_bl | csm == CSM_SET) - begin - if (bl_g_bs) - begin - dmacnt_c <= bsmax ; - end - else - begin - dmacnt_c <= blmax ; - end - end - else - begin - if (fl_g_bs) - begin - dmacnt_c <= bsmax ; - end - else - begin - dmacnt_c <= flmax ; - end - end - end - end - else - begin - dmacnt_c <= dmacnt_r; - end - end - - always @(posedge clk) - begin : dmacnt_reg_proc - if (rst) - begin - dmacnt_r <= {FIFODEPTH_MAX{1'b0}}; - end - else - begin - dmacnt_r <= dmacnt_c; - end - end - - assign dmacnt = dmacnt_c; - - always @(posedge clk) - begin : lastdma_reg_proc - if (rst) - begin - lastdma <= 1'b1 ; - end - else - begin - if (lsm == LSM_DES0 | - lsm == LSM_DES1 | - lsm == LSM_DES2 | - lsm == LSM_DES3 | - lsm == LSM_STAT | tsprog) - begin - lastdma <= 1'b1 ; - end - else if (!buffetch) - begin - if (pblz) - begin - if (fl_g_bs | csm == CSM_SET) - begin - lastdma <= 1'b1 ; - end - else - begin - lastdma <= 1'b0 ; - end - end - else - begin - if (fl_g_bl | csm == CSM_SET) - begin - if (bl_g_bs) - begin - lastdma <= 1'b1 ; - end - else - begin - lastdma <= 1'b0 ; - end - end - else - begin - if (fl_g_bs) - begin - lastdma <= 1'b1 ; - end - else - begin - lastdma <= 1'b0 ; - end - end - end - end - end - end - - always @(tsprog or lsm or statadi or bad or dad or statad) - begin : dmaaddro_proc - if (tsprog) - begin - dmaaddro <= statadi ; - end - else - begin - case (lsm) - LSM_BUF1, LSM_BUF2 : - begin - dmaaddro <= bad ; - end - LSM_STAT : - begin - dmaaddro <= statad ; - end - default : - begin - dmaaddro <= dad ; - end - endcase - end - end - - always @(req or - dmaack or - dmaeob or - lsm or - tsprog or - fifoval or - req_r) - begin : req_proc - case (lsm) - LSM_BUF1, LSM_BUF2 : - begin - if (dmaack & dmaeob) - begin - req_c <= 1'b0 ; - end - else if ((fifoval & req_r == 3'b000) | tsprog) - begin - req_c <= 1'b1 ; - end - else - begin - req_c <= req ; - end - end - LSM_DES0, LSM_DES1, LSM_DES2, LSM_DES3, LSM_STAT : - begin - if (dmaack) - begin - req_c <= 1'b0 ; - end - else - begin - req_c <= 1'b1 ; - end - end - default : - begin - if (dmaack) - begin - req_c <= 1'b0 ; - end - else if (tsprog) - begin - req_c <= 1'b1 ; - end - else - begin - req_c <= 1'b0 ; - end - end - endcase - end - - always @(posedge clk) - begin : req_reg_proc - if (rst) - begin - req <= 1'b0 ; - req_r <= {3{1'b0 }}; - dmaack_r <= 1'b0 ; - end - else - begin - req <= req_c ; - req_r[0] <= req; - req_r[1] <= req_r[0]; - req_r[2] <= req_r[1]; - dmaack_r <= dmaack & dmaeob ; - end - end - - assign dmawr = (tsprog | lsm == LSM_STAT) ? 1'b1 : 1'b0 ; - - assign dmareq = req ; - - always @(posedge clk) - begin : stat_reg_proc - if (rst) - begin - des <= 1'b0 ; - fbuf <= 1'b0 ; - stat <= 1'b0 ; - tsprog <= 1'b0 ; - buffetch <= 1'b0 ; - tu <= 1'b0 ; - end - else - begin - if (lsm == LSM_DES0 | - lsm == LSM_DES1 | - lsm == LSM_DES2 | - lsm == LSM_DES3) - begin - des <= 1'b1 ; - end - else - begin - des <= 1'b0 ; - end - - if (lsm == LSM_BUF1 | lsm == LSM_BUF2) - begin - fbuf <= 1'b1 ; - end - else - begin - fbuf <= 1'b0 ; - end - - if (tsprog) - begin - stat <= 1'b1 ; - end - else - begin - stat <= 1'b0 ; - end - - if ((dmaeob & dmaack) | itcomp | tcompack_r) - begin - tsprog <= 1'b0 ; - end - else if (csne & !idmareq & !icachere) - begin - tsprog <= 1'b1 ; - end - - if (dmaack_r) - begin - buffetch <= 1'b0 ; - end - else if (req_r[0] & (lsm == LSM_BUF1 | lsm == LSM_BUF2)) - begin - buffetch <= 1'b1 ; - end - - if (lsm == LSM_IDLE & !own) - begin - tu <= 1'b1 ; - end - else if (own_c) - begin - tu <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : tcompack_reg_proc - if (rst) - begin - tcompack_r <= 1'b0 ; - itcomp <= 1'b0 ; - end - else - begin - tcompack_r <= tcompack ; - - if (tsprog & dmaeob & dmaack) - begin - itcomp <= 1'b1 ; - end - else if (tcompack_r) - begin - itcomp <= 1'b0 ; - end - end - end - - assign tcomp = itcomp ; - - always @(posedge clk) - begin : setp_reg_proc - if (rst) - begin - setp <= 1'b0 ; - end - else - begin - if (csm == CSM_SET) - begin - setp <= 1'b1 ; - end - else - begin - setp <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : ifaddr_reg_proc - if (rst) - begin - ifaddr <= {ADDRDEPTH{1'b0}} ; - end - else - begin - if (csm == CSM_IDLE) - begin - ifaddr <= {ADDRDEPTH{1'b0}} ; - end - else if (ifwe) - begin - ifaddr <= ifaddr + 1 ; - end - end - end - - always @(posedge clk) - begin : ifwe_reg_proc - if (rst) - begin - ifwe <= 1'b0 ; - end - else - begin - case (DATAWIDTH) - 8 : - begin - if (csm == CSM_SET & - dmaack & - dmaaddr[1:0] == 2'b11 & - lsm == LSM_BUF1) - begin - ifwe <= 1'b1 ; - end - else - begin - ifwe <= 1'b0 ; - end - end - 16 : - begin - if (csm == CSM_SET & - dmaack & - dmaaddr[1] & - lsm == LSM_BUF1) - begin - ifwe <= 1'b1 ; - end - else - begin - ifwe <= 1'b0 ; - end - end - default : - begin - if (csm == CSM_SET & dmaack & - lsm == LSM_BUF1) - begin - ifwe <= 1'b1 ; - end - else - begin - ifwe <= 1'b0 ; - end - end - endcase - end - end - - assign faddr = ifaddr ; - - assign fwe = ifwe ; - - assign fdata = dataimax_r[15:0] ; - - always @(posedge clk) - begin : stop_reg_proc - if (rst) - begin - stop_r <= 1'b1 ; - stopo <= 1'b1 ; - end - else - begin - stop_r <= stopi ; - - if (lsm == LSM_IDLE & stop_r) - begin - stopo <= 1'b1 ; - end - else - begin - stopo <= 1'b0 ; - end - end - end - - assign fzero_max = {FIFODEPTH_MAX{1'b0}} ; - - assign dzero_max = {DATAWIDTH_MAX{1'b0}} ; - - assign bufzero_max = {(DATAWIDTH_MAX * 2 - 9){1'b0}} ; - - assign dmaaddr20 = dmaaddr[2:0] ; - - assign dmadatai_max = {dzero_max[DATAWIDTH_MAX+1:DATAWIDTH], - dmadatai}; - - assign buf_r_max = {bufzero_max[DATAWIDTH_MAX * 2 - 7: - DATAWIDTH * 2 - 8], - buf_r}; - -endmodule diff --git a/resources/soc/rtl/MAC/utility.v b/resources/soc/rtl/MAC/utility.v deleted file mode 100644 index aeef9aa..0000000 --- a/resources/soc/rtl/MAC/utility.v +++ /dev/null @@ -1,282 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - - //----------------------------------------------------------------- - // 802.3 parameters - //----------------------------------------------------------------- - // interframe space 1 interval = 60 bit times - parameter [3:0] IFS1_TIME = 4'b1110; - // interframe space 2 interval = 36 bit times - //parameter [3:0] IFS2_TIME = 4'b1000; - parameter [3:0] IFS2_TIME = 4'b0110; - // slot time interfal = 512 bit times - parameter [8:0] SLOT_TIME = 9'b001111111; - // maximum number of retransmission attempts = 16 - parameter [4:0] ATT_MAX = 5'b10000; - // proper crc remainder value = 0xc704dd7b - parameter [31:0] CRCVAL = 32'b11000111000001001101110101111011; - // minimum frame size = 64 - parameter [6:0] MIN_FRAME = 7'b1000000; - // maximum ethernet frame length field value = 1500 - parameter [15:0] MAX_SIZE = 16'b0000010111011100; - // maximum frame size - parameter [13:0] MAX_FRAME = 14'b00010111101111; // 1519 - - //_________________________________________________________________ - // Control and Status Register summary - //_________________________________________________________________ - // Register | ID | RV | Description - //_________________________________________________________________ - // CSR0 | 00h | fe000000h | Bus mode - // CSR1 | 08h | ffffffffh | Transmit pool demand - // CSR2 | 10h | ffffffffh | Teceive pool demand - // CSR3 | 18h | ffffffffh | Receive list base address - // CSR4 | 20h | ffffffffh | Rransmit list base address - // CSR5 | 28h | f0000000h | Status - // CSR6 | 30h | 32000040h | Operation mode - // CSR7 | 38h | f3fe0000h | Interrupt enable - // CSR8 | 40h | e0000000h | Missed frames and overflow cnt - // CSR9 | 48h | fff483ffh | MII management - // CSR11 | 58h | fffe0000h | Timer and interrupt mitigation - //_________________________________________________________________ - - //----------------------------------------------------------------- - // Special Function Register locations and reset values - //----------------------------------------------------------------- - // CSR0 : 00h : fe000000h : Bus mode - parameter [5:0] CSR0_ID = 6'b000000; - // CSR0 reset value - parameter [31:0] CSR0_RV = 32'b11111110000000000000000000000000; - - // CSR1 : 08h : ffffffffh : Transmit pool demand - parameter [5:0] CSR1_ID = 6'b000010; - // CSR1 reset value - parameter [31:0] CSR1_RV = 32'b11111111111111111111111111111111; - - // CSR2 : 10h : ffffffffh : Receive pool demand - parameter [5:0] CSR2_ID = 6'b000100; - // CSR2 reset value - parameter [31:0] CSR2_RV = 32'b11111111111111111111111111111111; - - // CSR3 : 18h : ffffffffh : Receive list base address - parameter [5:0] CSR3_ID = 6'b000110; - // CSR3 reset value - parameter [31:0] CSR3_RV = 32'b11111111111111111111111111111111; - - // CSR4 : 20h : ffffffffh : Transmit list base address - parameter [5:0] CSR4_ID = 6'b001000; - // CSR4 reset value - parameter [31:0] CSR4_RV = 32'b11111111111111111111111111111111; - - // CSR5 : 28h : f0000000h : Status - parameter [5:0] CSR5_ID = 6'b001010; - // CSR5 reset value - parameter [31:0] CSR5_RV = 32'b11110000000000000000000000000000; - - // CSR6 : 30h : 32000040h : Operation mode - parameter [5:0] CSR6_ID = 6'b001100; - // CSR6 reset value - parameter [31:0] CSR6_RV = 32'b00110010000000000000000001000000; - - // CSR7 : 38h : f3fe0000h : Interrupt enable - parameter [5:0] CSR7_ID = 6'b001110; - // CSR7 reset value - parameter [31:0] CSR7_RV = 32'b11110011111111100000000000000000; - - // CSR8 : 40h : e0000000h : Missed frames and overflow cnt - parameter [5:0] CSR8_ID = 6'b010000; - // CSR8 reset value - parameter [31:0] CSR8_RV = 32'b11100000000000000000000000000000; - - // CSR9 : 48h : fff483ffh : MII menagement - parameter [5:0] CSR9_ID = 6'b010010; - // CSR9 reset value - parameter [31:0] CSR9_RV = 32'b11111111111101001000001111111111; - - // CSR10 : 50h : 00000000h : Insert function enable - parameter [5:0] CSR10_ID = 6'b010100; - // CSR11 reset value - parameter [31:0] CSR10_RV = 32'b00000000000000000000000000000000; - - // CSR11 : 58h : fffe0000h : Timer and interrupt mitigation - parameter [5:0] CSR11_ID = 6'b010110; - // CSR11 reset value - parameter [31:0] CSR11_RV = 32'b11111111111111100000000000000000; - - // TDES0 - parameter [31:0] TDES0_RV = 32'b00000000000000000000000000000000; - - // SET0 - parameter [31:0] SET0_RV = 32'b00000000000000000000000000000000; - - // RDES0 - parameter [31:0] RDES0_RV = 32'b00000000000000000000000000000000; - - //----------------------------------------------------------------- - // Internal interface parameters - //----------------------------------------------------------------- - // CSR interface address width - parameter CSRDEPTH = 8; - // Filtering RAM address width - parameter ADDRDEPTH = 6; - // Filtering RAM data width - parameter ADDRWIDTH = 16; - // Maximum FIFO depth - parameter FIFODEPTH_MAX = 15; - // Maximum Data interface address width - parameter DATADEPTH_MAX = 32; - // Maximum Data interface width - parameter DATAWIDTH_MAX = 32; - // Maximum CSR interface width - parameter CSRWIDTH_MAX = 32; - // MII width - parameter MIIWIDTH = 4; - parameter MIIWIDTH_MAX = 8; - - - //----------------------------------------------------------------- - // Filtering modes - //----------------------------------------------------------------- - // Filtering mode - PREFECT -- - parameter [1:0] FT_PERFECT = 2'b00; - // Filtering mode - HASH -- - parameter [1:0] FT_HASH = 2'b01; - // Filtering mode - INVERSE -- - parameter [1:0] FT_INVERSE = 2'b10; - // Filtering mode - HONLY -- - parameter [1:0] FT_HONLY = 2'b11; - - //----------------------------------------------------------------- - // Phisical address position in setup frame - //----------------------------------------------------------------- - parameter [5:0] PERF1_ADDR = 6'b100111; - - //----------------------------------------------------------------- - // Ethernet frame fields - //----------------------------------------------------------------- - // jam field pattern - parameter [63:0] JAM_PATTERN = 64'b1010101010101010101010101010101010101010101010101010101010101010; - // preamble field pattern - parameter [63:0] PRE_PATTERN = 64'b0101010101010101010101010101010101010101010101010101010101010101; - // start of frame delimiter pattern - parameter [63:0] SFD_PATTERN = 64'b1101010111010101110101011101010111010101110101011101010111010101; - // padding field pattern - parameter [63:0] PAD_PATTERN = 64'b0000000000000000000000000000000000000000000000000000000000000000; - // carrier extension pattern - parameter [63:0] EXT_PATTERN = 64'b0000111100001111000011110000111100001111000011110000111100001111; - - //----------------------------------------------------------------- - // Enumeration types - //----------------------------------------------------------------- - - // DMA state machine - parameter [1:0] DSM_IDLE = 0; - parameter [1:0] DSM_CH1 = 1; - parameter [1:0] DSM_CH2 = 2; - - // process state machine type for HC - parameter [1:0] PSM_RUN = 0; - parameter [1:0] PSM_SUSPEND = 1; - parameter [1:0] PSM_STOP = 2; - - // receive state machine for HC - parameter [2:0] RSM_IDLE = 0; - parameter [2:0] RSM_ACQ1 = 1; // trying to acquire free descriptor - parameter [2:0] RSM_ACQ2 = 2; // trying to acquire free descriptor - parameter [2:0] RSM_REC = 3; // receiving frame - parameter [2:0] RSM_STORE = 4; // storing frame - parameter [2:0] RSM_STAT = 5; // status of the frame - - // linked list state machine for HC - parameter [3:0] LSM_IDLE = 0; - parameter [3:0] LSM_DES0P = 1; // des0 prefetching - parameter [3:0] LSM_DES0 = 2; // des0 fetching - parameter [3:0] LSM_DES1 = 3; // des1 fetching - parameter [3:0] LSM_DES2 = 4; // des2 fetching - parameter [3:0] LSM_DES3 = 5; // des3 fetching - parameter [3:0] LSM_BUF1 = 6; // buffer 1 fetching - parameter [3:0] LSM_BUF2 = 7; // buffer 2 fetching - parameter [3:0] LSM_STAT = 8; // descriptor status storing - parameter [3:0] LSM_FSTAT = 9; // frame status storing - parameter [3:0] LSM_NXT = 10; // next descriptor's address computing - - // descriptor's control state machine for HC - parameter [2:0] CSM_IDLE = 0; - parameter [2:0] CSM_F = 1; // first descriptor - parameter [2:0] CSM_I = 2; // intermediate descriptor - parameter [2:0] CSM_L = 3; // last descriptor - parameter [2:0] CSM_FL = 4; // first and last descriptor - parameter [2:0] CSM_SET = 5; // setup frame descriptor - parameter [2:0] CSM_BAD = 6; // invalid descriptor - - // master interface state machine for HC - parameter [1:0] MSM_IDLE = 0; - parameter [1:0] MSM_REQ = 1; - parameter [1:0] MSM_BURST = 2; - - // receive state machine for RC - parameter [3:0] RSM_IDLE_RCSMT = 0; - parameter [3:0] RSM_SFD = 1; - parameter [3:0] RSM_DEST = 2; - parameter [3:0] RSM_SOURCE = 3; - parameter [3:0] RSM_LENGTH = 4; - parameter [3:0] RSM_INFO = 5; - parameter [3:0] RSM_SUCC = 6; - parameter [3:0] RSM_INT = 7; - parameter [3:0] RSM_INT1 = 8; - parameter [3:0] RSM_BAD = 9; // flushing received frame from fifo - - // address filtering state machine - parameter [2:0] FSM_IDLE = 0; - parameter [2:0] FSM_PERF1 = 1; // checking single physical address - parameter [2:0] FSM_PERF16 = 2; // checking 16 addresses - parameter [2:0] FSM_HASH = 3; // hash fitering - parameter [2:0] FSM_MATCH = 4; // address match - parameter [2:0] FSM_FAIL = 5; // address failed - - // deffering state machine for TC - parameter [1:0] DSM_WAIT = 0; // end of IFS, waiting for pending frame - parameter [1:0] DSM_IFS1 = 1; // calculating interframe space time 1 - parameter [1:0] DSM_IFS2 = 2; // calculating interframe space time 2 - - // transmit state machine for TC - parameter [3:0] TSM_IDLE_TCSMT = 0; - parameter [3:0] TSM_PREA = 1; - parameter [3:0] TSM_SFD = 2; - parameter [3:0] TSM_INFO = 3; - parameter [3:0] TSM_PAD = 4; - parameter [3:0] TSM_CRC = 5; - parameter [3:0] TSM_BURST = 6; - parameter [3:0] TSM_JAM = 7; - parameter [3:0] TSM_FLUSH = 8; - parameter [3:0] TSM_INT = 9; diff --git a/resources/soc/rtl/SPI/godson_sbridge_spi.v b/resources/soc/rtl/SPI/godson_sbridge_spi.v deleted file mode 100644 index 1928447..0000000 --- a/resources/soc/rtl/SPI/godson_sbridge_spi.v +++ /dev/null @@ -1,896 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -module spi_flash_ctrl( - input aclk, - input aresetn, - input [15:0] spi_addr, - input power_down_req, - output power_down_ack, - input fast_startup, - - input [3:0] s_awlen, - input [3:0] s_awcache, - input [3:0] s_awid, - input [31:0] s_awaddr, - input [2:0] s_awsize, - input [2:0] s_awprot, - input [1:0] s_awburst, - input [1:0] s_awlock, - input s_awvalid, - output s_awready, - - input [3:0] s_wid, - input [31:0] s_wdata, - input [3:0] s_wstrb, - input s_wlast, - input s_wvalid, - output s_wready, - - output [3:0] s_bid, - output [1:0] s_bresp, - output s_bvalid, - input s_bready, - - input [3:0] s_arlen, - input [3:0] s_arcache, - input [3:0] s_arid, - input [31:0] s_araddr, - input [2:0] s_arsize, - input [2:0] s_arprot, - input [1:0] s_arburst, - input [1:0] s_arlock, - input s_arvalid, - output s_arready, - - output [3:0] s_rid, - output [31:0] s_rdata, - output [1:0] s_rresp, - output s_rlast, - output s_rvalid, - input s_rready, - - output [3:0] csn_o, - output [3:0] csn_en, - output sck_o, - input sdo_i, - output sdo_o, - output sdo_en, - input sdi_i, - output sdi_o, - output sdi_en, - output inta_o -); - - wire areset = ~aresetn; - - wire param_memory_en; - wire param_burst_en; - wire param_fast_read; - wire param_dual_io; - wire [1:0] param_tCSH; - wire param_tFAST; - - reg [9:0] rd_state; - reg [9:0] rd_state_nxt; - - parameter S_IDLE = 10'b0000000001; - parameter S_IOREAD = 10'b0000000010; - parameter S_CSTURN = 10'b0000000100; - parameter S_ADDR = 10'b0000001000; - parameter S_DATA = 10'b0000010000; - parameter S_WAITBUS= 10'b0000100000; - parameter S_PDENTER= 10'b0001000000; - parameter S_PDEXIT = 10'b0010000000; - parameter S_STARTUP= 10'b0100000000; - parameter S_PWRDOWN= 10'b1000000000; - - wire s_idle = rd_state[0]; - wire s_ioread = rd_state[1]; - wire s_csturn = rd_state[2]; - wire s_addr = rd_state[3]; - wire s_data = rd_state[4]; - wire s_waitbus= rd_state[5]; - wire s_pdenter= rd_state[6]; - wire s_pdexit = rd_state[7]; - wire s_startup= rd_state[8]; - wire s_pwrdown= rd_state[9]; - - wire ns_idle = rd_state_nxt[0]; - wire ns_ioread = rd_state_nxt[1]; - wire ns_csturn = rd_state_nxt[2]; - wire ns_addr = rd_state_nxt[3]; - wire ns_data = rd_state_nxt[4]; - wire ns_waitbus= rd_state_nxt[5]; - wire ns_pdenter= rd_state_nxt[6]; - wire ns_pdexit = rd_state_nxt[7]; - wire ns_startup= rd_state_nxt[8]; - wire ns_pwrdown= rd_state_nxt[9]; - - reg pdreq_r; - - reg [15:0] cs_timer; - reg cs; - reg [23:0] nxt_addr; - - wire write_valid; - wire reg_acc = s_ioread | write_valid; - wire reg_ack; - wire [7:0] reg_dat_i, reg_dat_o; - wire [7:0] param_o; - - reg [31:0] shift_reg; - reg [ 1:0] sample; - wire [31:0] shift_reg_nxt; - wire sr_shift_inst; - wire sr_shift_one; - wire sr_shift_two; - reg sr_shift_inst_r; - reg sr_shift_two_r; - wire sample_en; - wire shift_en; - wire dual_out; - wire dual_in; - wire [1:0] serial_out; - wire cyc_end; - - - reg [2:0] bit_cnt; - wire spi_pause; - wire spibus_busy; - - reg [5:0] adbit_cnt; - reg spi_run; - reg sck; - - reg buf_busy; - reg [31:0] buf_addr; - reg [ 3:0] buf_len; - reg [ 2:0] buf_size; - reg [ 3:0] buf_id; - reg buf_write; - reg buf_wrap; - - assign s_arready = s_idle & ~pdreq_r & ~buf_busy & ~s_awvalid; - assign s_awready = s_idle & ~pdreq_r & ~buf_busy; - - reg buf_busy_d; - wire new_axireq = ~buf_busy_d & buf_busy; - wire io_hit =(buf_addr[31:4] == {spi_addr, 12'b0}) & - (buf_len == 4'b0); - - wire [63:0] buf_addr_t = (buf_addr[31:20]==12'h1fc)? - {12'h0, buf_addr[19:0]}: - { 8'h0, buf_addr[23:0]}; - - wire burst_cont = param_burst_en & cs & - (buf_addr_t[23:0] == nxt_addr[23:0]); - - wire burst_switch = param_burst_en & cs & - (buf_addr_t[23:0] != nxt_addr[23:0]); - - reg [7:0] tot_bytes; - wire byte_ready; - - always @(posedge aclk) begin - if (areset) begin - buf_busy <= 1'b0; - buf_write <= 1'b0; - tot_bytes <= 8'b0; - end else begin - if ((s_arvalid|s_awvalid)&~buf_busy&s_idle&~pdreq_r) begin - buf_busy <= 1'b1; - buf_addr <= s_awvalid ? s_awaddr : s_araddr; - buf_size <= s_awvalid ? s_awsize : s_arsize; - buf_len <= s_awvalid ? s_awlen : s_arlen; - buf_id <= s_awvalid ? s_awid : s_arid; - buf_write<= s_awvalid; - buf_wrap <= s_arvalid & (s_arburst==2'b10) & - (|s_araddr[4:2]) & (|s_arlen); - tot_bytes<= {8{s_arvalid&~s_awvalid}}& - (({4'b0,s_arlen} << s_arsize)| - ((8'b1<=6'd8) | s_data) & param_dual_io; - always @(posedge aclk) begin - sr_shift_inst_r <= areset ? 1'b0 : - cyc_end|(~s_addr&ns_addr) ? ns_addr & (adbit_cnt < 6'd7) : - sr_shift_inst_r; - sr_shift_two_r <= areset ? 1'b0 : - cyc_end|(~s_data&ns_data) ? (s_addr & (adbit_cnt >=6'd7) | ns_data) & param_dual_io : - sr_shift_two_r; - end - - assign sr_shift_one = 1'bz; - wire addr_done; - assign addr_done = param_dual_io ? adbit_cnt == 6'd23 : - param_fast_read ? adbit_cnt == 6'd39 : - adbit_cnt == 6'd31 ; - assign dual_out = param_dual_io & - (adbit_cnt >= 6'd8 && adbit_cnt < 6'd22); - reg dual_in_r; - assign dual_in = param_dual_io & - (adbit_cnt >= 6'd22 | s_data | dual_in_r); - always @(posedge aclk) begin - dual_in_r <= areset ? 1'b0 : - s_csturn&cswcnt[0]? 1'b0 : - ~cs ? 1'b0 : - dual_in ? 1'b1 : dual_in_r; - end - - - always @(posedge aclk) begin - pdreq_r <= power_down_req; - end - wire go_power_down = pdreq_r & ~buf_busy; - assign power_down_ack = s_pwrdown | s_pdexit | s_startup; - - always @(posedge aclk) begin - rd_state <= areset ? S_PWRDOWN : rd_state_nxt; - end - - always @(*) begin - rd_state_nxt = rd_state; - case (rd_state) // synopsys parallel_case - S_IDLE :if (new_axireq & ~buf_write) begin - rd_state_nxt = io_hit ? S_IOREAD: - spibus_busy ? S_WAITBUS: - burst_cont ? S_DATA : - S_CSTURN; - end else if (go_power_down) begin - rd_state_nxt = cs ? S_CSTURN : - S_PDENTER; - end - S_IOREAD: rd_state_nxt = S_IDLE; - S_CSTURN: rd_state_nxt = clkena & (&cswcnt_w)? (go_power_down? S_PDENTER:S_ADDR): - S_CSTURN; - S_ADDR : rd_state_nxt = clkena & sck & - addr_done ? S_DATA : S_ADDR; - S_DATA : rd_state_nxt = byte_ready & ~spi_pause & ~|tot_bytes ? S_IDLE: - byte_ready & ~spi_pause & buf_wrap - & (&nxt_addr[4:0])? S_CSTURN: - byte_ready & ~spi_pause & ~param_burst_en ? S_CSTURN: - S_DATA; - S_WAITBUS:rd_state_nxt = spibus_busy ? S_WAITBUS : S_ADDR; - - S_PWRDOWN:rd_state_nxt = go_power_down ? S_PWRDOWN : S_PDEXIT; - S_PDEXIT :rd_state_nxt = cyc_end & (&bit_cnt[2:0]) ? S_STARTUP : S_PDEXIT; - S_PDENTER:rd_state_nxt = cyc_end & (&bit_cnt[2:0]) ? S_PWRDOWN : S_PDENTER; - S_STARTUP:rd_state_nxt = &(cs_timer[10:0]|{{5{fast_startup}}, 6'b0}) ? S_IDLE : - S_STARTUP; - endcase - end - - - wire ss_sck, ss_mosi, ss_miso; - wire [7:0] param, softcs, param2; - wire sspi_write = buf_write | second_write; - - simple_spi_top simple_spi( - .clk_i (aclk ), - .rst_i (aresetn ), - .cyc_i (buf_busy ), - .stb_i (reg_acc ), - .adr_i (buf_addr[3:0] ), - .we_i (sspi_write ), - .dat_i (reg_dat_i ), - .dat_o (reg_dat_o ), - .ack_o (reg_ack ), - .inta_o (inta_o ), - - .sck_o (ss_sck ), - .mosi_o (ss_mosi ), - .miso_i (ss_miso ), - - .param (param ), - .param2 (param2 ), - .softcs (softcs ), - .busy (spibus_busy ) - ); - assign ss_miso = sdi_i; - - assign reg_dat_i = second_write ? s_wdata[ 31: 24] : - buf_addr[1:0]==2'h0 ? s_wdata[ 7: 0] : - buf_addr[1:0]==2'h1 ? s_wdata[ 15: 8] : - buf_addr[1:0]==2'h2 ? s_wdata[ 23: 16] : - s_wdata[ 31: 24] ; - - assign param_memory_en = param[0]; - assign param_burst_en = param[1]; - assign param_fast_read = param[2]; - assign param_dual_io = param[3]; - assign espr = param[7:4]; - - assign param_tCSH = param2[1:0]; - assign param_tFAST = param2[2]; - assign param_scs = param2[3]; - - assign csn_en[0] = param_memory_en? 1'b0: ~softcs[0]; - assign csn_o [0] = param_memory_en? ~cs : softcs[4]; - - assign csn_en[3:1] =~softcs[3:1]; - assign csn_o [3:1] = softcs[7:5]|{3{cs|(~spibus_busy & param_scs)}}; - - assign sdi_en = ~spibus_busy¶m_memory_en? ~dual_out : 1'b1; - assign sdi_o = ~spibus_busy¶m_memory_en? serial_out[1] : 1'b0; - - assign sdo_en = ~spibus_busy¶m_memory_en? dual_in : 1'b0; - assign sdo_o = ~spibus_busy¶m_memory_en? serial_out[0] | s_data - : ss_mosi; - - assign sck_o = ~spibus_busy¶m_memory_en? sck : ss_sck; - -endmodule - - -module simple_spi_top( - input wire clk_i, - input wire rst_i, - input wire cyc_i, - input wire stb_i, - input wire [3:0] adr_i, - input wire we_i, - input wire [7:0] dat_i, - output reg [7:0] dat_o, - output reg ack_o, - output reg inta_o, - - output reg sck_o, - output wire mosi_o, - input wire miso_i, - - output reg [7:0] param, - output reg [7:0] param2, - output reg [7:0] softcs, - output reg busy -); - - reg [7:0] spcr; - wire [7:0] spsr; - reg [7:0] sper; - reg [7:0] treg, rreg; - - wire [7:0] rfdout; - reg wfre, rfwe; - wire rfre, rffull, rfempty; - wire [7:0] wfdout; - wire wfwe, wffull, wfempty; - - wire tirq; - wire wfov; - reg [1:0] state; - reg [2:0] bcnt; - - wire wb_acc = cyc_i & stb_i; - wire wb_wr = wb_acc & we_i; - - always @(posedge clk_i) - if (~rst_i) - begin - spcr <= 8'h12; - sper <= 8'h00; - `ifdef FAST_SIMU - param<= 8'h1; - param2<=8'h07; - `else - param<= 8'h1; - param2<=8'h03; - `endif - softcs<=8'hf0; - end - else if (wb_wr) - begin - if (adr_i == 4'b00) - spcr <= dat_i | 8'h10; - - if (adr_i == 4'b11) - sper <= dat_i; - - if (adr_i == 4'b0100) - param <= dat_i; - if (adr_i == 4'b0101) - softcs<= dat_i; - if (adr_i == 4'b0110) - param2 <= dat_i; - end - - assign wfwe = wb_acc & (adr_i == 4'b10) & ack_o & we_i; - assign wfov = wfwe & wffull; - - always @(*) - case(adr_i) // synopsys full_case parallel_case - 4'b0000: dat_o = spcr; - 4'b0001: dat_o = spsr; - 4'b0010: dat_o = rfdout; - 4'b0011: dat_o = sper; - 4'b0100: dat_o = param; - 4'b0101: dat_o = softcs; - 4'b0110: dat_o = param2; - default dat_o = 8'h0; - endcase - - assign rfre = wb_acc & (adr_i == 2'b10) & ack_o & ~we_i; - - always @(posedge clk_i) - ack_o <= 1'b1; - - wire spie = spcr[7]; - wire spe = spcr[6]; - wire dwom = spcr[5]; - wire mstr = spcr[4]; - wire cpol = spcr[3]; - wire cpha = spcr[2]; - wire [1:0] spr = spcr[1:0]; - - wire [1:0] icnt = sper[7:6]; - wire [1:0] spre = sper[1:0]; - wire smh_spi= sper[2]; - - wire [3:0] espr = {spre, spr}; - - wire wr_spsr = wb_wr & (adr_i == 2'b01); - - reg spif; - always @(posedge clk_i) - if (~spe) - spif <= 1'b0; - else - spif <= (tirq | spif) & ~(wr_spsr & dat_i[7]); - - reg wcol; - always @(posedge clk_i) - if (~spe) - wcol <= 1'b0; - else - wcol <= (wfov | wcol) & ~(wr_spsr & dat_i[6]); - - assign spsr[7] = spif; - assign spsr[6] = wcol; - assign spsr[5:4] = 2'b00; - assign spsr[3] = wffull; - assign spsr[2] = wfempty; - assign spsr[1] = rffull; - assign spsr[0] = rfempty; - - - always @(posedge clk_i) - inta_o <= spif & spie; - - spi_fifo4 #(8) - rfifo( - .clk ( clk_i ), - .rst ( rst_i ), - .clr ( ~spe ), - .din ( treg ), - .we ( rfwe ), - .dout ( rfdout ), - .re ( rfre ), - .full ( rffull ), - .empty ( rfempty ) - ), - wfifo( - .clk ( clk_i ), - .rst ( rst_i ), - .clr ( ~spe ), - .din ( dat_i ), - .we ( wfwe ), - .dout ( wfdout ), - .re ( wfre ), - .full ( wffull ), - .empty ( wfempty ) - ); - - reg [11:0] clkcnt; - always @(posedge clk_i) - if(spe & (|clkcnt & |state)) - clkcnt <= clkcnt - 11'h1; - else - case (espr) // synopsys full_case parallel_case - 4'b0000: clkcnt <= 12'h0; - 4'b0001: clkcnt <= 12'h1; - 4'b0010: clkcnt <= 12'h7; - 4'b0011: clkcnt <= 12'hf; - 4'b0100: clkcnt <= 12'h3; - 4'b0101: clkcnt <= 12'h1f; - 4'b0110: clkcnt <= 12'h3f; - 4'b0111: clkcnt <= 12'h7f; - 4'b1000: clkcnt <= 12'hff; - 4'b1001: clkcnt <= 12'h1ff; - 4'b1010: clkcnt <= 12'h3ff; - 4'b1011: clkcnt <= 12'h7ff; - default:; - endcase - - wire ena = ~|clkcnt; - reg sample; - always @(posedge clk_i) - if (~spe) - begin - state <= 2'b00; - bcnt <= 3'h0; - treg <= 8'h00; - wfre <= 1'b0; - rfwe <= 1'b0; - sck_o <= 1'b0; - end - else if (smh_spi) - begin - wfre <= 1'b0; - rfwe <= 1'b0; - - case (state) //synopsys full_case parallel_case - 2'b00: - begin - bcnt <= 3'h7; - treg <= wfdout; - sck_o <= cpol; - - if (~wfempty) begin - wfre <= 1'b1; - state <= 2'b01; - end - end - - 2'b01: - if (ena) begin - sck_o <= ~sck_o; - state <= 2'b10; - if (cpha==0) sample <= miso_i; - end - - 2'b10: - if (ena) begin - sck_o <= ~sck_o; - state <= 2'b11; - if (cpha==0) begin - treg <= {treg[6:0], sample}; - end else begin - sample <= miso_i; - end - end - - 2'b11: - if (ena) begin - bcnt <= bcnt -3'h1; - if (cpha==0) begin - sample <= miso_i; - end else begin - treg <= {treg[6:0], sample}; - end - - if (~|bcnt) begin - state <= 2'b00; - sck_o <= cpol; - rfwe <= 1'b1; - end else begin - state <= 2'b10; - sck_o <= ~sck_o; - end - - end - - endcase - end - else - begin - wfre <= 1'b0; - rfwe <= 1'b0; - - case (state) //synopsys full_case parallel_case - 2'b00: - begin - bcnt <= 3'h7; - treg <= wfdout; - sck_o <= cpol; - - if (~wfempty) begin - wfre <= 1'b1; - state <= 2'b01; - if (cpha) sck_o <= ~sck_o; - end - end - - 2'b01: - if (ena) begin - sck_o <= ~sck_o; - state <= 2'b11; - end - - 2'b11: - if (ena) begin - treg <= {treg[6:0], miso_i}; - bcnt <= bcnt -3'h1; - - if (~|bcnt) begin - state <= 2'b00; - sck_o <= cpol; - rfwe <= 1'b1; - end - else begin - state <= 2'b01; - sck_o <= ~sck_o; - end - end - - 2'b10: state <= 2'b00; - default: state <=2'b00; - endcase - end - - assign mosi_o = treg[7]; - - reg [1:0] tcnt; - always @(posedge clk_i) - if (~spe) - tcnt <= icnt; - else if (rfwe) begin - if (|tcnt) - tcnt <= tcnt - 2'h1; - else - tcnt <= icnt; - end - - assign tirq = ~|tcnt & rfwe; - - always @(posedge clk_i) - busy <= ~wfempty | (|state); -endmodule - -module spi_fifo4(clk, rst, clr, din, we, dout, re, full, empty); - -parameter dw = 8; - -input clk, rst; -input clr; -input [dw:1] din; -input we; -output [dw:1] dout; -input re; -output full, empty; - -reg [dw:1] mem[0:3]; -reg [1:0] wp; -reg [1:0] rp; -wire [1:0] wp_p1; -wire [1:0] wp_p2; -wire [1:0] rp_p1; -wire full, empty; -reg gb; - -always @(posedge clk) - if(!rst) wp <= 2'h0; - else - if(clr) wp <= 2'h0; - else - if(we) wp <= wp_p1; - -assign wp_p1 = wp + 2'h1; -assign wp_p2 = wp + 2'h2; - -always @(posedge clk) - if(!rst) rp <= 2'h0; - else - if(clr) rp <= 2'h0; - else - if(re) rp <= rp_p1; - -assign rp_p1 = rp + 2'h1; - -assign dout = mem[ rp ]; - -always @(posedge clk) - if(we) mem[ wp ] <= din; - -assign empty = (wp == rp) & !gb; -assign full = (wp == rp) & gb; - -always @(posedge clk) - if(!rst) gb <= 1'b0; - else - if(clr) gb <= 1'b0; - else - if((wp_p1 == rp) & we) gb <= 1'b1; - else - if(re) gb <= 1'b0; - -endmodule diff --git a/resources/soc/rtl/TOP/config.h b/resources/soc/rtl/TOP/config.h deleted file mode 100644 index b52301e..0000000 --- a/resources/soc/rtl/TOP/config.h +++ /dev/null @@ -1,98 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -`define Lconfbus 10 -`define Lconfret 9 -`define Lconfbusreg 64 -`define Lconfbusaddr 16 - -`define ORDER_REG_ADDR 16'h1160 - -`define Lawcmd 4 -`define Lawdirqid 4 -`define Lawstate 2 -`define Lawscseti 2 -`define Lawid 4 -`define Lawaddr 32 -`define Lawlen 4 -`define Lawsize 3 -`define Lawburst 2 -`define Lawlock 2 -`define Lawcache 4 -`define Lawprot 3 -`define Lawvalid 1 -`define Lawready 1 -`define Lwid 4 -`define Lwdata 32 -`define Lwstrb 4 -`define Lwlast 1 -`define Lwvalid 1 -`define Lwready 1 -`define Lbid 4 -`define Lbresp 2 -`define Lbvalid 1 -`define Lbready 1 -`define Larcmd 4 -`define Larcpuno 10 -`define Larid 4 -`define Laraddr 32 -`define Larlen 4 -`define Larsize 3 -`define Larburst 2 -`define Larlock 2 -`define Larcache 4 -`define Larprot 3 -`define Larvalid 1 -`define Larready 1 -`define Lrstate 2 -`define Lrscseti 2 -`define Lrid 4 -`define Lrdata 32 -`define Lrresp 2 -`define Lrlast 1 -`define Lrvalid 1 -`define Lrready 1 -`define Lrrequest 1 -/*************************/ -`define LID 4 -`define LADDR 32 -`define LLEN 4 -`define LSIZE 3 -`define LDATA 32 -`define LSTRB 4 -`define LBURST 2 -`define LLOCK 2 -`define LCACHE 4 -`define LPROT 3 -`define LRESP 2 -/************************************/ diff --git a/resources/soc/rtl/TOP/soc_up_top.v b/resources/soc/rtl/TOP/soc_up_top.v deleted file mode 100644 index ab0661f..0000000 --- a/resources/soc/rtl/TOP/soc_up_top.v +++ /dev/null @@ -1,1493 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -`include "config.h" - -module soc_up_top( - input resetn, - input clk, - - //------gpio---------------- - output [15:0] led, - output [1 :0] led_rg0, - output [1 :0] led_rg1, - output [7 :0] num_csn, - output [6 :0] num_a_g, - input [7 :0] switch, - output [3 :0] btn_key_col, - input [3 :0] btn_key_row, - input [1 :0] btn_step, - - //------DDR3 interface------ - inout [15:0] ddr3_dq, - output [12:0] ddr3_addr, - output [2 :0] ddr3_ba, - output ddr3_ras_n, - output ddr3_cas_n, - output ddr3_we_n, - output ddr3_odt, - output ddr3_reset_n, - output ddr3_cke, - output [1:0] ddr3_dm, - inout [1:0] ddr3_dqs_p, - inout [1:0] ddr3_dqs_n, - output ddr3_ck_p, - output ddr3_ck_n, - - //------mac controller------- - //TX - input mtxclk_0, - output mtxen_0, - output [3:0] mtxd_0, - output mtxerr_0, - //RX - input mrxclk_0, - input mrxdv_0, - input [3:0] mrxd_0, - input mrxerr_0, - input mcoll_0, - input mcrs_0, - // MIIM - output mdc_0, - inout mdio_0, - - output phy_rstn, - - //------EJTAG------- - // input EJTAG_TRST, - // input EJTAG_TCK, - // input EJTAG_TDI, - // input EJTAG_TMS, - // output EJTAG_TDO, - - //------uart------- - inout UART_RX, - inout UART_TX, - - //------nand------- - output NAND_CLE , - output NAND_ALE , - input NAND_RDY , - inout [7:0] NAND_DATA, - output NAND_RD , - output NAND_CE , //low active - output NAND_WR , - - //------spi flash------- - output SPI_CLK, - output SPI_CS, - inout SPI_MISO, - inout SPI_MOSI -); -wire aclk; -wire aresetn; - -wire [`LID -1 :0] m0_awid; -wire [`Lawaddr -1 :0] m0_awaddr; -wire [`Lawlen -1 :0] m0_awlen; -wire [`Lawsize -1 :0] m0_awsize; -wire [`Lawburst -1 :0] m0_awburst; -wire [`Lawlock -1 :0] m0_awlock; -wire [`Lawcache -1 :0] m0_awcache; -wire [`Lawprot -1 :0] m0_awprot; -wire m0_awvalid; -wire m0_awready; -wire [`LID -1 :0] m0_wid; -wire [`Lwdata -1 :0] m0_wdata; -wire [`Lwstrb -1 :0] m0_wstrb; -wire m0_wlast; -wire m0_wvalid; -wire m0_wready; -wire [`LID -1 :0] m0_bid; -wire [`Lbresp -1 :0] m0_bresp; -wire m0_bvalid; -wire m0_bready; -wire [`LID -1 :0] m0_arid; -wire [`Laraddr -1 :0] m0_araddr; -wire [`Larlen -1 :0] m0_arlen; -wire [`Larsize -1 :0] m0_arsize; -wire [`Larburst -1 :0] m0_arburst; -wire [`Larlock -1 :0] m0_arlock; -wire [`Larcache -1 :0] m0_arcache; -wire [`Larprot -1 :0] m0_arprot; -wire m0_arvalid; -wire m0_arready; -wire [`LID -1 :0] m0_rid; -wire [`Lrdata -1 :0] m0_rdata; -wire [`Lrresp -1 :0] m0_rresp; -wire m0_rlast; -wire m0_rvalid; -wire m0_rready; - -wire [`LID -1 :0] spi_s_awid; -wire [`Lawaddr -1 :0] spi_s_awaddr; -wire [`Lawlen -1 :0] spi_s_awlen; -wire [`Lawsize -1 :0] spi_s_awsize; -wire [`Lawburst -1 :0] spi_s_awburst; -wire [`Lawlock -1 :0] spi_s_awlock; -wire [`Lawcache -1 :0] spi_s_awcache; -wire [`Lawprot -1 :0] spi_s_awprot; -wire spi_s_awvalid; -wire spi_s_awready; -wire [`LID -1 :0] spi_s_wid; -wire [`Lwdata -1 :0] spi_s_wdata; -wire [`Lwstrb -1 :0] spi_s_wstrb; -wire spi_s_wlast; -wire spi_s_wvalid; -wire spi_s_wready; -wire [`LID -1 :0] spi_s_bid; -wire [`Lbresp -1 :0] spi_s_bresp; -wire spi_s_bvalid; -wire spi_s_bready; -wire [`LID -1 :0] spi_s_arid; -wire [`Laraddr -1 :0] spi_s_araddr; -wire [`Larlen -1 :0] spi_s_arlen; -wire [`Larsize -1 :0] spi_s_arsize; -wire [`Larburst -1 :0] spi_s_arburst; -wire [`Larlock -1 :0] spi_s_arlock; -wire [`Larcache -1 :0] spi_s_arcache; -wire [`Larprot -1 :0] spi_s_arprot; -wire spi_s_arvalid; -wire spi_s_arready; -wire [`LID -1 :0] spi_s_rid; -wire [`Lrdata -1 :0] spi_s_rdata; -wire [`Lrresp -1 :0] spi_s_rresp; -wire spi_s_rlast; -wire spi_s_rvalid; -wire spi_s_rready; - -wire [`LID -1 :0] conf_s_awid; -wire [`Lawaddr -1 :0] conf_s_awaddr; -wire [`Lawlen -1 :0] conf_s_awlen; -wire [`Lawsize -1 :0] conf_s_awsize; -wire [`Lawburst -1 :0] conf_s_awburst; -wire [`Lawlock -1 :0] conf_s_awlock; -wire [`Lawcache -1 :0] conf_s_awcache; -wire [`Lawprot -1 :0] conf_s_awprot; -wire conf_s_awvalid; -wire conf_s_awready; -wire [`LID -1 :0] conf_s_wid; -wire [`Lwdata -1 :0] conf_s_wdata; -wire [`Lwstrb -1 :0] conf_s_wstrb; -wire conf_s_wlast; -wire conf_s_wvalid; -wire conf_s_wready; -wire [`LID -1 :0] conf_s_bid; -wire [`Lbresp -1 :0] conf_s_bresp; -wire conf_s_bvalid; -wire conf_s_bready; -wire [`LID -1 :0] conf_s_arid; -wire [`Laraddr -1 :0] conf_s_araddr; -wire [`Larlen -1 :0] conf_s_arlen; -wire [`Larsize -1 :0] conf_s_arsize; -wire [`Larburst -1 :0] conf_s_arburst; -wire [`Larlock -1 :0] conf_s_arlock; -wire [`Larcache -1 :0] conf_s_arcache; -wire [`Larprot -1 :0] conf_s_arprot; -wire conf_s_arvalid; -wire conf_s_arready; -wire [`LID -1 :0] conf_s_rid; -wire [`Lrdata -1 :0] conf_s_rdata; -wire [`Lrresp -1 :0] conf_s_rresp; -wire conf_s_rlast; -wire conf_s_rvalid; -wire conf_s_rready; - -wire [`LID -1 :0] mac_s_awid; -wire [`Lawaddr -1 :0] mac_s_awaddr; -wire [`Lawlen -1 :0] mac_s_awlen; -wire [`Lawsize -1 :0] mac_s_awsize; -wire [`Lawburst -1 :0] mac_s_awburst; -wire [`Lawlock -1 :0] mac_s_awlock; -wire [`Lawcache -1 :0] mac_s_awcache; -wire [`Lawprot -1 :0] mac_s_awprot; -wire mac_s_awvalid; -wire mac_s_awready; -wire [`LID -1 :0] mac_s_wid; -wire [`Lwdata -1 :0] mac_s_wdata; -wire [`Lwstrb -1 :0] mac_s_wstrb; -wire mac_s_wlast; -wire mac_s_wvalid; -wire mac_s_wready; -wire [`LID -1 :0] mac_s_bid; -wire [`Lbresp -1 :0] mac_s_bresp; -wire mac_s_bvalid; -wire mac_s_bready; -wire [`LID -1 :0] mac_s_arid; -wire [`Laraddr -1 :0] mac_s_araddr; -wire [`Larlen -1 :0] mac_s_arlen; -wire [`Larsize -1 :0] mac_s_arsize; -wire [`Larburst -1 :0] mac_s_arburst; -wire [`Larlock -1 :0] mac_s_arlock; -wire [`Larcache -1 :0] mac_s_arcache; -wire [`Larprot -1 :0] mac_s_arprot; -wire mac_s_arvalid; -wire mac_s_arready; -wire [`LID -1 :0] mac_s_rid; -wire [`Lrdata -1 :0] mac_s_rdata; -wire [`Lrresp -1 :0] mac_s_rresp; -wire mac_s_rlast; -wire mac_s_rvalid; -wire mac_s_rready; - -wire [`LID -1 :0] mac_m_awid; -wire [`Lawaddr -1 :0] mac_m_awaddr; -wire [`Lawlen -1 :0] mac_m_awlen; -wire [`Lawsize -1 :0] mac_m_awsize; -wire [`Lawburst -1 :0] mac_m_awburst; -wire [`Lawlock -1 :0] mac_m_awlock; -wire [`Lawcache -1 :0] mac_m_awcache; -wire [`Lawprot -1 :0] mac_m_awprot; -wire mac_m_awvalid; -wire mac_m_awready; -wire [`LID -1 :0] mac_m_wid; -wire [`Lwdata -1 :0] mac_m_wdata; -wire [`Lwstrb -1 :0] mac_m_wstrb; -wire mac_m_wlast; -wire mac_m_wvalid; -wire mac_m_wready; -wire [`LID -1 :0] mac_m_bid; -wire [`Lbresp -1 :0] mac_m_bresp; -wire mac_m_bvalid; -wire mac_m_bready; -wire [`LID -1 :0] mac_m_arid; -wire [`Laraddr -1 :0] mac_m_araddr; -wire [`Larlen -1 :0] mac_m_arlen; -wire [`Larsize -1 :0] mac_m_arsize; -wire [`Larburst -1 :0] mac_m_arburst; -wire [`Larlock -1 :0] mac_m_arlock; -wire [`Larcache -1 :0] mac_m_arcache; -wire [`Larprot -1 :0] mac_m_arprot; -wire mac_m_arvalid; -wire mac_m_arready; -wire [`LID -1 :0] mac_m_rid; -wire [`Lrdata -1 :0] mac_m_rdata; -wire [`Lrresp -1 :0] mac_m_rresp; -wire mac_m_rlast; -wire mac_m_rvalid; -wire mac_m_rready; - -wire [`LID -1 :0] s0_awid; -wire [`Lawaddr -1 :0] s0_awaddr; -wire [`Lawlen -1 :0] s0_awlen; -wire [`Lawsize -1 :0] s0_awsize; -wire [`Lawburst -1 :0] s0_awburst; -wire [`Lawlock -1 :0] s0_awlock; -wire [`Lawcache -1 :0] s0_awcache; -wire [`Lawprot -1 :0] s0_awprot; -wire s0_awvalid; -wire s0_awready; -wire [`LID -1 :0] s0_wid; -wire [`Lwdata -1 :0] s0_wdata; -wire [`Lwstrb -1 :0] s0_wstrb; -wire s0_wlast; -wire s0_wvalid; -wire s0_wready; -wire [`LID -1 :0] s0_bid; -wire [`Lbresp -1 :0] s0_bresp; -wire s0_bvalid; -wire s0_bready; -wire [`LID -1 :0] s0_arid; -wire [`Laraddr -1 :0] s0_araddr; -wire [`Larlen -1 :0] s0_arlen; -wire [`Larsize -1 :0] s0_arsize; -wire [`Larburst -1 :0] s0_arburst; -wire [`Larlock -1 :0] s0_arlock; -wire [`Larcache -1 :0] s0_arcache; -wire [`Larprot -1 :0] s0_arprot; -wire s0_arvalid; -wire s0_arready; -wire [`LID -1 :0] s0_rid; -wire [`Lrdata -1 :0] s0_rdata; -wire [`Lrresp -1 :0] s0_rresp; -wire s0_rlast; -wire s0_rvalid; -wire s0_rready; - -wire [8 -1 :0] mig_awid; -wire [`Lawaddr -1 :0] mig_awaddr; -wire [8 -1 :0] mig_awlen; -wire [`Lawsize -1 :0] mig_awsize; -wire [`Lawburst -1 :0] mig_awburst; -wire [`Lawlock -1 :0] mig_awlock; -wire [`Lawcache -1 :0] mig_awcache; -wire [`Lawprot -1 :0] mig_awprot; -wire mig_awvalid; -wire mig_awready; -wire [8 -1 :0] mig_wid; -wire [`Lwdata -1 :0] mig_wdata; -wire [`Lwstrb -1 :0] mig_wstrb; -wire mig_wlast; -wire mig_wvalid; -wire mig_wready; -wire [8 -1 :0] mig_bid; -wire [`Lbresp -1 :0] mig_bresp; -wire mig_bvalid; -wire mig_bready; -wire [8 -1 :0] mig_arid; -wire [`Laraddr -1 :0] mig_araddr; -wire [8 -1 :0] mig_arlen; -wire [`Larsize -1 :0] mig_arsize; -wire [`Larburst -1 :0] mig_arburst; -wire [`Larlock -1 :0] mig_arlock; -wire [`Larcache -1 :0] mig_arcache; -wire [`Larprot -1 :0] mig_arprot; -wire mig_arvalid; -wire mig_arready; -wire [8 -1 :0] mig_rid; -wire [`Lrdata -1 :0] mig_rdata; -wire [`Lrresp -1 :0] mig_rresp; -wire mig_rlast; -wire mig_rvalid; -wire mig_rready; - -wire [`LID -1 :0] dma0_awid ; -wire [`Lawaddr -1 :0] dma0_awaddr ; -wire [`Lawlen -1 :0] dma0_awlen ; -wire [`Lawsize -1 :0] dma0_awsize ; -wire [`Lawburst -1 :0] dma0_awburst ; -wire [`Lawlock -1 :0] dma0_awlock ; -wire [`Lawcache -1 :0] dma0_awcache ; -wire [`Lawprot -1 :0] dma0_awprot ; -wire dma0_awvalid ; -wire dma0_awready ; -wire [`LID -1 :0] dma0_wid ; -wire [64 -1 :0] dma0_wdata ; -wire [8 -1 :0] dma0_wstrb ; -wire dma0_wlast ; -wire dma0_wvalid ; -wire dma0_wready ; -wire [`LID -1 :0] dma0_bid ; -wire [`Lbresp -1 :0] dma0_bresp ; -wire dma0_bvalid ; -wire dma0_bready ; -wire [`LID -1 :0] dma0_arid ; -wire [`Laraddr -1 :0] dma0_araddr ; -wire [`Larlen -1 :0] dma0_arlen ; -wire [`Larsize -1 :0] dma0_arsize ; -wire [`Larburst -1 :0] dma0_arburst ; -wire [`Larlock -1 :0] dma0_arlock ; -wire [`Larcache -1 :0] dma0_arcache ; -wire [`Larprot -1 :0] dma0_arprot ; -wire dma0_arvalid ; -wire dma0_arready ; -wire [`LID -1 :0] dma0_rid ; -wire [64 -1 :0] dma0_rdata ; -wire [`Lrresp -1 :0] dma0_rresp ; -wire dma0_rlast ; -wire dma0_rvalid ; -wire dma0_rready ; - -wire [`LID -1 :0] apb_s_awid; -wire [`Lawaddr -1 :0] apb_s_awaddr; -wire [`Lawlen -1 :0] apb_s_awlen; -wire [`Lawsize -1 :0] apb_s_awsize; -wire [`Lawburst -1 :0] apb_s_awburst; -wire [`Lawlock -1 :0] apb_s_awlock; -wire [`Lawcache -1 :0] apb_s_awcache; -wire [`Lawprot -1 :0] apb_s_awprot; -wire apb_s_awvalid; -wire apb_s_awready; -wire [`LID -1 :0] apb_s_wid; -wire [`Lwdata -1 :0] apb_s_wdata; -wire [`Lwstrb -1 :0] apb_s_wstrb; -wire apb_s_wlast; -wire apb_s_wvalid; -wire apb_s_wready; -wire [`LID -1 :0] apb_s_bid; -wire [`Lbresp -1 :0] apb_s_bresp; -wire apb_s_bvalid; -wire apb_s_bready; -wire [`LID -1 :0] apb_s_arid; -wire [`Laraddr -1 :0] apb_s_araddr; -wire [`Larlen -1 :0] apb_s_arlen; -wire [`Larsize -1 :0] apb_s_arsize; -wire [`Larburst -1 :0] apb_s_arburst; -wire [`Larlock -1 :0] apb_s_arlock; -wire [`Larcache -1 :0] apb_s_arcache; -wire [`Larprot -1 :0] apb_s_arprot; -wire apb_s_arvalid; -wire apb_s_arready; -wire [`LID -1 :0] apb_s_rid; -wire [`Lrdata -1 :0] apb_s_rdata; -wire [`Lrresp -1 :0] apb_s_rresp; -wire apb_s_rlast; -wire apb_s_rvalid; -wire apb_s_rready; - -wire apb_ready_dma0; -wire apb_start_dma0; -wire apb_rw_dma0; -wire apb_psel_dma0; -wire apb_penable_dma0; -wire[31:0] apb_addr_dma0; -wire[31:0] apb_wdata_dma0; -wire[31:0] apb_rdata_dma0; - -wire dma_int; -wire dma_ack; -wire dma_req; - -wire dma0_gnt; -wire[31:0] order_addr_in; -wire write_dma_end; -wire finish_read_order; - -//spi -wire [3:0]spi_csn_o ; -wire [3:0]spi_csn_en; -wire spi_sck_o ; -wire spi_sdo_i ; -wire spi_sdo_o ; -wire spi_sdo_en; -wire spi_sdi_i ; -wire spi_sdi_o ; -wire spi_sdi_en; -wire spi_inta_o; -assign SPI_CLK = spi_sck_o; -assign SPI_CS = ~spi_csn_en[0] & spi_csn_o[0]; -assign SPI_MOSI = spi_sdo_en ? 1'bz : spi_sdo_o ; -assign SPI_MISO = spi_sdi_en ? 1'bz : spi_sdi_o ; -assign spi_sdo_i = SPI_MOSI; -assign spi_sdi_i = SPI_MISO; - -// confreg -wire [31:0] cr00,cr01,cr02,cr03,cr04,cr05,cr06,cr07; - -//mac -wire md_i_0; // MII data input (from I/O cell) -wire md_o_0; // MII data output (to I/O cell) -wire md_oe_0; // MII data output enable (to I/O cell) -IOBUF mac_mdio(.IO(mdio_0),.I(md_o_0),.T(~md_oe_0),.O(md_i_0)); -assign phy_rstn = aresetn; - -//nand -wire nand_cle ; -wire nand_ale ; -wire [3:0] nand_rdy ; -wire [3:0] nand_ce ; -wire nand_rd ; -wire nand_wr ; -wire nand_dat_oe; -wire [7:0] nand_dat_i ; -wire [7:0] nand_dat_o ; -wire nand_int ; -assign NAND_CLE = nand_cle; -assign NAND_ALE = nand_ale; -assign nand_rdy = {3'd0,NAND_RDY}; -assign NAND_RD = nand_rd; -assign NAND_CE = nand_ce[0]; //low active -assign NAND_WR = nand_wr; -generate - genvar i; - for(i=0;i<8;i=i+1) - begin: nand_data_loop - IOBUF nand_data(.IO(NAND_DATA[i]),.I(nand_dat_o[i]),.T(nand_dat_oe),.O(nand_dat_i[i])); - end -endgenerate - -//uart -wire UART_CTS, UART_RTS; -wire UART_DTR, UART_DSR; -wire UART_RI, UART_DCD; -assign UART_CTS = 1'b0; -assign UART_DSR = 1'b0; -assign UART_DCD = 1'b0; -wire uart0_int ; -wire uart0_txd_o ; -wire uart0_txd_i ; -wire uart0_txd_oe; -wire uart0_rxd_o ; -wire uart0_rxd_i ; -wire uart0_rxd_oe; -wire uart0_rts_o ; -wire uart0_cts_i ; -wire uart0_dsr_i ; -wire uart0_dcd_i ; -wire uart0_dtr_o ; -wire uart0_ri_i ; -assign UART_RX = uart0_rxd_oe ? 1'bz : uart0_rxd_o ; -assign UART_TX = uart0_txd_oe ? 1'bz : uart0_txd_o ; -assign UART_RTS = uart0_rts_o ; -assign UART_DTR = uart0_dtr_o ; -assign uart0_txd_i = UART_TX; -assign uart0_rxd_i = UART_RX; -assign uart0_cts_i = UART_CTS; -assign uart0_dcd_i = UART_DCD; -assign uart0_dsr_i = UART_DSR; -assign uart0_ri_i = UART_RI ; - -//interrupt -wire mac_int; -wire [5:0] int_out; -wire [5:0] int_n_i; -assign int_out = {1'b0,dma_int,nand_int,spi_inta_o,uart0_int,mac_int}; -assign int_n_i = ~int_out; - -// cpu -mycpu_top mycpu( - .aclk (aclk ), - .ext_int (int_out ), - .aresetn (aresetn ), - .arid (m0_arid[3:0] ), - .araddr (m0_araddr ), - .arlen (m0_arlen ), - .arsize (m0_arsize ), - .arburst (m0_arburst ), - .arlock (m0_arlock ), - .arcache (m0_arcache ), - .arprot (m0_arprot ), - .arvalid (m0_arvalid ), - .arready (m0_arready ), - .rid (m0_rid[3:0] ), - .rdata (m0_rdata ), - .rresp (m0_rresp ), - .rlast (m0_rlast ), - .rvalid (m0_rvalid ), - .rready (m0_rready ), - .awid (m0_awid[3:0] ), - .awaddr (m0_awaddr ), - .awlen (m0_awlen ), - .awsize (m0_awsize ), - .awburst (m0_awburst ), - .awlock (m0_awlock ), - .awcache (m0_awcache ), - .awprot (m0_awprot ), - .awvalid (m0_awvalid ), - .awready (m0_awready ), - .wid (m0_wid[3:0] ), - .wdata (m0_wdata ), - .wstrb (m0_wstrb ), - .wlast (m0_wlast ), - .wvalid (m0_wvalid ), - .wready (m0_wready ), - .bid (m0_bid[3:0] ), - .bresp (m0_bresp ), - .bvalid (m0_bvalid ), - .bready (m0_bready ) -); - -// AXI_MUX -axi_slave_mux AXI_SLAVE_MUX -( -.axi_s_aresetn (aresetn ), -.spi_boot (1'b1 ), - -.axi_s_awid (m0_awid ), -.axi_s_awaddr (m0_awaddr ), -.axi_s_awlen (m0_awlen ), -.axi_s_awsize (m0_awsize ), -.axi_s_awburst (m0_awburst ), -.axi_s_awlock (m0_awlock ), -.axi_s_awcache (m0_awcache ), -.axi_s_awprot (m0_awprot ), -.axi_s_awvalid (m0_awvalid ), -.axi_s_awready (m0_awready ), -.axi_s_wready (m0_wready ), -.axi_s_wid (m0_wid ), -.axi_s_wdata (m0_wdata ), -.axi_s_wstrb (m0_wstrb ), -.axi_s_wlast (m0_wlast ), -.axi_s_wvalid (m0_wvalid ), -.axi_s_bid (m0_bid ), -.axi_s_bresp (m0_bresp ), -.axi_s_bvalid (m0_bvalid ), -.axi_s_bready (m0_bready ), -.axi_s_arid (m0_arid ), -.axi_s_araddr (m0_araddr ), -.axi_s_arlen (m0_arlen ), -.axi_s_arsize (m0_arsize ), -.axi_s_arburst (m0_arburst ), -.axi_s_arlock (m0_arlock ), -.axi_s_arcache (m0_arcache ), -.axi_s_arprot (m0_arprot ), -.axi_s_arvalid (m0_arvalid ), -.axi_s_arready (m0_arready ), -.axi_s_rready (m0_rready ), -.axi_s_rid (m0_rid ), -.axi_s_rdata (m0_rdata ), -.axi_s_rresp (m0_rresp ), -.axi_s_rlast (m0_rlast ), -.axi_s_rvalid (m0_rvalid ), - -.s0_awid (s0_awid ), -.s0_awaddr (s0_awaddr ), -.s0_awlen (s0_awlen ), -.s0_awsize (s0_awsize ), -.s0_awburst (s0_awburst ), -.s0_awlock (s0_awlock ), -.s0_awcache (s0_awcache ), -.s0_awprot (s0_awprot ), -.s0_awvalid (s0_awvalid ), -.s0_awready (s0_awready ), -.s0_wid (s0_wid ), -.s0_wdata (s0_wdata ), -.s0_wstrb (s0_wstrb ), -.s0_wlast (s0_wlast ), -.s0_wvalid (s0_wvalid ), -.s0_wready (s0_wready ), -.s0_bid (s0_bid ), -.s0_bresp (s0_bresp ), -.s0_bvalid (s0_bvalid ), -.s0_bready (s0_bready ), -.s0_arid (s0_arid ), -.s0_araddr (s0_araddr ), -.s0_arlen (s0_arlen ), -.s0_arsize (s0_arsize ), -.s0_arburst (s0_arburst ), -.s0_arlock (s0_arlock ), -.s0_arcache (s0_arcache ), -.s0_arprot (s0_arprot ), -.s0_arvalid (s0_arvalid ), -.s0_arready (s0_arready ), -.s0_rid (s0_rid ), -.s0_rdata (s0_rdata ), -.s0_rresp (s0_rresp ), -.s0_rlast (s0_rlast ), -.s0_rvalid (s0_rvalid ), -.s0_rready (s0_rready ), - -.s1_awid (spi_s_awid ), -.s1_awaddr (spi_s_awaddr ), -.s1_awlen (spi_s_awlen ), -.s1_awsize (spi_s_awsize ), -.s1_awburst (spi_s_awburst ), -.s1_awlock (spi_s_awlock ), -.s1_awcache (spi_s_awcache ), -.s1_awprot (spi_s_awprot ), -.s1_awvalid (spi_s_awvalid ), -.s1_awready (spi_s_awready ), -.s1_wid (spi_s_wid ), -.s1_wdata (spi_s_wdata ), -.s1_wstrb (spi_s_wstrb ), -.s1_wlast (spi_s_wlast ), -.s1_wvalid (spi_s_wvalid ), -.s1_wready (spi_s_wready ), -.s1_bid (spi_s_bid ), -.s1_bresp (spi_s_bresp ), -.s1_bvalid (spi_s_bvalid ), -.s1_bready (spi_s_bready ), -.s1_arid (spi_s_arid ), -.s1_araddr (spi_s_araddr ), -.s1_arlen (spi_s_arlen ), -.s1_arsize (spi_s_arsize ), -.s1_arburst (spi_s_arburst ), -.s1_arlock (spi_s_arlock ), -.s1_arcache (spi_s_arcache ), -.s1_arprot (spi_s_arprot ), -.s1_arvalid (spi_s_arvalid ), -.s1_arready (spi_s_arready ), -.s1_rid (spi_s_rid ), -.s1_rdata (spi_s_rdata ), -.s1_rresp (spi_s_rresp ), -.s1_rlast (spi_s_rlast ), -.s1_rvalid (spi_s_rvalid ), -.s1_rready (spi_s_rready ), - -.s2_awid (apb_s_awid ), -.s2_awaddr (apb_s_awaddr ), -.s2_awlen (apb_s_awlen ), -.s2_awsize (apb_s_awsize ), -.s2_awburst (apb_s_awburst ), -.s2_awlock (apb_s_awlock ), -.s2_awcache (apb_s_awcache ), -.s2_awprot (apb_s_awprot ), -.s2_awvalid (apb_s_awvalid ), -.s2_awready (apb_s_awready ), -.s2_wid (apb_s_wid ), -.s2_wdata (apb_s_wdata ), -.s2_wstrb (apb_s_wstrb ), -.s2_wlast (apb_s_wlast ), -.s2_wvalid (apb_s_wvalid ), -.s2_wready (apb_s_wready ), -.s2_bid (apb_s_bid ), -.s2_bresp (apb_s_bresp ), -.s2_bvalid (apb_s_bvalid ), -.s2_bready (apb_s_bready ), -.s2_arid (apb_s_arid ), -.s2_araddr (apb_s_araddr ), -.s2_arlen (apb_s_arlen ), -.s2_arsize (apb_s_arsize ), -.s2_arburst (apb_s_arburst ), -.s2_arlock (apb_s_arlock ), -.s2_arcache (apb_s_arcache ), -.s2_arprot (apb_s_arprot ), -.s2_arvalid (apb_s_arvalid ), -.s2_arready (apb_s_arready ), -.s2_rid (apb_s_rid ), -.s2_rdata (apb_s_rdata ), -.s2_rresp (apb_s_rresp ), -.s2_rlast (apb_s_rlast ), -.s2_rvalid (apb_s_rvalid ), -.s2_rready (apb_s_rready ), - -.s3_awid (conf_s_awid ), -.s3_awaddr (conf_s_awaddr ), -.s3_awlen (conf_s_awlen ), -.s3_awsize (conf_s_awsize ), -.s3_awburst (conf_s_awburst ), -.s3_awlock (conf_s_awlock ), -.s3_awcache (conf_s_awcache ), -.s3_awprot (conf_s_awprot ), -.s3_awvalid (conf_s_awvalid ), -.s3_awready (conf_s_awready ), -.s3_wid (conf_s_wid ), -.s3_wdata (conf_s_wdata ), -.s3_wstrb (conf_s_wstrb ), -.s3_wlast (conf_s_wlast ), -.s3_wvalid (conf_s_wvalid ), -.s3_wready (conf_s_wready ), -.s3_bid (conf_s_bid ), -.s3_bresp (conf_s_bresp ), -.s3_bvalid (conf_s_bvalid ), -.s3_bready (conf_s_bready ), -.s3_arid (conf_s_arid ), -.s3_araddr (conf_s_araddr ), -.s3_arlen (conf_s_arlen ), -.s3_arsize (conf_s_arsize ), -.s3_arburst (conf_s_arburst ), -.s3_arlock (conf_s_arlock ), -.s3_arcache (conf_s_arcache ), -.s3_arprot (conf_s_arprot ), -.s3_arvalid (conf_s_arvalid ), -.s3_arready (conf_s_arready ), -.s3_rid (conf_s_rid ), -.s3_rdata (conf_s_rdata ), -.s3_rresp (conf_s_rresp ), -.s3_rlast (conf_s_rlast ), -.s3_rvalid (conf_s_rvalid ), -.s3_rready (conf_s_rready ), - -.s4_awid (mac_s_awid ), -.s4_awaddr (mac_s_awaddr ), -.s4_awlen (mac_s_awlen ), -.s4_awsize (mac_s_awsize ), -.s4_awburst (mac_s_awburst ), -.s4_awlock (mac_s_awlock ), -.s4_awcache (mac_s_awcache ), -.s4_awprot (mac_s_awprot ), -.s4_awvalid (mac_s_awvalid ), -.s4_awready (mac_s_awready ), -.s4_wid (mac_s_wid ), -.s4_wdata (mac_s_wdata ), -.s4_wstrb (mac_s_wstrb ), -.s4_wlast (mac_s_wlast ), -.s4_wvalid (mac_s_wvalid ), -.s4_wready (mac_s_wready ), -.s4_bid (mac_s_bid ), -.s4_bresp (mac_s_bresp ), -.s4_bvalid (mac_s_bvalid ), -.s4_bready (mac_s_bready ), -.s4_arid (mac_s_arid ), -.s4_araddr (mac_s_araddr ), -.s4_arlen (mac_s_arlen ), -.s4_arsize (mac_s_arsize ), -.s4_arburst (mac_s_arburst ), -.s4_arlock (mac_s_arlock ), -.s4_arcache (mac_s_arcache ), -.s4_arprot (mac_s_arprot ), -.s4_arvalid (mac_s_arvalid ), -.s4_arready (mac_s_arready ), -.s4_rid (mac_s_rid ), -.s4_rdata (mac_s_rdata ), -.s4_rresp (mac_s_rresp ), -.s4_rlast (mac_s_rlast ), -.s4_rvalid (mac_s_rvalid ), -.s4_rready (mac_s_rready ), - -.axi_s_aclk (aclk ) -); - -//SPI -spi_flash_ctrl SPI -( -.aclk (aclk ), -.aresetn (aresetn ), -.spi_addr (16'h1fe8 ), -.fast_startup (1'b0 ), -.s_awid (spi_s_awid ), -.s_awaddr (spi_s_awaddr ), -.s_awlen (spi_s_awlen ), -.s_awsize (spi_s_awsize ), -.s_awburst (spi_s_awburst ), -.s_awlock (spi_s_awlock ), -.s_awcache (spi_s_awcache ), -.s_awprot (spi_s_awprot ), -.s_awvalid (spi_s_awvalid ), -.s_awready (spi_s_awready ), -.s_wready (spi_s_wready ), -.s_wid (spi_s_wid ), -.s_wdata (spi_s_wdata ), -.s_wstrb (spi_s_wstrb ), -.s_wlast (spi_s_wlast ), -.s_wvalid (spi_s_wvalid ), -.s_bid (spi_s_bid ), -.s_bresp (spi_s_bresp ), -.s_bvalid (spi_s_bvalid ), -.s_bready (spi_s_bready ), -.s_arid (spi_s_arid ), -.s_araddr (spi_s_araddr ), -.s_arlen (spi_s_arlen ), -.s_arsize (spi_s_arsize ), -.s_arburst (spi_s_arburst ), -.s_arlock (spi_s_arlock ), -.s_arcache (spi_s_arcache ), -.s_arprot (spi_s_arprot ), -.s_arvalid (spi_s_arvalid ), -.s_arready (spi_s_arready ), -.s_rready (spi_s_rready ), -.s_rid (spi_s_rid ), -.s_rdata (spi_s_rdata ), -.s_rresp (spi_s_rresp ), -.s_rlast (spi_s_rlast ), -.s_rvalid (spi_s_rvalid ), - -.power_down_req (1'b0 ), -.power_down_ack ( ), -.csn_o (spi_csn_o ), -.csn_en (spi_csn_en ), -.sck_o (spi_sck_o ), -.sdo_i (spi_sdo_i ), -.sdo_o (spi_sdo_o ), -.sdo_en (spi_sdo_en ), // active low -.sdi_i (spi_sdi_i ), -.sdi_o (spi_sdi_o ), -.sdi_en (spi_sdi_en ), -.inta_o (spi_inta_o ) -); - -//confreg -confreg CONFREG( -.aclk (aclk ), -.aresetn (aresetn ), -.s_awid (conf_s_awid ), -.s_awaddr (conf_s_awaddr ), -.s_awlen (conf_s_awlen ), -.s_awsize (conf_s_awsize ), -.s_awburst (conf_s_awburst ), -.s_awlock (conf_s_awlock ), -.s_awcache (conf_s_awcache ), -.s_awprot (conf_s_awprot ), -.s_awvalid (conf_s_awvalid ), -.s_awready (conf_s_awready ), -.s_wready (conf_s_wready ), -.s_wid (conf_s_wid ), -.s_wdata (conf_s_wdata ), -.s_wstrb (conf_s_wstrb ), -.s_wlast (conf_s_wlast ), -.s_wvalid (conf_s_wvalid ), -.s_bid (conf_s_bid ), -.s_bresp (conf_s_bresp ), -.s_bvalid (conf_s_bvalid ), -.s_bready (conf_s_bready ), -.s_arid (conf_s_arid ), -.s_araddr (conf_s_araddr ), -.s_arlen (conf_s_arlen ), -.s_arsize (conf_s_arsize ), -.s_arburst (conf_s_arburst ), -.s_arlock (conf_s_arlock ), -.s_arcache (conf_s_arcache ), -.s_arprot (conf_s_arprot ), -.s_arvalid (conf_s_arvalid ), -.s_arready (conf_s_arready ), -.s_rready (conf_s_rready ), -.s_rid (conf_s_rid ), -.s_rdata (conf_s_rdata ), -.s_rresp (conf_s_rresp ), -.s_rlast (conf_s_rlast ), -.s_rvalid (conf_s_rvalid ), - -//dma -.order_addr_reg (order_addr_in ), -.write_dma_end (write_dma_end ), -.finish_read_order (finish_read_order ), - -//cr00~cr07 -.cr00 (cr00 ), -.cr01 (cr01 ), -.cr02 (cr02 ), -.cr03 (cr03 ), -.cr04 (cr04 ), -.cr05 (cr05 ), -.cr06 (cr06 ), -.cr07 (cr07 ), - -.led (led ), -.led_rg0 (led_rg0 ), -.led_rg1 (led_rg1 ), -.num_csn (num_csn ), -.num_a_g (num_a_g ), -.switch (switch ), -.btn_key_col (btn_key_col ), -.btn_key_row (btn_key_row ), -.btn_step (btn_step ) -); - -//MAC top -ethernet_top ETHERNET_TOP( - - .hclk (aclk ), - .hrst_ (aresetn), - //axi master - .mawid_o (mac_m_awid ), - .mawaddr_o (mac_m_awaddr ), - .mawlen_o (mac_m_awlen ), - .mawsize_o (mac_m_awsize ), - .mawburst_o (mac_m_awburst ), - .mawlock_o (mac_m_awlock ), - .mawcache_o (mac_m_awcache ), - .mawprot_o (mac_m_awprot ), - .mawvalid_o (mac_m_awvalid ), - .mawready_i (mac_m_awready ), - .mwid_o (mac_m_wid ), - .mwdata_o (mac_m_wdata ), - .mwstrb_o (mac_m_wstrb ), - .mwlast_o (mac_m_wlast ), - .mwvalid_o (mac_m_wvalid ), - .mwready_i (mac_m_wready ), - .mbid_i (mac_m_bid ), - .mbresp_i (mac_m_bresp ), - .mbvalid_i (mac_m_bvalid ), - .mbready_o (mac_m_bready ), - .marid_o (mac_m_arid ), - .maraddr_o (mac_m_araddr ), - .marlen_o (mac_m_arlen ), - .marsize_o (mac_m_arsize ), - .marburst_o (mac_m_arburst ), - .marlock_o (mac_m_arlock ), - .marcache_o (mac_m_arcache ), - .marprot_o (mac_m_arprot ), - .marvalid_o (mac_m_arvalid ), - .marready_i (mac_m_arready ), - .mrid_i (mac_m_rid ), - .mrdata_i (mac_m_rdata ), - .mrresp_i (mac_m_rresp ), - .mrlast_i (mac_m_rlast ), - .mrvalid_i (mac_m_rvalid ), - .mrready_o (mac_m_rready ), - //axi slaver - .sawid_i (mac_s_awid ), - .sawaddr_i (mac_s_awaddr ), - .sawlen_i (mac_s_awlen ), - .sawsize_i (mac_s_awsize ), - .sawburst_i (mac_s_awburst ), - .sawlock_i (mac_s_awlock ), - .sawcache_i (mac_s_awcache ), - .sawprot_i (mac_s_awprot ), - .sawvalid_i (mac_s_awvalid ), - .sawready_o (mac_s_awready ), - .swid_i (mac_s_wid ), - .swdata_i (mac_s_wdata ), - .swstrb_i (mac_s_wstrb ), - .swlast_i (mac_s_wlast ), - .swvalid_i (mac_s_wvalid ), - .swready_o (mac_s_wready ), - .sbid_o (mac_s_bid ), - .sbresp_o (mac_s_bresp ), - .sbvalid_o (mac_s_bvalid ), - .sbready_i (mac_s_bready ), - .sarid_i (mac_s_arid ), - .saraddr_i (mac_s_araddr ), - .sarlen_i (mac_s_arlen ), - .sarsize_i (mac_s_arsize ), - .sarburst_i (mac_s_arburst ), - .sarlock_i (mac_s_arlock ), - .sarcache_i (mac_s_arcache ), - .sarprot_i (mac_s_arprot ), - .sarvalid_i (mac_s_arvalid ), - .sarready_o (mac_s_arready ), - .srid_o (mac_s_rid ), - .srdata_o (mac_s_rdata ), - .srresp_o (mac_s_rresp ), - .srlast_o (mac_s_rlast ), - .srvalid_o (mac_s_rvalid ), - .srready_i (mac_s_rready ), - - .interrupt_0 (mac_int), - - // I/O pad interface signals - //TX - .mtxclk_0 (mtxclk_0 ), - .mtxen_0 (mtxen_0 ), - .mtxd_0 (mtxd_0 ), - .mtxerr_0 (mtxerr_0 ), - //RX - .mrxclk_0 (mrxclk_0 ), - .mrxdv_0 (mrxdv_0 ), - .mrxd_0 (mrxd_0 ), - .mrxerr_0 (mrxerr_0 ), - .mcoll_0 (mcoll_0 ), - .mcrs_0 (mcrs_0 ), - // MIIM - .mdc_0 (mdc_0 ), - .md_i_0 (md_i_0 ), - .md_o_0 (md_o_0 ), - .md_oe_0 (md_oe_0 ) - -); - -//ddr3 -wire c1_sys_clk_i; -wire c1_clk_ref_i; -wire c1_sys_rst_i; -wire c1_calib_done; -wire c1_clk0; -wire c1_rst0; -wire ddr_aresetn; -reg interconnect_aresetn; - -wire cpu_clk; -clk_pll_33 clk_pll_33 - ( - // Clock out ports - .clk_out1(cpu_clk), //33MHz - // Clock in ports - .clk_in1(clk) //100MHz - ); - -clk_wiz_0 clk_pll_1 -( - .clk_out1(c1_clk_ref_i), //200MHz - .clk_in1(clk) //100MHz -); - -assign c1_sys_clk_i = clk; -assign c1_sys_rst_i = resetn; -assign aclk = cpu_clk; -//assign aclk = c1_clk0; -// Reset to the AXI shim -reg c1_calib_done_0; -reg c1_calib_done_1; -reg c1_rst0_0; -reg c1_rst0_1; -reg interconnect_aresetn_0; -/*always @(posedge aclk) -begin - c1_calib_done_0 <= c1_calib_done; - c1_calib_done_1 <= c1_calib_done_0; - c1_rst0_0 <= c1_rst0; - c1_rst0_1 <= c1_rst0_0; - - interconnect_aresetn_0 <= ~c1_rst0_1 && c1_calib_done_1; - interconnect_aresetn <= interconnect_aresetn_0 ; -end*/ -always @(posedge c1_clk0) -begin - interconnect_aresetn <= ~c1_rst0 && c1_calib_done; -end - -//axi 3x1 -axi_interconnect_0 mig_axi_interconnect ( - .INTERCONNECT_ACLK (c1_clk0 ), - .INTERCONNECT_ARESETN (interconnect_aresetn), - .S00_AXI_ARESET_OUT_N (aresetn ), - .S00_AXI_ACLK (aclk ), - .S00_AXI_AWID (s0_awid[3:0] ), - .S00_AXI_AWADDR (s0_awaddr ), - .S00_AXI_AWLEN ({4'b0,s0_awlen} ), - .S00_AXI_AWSIZE (s0_awsize ), - .S00_AXI_AWBURST (s0_awburst ), - .S00_AXI_AWLOCK (s0_awlock[0:0] ), - .S00_AXI_AWCACHE (s0_awcache ), - .S00_AXI_AWPROT (s0_awprot ), - .S00_AXI_AWQOS (4'b0 ), - .S00_AXI_AWVALID (s0_awvalid ), - .S00_AXI_AWREADY (s0_awready ), - .S00_AXI_WDATA (s0_wdata ), - .S00_AXI_WSTRB (s0_wstrb ), - .S00_AXI_WLAST (s0_wlast ), - .S00_AXI_WVALID (s0_wvalid ), - .S00_AXI_WREADY (s0_wready ), - .S00_AXI_BID (s0_bid[3:0] ), - .S00_AXI_BRESP (s0_bresp ), - .S00_AXI_BVALID (s0_bvalid ), - .S00_AXI_BREADY (s0_bready ), - .S00_AXI_ARID (s0_arid[3:0] ), - .S00_AXI_ARADDR (s0_araddr ), - .S00_AXI_ARLEN ({4'b0,s0_arlen} ), - .S00_AXI_ARSIZE (s0_arsize ), - .S00_AXI_ARBURST (s0_arburst ), - .S00_AXI_ARLOCK (s0_arlock[0:0] ), - .S00_AXI_ARCACHE (s0_arcache ), - .S00_AXI_ARPROT (s0_arprot ), - .S00_AXI_ARQOS (4'b0 ), - .S00_AXI_ARVALID (s0_arvalid ), - .S00_AXI_ARREADY (s0_arready ), - .S00_AXI_RID (s0_rid[3:0] ), - .S00_AXI_RDATA (s0_rdata ), - .S00_AXI_RRESP (s0_rresp ), - .S00_AXI_RLAST (s0_rlast ), - .S00_AXI_RVALID (s0_rvalid ), - .S00_AXI_RREADY (s0_rready ), - - .S01_AXI_ARESET_OUT_N ( ), - .S01_AXI_ACLK (aclk ), - .S01_AXI_AWID (mac_m_awid[3:0] ), - .S01_AXI_AWADDR (mac_m_awaddr ), - .S01_AXI_AWLEN ({4'b0,mac_m_awlen} ), - .S01_AXI_AWSIZE (mac_m_awsize ), - .S01_AXI_AWBURST (mac_m_awburst ), - .S01_AXI_AWLOCK (mac_m_awlock[0:0] ), - .S01_AXI_AWCACHE (mac_m_awcache ), - .S01_AXI_AWPROT (mac_m_awprot ), - .S01_AXI_AWQOS (4'b0 ), - .S01_AXI_AWVALID (mac_m_awvalid ), - .S01_AXI_AWREADY (mac_m_awready ), - .S01_AXI_WDATA (mac_m_wdata ), - .S01_AXI_WSTRB (mac_m_wstrb ), - .S01_AXI_WLAST (mac_m_wlast ), - .S01_AXI_WVALID (mac_m_wvalid ), - .S01_AXI_WREADY (mac_m_wready ), - .S01_AXI_BID (mac_m_bid[3:0] ), - .S01_AXI_BRESP (mac_m_bresp ), - .S01_AXI_BVALID (mac_m_bvalid ), - .S01_AXI_BREADY (mac_m_bready ), - .S01_AXI_ARID (mac_m_arid[3:0] ), - .S01_AXI_ARADDR (mac_m_araddr ), - .S01_AXI_ARLEN ({4'b0,mac_m_arlen} ), - .S01_AXI_ARSIZE (mac_m_arsize ), - .S01_AXI_ARBURST (mac_m_arburst ), - .S01_AXI_ARLOCK (mac_m_arlock[0:0] ), - .S01_AXI_ARCACHE (mac_m_arcache ), - .S01_AXI_ARPROT (mac_m_arprot ), - .S01_AXI_ARQOS (4'b0 ), - .S01_AXI_ARVALID (mac_m_arvalid ), - .S01_AXI_ARREADY (mac_m_arready ), - .S01_AXI_RID (mac_m_rid[3:0] ), - .S01_AXI_RDATA (mac_m_rdata ), - .S01_AXI_RRESP (mac_m_rresp ), - .S01_AXI_RLAST (mac_m_rlast ), - .S01_AXI_RVALID (mac_m_rvalid ), - .S01_AXI_RREADY (mac_m_rready ), - - .S02_AXI_ARESET_OUT_N ( ), - .S02_AXI_ACLK (aclk ), - .S02_AXI_AWID (dma0_awid ), - .S02_AXI_AWADDR (dma0_awaddr ), - .S02_AXI_AWLEN ({4'd0,dma0_awlen} ), - .S02_AXI_AWSIZE (dma0_awsize ), - .S02_AXI_AWBURST (dma0_awburst ), - .S02_AXI_AWLOCK (dma0_awlock[0:0] ), - .S02_AXI_AWCACHE (dma0_awcache ), - .S02_AXI_AWPROT (dma0_awprot ), - .S02_AXI_AWQOS (4'b0 ), - .S02_AXI_AWVALID (dma0_awvalid ), - .S02_AXI_AWREADY (dma0_awready ), - .S02_AXI_WDATA (dma0_wdata ), - .S02_AXI_WSTRB (dma0_wstrb ), - .S02_AXI_WLAST (dma0_wlast ), - .S02_AXI_WVALID (dma0_wvalid ), - .S02_AXI_WREADY (dma0_wready ), - .S02_AXI_BID (dma0_bid ), - .S02_AXI_BRESP (dma0_bresp ), - .S02_AXI_BVALID (dma0_bvalid ), - .S02_AXI_BREADY (dma0_bready ), - .S02_AXI_ARID (dma0_arid ), - .S02_AXI_ARADDR (dma0_araddr ), - .S02_AXI_ARLEN ({4'd0,dma0_arlen} ), - .S02_AXI_ARSIZE (dma0_arsize ), - .S02_AXI_ARBURST (dma0_arburst ), - .S02_AXI_ARLOCK (dma0_arlock[0:0] ), - .S02_AXI_ARCACHE (dma0_arcache ), - .S02_AXI_ARPROT (dma0_arprot ), - .S02_AXI_ARQOS (4'b0 ), - .S02_AXI_ARVALID (dma0_arvalid ), - .S02_AXI_ARREADY (dma0_arready ), - .S02_AXI_RID (dma0_rid ), - .S02_AXI_RDATA (dma0_rdata ), - .S02_AXI_RRESP (dma0_rresp ), - .S02_AXI_RLAST (dma0_rlast ), - .S02_AXI_RVALID (dma0_rvalid ), - .S02_AXI_RREADY (dma0_rready ), - - .M00_AXI_ARESET_OUT_N (ddr_aresetn ), - .M00_AXI_ACLK (c1_clk0 ), - .M00_AXI_AWID (mig_awid ), - .M00_AXI_AWADDR (mig_awaddr ), - .M00_AXI_AWLEN ({mig_awlen} ), - .M00_AXI_AWSIZE (mig_awsize ), - .M00_AXI_AWBURST (mig_awburst ), - .M00_AXI_AWLOCK (mig_awlock[0:0] ), - .M00_AXI_AWCACHE (mig_awcache ), - .M00_AXI_AWPROT (mig_awprot ), - .M00_AXI_AWQOS ( ), - .M00_AXI_AWVALID (mig_awvalid ), - .M00_AXI_AWREADY (mig_awready ), - .M00_AXI_WDATA (mig_wdata ), - .M00_AXI_WSTRB (mig_wstrb ), - .M00_AXI_WLAST (mig_wlast ), - .M00_AXI_WVALID (mig_wvalid ), - .M00_AXI_WREADY (mig_wready ), - .M00_AXI_BID (mig_bid ), - .M00_AXI_BRESP (mig_bresp ), - .M00_AXI_BVALID (mig_bvalid ), - .M00_AXI_BREADY (mig_bready ), - .M00_AXI_ARID (mig_arid ), - .M00_AXI_ARADDR (mig_araddr ), - .M00_AXI_ARLEN ({mig_arlen} ), - .M00_AXI_ARSIZE (mig_arsize ), - .M00_AXI_ARBURST (mig_arburst ), - .M00_AXI_ARLOCK (mig_arlock[0:0] ), - .M00_AXI_ARCACHE (mig_arcache ), - .M00_AXI_ARPROT (mig_arprot ), - .M00_AXI_ARQOS ( ), - .M00_AXI_ARVALID (mig_arvalid ), - .M00_AXI_ARREADY (mig_arready ), - .M00_AXI_RID (mig_rid ), - .M00_AXI_RDATA (mig_rdata ), - .M00_AXI_RRESP (mig_rresp ), - .M00_AXI_RLAST (mig_rlast ), - .M00_AXI_RVALID (mig_rvalid ), - .M00_AXI_RREADY (mig_rready ) -); -//ddr3 controller -mig_axi_32 mig_axi ( - // Inouts - .ddr3_dq (ddr3_dq ), - .ddr3_dqs_p (ddr3_dqs_p ), // for X16 parts - .ddr3_dqs_n (ddr3_dqs_n ), // for X16 parts - // Outputs - .ddr3_addr (ddr3_addr ), - .ddr3_ba (ddr3_ba ), - .ddr3_ras_n (ddr3_ras_n ), - .ddr3_cas_n (ddr3_cas_n ), - .ddr3_we_n (ddr3_we_n ), - .ddr3_reset_n (ddr3_reset_n ), - .ddr3_ck_p (ddr3_ck_p ), - .ddr3_ck_n (ddr3_ck_n ), - .ddr3_cke (ddr3_cke ), - .ddr3_dm (ddr3_dm ), - .ddr3_odt (ddr3_odt ), - - .ui_clk (c1_clk0 ), - .ui_clk_sync_rst (c1_rst0 ), - - .sys_clk_i (c1_sys_clk_i ), - .sys_rst (c1_sys_rst_i ), - .init_calib_complete (c1_calib_done ), - .clk_ref_i (c1_clk_ref_i ), - .mmcm_locked ( ), - - .app_sr_active ( ), - .app_ref_ack ( ), - .app_zq_ack ( ), - .app_sr_req (1'b0 ), - .app_ref_req (1'b0 ), - .app_zq_req (1'b0 ), - - .aresetn (ddr_aresetn ), - .s_axi_awid (mig_awid ), - .s_axi_awaddr (mig_awaddr[26:0]), - .s_axi_awlen ({mig_awlen} ), - .s_axi_awsize (mig_awsize ), - .s_axi_awburst (mig_awburst ), - .s_axi_awlock (mig_awlock[0:0] ), - .s_axi_awcache (mig_awcache ), - .s_axi_awprot (mig_awprot ), - .s_axi_awqos (4'b0 ), - .s_axi_awvalid (mig_awvalid ), - .s_axi_awready (mig_awready ), - .s_axi_wdata (mig_wdata ), - .s_axi_wstrb (mig_wstrb ), - .s_axi_wlast (mig_wlast ), - .s_axi_wvalid (mig_wvalid ), - .s_axi_wready (mig_wready ), - .s_axi_bid (mig_bid ), - .s_axi_bresp (mig_bresp ), - .s_axi_bvalid (mig_bvalid ), - .s_axi_bready (mig_bready ), - .s_axi_arid (mig_arid ), - .s_axi_araddr (mig_araddr[26:0]), - .s_axi_arlen ({mig_arlen} ), - .s_axi_arsize (mig_arsize ), - .s_axi_arburst (mig_arburst ), - .s_axi_arlock (mig_arlock[0:0] ), - .s_axi_arcache (mig_arcache ), - .s_axi_arprot (mig_arprot ), - .s_axi_arqos (4'b0 ), - .s_axi_arvalid (mig_arvalid ), - .s_axi_arready (mig_arready ), - .s_axi_rid (mig_rid ), - .s_axi_rdata (mig_rdata ), - .s_axi_rresp (mig_rresp ), - .s_axi_rlast (mig_rlast ), - .s_axi_rvalid (mig_rvalid ), - .s_axi_rready (mig_rready ) -); - -//DMA -dma_master DMA_MASTER0 -( -.clk (aclk ), -.rst_n (aresetn ), -.awid (dma0_awid ), -.awaddr (dma0_awaddr ), -.awlen (dma0_awlen ), -.awsize (dma0_awsize ), -.awburst (dma0_awburst ), -.awlock (dma0_awlock ), -.awcache (dma0_awcache ), -.awprot (dma0_awprot ), -.awvalid (dma0_awvalid ), -.awready (dma0_awready ), -.wid (dma0_wid ), -.wdata (dma0_wdata ), -.wstrb (dma0_wstrb ), -.wlast (dma0_wlast ), -.wvalid (dma0_wvalid ), -.wready (dma0_wready ), -.bid (dma0_bid ), -.bresp (dma0_bresp ), -.bvalid (dma0_bvalid ), -.bready (dma0_bready ), -.arid (dma0_arid ), -.araddr (dma0_araddr ), -.arlen (dma0_arlen ), -.arsize (dma0_arsize ), -.arburst (dma0_arburst ), -.arlock (dma0_arlock ), -.arcache (dma0_arcache ), -.arprot (dma0_arprot ), -.arvalid (dma0_arvalid ), -.arready (dma0_arready ), -.rid (dma0_rid ), -.rdata (dma0_rdata ), -.rresp (dma0_rresp ), -.rlast (dma0_rlast ), -.rvalid (dma0_rvalid ), -.rready (dma0_rready ), - -.dma_int (dma_int ), -.dma_req_in (dma_req ), -.dma_ack_out (dma_ack ), - -.dma_gnt (dma0_gnt ), -.apb_rw (apb_rw_dma0 ), -.apb_psel (apb_psel_dma0 ), -.apb_valid_req (apb_start_dma0 ), -.apb_penable (apb_penable_dma0 ), -.apb_addr (apb_addr_dma0 ), -.apb_wdata (apb_wdata_dma0 ), -.apb_rdata (apb_rdata_dma0 ), - -.order_addr_in (order_addr_in ), -.write_dma_end (write_dma_end ), -.finish_read_order (finish_read_order ) -); - -//AXI2APB -axi2apb_misc APB_DEV -( -.clk (aclk ), -.rst_n (aresetn ), - -.axi_s_awid (apb_s_awid ), -.axi_s_awaddr (apb_s_awaddr ), -.axi_s_awlen (apb_s_awlen ), -.axi_s_awsize (apb_s_awsize ), -.axi_s_awburst (apb_s_awburst ), -.axi_s_awlock (apb_s_awlock ), -.axi_s_awcache (apb_s_awcache ), -.axi_s_awprot (apb_s_awprot ), -.axi_s_awvalid (apb_s_awvalid ), -.axi_s_awready (apb_s_awready ), -.axi_s_wid (apb_s_wid ), -.axi_s_wdata (apb_s_wdata ), -.axi_s_wstrb (apb_s_wstrb ), -.axi_s_wlast (apb_s_wlast ), -.axi_s_wvalid (apb_s_wvalid ), -.axi_s_wready (apb_s_wready ), -.axi_s_bid (apb_s_bid ), -.axi_s_bresp (apb_s_bresp ), -.axi_s_bvalid (apb_s_bvalid ), -.axi_s_bready (apb_s_bready ), -.axi_s_arid (apb_s_arid ), -.axi_s_araddr (apb_s_araddr ), -.axi_s_arlen (apb_s_arlen ), -.axi_s_arsize (apb_s_arsize ), -.axi_s_arburst (apb_s_arburst ), -.axi_s_arlock (apb_s_arlock ), -.axi_s_arcache (apb_s_arcache ), -.axi_s_arprot (apb_s_arprot ), -.axi_s_arvalid (apb_s_arvalid ), -.axi_s_arready (apb_s_arready ), -.axi_s_rid (apb_s_rid ), -.axi_s_rdata (apb_s_rdata ), -.axi_s_rresp (apb_s_rresp ), -.axi_s_rlast (apb_s_rlast ), -.axi_s_rvalid (apb_s_rvalid ), -.axi_s_rready (apb_s_rready ), - -.apb_rw_dma (apb_rw_dma0 ), -.apb_psel_dma (apb_psel_dma0 ), -.apb_enab_dma (apb_penable_dma0 ), -.apb_addr_dma (apb_addr_dma0[19:0]), -.apb_valid_dma (apb_start_dma0 ), -.apb_wdata_dma (apb_wdata_dma0 ), -.apb_rdata_dma (apb_rdata_dma0 ), -.apb_ready_dma ( ), //output, no use -.dma_grant (dma0_gnt ), - -.dma_req_o (dma_req ), -.dma_ack_i (dma_ack ), - -//UART0 -.uart0_txd_i (uart0_txd_i ), -.uart0_txd_o (uart0_txd_o ), -.uart0_txd_oe (uart0_txd_oe ), -.uart0_rxd_i (uart0_rxd_i ), -.uart0_rxd_o (uart0_rxd_o ), -.uart0_rxd_oe (uart0_rxd_oe ), -.uart0_rts_o (uart0_rts_o ), -.uart0_dtr_o (uart0_dtr_o ), -.uart0_cts_i (uart0_cts_i ), -.uart0_dsr_i (uart0_dsr_i ), -.uart0_dcd_i (uart0_dcd_i ), -.uart0_ri_i (uart0_ri_i ), -.uart0_int (uart0_int ), - -.nand_type (2'h2 ), //1Gbit -.nand_cle (nand_cle ), -.nand_ale (nand_ale ), -.nand_rdy (nand_rdy ), -.nand_rd (nand_rd ), -.nand_ce (nand_ce ), -.nand_wr (nand_wr ), -.nand_dat_i (nand_dat_i ), -.nand_dat_o (nand_dat_o ), -.nand_dat_oe (nand_dat_oe ), - -.nand_int (nand_int ) -); -endmodule - diff --git a/resources/soc/rtl/cpu232/龙芯开源处理器gs232源码，目前缺少，请联系龙芯开源获得.txt b/resources/soc/rtl/cpu232/龙芯开源处理器gs232源码，目前缺少，请联系龙芯开源获得.txt deleted file mode 100644 index 1c57634..0000000 --- a/resources/soc/rtl/cpu232/龙芯开源处理器gs232源码，目前缺少，请联系龙芯开源获得.txt +++ /dev/null @@ -1,7 +0,0 @@ - -1.龙芯开源处理器GS232源码是可以免费获得的。 - -2.但是为了更好地对GS232源码进行版本维护和流通追溯，此处无法直接提供源码。 - -3.高校老师可在龙芯官网上通过开源申请获得GS232源码。 - diff --git a/resources/soc/simu/run/run_func/lib.list b/resources/soc/simu/run/run_func/lib.list deleted file mode 100644 index 8d1ff4d..0000000 --- a/resources/soc/simu/run/run_func/lib.list +++ /dev/null @@ -1,82 +0,0 @@ -../../lib/sram_simu.v -../../lib/func_emul/cell_emul.v -../../lib/glbl.v -../../lib/AND2B1L.v -../../lib/BUFG.v -../../lib/BUFGCE.v -../../lib/BUFGMUX.v -../../lib/BUFPLL_MCB.v -../../lib/DCM_SP.v -../../lib/FDRE.v -../../lib/FDSE.v -../../lib/IBUFG.v -../../lib/INV.v -../../lib/IOBUF.v -../../lib/IOBUFDS.v -../../lib/IODRP2.v -../../lib/IODRP2_MCB.v -../../lib/LUT4.v -../../lib/LUT6.v -../../lib/LUT6_2.v -../../lib/MCB.v -../../lib/MUXCY.v -../../lib/OBUFDS.v -../../lib/OBUFT.v -../../lib/OBUFTDS.v -../../lib/OR2L.v -../../lib/OSERDES2.v -../../lib/PLL_ADV.v -../../lib/PULLDOWN.v -../../lib/PULLUP.v -../../lib/SRLC32E.v -../../lib/XORCY.v -../../lib/BLK_MEM_GEN_V6_2.v -../../lib/BLK_MEM_GEN_V6_1.v -../../lib/mcb_001.vp -../../lib/mcb_002.vp -../../lib/mcb_003.vp -../../lib/mcb_004.vp -../../lib/mcb_005.vp -../../lib/mcb_006.vp -../../lib/mcb_007.vp -../../lib/mcb_008.vp -../../lib/mcb_009.vp -../../lib/mcb_010.vp -../../lib/mcb_011.vp -../../lib/mcb_012.vp -../../lib/mcb_013.vp -../../lib/mcb_014.vp -../../lib/mcb_015.vp -../../lib/mcb_016.vp -../../lib/mcb_017.vp -../../lib/mcb_018.vp -../../lib/mcb_019.vp -../../lib/mcb_020.vp -../../lib/mcb_021.vp -../../lib/mcb_022.vp -../../lib/mcb_023.vp -../../lib/mcb_024.vp -../../lib/mcb_025.vp -../../lib/mcb_026.vp -../../lib/mcb_027.vp -../../lib/mcb_028.vp -../../lib/mcb_029.vp -../../lib/mcb_030.vp -../../lib/mcb_031.vp -../../lib/mcb_032.vp -../../lib/mcb_033.vp -../../lib/mcb_034.vp -../../lib/mcb_035.vp -../../lib/mcb_036.vp -../../lib/mcb_037.vp -../../lib/mcb_038.vp -../../lib/mcb_039.vp -../../lib/mcb_040.vp -../../lib/mcb_041.vp -../../lib/mcb_042.vp -../../lib/mcb_043.vp -../../lib/mcb_044.vp -../../lib/mcb_045.vp -../../lib/mcb_046.vp -../../lib/mcb_047.vp - diff --git a/resources/soc/simu/run/run_func/ncompile b/resources/soc/simu/run/run_func/ncompile deleted file mode 100644 index b04118c..0000000 --- a/resources/soc/simu/run/run_func/ncompile +++ /dev/null @@ -1,3 +0,0 @@ -#!/bin/bash - -ncverilog -f run.f diff --git a/resources/soc/simu/run/run_func/rtl.list b/resources/soc/simu/run/run_func/rtl.list deleted file mode 100644 index 423a71f..0000000 --- a/resources/soc/simu/run/run_func/rtl.list +++ /dev/null @@ -1,117 +0,0 @@ -../../../rtl/TOP/archlab_sopc_top.v - -../../../rtl/CPU/axi_interface.v -../../../rtl/CPU/godson_addr_module.v -../../../rtl/CPU/godson_alu_module.v -../../../rtl/CPU/godson_bus_module.v -../../../rtl/CPU/godson_cpu_core.v -../../../rtl/CPU/godson_cpu_mid.v -../../../rtl/CPU/godson_dcache_module.v -../../../rtl/CPU/godson_dcr_module.v -../../../rtl/CPU/godson_decoder_module.v -../../../rtl/CPU/godson_dtlb_module.v -../../../rtl/CPU/godson_ejtag_tap_module.v -../../../rtl/CPU/godson_fetch_module.v -../../../rtl/CPU/godson_gr_module.v -../../../rtl/CPU/godson_hb_module.v -../../../rtl/CPU/godson_icache_module.v -../../../rtl/CPU/godson_itlb_module.v -../../../rtl/CPU/godson_memqueue_module.v -../../../rtl/CPU/godson_queue_module.v -../../../rtl/CPU/godson_ram_bist.v -../../../rtl/CPU/godson_rs_module.v -../../../rtl/CPU/godson_tap_buffer_module.v -../../../rtl/CPU/tools.v - -../../../rtl/CPU/sram/sram_128x22.v -../../../rtl/CPU/sram/sram_128x32.v -../../../rtl/CPU/sram/sram_128x64.v -../../../rtl/CPU/sram/sram_32x52bit.v - -../../../rtl/AMBA/axi_mux.v -../../../rtl/AMBA/axi2apb.v - -../../../rtl/MIG/memc_wrapper.v -../../../rtl/MIG/ddr3_3port.v -../../../rtl/MIG/infrastructure.v -../../../rtl/MIG/axi/a_upsizer.v -../../../rtl/MIG/axi/axi_mcb.v -../../../rtl/MIG/axi/axi_mcb_ar_channel.v -../../../rtl/MIG/axi/axi_mcb_aw_channel.v -../../../rtl/MIG/axi/axi_mcb_b_channel.v -../../../rtl/MIG/axi/axi_mcb_cmd_arbiter.v -../../../rtl/MIG/axi/axi_mcb_cmd_fsm.v -../../../rtl/MIG/axi/axi_mcb_cmd_translator.v -../../../rtl/MIG/axi/axi_mcb_incr_cmd.v -../../../rtl/MIG/axi/axi_mcb_r_channel.v -../../../rtl/MIG/axi/axi_mcb_simple_fifo.v -../../../rtl/MIG/axi/axi_mcb_w_channel.v -../../../rtl/MIG/axi/axi_mcb_wrap_cmd.v -../../../rtl/MIG/axi/axi_register_slice.v -../../../rtl/MIG/axi/axi_upsizer.v -../../../rtl/MIG/axi/axic_register_slice.v -../../../rtl/MIG/axi/carry.v -../../../rtl/MIG/axi/carry_and.v -../../../rtl/MIG/axi/carry_latch_and.v -../../../rtl/MIG/axi/carry_latch_or.v -../../../rtl/MIG/axi/carry_or.v -../../../rtl/MIG/axi/command_fifo.v -../../../rtl/MIG/axi/comparator.v -../../../rtl/MIG/axi/comparator_mask.v -../../../rtl/MIG/axi/comparator_mask_static.v -../../../rtl/MIG/axi/comparator_sel.v -../../../rtl/MIG/axi/comparator_sel_mask.v -../../../rtl/MIG/axi/comparator_sel_mask_static.v -../../../rtl/MIG/axi/comparator_sel_static.v -../../../rtl/MIG/axi/comparator_static.v -../../../rtl/MIG/axi/mcb_ui_top_synch.v -../../../rtl/MIG/axi/mux_enc.v -../../../rtl/MIG/axi/r_upsizer.v -../../../rtl/MIG/axi/w_upsizer.v -../../../rtl/MIG/mcb_controller/iodrp_controller.v -../../../rtl/MIG/mcb_controller/iodrp_mcb_controller.v -../../../rtl/MIG/mcb_controller/mcb_raw_wrapper.v -../../../rtl/MIG/mcb_controller/mcb_soft_calibration.v -../../../rtl/MIG/mcb_controller/mcb_soft_calibration_top.v -../../../rtl/MIG/mcb_controller/mcb_ui_top.v - -../../../rtl/APB_DEV/URT/raminfr.v -../../../rtl/APB_DEV/URT/uart_receiver.v -../../../rtl/APB_DEV/URT/uart_regs.v -../../../rtl/APB_DEV/URT/uart_rfifo.v -../../../rtl/APB_DEV/URT/uart_sync_flops.v -../../../rtl/APB_DEV/URT/uart_tfifo.v -../../../rtl/APB_DEV/URT/uart_top.v -../../../rtl/APB_DEV/URT/uart_transmitter.v - -../../../rtl/CONFREG/confreg.v -../../../rtl/SPI/godson_sbridge_spi.v - -../../../rtl/MAC/utility.v -../../../rtl/MAC/ethernet_top.v -../../../rtl/MAC/mac_top.v -../../../rtl/MAC/mac_axi.v -../../../rtl/MAC/mac.v -../../../rtl/MAC/csr.v -../../../rtl/MAC/rc.v -../../../rtl/MAC/rfifo.v -../../../rtl/MAC/rlsm.v -../../../rtl/MAC/tc.v -../../../rtl/MAC/bd.v -../../../rtl/MAC/dma.v -../../../rtl/MAC/rstc.v -../../../rtl/MAC/tfifo.v -../../../rtl/MAC/tlsm.v -../../../rtl/MAC/mac2axi.v -../../../rtl/MAC/maccsr2axi.v -../../../rtl/MAC/macdata2axi.v -../../../rtl/MAC/cam.v -../../../rtl/MAC/dpram_512x32.v - -../../../rtl/DMA/dma.v - -../../../rtl/APB_DEV/apb_dev_top.v -../../../rtl/APB_DEV/apb_mux2.v -../../../rtl/APB_DEV/nand_module.v - -../../../rtl/APB_DEV/NAND/nand.v diff --git a/resources/soc/simu/run/run_func/run.f b/resources/soc/simu/run/run_func/run.f deleted file mode 100644 index a0e96c5..0000000 --- a/resources/soc/simu/run/run_func/run.f +++ /dev/null @@ -1,28 +0,0 @@ -+incdir+../../../rtl/TOP -+incdir+../../../rtl/CPU -+incdir+../../../rtl/APB_DEV -+incdir+../../../rtl/APB_DEV/NAND -+incdir+../../../rtl/APB_DEV/URT -+incdir+../../../rtl/SPI -+incdir+../../../rtl/MIG -+incdir+../../../rtl/MAC -+incdir+../../../rtl/AMBA -+incdir+../../../rtl/CONFREG -+incdir+../../testbench -+incdir+../../testbench/vmac -+nclog_ncsim+ncsim.log -+access+rw --sv --64bit --nowarn MRSTAR -+pathpulse -+profile -+define+x1Gb -+define+sg15E -+define+x16 -+define+VIRTUAL_MAC -+define+_DUMPDUMP --f sys.list --f rtl.list --f lib.list - diff --git a/resources/soc/simu/run/run_func/sys.list b/resources/soc/simu/run/run_func/sys.list deleted file mode 100644 index 8462747..0000000 --- a/resources/soc/simu/run/run_func/sys.list +++ /dev/null @@ -1,11 +0,0 @@ -../../testbench/godson_system.v -../../testbench/MX25L6405D.v -../../testbench/uart_dev.v -../../testbench/ejtag_virtual_host.v -../../testbench/ddr3_model_c1.v -../../testbench/vmac/virtual_mac.v -../../testbench/vmac/mac_top.v -../../testbench/vmac/mac_ram.v -../../testbench/nand_sim.v - - diff --git a/resources/soc/simu/soft/func/Makefile b/resources/soc/simu/soft/func/Makefile deleted file mode 100644 index 477a6ae..0000000 --- a/resources/soc/simu/soft/func/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -TOPDIR = $(shell pwd) - -CROSS_COMPILE = mipsel-linux- -DEBUG = -g -FLAGS = - -CC = $(CROSS_COMPILE)gcc -LD = $(CROSS_COMPILE)ld -OBJCOPY = $(CROSS_COMPILE)objcopy -OBJDUMP = $(CROSS_COMPILE)objdump -AR = $(CROSS_COMPILE)ar - -export TOPDIR AR CC DEBUG FLAGS - -all:test.bin convert - ./convert - $(OBJDUMP) -ald test >test.s - -libtinyc.a: - make -C lib $(TOPDIR)/$@ - -start.o:start.S include/ls1d.h include/asm/mipsregs.h include/asm/regdef.h include/asm/ns16550.h - $(CC) $(DEBUG) $(FLAGS) -mips32 -EL -c -o $@ $< - -nand.o:nand_test.S include/ls1d.h include/asm/mipsregs.h include/asm/regdef.h include/asm/ns16550.h - $(CC) $(DEBUG) $(FLAGS) -mips32 -EL -c -o $@ $< - -main.o:main.c include/*.h - $(CC) $(DEBUG) $(FLAGS) -EL -c -o $@ $< - -%.o:source/%.c include/%.h include/ls1d.h - $(CC) $(DEBUG) $(FLAGS) -EL -c -o $@ $< - -#test_cycle.o myprintf.o -OBJ1 = Interrupt.o lcd.o SystemInit.o Calendar.o key.o battery.o common.o temp_flow.o Infrare.o frame.o MonthData.o isp.o adc.o cmdline.o flash.o dg_rs232.o - -test:start.o nand.o main.o $(OBJ1) libtinyc.a - $(LD) -T test.lds -Ttext 0xBFC00000 -Map test.map start.o nand.o main.o $(OBJ1) -o $@ -L . -ltinyc - #rm -f *.o - -test.bin:test - $(OBJCOPY) --gap-fill=0xff -O binary $< $@ - -clean: - rm -f *.o *.a test test.bin test.map test.s convert flash.vlog - make -C lib clean -convert:convert.c - gcc -o convert convert.c diff --git a/resources/soc/simu/soft/func/config.h b/resources/soc/simu/soft/func/config.h deleted file mode 100644 index 31c1864..0000000 --- a/resources/soc/simu/soft/func/config.h +++ /dev/null @@ -1,179 +0,0 @@ -#include "include/ls1d.h" -#include "include/SystemInit.h" -#include "include/Calendar.h" -#include "include/lcd.h" -#include "include/key.h" -#include "include/common.h" -#include "include/temp_flow.h" -#include "include/MonthData.h" -#include "include/Infrare.h" -#include "include/frame.h" -#include "include/battery.h" -#include "include/Interrupt.h" -#include "include/xmodem.h" -#include "include/isp.h" -#include "include/cmdline.h" -//#include "myprintf.h" -//#include "test_cycle.h" - -//#include -//#include - -#define DisableWatchDog() PMU_Command &= 0xdfffffff ; -#define EnableWatchDog() PMU_Command |= 0x20000000 ; -#define FeedWatchDog() PMU_CommandW = 0x40000000 ; - -#define NUM 10 -extern _u32 wait[NUM]; -extern _u32 main_flag; -extern _u32 work_mode; -extern _u32 *PMU; -extern _u32 *Sonar; -extern _u32 *Thsens; - -/********************************Defined by user*******************************************************************************************************************/ -#define IR_PWR_ON PMU_GPIO_O |= (1 << 3) //Infrare receiver power on -#define IR_PWR_OFF PMU_GPIO_O &=~(1 << 3) //Infrare receiver power off -#define KEY_OFF 0x10 //when the key is off, the key_bit of gpio_in will be high - -#define STDC_CALIBRATE 200 //default value -#define COUNT_MASK 0xffffff //refer to count reg, PMU -#define COUNT_COMPARE 0X1000000 - -#define LCD_MULTIPLE 100000 //every varible printed in lcd will plus LCD_MULTIPLE, thus the real value should divide LCD_MULTIPLE -#define LCD_LENGTH 10 //the lcd buf will divide into LCD_LENGTH -#define LCD_NUM_LENGTH 8 //the numbers of number that the lcd can print - -#define CJT188_DI_SEQ 1 //it will change the sequence of DI0 and DI1 -#define CJT188_DEF_READ 0x0e -#define CJT188_DEF_WRITE 0x1e - -#define UART1_INT 0 //enable uart1_rx_int when a key comes, then disable it when received a right frame - - -/***********************************xmodem Option*****************************************************************************************************************/ -#define FLASH_BLOCK_SIZE 256 -#define FLASH_ERASE_START 0xbfc00000 -#define FLASH_ERASE_END 0xbfc0efff //60kB - -/********************************Info flash Option****************************************************************************************************************/ -#define INFO_FLASH_START 0xbfc0fe00 -#define AUTO_SAVE_ADDR 0xbfc0fd00 - -/********************************Pipe Option**********************************************************************************************************************/ -#define SOUND_PATH 0.072f //m -#define COS_RESULT 1 -#define K_COEFFICIENT 0.5f -#define DIAMETER 0.020f //m -#define PI 3.1415926f -#define CONST PI/4 - -/********************************Compile Option**********************************************************************************************************************/ -#define ISP 1 //ISP module -#define LS1D_FPGA 1 //Choose code for fpga_board or chip_flash. - -#define AD_MODULE 0 -#define ADC_MODULE 0 -#define LCD_MODULE 0 -#define TDC_TEMP_MODULE 0 -#define TDC_FLOW_MODULE 0 -#define MONTHDATA_MODULE 0 -#define KEY_MODULE 0 -#define MBUS_MODULE 0 -#define INFRARE_MODULE 0 -#define CALENDAR_MODULE 0 //need TIMER_MODULE and LCD_MODULE -#define FRAME_MODULE 0 -#define TIMER_MODULE 0 - - -/********************************Debug Option/Print*******************************************************************************************************************/ -#define PRINT 1 //only print necessory information -#if PRINT -#define AD_TEST 0 //need TIMER_MODULE for 2s delay -#define ADC_TEST 0 -#define LCD_TEST 0 //need TIMER_MODULE for 1s delay -#define TEMP_TEST 0 -#define FLOW_TEST 0 -#define MONTHDATA_TEST 0 //use lcd A3 -#define KEY_TEST 0 -#define MBUS_TEST 0 -#define INFRARE_TEST 0 -#define CALENDAR_TEST 0 -#define FRAME_TEST 0 -#define RES_TEST 0 -#define TIMER_TEST 0 -#endif - -#if PRINT -#define DEBUG 1 //print information in detail -#endif - -#if DEBUG -#define BUG 1 -#define debug(fmt,args...) printf(fmt ,##args); -#define debugX(level,fmt,args...) if(DEBUG>=level) printf(fmt,##args); -#else -#define BUG 0 -#define debug(fmt,args...) -#define debugX(level,fmt,args...) -#endif - -#if BUG -#define BUG() printf("BUG: failure at %s:%d in %s()!\n", __FILE__, __LINE__, __FUNCTION__); -#define BUG_ON(condition) if(condition) BUG(); -#endif /* BUG */ - - -/*************************************main_flag***********************************************************************************************************************/ -//unsigned char main_flag0; -#define test_bit 0x80 //͵ѹ -#define temp_bit 0x40 -#define flow_bit 0x20 -#define month_bit 0x10 -#define key_bit 0x8 -#define lcd_bit 0x4 -#define mbus_bit 0x2 -#define infrare_bit 0x1 -//unsigned char main_flag1; -#define state_bit 0x8000 //gp21״̬, '0'Ϊ'1'Ϊ쳣 -#define lowV1_bit 0x4000 //͵ѹ1,ÿ2 -#define lowV2_bit 0x2000 //͵ѹ2,ÿ7142128賿3'1' -#define time_bit 0x1000 //ʱ -#define long_key 0x800 // -#define month_flag 0x400 //½ʱǷΪĬʱ䣬ĬʱΪÿµף'1' -#define A3_delay 0x200 //A3˵3Զл -#define wait_halfsec 0x100 //ȴ0.5 -//unsigned char main_flag2; -#define wait_3sec 0x800000 //3 -#define wait_8sec 0x400000 //8 -#define wait_9sec 0x200000 //9 -#define wait_10sec 0x100000 //10 -#define wait_1min 0x80000 //1 -#define wait_2min 0x40000 //2 -#define wait_16min 0x20000 //16 -#define wait_2hour 0x10000 //2Сʱ -//unsigned char main_flag3; -#define rx_bit 0x80000000 //usartյһ֡ -#define infrare_flag 0x40000000 //״̬'0'ر'1' -#define lowV_flag 0x20000000 //͵ѹ״̬Ϊ'1' -#define wait_oneday 0x10000000 //͵ѹ⣬ȴһ -#define power_on 0x8000000 //ϵ -#define res_valid 0x4000000 //RES_VALID -#define per_timer 0x2000000 - -/********************************************************************************************************************************************************************/ - -/*************************************work_mode***********************************************************************************************************************/ -#define MODE_0 0 -#define MODE_1 1 -#define MODE_2 2 -#define MODE_3 3 -#define MODE_4 4 -#define MODE_5 5 -#define MODE_6 6 -#define MODE_7 7 -#define MODE_8 8 -#define MODE_9 9 - -/********************************************************************************************************************************************************************/ - diff --git a/resources/soc/simu/soft/func/convert.c b/resources/soc/simu/soft/func/convert.c deleted file mode 100644 index 0e66323..0000000 --- a/resources/soc/simu/soft/func/convert.c +++ /dev/null @@ -1,29 +0,0 @@ -#include -#include - -int main(void) -{ - FILE *in; - FILE *out; - FILE *out0, *out1, *out2, *out3; - FILE *out4, *out5, *out6, *out7; - - int i,j,k; - unsigned char mem[32]; - - in = fopen("test.bin", "rb"); - out = fopen("flash.vlog", "w"); - - fprintf(out, " @00\n"); - while(!feof(in)) { - if(fread(mem,1,4,in)!=4) { - fprintf(out, " %02x %02x %02x %02x\n", mem[0], mem[1], mem[2], mem[3]); - break; - } - fprintf(out, " %02x %02x %02x %02x\n", mem[0], mem[1], mem[2],mem[3]); - } - fclose(in); - fclose(out); - - return 0; -} diff --git a/resources/soc/simu/soft/func/include/Calendar.h b/resources/soc/simu/soft/func/include/Calendar.h deleted file mode 100644 index f51c62d..0000000 --- a/resources/soc/simu/soft/func/include/Calendar.h +++ /dev/null @@ -1,12 +0,0 @@ -struct Date_Time{ - _u32 Year; - _u32 Month; - _u32 Day; - _u32 Hour; - _u32 Minute; - _u32 Second; -}; - -void calendar(struct Date_Time *Date_and_Time); -//void calendar(struct Date_Time *Date_and_Time, _u32 lcdmode); -void DateInit(struct Date_Time *Date_and_Time); diff --git a/resources/soc/simu/soft/func/include/Infrare.h b/resources/soc/simu/soft/func/include/Infrare.h deleted file mode 100644 index 775975a..0000000 --- a/resources/soc/simu/soft/func/include/Infrare.h +++ /dev/null @@ -1 +0,0 @@ -void Infrare(void); diff --git a/resources/soc/simu/soft/func/include/Interrupt.h b/resources/soc/simu/soft/func/include/Interrupt.h deleted file mode 100644 index f605aea..0000000 --- a/resources/soc/simu/soft/func/include/Interrupt.h +++ /dev/null @@ -1,9 +0,0 @@ -void TIMER_INT(); -void KEY_INT(); -void BAT_FAIL(); -void RES_VALID(); -void INTC(); -void Ring(); -void Per_timer(struct Data *Lcd_data); - -void Interrupt_Init(); diff --git a/resources/soc/simu/soft/func/include/MonthData.h b/resources/soc/simu/soft/func/include/MonthData.h deleted file mode 100644 index a4ab8f4..0000000 --- a/resources/soc/simu/soft/func/include/MonthData.h +++ /dev/null @@ -1,23 +0,0 @@ -void MonthData(struct Date_Time *Date_and_Time, struct Data *Lcd_data); -void Flash_Read_Info(); -void Flash_Write_Test(); -extern _u32 Last_month_num; - -#define CHRWRITE 0 -#define BLKWRITE 1 -struct Record_0{ - _u32 Date; /*ϢDate = Year*1000 + Month*10, 2011.10,Date = 20110100 */ - _u32 TotalHeat; //xxxxxx.xx, plus 100 - _u32 TotalFlow; //xxxxxx.xx, plus 100 -}; - -struct Record_1{ - _u32 Date; /*ϢDate = Year*10000 + Month*100 + Day, 2011.10.12,Date = 20111012 */ - _u32 Time; /*ʱϢTime = Hour*100 + Minute, 930Time = 930 */ - _fp32 TotalHeat; - _fp32 TotalFlow; - _u32 WorkTime; - _u32 ErrTime; -}; -extern struct Record_1 Latest_Record; - diff --git a/resources/soc/simu/soft/func/include/SystemInit.h b/resources/soc/simu/soft/func/include/SystemInit.h deleted file mode 100644 index 7735907..0000000 --- a/resources/soc/simu/soft/func/include/SystemInit.h +++ /dev/null @@ -1,4 +0,0 @@ -void Uart0_Init(); -void SystemInit(); -void PowerDetec(); -//void ReLoad(); diff --git a/resources/soc/simu/soft/func/include/adc.h b/resources/soc/simu/soft/func/include/adc.h deleted file mode 100644 index 93823ec..0000000 --- a/resources/soc/simu/soft/func/include/adc.h +++ /dev/null @@ -1,2 +0,0 @@ - -float BatteryMeasure(void) diff --git a/resources/soc/simu/soft/func/include/asm/interrupt.h b/resources/soc/simu/soft/func/include/asm/interrupt.h deleted file mode 100644 index 28f034f..0000000 --- a/resources/soc/simu/soft/func/include/asm/interrupt.h +++ /dev/null @@ -1,287 +0,0 @@ -#if 1 /*It's not a good method. Don't use it!*/ -#define SAVE_REGS \ - li k1, SRAM_BASEADDR+0x1000; \ - sw $0, 0x0(k1); \ - sw $1, 0x4(k1); \ - sw $2, 0x8(k1); \ - sw $3, 0xc(k1); \ - sw $4, 0x10(k1); \ - sw $5, 0x14(k1); \ - sw $6, 0x18(k1); \ - sw $7, 0x1c(k1); \ - sw $8, 0x20(k1); \ - sw $9, 0x24(k1); \ - sw $10, 0x28(k1); \ - sw $11, 0x2c(k1); \ - sw $12, 0x30(k1); \ - sw $13, 0x34(k1); \ - sw $14, 0x38(k1); \ - sw $15, 0x3c(k1); \ - sw $16, 0x40(k1); \ - sw $17, 0x44(k1); \ - sw $18, 0x48(k1); \ - sw $19, 0x4c(k1); \ - sw $20, 0x50(k1); \ - sw $21, 0x54(k1); \ - sw $22, 0x58(k1); \ - sw $23, 0x5c(k1); \ - sw $24, 0x60(k1); \ - sw $25, 0x64(k1); \ - sw $26, 0x68(k1); \ - sw $27, 0x6c(k1); \ - sw $28, 0x70(k1); \ - sw $29, 0x74(k1); \ - sw $30, 0x78(k1); - //sw $31, 0x7c(k1) - -#define LOAD_REGS \ - li k1, SRAM_BASEADDR+0x1000; \ - lw $0, 0x0(k1); \ - lw $1, 0x4(k1); \ - lw $2, 0x8(k1); \ - lw $3, 0xc(k1); \ - lw $4, 0x10(k1); \ - lw $5, 0x14(k1); \ - lw $6, 0x18(k1); \ - lw $7, 0x1c(k1); \ - lw $8, 0x20(k1); \ - lw $9, 0x24(k1); \ - lw $10, 0x28(k1); \ - lw $11, 0x2c(k1); \ - lw $12, 0x30(k1); \ - lw $13, 0x34(k1); \ - lw $14, 0x38(k1); \ - lw $15, 0x3c(k1); \ - lw $16, 0x40(k1); \ - lw $17, 0x44(k1); \ - lw $18, 0x48(k1); \ - lw $19, 0x4c(k1); \ - lw $20, 0x50(k1); \ - lw $21, 0x54(k1); \ - lw $22, 0x58(k1); \ - lw $23, 0x5c(k1); \ - lw $24, 0x60(k1); \ - lw $25, 0x64(k1); \ - lw $26, 0x68(k1); \ - lw $27, 0x6c(k1); \ - lw $28, 0x70(k1); \ - lw $29, 0x74(k1); \ - lw $30, 0x78(k1); \ - //lw $26, 0x7c(k1); \ - //sw $26, 0x10($30); - //lw $31, 0x7c(k1) -#endif - -/***********************************method 1*************************************/ -#if 0 -#define SAVE_ALL \ - addi sp, -4; \ - sw $0, 0x0(sp); \ - addi sp, -4; \ - sw $1, 0x0(sp); \ - addi sp, -4; \ - sw $2, 0x0(sp); \ - addi sp, -4; \ - sw $3, 0x0(sp); \ - addi sp, -4; \ - sw $4, 0x0(sp); \ - addi sp, -4; \ - sw $5, 0x0(sp); \ - addi sp, -4; \ - sw $6, 0x0(sp); \ - addi sp, -4; \ - sw $7, 0x0(sp); \ - addi sp, -4; \ - sw $8, 0x0(sp); \ - addi sp, -4; \ - sw $9, 0x0(sp); \ - addi sp, -4; \ - sw $10, 0x0(sp); \ - addi sp, -4; \ - sw $11, 0x0(sp); \ - addi sp, -4; \ - sw $12, 0x0(sp); \ - addi sp, -4; \ - sw $13, 0x0(sp); \ - addi sp, -4; \ - sw $14, 0x0(sp); \ - addi sp, -4; \ - sw $15, 0x0(sp); \ - addi sp, -4; \ - sw $16, 0x0(sp); \ - addi sp, -4; \ - sw $17, 0x0(sp); \ - addi sp, -4; \ - sw $18, 0x0(sp); \ - addi sp, -4; \ - sw $19, 0x0(sp); \ - addi sp, -4; \ - sw $20, 0x0(sp); \ - addi sp, -4; \ - sw $21, 0x0(sp); \ - addi sp, -4; \ - sw $22, 0x0(sp); \ - addi sp, -4; \ - sw $23, 0x0(sp); \ - addi sp, -4; \ - sw $24, 0x0(sp); \ - addi sp, -4; \ - sw $25, 0x0(sp); \ - addi sp, -4; \ - sw $26, 0x0(sp); \ - addi sp, -4; \ - sw $27, 0x0(sp); \ - addi sp, -4; \ - sw $28, 0x0(sp); \ - addi sp, -4; \ - sw $29, 0x0(sp); \ - addi sp, -4; \ - sw $30, 0x0(sp); \ - addi sp, -4; \ - sw $31, 0x0(sp); \ - addi sp, -4 - - -#define LOAD_ALL \ - addi sp, 4; \ - lw $31, 0x0(sp); \ - addi sp, 4; \ - lw $30, 0x0(sp); \ - addi sp, 4; \ - lw $29, 0x0(sp); \ - addi sp, 4; \ - lw $28, 0x0(sp); \ - addi sp, 4; \ - lw $27, 0x0(sp); \ - addi sp, 4; \ - lw $26, 0x0(sp); \ - addi sp, 4; \ - lw $25, 0x0(sp); \ - addi sp, 4; \ - lw $24, 0x0(sp); \ - addi sp, 4; \ - lw $23, 0x0(sp); \ - addi sp, 4; \ - lw $22, 0x0(sp); \ - addi sp, 4; \ - lw $21, 0x0(sp); \ - addi sp, 4; \ - lw $20, 0x0(sp); \ - addi sp, 4; \ - lw $19, 0x0(sp); \ - addi sp, 4; \ - lw $18, 0x0(sp); \ - addi sp, 4; \ - lw $17, 0x0(sp); \ - addi sp, 4; \ - lw $16, 0x0(sp); \ - addi sp, 4; \ - lw $15, 0x0(sp); \ - addi sp, 4; \ - lw $14, 0x0(sp); \ - addi sp, 4; \ - lw $13, 0x0(sp); \ - addi sp, 4; \ - lw $12, 0x0(sp); \ - addi sp, 4; \ - lw $11, 0x0(sp); \ - addi sp, 4; \ - lw $10, 0x0(sp); \ - addi sp, 4; \ - lw $9, 0x0(sp); \ - addi sp, 4; \ - lw $8, 0x0(sp); \ - addi sp, 4; \ - lw $7, 0x0(sp); \ - addi sp, 4; \ - lw $6, 0x0(sp); \ - addi sp, 4; \ - lw $5, 0x0(sp); \ - addi sp, 4; \ - lw $4, 0x0(sp); \ - addi sp, 4; \ - lw $3, 0x0(sp); \ - addi sp, 4; \ - lw $2, 0x0(sp); \ - addi sp, 4; \ - lw $1, 0x0(sp); \ - addi sp, 4; \ - lw $0, 0x0(sp); \ - addi sp, 4 -#endif -/****************************************************************************/ - -/*************************************method 2***********************************/ -#if 1 -#define SAVE_ALL \ - addi sp, -132; \ - sw $0, 0x80(sp); \ - sw $1, 0x7c(sp); \ - sw $2, 0x78(sp); \ - sw $3, 0x74(sp); \ - sw $4, 0x70(sp); \ - sw $5, 0x6c(sp); \ - sw $6, 0x68(sp); \ - sw $7, 0x64(sp); \ - sw $8, 0x60(sp); \ - sw $9, 0x5c(sp); \ - sw $10, 0x58(sp); \ - sw $11, 0x54(sp); \ - sw $12, 0x50(sp); \ - sw $13, 0x4c(sp); \ - sw $14, 0x48(sp); \ - sw $15, 0x44(sp); \ - sw $16, 0x40(sp); \ - sw $17, 0x3c(sp); \ - sw $18, 0x38(sp); \ - sw $19, 0x34(sp); \ - sw $20, 0x30(sp); \ - sw $21, 0x2c(sp); \ - sw $22, 0x28(sp); \ - sw $23, 0x24(sp); \ - sw $24, 0x20(sp); \ - sw $25, 0x1c(sp); \ - sw $26, 0x18(sp); \ - sw $27, 0x14(sp); \ - sw $28, 0x10(sp); \ - sw $29, 0xc(sp); \ - sw $30, 0x8(sp); \ - sw $31, 0x4(sp) - - -#define LOAD_ALL \ - lw $0, 0x80(sp); \ - lw $1, 0x7c(sp); \ - lw $2, 0x78(sp); \ - lw $3, 0x74(sp); \ - lw $4, 0x70(sp); \ - lw $5, 0x6c(sp); \ - lw $6, 0x68(sp); \ - lw $7, 0x64(sp); \ - lw $8, 0x60(sp); \ - lw $9, 0x5c(sp); \ - lw $10, 0x58(sp); \ - lw $11, 0x54(sp); \ - lw $12, 0x50(sp); \ - lw $13, 0x4c(sp); \ - lw $14, 0x48(sp); \ - lw $15, 0x44(sp); \ - lw $16, 0x40(sp); \ - lw $17, 0x3c(sp); \ - lw $18, 0x38(sp); \ - lw $19, 0x34(sp); \ - lw $20, 0x30(sp); \ - lw $21, 0x2c(sp); \ - lw $22, 0x28(sp); \ - lw $23, 0x24(sp); \ - lw $24, 0x20(sp); \ - lw $25, 0x1c(sp); \ - lw $26, 0x18(sp); \ - lw $27, 0x14(sp); \ - lw $28, 0x10(sp); \ - lw $29, 0xc(sp); \ - lw $30, 0x8(sp); \ - lw $31, 0x4(sp); \ - addi sp, 132 -#endif -/****************************************************************************/ diff --git a/resources/soc/simu/soft/func/include/asm/mipsregs.h b/resources/soc/simu/soft/func/include/asm/mipsregs.h deleted file mode 100644 index 6c07b12..0000000 --- a/resources/soc/simu/soft/func/include/asm/mipsregs.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Coprocessor 0 register names - */ -#define CP0_INDEX $0 -#define CP0_RANDOM $1 -#define CP0_ENTRYLO0 $2 -#define CP0_ENTRYLO1 $3 -#define CP0_CONF $3 -#define CP0_CONTEXT $4 -#define CP0_PAGEMASK $5 -#define CP0_WIRED $6 -#define CP0_INFO $7 -#define CP0_BADVADDR $8 -#define CP0_COUNT $9 -#define CP0_ENTRYHI $10 -#define CP0_COMPARE $11 -#define CP0_STATUS $12 -#define CP0_CAUSE $13 -#define CP0_EPC $14 -#define CP0_PRID $15 -#define CP0_CONFIG $16 -#define CP0_LLADDR $17 -#define CP0_WATCHLO $18 -#define CP0_WATCHHI $19 -#define CP0_XCONTEXT $20 -#define CP0_FRAMEMASK $21 -#define CP0_DIAGNOSTIC $22 -#define CP0_DEBUG $23 -#define CP0_DEPC $24 -#define CP0_PERFORMANCE $25 -#define CP0_ECC $26 -#define CP0_CACHEERR $27 -#define CP0_TAGLO $28 -#define CP0_TAGHI $29 -#define CP0_ERROREPC $30 -#define CP0_DESAVE $31 - - diff --git a/resources/soc/simu/soft/func/include/asm/ns16550.h b/resources/soc/simu/soft/func/include/asm/ns16550.h deleted file mode 100644 index ce32524..0000000 --- a/resources/soc/simu/soft/func/include/asm/ns16550.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (c) 2009 yanhua - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2, or (at - * your option) any later version. - */ - -#ifdef CONFIG_CPU_UART -//#define COMMON_COM_BASE_ADDR 0xbff003f8 -#define COMMON_COM_BASE_ADDR 0xbfd00000 -#define NS16550HZ 3686400 -#else -#define COMMON_COM_BASE_ADDR 0xbfd003f8 -#define NS16550HZ 1843200 -#endif - -#define CONS_BAUD B115200 -/* - * NS16550 UART registers - */ - -#define NS16550_CHANA PHYS_TO_K1(UART0_BASE) -#define NS16550_CHANB PHYS_TO_K1(UART1_BASE) - -/* - * Standard speeds, make these available for start.S et al. - */ -#define B0 0 -#define B50 50 -#define B75 75 -#define B110 110 -#define B134 134 -#define B150 150 -#define B200 200 -#define B300 300 -#define B600 600 -#define B1200 1200 -#define B1800 1800 -#define B2400 2400 -#define B4800 4800 -#define B9600 9600 -#define B19200 19200 -#define B38400 38400 -#define B7200 7200 -#define B14400 14400 -#define B28800 28800 -#define B57600 57600 -#define B76800 76800 -#define B115200 115200 -#define B230400 230400 - -#ifndef NSREG -#define NSREG(x) x -#endif - -#define NS16550_DATA 0 -#define NS16550_IER 1 -#define NS16550_IIR 2 -#define NS16550_FIFO 2 -#define NS16550_CFCR 3 -#define NS16550_MCR 4 -#define NS16550_LSR 5 -#define NS16550_MSR 6 -#define NS16550_SCR 7 - - -/* interrupt enable register */ -#define IER_ERXRDY 0x1 /* int on rx ready */ -#define IER_ETXRDY 0x2 /* int on tx ready */ -#define IER_ERLS 0x4 /* int on line status change */ -#define IER_EMSC 0x8 /* int on modem status change */ - -/* interrupt identification register */ -#define IIR_IMASK 0xf /* mask */ -#define IIR_RXTOUT 0xc /* receive timeout */ -#define IIR_RLS 0x6 /* receive line status */ -#define IIR_RXRDY 0x4 /* receive ready */ -#define IIR_TXRDY 0x2 /* transmit ready */ -#define IIR_NOPEND 0x1 /* nothing */ -#define IIR_MLSC 0x0 /* modem status */ -#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ - -/* fifo control register */ -#define FIFO_ENABLE 0x01 /* enable fifo */ -#define FIFO_RCV_RST 0x02 /* reset receive fifo */ -#define FIFO_XMT_RST 0x04 /* reset transmit fifo */ -#define FIFO_DMA_MODE 0x08 /* enable dma mode */ -#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */ -#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */ -#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */ -#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */ - -/* character format control register */ -#define CFCR_DLAB 0x80 /* divisor latch */ -#define CFCR_SBREAK 0x40 /* send break */ -#define CFCR_PZERO 0x30 /* zero parity */ -#define CFCR_PONE 0x20 /* one parity */ -#define CFCR_PEVEN 0x10 /* even parity */ -#define CFCR_PODD 0x00 /* odd parity */ -#define CFCR_PENAB 0x08 /* parity enable */ -#define CFCR_STOPB 0x04 /* 2 stop bits */ -#define CFCR_8BITS 0x03 /* 8 data bits */ -#define CFCR_7BITS 0x02 /* 7 data bits */ -#define CFCR_6BITS 0x01 /* 6 data bits */ -#define CFCR_5BITS 0x00 /* 5 data bits */ - -/* modem control register */ -#define MCR_LOOPBACK 0x10 /* loopback */ -#define MCR_IENABLE 0x08 /* output 2 = int enable */ -#define MCR_DRS 0x04 /* output 1 = xxx */ -#define MCR_RTS 0x02 /* enable RTS */ -#define MCR_DTR 0x01 /* enable DTR */ - -/* line status register */ -#define LSR_RCV_FIFO 0x80 /* error in receive fifo */ -#define LSR_TSRE 0x40 /* transmitter empty */ -#define LSR_TXRDY 0x20 /* transmitter ready */ -#define LSR_BI 0x10 /* break detected */ -#define LSR_FE 0x08 /* framing error */ -#define LSR_PE 0x04 /* parity error */ -#define LSR_OE 0x02 /* overrun error */ -#define LSR_RXRDY 0x01 /* receiver ready */ -#define LSR_RCV_MASK 0x1f - -/* modem status register */ -#define MSR_DCD 0x80 /* DCD active */ -#define MSR_RI 0x40 /* RI active */ -#define MSR_DSR 0x20 /* DSR active */ -#define MSR_CTS 0x10 /* CTS active */ -#define MSR_DDCD 0x08 /* DCD changed */ -#define MSR_TERI 0x04 /* RI changed */ -#define MSR_DDSR 0x02 /* DSR changed */ -#define MSR_DCTS 0x01 /* CTS changed */ diff --git a/resources/soc/simu/soft/func/include/asm/regdef.h b/resources/soc/simu/soft/func/include/asm/regdef.h deleted file mode 100644 index 570511e..0000000 --- a/resources/soc/simu/soft/func/include/asm/regdef.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Symbolic register names for 32 bit ABI - */ -#define zero $0 /* wired zero */ -#define AT $1 /* assembler temp - uppercase because of ".set at" */ -#define v0 $2 /* return value */ -#define v1 $3 -#define a0 $4 /* argument registers */ -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define t0 $8 /* caller saved */ -#define t1 $9 -#define t2 $10 -#define t3 $11 -#define t4 $12 -#define t5 $13 -#define t6 $14 -#define t7 $15 -#define s0 $16 /* callee saved */ -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 /* caller saved */ -#define t9 $25 -#define jp $25 /* PIC jump register */ -#define k0 $26 /* kernel scratch */ -#define k1 $27 -#define gp $28 /* global pointer */ -#define sp $29 /* stack pointer */ -#define fp $30 /* frame pointer */ -#define s8 $30 /* same like fp! */ -#define ra $31 /* return address */ - - diff --git a/resources/soc/simu/soft/func/include/battery.h b/resources/soc/simu/soft/func/include/battery.h deleted file mode 100644 index 4e54880..0000000 --- a/resources/soc/simu/soft/func/include/battery.h +++ /dev/null @@ -1,4 +0,0 @@ - -void ADC_Init(void); -void BatteryTest1(); -void BatteryTest2(); diff --git a/resources/soc/simu/soft/func/include/cmdline.h b/resources/soc/simu/soft/func/include/cmdline.h deleted file mode 100644 index b8bfb0f..0000000 --- a/resources/soc/simu/soft/func/include/cmdline.h +++ /dev/null @@ -1,9 +0,0 @@ - -int help(int argc, char argv[][30]); -int m4(int argc, char argv[][30]); -int m1(int argc, char argv[][30]); -int d4(int argc, char argv[][30]); -int d1(int argc, char argv[][30]); -unsigned int str2num(char str[30]); - -int cmdline(void); diff --git a/resources/soc/simu/soft/func/include/common.h b/resources/soc/simu/soft/func/include/common.h deleted file mode 100644 index cb305d7..0000000 --- a/resources/soc/simu/soft/func/include/common.h +++ /dev/null @@ -1,5 +0,0 @@ - -_fp32 bubble_sort(_fp32 *delta, _s32 len); -void UintToBcd(_u32 dat, _u8 *bcd_buf); -void BcdToUint(_u8 *bcd_buf, _u32 dat); -_s32 printf_float(_fp32 data); diff --git a/resources/soc/simu/soft/func/include/dg_rs232.h b/resources/soc/simu/soft/func/include/dg_rs232.h deleted file mode 100644 index 3794f9e..0000000 --- a/resources/soc/simu/soft/func/include/dg_rs232.h +++ /dev/null @@ -1 +0,0 @@ -int dg_ctrl(int argc, char argv[][30]); diff --git a/resources/soc/simu/soft/func/include/flash.h b/resources/soc/simu/soft/func/include/flash.h deleted file mode 100644 index 0b0efb5..0000000 --- a/resources/soc/simu/soft/func/include/flash.h +++ /dev/null @@ -1,6 +0,0 @@ -// CONFIDENTIAL - -int verif(int argc, char argv[][30]); -int set_pe_time_mode(int argc, char argv[][30]); -int flash_tk(int argc, char argv[][30]); -int flash_accg(int argc, char argv[][30]); diff --git a/resources/soc/simu/soft/func/include/frame.h b/resources/soc/simu/soft/func/include/frame.h deleted file mode 100644 index 022a4e4..0000000 --- a/resources/soc/simu/soft/func/include/frame.h +++ /dev/null @@ -1,43 +0,0 @@ - -#define ERROR 1 -#define DATA_LENGTH 100 - -extern _u32 RX_IndexW; -void IrSend(_u8 *str); -void uart_tx(); -void uart_rx(); -void Frame_exe(struct Date_Time *Date_and_Time, struct Data *Lcd_data); - -union uint_uchar{ - _u32 i_value; - _u8 c_value[4]; -}; - -/*-----------------Эֶ-----------------*/ -struct FrameFormat{ - _u8 HeadCode; - _u8 TypeCode; - _u8 Address[7]; - _u8 CtrlCode; - _u8 DataLen; - _u8 DI0,DI1,SER; - _u8 Data[DATA_LENGTH]; - _u8 CheckSum; - _u8 TailCode; -}; - -/****************д*****************/ -struct ModifyData{ - _u8 seg; //κ - _u32 flowpoint; //㣬ʹʱҪ10xxxxx.x - _u8 danwei; //λ - _u32 flowdata; //׼ݣʹʱҪ1000xxx.xxx - _u32 rcode; //ȵ - _u32 temp; //궨¶ֵ - _u32 rdata; //ȵֵʹʱҪ100xxxx.xx - _u32 tempmodify; //¶ϵʹʱҪ100000x.xxxxx -}; - - - - diff --git a/resources/soc/simu/soft/func/include/isp.h b/resources/soc/simu/soft/func/include/isp.h deleted file mode 100644 index 8d3d26a..0000000 --- a/resources/soc/simu/soft/func/include/isp.h +++ /dev/null @@ -1,10 +0,0 @@ -void tgt_putchar(_u8 chr); -_u8 tgt_getchar(); -_u8 tgt_testchar(); -_u32 now(); - -void Flash_Erase(_u32 addr); -_u32 Flash_Write(_u32 addr, _u32 *data, _u32 num); -void spiflash_erase(_u32 addr_start, _u32 addr_end); -void spiflash_write(_u32 addr_w, _u32 addr_r, _u32 length); - diff --git a/resources/soc/simu/soft/func/include/key.h b/resources/soc/simu/soft/func/include/key.h deleted file mode 100644 index 19a20bd..0000000 --- a/resources/soc/simu/soft/func/include/key.h +++ /dev/null @@ -1 +0,0 @@ -void Key(struct Data *Lcd_data); diff --git a/resources/soc/simu/soft/func/include/lcd.h b/resources/soc/simu/soft/func/include/lcd.h deleted file mode 100644 index 515b77a..0000000 --- a/resources/soc/simu/soft/func/include/lcd.h +++ /dev/null @@ -1,132 +0,0 @@ -/************************************************************************** -*************************************************************************** - Notice: Some variable of Lcd_data = real_value * LCD_MULTIPLE -*************************************************************************** -**************************************************************************/ -struct Data{ - _fp32 total_heat; //ۼ, plus LCD_MULTIPLE - _fp32 heat; //ȹ, plus LCD_MULTIPLE - _fp32 temp1; //ˮ¶, plus LCD_MULTIPLE - _fp32 temp2; //ˮ¶, plus LCD_MULTIPLE - _fp32 temp0; //², plus LCD_MULTIPLE - _fp32 total_flow; //ۼ, plus LCD_MULTIPLE - _fp32 flow; //˲ʱ, plus LCD_MULTIPLE - _u32 total_time; //ʱ - _u32 alarm_time; //ʱ - _u32 date; // - _u32 time; //ʱ - _u32 usercode; - _fp32 version; - _u32 history; - _u32 lcdmode; //A1_1; - _u32 auto_caculate; -}; -void LcdDisplay(struct Date_Time *Date_and_Time, struct Data *Lcd_data); - -//---------------A1˵------------- -#define A1 1 -#define A1_0 10 //ʾA1 - -#define A1_1 11 -#define A1_1_0 (0x08+0x04) //'ۻ ' -#define A1_1_1 (0x10+0x20) //'KW*h' - -#define A1_2 12 //һλС -#define A1_2_0 (0x10) //' ' -#define A1_2_1 (0x00) // - -#define A1_3 13 //'T T' һλС -#define A1_3_0 (0x20) //'T' -#define A1_3_1 (0x04) //'`C' - -#define A1_4 14 //λС -#define A1_4_0 (0x02) //'² ' -#define A1_4_1 (0x04) //'`C' - -#define A1_5 15 //λС -#define A1_5_0 (0x08+0x01) //'ۻ' -#define A1_5_1 (0x02) //'m3' - -#define A1_6 16 //λС -#define A1_6_0 (0x01) //'˲ʱ ' -#define A1_6_1 (0x02+0x01+0x80) //'m3/h' - -#define A1_7 17 -#define A1_7_0 (0x08+0x80) //'ۻʱ' -#define A1_7_1 (0x80) //'h' - -#define A1_8 18 -#define A1_8_0 (0x40) //'ʱ' -#define A1_8_1 (0x80) //'h' - -//--------------A2˵------------- -#define A2 2 -#define A2_0 20 //ʾA2 - -#define A2_1 21 // -#define A2_1_0 (0x80) //'ʱ' -#define A2_1_1 (0x00) - -#define A2_2 22 //ʱ -#define A2_2_0 (0x80) //'ʱ' -#define A2_2_1 (0x00) - -#define A2_3 23 //û -#define A2_3_0 (0x00) // -#define A2_3_1 (0x00) - -#define A2_4 24 //汾 -#define A2_4_0 (0x00) // -#define A2_4_1 (0x00) - -#define A2_5 25 //͵ѹ'P6' -#define A2_5_0 (0x00) // -#define A2_5_1 (0x00) - -#define A2_6 26 //ȫ - -//--------------A3˵-------------- -#define A3 3 -#define A3_0 30 //ʾA3 - -#define A3_1 31 // -#define A3_1_0 (0x80) //'ʱ' -#define A3_1_1 (0x00) - -#define A3_2 32 -#define A3_2_0 (0x08+0x01) //'ۻ' -#define A3_2_1 (0x02) //'m3' - -#define A3_3 33 -#define A3_3_0 (0x08+0x04) //'ۼ ' -#define A3_3_1 (0x10+0x20) //'KW*h' - -//--------------A4˵-------------- -#define A4 4 -#define A4_0 40 //ʾA4 - -#define A4_1 41 //λС -#define A4_1_0 (0x01) //'˲ʱ ' -#define A4_1_1 (0x02+0x01+0x80+0x08) //'m3/h'+'춨' - -#define A4_2 42 //λС -#define A4_2_0 (0x08+0x01) //'ۻ' -#define A4_2_1 (0x02+0x08) //'m3'+'춨' - -#define A4_3 43 -#define A4_3_0 (0x10) //' ' -#define A4_3_1 (0x00+0x08) // +'춨' - -#define A4_4 44 //λС -#define A4_4_0 (0x08+0x04) //'ۻ ' -#define A4_4_1 (0x10+0x20+0x08) //'KW*h'+'춨' - -#define A4_5 45 //'T T' λС -#define A4_5_0 (0x20) //'T' -#define A4_5_1 (0x04+0x08) //'`C'+'춨' - -#define A4_6 46 -#define A4_6_0 (0x02) //'² ' -#define A4_6_1 (0x04+0x08) //'`C'+'춨' - - diff --git a/resources/soc/simu/soft/func/include/ls1d.h b/resources/soc/simu/soft/func/include/ls1d.h deleted file mode 100644 index 33b317a..0000000 --- a/resources/soc/simu/soft/func/include/ls1d.h +++ /dev/null @@ -1,158 +0,0 @@ - -/********************************Variable Option**********************************************************************************************************************/ -typedef char _s8; -typedef unsigned char _u8; - -typedef short _s16; -typedef unsigned short _u16; - -typedef int _s32; -typedef unsigned int _u32; - -typedef float _fp32; - -/********************************LS1D Chip Option**********************************************************************************************************************/ -/********************************LS1D Address Space********************************/ -#define UNCACHED_MEMORY_ADDR 0xa0000000 -#define UNCACHED_TO_PHYS(x) ((x) & 0x1fffffff) -#define PHYS_TO_UNCACHED(x) ((x) | UNCACHED_MEMORY_ADDR) - -#define SRAM_BASEADDR PHYS_TO_UNCACHED(0x0) //sram -#define SPI_FLASH_BASEADDR PHYS_TO_UNCACHED(0x1e000000) //spi flash -#define FLASH_BASEADDR PHYS_TO_UNCACHED(0x1f000000) //spi/nand/lpc -#define BOOT_ADDR PHYS_TO_UNCACHED(0x1fc00000) //spi/flash -#define FLASH_REG_BASEADDR PHYS_TO_UNCACHED(0x1fe60000) //flash regs -#define SPI_REG_BASEADDR PHYS_TO_UNCACHED(0x1fe80000) //spi regs -#define UART0_BASEADDR PHYS_TO_UNCACHED(0x1fe40000) // LS 20130123 -#define UART1_BASEADDR PHYS_TO_UNCACHED(0x1fe88000) -#define I2C_BASEADDR PHYS_TO_UNCACHED(0x1fe90000) -#define REGS_BASEADDR PHYS_TO_UNCACHED(0x1fea0000) //Interrupt_Regs_Baseaddr - -#define PMU_BASEADDR PHYS_TO_UNCACHED(0x1feb0000) -#define SONAR_BASEADDR PHYS_TO_UNCACHED(0x1feb4000) -#define THSENS_BASEADDR PHYS_TO_UNCACHED(0x1feb8000) - -#define SLCD_REG_BASEADDR PHYS_TO_UNCACHED(0x1febc000) -#define ADC_BASEADDR PHYS_TO_UNCACHED(0x1fea8000) - -/********************************PMU REGS********************************/ -#define PMU_Timing *(volatile _u32 *)(PMU_BASEADDR) -#define PMU_Command *(volatile _u32 *)(PMU_BASEADDR+0x04) -#define PMU_Compare *(volatile _u32 *)(PMU_BASEADDR+0x08) - -#define PMU_ChipCtrl *(volatile _u32 *)(PMU_BASEADDR+0x0C) -#define PMU_GPIO_OE *(volatile _u32 *)(PMU_BASEADDR+0x10) -#define PMU_GPIO_O *(volatile _u32 *)(PMU_BASEADDR+0x14) -#define PMU_GPIO_I *(volatile _u32 *)(PMU_BASEADDR+0x18) - -#define PMU_Count *(volatile _u32 *)(PMU_BASEADDR+0x1c) - -#define PMU_UserDat0 *(volatile _u32 *)(PMU_BASEADDR+0x20) -#define PMU_UserDat1 *(volatile _u32 *)(PMU_BASEADDR+0x24) -#define PMU_UserDat2 *(volatile _u32 *)(PMU_BASEADDR+0x28) -#define PMU_UserDat3 *(volatile _u32 *)(PMU_BASEADDR+0x2c) -#define PMU_UserDat4 *(volatile _u32 *)(PMU_BASEADDR+0x30) - -#define PMU_AutoSave *(volatile _u32 *)(PMU_BASEADDR+0x34) -#define PMU_Exint *(volatile _u32 *)(PMU_BASEADDR+0x38) //external interrupt -#define PMU_CommandW *(volatile _u32 *)(PMU_BASEADDR+0x3c) - -/******************************SONAR REGS********************************/ -#define SONAR_PulseDef *(volatile _u32 *)(SONAR_BASEADDR) -#define SONAR_SonarCtrl0 *(volatile _u32 *)(SONAR_BASEADDR+0x04) -#define SONAR_SonarCtrl1 *(volatile _u32 *)(SONAR_BASEADDR+0x08) -#define SONAR_GateDef1 *(volatile _u32 *)(SONAR_BASEADDR+0x0C) -#define SONAR_GateDef2 *(volatile _u32 *)(SONAR_BASEADDR+0x10) -#define SONAR_GateDef3 *(volatile _u32 *)(SONAR_BASEADDR+0x14) -#define SONAR_WaveW_Cur *(volatile _u32 *)(SONAR_BASEADDR+0x18) -#define SONAR_WaveW_Last *(volatile _u32 *)(SONAR_BASEADDR+0x1C) -#define SONAR_ResPtr *(volatile _u32 *)(SONAR_BASEADDR+0x20) - -#define SONAR_Result *(volatile _u32 *)(SONAR_BASEADDR+0x40) -//Result[15:0] SONAR_BASEADDR + [0x40 ~ 0x7c] - -/*****************************THSENS REGS********************************/ -#define ThsensCtrl *(volatile _u32 *)(THSENS_BASEADDR) - - -/*******************************LCD REGS*********************************/ -#define LCD_FB_0 *(volatile _u32 *)(SLCD_REG_BASEADDR) -#define LCD_FB_1 *(volatile _u32 *)(SLCD_REG_BASEADDR+0x04) -#define LCD_FB_2 *(volatile _u32 *)(SLCD_REG_BASEADDR+0x08) -#define LCD_RefeshRate *(volatile _u32 *)(SLCD_REG_BASEADDR+0x0C) - -/***************************INTERRUPT REGS******************************/ -#define INT_EN *(volatile _u8 *)(REGS_BASEADDR) -#define INT_EGDE *(volatile _u8 *)(REGS_BASEADDR+0x01) -#define INT_POL *(volatile _u8 *)(REGS_BASEADDR+0x02) -#define INT_CLR *(volatile _u8 *)(REGS_BASEADDR+0x03) -#define INT_SET *(volatile _u8 *)(REGS_BASEADDR+0x04) -#define INT_OUT *(volatile _u8 *)(REGS_BASEADDR+0x05) - -/*******************************ADC REGS********************************/ - -#define ADC_CR *(volatile _u8 *)(ADC_BASEADDR) -#define ADC_D0 *(volatile _u8 *)(ADC_BASEADDR+0x1) -#define ADC_D1 *(volatile _u8 *)(ADC_BASEADDR+0x2) - -/*******************************I2C REGS********************************/ -#define IIC_PRER_L *(volatile _u8 *)(I2C_BASEADDR+0x00) -#define IIC_PRER_H *(volatile _u8 *)(I2C_BASEADDR+0x01) -#define IIC_CTR *(volatile _u8 *)(I2C_BASEADDR+0x02) -#define IIC_TXR *(volatile _u8 *)(I2C_BASEADDR+0x03) //w -#define IIC_RXR *(volatile _u8 *)(I2C_BASEADDR+0x03) //r -#define IIC_CR *(volatile _u8 *)(I2C_BASEADDR+0x04) //w -#define IIC_SR *(volatile _u8 *)(I2C_BASEADDR+0x04) //r -#define IIC_ADDR *(volatile _u8 *)(I2C_BASEADDR+0x07) // 7位地址 MSB 无效 - -/*****************************UART0 REGS********************************/ -//NS16550 -#define Uart0_RxData *(volatile _u8 *)(UART0_BASEADDR) -#define Uart0_TxData *(volatile _u8 *)(UART0_BASEADDR) -#define Uart0_IER *(volatile _u8 *)(UART0_BASEADDR+0x01) -#define Uart0_IIR *(volatile _u8 *)(UART0_BASEADDR+0x02) //read only -#define Uart0_FCR *(volatile _u8 *)(UART0_BASEADDR+0x02) //write only -#define Uart0_LCR *(volatile _u8 *)(UART0_BASEADDR+0x03) -#define Uart0_MCR *(volatile _u8 *)(UART0_BASEADDR+0x04) -#define Uart0_LSR *(volatile _u8 *)(UART0_BASEADDR+0x05) -#define Uart0_MSR *(volatile _u8 *)(UART0_BASEADDR+0x06) - -#define Uart0_BaudL *(volatile _u8 *)(UART0_BASEADDR) -#define Uart0_BaudH *(volatile _u8 *)(UART0_BASEADDR+0x01) - -/*****************************UART1 REGS********************************/ -//NS16550 -#define Uart1_RxData *(volatile _u8 *)(UART1_BASEADDR) -#define Uart1_TxData *(volatile _u8 *)(UART1_BASEADDR) -#define Uart1_IER *(volatile _u8 *)(UART1_BASEADDR+0x01) -#define Uart1_IIR *(volatile _u8 *)(UART1_BASEADDR+0x02) //read only -#define Uart1_FCR *(volatile _u8 *)(UART1_BASEADDR+0x02) //write only -#define Uart1_LCR *(volatile _u8 *)(UART1_BASEADDR+0x03) -#define Uart1_MCR *(volatile _u8 *)(UART1_BASEADDR+0x04) -#define Uart1_LSR *(volatile _u8 *)(UART1_BASEADDR+0x05) -#define Uart1_MSR *(volatile _u8 *)(UART1_BASEADDR+0x06) - -#define Uart1_BaudL *(volatile _u8 *)(UART1_BASEADDR) -#define Uart1_BaudH *(volatile _u8 *)(UART1_BASEADDR+0x01) - -/*******************************SPI REGS********************************/ -#define SPI_SPCR *(volatile _u8 *)(SPI_REG_BASEADDR) -#define SPI_SPSR *(volatile _u8 *)(SPI_REG_BASEADDR+0x01) -#define SPI_TxFIFO *(volatile _u8 *)(SPI_REG_BASEADDR+0x02) -#define SPI_RxFIFO *(volatile _u8 *)(SPI_REG_BASEADDR+0x02) -#define SPI_SPER *(volatile _u8 *)(SPI_REG_BASEADDR+0x03) -#define SPI_SFC_PARAM *(volatile _u8 *)(SPI_REG_BASEADDR+0x04) -#define SPI_SFC_SOFTCS *(volatile _u8 *)(SPI_REG_BASEADDR+0x05) -#define SPI_SFC_TIMING *(volatile _u8 *)(SPI_REG_BASEADDR+0x06) - -/*****************************FLASH REGS********************************/ -#define FLASH_CMD_REG *(volatile _u32 *)(FLASH_REG_BASEADDR) -#define FLASH_ERASE_ALL 0x80000000 -#define FLASH_ERASE_CMD 0xa0000000 -#define FLASH_WRITE_CMD 0xe0000000 -#define FLASH_PAGE_LATCH_CLEAR 0X40000000 -#define FLASH_ADDR_MASK 0x7ffff80 - -#define FLASH_PAGE_LATCH_BASEADDR 0xbfe68000 //128bytes - -/**********************************************************************************************************************************************************************/ diff --git a/resources/soc/simu/soft/func/include/temp_flow.h b/resources/soc/simu/soft/func/include/temp_flow.h deleted file mode 100644 index 1eba1a8..0000000 --- a/resources/soc/simu/soft/func/include/temp_flow.h +++ /dev/null @@ -1,11 +0,0 @@ - -void InitTdc(void); -//_fp32 Time_Caculate(_u32 *result, struct Data *Lcd_data, _u16 start, _u32 stop_num); -//void Flow_Caculate(_fp32 delta_time, _fp32 duration, struct Data *Lcd_data); -//void Temp_Caculate(_u32 *result, struct Data *Lcd_data, _u32 num); -//void Heat_Caculate(_fp32 duration, struct Data *Lcd_data); -_u32 res_ready(struct Data *Lcd_data); - - -extern _fp32 Last_total_flow; //ϴμʱۻ - diff --git a/resources/soc/simu/soft/func/include/xmodem.h b/resources/soc/simu/soft/func/include/xmodem.h deleted file mode 100644 index 83061fa..0000000 --- a/resources/soc/simu/soft/func/include/xmodem.h +++ /dev/null @@ -1,16 +0,0 @@ -_u32 xmodem(void); - -//³£Êý¶¨Òå -#define BLOCKSIZE 128 //M16µÄÒ»¸öFlashҳΪ128×Ö½Ú(64×Ö) - - -//¶¨ÒåÈ«¾Ö±äÁ¿ -struct str_XMODEM -{ - unsigned char SOH; //Æðʼ×Ö½Ú - unsigned char BlockNo; //Êý¾Ý¿é±àºÅ - unsigned char nBlockNo; //Êý¾Ý¿é±àºÅ·´Âë - unsigned char Xdata[BLOCKSIZE]; //Êý¾Ý128×Ö½Ú - unsigned char CRC16hi; //CRC16УÑéÊý¾Ý¸ßλ - unsigned char CRC16lo; //CRC16УÑéÊý¾ÝµÍλ -}; diff --git a/resources/soc/simu/soft/func/lib/Makefile b/resources/soc/simu/soft/func/lib/Makefile deleted file mode 100644 index 9b741e6..0000000 --- a/resources/soc/simu/soft/func/lib/Makefile +++ /dev/null @@ -1,12 +0,0 @@ - -%.o:%.c - $(CC) $(DEBUG) $(FLAGS) -EL -c -o $@ $< - -objs= memset.o memcpy.o printf.o udelay.o putchar.o puts.o printhex.o printbase.o memcmp.o strcat.o strchr.o strcmp.o strtok.o strspn.o strcspn.o - -$(TOPDIR)/libtinyc.a: $(objs) - $(AR) -cr $@ $? - -clean: - rm -f *.o *.a *.s - diff --git a/resources/soc/simu/soft/func/lib/memcmp.c b/resources/soc/simu/soft/func/lib/memcmp.c deleted file mode 100644 index 5f3cbdd..0000000 --- a/resources/soc/simu/soft/func/lib/memcmp.c +++ /dev/null @@ -1,16 +0,0 @@ -/** - * memcmp - Compare two areas of memory - * @cs: One area of memory - * @ct: Another area of memory - * @count: The size of the area. - */ -int memcmp(const void * cs,const void * ct,int count) -{ - const unsigned char *su1, *su2; - signed char res = 0; - - for( su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--) - if ((res = *su1 - *su2) != 0) - break; - return res; -} diff --git a/resources/soc/simu/soft/func/lib/memcpy.c b/resources/soc/simu/soft/func/lib/memcpy.c deleted file mode 100644 index e4a56c2..0000000 --- a/resources/soc/simu/soft/func/lib/memcpy.c +++ /dev/null @@ -1,16 +0,0 @@ -typedef int size_t; -void *memcpy(void *s1, const void *s2, size_t n) -{ - const char *f = s2; - char *t = s1; - - if (f < t) { - f += n; - t += n; - while (n-- > 0) - *--t = *--f; - } else - while (n-- > 0) - *t++ = *f++; - return s1; -} diff --git a/resources/soc/simu/soft/func/lib/memset.c b/resources/soc/simu/soft/func/lib/memset.c deleted file mode 100644 index 5d4bae4..0000000 --- a/resources/soc/simu/soft/func/lib/memset.c +++ /dev/null @@ -1,10 +0,0 @@ -typedef int size_t; -void * memset(void * s,int c, size_t count) -{ - char *xs = (char *) s; - - while (count--) - *xs++ = c; - - return s; -} diff --git a/resources/soc/simu/soft/func/lib/printbase.c b/resources/soc/simu/soft/func/lib/printbase.c deleted file mode 100644 index 2d39a72..0000000 --- a/resources/soc/simu/soft/func/lib/printbase.c +++ /dev/null @@ -1,28 +0,0 @@ -int printbase(long v,int w,int base,int sign) -{ - int i,j; - int c; - char buf[64]; - unsigned long value; - if(sign && v<0) - { - value = -v; - putchar('-'); - } - else value=v; - - for(i=0;value;i++) - { - buf[i]=value%base; - value=value/base; - } - -#define max(a,b) (((a)>(b))?(a):(b)) - - for(j=max(w,i);j>0;j--) - { - c=j>i?0:buf[j-1]; - putchar((c<=9)?c+'0':c-0xa+'a'); - } - return 0; -} diff --git a/resources/soc/simu/soft/func/lib/printf.c b/resources/soc/simu/soft/func/lib/printf.c deleted file mode 100644 index c49827e..0000000 --- a/resources/soc/simu/soft/func/lib/printf.c +++ /dev/null @@ -1,79 +0,0 @@ -int printf(char *fmt,...) -{ -int i; -char c; -void **arg; -void *ap; -int w; -__builtin_va_start(ap,fmt); -arg=ap; -for(i=0;fmt[i];i++) -{ - c=fmt[i]; - if(c=='%') - { - w=1; -again: - switch(fmt[i+1]) - { - case 's': - puts(*arg); - arg++; - i++; - break; - case 'c': - putchar((long)*arg); - arg++; - i++; - break; - case 'u': - printbase((long)*arg,w,10,0); - arg++; - i++; - break; - case 'd': - printbase((long)*arg,w,10,0); - arg++; - i++; - break; - case 'o': - printbase((long)*arg,w,8,0); - arg++; - i++; - break; - case 'b': - printbase((long)*arg,w,2,0); - arg++; - i++; - break; - case 'p': - case 'x': - printbase((long)*arg,w,16,0); - arg++; - i++; - break; - case '%': - putchar('%'); - i++; - break; - case '0': - i++; - case '1' ... '9': - for(w=0;fmt[i+1]>'0' && fmt[i+1]<='9';i++) - w=w*10+(fmt[i+1]-'0'); - goto again; - break; - - default: - putchar('%'); - break; - } - - } - else{ - if(c=='\n') putchar('\r'); - putchar(c); - } -} - return 0; -} diff --git a/resources/soc/simu/soft/func/lib/printhex.c b/resources/soc/simu/soft/func/lib/printhex.c deleted file mode 100644 index 1cb12bb..0000000 --- a/resources/soc/simu/soft/func/lib/printhex.c +++ /dev/null @@ -1,11 +0,0 @@ -int printhex(long v,int w) -{ - int i; - int c; - for(i=4*(w-1);i>=0;i-=4) - { - c=(v>>i)&0xf; - putchar((c<=9)?c+'0':c-0xa+'a'); - } - return 0; -} diff --git a/resources/soc/simu/soft/func/lib/putchar.c b/resources/soc/simu/soft/func/lib/putchar.c deleted file mode 100644 index dc435d4..0000000 --- a/resources/soc/simu/soft/func/lib/putchar.c +++ /dev/null @@ -1,5 +0,0 @@ -int putchar(unsigned char c) -{ -tgt_putchar(c); -return 0; -} diff --git a/resources/soc/simu/soft/func/lib/puts.c b/resources/soc/simu/soft/func/lib/puts.c deleted file mode 100644 index e7d19dd..0000000 --- a/resources/soc/simu/soft/func/lib/puts.c +++ /dev/null @@ -1,13 +0,0 @@ -int puts(char *s) -{ -char c; -while((c=*s)) -{ - if(c == '\n') putchar('\r'); - putchar(c); - s++; -} -putchar('\r'); -putchar('\n'); -return 0; -} diff --git a/resources/soc/simu/soft/func/lib/strcat.c b/resources/soc/simu/soft/func/lib/strcat.c deleted file mode 100644 index 5825675..0000000 --- a/resources/soc/simu/soft/func/lib/strcat.c +++ /dev/null @@ -1,48 +0,0 @@ -/* $Id: strcat.c,v 1.1.1.1 2006/09/14 01:59:06 root Exp $ */ - -/* - * Copyright (c) 2000-2002 Opsycon AB (www.opsycon.se) - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Opsycon AB. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -char * -strcat(char *dst, const char *src) -{ - char *d; - - if (!dst || !src) - return (dst); - - d = dst; - for (; *d; d++); - for (; *src; src++) - *d++ = *src; - *d = 0; - return (dst); -} diff --git a/resources/soc/simu/soft/func/lib/strchr.c b/resources/soc/simu/soft/func/lib/strchr.c deleted file mode 100644 index 30c86b8..0000000 --- a/resources/soc/simu/soft/func/lib/strchr.c +++ /dev/null @@ -1,44 +0,0 @@ -/* $Id: strchr.c,v 1.1.1.1 2006/09/14 01:59:06 root Exp $ */ - -/* - * Copyright (c) 2000-2002 Opsycon AB (www.opsycon.se) - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Opsycon AB. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -char * -strchr(const char *p, int c) -{ - if (!p) - return (0); - - for (; *p; p++) - if (*p == c) - return ((char *)p); - return (0); -} diff --git a/resources/soc/simu/soft/func/lib/strcmp.c b/resources/soc/simu/soft/func/lib/strcmp.c deleted file mode 100644 index 406b0d0..0000000 --- a/resources/soc/simu/soft/func/lib/strcmp.c +++ /dev/null @@ -1,11 +0,0 @@ -/* - * Compare strings. - */ -int -strcmp(const char *s1, const char *s2) -{ - while (*s1 == *s2++) - if (*s1++ == 0) - return (0); - return (*(const unsigned char *)s1 - *(const unsigned char *)--s2); -} diff --git a/resources/soc/simu/soft/func/lib/strcspn.c b/resources/soc/simu/soft/func/lib/strcspn.c deleted file mode 100644 index f9f8a69..0000000 --- a/resources/soc/simu/soft/func/lib/strcspn.c +++ /dev/null @@ -1,48 +0,0 @@ -/* $Id: strcspn.c,v 1.1.1.1 2006/09/14 01:59:06 root Exp $ */ - -/* - * Copyright (c) 2000-2002 Opsycon AB (www.opsycon.se) - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Opsycon AB. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -int -strcspn (const char *p, const char *s) -{ - int i, j; - - for (i = 0; p[i]; i++) { - for (j = 0; s[j]; j++) { - if (s[j] == p[i]) - break; - } - if (s[j]) - break; - } - return (i); -} diff --git a/resources/soc/simu/soft/func/lib/strspn.c b/resources/soc/simu/soft/func/lib/strspn.c deleted file mode 100644 index 240b1ed..0000000 --- a/resources/soc/simu/soft/func/lib/strspn.c +++ /dev/null @@ -1,51 +0,0 @@ -/* $Id: strspn.c,v 1.1.1.1 2006/09/14 01:59:06 root Exp $ */ - -/* - * Copyright (c) 2000-2002 Opsycon AB (www.opsycon.se) - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Opsycon AB. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -/* return length of initial segment of p that consists entirely of - * characters from s */ - -int -strspn(const char *p, const char *s) -{ - int i, j; - - for (i = 0; p[i]; i++) { - for (j = 0; s[j]; j++) { - if (s[j] == p[i]) - break; - } - if (!s[j]) - break; - } - return (i); -} diff --git a/resources/soc/simu/soft/func/lib/strtok.c b/resources/soc/simu/soft/func/lib/strtok.c deleted file mode 100644 index a8ca3b5..0000000 --- a/resources/soc/simu/soft/func/lib/strtok.c +++ /dev/null @@ -1,51 +0,0 @@ -/* $Id: strtok.c,v 1.1.1.1 2006/09/14 01:59:06 root Exp $ */ - -/* - * Copyright (c) 2000-2002 Opsycon AB (www.opsycon.se) - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Opsycon AB. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -char * -strtok(char *p, const char *tok) -{ -static char *t; /* XXX */ - char *r; - int n; - - if (p) - t = p; - - r = t + strspn (t, tok); - if (!(n = strcspn (r, tok))) - return (0); - t = r + n; - if (*t) - *t++ = 0; - return (r); -} diff --git a/resources/soc/simu/soft/func/lib/udelay.c b/resources/soc/simu/soft/func/lib/udelay.c deleted file mode 100644 index 243f40a..0000000 --- a/resources/soc/simu/soft/func/lib/udelay.c +++ /dev/null @@ -1,13 +0,0 @@ -void udelay(int us) -{ -#if 0 -int count0,count1; -int debug=0; -us *=CPU_COUNT_PER_US; -asm volatile("mfc0 %0,$9":"=r"(count0)); -do{ -asm volatile("mfc0 %0,$9":"=r"(count1)); -}while(count1 -count0Day){ - case 7: - case 14: - case 21: - case 28: - if(Date_and_Time->Hour == 3) - { - main_flag |= test_bit; - main_flag |= lowV2_bit; - } - break; - default: - break; - } -} - -static void AddDay(struct Date_Time *Date_and_Time) -{ - Date_and_Time->Day +=1; - Date_and_Time->Hour =0; -} - -static void AddMonth(struct Date_Time *Date_and_Time) -{ - Date_and_Time->Month +=1; - Date_and_Time->Day =1; //ע,ÿµһ'1''0' - Date_and_Time->Hour =0; - if(main_flag & month_flag) main_flag |= month_bit; //Ĭ½ʱΪÿµ -} - -static void AddYear(struct Date_Time *Date_and_Time) -{ - Date_and_Time->Year +=1; - Date_and_Time->Month =1; //ע - Date_and_Time->Day =1; //ע - Date_and_Time->Hour =0; - if(main_flag & month_flag) main_flag |= month_bit; //Ĭ½ʱΪÿµ -} - -//void calendar(struct Date_Time *Date_and_Time, unsigned short lcdmode) -void calendar(struct Date_Time *Date_and_Time) -{ -#if CALENDAR_TEST - printf("calendar()...\n"); -#endif - //if(lcdmode == A2_1 || lcdmode == A2_2) //once per second - if(1) - { - Date_and_Time->Second +=1; - if(Date_and_Time->Second == 60){ - Date_and_Time->Minute += 1; - Date_and_Time->Second = 0; - } - if(Date_and_Time->Minute == 60){ - Date_and_Time->Hour += 1; - Date_and_Time->Minute =0; - } - } - else //cpu will sleep less than a day in most. - { - static _u32 last_count; - _u32 count, sleep_time; - count = *(volatile _u32 *)0xbfeb001c; - count &= COUNT_MASK; - sleep_time = (count - last_count)%COUNT_COMPARE; - _u32 i; - for(i=0;i<(sleep_time/57600);i++) //57600=3600*16, one hour - Date_and_Time->Hour += 1; - for(i=0;i<((sleep_time%57600)/960);i++) //960=60*16, one minute - Date_and_Time->Minute += 1; - for(i=0;i<((sleep_time%960)/16);i++) - Date_and_Time->Second += 1; - last_count = count - (count%16); //This is a good write! Read the last 6 lines to understand it. - if(Date_and_Time->Second >= 60) - { - Date_and_Time->Minute += 1; - Date_and_Time->Second %= 60; - } - if(Date_and_Time->Minute >= 60) - { - Date_and_Time->Hour += 1; - Date_and_Time->Minute %= 60; - } - } - - if(Date_and_Time->Hour >= 24) - { - /**/ - if((Date_and_Time->Year%400==0)||((Date_and_Time->Year%4 ==0)&&(Date_and_Time->Year%100 !=0))){ - switch(Date_and_Time->Day){ - case 29: - if(Date_and_Time->Month == 2) AddMonth(Date_and_Time); - else AddDay(Date_and_Time); - break; - case 30: - if((Date_and_Time->Month ==4)||(Date_and_Time->Month ==6)||(Date_and_Time->Month ==9)||(Date_and_Time->Month ==11)) - AddMonth(Date_and_Time); - else AddDay(Date_and_Time); - break; - case 31: - if(Date_and_Time->Month == 12) AddYear(Date_and_Time); - else AddMonth(Date_and_Time); - break; - default: - AddDay(Date_and_Time); - break; - } - } - else{ - switch(Date_and_Time->Day){ - case 28: - if(Date_and_Time->Month == 2) AddMonth(Date_and_Time); - else AddDay(Date_and_Time); - break; - case 30: - if((Date_and_Time->Month ==4)||(Date_and_Time->Month ==6)||(Date_and_Time->Month ==9)||(Date_and_Time->Month ==11)) - AddMonth(Date_and_Time); - else AddDay(Date_and_Time); - break; - case 31: - if(Date_and_Time->Month == 12) AddYear(Date_and_Time); - else AddMonth(Date_and_Time); - break; - default: - AddDay(Date_and_Time); - break; - } - } - Date_and_Time->Hour %= 24; - } - - DateLowV(Date_and_Time); -} - -void DateInit(struct Date_Time *Date_and_Time) -{ - Date_and_Time->Year = 2012; - Date_and_Time->Month = 1; - Date_and_Time->Day = 31; - Date_and_Time->Hour = 23; - Date_and_Time->Minute = 40; //59; - Date_and_Time->Second = 15; //45; - main_flag |= month_flag; -} -#endif diff --git a/resources/soc/simu/soft/func/source/Infrare.c b/resources/soc/simu/soft/func/source/Infrare.c deleted file mode 100644 index 45a80f8..0000000 --- a/resources/soc/simu/soft/func/source/Infrare.c +++ /dev/null @@ -1,33 +0,0 @@ -/********************************************************************************************************************************************************************** - This file enables the Infrare receiver to receive signals. -**********************************************************************************************************************************************************************/ - -#include "../config.h" - -#if INFRARE_MODULE -void Infrare() -{ - if((main_flag & wait_8sec)==0){ - if(main_flag & infrare_flag) //⴦ڴ״̬ - { - PMU_GPIO_O &= 0xfffffff7; //IR_PWR OFF - //rUart1_MCR &= ~0xa0; //MCR bit7: ; bit6:Rx bit5:Tx - main_flag &= ~infrare_flag; - } - else //⴦ڹر״̬ - { - main_flag |= infrare_flag; - PMU_GPIO_OE |= 1 << 3; //IO - PMU_GPIO_O |= 1 << 3; //IR - RX_IndexW = 0; -#if UART1_INT - Uart1_IER |= 0x1; //enable uart1 rx int -#endif - - wait[1] = 0; - main_flag |= wait_8sec; - } - } -} - -#endif diff --git a/resources/soc/simu/soft/func/source/Interrupt.c b/resources/soc/simu/soft/func/source/Interrupt.c deleted file mode 100644 index 9d49a58..0000000 --- a/resources/soc/simu/soft/func/source/Interrupt.c +++ /dev/null @@ -1,6 +0,0 @@ -/********************************************************************************************************************************************************************** - This file processes all kinds of interrupt, some parts are placed in start.S. -**********************************************************************************************************************************************************************/ - -#include "../config.h" - diff --git a/resources/soc/simu/soft/func/source/MonthData.c b/resources/soc/simu/soft/func/source/MonthData.c deleted file mode 100644 index 49bf59e..0000000 --- a/resources/soc/simu/soft/func/source/MonthData.c +++ /dev/null @@ -1,62 +0,0 @@ -/********************************************************************************************************************************************************************** - This file writes the info flash when MonthDate comes. - It should need four step to write flash: - 1) clear page_latch - 2) write data into page_latch - 3) clear the flash page - 4) write the flash page - *page_latch just like a buffer. -**********************************************************************************************************************************************************************/ - -#include "../config.h" - -_u32 Last_month_num; //0~17 -#if MONTHDATA_MODULE -struct Record_1 Latest_Record; - -void Flash_Read_Info() -{ - -} - -void MonthData(struct Date_Time *Date_and_Time, struct Data *Lcd_data) //flashݱʽΪBCD -{ -#if MONTHDATA_TEST - printf("%s()...\n", __FUNCTION__); -#endif - struct Record_0 Month_Record; - if(Date_and_Time->Month == 1) - { - Month_Record.Date = (Date_and_Time->Year-1)*1000 + 12*10; //store in _u32 format - } - else - { - Month_Record.Date = Date_and_Time->Year*1000 + (Date_and_Time->Month-1)*10; //store in _u32 format - } //eg: 20110120 - - Month_Record.TotalHeat = (_u32)(Lcd_data->total_heat)*100/LCD_MULTIPLE; - Month_Record.TotalFlow = (_u32)(Lcd_data->total_flow)*100/LCD_MULTIPLE; - - //write flash - Last_month_num++; - Last_month_num %= 18; - - _u32 addr, err=1; - addr = INFO_FLASH_START + Last_month_num*12 ; - err = Flash_Write( addr, &Month_Record, 3) ; - - BUG_ON(err) - -} - -void Flash_Write_Test() -{ - _u32 data[4]; - _u32 i,addr; - for(i=0;i<4;i++) - data[i] = i; - addr = 0xbfc0f004; - Flash_Write(addr, data, 4) ; - -} -#endif diff --git a/resources/soc/simu/soft/func/source/SystemInit.c b/resources/soc/simu/soft/func/source/SystemInit.c deleted file mode 100644 index c7e5c22..0000000 --- a/resources/soc/simu/soft/func/source/SystemInit.c +++ /dev/null @@ -1,118 +0,0 @@ -/********************************************************************************************************************************************************************** - This file inits some module in LS1D chip. -**********************************************************************************************************************************************************************/ - -#include "../config.h" -#include "../include/asm/ns16550.h" - -void Uart0_Init() -{ - /* - 8bit 1stop 38400Baut - */ -#if 1 - Uart0_FCR = FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_4; - Uart0_LCR = CFCR_DLAB; - Uart0_FCR = 0xCF; - Uart0_BaudL = 0x23; //set 57600Baut - Uart0_LCR = CFCR_8BITS; //8bit, 1stop - Uart0_MCR = MCR_DTR|MCR_RTS; - Uart0_IER = 0; -#endif - /*the uart0 rx default state is high, it can work when egde_low or no_egde_low.*/ -#if 0 - INT_EGDE |= 0x08; //egde change available - INT_POL |= 0x08; //low available - //INT_POL &= ~0x08; //high available - Uart0_IER |= 0x01; //enable uart0 rx int - INT_EN |= 0x08; //enable uart0 int -#endif - -#if PRINT - printf("Uart0 init...\n"); -#endif -} - -static void Uart1_Init(void) -{ - /* - 8bit 1stop 2400Baut odd parity - */ -#if 0 - __asm__ volatile( - "lui $2,0xbfe8;\n" \ - "ori $2,$2,0x8000;\n" \ - "li $3,7;\n" \ - "sb $3,2($2);\n" \ - "li $3,-128;\n" \ - "sb $3,3($2);\n" \ - "li $3,-48;\n" \ - "sb $3,0($2);\n" \ - "li $3,11;\n" \ - "sb $3,3($2);\n" \ - "li $3,3;\n" \ - "sb $3,4($2);\n" \ - "li $3,0;\n" \ - "sb $3,1($2);\n" \ - :::"$2","$3" - ); -#else - Uart1_FCR = FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_1; - Uart1_LCR = CFCR_DLAB; - Uart1_BaudL = 208; //set 2400Baut - Uart1_LCR = CFCR_8BITS|CFCR_PENAB|CFCR_PODD; //8bit, 1stop, odd parity - Uart1_MCR = MCR_DTR|MCR_RTS; - Uart1_IER = 0; -#endif - - /*the uart1 rx default state is low, when IR_PWR is off; only can it work when no_egde_low.*/ - //INT_EGDE |= 0x04; //egde change available - //INT_CLR = 0x3f; //clear all int bit - //INT_POL &= ~0x04; //high available - INT_POL |= 0x04; //low available - INT_EN |= 0x04; //enable uart1 int - -#if PRINT - printf("Uart1 init...\n"); -#endif - -#if !(UART1_INT) - _u8 data; - data = Uart1_RxData; //clear the receive fifo - Uart1_IER |= 0x01; //enable uart1 rx int -#endif -} - -static void ReLoad() //ϵָӵ籣λöȡݣ¸ֵ -{ -#if 0 - DateInit(); -#endif - - //Monthdata.h - //temp_flow.h - //Last_total_flow = -} - -void SystemInit() -{ - //DisableWatchDog(); - /* - enable BT\UART\KEY\BAT_FAIL Interrupt - */ -// Interrupt_Init(); - - //Uart0_Init(); -#if (INFRARE_MODULE|FRAME_MODULE) - Uart1_Init(); -#endif - ReLoad(); -#if (TDC_TEMP_MODULE|TDC_FLOW_MODULE) - InitTdc(); -#endif -#if AD_MODULE - ADC_Init(); -#endif - -} - diff --git a/resources/soc/simu/soft/func/source/adc.c b/resources/soc/simu/soft/func/source/adc.c deleted file mode 100644 index 7e77c0d..0000000 --- a/resources/soc/simu/soft/func/source/adc.c +++ /dev/null @@ -1,49 +0,0 @@ -#include "../config.h" - -/**************************** -*ADC* base addr : 0xbfea8000 - cr offset : 0x0 - datalow offset : 0x1 (result[3:0] in D0[7:4]) - datahigh offset : 0x2 (result[11:4] in D1[7:0]) -*cr* [8] : start - [7] : standby (RO) - [2:0] : select - select=0: adci_a (battery voltage 3~3.7V ) - select=1: ldo output (core voltage 1.8V ) - -Liu Su -liusu-cpu@ict.ac.cn -****************************/ - -#if ADC_MODULE - -#define adc_start 0x80 -#define adc_standby 0x40 - -static _u32 ADC_measure(_u8 adc_sel) -{ - ADC_CR = adc_start | adc_sel; - while (ADC_CR & adc_standby != adc_standby) {} - return (ADC_D1 << 8 + ADC_D0) >> 4; -} - -float BatteryMeasure(void) -{ - float BatteryVoltage; - _u32 result_battery, result_core; - - result_core = ADC_measure(0); - result_battery = ADC_measure(1); - - BatteryVoltage = 1.8 * result_battery / result_core; - //printf("Battery Voltage : %f V\n", BatteryVoltage); - return BatteryVoltage; -} - -#endif // ADC_MODULE -int ADC_test(int argc, char argv[][30]) -{ - printf("\nin ADC_test"); - return 0; -} - diff --git a/resources/soc/simu/soft/func/source/battery.c b/resources/soc/simu/soft/func/source/battery.c deleted file mode 100644 index e85eb6f..0000000 --- a/resources/soc/simu/soft/func/source/battery.c +++ /dev/null @@ -1,148 +0,0 @@ -/********************************************************************************************************************************************************************** - This file uses ADC module to detect and measure the voltage of battery. -**********************************************************************************************************************************************************************/ - -#include "../config.h" - -#if AD_MODULE -void ADC_Init(void) -{ - IIC_PRER_L = 0x64; //Baud rate= 8M/4/PRER - IIC_PRER_H = 0x0; - IIC_CTR = 0xa0; //CTR[7]:core_en [6]:int_en [5]:master:1 slave:0 [4]:txr_ok [3]:rxr_ok bit[4,3] use in slave mode - - IIC_TXR = 0x6c; //slave addr + w - IIC_CR = 0x90; //start and write - while( (IIC_SR & 0x83) != 0x01 ); - IIC_CR = 0x01; - - IIC_TXR = 0x63; // max11645 config byte converte channel AN1 ,single ended - IIC_CR = 0x50; //send congig byte and stop - while( (IIC_SR & 0x83) != 0x01 ); - IIC_CR = 0x01; - -#if AD_TEST - printf("AD module initted...\n"); -#endif -} - - -static _u32 ADC() //power_detect -{ - _u32 sum = 0; - _u32 tmp = 0; - _u32 i; - for( i = 0; i < 8; i++) - { - IIC_TXR = 0x6c; //slave addr + w - IIC_CR = 0x90; //start and write - while( (IIC_SR & 0x83) != 0x01 ); - IIC_CR = 0x01; - - //IIC_TXR = 0xd2; //max11645 setup byte Vref = 2.048 (internal Vref), if use external Vref :a2 - IIC_TXR = 0xa2; //max11645 setup byte Vref = 2.048 (internal Vref), if use external Vref :a2 - IIC_CR = 0x50; //tx and stop - while( (IIC_SR & 0x83) != 0x01 ); - IIC_CR = 0x01; - - /************ read *********************/ - IIC_TXR = 0x6d; //slave addr + r - IIC_CR = 0x90; - while( (IIC_SR & 0x83) != 0x01 ); - IIC_CR = 0x01; - - IIC_CR = 0x20; //read - while( (IIC_SR & 0x83) != 0x01 ); - IIC_CR = 0x01; - tmp = IIC_RXR & 0x0f; - - IIC_CR = 0x60; //read & stop - while( (IIC_SR & 0x83) != 0x01 ); - IIC_CR = 0x01; - - tmp = tmp << 8; - tmp |= IIC_RXR & 0xff; - sum += tmp; - } - return (sum >> 3); -} - -void BatteryTest1() -{ - _u32 i; - _fp32 V_BAT; - - i = ADC(); - V_BAT = 4096*1.8f/i ; -#if AD_TEST - printf("---------------------------------------------------Battery: 0x%x------------", i); - printf_float(V_BAT); -#endif - -#if 0 - if(main_flag & wait_10sec){ //ŵѹ - if((main_flag & lowV_flag) == 0) //ǰΪ״̬ - { - if(i<0x0900) //Ϊ͵ѹ - { - if(main_flag & wait_oneday) //ڶηŵ - { - main_flag |= lowV_flag; - main_flag |= lcd_bit; - } - else //һηŵ - { - wait[6] = 0; - main_flag |= wait_oneday; - } - } - else //Ϊ - { - } - } - else //ǰѾΪ͵ѹ״̬ //ӳһ ڶηŵ - { - if(i>0x0b00){ - main_flag &= ~lowV_flag; - main_flag |= lcd_bit; - } - } - } - else //ŵѹ - { - static unsigned short m; - if((main_flag & lowV_flag) == 0) //ǰΪ״̬ - { - if(i<0x0aaa){ - main_flag |= lowV_flag; - main_flag |= lcd_bit; - } - } - else //ǰѾΪ͵ѹ״̬ - { - if(i>0x0b00){ - if(m==0) - { - wait[4] = 0; - main_flag |= wait_16min; - } - m = 1; - } - else m = 0; - } - } -#endif - //P3DIR &= ~0x10; -} - -void BatteryTest2() //ŵ -{ - //طŵ -#if 0 - P3DIR |=0x20; - P3OUT |=0x20; -#endif - wait[5] = 0; - main_flag |= wait_10sec; -} -#endif diff --git a/resources/soc/simu/soft/func/source/cmdline.c b/resources/soc/simu/soft/func/source/cmdline.c deleted file mode 100644 index 4978482..0000000 --- a/resources/soc/simu/soft/func/source/cmdline.c +++ /dev/null @@ -1,326 +0,0 @@ -#include "../config.h" -#include -#include -#include -#include -#define write_u32(addr,value) (*(volatile _u32*)(addr) = (value)) -#define read_u32(addr) (*(volatile _u32*)(addr)) - -#define LS1D -int help(int argc, char argv[][30]); -int m4(int argc, char argv[][30]); -int m1(int argc, char argv[][30]); -int d4(int argc, char argv[][30]); -int d1(int argc, char argv[][30]); -int float_test(int argc, char argv[][30]); - - -unsigned int str2num(char str[30]); - char cmdpara[10][30]; - char **pp; -static _u8 mygetchar(); -static void myputchar(_u8 chr); -struct cmd_struc { - const char *cmdname; - int (*func) __P((int, char *[])); -} cmd[] = {{"exit", NULL}, - {"help", help}, - {"m4", m4}, - {"m1", m1}, - {"d4", d4}, - {"d1", d1}, - {"", NULL} -}; - -int float_test(int argc, char argv[][30]) -{ - unsigned int a,b; - float i,j,k,l,m; - a = 3000; - b = 4096; - k = (float)a/(float)b; - i = 2.0; - j = 3.3; - l = 0.99; - m = 1.01; - i = i/j; - l = l/m; - k = i/l; - if(k>0.99 && k<1.01) a++; - else a--; - return 0; -} - - -static void myputchar(_u8 chr) -{ - while(!(Uart0_LSR & 0x20)) ; - Uart0_TxData = chr; -} - -static _u8 mygetchar() -{ - _u8 chr; -// int i=0,j; -// while(1) {if(Uart0_LSR & 0x1) break;else -// for(i=0;i<100;i++) {j=*(volatile _u32*)(0xbe000000);}} - while(!(Uart0_LSR & 0x1)) ; - chr = Uart0_RxData ; -// printf("f"); -// printf("%d",chr); - return chr; -} - -int help(int argc, char argv[][30]) -{ - int i; - printf("\ncommands:\n"); - for(i=1;i<100;i++) - { - if(strcmp(cmd[i].cmdname,"")==0) break; - else printf(" %s",cmd[i].cmdname); - } -// printf("\n"); - - return 0; -} - -unsigned int str2num(char str[30]) -{ - int value = 0; - int sign = 1; - int radix; - - if(*str == '-') - { - sign = -1; - str++; - } - if(*str == '0' && (*(str+1) == 'x' || *(str+1) == 'X')) - { - radix = 16; - str += 2; - } - else if(*str == '0') // 八进制首字符为0 - { - radix = 8; - str++; - } - else - radix = 10; - while(*str) - { - if(radix == 16) - { - if(*str >= '0' && *str <= '9') - value = value * radix + *str - '0'; - else - value = value * radix + (*str | 0x20) - 'a' + 10; - // value = value * radix + *str - 'a' + 10; // 也没问题啊 - } - else - value = value * radix + *str - '0'; - str++; - } - return (unsigned int *)(sign*value); -} - -int m4(int argc, char argv[][30]) -{ - unsigned int addr,value; -// printf("%s\n",argv[1]); - if(argc != 3) - { - printf("\nusage: m4 "); - return 1; - } - addr=str2num(argv[1]); - value=str2num(argv[2]); -#ifdef LS1D - *(volatile unsigned int*)(addr) = value; -#else - printf("addr: %x ,value: %x\n",addr,value); -#endif - return 0; -} - -int m1(int argc, char argv[][30]) -{ - unsigned int addr,value; -// printf("%s\n",argv[1]); - if(argc != 3) - { - printf("\nusage: m1 "); - return 1; - } - addr=str2num(argv[1]); - value=str2num(argv[2]); -#ifdef LS1D - *(volatile unsigned char*)(addr) = value; -#else - printf("addr: %x ,value: %x\n",addr,value); -#endif - return 0; -} - -int d4(int argc, char argv[][30]) -{ - unsigned int addr; - if(argc != 2) - { - printf("\nusage: d4 "); - return 1; - } - addr=str2num(argv[1]); -#ifdef LS1D - printf("\n0x%08x: %08x",addr,*(volatile unsigned int*)(addr)); -#else - printf("0x%08x:\n",addr); -#endif - return 0; -} - -int d1(int argc, char argv[][30]) -{ - unsigned int addr; - if(argc != 2) - { - printf("\nusage: d1 "); - return 1; - } - addr=str2num(argv[1]); -#ifdef LS1D - printf("\n0x%08x: %02x",addr,*(volatile unsigned char*)(addr)); -#else - printf("0x%08x:\n",addr); -#endif - return 0; -} - -int cmdline(void) -{ - char c; - char cmdbuffer[40]; - char *cbuffer; - short ccc,cpc,cbc,i,j; - int count=0; -// int (*func) (int , char **); - int (*op)(int argc,char **argv); - i=0; - j=0; - ccc=0; - cpc=0; - printf("This is the 1st test!\n"); - printf("This is the 2nd test!\n"); -// printf("This is the 3rd test!\n"); -// printf("This is the 4th test!\n"); -// printf("This is the 5th test!\n"); -// test mult - int opa = 1; - int opb = 2; - int result1 = opa * opb; - int result10 = 1 * 2; - int result2 = (opa+1) * (opb+4); - int result20 = 2 * 6; - int result3 = (opa+299) * (opb+298); - int result30 = 300 * 300; - printf("result: %d %d\n", result1, result10); - printf("result: %d %d\n", result2, result20); - printf("result: %d %d\n", result3, result30); - while(1){} -while(1) -{ - for(i=0;i<10;i++) - for(j=0;j<30;j++) - cmdpara[i][j] = '\0'; - for(i=0;i<40;i++) cmdbuffer[i]= '\0'; -// printf("\n$ "); - cbuffer = cmdpara[0]; -// printf("@ "); - ccc=0; -// printf("@ "); - cpc=0; -// printf("@ "); - cbc=0; -// printf("@ "); - count++; -// for(i=0;i<1000;i++) i++; - printf("\nS "); -// for(i=0;i<500;i++) j=Uart0_LSR; -// printf("%4d ",count); -// i=1; -// while(i++) {printf("\n%4d",i);j++;} - // internal loop - while(1) - { -// printf("|\n"); - c=mygetchar(); -// printf("%d\n",c); -// printf("/"); -// c=13; -// c=53; - if(c==8) - { - cbc=cbc-1; - cmdbuffer[cbc] = '\0'; - myputchar(8);myputchar(32);myputchar(8); - } - else - { - cmdbuffer[cbc++] = c; - myputchar(c); - } -// printf("\r%s",cmdbuffer); - if(c==10 || c==13) break; - } - for(i=0;i 0; i--) - { - for(j = 0; j < (i - 1); j++) - { - if(delta[j] > delta[j+1]) - { - tmp = delta[j]; - delta[j] = delta[j+1]; - delta[j+1] = tmp; - } - } - } -#if 0 //PRINT - for(i = 0; i < len; i++) - { - //printf("%f ", delta[i]); - if(delta[i] < 0) - { - tmp_print = 0 - delta[i]; - printf("-%d ", (unsigned int)(tmp_print*1000)); - } - else - { - tmp_print = delta[i]; - printf("%d ", (unsigned int)(tmp_print*1000)); - } - if(i == len-1) printf("\r\n"); - } -#endif - - for(i = 1; i < len - 1; i++) - { - sum += delta[i]; - } - average = sum/(len -2); - return average; -} - -void UintToBcd(_u32 dat, _u8 *bcd_buf) -{ - //_u32 tmp = dat; - - //if(dat>=100000000) dat=dat%100000000 ; - dat = dat%100000000 ; - bcd_buf[3] = dat/10000000 ; - bcd_buf[3] <<= 4 ; - dat = dat%10000000 ; - bcd_buf[3] |= (dat/1000000) ; - - dat = dat%1000000 ; - bcd_buf[2] = dat/100000 ; - bcd_buf[2] <<= 4 ; - dat = dat%100000 ; - bcd_buf[2] |= (dat/10000) ; - - dat = dat%10000 ; - bcd_buf[1] = dat/1000 ; - bcd_buf[1] <<= 4 ; - dat = dat%1000 ; - bcd_buf[1] |= (dat/100) ; - - dat = dat%100 ; - bcd_buf[0] = dat/10 ; - bcd_buf[0] <<= 4 ; - dat = dat%10 ; - bcd_buf[0] |= dat ; - -//printf("***: %d\t***BCD:%x %x %x %x\n", tmp, bcd_buf[3], bcd_buf[2], bcd_buf[1], bcd_buf[0]); -} - -void BcdToUint(_u8 *bcd_buf, _u32 dat) -{ - dat = ( ( (_u32)bcd_buf[3]>>4 ) *10000000 ) - + ( ( (_u32)bcd_buf[3]&0xf )*1000000 ) - + ( ( (_u32)bcd_buf[2]>>4 ) *100000 ) - + ( ( (_u32)bcd_buf[2]&0xf )*10000 ) - + ( ( (_u32)bcd_buf[1]>>4 ) *1000 ) - + ( ( (_u32)bcd_buf[1]&0xf )*100 ) - + ( ( (_u32)bcd_buf[0]>>4 ) *10 ) - + ( ( (_u32)bcd_buf[0]&0xf ) ); - -//printf("***BCD:%x %x %x %x\t***: %d\n", bcd_buf[3], bcd_buf[2], bcd_buf[1], bcd_buf[0], dat); -} - -//print float number -#if PRINT -int printf_float(float data) -{ - unsigned int i=0,j=0; - i = (unsigned int)(data); - j = (unsigned int)((data-i)*1000000); - printf("%d.%06d\n", i, j); - - return 0; -} -#endif - diff --git a/resources/soc/simu/soft/func/source/dg_rs232.c b/resources/soc/simu/soft/func/source/dg_rs232.c deleted file mode 100644 index 36fe314..0000000 --- a/resources/soc/simu/soft/func/source/dg_rs232.c +++ /dev/null @@ -1,193 +0,0 @@ -#include -#include "../config.h" -#include "../include/asm/ns16550.h" - -#define COM_BASE 0xbfe88000 //com1 for 1D -#define NS16550_LSR 5 -#define NS16550_DATA 0 - -#define LSR_TXRDY 0x20 -#define LSR_RXRDY 0x01 - -#define writeb(val, addr) (*(volatile unsigned char*)(addr) = (val)) -#define readb(addr) (*(volatile unsigned char*)(addr)) -int dg_write(char *str); -int dg_read(char *buffer, unsigned num); -static void uart_putchar(char a0); -static char uart_getchar(void); -static void uart1_init(void) -{ - Uart1_FCR = FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_4; - Uart1_LCR = CFCR_DLAB; - Uart1_BaudL = 52; //set 9600Baut - Uart1_LCR = CFCR_8BITS; //8bit, 1stop - Uart1_MCR = MCR_DTR|MCR_RTS; - Uart1_IER = 0; -} - -int dg_ctrl(int argc, char argv[][30]) // main -{ - char buffer[1024]; - uart1_init(); - printf("\n"); - /* Make sure ip address is supplied on the command line */ -// if ( argc < 2 ) { -// printf("Usage: dg_ctrl IP_ADDRESS\n"); -// exit(1); -// } - /* Initialize the sockets library */ -// init_tcpip(); - /* Connect to the dg645 */ -// if ( dg_connect( inet_addr(argv[1]) ) ) { -// printf("Connection Succeeded\n"); - /* Get identification string */ - dg_write("*idn?\n"); -// printf("\n*idn?\n"); - if ( dg_read(buffer,sizeof(buffer)) ) - printf("%s\n",buffer); - else - printf("Timeout\n"); - /* Load default settings */ - dg_write("*rst\n"); // load default settings - dg_write("tsrc 1\n"); // set trigger source to 1(external posedge) - dg_write("burc 1\n"); // set burst count to 1 - dg_write("burd 4e-6\n"); // set burst delay to 4us - dg_write("burm 1\n"); // set burst mode to ON - dg_write("burp 1e-6\n"); // set burst period to 1us - dg_write("dlay 2,0,5e-8\n"); // set A to 0 delay to 50ns - dg_write("dlay 3,2,5e-7\n"); // set B to A delay to 500ns - dg_write("tlvl 0.9\n"); // set trigger level to 0.9V - dg_write("lamp 0,1.66\n"); // set T0 amplitude to 1.66V - dg_write("lamp 1,1.66\n"); // set AB amplitude to 1.66V - dg_write("*sav 4\n"); // save config to 4 -// dg_write("*wai\n"); // wait execute - /* Make sure all commands have executed before closing connection */ -// dg_write("*opc?\n"); -// if ( !dg_read(buffer,sizeof(buffer)) ) -// printf("Timeout\n"); - /* Close the connection */ -// if (dg_close()) -// printf("Closed connection\n"); -// else -// printf("Unable to close connection"); -// } -// else -// printf("Connection Failed\n"); - return 0; -} - -int dg_cmd(int argc, char argv[][30]) -{ - printf("\n"); - dg_write(argv[1]); - dg_write("\n"); -return 0; -} - -int dg_write(char *str) -{ -// printf("\n"); - while(*str != '\0'){ - uart_putchar(*str); - printf("%c",*str); - str++; - } - if(*(str-1) == '\n') printf("\r"); - return 0; -} - -int dg_read(char *buffer, unsigned num) -{ - char t; - int count=0; - unsigned flag=0; - while(1){ - t=uart_getchar(); - if(t==-1) { - *buffer = '\0'; return count; - } - //if(t==10 || t==13 || t=='\0') flag=1; // - if(flag){ - *buffer = '\0'; return count; - } - else{ - *buffer = t; buffer++; count++; - } - } -} - -static void uart_putchar(char a0) -{ - while((readb(COM_BASE + NS16550_LSR) & LSR_TXRDY)==0){} - writeb(a0, COM_BASE + NS16550_DATA); -} - -static char uart_getchar() -{ -//printf("fly to here\n"); - int cnt=0; - while(cnt<1000000 && (readb(COM_BASE + NS16550_LSR) & LSR_RXRDY)==0){cnt++;} - if (cnt>=1000000) return -1; - return readb(COM_BASE + NS16550_DATA); -} - -/* - -TSRC(?){i} Trigger Source -Set (query) the trigger source {to i}. The parameter i determines the trigger -source according to the following table: -i Trigger Source -0 Internal -1 External rising edges -2 External falling edges -3 Single shot external rising edges -4 Single shot external falling edges -5 Single shot -6 Line -Example -TSRC 5 Set up the DG645 for single shot triggering. - -///------------------------- - -DLAY(?)c{,d,t} Delay -Set (query) the delay for channel c {to t relative to channel d}. -Example -DLAY 2,0,10e-6 Set channel A delay to equal channel T0 plus 10 μs. -DLAY 3,2,1e-3 Set channel B delay to equal channel A delay plus 1 ms. -DLAY?3 Query channel B. Should return ‘2,+0.001000000000’ to -indicate that B = A + 1 ms. - -///-------------------------BURST - -BURC(?){i} Burst Count -Set (query) the burst count {to i}. When burst mode is enabled, the DG645 -outputs burst count delay cycles per trigger. -Example -BURC 10 Set the burst count to 10 so that the DG645 will output -10 delay cycles per triggered burst. - -BURD(?){t} Burst Delay -Set (query) the burst delay {to t}. When burst mode is enabled the DG645 delays -the first burst pulse relative to the trigger by the burst delay. -Example -BURD 5e-6 Set the burst delay to 5 μs so that the DG645 will delay the -first cycle of the burst by 5 μs relative to the trigger. - -BURM(?){i} Burst Mode -Set (query) the burst mode {to i}. If i is 0, burst mode is disabled. If i is 1, burst -mode is enabled. - -BURP(?){t} Burst Period -Set (query) the burst period {to t}. The burst period sets the time between delay -cycles during a burst. The burst period may range from 100 ns to 2000 – 10 ns in -10 ns steps. -Example -BURP 1e-3 Set burst period to 1 ms. When a burst is triggered, the -DG645 will generate burst count delay cycles at a 1 kHz rate. - -BURT(?){i} Burst T0 Configuration -Set (query) the burst T0 configuration {to i}. If i is 0, the T0 output is enabled for -all delay cycles of the burst. If i is 1, the T0 output is enabled for first delay cycle -of the burst only. - -*/ diff --git a/resources/soc/simu/soft/func/source/flash.c b/resources/soc/simu/soft/func/source/flash.c deleted file mode 100644 index c54c5f2..0000000 --- a/resources/soc/simu/soft/func/source/flash.c +++ /dev/null @@ -1,255 +0,0 @@ -#include "../config.h" - -extern unsigned int str2num (char str[30]); -void mywait(void); -/****************************** -*Flash Test* CONFIDENTIAL - ->CAUTION< -DO NOT add this program to ANY release version! - -Liu Su -liusu-cpu@ict.ac.cn -******************************/ - -//#if FLASH_TEST - -static void flash_clearHVPL(void) -{ - *(volatile _u32*)(0xbfe60000) = 0x40000000; -} - -static void flash_erase(_u32 offset) -{ - *(volatile _u32*)(0xbfe60000) = 0xa0000000|offset; -} - -static void flash_page(_u32 offset) -{ - *(volatile _u32*)(0xbfe60000) = 0xe0000000|offset; -} - -static void flash_setca(_u32 cah, _u32 cal) -{ - *(volatile _u32*)(0xbfe60008) = cal; - *(volatile _u32*)(0xbfe60004) = cah; - *(volatile _u32*)(0xbfe60000) = 0xf0000000; -} - -int set_ca(int argc, char argv[][30]) -{ - _u32 cah,cal; - if(argc !=3 ) {printf("\nUsage: setca ");return 1;} - cah = str2num(argv[1]); - cal = str2num(argv[2]); - *(volatile _u32*)(0xbfe60008) = cal; - *(volatile _u32*)(0xbfe60004) = cah; - *(volatile _u32*)(0xbfe60000) = 0xf0000000; -// mywait(); - return 0; -} - -static void flash_writepl() -{ - int i; - for(i=0; i<128; i+=4) - *(volatile _u32*)(0xbf00e000 + i) = i; -} - -int verif(int argc, char argv[][30]) -{ - printf("\nverif"); - _u32 page_offset; - _u32 page_latch[33]; - int i; - page_offset = 0xe000; - printf("\noffset"); -// crypt - flash_setca(0x1f00e100,0x1f00e000); - printf("\nsetca\n"); -// normal page - flash_clearHVPL(); - printf("clearHVPL\n"); - flash_writepl(); - printf("writepl\n"); - flash_erase(page_offset); -// mywait(); - printf("erase\n"); - flash_page(page_offset); -// mywait(); - printf("page\n"); -// verif - *(volatile _u32*)(0xbfe60010) = 0x14; - *(volatile _u32*)(0xbfe60000) = 0x1000e014; - while(*(volatile _u32*)(0xbfe60014) & 0x2 != 0x2){} - if(*(volatile _u32*)(0xbfe60014) & 0x1) - printf("verif correct\n"); - else - printf("verif error"); -// flash_setca(0x1f000001,0x1f000001); -return 0; -} - -int set_pe_time_mode(int argc, char argv[][30]) -{ - unsigned int mode; - mode = str2num(argv[1]); - *(volatile _u32*)(0xbfe60024) = mode; -/**************************** -mode: 0: 1.5ms - 1: 2.0ms - 2: 2.5ms - 3: 3.0ms - 4: 3.5ms -****************************/ -return 0; -} - -static void set_pe_time(int mode) -{ - *(volatile _u32*)(0xbfe60024) = mode; -} - -int flash_tk(int argc, char argv[][30]) -{ - unsigned int i,num; - num = str2num(argv[1]); - for(i=0; i 0){ - UART_OutpLen--; - Uart1_TxData = frame_tx[TX_IndexW]; - TX_IndexW +=1; - } - else{ - //IFG1 &= ~UTXIFG0; - } -} - -void uart_rx(void) -{ - static _u32 rx_head_flag; //'0'δյ֡ʼ - frame_rx[RX_IndexW] = Uart1_RxData; //ıȽϸߣʱᶪʧһַ֡??? -#if PRINT -printf("%x ", frame_rx[RX_IndexW]); -#endif - RX_IndexW +=1; - - static _u32 len; - if((rx_head_flag == 0) && (frame_rx[RX_IndexW-1] == HEAD)){ - len = RX_IndexW + 9; - rx_head_flag = 1; //յ֡ʼ - } - if(rx_head_flag == 1){ - if((frame_rx[RX_IndexW-1] == TAIL) && (RX_IndexW > (len+(_u32)frame_rx[len]+2))){ - //if(RX_BUFF[len+(_u32)RX_BUFF[len])+2] == TAIL){ - rx_head_flag = 0; - //UART_InpLen = RX_IndexW; - RX_IndexW =0; - main_flag |= rx_bit; //usartյһ֡ -#if PRINT -printf("\n"); -#endif - } - } - -} - -/*-----------------------Ӧ֡----------------------*/ -void Answer() -{ - _u32 i=0; - _u32 j; - _u32 head = 3; - Frame.CheckSum = 0x0; - frame_tx[i++] = 0xfe; - frame_tx[i++] = 0xfe; - frame_tx[i++] = 0xfe; - frame_tx[i++] = Frame.HeadCode; - frame_tx[i++] = Frame.TypeCode; - for(j=0;j<7;j++) - frame_tx[i++] = Frame.Address[j]; - frame_tx[i++] = Frame.CtrlCode; //Ҫ쳣жϺλ - frame_tx[i++] = Frame.DataLen; -#if CJT188_DI_SEQ - frame_tx[i++] = Frame.DI0; - frame_tx[i++] = Frame.DI1; -#else - frame_tx[i++] = Frame.DI1; - frame_tx[i++] = Frame.DI0; -#endif - frame_tx[i++] = Frame.SER; - for(j=0;j<((_u32)Frame.DataLen-3);j++) - frame_tx[i++] = Frame.Data[j]; - while(head < i){ - Frame.CheckSum += frame_tx[head]; - Frame.CheckSum %= 256; - head++; - } - frame_tx[i++] = Frame.CheckSum; - frame_tx[i++] = Frame.TailCode; - UART_OutpLen =i; -} - -_u32 read1(struct Date_Time *Date_and_Time, struct Data *Lcd_data) -{ - _u32 i=0; - _u32 j; - _u32 dat; - union uint_uchar uint2uchar; - Frame.DataLen = 0x2e; - - dat = *(_u32 *)(INFO_FLASH_START + Last_month_num*12 + 4);//total heat of last month - UintToBcd(dat, &uint2uchar); - for(j=0; j<4; j++) - Frame.Data[i++] = uint2uchar.c_value[j]; - Frame.Data[i++] = danwei_KWh; - - dat = (_u32)Lcd_data->total_heat*100/LCD_MULTIPLE; //ǰ - UintToBcd(dat, &uint2uchar); - for(j=0; j<4; j++) - Frame.Data[i++] = uint2uchar.c_value[j]; - Frame.Data[i++] = danwei_KWh; - - dat = (_u32)Lcd_data->heat*100/LCD_MULTIPLE; //ȹ - UintToBcd(dat, &uint2uchar); - for(j=0; j<4; j++) - Frame.Data[i++] = uint2uchar.c_value[j]; - Frame.Data[i++] = danwei_KW; - - dat = (_u32)Lcd_data->flow*10000; //˲ʱ - UintToBcd(dat, &uint2uchar); - for(j=0; j<4; j++) - Frame.Data[i++] = uint2uchar.c_value[j]; - Frame.Data[i++] = danwei_m3; - - dat = (_u32)Lcd_data->total_flow*100/LCD_MULTIPLE; //ۼ - UintToBcd(dat, &uint2uchar); - for(j=0; j<4; j++) - Frame.Data[i++] = uint2uchar.c_value[j]; - Frame.Data[i++] = danwei_m3; - - dat = (_u32)Lcd_data->temp1*100/LCD_MULTIPLE; //ˮ¶ - UintToBcd(dat, &uint2uchar); - for(j=1; j<4; j++) - Frame.Data[i++] = uint2uchar.c_value[j]; - - dat = (_u32)Lcd_data->temp2*100/LCD_MULTIPLE; //ˮ¶ - UintToBcd(dat, &uint2uchar); - for(j=1; j<4; j++) - Frame.Data[i++] = uint2uchar.c_value[j]; - - dat = (_u32)Lcd_data->total_time; //ۼƹʱ - UintToBcd(dat, &uint2uchar); - for(j=1; j<4; j++) - Frame.Data[i++] = uint2uchar.c_value[j]; - - //ʵʱʱ - dat = (_u32)Date_and_Time->Day*1000000 + (_u32)Date_and_Time->Hour*10000 + (_u32)Date_and_Time->Minute*100 + (_u32)Date_and_Time->Second; - UintToBcd(dat, &uint2uchar); - for(j=0; j<4; j++) - Frame.Data[i++] = uint2uchar.c_value[j]; - dat = (_u32)Date_and_Time->Year*100 + (_u32)Date_and_Time->Month; - UintToBcd(dat, &uint2uchar); - for(j=0; j<3; j++) - Frame.Data[i++] = uint2uchar.c_value[j]; - - dat = (_u32)ST; //״̬ST - UintToBcd(dat, &uint2uchar); - Frame.Data[i++] = uint2uchar.c_value[0]; - Frame.Data[i++] = uint2uchar.c_value[1]; - - return 0; -} - -_u32 read2() //ϼ½ -{ - _u32 j; - j = (_u32)Frame.DI1; - Frame.DataLen = 0x08; -#if 0 - Flash_Read_Info(); - _u32 i; - for(i=0; i<256; i++) - { - TXBUF0 = Array[i]; - while((U0TCTL & TXEPT) == 0) ; - } -#endif - - _u32 offset; - _u32 dat; - union uint_uchar uint2uchar; - offset = ((Last_month_num-(j-32))%18)*12+4; //0~216 - dat = *(_u32 *)(INFO_FLASH_START + offset);//total heat - UintToBcd(dat, &uint2uchar); - for(j=0; j<4; j++) - Frame.Data[j] = uint2uchar.c_value[j]; - Frame.Data[4] = danwei_KWh; - - return 0; -} - -_u32 read3() -{ - switch(Frame.DI1){ - case 0x02: //۸ - Frame.DataLen = 0x12; - break; - case 0x03: // - Frame.DataLen = 0x04; - break; - case 0x04: // - Frame.DataLen = 0x04; - break; - case 0x05: // - Frame.DataLen = 0x12; - break; - default: - return ERROR; - break; - } - - return 0; -} - -_u32 read4() -{ - Frame.DataLen = 0x04; - - return 0; -} - -_u32 read5() -{ - Frame.DataLen = 0x03; - - return 0; -} - -_u32 write1() -{ - switch(Frame.DI1){ - case 0x10: - Frame.DataLen = 0x05; - break; - case 0x11: - Frame.DataLen = 0x03; - break; - case 0x12: - Frame.DataLen = 0x03; - break; - case 0x13: - Frame.DataLen = 0x08; - break; - case 0x14: - Frame.DataLen = 0x04; - break; - case 0x15: - Frame.DataLen = 0x03; - break; - case 0x17: - Frame.DataLen = 0x05; - break; - case 0x19: - Frame.DataLen = 0x03; - break; - default: - return ERROR; - break; - } - - return 0; -} - -_u32 write2() -{ - Frame.DataLen = 0x03; - - return 0; -} - -_u32 write3() -{ - Frame.DataLen = 0x05; - - return 0; -} - -_u32 write4() -{ - switch(Frame.DI1){ - case 0x12: - Frame.DataLen = 0x05; - break; - case 0x14: - Frame.DataLen = 0x05; - break; - case 0x16: - Frame.DataLen = 0x05; - break; - default: - return ERROR; - break; - } - - return 0; -} - -void do_err() -{ - _u32 dat; - union uint_uchar uint2uchar; - - Frame.CtrlCode |= 0x40; - Frame.DataLen = 0x03; - Frame.DI0 = Frame.SER; - UintToBcd(ST, &uint2uchar); - Frame.DI1 = uint2uchar.c_value[0]; - Frame.SER = uint2uchar.c_value[1]; -} - -//_u32 do_frame() //λӦģʽЭн -_u32 do_frame(struct Date_Time *Date_and_Time, struct Data *Lcd_data) -{ - _u32 err; - _u32 i,j,head,tail; - /*----------------ʼ֡ʽ----------------*/ - - Frame.CheckSum = 0x0; - for(i=0;frame_rx[i] == 0xfe;i++); - head = i; - j = head; - - Frame.HeadCode = frame_rx[head++]; - Frame.TypeCode = frame_rx[head++]; - for(i=0;i<7;i++) - Frame.Address[i] = frame_rx[head++]; - Frame.CtrlCode = frame_rx[head++]; - Frame.DataLen = frame_rx[head++]; -#if CJT188_DI_SEQ - Frame.DI0 = frame_rx[head++]; - Frame.DI1 = frame_rx[head++]; -#else - Frame.DI1 = frame_rx[head++]; - Frame.DI0 = frame_rx[head++]; -#endif - Frame.SER = frame_rx[head++]; - for(i=0;i<((_u32)Frame.DataLen-3);i++) - Frame.Data[i] = frame_rx[head++]; - while(j < head){ - Frame.CheckSum += frame_rx[j]; - Frame.CheckSum %= 256; - j++; - } - if(Frame.CheckSum != frame_rx[j]) { - return 1; - } - tail = j+1; - Frame.TailCode = frame_rx[tail]; - /*----------------֡ʽ----------------*/ - - /*------------------------ݿͽ--------------------------*/ - switch(Frame.CtrlCode){ - case 0x01: //read data - if((Frame.DI0==0x90)&&(Frame.DI1==0x1f)) err = read1(Date_and_Time, Lcd_data); - else if(Frame.DI0==0xd1) err = read2(); - else if(Frame.DI0==0x81) err = read3(); - break; - case 0x09: //Կ汾 - if((Frame.DI0==0x81)&&(Frame.DI1==0x06)) err = read4(); - break; - case 0x03: //ַ - if((Frame.DI0==0x81)&&(Frame.DI1==0x0a)) err = read5(); - break; - case 0x04: //д - if(Frame.DI0==0xa0) err = write1(); - break; - case 0x15: //дַ - if((Frame.DI0==0xa0)&&(Frame.DI1==0x18)) err = write2(); - break; - case 0x16: //дͬ - if((Frame.DI0==0xa0)&&(Frame.DI1==0x16)) err = write3(); - break; - case CJT188_DEF_READ: // - - break; - case CJT188_DEF_WRITE: //д - if(Frame.DI0==0xb0) err = write4(); - break; - default: - err = 2; - break; - } - /*------------------------ͽ--------------------------*/ - Frame.CtrlCode |= 0x80; - if(err) do_err(); - Answer(); - - return 0; -} - -void Frame_exe(struct Date_Time *Date_and_Time, struct Data *Lcd_data) -{ - _u32 err; - err = do_frame(&Date_and_Time, &Lcd_data); - if(err==0) - { - TX_IndexW = 0; - Uart1_TxData = 0xfe; - //IFG1 |= UTXIFG0; - } - else if(err==1) - { - //TXBUF0 = 0xdd; - //while((U0TCTL & TXEPT) == 0) ; - } - else if(err==2) - { - //TXBUF0 = 0xee; - //while((U0TCTL & TXEPT) == 0) ; - } -} -#endif diff --git a/resources/soc/simu/soft/func/source/isp.c b/resources/soc/simu/soft/func/source/isp.c deleted file mode 100644 index 41d856c..0000000 --- a/resources/soc/simu/soft/func/source/isp.c +++ /dev/null @@ -1,279 +0,0 @@ - -#include "../config.h" - -#if PRINT -void tgt_putchar(_u8 chr) -{ - while(!(Uart0_LSR & 0x20)) ; - Uart0_TxData = chr; -} - -_u8 tgt_getchar() -{ - _u8 chr; - while(!(Uart0_LSR & 0x1)) ; - chr = Uart0_RxData ; - - return chr; -} - -_u8 tgt_testchar() -{ - _u8 chr; - chr = (Uart0_LSR & 0x1); - - return chr; -} -#endif - -_u32 now() -{ - _u32 count; - count = PMU_Count; - count &= COUNT_MASK; - - return count; -} - -#if (ISP || MONTHDATA_MODULE) -#if (LS1D_FPGA) -void spiflash_erase(_u32 addr_start, _u32 addr_end) -{ - __asm__ volatile( - "move $15,$31;\n" -/**spi_flash init**/ - "li $8,0xbfe70000;\n" - "li $9,0xc0;\n" - "sb $9,1($8);\n" - "li $9,0x10;\n" - "sb $9,4($8);\n" - "li $9,0x5;\n" - "sb $9,3($8);\n" - "li $9,0x1;\n" - "sb $9,6($8);\n" - "li $9,0x50;\n" - "sb $9,0($8);\n" -/**spi_flash code_program**/ - "li $14, 0x1000;\n" - "1:li $9,0x11;\n" - "sb $9,5($8);\n" /*high cs*/ - "bal 102f;\n" /*wait sr */ - "nop;\n" - "li $9,6;\n" /* write enable */ - "bal 101f;\n" - "nop;\n" - "li $9,0x11;\n" /*high cs*/ - "sb $9,5($8);\n" - "li $9,1;\n" /* write status*/ - "bal 101f;\n" - "nop;\n" - "li $9,0;\n" /* write 0*/ - "bal 103f;\n" - "nop;\n" - "li $9,0x11;\n" /*high cs*/ - "sb $9,5($8);\n" - "bal 102f;\n" /*wait sr */ - "nop;\n" - "li $9,6;\n" /* write enable */ - "bal 101f;\n" - "nop;\n" - "li $9,0x11;\n" /*high cs*/ - "sb $9,5($8);\n" - "li $9,0x20;\n" /*bulk erase, 4kB*/ - "bal 101f;\n" - "nop;\n" - "srl $9,$4,16;\n" /*addr*/ - "bal 103f;\n" - "nop;\n" - "srl $9,$4,8;\n" - "bal 103f;\n" - "nop;\n" - "move $9,$4;\n" - "bal 103f;\n" - "nop;\n" - "li $9,0x11;\n" /*high cs*/ - "sb $9,5($8);\n" - "bal 102f;\n" /*wait sr*/ - "nop;" - "addu $4,$14;\n" - "slt $9,$5,$4;\n" - "beqz $9,1b;\n" - "nop;\n" - "3:\n" - "li $9,0x11;\n" - "sb $9,5($8);\n" /*high cs*/ - - "li $9,0x11;\n" - "sb $9,4($8);\n" - "b 999f;\n" - "nop;\n" - - "101:li $11,1;\n" - "sb $11,5($8);\n" /*enable and low cs*/ - "103:sb $9,2($8);\n" - "1:lb $9,1($8);\n" - "andi $9,1;\n" - "bnez $9,1b;\n" - "nop;\n" - "lb $9,2($8);\n" - "jr $31;\n" - "nop\n;" - "102:move $10,$31;\n" - "1:li $9,5;\n" /*wait read sr*/ - "bal 101b;\n" - "nop;\n" - "andi $9,1;\n" - "bnez $9,1b;\n" /*can continue read sr,write to gen clock*/ - "nop;\n" - "li $9,0x11;\n" /*high cs*/ - "sb $9,5($8);\n" - "jr $10;\n" - "nop;\n" - - "999:move $31,$15;\n" - :::"$8","$9","$10","$11","$4","$5","$14","$15" - ); -} -void spiflash_write(_u32 addr_w, _u32 addr_r, _u32 length) -{ - __asm__ volatile( - "move $15,$31;\n" -/**spi_flash init**/ - "li $8,0xbfe70000;\n" - "li $9,0xc0;\n" - "sb $9,1($8);\n" - "li $9,0x10;\n" - "sb $9,4($8);\n" - "li $9,0x5;\n" - "sb $9,3($8);\n" - "li $9,0x1;\n" - "sb $9,6($8);\n" - "li $9,0x50;\n" - "sb $9,0($8);\n" -/**spi_flash code_program**/ - "li $9,0x11;\n" - "sb $9,5($8);\n" /*high cs*/ - "bal 102f;\n" /*wait sr */ - "nop;\n" - "li $9,6;\n" /* write enable */ - "bal 101f;\n" - "nop;\n" - "li $9,0x11;\n" /*high cs*/ - "sb $9,5($8);\n" - "li $9,1;\n" /* write status*/ - "bal 101f;\n" - "nop;\n" - "li $9,0;\n" /* write 0*/ - "bal 103f;\n" - "nop;\n" - "1:li $9,0x11;\n" /*high cs*/ - "sb $9,5($8);\n" - "bal 102f;\n" /*wait sr */ - "nop;\n" - "li $9,6;\n" /* write enable */ - "bal 101f;\n" - "nop;\n" - "li $9,0x11;\n" /*high cs*/ - "sb $9,5($8);\n" - "bal 102f;\n" /*wait sr*/ - "nop;" - "li $9,2;\n" /*write sector*/ - "bal 101f;\n" - "nop;\n" - "srl $9,$4,16;\n" /*addr*/ - "bal 103f;\n" - "nop;\n" - "srl $9,$4,8;\n" - "bal 103f;\n" - "nop;\n" - "move $9,$4;\n" - "bal 103f;\n" - "nop;\n" - "2:lb $9,0($5);\n" /*write 1 data*/ - "bal 103f;\n" - "nop;\n" - "addiu $4,1;\n" - "addiu $5,1;\n" - "addiu $6,-1;\n" - "beqz $6,3f;\n" - "nop;\n" - "b 1b;\n" - "nop;\n" - "3:\n" - "li $9,0x11;\n" - "sb $9,5($8);\n" /*high cs*/ - - "li $9,0x11;\n" - "sb $9,4($8);\n" - "b 999f;\n" - "nop;\n" - - "101:li $11,1;\n" - "sb $11,5($8);\n" /*enable and low cs*/ - "103:sb $9,2($8);\n" - "1:lb $9,1($8);\n" - "andi $9,1;\n" - "bnez $9,1b;\n" - "nop;\n" - "lb $9,2($8);\n" - "jr $31;\n" - "nop\n;" - "102:move $10,$31;\n" - "1:li $9,5;\n" /*wait read sr*/ - "bal 101b;\n" - "nop;\n" - "andi $9,1;\n" - "bnez $9,1b;\n" /*can continue read sr,write to gen clock*/ - "nop;\n" - "li $9,0x11;\n" /*high cs*/ - "sb $9,5($8);\n" - "jr $10;\n" - "nop;\n" - - "999:move $31,$15;\n" - :::"$8","$9","$10","$11","$4","$5","$6","$15" - ); -} -#else -//²Á³ýaddrËùÔڵĶΠ-void Flash_Erase(_u32 addr) -{ - FLASH_CMD_REG = FLASH_ERASE_CMD | (addr & FLASH_ADDR_MASK) ; - -} - -_u32 Flash_Write(_u32 addr, _u32 *data, _u32 num) -{ - FLASH_CMD_REG = FLASH_PAGE_LATCH_CLEAR; - /*wait interrupt ? Should I disable other int??????*/ - //debug("Page_latch is clean now...\n") - - _u32 flash_block_mask = FLASH_BLOCK_SIZE - 1; - _u32 *page_data = (_u32 *)(addr & ~flash_block_mask) ; - _u32 *old_data = (_u32 *)(addr & ~flash_block_mask) ; - _u32 i, j, offset; - - j = 0; - offset = ((addr & flash_block_mask)>>2); - for(i=0; i<(FLASH_BLOCK_SIZE/4); i++) - { - if( (offset <= i) && (j < num) ) - page_data[i] = data[j++]; - else - page_data[i] = old_data[i]; - } - - Flash_Erase(addr); - /*wait interrupt ? */ - //debug("Flash page is clean now...\n") - - FLASH_CMD_REG = FLASH_WRITE_CMD | (addr & FLASH_ADDR_MASK) ; - /*wait interrupt ? */ - //debug("Flash page write is finish...\n") - - return 0; -} -#endif -#endif - - diff --git a/resources/soc/simu/soft/func/source/key.c b/resources/soc/simu/soft/func/source/key.c deleted file mode 100644 index 4b6c0e9..0000000 --- a/resources/soc/simu/soft/func/source/key.c +++ /dev/null @@ -1,77 +0,0 @@ -/********************************************************************************************************************************************************************** - This file uses key to jump between diffrence cases. -**********************************************************************************************************************************************************************/ - -#include "../config.h" - -#if KEY_MODULE -static void Auto_jump(struct Data *Lcd_data) -{ - wait[1] = 0; - main_flag &= ~A3_delay; - if(Lcd_data->lcdmode/10 == A4) { - main_flag |= wait_2hour; - } - else { - if(Lcd_data->lcdmode/10 == A3){ - wait[2] = 0; - main_flag |= A3_delay; - } - main_flag |= wait_1min; - } - main_flag |= lcd_bit; -} - -static void Key_short(struct Data *Lcd_data) -{ - if(Lcd_data->lcdmode/10 == A4) Lcd_data->lcdmode = (Lcd_data->lcdmode%10 + 1)%7 + (Lcd_data->lcdmode/10)*10; - if(Lcd_data->lcdmode/10 == A1) Lcd_data->lcdmode = (Lcd_data->lcdmode%10 + 1)%9 + (Lcd_data->lcdmode/10)*10; - if(Lcd_data->lcdmode/10 == A2) Lcd_data->lcdmode = (Lcd_data->lcdmode%10 + 1)%7 + (Lcd_data->lcdmode/10)*10; - if(Lcd_data->lcdmode/10 == A3){ - if(Lcd_data->lcdmode == A3_0){ - Lcd_data->lcdmode = A3_1; - Lcd_data->history = Last_month_num; - } - else { - Lcd_data->lcdmode = A3_1; - Lcd_data->history += 1; - Lcd_data->history %= 18; - } - } - Auto_jump(Lcd_data); -} - -static void Key_long(struct Data *Lcd_data) -{ - /**/ - if(Lcd_data->lcdmode == A1_6) { - Lcd_data->lcdmode = A4_0; - PMU[0] = 0x4; //cruise delay 0.25s,2s - main_flag &= ~wait_1min; - } - else { - if(Lcd_data->lcdmode/10 == A4) { - Lcd_data->lcdmode = A1_0; - PMU[0] = 0x7004; //cruise delay 2s,8s - main_flag &= ~wait_2hour; - } - else if(Lcd_data->lcdmode/10 == A1) Lcd_data->lcdmode = A2_0; - else if(Lcd_data->lcdmode/10 == A2) Lcd_data->lcdmode = A3_0; - else if(Lcd_data->lcdmode/10 == A3) Lcd_data->lcdmode = A1_0; - } - Auto_jump(Lcd_data); -} - -void Key(struct Data *Lcd_data) -{ - if(main_flag & long_key) - { - main_flag &= ~long_key; - Key_long(Lcd_data); - } - else - { - Key_short(Lcd_data); - } -} -#endif diff --git a/resources/soc/simu/soft/func/source/lcd.c b/resources/soc/simu/soft/func/source/lcd.c deleted file mode 100644 index 3db28d7..0000000 --- a/resources/soc/simu/soft/func/source/lcd.c +++ /dev/null @@ -1,414 +0,0 @@ -#include "../config.h" - -/****************************************************************************** -lcd module - 1.LcdClear - 2.LcdPrintAll - 3.LcdLowV - 4.LcdDisplay - - Notice: Some variable of Lcd_data = real_value * LCD_MULTIPLE -******************************************************************************/ - -#if LCD_MODULE -//clear lcd_buf -static void LcdClear(_u8 *LCD_BUF) -{ - _u32 i ; - - for(i=0;i>4)]; - if(!(minus++)) LCD_BUF[0] = word[5]; //'F', overflow -step1: - if(!(minus++)) LCD_BUF[0] = MINUS; - LCD_BUF[1] = number[(bcd_buf[3])&0xf]; -step2: - if(!(minus++)) LCD_BUF[1] = MINUS; - LCD_BUF[2] = number[(bcd_buf[2]>>4)]; -step3: - if(!(minus++)) LCD_BUF[2] = MINUS; - LCD_BUF[3] = number[(bcd_buf[2])&0xf]; -step4: - if(!(minus++)) LCD_BUF[3] = MINUS; - LCD_BUF[4] = number[(bcd_buf[1]>>4)]; -step5: - if(!(minus++)) LCD_BUF[4] = MINUS; - LCD_BUF[5] = number[(bcd_buf[1])&0xf]; -step6: - if(!(minus++)) LCD_BUF[5] = MINUS; - LCD_BUF[6] = number[(bcd_buf[0]>>4)]; -step7: - if(!(minus++)) LCD_BUF[6] = MINUS; - LCD_BUF[7] = number[(bcd_buf[0])&0xf]; - - if(decimal_length==5) LCD_BUF[2] |= 0x80; //print p1 - if(decimal_length==4) LCD_BUF[3] |= 0x80; //print p2 - if(decimal_length==3) LCD_BUF[4] |= 0x80; //print p3 - if(decimal_length==2) LCD_BUF[5] |= 0x80; //print p4 - if(decimal_length==1) LCD_BUF[6] |= 0x80; //print p5 -} - -void LcdDisplay(struct Date_Time *Date_and_Time, struct Data *Lcd_data) -{ - _u8 LCD_BUF[LCD_LENGTH]; - LcdClear(&LCD_BUF) ; - -#if LCD_TEST - //LcdTest1(); - LcdTest2(&LCD_BUF); -#else - //printf("lcdmode = %d\n", Lcd_data->lcdmode); - - _u8 bcd_buf[4]; - _u32 i; - _u32 minus = 1; - volatile _u32 display; - - i = Lcd_data->lcdmode/10; - if(i == A1){ //-------------------------A1----- - switch(Lcd_data->lcdmode){ - case A1_0: - LCD_BUF[0] = word[0]; //'A' - LCD_BUF[1] = number[1]; //'1' - break; - case A1_1: - if(Lcd_data->total_heat < 0) minus = 0; - display = minus?(_u32)(Lcd_data->total_heat):(_u32)(0 - Lcd_data->total_heat); - UintToBcd((display/100000), &bcd_buf); - LcdBufWrite(&LCD_BUF, &bcd_buf, 0, minus); - LCD_BUF[8] = A1_1_0; - LCD_BUF[9] = A1_1_1; //KW*h - break; - case A1_2: - if(Lcd_data->heat < 0) minus = 0; - display = minus?(_u32)(Lcd_data->heat):(_u32)(0 - Lcd_data->heat); - UintToBcd((display/10000), &bcd_buf); - LcdBufWrite(&LCD_BUF, &bcd_buf, 1, minus); - LCD_BUF[8] = A1_2_0; - LCD_BUF[9] = A1_2_1; - break; - case A1_3: - if(Lcd_data->temp1 < 0) minus = 0; - display = minus?(_u32)(Lcd_data->temp1):(_u32)(0 - Lcd_data->temp1); - UintToBcd((display), &bcd_buf); - LcdBufWrite(&LCD_BUF, &bcd_buf, 5, minus); - LCD_BUF[4] = 0x0; - - if(Lcd_data->temp2 < 0) minus = 0; - display = minus?(_u32)(Lcd_data->temp2):(_u32)(0 - Lcd_data->temp2); - UintToBcd((display/10000), &bcd_buf); - LcdBufWrite(&LCD_BUF, &bcd_buf, 1, minus); - - LCD_BUF[8] = A1_3_0; - LCD_BUF[9] = A1_3_1; - break; - case A1_4: - if(Lcd_data->temp0 < 0) minus = 0; - display = minus?(_u32)(Lcd_data->temp0):(_u32)(0 - Lcd_data->temp0); - UintToBcd((display/1000), &bcd_buf); - LcdBufWrite(&LCD_BUF, &bcd_buf, 2, minus); - LCD_BUF[8] = A1_4_0; - LCD_BUF[9] = A1_4_1; - break; - case A1_5: - if(Lcd_data->total_flow < 0) minus = 0; - display = minus?(_u32)(Lcd_data->total_flow):(_u32)(0 - Lcd_data->total_flow); - UintToBcd((display/1000), &bcd_buf); - LcdBufWrite(&LCD_BUF, &bcd_buf, 2, minus); - LCD_BUF[8] = A1_5_0; - LCD_BUF[9] = A1_5_1; - break; - case A1_6: - if(Lcd_data->flow < 0) minus = 0; - display = minus?(_u32)(Lcd_data->flow):(_u32)(0 - Lcd_data->flow); - UintToBcd((display/100), &bcd_buf); - LcdBufWrite(&LCD_BUF, &bcd_buf, 3, minus); - LCD_BUF[8] = A1_6_0; - LCD_BUF[9] = A1_6_1; - break; - case A1_7: - display = Lcd_data->total_time; - UintToBcd(display, &bcd_buf); - LcdBufWrite(&LCD_BUF, &bcd_buf, 0, minus); - LCD_BUF[8] = A1_7_0; - LCD_BUF[9] = A1_7_1; - break; - case A1_8: - display = Lcd_data->alarm_time; - UintToBcd(display, &bcd_buf); - LcdBufWrite(&LCD_BUF, &bcd_buf, 0, minus); - LCD_BUF[8] = A1_8_0; - LCD_BUF[9] = A1_8_1; - break; - } - } - else if(i == A2){ //--------------------A2----- - switch(Lcd_data->lcdmode){ - case A2_0: - LCD_BUF[0] = word[0]; //'A' - LCD_BUF[1] = number[2]; //'2' - break; - case A2_1: - Lcd_data->date = Date_and_Time->Year*10000 + Date_and_Time->Month*100 + Date_and_Time->Day; //ע⣬Ҫתֹ - display = Lcd_data->date; - UintToBcd(display, &bcd_buf); - LcdBufWrite(&LCD_BUF, &bcd_buf, 0, minus); - LCD_BUF[3] |= 0x80; - LCD_BUF[5] |= 0x80; - LCD_BUF[8] = A2_1_0; //ʱ - LCD_BUF[9] = A2_1_1; // - break; - case A2_2: - Lcd_data->time = Date_and_Time->Hour*1000000 + Date_and_Time->Minute*1000 + Date_and_Time->Second; //ע⣬Ҫתֹ - display = Lcd_data->time; - UintToBcd(display, &bcd_buf); - LcdBufWrite(&LCD_BUF, &bcd_buf, 0, minus); - LCD_BUF[2] = 0x02; - LCD_BUF[5] = 0x02; - LCD_BUF[8] = A2_2_0; //ʱ ʱ - LCD_BUF[9] = A2_2_1; // - break; - case A2_3: //û - display = Lcd_data->usercode; - UintToBcd(display, &bcd_buf); - LcdBufWrite(&LCD_BUF, &bcd_buf, 0, minus); - break; - case A2_4: //汾 - display = (_u32)(Lcd_data->version*10); - UintToBcd(display, &bcd_buf); - LcdBufWrite(&LCD_BUF, &bcd_buf, 1, minus); - break; - case A2_5: //͵ѹ - LcdLowV(&LCD_BUF); - break; - case A2_6: /*ȫ*/ - LcdPrintAll(&LCD_BUF); - break; - } - } - else if(i == A3){ //--------------------A3----- - switch(Lcd_data->lcdmode){ - case A3_0: - LCD_BUF[0] = word[0]; //'A' - LCD_BUF[1] = number[3]; //'3' - break; - case A3_1: - display = *(_u32 *)(INFO_FLASH_START + Lcd_data->history*12); - UintToBcd(display, &bcd_buf); - LcdBufWrite(&LCD_BUF, &bcd_buf, 0, minus); - LCD_BUF[4] = 0x02; - LCD_BUF[7] = 0x0; - LCD_BUF[8] = A3_1_0; //ʱ - LCD_BUF[9] = A3_1_1; // - break; - case A3_2: - display = *(_u32 *)(INFO_FLASH_START + Lcd_data->history*12+8); - UintToBcd((display), &bcd_buf); - LcdBufWrite(&LCD_BUF, &bcd_buf, 2, minus); - LCD_BUF[8] = A3_2_0; //ۻ - LCD_BUF[9] = A3_2_1; //m3 - break; - case A3_3: - display = *(_u32 *)(INFO_FLASH_START + Lcd_data->history*12+4); - UintToBcd((display), &bcd_buf); - LcdBufWrite(&LCD_BUF, &bcd_buf, 2, minus); - LCD_BUF[8] = A3_3_0; //ۼ - LCD_BUF[9] = A3_3_1; //KW*h - break; - } - } - else if(i == A4){ //--------------------A4----- - switch(Lcd_data->lcdmode){ - case A4_0: - LCD_BUF[0] = word[0]; //'A' - LCD_BUF[1] = number[4]; //'4' - break; - case A4_1: - if(Lcd_data->flow < 0) minus = 0; - display = minus?(_u32)(Lcd_data->flow):(_u32)(0 - Lcd_data->flow); - UintToBcd((display/100), &bcd_buf); - LcdBufWrite(&LCD_BUF, &bcd_buf, 3, minus); - LCD_BUF[8] = A4_1_0; - LCD_BUF[9] = A4_1_1; - break; - case A4_2: - if(Lcd_data->total_flow < 0) minus = 0; - display = minus?(_u32)(Lcd_data->total_flow):(_u32)(0 - Lcd_data->total_flow); - UintToBcd((display), &bcd_buf); - LcdBufWrite(&LCD_BUF, &bcd_buf, 5, minus); - LCD_BUF[8] = A4_2_0; - LCD_BUF[9] = A4_2_1; - break; - case A4_3: - if(Lcd_data->heat < 0) minus = 0; - display = minus?(_u32)(Lcd_data->heat):(_u32)(0 - Lcd_data->heat); - UintToBcd((display/10), &bcd_buf); - LcdBufWrite(&LCD_BUF, &bcd_buf, 4, minus); - LCD_BUF[8] = A4_3_0; - LCD_BUF[9] = A4_3_1; - break; - case A4_4: - if(Lcd_data->total_heat < 0) minus = 0; - display = minus?(_u32)(Lcd_data->total_heat):(_u32)(0 - Lcd_data->total_heat); - UintToBcd((display/10), &bcd_buf); - LcdBufWrite(&LCD_BUF, &bcd_buf, 4, minus); - LCD_BUF[8] = A4_4_0; - LCD_BUF[9] = A4_4_1; //KW*h - break; - case A4_5: - if(Lcd_data->temp1 < 0) minus = 0; - display = minus?(_u32)(Lcd_data->temp1):(_u32)(0 - Lcd_data->temp1); - UintToBcd((display*10), &bcd_buf); - LcdBufWrite(&LCD_BUF, &bcd_buf, 0, minus); - - if(Lcd_data->temp2 < 0) minus = 0; - display = minus?(_u32)(Lcd_data->temp2):(_u32)(0 - Lcd_data->temp2); - UintToBcd((display/1000), &bcd_buf); - LcdBufWrite(&LCD_BUF, &bcd_buf, 0, minus); - - LCD_BUF[8] = A4_5_0; - LCD_BUF[9] = A4_5_1; - break; - case A4_6: - if(Lcd_data->temp0 < 0) minus = 0; - display = minus?(_u32)(Lcd_data->temp0):(_u32)(0 - Lcd_data->temp0); - UintToBcd((display/1000), &bcd_buf); - LcdBufWrite(&LCD_BUF, &bcd_buf, 2, minus); - LCD_BUF[8] = A4_6_0; - LCD_BUF[9] = A4_6_1; - break; - } - } - - if(main_flag & lowV_flag) LcdLowV(&LCD_BUF); - - WriteLcdRegs(&LCD_BUF); -#endif -} - -#endif diff --git a/resources/soc/simu/soft/func/source/temp_flow.c b/resources/soc/simu/soft/func/source/temp_flow.c deleted file mode 100644 index 88bee1f..0000000 --- a/resources/soc/simu/soft/func/source/temp_flow.c +++ /dev/null @@ -1,416 +0,0 @@ -/********************************************************************************************************************************************************************** - This file uses TDC module to caculate temperature and waterflow. -**********************************************************************************************************************************************************************/ - -#include "../config.h" - -#if (TDC_TEMP_MODULE|TDC_FLOW_MODULE) -//#undef PRINT - -void InitTdc(void) -{ -#if (TEMP_TEST|FLOW_TEST) - //if PMU[0]&0x10000, the cruise delay will divide 4. - PMU[0] = 0x4; //cruise delay 0.25s,2s -#else - PMU[0] = 0x7004; //cruise delay 2s,8s -#endif - Sonar[0] = 0xa210; //4M div 4, 96mA, Fireup, stop2 - Sonar[1] = 0xf8840081; //use Stdc, measure 2 - Sonar[2] = 0xc0300000; //detect first wave - Sonar[3] = 0x8004000; //set delay, detect first wave - Sonar[4] = 0x4000500; //set delay, from first wave to the first stop - Thsens[0] = 0xf7; -#if TDC_TEMP_MODULE - PMU[1] |= 0x80; //cruise mode, temp -#endif -#if TDC_FLOW_MODULE - PMU[1] |= 0x40; //cruise mode, flow -#endif - -#if (TEMP_TEST|FLOW_TEST) - printf("Tdc initted...\n"); -#endif -} - -static _fp32 Time_Caculate(_u32 *result, struct Data *Lcd_data, _u32 start, _u32 stop_num) -{ - _u32 i; -#if FLOW_TEST - //printf("Time_Caculate...\n"); -#endif - - _fp32 average_time; - short a[stop_num],b[stop_num]; - short sum_a, sum_b; - for(i=0;i0xd5) -{ - printf("result_low[%d] = 0x%x\n", i, b[i]); //0xc7==199 - printf("-------------------------------------------------------------------------------------------------------------------------------------------\n"); -} -#endif - } - - sum_a = 0; - sum_b = 0; - for(i=1;iauto_caculate; //ns, 10-9(s) - - return average_time; -} - -static _fp32 GetUltrasonicVelocity(_fp32 temp) -{ - _fp32 V; - V = 1402336 + - 5033.58f*temp - - 5795.06f*temp*temp/100 + - 3316.36f*temp*temp*temp/10000 - - 1452.62f*temp*temp*temp*temp/1000000 + - 3044.9f*temp*temp*temp*temp*temp/1000000000; - -//printf("UltrasonicVelocity: %d\t", (unsigned int)(V)); - return V/1000; //m/s -} - -void Flow_Caculate(_fp32 delta_time, _fp32 duration, struct Data *Lcd_data) -{ - /*delta_time***********ns*/ -#if (FLOW_TEST&TEMP_TEST) - _fp32 UltrasonicVelocity; - UltrasonicVelocity = GetUltrasonicVelocity(Lcd_data->temp1/LCD_MULTIPLE); - - _fp32 flow_Velocity; - //flow_Velocity = (delta_time/1000000000)*UltrasonicVelocity*UltrasonicVelocity/(2*SOUND_PATH*COS_RESULT); - flow_Velocity = delta_time*UltrasonicVelocity*UltrasonicVelocity/(2*SOUND_PATH*COS_RESULT*10000); //m/s, flow_Velocity*LCD_MULTIPLE - - Lcd_data->flow = CONST*K_COEFFICIENT*DIAMETER*DIAMETER*flow_Velocity*3600; //m3/h, Lcd_data->flow*LCD_MULTIPLE - Lcd_data->total_flow += Lcd_data->flow*duration/3600; //m3, Lcd_data->total_flow*LCD_MULTIPLE -#endif -} - -void Temp_Caculate(unsigned int *result, struct Data *Lcd_data, unsigned int num) -{ - int i; -#if TEMP_TEST - //printf("Temp_Caculate...\n"); -#endif - - short a[num],b[num]; - for(i=0;iauto_caculate-(b[5]-b[4]))*2/(_fp32)((a[3]-a[2]+a[1]-a[0])*Lcd_data->auto_caculate-(b[3]-b[2]+b[1]-b[0])) ; - r_output = (_fp32)((a[7]-a[6])*Lcd_data->auto_caculate-(b[7]-b[6]))*2/(_fp32)((a[3]-a[2]+a[1]-a[0])*Lcd_data->auto_caculate-(b[3]-b[2]+b[1]-b[0])) ; - - r_input += (_fp32)((a[11]-a[10])*Lcd_data->auto_caculate-(b[11]-b[10]))*2/(_fp32)((a[15]-a[14]+a[13]-a[12])*Lcd_data->auto_caculate-(b[15]-b[14]+a[13]-a[12])) ; - r_input /= 2; - r_output += (_fp32)((a[9]-a[8])*Lcd_data->auto_caculate-(b[9]-b[8]))*2/(_fp32)((a[15]-a[14]+a[13]-a[12])*Lcd_data->auto_caculate-(b[15]-b[14]+a[13]-a[12])) ; - r_output /=2; - } - else - { - r_input = (_fp32)((a[3]-a[2])*Lcd_data->auto_caculate-(b[3]-b[2]))*2/(_fp32)((a[7]-a[6]+a[5]-a[4])*Lcd_data->auto_caculate-(b[7]-b[6]+b[5]-b[4])) ; - r_output = (_fp32)((a[1]-a[0])*Lcd_data->auto_caculate-(b[1]-b[0]))*2/(_fp32)((a[7]-a[6]+a[5]-a[4])*Lcd_data->auto_caculate-(b[7]-b[6]+b[5]-b[4])) ; - - r_input += (_fp32)((a[13]-a[12])*Lcd_data->auto_caculate-(b[13]-b[12]))*2/(_fp32)((a[11]-a[10]+a[9]-a[8])*Lcd_data->auto_caculate-(b[11]-b[10]+a[9]-a[8])) ; - r_input /= 2; - r_output += (_fp32)((a[15]-a[14])*Lcd_data->auto_caculate-(b[15]-b[14]))*2/(_fp32)((a[11]-a[10]+a[9]-a[8])*Lcd_data->auto_caculate-(b[11]-b[10]+a[9]-a[8])) ; - r_output /=2; - } - - _fp32 temp_in, temp_out; - _fp32 tmp; - //ͨ¹ý¹«Ê½¼ÆË㣬Õâʱr_inputºÍr_outputÊÇζÈÖµ - //¹«Ê½À´Ô´ÓÚhttp://wenku.baidu.com/view/f9bab86a561252d380eb6e56.html ͨ¹ý²¬µç×è×èÖµÇóµÃζȵķ½·¨ - /******************************************************************************************************************************/ - /* IN */ - //tmp = r_input*1000; - //temp_in = 101.373e-5*tmp*tmp + 23.5515*tmp - 245649725e-4;//ÊäÈëR(µ¥Î»:0.01R) Êä³öT(µ¥Î»:0.01¶È) - //temp_in /= 100; - temp_in = 10.1373f*r_input*r_input + 235.515f*r_input - 245.649725f;//ÊäÈëR(µ¥Î»:0.01R) Êä³öT(µ¥Î»:0.01¶È) - - /* OUT */ - //tmp = r_output*1000; - //temp_out = 101.373e-5*tmp*tmp + 23.5515*tmp - 245649725e-4;//ÊäÈëR(µ¥Î»:0.01R) Êä³öT(µ¥Î»:0.01¶È) - //temp_out /= 100; - temp_out = 10.1373f*r_output*r_output + 235.515f*r_output - 245.649725f;//ÊäÈëR(µ¥Î»:0.01R) Êä³öT(µ¥Î»:0.01¶È) - /******************************************************************************************************************************/ - -#if TEMP_TEST - if((temp_in<0)||(temp_in>100)||(temp_out<0)||(temp_out>100)) - { - printf("---------------------------------------------------------------ERROR-----------------------------------------------------------------------\n"); - for(i=0;itemp1 = temp_in*LCD_MULTIPLE; - Lcd_data->temp2 = temp_out*LCD_MULTIPLE; - Lcd_data->temp0 = (temp_in - temp_out)*LCD_MULTIPLE; -} - -_fp32 get_density(_fp32 temp) -{ - _fp32 density; - density = 1000.2f - temp*0.42f; //kg/m3 - return density; -} - -_fp32 get_enthalpy(_fp32 temp) -{ - _fp32 enthalpy; - enthalpy = temp*4.18f + 0.85f; //kJ/kg - return enthalpy; -} - -void Heat_Caculate(_fp32 duration, struct Data *Lcd_data) -{ - _fp32 density; //ÃÜ¶È - _fp32 enthalpy_in, enthalpy_out; //<9f>áìÊÖµ - _fp32 heat_duration; - - density = get_density(Lcd_data->temp1/LCD_MULTIPLE); //µ±ÈÈÁ¿±í°²×°ÔÚ½øË®¹ÜÉÏ - enthalpy_in = get_enthalpy(Lcd_data->temp1/LCD_MULTIPLE); - enthalpy_out = get_enthalpy(Lcd_data->temp2/LCD_MULTIPLE); - - static _fp32 Last_total_flow; //ÉϴμÆËãʱµÄÀÛ»ýÁ÷Á¿ - heat_duration = (Lcd_data->total_flow - Last_total_flow)*density*(enthalpy_in - enthalpy_out); - Lcd_data->heat = heat_duration/(duration/3600); - Lcd_data->total_heat += heat_duration; - - Last_total_flow = Lcd_data->total_flow; - -} - -/********************************************************************************************************************************************************************** - When a res_valid interrupt comes, it will do - Firstly clear the interrupt bit; - Secondly read the result from the related regs; - Finally clear the result pointer. -***********************************************************************************************************************************************************************/ -_u32 res_ready(struct Data *Lcd_data) -{ -#if RES_TEST - printf("res_ready...\n"); -#endif - - _u32 ptr; - ptr = Sonar[8]; //0xbfeb4020 -#if RES_TEST - printf("ptr:0x%x\n", ptr); -#endif - _u32 current_ptr0,current_ptr1,last_ptr0,last_ptr1; - current_ptr0 = ptr&0xf; -#if RES_TEST - printf("current_ptr0:0x%x\n", current_ptr0); -#endif - current_ptr1 = (ptr>>4)&0xf; -#if RES_TEST - printf("current_ptr1:0x%x\n", current_ptr1); -#endif - last_ptr0 = (ptr>>8)&0xf; -#if RES_TEST - printf("last_ptr0:0x%x\n", last_ptr0); -#endif - last_ptr1 = (ptr>>12)&0xf; -#if RES_TEST - printf("last_ptr1:0x%x\n", last_ptr1); -#endif - - _u32 state, direction; - static _fp32 delta_time,time_up,time_down; - state = PMU[1]; - direction = Sonar[0]; - - _u32 result[16]; - _u32 i; - for(i=0; i<16; i++) - { - result[i] = Sonar[16+i]; //0xbfeb4040 Result[0] -#if RES_TEST - printf("result[%d] = 0x%x\n", i, result[i]); -#endif - } - PMU[15] = 0x80000000; //0xbfeb003c, clear regs, then you can start next measure - - /******************************************************************************************************************************/ - if((state&0xe00)==0x400) - { - _u32 sonar; - _u32 stop_num; - sonar = Sonar[1]; - stop_num = ((sonar>>21)&0x7); -#if FLOW_TEST - //printf("stop_num = %d\n", stop_num); -#endif - - if((sonar&0x100000)==0x0) - { - Lcd_data->auto_caculate = result[last_ptr0-1] - result[last_ptr0-2]; - } - - if((current_ptr0-last_ptr0) 1000.0) //if delta_time>1us - { - delta_time = 0; - printf("---------------------------------------------------------------ERROR-----------------------------------------------------------------------\n"); - for(i=0;i<12;i++) - { - printf("result[%d] = 0x%x\n", i,result[i]); - } - printf("-------------------------------------------------------------------------------------------------------------------------------------------\n"); - } -#endif - _fp32 tmp; -#if 0 //FLOW_TEST - if(delta_time<0) - { - tmp = 0 - delta_time; - printf("delta_time: -%d\n", (unsigned int)(tmp*1000)); - } - else - { - tmp = delta_time; - printf("delta_time: %d\n", (unsigned int)(tmp*1000)); - } -#endif - -#if 1 - static _u32 last_count=0; - static _u32 j=0; - static _fp32 delta[8]; - delta[j++] = delta_time; - if(j==8) - { - _fp32 average_delta_time; - average_delta_time = bubble_sort(&delta, j); - j=0; -#if FLOW_TEST - if(average_delta_time<0) - { - tmp = 0 - average_delta_time; - printf("------------------average_delta_time: -%d\n", (_u32)(tmp*1000)); - } - else - { - tmp = average_delta_time; - printf("------------------average_delta_time: %d\n", (_u32)(tmp*1000)); - } -#endif - _u32 count; - _fp32 duration; - count = *(volatile _u32 *)0xbfeb001c; - count &= COUNT_MASK; -#if PRINT -//printf("count: %d\n", count); -#endif - duration = (_fp32)( (count - last_count)%COUNT_COMPARE )/16; - last_count = count; - if(duration>16) return 2; //if duration > 16seconds, it should be an error. - - Flow_Caculate(average_delta_time, duration, Lcd_data); - Heat_Caculate(duration, Lcd_data); - } -#endif - - } - else if((state&0xe00)==0x600) - { - Temp_Caculate(&result, Lcd_data, 16); - } - - return 0; -} -#endif diff --git a/resources/soc/simu/soft/func/source/xmodem.c b/resources/soc/simu/soft/func/source/xmodem.c deleted file mode 100644 index 6370152..0000000 --- a/resources/soc/simu/soft/func/source/xmodem.c +++ /dev/null @@ -1,233 +0,0 @@ -/********************************************************************************************************************************************************************** - This file uses xmodem to download code, then writes it into flash. -**********************************************************************************************************************************************************************/ - -#include "../config.h" - -static _u16 _crc_xmodem_update (_u16 crc, _u8 data) -{ - int i; - crc = crc ^ ((_u16)data << 8); - for (i=0; i<8; i++) - { - if (crc & 0x8000) - crc = (crc << 1) ^ 0x1021; - else - crc <<= 1; - } - return crc; -} - -//Xmodenַ -#define XMODEM_NUL 0x00 -#define XMODEM_SOH 0x01 -#define XMODEM_STX 0x02 -#define XMODEM_EOT 0x04 -#define XMODEM_ACK 0x06 -#define XMODEM_NAK 0x15 -#define XMODEM_CAN 0x18 -#define XMODEM_EOF 0x1A -#define XMODEM_WAIT_CHAR 'C' - - -#define ST_WAIT_START 0x00 //ȴ -#define ST_BLOCK_OK 0x01 //һݿɹ -#define ST_BLOCK_FAIL 0x02 //һݿʧ -#define ST_OK 0x03 // - -#if LS1D_FPGA -static int testchar(unsigned int timeout) -{ - int total, start; - start = now(); - - while(1) - { - if(tgt_testchar()) return 100; - if( (now()-start) > timeout ) break; - } - - return 0; -} -#else -static int testchar(unsigned int timeout) -{ - int total, start; - //start = now(); - - _u32 i,j; - for(i=1000;i>0;i--) - for(j=500;j>0;j--) - //while(1) - { - if(tgt_testchar()) return 100; - //if( ((now()-start)%COUNT_COMPARE) > timeout ) break; - } - - return 0; -} -#endif -static int get_data(unsigned char *ptr,unsigned int len,unsigned int timeout) -{ - int i=0; - while(i0) - ptr[i++] = tgt_getchar(); - else break; //It doesn't receive data in 1 second. - } - - return i; -} -//CRC16 -static unsigned int calcrc(unsigned char *ptr, unsigned int count, _u8 crc_mode) -{ - _u16 crc = 0; - while (count--) - { - if(crc_mode) - crc = _crc_xmodem_update(crc,*ptr++); - else - { - crc += *ptr++ ; - crc &= 0xff; - } - } - - return crc; -} - -static int xmodem_transfer(_u32 base) -{ - unsigned int i; - _u16 crc; - unsigned int filesize=0; - unsigned char BlockCount=1; //ݿۼ(8λ뿼) - _u8 crc_mode = 1; - _u8 chr; -#if LS1D_FPGA - _u32 addr_w = base; - _u32 length = 128; -#endif - unsigned char STATUS; //״̬ - STATUS = ST_WAIT_START; //='d''D',XMODEM - while(1) - { - chr = crc_mode?XMODEM_WAIT_CHAR:XMODEM_NAK ; - tgt_putchar(chr); - if(testchar(80)>0)break; //5 seconds timeout - crc_mode += 1; - crc_mode %= 2; - } //send 'c' first, if there is no respond, then send NAK. - - struct str_XMODEM strXMODEM; //XMODEMĽݽṹ - while(STATUS!=ST_OK) //ѭգֱȫ - { -/**********************************************************************************************************************************************************************************************************************************************************************************************************************************************/ - i = get_data(&strXMODEM.SOH, BLOCKSIZE+5, 1); // 1/16 second timeout, it'll affect the total time of download. - -/**********************************************************************************************************************************************************************************************************************************************************************************************************************************************/ - if(i) - { - //ݰĵһ SOH/EOT/CAN - switch(strXMODEM.SOH) - { - case XMODEM_SOH: //յʼSOH - if (i>=(crc_mode?(BLOCKSIZE+5):(BLOCKSIZE+4))) - { - STATUS=ST_BLOCK_OK; - } - else - { - STATUS=ST_BLOCK_FAIL; //ݲ㣬Ҫطǰݿ - tgt_putchar(XMODEM_NAK); - } - break; - case XMODEM_EOT: //յEOT - tgt_putchar(XMODEM_ACK); //֪ͨPCȫյ - STATUS=ST_OK; - break; - case XMODEM_CAN: //յȡCAN - tgt_putchar(XMODEM_ACK); //ӦPC - STATUS=ST_OK; - break; - default: //ʼֽڴ - tgt_putchar(XMODEM_NAK); //Ҫطǰݿ - STATUS=ST_BLOCK_FAIL; - break; - } - } - else - { - break; - //tgt_putchar(XMODEM_NAK); //ݿŴҪطǰݿ - //continue; - } - - if (STATUS==ST_BLOCK_OK) //133ֽOKʼֽȷ - { - if (BlockCount != strXMODEM.BlockNo)//˶ݿȷ - { - tgt_putchar(XMODEM_NAK); //ݿŴҪطǰݿ - continue; - } - if (BlockCount !=(unsigned char)(~strXMODEM.nBlockNo)) - { - tgt_putchar(XMODEM_NAK); //ݿŷҪطǰݿ - continue; - } - - if(crc_mode) - { - crc = strXMODEM.CRC16hi<<8; - crc += strXMODEM.CRC16lo; - } - else - { - crc = strXMODEM.CRC16hi; - } - - if(calcrc(&strXMODEM.Xdata[0], BLOCKSIZE, crc_mode)!=crc) - { - tgt_putchar(XMODEM_NAK); //CRCҪطǰݿ - continue; - } - -#if LS1D_FPGA - _u32 addr_r = (_u32)&strXMODEM.Xdata[0]; - spiflash_write(addr_w, addr_r, length); - addr_w += length; -#else - //Flash_Write(base+filesize, &buf[0],32) ; -#endif - - filesize += 128; - tgt_putchar(XMODEM_ACK); //Ӧȷյһݿ - BlockCount++; //ݿۼƼ1 - } - } - - //printf("xmodem finished\n"); - - return filesize; -} - - -_u32 xmodem() -{ - _u32 base = FLASH_ERASE_START; - int file_size; - - //printf("Waiting for serial transmitting datas...\n"); -#if LS1D_FPGA - _u32 addr_start = FLASH_ERASE_START; - _u32 addr_end = FLASH_ERASE_END; - spiflash_erase(addr_start, addr_end); -#endif - file_size = xmodem_transfer(base); - //printf("Load successfully! Start at 0x%x, size 0x%x\n", base, file_size); - - return 0; -} - - diff --git a/resources/soc/simu/soft/func/start.S b/resources/soc/simu/soft/func/start.S deleted file mode 100644 index fe6f115..0000000 --- a/resources/soc/simu/soft/func/start.S +++ /dev/null @@ -1,657 +0,0 @@ - -/************************************************************************************************************************************************************************************************/ - -#include "include/asm/regdef.h" -#include "include/asm/mipsregs.h" -#include "include/asm/ns16550.h" -#include "include/asm/interrupt.h" - -#define NAND_TEST -#define SRAM_BASEADDR 0xa0000000 -#define UART0_BASEADDR 0xbfe40000 -#define NAND_BASEADDR 0xbfe48000 -#define CONFIG_BASE 0xaff00000 -#define MAC_BASEADDR 0xbff00000 -#define CONFREG_BASE 0xbfd00000 - -#define DELAY 0x4 -#define print_hex 1 -#define print_reg 0 -#define PRINTSTR(x) \ - .rdata;98: .asciz x; .text; la a0, 98b; bal stringserial; nop -#define PRINT(x) \ - .rdata; .text; la a0, x; bal stringserial; nop -#define RVECENT(f,n) \ - b f; \ - nop -#define XVECENT(f,bev) \ - b f; \ - nop - - .set noreorder - - .globl _start - .text -_start: - RVECENT(reset,0) /* hard-reset entry point */ - RVECENT(reset,1) /* software reboot */ - RVECENT(romReserved,2) - RVECENT(romReserved,3) - RVECENT(romReserved,4) - RVECENT(romReserved,5) - RVECENT(romReserved,6) - RVECENT(romReserved,7) - RVECENT(romReserved,8) - RVECENT(romReserved,9) - RVECENT(romReserved,10) - RVECENT(romReserved,11) - RVECENT(romReserved,12) - RVECENT(romReserved,13) - RVECENT(romReserved,14) - RVECENT(romReserved,15) - RVECENT(romReserved,16) - RVECENT(romReserved,17) - RVECENT(romReserved,18) - RVECENT(romReserved,19) - RVECENT(romReserved,20) - RVECENT(romReserved,21) - RVECENT(romReserved,22) - RVECENT(romReserved,23) - RVECENT(romReserved,24) - RVECENT(romReserved,25) - RVECENT(romReserved,26) - RVECENT(romReserved,27) - RVECENT(romReserved,28) - RVECENT(romReserved,29) - RVECENT(romReserved,30) - RVECENT(romReserved,31) - RVECENT(romReserved,32) - RVECENT(romReserved,33) - RVECENT(romReserved,34) - RVECENT(romReserved,35) - RVECENT(romReserved,36) - RVECENT(romReserved,37) - RVECENT(romReserved,38) - RVECENT(romReserved,39) - RVECENT(romReserved,40) - RVECENT(romReserved,41) - RVECENT(romReserved,42) - RVECENT(romReserved,43) - RVECENT(romReserved,44) - RVECENT(romReserved,45) - RVECENT(romReserved,46) - RVECENT(romReserved,47) - RVECENT(romReserved,48) - RVECENT(romReserved,49) - RVECENT(romReserved,50) - RVECENT(romReserved,51) - RVECENT(romReserved,52) - RVECENT(romReserved,53) - RVECENT(romReserved,54) - RVECENT(romReserved,55) - RVECENT(romReserved,56) - RVECENT(romReserved,57) - RVECENT(romReserved,58) - RVECENT(romReserved,59) - RVECENT(romReserved,60) - RVECENT(romReserved,61) - RVECENT(romReserved,62) - RVECENT(romReserved,63) - XVECENT(romExcHandle,0x200) /* bfc00200: R4000 tlbmiss vector */ - RVECENT(romReserved,65) - RVECENT(romReserved,66) - RVECENT(romReserved,67) - RVECENT(romReserved,68) - RVECENT(romReserved,69) - RVECENT(romReserved,70) - RVECENT(romReserved,71) - RVECENT(romReserved,72) - RVECENT(romReserved,73) - RVECENT(romReserved,74) - RVECENT(romReserved,75) - RVECENT(romReserved,76) - RVECENT(romReserved,77) - RVECENT(romReserved,78) - RVECENT(romReserved,79) - XVECENT(romExcHandle,0x280) /* bfc00280: R4000 xtlbmiss vector */ - RVECENT(romReserved,81) - RVECENT(romReserved,82) - RVECENT(romReserved,83) - RVECENT(romReserved,84) - RVECENT(romReserved,85) - RVECENT(romReserved,86) - RVECENT(romReserved,87) - RVECENT(romReserved,88) - RVECENT(romReserved,89) - RVECENT(romReserved,90) - RVECENT(romReserved,91) - RVECENT(romReserved,92) - RVECENT(romReserved,93) - RVECENT(romReserved,94) - RVECENT(romReserved,95) - XVECENT(romExcHandle,0x300) /* bfc00300: R4000 cache vector */ - RVECENT(romReserved,97) - RVECENT(romReserved,98) - RVECENT(romReserved,99) - RVECENT(romReserved,100) - RVECENT(romReserved,101) - RVECENT(romReserved,102) - RVECENT(romReserved,103) - RVECENT(romReserved,104) - RVECENT(romReserved,105) - RVECENT(romReserved,106) - RVECENT(romReserved,107) - RVECENT(romReserved,108) - RVECENT(romReserved,109) - RVECENT(romReserved,110) - RVECENT(romReserved,111) -#if 0 - XVECENT(IntHandle,0x380) /* bfc00380: R4000 general vector */ -#else -IntHandle: - SAVE_ALL -# PRINTSTR("Interrupt 0 is coming...\r\n") -#if 1 // print_reg -# bal PRINT_CP0 -# nop -#endif - -7: - mfc0 t0, CP0_CAUSE - and t1, t0, 0x400 - bne zero, t1, 1f - nop - and t1, t0, 0x800 - bne zero, t1, 2f - nop - and t1, t0, 0x1000 - bne zero, t1, 3f - nop - and t1, t0, 0x2000 - bne zero, t1, 4f - nop - and t1, t0, 0x4000 - bne zero, t1, 5f - nop - and t1, t0, 0x8000 - bne zero, t1, 6f - nop - #PRINTSTR("No interrupt left...\r\n\r\n") - b 8f - nop - -1: /*timer*/ -# PRINTSTR("Timer interrupt is coming...\r\n") - -2: /*key*/ -# PRINTSTR("Key interrupt is coming...\r\n") - -3: /*batfail*/ -# PRINTSTR("BatFail interrupt is coming...\r\n") - -4: /*res_valid*/ -# PRINTSTR("ResVaild interrupt is coming...\r\n") - -5: /*INTC*/ -# PRINTSTR("IP6 is coming...\r\n") - -6: /*Ring*/ -# PRINTSTR("IP7 is coming...\r\n") - -8: - LOAD_ALL - .set mips32 - eret - .set mips1 - nop -#endif - - RVECENT(romReserved,113) - RVECENT(romReserved,114) - RVECENT(romReserved,115) - RVECENT(romReserved,116) - RVECENT(romReserved,116) - RVECENT(romReserved,118) - RVECENT(romReserved,119) - RVECENT(romReserved,120) - RVECENT(romReserved,121) - RVECENT(romReserved,122) - RVECENT(romReserved,123) - RVECENT(romReserved,124) - RVECENT(romReserved,125) - RVECENT(romReserved,126) - RVECENT(romReserved,127) - - /* We hope there are no more reserved vectors! - * 128 * 8 == 1024 == 0x400 - * so this is address R_VEC+0x400 == 0xbfc00400 - */ - .align 4 -#if print_hex - .rdata -hexchar: - .ascii "0123456789abcdef" - .text //Don't forget it! -#endif - -reset: - mtc0 zero, CP0_CAUSE # - li t0, 0x30400000 - mtc0 t0, CP0_STATUS # - li t0, 0x00000000 #set fp reg - /* Initialize $gp. - */ - bal 1f - nop - .word _gp -1: - lw gp, 0(ra) - - bal initserial0 - nop - - PRINTSTR("\r\nInitializing...\r\n"); - PRINTSTR("\r\nHello, Loongson...\r\n"); - - li t0, 0xbfd00010 - lw t1,0(t0) - ori t1, t1, 0x0 - sw t1,0(t0) -################################################### -#####nand test -##### -#ifdef NAND_TEST - bal nand_test - nop -## PRINTSTR("\r\nGouSheng!!!\r\n"); -#endif -##### -#####nand test -################################################### - - - PRINTSTR("\r\nMac_test start...\r\n"); - bal mac_test - nop - PRINTSTR("\r\nMac_test end...\r\n"); - // bal ddr2_config //old ddr config - // nop - - la v0, SRAM_BASEADDR - li t0, 0x0a424242 - sw t0, 0x0(v0) - la a0, 0x0(v0) - bal stringserial - nop - - la a0, loongson - bal stringserial - nop - - la v0, SRAM_BASEADDR - li t0, 0x0a454545 - sw t0, 0x0(v0) - la a0, 0x0(v0) - bal stringserial - nop - - -###ddr3 test -# if 1 -#####write data to sram - .align 5 - la v0, SRAM_BASEADDR - la s0, SRAM_BASEADDR+0x00000100 - li t0, 0x11111111 - li t1, 0x21212121 - li t2, 0x31313131 - li t3, 0x41414141 - li t4, 0x51515151 - li t5, 0x61616161 - li t6, 0x71717171 - li t7, 0x81818181 -1: - sw t0, 0x0(v0) - sw t1, 0x4(v0) - sw t2, 0x8(v0) - sw t3, 0xc(v0) - sw t4, 0x10(v0) - sw t5, 0x14(v0) - sw t6, 0x18(v0) - sw t7, 0x1c(v0) - addiu v0, v0, 0x20 - bne v0, s0, 1b - nop - -#####read data from sram - la v0, SRAM_BASEADDR -2: - lw t8, 0x0(v0) - beq t0, t8, 1f - nop - jal checkerr - nop -1: - lw t8, 0x4(v0) - beq t1, t8, 1f - nop - jal checkerr - nop -1: - lw t8, 0x8(v0) - beq t2, t8, 1f - nop - jal checkerr - nop -1: - lw t8, 0xc(v0) - beq t3, t8, 1f - nop - jal checkerr - nop -1: - lw t8, 0x10(v0) - beq t4, t8, 1f - nop - jal checkerr - nop -1: - lw t8, 0x14(v0) - beq t5, t8, 1f - nop - jal checkerr - nop -1: - lw t8, 0x18(v0) - beq t6, t8, 1f - nop - jal checkerr - nop -1: - lw t8, 0x1c(v0) - beq t7, t8, 1f - nop - jal checkerr - nop -1: - addiu v0, v0, 0x20 - bne v0, s0, 2b - nop - -#endif - -# la a0, 0x0(v0) -# bal stringserial -# nop -# la a0, 0x4(v0) -# PRINTSTR("\r\nHello, Loongson again...\r\n"); -# la a0, loongsonagain -# bal stringserial -# nop - - - -100: -#if 0 - /********enable interrupt**********/ - mfc0 t0, CP0_STATUS - li t1, 0xffff00fe - and t2, t0, t1 - li t1, 0xfc01 - or t0, t2, t1 - mtc0 t0, CP0_STATUS -#endif - li t0, SRAM_BASEADDR+0xffc - la sp, 0(t0) # - - la t9, main - jr t9 - nop - -1: - b 1b - nop - -/*********************************************************************************/ -##### mac func start - .align 5 - .ent mac_test -mac_test: -# addi sp, sp, 0xfffc -# sw ra, 0(sp) - move a3, ra -#read descriptor - li a2, 0xa0701100 - li a1, 0x80000000 - sw a1, 0x00(a2) - li a1, 0x00000100 - sw a1, 0x04(a2) - li a1, 0x007027f0 - sw a1, 0x08(a2) - -#start read process - li a2, MAC_BASEADDR - li a1, 0x0 - sw a1, 0x0(a2) - li a1, 0x00701000 - sw a1, 0x20(a2) - li a1, 0x00701100 - sw a1, 0x18(a2) - li a1, 0x40000002 - sw a1, 0x30(a2) - -#write gpio to enable virtual mac sw - li a0, 0x10 - li a1, CONFREG_BASE - sb a0, 0(a1) - sb a0, 0x10(a1) - -#detect read frame -read_interrupt: - lw a1, 0x28(a2) - li a0, 0xa0700010 - and a0, a1, 0x40 - beqz a0, read_interrupt - nop - -#write descriptor - - li a2, 0xa0701000 - li a1, 0x80000000 - sw a1, 0x00(a2) - li a1, 0x62000100 - sw a1, 0x04(a2) - li a1, 0x007027f0 - sw a1, 0x08(a2) - -#start write process - li a2, MAC_BASEADDR - li a1, 0x00701000 - sw a1, 0x20(a2) - li a1, 0x00701100 - sw a1, 0x18(a2) - li a1, 0x40002002 - sw a1, 0x30(a2) - - j a3 - nop - .end mac_test -##### mac func end - -initserial0: - la v0, UART0_BASEADDR -1: - li v1, FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_4 - sb v1, NSREG(NS16550_FIFO)(v0) - li v1, CFCR_DLAB #DLAB - sb v1, NSREG(NS16550_CFCR)(v0) - li v1, 0xCF - sb v1, NSREG(NS16550_FIFO)(v0) - li v1, 0x23 #set BRDL 57600Baut - sb v1, NSREG(NS16550_DATA)(v0) - srl v1, 8 #no necessary - sb v1, NSREG(NS16550_IER)(v0) #set BRDH #no necessary - li v1, CFCR_8BITS #8bit, 1stop - sb v1, NSREG(NS16550_CFCR)(v0) - li v1, MCR_DTR|MCR_RTS - sb v1, NSREG(NS16550_MCR)(v0) - li v1, 0x0 - sb v1, NSREG(NS16550_IER)(v0) - - move v1, v0 - la v0, UART0_BASEADDR - bne v0, v1, 1b - nop - - j ra - nop - - - - -tgt_putchar: - la v0, UART0_BASEADDR -1: - lbu v1, NSREG(NS16550_LSR)(v0) - and v1, LSR_TXRDY - beqz v1, 1b - nop - - sb a0, NSREG(NS16550_DATA)(v0) - move v1,v0 - la v0, UART0_BASEADDR - bne v0,v1,1b - nop - j ra - nop - -#if print_hex -hexserial: - nop - move a2, ra - move a1, a0 - li a3, 8 -1: - rol a0, a1, 4 - move a1, a0 - and a0, 0xf - la v0, hexchar - addu v0, a0 - lbu a0, 0(v0) - bal tgt_putchar - nop - - addi a3, -1 - bnez a3, 1b - nop - - j a2 - nop -#endif - -PRINT_CP0: -#if print_hex - move t0, ra - PRINTSTR("STATUS=0x") - mfc0 a0, CP0_STATUS - bal hexserial - nop - PRINTSTR("\r\n") - - PRINTSTR("CAUSE=0x") - mfc0 a0, CP0_CAUSE - bal hexserial - nop - PRINTSTR("\r\n") - - j t0 - nop -#endif - - -/*******************************************************************/ - - /* Exception handlers. - */ -romReserved: - PRINTSTR("Interrupt 1 is coming...\r\n") - b romReserved - nop - -romExcHandle: - PRINTSTR("Interrupt 2 is coming...\r\n") - b romExcHandle - nop - -ddr2_config: - li t0, 0xbfd00000 - li t1, 0x1 - sw t1, 0x0(t0) - - ##########start######## - li t2, CONFIG_BASE - li a1, 0x1 - sb a1, 0x18(t2) - ####################### - -1: - lb a1, 0x163(t2) - beqz a1, 1b - nop - - li t0, 0xbfd00000 - li t1, 0x0 - sw t1, 0x0(t0) - - jr ra - nop - - .global stringserial - .ent stringserial -stringserial: - move a2, ra - move a1, a0 - lbu a0, 0(a1) -1: - beqz a0, 2f - nop - addiu a1, 1 - bal tgt_putchar - nop - lbu a0, 0(a1) - b 1b - nop -2: - j a2 - nop - .end stringserial - - .ent checkerr -checkerr: - la a0, errstr - bal stringserial - nop - jr ra - nop - .end checkerr - - .rdata - .align 5 -msg_nand_test_reset_begin: - .asciiz "rst\n" -msg_nand_test_reset_end: - .asciiz "nand rst pass\n" -msg_nand_test_write_begin: - .asciiz "nand wr go\n" -msg_nand_test_write_end: - .asciiz "nand write pass \n" -msg_nand_test_read_begin: - .asciiz "nand rd go\n" -msg_nand_test_read_end: - .asciiz "nand rd pass\n" -errstr: - .asciz "error" -loongson: - .asciz "Loongson Test\n" -loongsonagain: - .asciz "Loongson Test Twice" diff --git a/resources/soc/simu/soft/func/test.lds b/resources/soc/simu/soft/func/test.lds deleted file mode 100644 index b487f0d..0000000 --- a/resources/soc/simu/soft/func/test.lds +++ /dev/null @@ -1,72 +0,0 @@ -/* - * (C) Masami Komiya 2004 - * - * (C) Copyright 2003 - * Wolfgang Denk Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips") - -OUTPUT_ARCH(mips) -ENTRY(_start) -SECTIONS -{ - - . = ALIGN(4); - .text : - { - *(.text) - } - - . = ALIGN(4); - .rel.text : { *(.rel.text) } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .reginfo : { *(.reginfo) } - - . = ALIGN(4); - .ptr : { *(.ptr) } - - . = ALIGN(4); - .shstrtab : { *(.shstrtab) } - - . = ALIGN(4); - .strtab : { *(.strtab) } - - . = .; - _gp = ALIGN(16) + 0x7ff0; - .got : { - __got_start = .; - *(.got) - __got_end = .; - } - - . = 0xa0000000; - . = ALIGN(4); - .sbss : { *(.sbss) } - .bss : { *(.bss) . = ALIGN(4); } -} diff --git a/resources/soc/simu/testbench/MX25L6405D.v b/resources/soc/simu/testbench/MX25L6405D.v deleted file mode 100644 index 33ea9d0..0000000 --- a/resources/soc/simu/testbench/MX25L6405D.v +++ /dev/null @@ -1,2154 +0,0 @@ -// *============================================================================================== -// * -// * MX25L6405D.v - 64M-BIT CMOS Serial Flash Memory -// * -// * COPYRIGHT 2008 Macronix International Co., Ltd. -// *---------------------------------------------------------------------------------------------- -// * Environment : Cadence NC-Verilog -// * Reference Doc: MX25L1605D-3205D-6405D REV.1.1,MAY.12, 2008 -// * Creation Date: @(#)$Date: 2008/06/13 05:24:15 $ -// * Version : @(#)$Revision: 1.4 $ -// * Description : There is only one module in this file -// * module MX25L6405D->behavior model for the 64M-Bit flash -// *---------------------------------------------------------------------------------------------- -// * Note 1:model can load initial flash data from file when model define parameter Init_File = "xxx"; -// * xxx: initial flash data file name;default value xxx = "none", initial flash data is "FF". -// * Note 2:power setup time is tVSL = 200_000 ns, so after power up, chip can be enable. -// * Note 3:time delay to write instruction is tPUW = 10_000_000 ns. -// * Note 4:If define KGD product, Model support good ID read (Addr 0x3f Data 55h). -// * Note 5:If you have any question and suggestion, please send your mail to follow email address : -// * flash_model@mxic.com.tw -// *---------------------------------------------------------------------------------------------- -// * History -// * Date | Version Description -// * $Log: MX25L6405D.v,v $ -// * Revision 1.4 2008/06/13 05:24:15 simmodel -// * update fTSCLK=50MHz. -// * -// * Revision 1.3 2008/06/12 02:06:42 simmodel -// * disable KGD product define -// * -// * Revision 1.2 2008/03/04 16:32:05 simmodel -// * update DISWRSR -// * -// *============================================================================================== -// *============================================================================================== -// * timescale define -// *============================================================================================== -`timescale 1ns / 100ps - -// *============================================================================================== -// * product parameter define -// *============================================================================================== - /*----------------------------------------------------------------------*/ - /* Define controller STATE */ - /*----------------------------------------------------------------------*/ - `define STANDBY_STATE 0 - `define ACTION_STATE 1 - `define CMD_STATE 2 - `define BAD_CMD_STATE 3 - - `define MX25L6405D - // `define MX25L6405D - // `define MX25L6415D - `ifdef MX25L6405D - `define PADOP1 1'b0 - `endif - - `ifdef MX25L6415D - `define PADOP1 1'b1 - `endif - - `define KGD_PRODUCT 1'b0 - -module MX25L6405D( SCLK, - CS, - SI, - SO, - WP, - HOLD ); - -// *============================================================================================== -// * Declaration of ports (input, output, inout) -// *============================================================================================== - input SCLK; // Signal of Clock Input - input CS; // Chip select (Low active) - inout SI; // Serial Input/Output SIO0 - inout SO; // Serial Input/Output SIO1 - input WP; // Hardware write protection - input HOLD; // Pause the chip without diselecting the chip - -// *============================================================================================== -// * Declaration of parameter (parameter) -// *============================================================================================== - /*----------------------------------------------------------------------*/ - /* Density STATE parameter */ - /*----------------------------------------------------------------------*/ - parameter A_MSB = 22, - TOP_Add = 23'h7fffff, - Secur_TOP_Add = 7'h7f, - Sector_MSB = 10, - Block_MSB = 6, - Block_NUM = 128, - PRO_128K_Beg = 23'h7d0000, - PRO_128K_End = 23'h7effff; - - /*----------------------------------------------------------------------*/ - /* Define ID Parameter */ - /*----------------------------------------------------------------------*/ - parameter ID_MXIC = 8'hc2, - ID_Device = `PADOP1? 8'h1e : 8'h16, - Memory_Type = `PADOP1? 8'h22 : 8'h20, - Memory_Density = 8'h17; - - /*----------------------------------------------------------------------*/ - /* Define Initial Memory File Name */ - /*----------------------------------------------------------------------*/ - parameter Init_File = "none"; // initial flash data - - /*----------------------------------------------------------------------*/ - /* AC Charicters Parameter */ - /*----------------------------------------------------------------------*/ - parameter tSHQZ = 8, // CS High to SO Float Time [ns] - tCLQV = 8, // Clock Low to Output Valid - tHHQX = 8, // HOLD to Output Low-z - tHLQZ = 8, // HOLD to Output High-z - tDP = 10_000, - tRES1 = 8_800, - tRES2 = 8_800; - parameter tREP0 = 100, // 100ns Reset# recovery time (during read algorithm) - // to read or write - tREP1 = 50_000; // 50us Reset# recovery time (during program/erase algorithm) - // to read or write - //tOHZ = 10, // 10ns PR# goes high and SCLK falling to data out - //tRD = 10; // 10ns PR# goes high and SCLK falling to data out - parameter tAA = 50; // 50ns Parallel mode read time - parameter tBP = 9_000; // Byte program time - parameter tSE = 90_000_000, // Sector erase time - tBE = 700_000_000, // Block erase time - tCE = 50_000, // unit is ms instead of ns - tPP = 1_400_000, // Program time - tW = 40_000_000, // Write Status time - tPUW = 10_000_000, // Time delay to write instruction - tVSL = 20; // Time delay to chip select allowed - //smh tVSL = 200_000; // Time delay to chip select allowed - - specify - specparam tSCLK = 12, // Clock Cycle Time [ns] - fSCLK = 86, // Clock Frequence except READ instruction[ns] 15pF - tRSCLK = 30, // Clock Cycle Time for READ instruction[ns] 15pF - fRSCLK = 33, // Clock Frequence for READ instruction[ns] 15pF - tCH = 5.5, // Clock High Time (min) [ns] - tCL = 5.5, // Clock Low Time (min) [ns] - tSLCH = 5, // CS# Active Setup Time (relative to SCLK) (min) [ns] - tCHSL = 5, // CS# Not Active Hold Time (relative to SCLK)(min) [ns] - tSHSL = 100, // CS High Time (min) [ns] - tDVCH = 2, // SI Setup Time (min) [ns] - tCHDX = 5, // SI Hold Time (min) [ns] - tCHSH = 5, // CS# Active Hold Time (relative to SCLK) (min) [ns] - tSHCH = 5, // CS# Not Active Setup Time (relative to SCLK) (min) [ns] - tHLCH = 5, // HOLD# Setup Time (relative to SCLK) (min) [ns] - tCHHH = 5, // HOLD# Hold Time (relative to SCLK) (min) [ns] - tHHCH = 5, // HOLD Setup Time (relative to SCLK) (min) [ns] - tCHHL = 5, // HOLD Hold Time (relative to SCLK) (min) [ns] - tWHSL = 20, // Write Protection Setup Time - tSHWL = 100, // Write Protection Hold Time - tCLHS = 3, // Clock Low to HOLD# setup time - tCLHH = 3; // Clock Low to HOLD# hold time - specparam tTSCLK = 20, // Clock Cycle Time for 2XI/O READ instruction[ns] 15pF - fTSCLK = 50; // Clock Frequence for 2XI/O READ instruction[ns] 15pF - - endspecify - - /*----------------------------------------------------------------------*/ - /* Define Command Parameter */ - /*----------------------------------------------------------------------*/ - parameter WREN = 8'h06, // WriteEnable - WRDI = 8'h04, // WriteDisable - RDID = 8'h9F, // ReadID - RDSR = 8'h05, // ReadStatus - WRSR = 8'h01, // WriteStatus - READ1X = 8'h03, // ReadData - FASTREAD1X = 8'h0b, // FastReadData - SE = 8'h20, // SectorErase - CE1 = 8'h60, // ChipErase - CE2 = 8'hc7, // ChipErase - PP = 8'h02, // PageProgram - DP = 8'hb9, // DeepPowerDown - RDP = 8'hab, // ReleaseFromDeepPowerDwon - RES = 8'hab, // ReadElectricID - REMS = 8'h90; // ReadElectricManufacturerDeviceID - parameter RDPR = 8'ha1, // Read parameter register - WRPR = 8'hf1; // Write parameter register - parameter BE = 8'hd8, // BlockErase - READ2X = 8'hbb, // 2X Read - CP = 8'had, // Continuously program mode; - REMS2 = 8'hef, // ReadElectricManufacturerDeviceID - ENSO = 8'hb1, // Enter secured OTP; - EXSO = 8'hc1, // Exit secured OTP; - RDSCUR = 8'h2b, // Read security register; - WDSCUR = 8'h2f, // Write security register; - WRLB = 8'h21, // Write read-lock register; - ESRY = 8'h70, // Enable SO to output RY/BY; - DSRY = 8'h80; // Disable SO to output RY/BY; - - /*----------------------------------------------------------------------*/ - /* Declaration of internal-register (reg) */ - /*----------------------------------------------------------------------*/ - reg [7:0] ARRAY[0:TOP_Add]; // memory array - reg [7:0] Status_Reg; // Status Register - reg [7:0] CMD_BUS; - reg [6:0] PO_Reg; - reg [6:0] Latch_PO; - reg Latch_SO; - reg [23:0] SI_Reg; // temp reg to store serial in - reg [7:0] Dummy_A[0:255]; // page size - reg [A_MSB:0] Address; - reg [Sector_MSB:0] Sector; - reg [Block_MSB:0] Block; - reg [2:0] STATE; - - reg EN_S0; //EN_S0 fSCLK Serial AC Characteristics; - reg EN_P0; //EN_P0 fSCLK parallel AC Characteristics; - reg EN_S1; //EN_S1 fRSCLK Serial AC Characteristics; - reg EN_P1; //EN_P1 fRSCLK parallel AC Characteristics; - reg SIO1_Reg; - reg Write_EN; - reg Read_EN; - reg P_Mode; // parallel mode - reg DP_Mode; // deep power down mode - reg Read_Mode; - reg Read_1XIO_Mode; - reg Read_1XIO_Chk; - reg FastRD_1XIO_Mode; - reg PP_1XIO_Mode; - reg SE_4K_Mode; - reg BE_Mode; - reg CE_Mode; - reg WRSR_Mode; - reg RES_Mode; - reg REMS_Mode; - reg SCLK_EN; - reg HOLD_OUT_B; - reg SO_OUT_EN; // for SO - reg SI_IN_EN; // for SI - wire HOLD_B_INT; - wire WP_B_INT; - wire ISCLK; - wire WIP; - wire WEL; - wire SRWD; - wire Dis_CE, Dis_WRSR; - event WRSR_Event; - event BE_Event; - event SE_4K_Event; - event CE_Event; - event PP_Event; - event RDP_Event; - event DP_Event; - integer i; - integer j; - integer Bit; - integer Bit_Tmp; - integer Start_Add; - integer End_Add; - integer Page_Size; - time tRES; - - reg [7:0] Param_Reg; // Parameter register - wire RESET_B; - - reg [7:0] Secur_ARRAY[0:Secur_TOP_Add]; // Secured OTP - reg [7:0] Secur_Reg; // security register - reg [15:0] CP_Data; - - reg Secur_Mode; // enter secured mode - reg CP_ESRY_Mode; - reg EN_CP_Mode; - reg CP_Mode; - reg Read_2XIO_Mode; - reg Read_2XIO_Chk; - reg SE_1K_Mode; - reg Byte_PGM_Mode; //Program one byte is 7us - reg SI_OUT_EN; // for SI - reg SO_IN_EN; // for SO - reg SIO0_Reg; - wire CP_Busy; - event CP_Event; - event WRSCUR_Event; - event SE_1K_Event; - - - - /*----------------------------------------------------------------------*/ - /* initial variable value */ - /*----------------------------------------------------------------------*/ - initial begin - reset_sm; - Secur_Reg = 8'b0000_0000; - end - - task reset_sm; - begin - Status_Reg = 8'b0000_0000; - SO_OUT_EN = 1'b0; // SO output enable - SI_IN_EN = 1'b0; // SI input enable - CMD_BUS = 8'b0000_0000; - Address = 0; - i = 0; - j = 0; - Bit = 0; - Bit_Tmp = 0; - Start_Add = 0; - End_Add = 0; - Page_Size = 256; - DP_Mode = 1'b0; - P_Mode = 1'b0; - Write_EN = 1'b0; - Read_EN = 1'b0; - SCLK_EN = 1'b1; - Read_Mode = 1'b0; - Read_1XIO_Mode = 1'b0; - Read_1XIO_Chk = 1'b0; - PP_1XIO_Mode = 1'b0; - SE_4K_Mode = 1'b0; - BE_Mode = 1'b0; - CE_Mode = 1'b0; - WRSR_Mode = 1'b0; - RES_Mode = 1'b0; - REMS_Mode = 1'b0; - FastRD_1XIO_Mode = 1'b0; - HOLD_OUT_B = 1'b1; - {EN_S0, EN_P0, EN_S1, EN_P1} = {1'b1, 1'b0, 1'b0, 1'b0}; - Param_Reg = 8'b0000_0000; - SI_OUT_EN = 1'b0; // SI output enable - SO_IN_EN = 1'b0; // SO input enable - CP_Data = 8'b0000_0000; - Secur_Mode = 1'b0; - CP_ESRY_Mode = 1'b0; - EN_CP_Mode = 1'b0; - CP_Mode = 1'b0; - Read_2XIO_Mode = 1'b0; - Read_2XIO_Chk = 1'b0; - SE_1K_Mode = 1'b0; - Byte_PGM_Mode = 1'b0; - Secur_Reg[3:2] = 2'b00; - - - end - endtask // reset_sm - - /*----------------------------------------------------------------------*/ - /* initial flash data */ - /*----------------------------------------------------------------------*/ -//MX25L6405D #(.Init_File(`APP_FLASH)) - initial - begin : memory_initialize - for ( i = 0; i <= TOP_Add; i = i + 1 ) - ARRAY[i] = 8'hff; - if ( Init_File != "none" ) begin - $readmemh(Init_File,ARRAY) ; - $display("load Init_File %s, array[0..3]=%h %h %h %h", Init_File, - ARRAY[0],ARRAY[1],ARRAY[2],ARRAY[3]); - end - for( i = 0; i <= Secur_TOP_Add; i = i + 1 ) begin - Secur_ARRAY[i]=8'hff; - end - if ( `KGD_PRODUCT == 1'b1 ) begin - Secur_ARRAY[8'h3f]=8'h55; - end - end - -// *============================================================================================== -// * Input/Output bus opearation -// *============================================================================================== - assign ISCLK = (SCLK_EN == 1'b1) ? SCLK:1'b0; - assign HOLD_B_INT = (CS == 1'b0 && `PADOP1 == 1'b0 ) ? HOLD : 1'b1; - assign RESET_B = `PADOP1 == 1'b1 ? HOLD : 1'b1; - assign WP_B_INT = (CS == 1'b0 ) ? WP : 1'b1; - assign SO = (SO_OUT_EN && HOLD_OUT_B) ? SIO1_Reg : 1'bz ; - assign SI = (SI_OUT_EN && HOLD_OUT_B) ? SIO0_Reg : 1'bz ; - - - /*----------------------------------------------------------------------*/ - /* When CP_mode, Enable SO to output RY/BY; */ - /*----------------------------------------------------------------------*/ - assign CP_Busy = !(EN_CP_Mode && Status_Reg[0]); - always @ ( negedge CS or CP_Busy or ISCLK ) begin - if ( (EN_CP_Mode == 1) && (CS == 0) && (CP_ESRY_Mode == 1'b1) ) begin - SIO1_Reg <= #tCLQV CP_Busy; - SO_OUT_EN = 1'b1; - end - end - - /*----------------------------------------------------------------------*/ - /* When Hold Condtion Operation; */ - /*----------------------------------------------------------------------*/ - always @ ( HOLD_B_INT or negedge SCLK) begin - if ( HOLD_B_INT == 1'b0 && SCLK == 1'b0) begin - SCLK_EN =1'b0; - HOLD_OUT_B<= #tHLQZ 1'b0; - end - else if ( HOLD_B_INT == 1'b1 && SCLK == 1'b0) begin - SCLK_EN =1'b1; - HOLD_OUT_B<= #tHHQX 1'b1; - end - end - - /*----------------------------------------------------------------------*/ - /* When Reset Condtion Operation; */ - /*----------------------------------------------------------------------*/ - always @ ( RESET_B ) begin - if ( RESET_B == 1'b0 ) begin - disable write_status; - disable block_erase; - disable sector_erase_4k; - disable sector_erase_1k; - disable chip_erase; - disable page_program_mode; - disable cp_program; - disable write_secur_register; - disable deep_power_down; - disable release_from_deep_power_down; - disable read_1xio; - disable read_2xio; - disable fastread_1xio; - disable read_electronic_id; - disable read_electronic_manufacturer_device_id; - disable read_function; - disable dummy_cycle; - SO_OUT_EN <=#tSHQZ 1'b0; - SI_OUT_EN <=#tSHQZ 1'b0; - end - else begin - if ( Status_Reg[0] == 1'b1 ) - STATE <= #tREP1 `STANDBY_STATE; - else - STATE <= #tREP0 `STANDBY_STATE; - reset_sm; - end - end - /*----------------------------------------------------------------------*/ - /* When Secur_Mode, Page_Size 256-->64 */ - /*----------------------------------------------------------------------*/ - always @ ( Secur_Mode ) begin - Page_Size = (Secur_Mode == 1) ? 64 : 256; - end - - -// *============================================================================================== -// * Finite State machine to control Flash operation -// *============================================================================================== - /*----------------------------------------------------------------------*/ - /* power on */ - /*----------------------------------------------------------------------*/ - initial begin - Write_EN <= #tPUW 1'b1;// Time delay to write instruction - Read_EN <= #tVSL 1'b1;// Time delay to chip select allowed - end - - /*----------------------------------------------------------------------*/ - /* Command Decode */ - /*----------------------------------------------------------------------*/ - assign WIP = Status_Reg[0] ; - assign WEL = Status_Reg[1] ; - assign SRWD = Status_Reg[7] ; - assign Dis_CE = Status_Reg[5] == 1'b1 || Status_Reg[4] == 1'b1 || - Status_Reg[3] == 1'b1 || Status_Reg[2] == 1'b1 ; - assign Dis_WRSR = (WP_B_INT == 1'b0 && Status_Reg[7] == 1'b1) || (Secur_Reg[3] == 1'b1) || Secur_Mode; - - - always @ ( negedge CS ) begin - SI_IN_EN = 1'b1; - end - - - always @ ( posedge ISCLK or posedge CS ) begin - #0; - if ( CS == 1'b0 ) begin - Bit_Tmp = Bit_Tmp + 1; - Bit = Bit_Tmp - 1; - - if ( SI_IN_EN == 1'b1 && SO_IN_EN == 1'b1 ) begin - SI_Reg[23:0] = {SI_Reg[21:0], SO, SI}; - end - else begin - SI_Reg[23:0] = {SI_Reg[22:0], SI}; - end - end - if ( Bit == 7 && CS == 1'b0 ) begin - STATE = `CMD_STATE; - CMD_BUS = SI_Reg[7:0]; - //$display( $time,"SI_Reg[7:0]= %h ", SI_Reg[7:0] ); - end - - case ( STATE ) - `STANDBY_STATE: - begin - end - - `CMD_STATE: - begin - case ( CMD_BUS ) - WREN: - begin - if ( !DP_Mode && !EN_CP_Mode && !WIP && Write_EN ) begin - if ( CS == 1'b1 && Bit == 7 ) begin - // $display( $time, " Enter Write Enable Function ..." ); - write_enable; - end - else if ( Bit > 7 ) - STATE <= `BAD_CMD_STATE; - end - else if ( Bit == 7 ) - STATE <= `BAD_CMD_STATE; - end - - WRDI: - begin - if ( !DP_Mode && !WIP && Read_EN ) begin - if ( CS == 1'b1 && Bit == 7 ) begin - // $display( $time, " Enter Write Disable Function ..." ); - write_disable; - end - else if ( Bit > 7 ) - STATE <= `BAD_CMD_STATE; - end - else if ( Bit == 7 ) - STATE <= `BAD_CMD_STATE; - end - - RDID: - begin - if ( !DP_Mode && !EN_CP_Mode && !WIP && Read_EN) begin - //$display( $time, " Enter Read ID Function ..." ); - read_id; - end - else if ( Bit == 7 ) - STATE <= `BAD_CMD_STATE; - end - - RDSR: - begin - if ( !DP_Mode && (EN_CP_Mode && CP_ESRY_Mode) == 1'b0 && Read_EN) begin - //$display( $time, " Enter Read Status Function ..." ); - read_status ; - end - else if ( Bit == 7 ) - STATE <= `BAD_CMD_STATE; - end - - WRSR: - begin - if ( !DP_Mode && !EN_CP_Mode && !WIP && WEL && Write_EN ) begin - if ( CS == 1'b1 && Bit == 15 && !Dis_WRSR ) begin - //$display( $time, " Enter Write Status Function ..." ); - ->WRSR_Event; - WRSR_Mode = 1'b1; - end - else if ( CS == 1'b1 && Bit < 15 || Bit > 15 ) - STATE <= `BAD_CMD_STATE; - end - else if ( Bit == 7 ) - STATE <= `BAD_CMD_STATE; - end - - READ1X: - begin - if ( !DP_Mode && !EN_CP_Mode && !WIP && Read_EN ) begin - //$display( $time, " Enter Read Data Function ..." ); - if ( Bit == 31 ) begin - Address = (Secur_Mode == 1) ? SI_Reg[5:0] : SI_Reg[A_MSB:0]; - end - Read_1XIO_Mode = 1'b1; - end - else if ( Bit == 7 ) - STATE <= `BAD_CMD_STATE; - end - - - FASTREAD1X: - begin - if ( !DP_Mode && !EN_CP_Mode && !WIP && Read_EN ) begin - //$display( $time, " Enter Fast Read Data Function ..." ); - if ( Bit == 31 ) begin - Address = (Secur_Mode == 1) ? SI_Reg[5:0] : SI_Reg[A_MSB:0]; - end - FastRD_1XIO_Mode = 1'b1; - end - else if ( Bit == 7 ) - STATE <= `BAD_CMD_STATE; - end - SE: - begin - if ( !DP_Mode && !EN_CP_Mode && !WIP && WEL && !Secur_Mode && Write_EN ) begin - if ( Bit == 31 ) begin - Address = SI_Reg[A_MSB:0]; - end - if ( CS == 1'b1 && Bit == 31 && write_protect(Address) == 1'b0 ) begin - //$display( $time, " Enter Sector Erase Function ..." ); - if ( (Param_Reg[0] == 1) && (Address[A_MSB:12] == 0) ) begin - ->SE_1K_Event; - SE_1K_Mode = 1'b1; - end - else begin - ->SE_4K_Event; - SE_4K_Mode = 1'b1; - end - end - else if ( CS == 1'b1 && Bit < 31 || Bit > 31 ) - STATE <= `BAD_CMD_STATE; - end - else if ( Bit == 7 ) - STATE <= `BAD_CMD_STATE; - end - - BE: - begin - if ( !DP_Mode && !EN_CP_Mode && !WIP && WEL && !Secur_Mode && Write_EN ) begin - if ( Bit == 31 ) begin - Address = SI_Reg[A_MSB:0] ; - end - if ( CS == 1'b1 && Bit == 31 && write_protect(Address) == 1'b0 ) begin - //$display( $time, " Enter Block Erase Function ..." ); - ->BE_Event; - BE_Mode = 1'b1; - end - else if ( CS == 1'b1 && Bit < 31 || Bit > 31 ) - STATE <= `BAD_CMD_STATE; - end - else if ( Bit == 7 ) - STATE <= `BAD_CMD_STATE; - end - - CE1, CE2: - begin - if ( !DP_Mode && !EN_CP_Mode && !WIP && WEL && !Secur_Mode && Write_EN ) begin - - if ( CS == 1'b1 && Bit == 7 && Dis_CE == 0 ) begin - //$display( $time, " Enter Chip Erase Function ..." ); - ->CE_Event; - CE_Mode = 1'b1 ; - end - else if ( Bit > 7 ) - STATE <= `BAD_CMD_STATE; - end - else if ( Bit == 7 ) - STATE <= `BAD_CMD_STATE; - end - - PP: - begin - if ( !DP_Mode && !EN_CP_Mode && !WIP && WEL && Write_EN ) begin - if ( Bit == 31 ) begin - Address = (Secur_Mode == 1) ? SI_Reg[5:0] : SI_Reg[A_MSB:0]; - end - - if ( Bit == 31 && (((write_protect(Address) == 1'b0) && (!Secur_Mode)) || - (Secur_Mode && (!(Secur_Reg[1] || Secur_Reg[0])))) ) begin - //$display( $time, " Enter Page Program Function ..." ); - ->PP_Event; - PP_1XIO_Mode = 1'b1; - end - else if ( CS == 1 && (Bit < 31 || ((Bit + 1) % 8 !== 0))) - STATE <= `BAD_CMD_STATE; - end - else if ( Bit == 7 ) - STATE <= `BAD_CMD_STATE; - end - - DP: - begin - if ( !WIP && !EN_CP_Mode && Read_EN ) begin - if ( CS == 1'b1 && Bit == 7 ) begin - //$display( $time, " Enter Deep Power Dwon Function ..." ); - ->DP_Event; - end - else if ( Bit > 7 ) - STATE <= `BAD_CMD_STATE; - end - else if ( Bit == 7 ) - STATE <= `BAD_CMD_STATE; - end - - - RDP, RES: - begin - if ( !WIP && !EN_CP_Mode && Read_EN ) begin - // $display( $time, " Enter Release from Deep Power Dwon Function ..." ); - RES_Mode = 1'b1; - if ( CS == 1'b1 ) begin - if ( Bit >= 38 ) begin - tRES = tRES2; - end - else begin - tRES = tRES1; - end - ->RDP_Event; - end - end - else if ( Bit == 7 ) - STATE <= `BAD_CMD_STATE; - end - - REMS, REMS2: - begin - if ( !DP_Mode && !EN_CP_Mode && !WIP && Read_EN ) begin - if ( Bit == 31 ) begin - Address = SI_Reg[A_MSB:0] ; - end - //$display( $time, " Enter Read Electronic Manufacturer & ID Function ..." ); - REMS_Mode = 1'b1; - end - else if ( Bit == 7 ) - STATE <= `BAD_CMD_STATE; - end - - WRPR: - begin - if ( !DP_Mode && !EN_CP_Mode && !WIP && WEL && Write_EN ) begin - if ( CS == 1'b1 && Bit == 15 ) begin - //$display( $time, " Enter Write Parameter Register Function ..." ); - write_parameter; - end - else if ( CS == 1'b1 && Bit < 15 || Bit > 15 ) - STATE <= `BAD_CMD_STATE; - end - else if ( Bit == 7 ) - STATE <= `BAD_CMD_STATE; - end - - RDPR: - begin - if ( !DP_Mode && (EN_CP_Mode && CP_ESRY_Mode) == 1'b0 && Read_EN) begin - //$display( $time, " Enter READ Parameter Register Function ..." ); - read_parameter; - end - else if ( Bit == 7 ) - STATE <= `BAD_CMD_STATE; - end - - READ2X: - begin - if ( !DP_Mode && !EN_CP_Mode && !WIP && Read_EN ) begin - //$display( $time, " Enter READX2 Function ..." ); - if ( Bit == 19 ) begin - Address = (Secur_Mode == 1) ? SI_Reg[5:0] : SI_Reg[A_MSB:0]; - end - Read_2XIO_Mode = 1'b1; - end - else if ( Bit == 7 ) - STATE <= `BAD_CMD_STATE; - end - - - CP: - begin - if ( !DP_Mode && !WIP && WEL && Write_EN ) begin - if ( EN_CP_Mode == 1'b0 && Bit == 31 ) begin - Address = (Secur_Mode == 1) ? SI_Reg[5:0] : SI_Reg[A_MSB:0]; - Address = {Address [A_MSB:1], 1'b0} ; - end - if ( ((EN_CP_Mode == 1'b0 && Bit == 47) || (EN_CP_Mode == 1'b1 && Bit == 23)) && - (( (write_protect(Address) == 1'b0 && (!Secur_Mode)) || - (Secur_Mode && (!(Secur_Reg[1] || Secur_Reg[0]))))) ) begin - //$display( $time, " Enter CP Mode Function ..." ); - ->CP_Event; - end - else if ( CS == 1'b1 && ((EN_CP_Mode == 1'b0 && Bit < 47) || - (EN_CP_Mode == 1'b1 && Bit < 23) || ((Bit + 1) % 8 !== 0))) - STATE <= `BAD_CMD_STATE; - end - else if ( Bit == 7 ) - STATE <= `BAD_CMD_STATE; - end - - WRLB: - begin - if ( !DP_Mode && !EN_CP_Mode && !WIP && WEL && `PADOP1 && Read_EN ) begin - if ( CS == 1'b1 && Bit == 15 ) begin - //$display( $time, " Enter WRLB Function ..." ); - write_lkbit; - end - else if ( CS == 1'b1 && Bit < 15 || Bit >15) - STATE <= `BAD_CMD_STATE; - end - else if ( Bit == 7 ) - STATE <= `BAD_CMD_STATE; - end - - ENSO: - begin - if ( !DP_Mode && !EN_CP_Mode && !WIP && Read_EN ) begin - - if ( CS == 1'b1 && Bit == 7 ) begin - //$display( $time, " Enter ENSO Function ..." ); - enter_secured_otp; - end - else if ( Bit > 7 ) - STATE <= `BAD_CMD_STATE; - end - else if ( Bit == 7 ) - STATE <= `BAD_CMD_STATE; - end - - EXSO: - begin - if ( !DP_Mode && !EN_CP_Mode && !WIP && Read_EN ) begin - if ( CS == 1'b1 && Bit == 7 ) begin - //$display( $time, " Enter EXSO Function ..." ); - exit_secured_otp; - end - else if ( Bit > 7 ) - STATE <= `BAD_CMD_STATE; - end - else if ( Bit == 7 ) - STATE <= `BAD_CMD_STATE; - end - - RDSCUR: - begin - if ( !DP_Mode && (EN_CP_Mode && CP_ESRY_Mode) == 1'b0 && Read_EN) begin - // $display( $time, " Enter Read Secur_Register Function ..." ); - read_Secur_Register; - end - else if ( Bit == 7 ) - STATE <= `BAD_CMD_STATE; - end - - - WDSCUR: - begin - if ( !DP_Mode && !EN_CP_Mode && !WIP && !Secur_Mode && Write_EN ) begin - if ( CS == 1'b1 && Bit == 7 ) begin - //$display( $time, " Enter WDSCUR Secur_Register Function ..." ); - ->WRSCUR_Event; - end - else if ( Bit > 7 ) - STATE <= `BAD_CMD_STATE; - end - else if ( Bit == 7 ) - STATE <= `BAD_CMD_STATE; - end - - ESRY: - begin - if ( !DP_Mode && !EN_CP_Mode && !WIP && Read_EN ) begin - if ( CS == 1'b1 && Bit == 7 ) begin - //$display( $time, " Enter ESRY Function ..." ); - read_ryby; - end - else if ( Bit > 7 ) - STATE <= `BAD_CMD_STATE; - end - else if ( Bit == 7 ) - STATE <= `BAD_CMD_STATE; - end - - DSRY: - begin - if ( !DP_Mode && !EN_CP_Mode && !WIP && Read_EN ) begin - if ( CS == 1'b1 && Bit == 7 ) begin - //$display( $time, " Enter DSRY Function ..." ); - disread_ryby; - end - else if ( Bit > 7 ) - STATE <= `BAD_CMD_STATE; - end - else if ( Bit == 7 ) - STATE <= `BAD_CMD_STATE; - end - default: - begin - STATE <= `BAD_CMD_STATE; - end - endcase - end - - `BAD_CMD_STATE: - begin - end - - default: - begin - STATE = `STANDBY_STATE; - end - endcase - - - if ( CS == 1'b1 ) begin - Bit = 1'b0; - Bit_Tmp = 1'b0; - SO_IN_EN = 1'b0; - SI_IN_EN = 1'b0; - - SO_OUT_EN <= #tSHQZ 1'b0; - SI_OUT_EN <= #tSHQZ 1'b0; - - Read_Mode = 1'b0; - RES_Mode = 1'b0; - REMS_Mode = 1'b0; - Read_1XIO_Mode = 1'b0; - Read_2XIO_Mode = 1'b0; - Read_1XIO_Chk = 1'b0; - Read_2XIO_Chk = 1'b0; - - FastRD_1XIO_Mode = 1'b0; - STATE <= #1 `STANDBY_STATE; - SIO0_Reg <= #tSHQZ 1'bx; - SIO1_Reg <= #tSHQZ 1'bx; - PO_Reg[6:0] <= #tSHQZ 7'bx; - #1; - disable read_1xio; - disable read_2xio; - disable fastread_1xio; - disable read_electronic_id; - disable read_electronic_manufacturer_device_id; - disable read_function; - disable dummy_cycle; - end - - end - - - - - - /*----------------------------------------------------------------------*/ - /* ALL function trig action */ - /*----------------------------------------------------------------------*/ - always @ ( posedge Read_1XIO_Mode - or posedge FastRD_1XIO_Mode - or posedge REMS_Mode - or posedge RES_Mode - or posedge Read_2XIO_Mode - ) begin:read_function - wait ( ISCLK == 1'b0 ); - - if ( Read_1XIO_Mode == 1'b1 ) begin - Read_1XIO_Chk = 1'b1; - read_1xio; - end - else if ( FastRD_1XIO_Mode == 1'b1 ) begin - fastread_1xio; - end - else if ( REMS_Mode == 1'b1 ) begin - read_electronic_manufacturer_device_id; - end - else if ( RES_Mode == 1'b1 ) begin - read_electronic_id; - end - - else if ( Read_2XIO_Mode == 1'b1 ) begin - Read_2XIO_Chk = 1'b1; - read_2xio; - end - end - - always @ ( WRSR_Event ) begin - write_status; - end - - always @ ( RDP_Event ) begin - disable deep_power_down; - release_from_deep_power_down; - end - - always @ ( DP_Event ) begin - deep_power_down; - end - - always @ ( BE_Event ) begin - block_erase; - end - - always @ ( CE_Event ) begin - chip_erase; - end - - always @ ( PP_Event ) begin:page_program_mode - page_program( Address ); - end - - always @ ( SE_4K_Event ) begin - sector_erase_4k; - end - - always @ ( CP_Event ) begin - cp_program; - end - - always @ ( WRSCUR_Event ) begin - write_secur_register; - end - always @ ( SE_1K_Event ) begin - sector_erase_1k; - end - - - -// *========================================================================================== -// * Module Task Declaration -// *========================================================================================== - /*----------------------------------------------------------------------*/ - /* Description: define a wait dummy cycle task */ - /* INPUT */ - /* Cnum: cycle number */ - /*----------------------------------------------------------------------*/ - task dummy_cycle; - input [31:0] Cnum; - begin - repeat( Cnum ) begin - @ ( posedge ISCLK ); - end - end - endtask // dummy_cycle - - /*----------------------------------------------------------------------*/ - /* Description: define a write enable task */ - /*----------------------------------------------------------------------*/ - task write_enable; - begin - //$display( $time, " Old Status Register = %b", Status_Reg ); - Status_Reg[1] = 1'b1; - // $display( $time, " New Status Register = %b", Status_Reg ); - end - endtask // write_enable - - /*----------------------------------------------------------------------*/ - /* Description: define a write disable task (WRDI) */ - /*----------------------------------------------------------------------*/ - task write_disable; - begin - //$display( $time, " Old Status Register = %b", Status_Reg ); - Status_Reg[1] = 1'b0; - EN_CP_Mode = 1'b0; - Status_Reg[6] = 1'b0; - //$display( $time, " New Status Register = %b", Status_Reg ); - end - endtask // write_disable - - /*----------------------------------------------------------------------*/ - /* Description: define a read id task (RDID) */ - /*----------------------------------------------------------------------*/ - task read_id; - reg [23:0] Dummy_ID; - integer Dummy_Count; - begin - Dummy_ID = {ID_MXIC, Memory_Type, Memory_Density}; - Dummy_Count = 0; - forever begin - @ ( negedge ISCLK or posedge CS ); - if ( CS == 1'b1 ) begin - disable read_id; - end - else begin - SO_OUT_EN = 1'b1; - if ( P_Mode == 1'b0 ) begin // check parallel mode (2) - {SIO1_Reg, Dummy_ID} <= #tCLQV {Dummy_ID, Dummy_ID[23]}; - end - else begin - if ( Dummy_Count == 0 ) begin - {SIO1_Reg,PO_Reg} <= #tAA ID_MXIC; - Dummy_Count = 1; - end - else if ( Dummy_Count == 1 ) begin - {SIO1_Reg,PO_Reg} <= #tAA Memory_Type; - Dummy_Count = 2; - end - else if ( Dummy_Count == 2 ) begin - {SIO1_Reg,PO_Reg} <= #tAA Memory_Density; - Dummy_Count = 0; - end - end - end - end // end forever - end - endtask // read_id - - /*----------------------------------------------------------------------*/ - /* Description: define a read status task (RDSR) */ - /*----------------------------------------------------------------------*/ - task read_status; - integer Dummy_Count; - begin - Dummy_Count = 8; - forever begin - @ ( negedge ISCLK or posedge CS ); - if ( CS == 1'b1 ) begin - disable read_status; - end - else begin - SO_OUT_EN = 1'b1; - if ( P_Mode == 1'b0 ) begin - if ( Dummy_Count ) begin - Dummy_Count = Dummy_Count - 1; - SIO1_Reg <= #tCLQV Status_Reg[Dummy_Count]; - end - else begin - Dummy_Count = 7; - SIO1_Reg <= #tCLQV Status_Reg[Dummy_Count]; - end - end - else begin - {SIO1_Reg,PO_Reg} <= #tAA Status_Reg; - end - end - end // end forever - end - endtask // read_status - - - /*----------------------------------------------------------------------*/ - /* Description: define a write status task */ - /*----------------------------------------------------------------------*/ - task write_status; - integer tWRSR; - reg [7:0] Status_Reg_Up; - begin - //$display( $time, " Old Status Register = %b", Status_Reg ); - Status_Reg_Up = SI_Reg[7:0] ; - if ( (Status_Reg[7] == Status_Reg_Up[7] ) - && (Status_Reg[5:2] == Status_Reg_Up[5:2] ) ) begin - Status_Reg[1] = 1'b0; - WRSR_Mode = 1'b0; - end - else begin - if ( (Status_Reg[7] == 1'b1 && Status_Reg_Up[7] == 1'b0 ) || - (Status_Reg[5] == 1'b1 && Status_Reg_Up[5] == 1'b0 ) || - (Status_Reg[4] == 1'b1 && Status_Reg_Up[4] == 1'b0 ) || - (Status_Reg[3] == 1'b1 && Status_Reg_Up[3] == 1'b0 ) || - (Status_Reg[2] == 1'b1 && Status_Reg_Up[2] == 1'b0 )) - tWRSR = tW; - else - tWRSR = tBP; - //SRWD:Status Register Write Protect - Status_Reg[0] = 1'b1; - #tWRSR; - Status_Reg[7] = Status_Reg_Up[7]; - Status_Reg[6:2] = Status_Reg_Up[6:2]; - //WIP:Write Enable Latch - Status_Reg[0] = 1'b0; - //WEL:Write Enable Latch - Status_Reg[1] = 1'b0; - WRSR_Mode = 1'b0; - end - - if ( Status_Reg[4] == 0 || Status_Reg[3] == 0 || Status_Reg [2] == 0 ) begin//BP2~0 not all 1 - Param_Reg = 8'h00; - end - end - endtask // write_status - - /*----------------------------------------------------------------------*/ - /* Description: define a read data task */ - /*----------------------------------------------------------------------*/ - task read_1xio; - integer Dummy_Count, Tmp_Int; - reg [7:0] OUT_Buf; - begin - Dummy_Count = 8; - dummy_cycle(24); - #1; - OUT_Buf = (Secur_Mode == 1) ? Secur_ARRAY[Address] : - ((read_protect(Address) == 1'b1) ? 8'b0 : ARRAY[Address] ); - forever begin - @ ( negedge ISCLK or posedge CS ); - if ( CS == 1'b1 ) begin - if ( P_Mode == 0 ) begin - {EN_S0, EN_P0, EN_S1, EN_P1} = {1'b1, 1'b0, 1'b0, 1'b0}; - end - else begin - {EN_S0, EN_P0, EN_S1, EN_P1} = {1'b0, 1'b1, 1'b0, 1'b0}; - end - disable read_1xio; - end - else begin //do work on non deep power down mode - Read_Mode = 1'b1; - SO_OUT_EN = 1'b1; - if ( P_Mode == 1'b0 ) begin - {EN_S0, EN_P0, EN_S1, EN_P1} = {1'b0, 1'b0, 1'b1, 1'b0}; - if ( Dummy_Count ) begin - {SIO1_Reg, OUT_Buf} <= #tCLQV {OUT_Buf, OUT_Buf[7]}; - Dummy_Count = Dummy_Count - 1; - end - else begin - Address = Address + 1; - Address = (Secur_Mode == 1) ? Address[5:0] : Address; - OUT_Buf = (Secur_Mode == 1) ? Secur_ARRAY[Address] - :((read_protect(Address) == 1'b1) ? 8'b0 : ARRAY[Address] ); - {SIO1_Reg, OUT_Buf} <= #tCLQV {OUT_Buf, OUT_Buf[7]}; - Dummy_Count = 7 ; - end - end - else begin - {EN_S0, EN_P0, EN_S1, EN_P1} = {1'b0, 1'b0, 1'b0, 1'b1}; - OUT_Buf = (Secur_Mode == 1) ? Secur_ARRAY[Address] - :((read_protect(Address) == 1'b1) ? 8'b0 : ARRAY[Address] ); - {SIO1_Reg,PO_Reg} <= #tCLQV {OUT_Buf}; - Address = Address + 1; - Address = (Secur_Mode == 1) ? Address[5:0] : Address; - end - end - end // end forever - end - endtask // read_1xio - - /*----------------------------------------------------------------------*/ - /* Description: define a fast read data task */ - /* 0B AD1 AD2 AD3 X */ - /*----------------------------------------------------------------------*/ - task fastread_1xio; - integer Dummy_Count, Tmp_Int; - reg [7:0] OUT_Buf; - begin - Dummy_Count = 8; - dummy_cycle(24); - dummy_cycle(8); - OUT_Buf = (Secur_Mode == 1) ? Secur_ARRAY[Address]: - ((read_protect(Address) == 1'b1) ? 8'b0 : ARRAY[Address] ); - - forever begin - @ ( negedge ISCLK or posedge CS ); - if ( CS == 1'b1 ) begin - disable fastread_1xio; - end - else begin //do work on non deep power down mode - Read_Mode = 1'b1; - SO_OUT_EN = 1'b1; - if ( Dummy_Count ) begin - {SIO1_Reg, OUT_Buf} <= #tCLQV {OUT_Buf, OUT_Buf[7]}; - Dummy_Count = Dummy_Count - 1; - end - else begin - Address = Address + 1; - Address = (Secur_Mode == 1) ? Address[5:0] : Address; - OUT_Buf = (Secur_Mode == 1) ? Secur_ARRAY[Address] - :((read_protect(Address) == 1'b1) ? 8'b0 : ARRAY[Address] ); - {SIO1_Reg, OUT_Buf} <= #tCLQV {OUT_Buf, OUT_Buf[7]}; - Dummy_Count = 7 ; - end - end - end // end forever - end - endtask // fastread_1xio - /*----------------------------------------------------------------------*/ - /* Description: define a block erase task */ - /* D8 AD1 AD2 AD3 */ - /*----------------------------------------------------------------------*/ - task block_erase; - reg [Block_MSB:0] Block; - integer i; - begin - Block = Address[A_MSB:16]; - Start_Add = (Address[A_MSB:16]<<16) + 16'h0; - End_Add = (Address[A_MSB:16]<<16) + 16'hffff; - //WIP : write in process Bit - Status_Reg[0] = 1'b1; - #tBE ; - for( i = Start_Add; i <= End_Add; i = i + 1 ) - begin - ARRAY[i] = 8'hff; - end - //WIP : write in process Bit - Status_Reg[0] = 1'b0;//WIP - //WEL : write enable latch - Status_Reg[1] = 1'b0;//WEL - BE_Mode = 1'b0; - end - endtask // block_erase - - /*----------------------------------------------------------------------*/ - /* Description: define a sector 4k erase task */ - /* 20(D8) AD1 AD2 AD3 */ - /*----------------------------------------------------------------------*/ - task sector_erase_4k; - integer i; - begin - Sector = Address[A_MSB:12]; - Start_Add = (Address[A_MSB:12]<<12) + 12'h000; - End_Add = (Address[A_MSB:12]<<12) + 12'hfff; - //WIP : write in process Bit - - Status_Reg[0] = 1'b1; - #tSE; - for( i = Start_Add; i <= End_Add; i = i + 1 ) - begin - ARRAY[i] = 8'hff; - end - //WIP : write in process Bit - Status_Reg[0] = 1'b0;//WIP - //WEL : write enable latch - Status_Reg[1] = 1'b0;//WEL - SE_4K_Mode = 1'b0; - - end - endtask // sector_erase_4k - - /*----------------------------------------------------------------------*/ - /* Description: define a sector 1k erase task */ - /* 20(D8) AD1 AD2 AD3 */ - /*----------------------------------------------------------------------*/ - task sector_erase_1k; - reg [1:0] SEC_1K; - integer i; - begin - SEC_1K = Address[11:10]; - Start_Add = (Address[A_MSB:10]<<10) + 12'h000; - End_Add = (Address[A_MSB:10]<<10) + 12'h3ff; - //WIP : write in process Bit - Status_Reg[0] = 1'b1; - #tSE - for( i = Start_Add; i <= End_Add; i = i + 1 ) - begin - ARRAY[i] = 8'hff; - end - //WIP : write in process Bit - Status_Reg[0] = 1'b0;//WIP - //WEL : write enable latch - Status_Reg[1] = 1'b0;//WEL - SE_1K_Mode = 1'b0; - end - endtask // sector_erase_1k - - /*----------------------------------------------------------------------*/ - /* Description: define a chip erase task */ - /* 60(C7) */ - /*----------------------------------------------------------------------*/ - - task chip_erase; - begin - Status_Reg[0] = 1'b1; - for ( i = 0;i 8 ) - Byte_PGM_Mode = 1'b0; - else - Byte_PGM_Mode = 1'b1; - update_array ( Address ); - end - disable page_program; - end - else begin // count how many Bits been shifted - if ( P_Mode == 1'b0 ) begin - Tmp_Int = Tmp_Int + 1; - if ( Tmp_Int % 8 == 0) begin - #1; - Dummy_A[Offset] = SI_Reg [7:0]; - Offset = Offset + 1; - Offset = (Secur_Mode == 1) ? Offset[5:0] : Offset[7:0]; - end - end - else begin - Tmp_Int = Tmp_Int + 8; - if ( Tmp_Int % 8 == 0) begin - #1; - Dummy_A[Offset] = {Latch_SO, Latch_PO}; - Offset = Offset + 1; - Offset = (Secur_Mode == 1) ? Offset[5:0] : Offset[7:0]; - end - end - end - end // end forever - end - endtask // page_program - /*----------------------------------------------------------------------*/ - /* Description: define a deep power down (DP) */ - /*----------------------------------------------------------------------*/ - task deep_power_down; - begin - //$display( $time, " Old DP Mode Register = %b", DP_Mode ); - if ( DP_Mode == 1'b0) - DP_Mode = #tDP 1'b1; - //$display( $time, " New DP Mode Register = %b", DP_Mode ); - end - endtask // deep_power_down - - /*----------------------------------------------------------------------*/ - /* Description: define a release from deep power dwon task (RDP) */ - /*----------------------------------------------------------------------*/ - task release_from_deep_power_down; - begin - //$display( $time, " Old DP Mode Register = %b", DP_Mode ); - if ( DP_Mode == 1'b1) - DP_Mode = #tRES 1'b0; - //$display( $time, " New DP Mode Register = %b", DP_Mode ); - end - endtask // release_from_deep_power_down - - /*----------------------------------------------------------------------*/ - /* Description: define a read electronic ID (RES) */ - /* AB X X X */ - /*----------------------------------------------------------------------*/ - task read_electronic_id; - reg [7:0] Dummy_ID; - begin - //$display( $time, " Old DP Mode Register = %b", DP_Mode ); - dummy_cycle(23); - Dummy_ID = ID_Device; - dummy_cycle(1); - - forever begin - @ ( negedge ISCLK or posedge CS ); - if ( CS == 1'b1 ) begin - disable read_electronic_id; - end - else begin - SO_OUT_EN = 1'b1; - if ( P_Mode == 1'b0 ) begin - {SIO1_Reg, Dummy_ID} <= #tCLQV {Dummy_ID, Dummy_ID[7]}; - end - else begin - {SIO1_Reg,PO_Reg} <= #tAA ID_Device; - end - end - end // end forever - end - endtask // read_electronic_id - - /*----------------------------------------------------------------------*/ - /* Description: define a read electronic manufacturer & device ID */ - /*----------------------------------------------------------------------*/ - task read_electronic_manufacturer_device_id; - reg [15:0] Dummy_ID; - integer Dummy_Count; - begin - dummy_cycle(24); - #1; - if ( Address[0] == 1'b0 ) begin - Dummy_ID = {ID_MXIC,ID_Device}; - end - else begin - Dummy_ID = {ID_Device,ID_MXIC}; - end - Dummy_Count = 0; - forever begin - @ ( negedge ISCLK or posedge CS ); - if ( CS == 1'b1 ) begin - disable read_electronic_manufacturer_device_id; - end - else begin - SO_OUT_EN = 1'b1; - if ( P_Mode == 1'b0 ) begin // check parallel mode (2) - {SIO1_Reg, Dummy_ID} <= #tCLQV {Dummy_ID, Dummy_ID[15]}; - end - else if ( P_Mode == 1'b1 ) begin - if ( Dummy_Count == 0 ) begin - {SIO1_Reg,PO_Reg} <= #tAA Dummy_ID[15:8]; - Dummy_Count = 1; - end - else begin - {SIO1_Reg,PO_Reg} <= #tAA Dummy_ID[7:0]; - Dummy_Count = 0; - end - end - end - end // end forever - end - endtask // read_electronic_manufacturer_device_id - - /*----------------------------------------------------------------------*/ - /* Description: define a program chip task */ - /* INPUT program_time */ - /* segment: segment address */ - /* offset : offset address */ - /*----------------------------------------------------------------------*/ - task update_array; - input [A_MSB:0] Address; - integer Dummy_Count; - integer program_time; - begin - Dummy_Count = Page_Size; - Address = { Address [A_MSB:8], 8'h0 }; - program_time = (Byte_PGM_Mode) ? tBP : tPP; - Status_Reg[0]= 1'b1; - #program_time ; - for ( i = 0; i < Dummy_Count; i = i + 1 ) begin - if ( Secur_Mode == 1'b1) - Secur_ARRAY[Address + i] = Secur_ARRAY[Address + i] & Dummy_A[i]; - else - ARRAY[Address+ i] = ARRAY[Address + i] & Dummy_A[i]; - end - - - Status_Reg[0] = 1'b0; - Status_Reg[1] = 1'b0; - PP_1XIO_Mode = 1'b0; - Byte_PGM_Mode = 1'b0; - end - endtask // update_array - - /*----------------------------------------------------------------------*/ - /* Description: define a write read-lock register task */ - /*----------------------------------------------------------------------*/ - task write_lkbit; - begin - if ( SI_Reg[2] == 1 ) begin - Secur_Reg[2] <= SI_Reg[2]; - end - if ( SI_Reg[3] == 1 ) begin - Secur_Reg[3] <= SI_Reg[3]; - end - Status_Reg[1]<=1'b0; - end - endtask // write_lkbit - - /*----------------------------------------------------------------------*/ - /* Description: define a enter secured OTP task */ - /*----------------------------------------------------------------------*/ - task enter_secured_otp; - begin - //$display( $time, " Enter secured OTP mode = %b", enter_Secur_Mode ); - Secur_Mode= 1; - //$display( $time, " New Enter secured OTP mode = %b", enter_Secur_Mode ); - end - endtask // enter_secured_otp - - /*----------------------------------------------------------------------*/ - /* Description: define a exit 512 secured OTP task */ - /*----------------------------------------------------------------------*/ - task exit_secured_otp; - begin - //$display( $time, " Enter 512 secured OTP mode = %b", enter_Secur_Mode ); - Secur_Mode = 0; - //$display( $time, " New Enter 512 secured OTP mode = %b", enter_Secur_Mode ); - end - endtask - - /*----------------------------------------------------------------------*/ - /* Description: Execute Reading Security Register */ - /*----------------------------------------------------------------------*/ - task read_Secur_Register; - integer Dummy_Count; - begin - Dummy_Count = 8; - forever @ ( negedge ISCLK or posedge CS ) begin // output security register info - if ( CS == 1 ) begin - disable read_Secur_Register; - end - else begin //do work on non deep power down mode and not in CP_Mode with hardware detection - SO_OUT_EN = 1'b1; - if ( P_Mode == 1'b0 ) begin - if ( Dummy_Count ) begin - Dummy_Count = Dummy_Count - 1; - SIO1_Reg <= #tCLQV Secur_Reg[Dummy_Count]; - end - else begin - Dummy_Count = 7; - SIO1_Reg <= #tCLQV Secur_Reg[Dummy_Count]; - end - end - else begin - {SIO1_Reg,PO_Reg} <= #tAA Secur_Reg; - end - end - end - end - endtask // read_Secur_Register - - /*----------------------------------------------------------------------*/ - /* Description: Execute Write Security Register */ - /*----------------------------------------------------------------------*/ - task write_secur_register; - begin - Status_Reg[0] = 1'b1; - #tBP; - Secur_Reg [1] = 1'b1; - Status_Reg[0] = 1'b0; - end - endtask // write_secur_register - - /*----------------------------------------------------------------------*/ - /* Description: define a continuously program task */ - /* 02 AD1 AD2 AD3 */ - /*----------------------------------------------------------------------*/ - task cp_program; - integer Tmp_Int; - begin - CP_Data = SI_Reg[15:0] ; - Tmp_Int = 0; - forever begin - @ ( posedge ISCLK or posedge CS ); - if ( CS == 1'b1 ) begin - if ( P_Mode == 1'b0 && Tmp_Int % 8 !== 0 ) begin - disable cp_program; - end - else begin - EN_CP_Mode = 1'b1; - CP_Mode = 1'b1; - Status_Reg[6] = EN_CP_Mode; - Status_Reg[0] = 1'b1; - #tBP; - Status_Reg[0]= 1'b0; - CP_Mode = 1'b0; - if ( Secur_Mode == 1) - begin - Secur_ARRAY[Address + 1] = Secur_ARRAY[Address + 1] & CP_Data [7:0]; - Secur_ARRAY[Address] = Secur_ARRAY[Address] & CP_Data [15:8]; - end - else - begin - ARRAY[Address + 1] = ARRAY[Address + 1] & CP_Data [7:0]; - ARRAY[Address] = ARRAY[Address] & CP_Data [15:8]; - end - - if ( Address == (Secur_Mode ? (Secur_TOP_Add - 1) : (TOP_Add - 1))) - begin - Status_Reg[6] = 1'b0; - Status_Reg[1] = 1'b0; - EN_CP_Mode = 1'b0; - end - else - begin - Address = Address + 2; - end - if ( write_protect(Address) == 1'b1 && (!Secur_Mode) ) - begin - Status_Reg[6] = 1'b0; - Status_Reg[1] = 1'b0; - EN_CP_Mode = 1'b0; - end - end - disable cp_program; - end - else begin // count how many Bits been shifted - if ( P_Mode == 1'b0 ) begin - Tmp_Int = Tmp_Int + 1; - end - else begin - Tmp_Int = Tmp_Int + 8; - end - end - end // end forever - end - endtask // cp_program - - /*----------------------------------------------------------------------*/ - /* Description: define a ESRY task */ - /*----------------------------------------------------------------------*/ - task read_ryby; - begin - //$display( $time, " Enter CP ESRY mode = %b", CP_ESRY_Mode ); - CP_ESRY_Mode= 1; - //$display( $time, " New Enter CP ESRY mode = %b", CP_ESRY_Mode ); - end - endtask // read_ryby - - /*----------------------------------------------------------------------*/ - /* Description: define a DSRY task */ - /*----------------------------------------------------------------------*/ - task disread_ryby; - begin - //$display( $time, " Enter CP ESRY mode = %b", CP_ESRY_Mode ); - CP_ESRY_Mode = 0; - //$display( $time, " New Enter CP ESRY mode = %b", CP_ESRY_Mode ); - end - endtask // disread_ryby - - /*----------------------------------------------------------------------*/ - /* Description: Execute 2X IO Read Mode */ - /*----------------------------------------------------------------------*/ - task read_2xio; - reg [7:0] OUT_Buf; - integer Dummy_Count; - begin - Dummy_Count=4; - SI_IN_EN = 1'b1; - SO_IN_EN = 1'b1; - SI_OUT_EN = 1'b0; - SO_OUT_EN = 1'b0; - dummy_cycle(12); - dummy_cycle(4); - OUT_Buf = (Secur_Mode == 1) ? Secur_ARRAY[Address] : - ((read_protect(Address) == 1'b1) ? 8'b0 : ARRAY[Address] ); - - forever @ ( negedge ISCLK or posedge CS ) begin - if ( CS == 1'b1 ) begin - disable read_2xio; - end - else begin - Read_Mode = 1'b1; - SO_OUT_EN = 1'b1; - SI_OUT_EN = 1'b1; - SI_IN_EN = 1'b0; - SO_IN_EN = 1'b0; - if ( Dummy_Count ) begin - {SIO1_Reg, SIO0_Reg, OUT_Buf} <= #tCLQV {OUT_Buf, OUT_Buf[1:0]}; - Dummy_Count = Dummy_Count - 1; - end - else begin - Address = Address + 1; - Address = (Secur_Mode == 1) ? Address[5:0] : Address; - OUT_Buf = (Secur_Mode == 1) ? Secur_ARRAY[Address] : - ((read_protect(Address) == 1'b1) ? 8'b0 : ARRAY[Address] ); - {SIO1_Reg, SIO0_Reg, OUT_Buf} <= #tCLQV {OUT_Buf, OUT_Buf[1:0]}; - Dummy_Count = 3 ; - end - end - end//forever - end - endtask // read_2xio - - /*----------------------------------------------------------------------*/ - /* Description: define Reading Parameter */ - /*----------------------------------------------------------------------*/ - task read_parameter; - integer Dummy_Count; - begin - Dummy_Count = 8; - forever begin - @ ( negedge ISCLK or posedge CS ); - if ( CS == 1'b1 ) begin - disable read_parameter; - end - else begin - SO_OUT_EN = 1'b1; - if ( Dummy_Count ) begin - Dummy_Count = Dummy_Count - 1; - SIO1_Reg <= #tCLQV Param_Reg[Dummy_Count]; - end - else begin - Dummy_Count = 7; - SIO1_Reg <= #tCLQV Param_Reg[Dummy_Count]; - end - - end - end // end forever - end - endtask // read_parameter - - /*----------------------------------------------------------------------*/ - /* Description: Execute Writing Parameter */ - /*----------------------------------------------------------------------*/ - task write_parameter; - begin - //$display( $time, " Old Parameter Register = %b", Param_Reg ); - if ( Status_Reg[4] == 0 || Status_Reg[3] == 0 || Status_Reg[2] == 0 ) begin//BP2~0 not all 1 - Param_Reg = 8'h00; - end - else begin //allow to change parameter register - Param_Reg = {3'b000,SI_Reg[4:0]}; - end - end - endtask // write_parameter - - /*----------------------------------------------------------------------*/ - /* Description: define a write_protect area function */ - /* INPUT */ - /* sector : sector address */ - /*----------------------------------------------------------------------*/ - function write_protect; - input [A_MSB:0] Address; - begin - //protect_define - Block = Address [A_MSB:16]; - if((Param_Reg[0] == 1) &&(Address[A_MSB:12] == 0)) begin - write_protect = Param_Reg[1]&&(Address[11:10] == 2'b00) || - Param_Reg[2]&&(Address[11:10] == 2'b01) || - Param_Reg[3]&&(Address[11:10] == 2'b10) || - Param_Reg[4]&&(Address[11:10] == 2'b11) ; - end - else if (Status_Reg[5:2] == 4'b0000) begin - write_protect = 1'b0; - end - else if (Status_Reg[5:2] == 4'b0001) begin - if (Block[Block_MSB:0] >= 126 && Block[Block_MSB:0] <= 127) begin - write_protect = 1'b1; - end - else begin - write_protect = 1'b0; - end - end - else if (Status_Reg[5:2] == 4'b0010) begin - if (Block[Block_MSB:0] >= 124 && Block[Block_MSB:0] <= 127) begin - write_protect = 1'b1; - end - else begin - write_protect = 1'b0; - end - end - else if (Status_Reg[5:2] == 4'b0011) begin - if (Block[Block_MSB:0] >= 120 && Block[Block_MSB:0] <= 127) begin - write_protect = 1'b1; - end - else begin - write_protect = 1'b0; - end - end - else if (Status_Reg[5:2] == 4'b0100) begin - if (Block[Block_MSB:0] >= 112 && Block[Block_MSB:0] <= 127) begin - write_protect = 1'b1; - end - else begin - write_protect = 1'b0; - end - end - else if (Status_Reg[5:2] == 4'b0101) begin - if (Block[Block_MSB:0] >= 96 && Block[Block_MSB:0] <= 127) begin - write_protect = 1'b1; - end - else begin - write_protect = 1'b0; - end - end - else if (Status_Reg[5:2] == 4'b0110) begin - if (Block[Block_MSB:0] >= 64 && Block[Block_MSB:0] <= 127) begin - write_protect = 1'b1; - end - else begin - write_protect = 1'b0; - end - end - else if (Status_Reg[5:2] == 4'b0111) begin - write_protect = 1'b1; - end - else if (Status_Reg[5:2] == 4'b1000) begin - write_protect = 1'b1; - end - else if (Status_Reg[5:2] == 4'b1001) begin - if (Block[Block_MSB:0] >= 0 && Block[Block_MSB:0] <= 63) begin - write_protect = 1'b1; - end - else begin - write_protect = 1'b0; - end - end - else if (Status_Reg[5:2] == 4'b1010) begin - if (Block[Block_MSB:0] >= 0 && Block[Block_MSB:0] <= 95) begin - write_protect = 1'b1; - end - else begin - write_protect = 1'b0; - end - end - else if (Status_Reg[5:2] == 4'b1011) begin - if (Block[Block_MSB:0] >= 0 && Block[Block_MSB:0] <= 111) begin - write_protect = 1'b1; - end - else begin - write_protect = 1'b0; - end - end - else if (Status_Reg[5:2] == 4'b1100) begin - if (Block[Block_MSB:0] >= 0 && Block[Block_MSB:0] <= 119) begin - write_protect = 1'b1; - end - else begin - write_protect = 1'b0; - end - end - else if (Status_Reg[5:2] == 4'b1101) begin - if (Block[Block_MSB:0] >= 0 && Block[Block_MSB:0] <= 123) begin - write_protect = 1'b1; - end - else begin - write_protect = 1'b0; - end - end - else if (Status_Reg[5:2] == 4'b1110) begin - if (Block[Block_MSB:0] >= 0 && Block[Block_MSB:0] <= 125) begin - write_protect = 1'b1; - end - else begin - write_protect = 1'b0; - end - end - else if (Status_Reg[5:2] == 4'b1111) begin - write_protect = 1'b1; - end - else begin - write_protect = 1'b1; - end - end - endfunction // write_protect - - - /*----------------------------------------------------------------------*/ - /* When WRLB Condtion Operation; */ - /*----------------------------------------------------------------------*/ - function read_protect; - input [A_MSB : 0] Address ; - begin - if ( (Secur_Reg[2] == 1'b1) && (Address >= PRO_128K_Beg) && (Address <= PRO_128K_End) ) begin - read_protect = 1'b1; - end - else begin - read_protect = 1'b0; - end - end - endfunction // read_protect -// *============================================================================================== -// * AC Timing Check Section -// *============================================================================================== - - wire Read_1XIO_Chk_w = Read_1XIO_Chk; - wire Read_2XIO_Chk_w = Read_2XIO_Chk; - wire SI_IN_EN_w = SI_IN_EN; - wire SO_IN_EN_w = SO_IN_EN; - - specify - /*----------------------------------------------------------------------*/ - /* Timing Check */ - /*----------------------------------------------------------------------*/ - $period( posedge ISCLK &&& ~CS, tSCLK ); // SCLK _/~ ->_/~ - $period( negedge ISCLK &&& ~CS, tSCLK ); // SCLK ~\_ ->~\_ - $period( posedge ISCLK &&& Read_1XIO_Chk_w , tRSCLK ); // SCLK ~\_ ->~\_ - $period( posedge ISCLK &&& Read_2XIO_Chk_w , tTSCLK ); // SCLK ~\_ ->~\_ - - - $width ( posedge ISCLK &&& ~CS, tCH ); // SCLK _/~~\_ - $width ( negedge ISCLK &&& ~CS, tCL ); // SCLK ~\__/~ - $width ( posedge CS , tSHSL ); // CS _/~\_ - $setup ( SI &&& ~CS, posedge ISCLK &&& SI_IN_EN_w, tDVCH ); - $hold ( posedge ISCLK &&& SI_IN_EN_w, SI &&& ~CS, tCHDX ); - - $setup ( SO &&& ~CS, posedge ISCLK &&& SO_IN_EN_w, tDVCH ); - $hold ( posedge ISCLK &&& SO_IN_EN_w, SO &&& ~CS, tCHDX ); - - $setup ( negedge CS, posedge ISCLK &&& ~CS, tSLCH ); - $hold ( posedge ISCLK &&& ~CS, posedge CS, tCHSH ); - - $setup ( posedge CS, posedge ISCLK &&& CS, tSHCH ); - $hold ( posedge ISCLK &&& CS, negedge CS, tCHSL ); - - - $setup ( negedge HOLD , posedge SCLK &&& ~CS, tHLCH ); - $hold ( posedge SCLK &&& ~CS, posedge HOLD , tCHHH ); - - $setup ( posedge HOLD , posedge SCLK &&& ~CS, tHHCH ); - $hold ( posedge SCLK &&& ~CS, negedge HOLD , tCHHL ); - - $setup ( posedge WP &&& SRWD, negedge CS, tWHSL ); - $hold ( posedge CS, negedge WP &&& SRWD, tSHWL ); - - $setup ( negedge SCLK &&& ~CS, negedge HOLD , tCLHS ); - $hold ( negedge SCLK &&& ~CS, posedge HOLD , tCLHH ); - endspecify - - - integer AC_Check_File; - // timing check module - initial - begin - AC_Check_File= $fopen ("ac_check.err" ); - end - - time T_CS_P , T_CS_N; - time T_WP_P , T_WP_N; - time T_SCLK_P , T_SCLK_N; - time T_ISCLK_P , T_ISCLK_N; - time T_HOLD_P , T_HOLD_N; - time T_SI; - time T_SO; - time T_WP; - time T_HOLD; - - initial - begin - T_CS_P = 0; - T_CS_N = 0; - T_WP_P = 0; - T_WP_N = 0; - T_SCLK_P = 0; - T_SCLK_N = 0; - T_ISCLK_P = 0; - T_ISCLK_N = 0; - T_HOLD_P = 0; - T_HOLD_N = 0; - T_SI = 0; - T_SO = 0; - T_WP = 0; - T_HOLD = 0; - end - - always @ ( posedge ISCLK ) begin - //tSCLK - if ( $time - T_ISCLK_P < tSCLK && $time > 0 && ~CS ) - $fwrite (AC_Check_File, "Clock Frequence for except READ struction fSCLK =%d Mhz, fSCLK timing violation at %d \n", fSCLK, $time ); - //fRSCLK - if ( $time - T_ISCLK_P < tRSCLK && Read_1XIO_Chk && $time > 0 && ~CS ) - $fwrite (AC_Check_File, "Clock Frequence for READ instruction fRSCLK =%d Mhz, fRSCLK timing violation at %d \n", fRSCLK, $time ); - //fTSCLK - if ( $time - T_ISCLK_P < tTSCLK && Read_2XIO_Chk && $time > 0 && ~CS ) - $fwrite (AC_Check_File, "Clock Frequence for 2/4XI/O instruction fTSCLK =%d Mhz, fRSCLK timing violation at %d \n", fTSCLK, $time ); - T_ISCLK_P = $time; - #0; - //tDVCH - if ( T_ISCLK_P - T_SI < tDVCH && SI_IN_EN && T_ISCLK_P > 0 ) - $fwrite (AC_Check_File, "minimun Data SI setup time tDVCH=%d ns, tDVCH timing violation at %d \n", tDVCH, $time ); - if ( T_ISCLK_P - T_SO < tDVCH && SO_IN_EN && T_ISCLK_P > 0 ) - $fwrite (AC_Check_File, "minimun Data SO setup time tDVCH=%d ns, tDVCH timing violation at %d \n", tDVCH, $time ); - //tCL - if ( T_ISCLK_P - T_ISCLK_N < tCL && ~CS && T_ISCLK_P > 0 ) - $fwrite (AC_Check_File, "minimun SCLK Low time tCL=%f ns, tCL timing violation at %d \n", tCL, $time ); - end - - always @ ( negedge ISCLK ) begin - T_ISCLK_N = $time; - #0; - //tCH - if ( T_ISCLK_N - T_ISCLK_P < tCH && ~CS && T_ISCLK_N > 0 ) - $fwrite (AC_Check_File, "minimun SCLK High time tCH=%f ns, tCH timing violation at %d \n", tCH, $time ); - end - - - always @ ( SI ) begin - T_SI = $time; - #0; - //tCHDX - if ( T_SI - T_ISCLK_P < tCHDX && SI_IN_EN && T_SI > 0 ) - $fwrite (AC_Check_File, "minimun Data SI hold time tCHDX=%d ns, tCHDX timing violation at %d \n", tCHDX, $time ); - end - - always @ ( SO ) begin - T_SO = $time; - #0; - //tCHDX - if ( T_SO - T_ISCLK_P < tCHDX && SO_IN_EN && T_SO > 0 ) - $fwrite (AC_Check_File, "minimun Data SO hold time tCHDX=%d ns, tCHDX timing violation at %d \n", tCHDX, $time ); - end - - - always @ ( posedge SCLK ) begin - T_SCLK_P = $time; - #0; - // tSLCH - if ( T_SCLK_P - T_CS_N < tSLCH && T_SCLK_P > 0 ) - $fwrite (AC_Check_File, "minimun CS# active setup time tSLCH=%d ns, tSLCH timing violation at %d \n", tSLCH, $time ); - - // tSHCH - if ( T_SCLK_P - T_CS_P < tSHCH && T_SCLK_P > 0 ) - $fwrite (AC_Check_File, "minimun CS# not active setup time tSHCH=%d ns, tSHCH timing violation at %d \n", tSHCH, $time ); - - - //tHLCH - if ( T_SCLK_P - T_HOLD_N < tHLCH && ~CS && T_SCLK_P > 0 ) - $fwrite (AC_Check_File, "minimun HOLD# setup time tHLCH=%d ns, tHLCH timing violation at %d \n", tHLCH, $time ); - - //tHHCH - if ( T_SCLK_P - T_HOLD_P < tHHCH && ~CS && T_SCLK_P > 0 ) - $fwrite (AC_Check_File, "minimun HOLD setup time tHHCH=%d ns, tHHCH timing violation at %d \n", tHHCH, $time ); - - end - - always @ ( negedge SCLK ) begin - T_SCLK_N = $time; - end - - always @ ( posedge CS ) begin - T_CS_P = $time; - #0; - // tCHSH - if ( T_CS_P - T_SCLK_P < tCHSH && T_CS_P > 0 ) - $fwrite (AC_Check_File, "minimun CS# active hold time tCHSH=%d ns, tCHSH timing violation at %d \n", tCHSH, $time ); - end - - - always @ ( negedge CS ) begin - T_CS_N = $time; - #0; - //tCHSL - if ( T_CS_N - T_SCLK_P < tCHSL && T_CS_N > 0 ) - $fwrite (AC_Check_File, "minimun CS# not active hold time tCHSL=%d ns, tCHSL timing violation at %d \n", tCHSL, $time ); - //tSHSL - if ( T_CS_N - T_CS_P < tSHSL && T_CS_N > 0 ) - $fwrite (AC_Check_File, "minimun CS# deslect time tSHSL=%d ns, tSHSL timing violation at %d \n", tSHSL, $time ); - //tWHSL - if ( T_CS_N - T_WP_P < tWHSL && SRWD && T_CS_N > 0 ) - $fwrite (AC_Check_File, "minimun WP setup time tWHSL=%d ns, tWHSL timing violation at %d \n", tWHSL, $time ); - - end - - - always @ ( posedge WP ) begin - T_WP_P = $time; - #0; - end - - always @ ( negedge WP ) begin - T_WP_N = $time; - #0; - //tSHWL - if ( ((T_WP_N - T_CS_P < tSHWL) || ~CS) && SRWD && T_WP_N > 0 ) - $fwrite (AC_Check_File, "minimun WP hold time tSHWL=%d ns, tSHWL timing violation at %d \n", tSHWL, $time ); - end - - always @ ( posedge HOLD ) begin - T_HOLD_P = $time; - #0; - - //tCHHH - if ( T_HOLD_P - T_SCLK_P < tCHHH && ~CS && T_HOLD_P > 0 ) - $fwrite (AC_Check_File, "minimun HOLD# hold time tCHHH=%d ns, tCHHH timing violation at %d \n", tCHHH, $time ); - - //tCLHH - if ( T_HOLD_P - T_SCLK_N < tCLHH && ~CS && T_HOLD_P > 0 ) - $fwrite (AC_Check_File, "Clock Low to HOLD# hold time tCLHH=%d ns, tCLHH timing violation at %d \n", tCLHH, $time ); - - end - - - always @ ( negedge HOLD ) begin - T_HOLD_N = $time; - #0; - //tCHHL - if ( T_HOLD_N - T_SCLK_P < tCHHL && ~CS && T_HOLD_N > 0 ) - $fwrite (AC_Check_File, "minimun HOLD hold time tCHHL=%d ns, tCHHL timing violation at %d \n", tCHHL, $time ); - - //tCLHS - if ( T_HOLD_N - T_SCLK_N < tCLHS && ~CS && T_HOLD_N > 0 ) - $fwrite (AC_Check_File, "Clock Low to HOLD# setup time tCLHS=%d ns, tCLHS timing violation at %d \n", tCLHS, $time ); - end - -endmodule - - - - diff --git a/resources/soc/simu/testbench/ddr3_model.sv b/resources/soc/simu/testbench/ddr3_model.sv deleted file mode 100644 index d600001..0000000 --- a/resources/soc/simu/testbench/ddr3_model.sv +++ /dev/null @@ -1,2937 +0,0 @@ -//`define MAX_MEM - -/**************************************************************************************** -* -* File Name: ddr3.v -* Version: 1.72 -* Model: BUS Functional -* -* Dependencies: ddr3_model_parameters.vh -* -* Description: Micron SDRAM DDR3 (Double Data Rate 3) -* -* Limitation: - doesn't check for average refresh timings -* - positive ck and ck_n edges are used to form internal clock -* - positive dqs and dqs_n edges are used to latch data -* - test mode is not modeled -* - Duty Cycle Corrector is not modeled -* - Temperature Compensated Self Refresh is not modeled -* - DLL off mode is not modeled. -* -* Note: - Set simulator resolution to "ps" accuracy -* - Set DEBUG = 0 to disable $display messages -* -* Disclaimer This software code and all associated documentation, comments or other -* of Warranty: information (collectively "Software") is provided "AS IS" without -* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY -* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES -* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT -* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE -* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. -* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR -* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, -* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE -* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, -* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, -* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, -* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, -* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE -* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH -* DAMAGES. Because some jurisdictions prohibit the exclusion or -* limitation of liability for consequential or incidental damages, the -* above limitation may not apply to you. -* -* Copyright 2003 Micron Technology, Inc. All rights reserved. -* -* Rev Author Date Changes -* --------------------------------------------------------------------------------------- -* 0.41 JMK 05/12/06 Removed auto-precharge to power down error check. -* 0.42 JMK 08/25/06 Created internal clock using ck and ck_n. -* TDQS can only be enabled in EMR for x8 configurations. -* CAS latency is checked vs frequency when DLL locks. -* Improved checking of DQS during writes. -* Added true BL4 operation. -* 0.43 JMK 08/14/06 Added checking for setting reserved bits in Mode Registers. -* Added ODTS Readout. -* Replaced tZQCL with tZQinit and tZQoper -* Fixed tWRPDEN and tWRAPDEN during BC4MRS and BL4MRS. -* Added tRFC checking for Refresh to Power-Down Re-Entry. -* Added tXPDLL checking for Power-Down Exit to Refresh to Power-Down Entry -* Added Clock Frequency Change during Precharge Power-Down. -* Added -125x speed grades. -* Fixed tRCD checking during Write. -* 1.00 JMK 05/11/07 Initial release -* 1.10 JMK 06/26/07 Fixed ODTH8 check during BLOTF -* Removed temp sensor readout from MPR -* Updated initialization sequence -* Updated timing parameters -* 1.20 JMK 09/05/07 Updated clock frequency change -* Added ddr3_dimm module -* 1.30 JMK 01/23/08 Updated timing parameters -* 1.40 JMK 12/02/08 Added support for DDR3-1866 and DDR3-2133 -* renamed ddr3_dimm.v to ddr3_module.v and added SODIMM support. -* Added multi-chip package model support in ddr3_mcp.v -* 1.50 JMK 05/04/08 Added 1866 and 2133 speed grades. -* 1.60 MYY 07/10/09 Merging of 1.50 version and pre-1.0 version changes -* 1.61 SPH 12/10/09 Only check tIH for cmd_addr if CS# LOW -* 1.62 SPH 10/26/10 Added 4Gb DDR3 SDRAM support -* 1.63 MYY 11/09/10 Added Dll Disable mode -* 1.64 MYY 07/28/11 Check dqs_in for dqs timing check -* 1.65 MYY 09/19/11 Widen internal bus width -* 1.66 MYY 01/20/12 Support ODT tied high feature -* 1.67 MYY 02/03/12 Added TJIT_PER margin for timing checks -* 1.68 SPH 04/02/12 Added memory preload -* 1.69 SPH 03/19/13 Update tZQCS, tZQinit, tZQoper timing parameters -* 1.70 SPH 04/08/14 Update tRFC to PRECHARGE check -* 1.71 SPH 04/21/14 Added 8Gb mono die parameters -* Remove strict CL check -* 1.72 DLH 06/18/15 calculate TZQCS from current tCK -*****************************************************************************************/ - -// DO NOT CHANGE THE TIMESCALE -// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION -`timescale 1ps / 1ps - -// model flags -// `define MODEL_PASR -//Memory Details -`define x1Gb -`define sg125 -`define x16 -module ddr3_model ( - rst_n, - ck, - ck_n, - cke, - cs_n, - ras_n, - cas_n, - we_n, - dm_tdqs, - ba, - addr, - dq, - dqs, - dqs_n, - tdqs_n, - odt -); - - `include "ddr3_model_parameters.vh" - - parameter check_strict_mrbits = 1; - parameter check_strict_timing = 1; - parameter feature_pasr = 1; - parameter feature_truebl4 = 0; - parameter feature_odt_hi = 0; - parameter PERTCKAVG=TDLLK; - - // text macros - `define DQ_PER_DQS DQ_BITS/DQS_BITS - `define BANKS (1<= 2. \nBL_MAX = %d", BL_MAX); - if ((1< BL_MAX) - $display("%m ERROR: 2^BO_BITS cannot be greater than BL_MAX parameter."); - - $timeformat (-12, 1, " ps", 1); - seed = RANDOM_SEED; - - ck_cntr = 0; - end - - function integer get_rtt_wr; - input [1:0] rtt; - begin - get_rtt_wr = RZQ/{rtt[0], rtt[1], 1'b0}; - end - endfunction - - function integer get_rtt_nom; - input [2:0] rtt; - begin - case (rtt) - 1: get_rtt_nom = RZQ/4; - 2: get_rtt_nom = RZQ/2; - 3: get_rtt_nom = RZQ/6; - 4: get_rtt_nom = RZQ/12; - 5: get_rtt_nom = RZQ/8; - default : get_rtt_nom = 0; - endcase - end - endfunction - - // calculate the absolute value of a real number - function real abs_value; - input arg; - real arg; - begin - if (arg < 0.0) - abs_value = -1.0 * arg; - else - abs_value = arg; - end - endfunction - - function integer ceil; - input number; - real number; - - // LMR 4.1.7 - // When either operand of a relational expression is a real operand then the other operand shall be converted - // to an equivalent real value, and the expression shall be interpreted as a comparison between two real values. - if (number > $rtoi(number)) - ceil = $rtoi(number) + 1; - else - ceil = number; - endfunction - - function integer floor; - input number; - real number; - - // LMR 4.1.7 - // When either operand of a relational expression is a real operand then the other operand shall be converted - // to an equivalent real value, and the expression shall be interpreted as a comparison between two real values. - if (number < $rtoi(number)) - floor = $rtoi(number) - 1; - else - floor = number; - endfunction - - function int max( input int a, b ); - max = (a < b) ? b : a; - endfunction - - function int min( input int a, b ); - min = (a > b) ? b : a; - endfunction - -`ifdef MAX_MEM - - function integer open_bank_file( input integer bank ); - integer fd; - reg [2048:1] filename; - begin - $sformat( filename, "%0s/%m.%0d", tmp_model_dir, bank ); - - fd = $fopen(filename, "wb+"); - if (fd == 0) - begin - $display("%m: at time %0t ERROR: failed to open %0s.", $time, filename); - $finish; - end - else - begin - if (DEBUG) $display("%m: at time %0t INFO: opening %0s.", $time, filename); - open_bank_file = fd; - end - - end - endfunction - - function [RFF_BITS:1] read_from_file( - input integer fd, - input integer index - ); - integer code; - integer offset; - reg [1024:1] msg; - reg [RFF_BITS:1] read_value; - - begin - offset = index * RFF_CHUNK; - code = $fseek( fd, offset, 0 ); - // $fseek returns 0 on success, -1 on failure - if (code != 0) - begin - $display("%m: at time %t ERROR: fseek to %d failed", $time, offset); - $finish; - end - - code = $fscanf(fd, "%z", read_value); - // $fscanf returns number of items read - if (code != 1) - begin - if ($ferror(fd,msg) != 0) - begin - $display("%m: at time %t ERROR: fscanf failed at %d", $time, index); - $display(msg); - $finish; - end - else - read_value = 'hx; - end - - /* when reading from unwritten portions of the file, 0 will be returned. - * Use 0 in bit 1 as indicator that invalid data has been read. - * A true 0 is encoded as Z. - */ - if (read_value[1] === 1'bz) - // true 0 encoded as Z, data is valid - read_value[1] = 1'b0; - else if (read_value[1] === 1'b0) - // read from file section that has not been written - read_value = 'hx; - - read_from_file = read_value; - end - endfunction - - task write_to_file( - input integer fd, - input integer index, - input [RFF_BITS:1] data - ); - integer code; - integer offset; - - begin - offset = index * RFF_CHUNK; - code = $fseek( fd, offset, 0 ); - if (code != 0) - begin - $display("%m: at time %t ERROR: fseek to %d failed", $time, offset); - $finish; - end - - // encode a valid data - if (data[1] === 1'bz) - data[1] = 1'bx; - else if (data[1] === 1'b0) - data[1] = 1'bz; - - $fwrite( fd, "%z", data ); - end - endtask -`else - function get_index; - input [`MAX_BITS-1:0] addr; - begin : index - get_index = 0; - for (memory_index=0; memory_index>(ROW_BITS+COL_BITS-BL_BITS)); - if (!banks[ba]) begin //bank is selected to keep - address[i] = address[memory_index]; - memory[i] = memory[memory_index]; - i = i + 1; - end - end - // clean up the unused banks - for (memory_index=i; memory_index TRAS_MAX) $display ("%m: at time %t ERROR: tRAS maximum violation during %s to bank %d", $time, cmd_string[cmd], bank); - if ($time - tm_bank_activate[bank] < TRAS_MIN-TJIT_PER) $display ("%m: at time %t ERROR: tRAS minimum violation during %s to bank %d", $time, cmd_string[cmd], bank);end - {1'bx, SAME_BANK , ACTIVATE , ACTIVATE } : begin if ($time - tm_bank_activate[bank] < TRC-TJIT_PER) $display ("%m: at time %t ERROR: tRC violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'bx, SAME_BANK , ACTIVATE , WRITE } , - {1'bx, SAME_BANK , ACTIVATE , READ } : ; // tRCD is checked outside this task - {1'b0, DIFF_BANK , ACTIVATE , ACTIVATE } : begin if (($time - tm_activate < TRRD) || (ck_cntr - ck_activate < TRRD_TCK)) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b1, DIFF_BANK , ACTIVATE , ACTIVATE } : begin if (($time - tm_group_activate[bank[1]] < TRRD) || (ck_cntr - ck_group_activate[bank[1]] < TRRD_TCK)) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b1, DIFF_GROUP, ACTIVATE , ACTIVATE } : begin if (($time - tm_activate < TRRD_DG) || (ck_cntr - ck_activate < TRRD_DG_TCK)) $display ("%m: at time %t ERROR: tRRD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'bx, DIFF_BANK , ACTIVATE , REFRESH } : begin if ($time - tm_activate < TRC-TJIT_PER) $display ("%m: at time %t ERROR: tRC violation during %s", $time, cmd_string[cmd]); end - {1'bx, DIFF_BANK , ACTIVATE , PWR_DOWN } : begin if (ck_cntr - ck_activate < TACTPDEN) $display ("%m: at time %t ERROR: tACTPDEN violation during %s", $time, cmd_string[cmd]); end - - // write - {1'bx, SAME_BANK , WRITE , PRECHARGE} : begin if (($time - tm_bank_write_end[bank] < TWR-TJIT_PER) || (ck_cntr - ck_bank_write[bank] <= write_latency + burst_length/2)) $display ("%m: at time %t ERROR: tWR violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b0, DIFF_BANK , WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b1, DIFF_BANK , WRITE , WRITE } : begin if (ck_cntr - ck_group_write[bank[1]] < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b0, DIFF_BANK , WRITE , READ } : begin if (ck_cntr - ck_write < write_latency + burst_length/2 + TWTR_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b1, DIFF_BANK , WRITE , READ } : begin if (ck_cntr - ck_group_write[bank[1]] < write_latency + burst_length/2 + TWTR_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b1, DIFF_GROUP, WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD_DG) $display ("%m: at time %t ERROR: tCCD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b1, DIFF_GROUP, WRITE , READ } : begin if (ck_cntr - ck_write < write_latency + burst_length/2 + TWTR_DG_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'bx, DIFF_BANK , WRITE , PWR_DOWN } : begin if (($time - tm_write_end < TWR-TJIT_PER) || (ck_cntr - ck_write < write_latency + burst_length/2)) $display ("%m: at time %t ERROR: tWRPDEN violation during %s", $time, cmd_string[cmd]); end - - // read - {1'bx, SAME_BANK , READ , PRECHARGE} : begin if (($time - tm_bank_read_end[bank] < TRTP-TJIT_PER) || (ck_cntr - ck_bank_read[bank] < additive_latency + TRTP_TCK)) $display ("%m: at time %t ERROR: tRTP violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b0, DIFF_BANK , READ , WRITE } : ; // tRTW is checked outside this task - {1'b1, DIFF_BANK , READ , WRITE } : ; // tRTW is checked outside this task - {1'b0, DIFF_BANK , READ , READ } : begin if (ck_cntr - ck_read < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b1, DIFF_BANK , READ , READ } : begin if (ck_cntr - ck_group_read[bank[1]] < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b1, DIFF_GROUP, READ , WRITE } : ; // tRTW is checked outside this task - {1'b1, DIFF_GROUP, READ , READ } : begin if (ck_cntr - ck_read < TCCD_DG) $display ("%m: at time %t ERROR: tCCD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'bx, DIFF_BANK , READ , PWR_DOWN } : begin if (ck_cntr - ck_read < read_latency + 5) $display ("%m: at time %t ERROR: tRDPDEN violation during %s", $time, cmd_string[cmd]); end - - // zq - {1'bx, DIFF_BANK , ZQ , LOAD_MODE} : ; // 1 tCK - {1'bx, DIFF_BANK , ZQ , REFRESH } , - {1'bx, DIFF_BANK , ZQ , PRECHARGE} , - {1'bx, DIFF_BANK , ZQ , ACTIVATE } , - {1'bx, DIFF_BANK , ZQ , ZQ } , - {1'bx, DIFF_BANK , ZQ , PWR_DOWN } , - {1'bx, DIFF_BANK , ZQ , SELF_REF } : begin if (ck_cntr - ck_zqinit < TZQINIT) $display ("%m: at time %t ERROR: tZQinit violation during %s", $time, cmd_string[cmd]); - if (ck_cntr - ck_zqoper < TZQOPER) $display ("%m: at time %t ERROR: tZQoper violation during %s", $time, cmd_string[cmd]); - if (ck_cntr - ck_zqcs < TZQCS) $display ("%m: at time %t ERROR: tZQCS violation during %s", $time, cmd_string[cmd]); end - - // power down - {1'bx, DIFF_BANK , PWR_DOWN , LOAD_MODE} , - {1'bx, DIFF_BANK , PWR_DOWN , REFRESH } , - {1'bx, DIFF_BANK , PWR_DOWN , PRECHARGE} , - {1'bx, DIFF_BANK , PWR_DOWN , ACTIVATE } , - {1'bx, DIFF_BANK , PWR_DOWN , WRITE } , - {1'bx, DIFF_BANK , PWR_DOWN , ZQ } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); end - {1'bx, DIFF_BANK , PWR_DOWN , READ } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); - else if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) $display ("%m: at time %t ERROR: tXPDLL violation during %s", $time, cmd_string[cmd]); end - {1'bx, DIFF_BANK , PWR_DOWN , PWR_DOWN } , - {1'bx, DIFF_BANK , PWR_DOWN , SELF_REF } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); - if ((tm_power_down > tm_refresh) && ($time - tm_refresh < TRFC_MIN)) $display ("%m: at time %t ERROR: tRFC violation during %s", $time, cmd_string[cmd]); - if ((tm_refresh > tm_power_down) && (($time - tm_power_down < TXPDLL) || (ck_cntr - ck_power_down < TXPDLL_TCK))) $display ("%m: at time %t ERROR: tXPDLL violation during %s", $time, cmd_string[cmd]); - if (($time - tm_cke_cmd < TCKE) || (ck_cntr - ck_cke_cmd < TCKE_TCK)) $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); end - - // self refresh - {1'bx, DIFF_BANK , SELF_REF , LOAD_MODE} , - {1'bx, DIFF_BANK , SELF_REF , REFRESH } , - {1'bx, DIFF_BANK , SELF_REF , PRECHARGE} , - {1'bx, DIFF_BANK , SELF_REF , ACTIVATE } , - {1'bx, DIFF_BANK , SELF_REF , WRITE } , - {1'bx, DIFF_BANK , SELF_REF , ZQ } : begin if (($time - tm_self_refresh < TXS) || (ck_cntr - ck_self_refresh < TXS_TCK)) $display ("%m: at time %t ERROR: tXS violation during %s", $time, cmd_string[cmd]); end - {1'bx, DIFF_BANK , SELF_REF , READ } : begin if (ck_cntr - ck_self_refresh < TXSDLL) $display ("%m: at time %t ERROR: tXSDLL violation during %s", $time, cmd_string[cmd]); end - {1'bx, DIFF_BANK , SELF_REF , PWR_DOWN } , - {1'bx, DIFF_BANK , SELF_REF , SELF_REF } : begin if (($time - tm_self_refresh < TXS) || (ck_cntr - ck_self_refresh < TXS_TCK)) $display ("%m: at time %t ERROR: tXS violation during %s", $time, cmd_string[cmd]); - if (($time - tm_cke_cmd < TCKE) || (ck_cntr - ck_cke_cmd < TCKE_TCK)) $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); end - endcase - end - endtask - - task cmd_task; - inout prev_cke; - input cke; - input [2:0] cmd; - input [BA_BITS-1:0] bank; - input [ADDR_BITS-1:0] addr; - reg [`BANKS:0] i; - integer j; - reg [`BANKS:0] tfaw_cntr; - reg [COL_BITS-1:0] col; - reg group; - begin - // tRFC max check - if (!er_trfc_max && !in_self_refresh) begin - if ($time - tm_refresh > TRFC_MAX && check_strict_timing) begin - $display ("%m: at time %t ERROR: tRFC maximum violation during %s", $time, cmd_string[cmd]); - er_trfc_max = 1; - end - end - if (cke) begin - if ((cmd < NOP) && (cmd != PRECHARGE)) begin - if (($time - tm_txpr < TXPR) || (ck_cntr - ck_txpr < TXPR_TCK)) - $display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[cmd]); - for (j=0; j<=SELF_REF; j=j+1) begin - chk_err(SAME_BANK , bank, j, cmd); - chk_err(DIFF_BANK , bank, j, cmd); - chk_err(DIFF_GROUP, bank, j, cmd); - end - end - case (cmd) - LOAD_MODE : begin - if (|odt_pipeline) - $display ("%m: at time %t ERROR: ODTL violation during %s", $time, cmd_string[cmd]); - if (odt_state && !feature_odt_hi) - $display ("%m: at time %t ERROR: ODT must be off prior to %s", $time, cmd_string[cmd]); - - if (|active_bank) begin - $display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]); - if (STOP_ON_ERROR) $stop(0); - end else begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d", $time, cmd_string[cmd], bank); - if (bank>>2) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved bank bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - case (bank) - 0 : begin - // Burst Length - if (addr[1:0] == 2'b00) begin - burst_length = 8; - blotf = 0; - truebl4 = 0; - if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = %d", $time, cmd_string[cmd], bank, burst_length); - end else if (addr[1:0] == 2'b01) begin - burst_length = 8; - blotf = 1; - if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = Select via A12", $time, cmd_string[cmd], bank); - end else if (addr[1:0] == 2'b10) begin - burst_length = 4; - blotf = 0; - if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = Fixed %d (chop)", $time, cmd_string[cmd], bank, burst_length); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Burst Length = %d", $time, cmd_string[cmd], bank, addr[1:0]); - end - // Burst Order - burst_order = addr[3]; - if (!burst_order) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Sequential", $time, cmd_string[cmd], bank); - end else if (burst_order) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Interleaved", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Burst Order = %d", $time, cmd_string[cmd], bank, burst_order); - end - // CAS Latency - cas_latency = {addr[2],addr[6:4]} + 4; - set_latency; - if ((cas_latency >= CL_MIN) && (cas_latency <= CL_MAX)) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency); - end - // Reserved - if (addr[7] !== 0 && check_strict_mrbits) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - // DLL Reset - dll_reset = addr[8]; - if (!dll_reset) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Normal", $time, cmd_string[cmd], bank); - end else if (dll_reset) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Reset DLL", $time, cmd_string[cmd], bank); - dll_locked = 0; - init_dll_reset = 1; - ck_dll_reset <= ck_cntr; - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal DLL Reset = %d", $time, cmd_string[cmd], bank, dll_reset); - end - - // Write Recovery - if (addr[11:9] == 0) begin - write_recovery = 16; - end else if (addr[11:9] < 4) begin - write_recovery = addr[11:9] + 4; - end else begin - write_recovery = 2*addr[11:9]; - end - - if ((write_recovery >= WR_MIN) && (write_recovery <= WR_MAX)) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery); - end - // Power Down Mode - low_power = !addr[12]; - if (!low_power) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = DLL on", $time, cmd_string[cmd], bank); - end else if (low_power) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = DLL off", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Power Down Mode = %d", $time, cmd_string[cmd], bank, low_power); - end - // Reserved - if (ADDR_BITS>13 && addr[13] !== 0 && check_strict_mrbits) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - end - 1 : begin - // DLL Enable - dll_en = !addr[0]; - if (!dll_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Disabled", $time, cmd_string[cmd], bank); - if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d DLL off mode is not fully modeled", $time, cmd_string[cmd], bank); - end else if (dll_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Enabled", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal DLL Enable = %d", $time, cmd_string[cmd], bank, dll_en); - end - // Output Drive Strength - if ({addr[5], addr[1]} == 2'b00) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/6); - end else if ({addr[5], addr[1]} == 2'b01) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/7); - end else if ({addr[5], addr[1]} == 2'b11) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/5); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Output Drive Strength = %d", $time, cmd_string[cmd], bank, {addr[5], addr[1]}); - end - // ODT Rtt (Rtt_NOM) - odt_rtt_nom = {addr[9], addr[6], addr[2]}; - if (odt_rtt_nom == 3'b000) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = Disabled", $time, cmd_string[cmd], bank); - odt_en = 0; - end else if ((odt_rtt_nom < 4) || ((!addr[7] || (addr[7] && addr[12])) && (odt_rtt_nom < 6))) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = %d Ohm", $time, cmd_string[cmd], bank, get_rtt_nom(odt_rtt_nom)); - odt_en = 1; - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal ODT Rtt = %d", $time, cmd_string[cmd], bank, odt_rtt_nom); - odt_en = 0; - end - // Report the additive latency value - al = addr[4:3]; - set_latency; - if (al == 0) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = %d", $time, cmd_string[cmd], bank, al); - end else if ((al >= AL_MIN) && (al <= AL_MAX)) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = CL - %d", $time, cmd_string[cmd], bank, al); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Additive Latency = %d", $time, cmd_string[cmd], bank, al); - end - // Write Levelization - write_levelization = addr[7]; - if (!write_levelization) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Levelization = Disabled", $time, cmd_string[cmd], bank); - end else if (write_levelization) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Levelization = Enabled", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Write Levelization = %d", $time, cmd_string[cmd], bank, write_levelization); - end - // Reserved - if (addr[8] !== 0 && check_strict_mrbits) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - // Reserved - if (addr[10] !== 0 && check_strict_mrbits) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - // TDQS Enable - tdqs_en = addr[11]; - if (!tdqs_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d TDQS Enable = Disabled", $time, cmd_string[cmd], bank); - end else if (tdqs_en) begin - if (8 == DQ_BITS) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d TDQS Enable = Enabled", $time, cmd_string[cmd], bank); - end - else begin - $display ("%m: at time %t WARNING: %s %d Illegal TDQS Enable. TDQS only exists on a x8 part", $time, cmd_string[cmd], bank); - tdqs_en = 0; - end - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal TDQS Enable = %d", $time, cmd_string[cmd], bank, tdqs_en); - end - // Output Enable - out_en = !addr[12]; - if (!out_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Qoff = Disabled", $time, cmd_string[cmd], bank); - end else if (out_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Qoff = Enabled", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Qoff = %d", $time, cmd_string[cmd], bank, out_en); - end - // Reserved - if (ADDR_BITS>13 && addr[13] !== 0 && check_strict_mrbits) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - end - 2 : begin - if (feature_pasr) begin - // Partial Array Self Refresh - pasr = addr[2:0]; - case (pasr) - 3'b000 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-7", $time, cmd_string[cmd], bank); - 3'b001 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-3", $time, cmd_string[cmd], bank); - 3'b010 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-1", $time, cmd_string[cmd], bank); - 3'b011 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0", $time, cmd_string[cmd], bank); - 3'b100 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 2-7", $time, cmd_string[cmd], bank); - 3'b101 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 4-7", $time, cmd_string[cmd], bank); - 3'b110 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 6-7", $time, cmd_string[cmd], bank); - 3'b111 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 7", $time, cmd_string[cmd], bank); - default : $display ("%m: at time %t ERROR: %s %d Illegal Partial Array Self Refresh = %d", $time, cmd_string[cmd], bank, pasr); - endcase - end - else - if (addr[2:0] !== 0 && check_strict_mrbits) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - // CAS Write Latency - cas_write_latency = addr[5:3]+5; - set_latency; - if ((cas_write_latency >= CWL_MIN) && (cas_write_latency <= CWL_MAX)) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Write Latency = %d", $time, cmd_string[cmd], bank, cas_write_latency); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal CAS Write Latency = %d", $time, cmd_string[cmd], bank, cas_write_latency); - end - // Auto Self Refresh Method - asr = addr[6]; - if (!asr) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Auto Self Refresh = Disabled", $time, cmd_string[cmd], bank); - end else if (asr) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Auto Self Refresh = Enabled", $time, cmd_string[cmd], bank); - if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d Auto Self Refresh is not modeled", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Auto Self Refresh = %d", $time, cmd_string[cmd], bank, asr); - end - // Self Refresh Temperature - srt = addr[7]; - if (!srt) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Self Refresh Temperature = Normal", $time, cmd_string[cmd], bank); - end else if (srt) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Self Refresh Temperature = Extended", $time, cmd_string[cmd], bank); - if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d Self Refresh Temperature is not modeled", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Self Refresh Temperature = %d", $time, cmd_string[cmd], bank, srt); - end - if (asr && srt) - $display ("%m: at time %t ERROR: %s %d SRT must be set to 0 when ASR is enabled.", $time, cmd_string[cmd], bank); - // Reserved - if (addr[8] !== 0 && check_strict_mrbits) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - // Dynamic ODT (Rtt_WR) - odt_rtt_wr = addr[10:9]; - if (odt_rtt_wr == 2'b00) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Dynamic ODT = Disabled", $time, cmd_string[cmd], bank); - dyn_odt_en = 0; - end else if ((odt_rtt_wr > 0) && (odt_rtt_wr < 3)) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Dynamic ODT Rtt = %d Ohm", $time, cmd_string[cmd], bank, get_rtt_wr(odt_rtt_wr)); - dyn_odt_en = 1; - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Dynamic ODT = %d", $time, cmd_string[cmd], bank, odt_rtt_wr); - dyn_odt_en = 0; - end - // Reserved - if (ADDR_BITS>13 && addr[13:11] !== 0 && check_strict_mrbits) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - end - 3 : begin - mpr_select = addr[1:0]; - // MultiPurpose Register Select - if (mpr_select == 2'b00) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Select = Pre-defined pattern", $time, cmd_string[cmd], bank); - end else begin - if (check_strict_mrbits) $display ("%m: at time %t ERROR: %s %d Illegal MultiPurpose Register Select = %d", $time, cmd_string[cmd], bank, mpr_select); - end - // MultiPurpose Register Enable - mpr_en = addr[2]; - if (!mpr_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Enable = Disabled", $time, cmd_string[cmd], bank); - end else if (mpr_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Enable = Enabled", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal MultiPurpose Register Enable = %d", $time, cmd_string[cmd], bank, mpr_en); - end - - if (feature_truebl4 && (addr[11] == 1'b1)) begin - if (addr[11] == 1'b1) begin - truebl4 = 1; - $display(" EMRS3 Set True Bl4 mode only "); - end - end - - // Reserved - if (ADDR_BITS>13 && addr[13:3] !== 0 && check_strict_mrbits) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - end - endcase - if (dyn_odt_en && write_levelization) - $display ("%m: at time %t ERROR: Dynamic ODT is not available during Write Leveling mode.", $time); - init_mode_reg[bank] = 1; - mode_reg[bank] = addr; - // dll_reset bit self clear - if(bank==0 && addr[8]==1'b1) - mode_reg[0][8] <= #($rtoi(tck_avg)) 1'b0; - tm_load_mode <= $time; - ck_load_mode <= ck_cntr; - end - end - REFRESH : begin - if (mpr_en) begin - $display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]); - if (STOP_ON_ERROR) $stop(0); - end else if (|active_bank) begin - $display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]); - if (STOP_ON_ERROR) $stop(0); - end else begin - if (DEBUG) $display ("%m: at time %t INFO: %s", $time, cmd_string[cmd]); - er_trfc_max = 0; - ref_cntr = ref_cntr + 1; - tm_refresh <= $time; - ck_refresh <= ck_cntr; - end - end - PRECHARGE : begin - if (addr[AP]) begin - if (DEBUG) $display ("%m: at time %t INFO: %s All", $time, cmd_string[cmd]); - end - // PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state), - // or if the previously open row is already in the process of precharging - if (|active_bank) begin - if (($time - tm_txpr < TXPR) || (ck_cntr - ck_txpr < TXPR_TCK)) - $display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[cmd]); - if (mpr_en) begin - $display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]); - if (STOP_ON_ERROR) $stop(0); - end else begin - for (i=0; i<`BANKS; i=i+1) begin - if (active_bank[i]) begin - if (addr[AP] || (i == bank)) begin - - for (j=0; j<=SELF_REF; j=j+1) begin - chk_err(SAME_BANK, i, j, cmd); - chk_err(DIFF_BANK, i, j, cmd); - end - - if (auto_precharge_bank[i]) begin - $display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], i); - if (STOP_ON_ERROR) $stop(0); - end else begin - if (DEBUG) $display ("%m: at time %t INFO: %s bank %d", $time, cmd_string[cmd], i); - active_bank[i] = 1'b0; - tm_bank_precharge[i] <= $time; - tm_precharge <= $time; - ck_precharge <= ck_cntr; - end - end - end - end - end - end // if (|active_bank) - else begin - chk_err(DIFF_BANK, 0, REFRESH, PRECHARGE); - end - end - ACTIVATE : begin - tfaw_cntr = 0; - for (i=0; i<`BANKS; i=i+1) begin - if ($time - tm_bank_activate[i] < TFAW) begin - tfaw_cntr = tfaw_cntr + 1; - end - end - if (tfaw_cntr > 3) begin - $display ("%m: at time %t ERROR: tFAW violation during %s to bank %d", $time, cmd_string[cmd], bank); - end - - if (mpr_en) begin - $display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]); - if (STOP_ON_ERROR) $stop(0); - end else if (!init_done) begin - $display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]); - if (STOP_ON_ERROR) $stop(0); - end else if (active_bank[bank]) begin - $display ("%m: at time %t ERROR: %s Failure. Bank %d must be Precharged.", $time, cmd_string[cmd], bank); - if (STOP_ON_ERROR) $stop(0); - end else begin - if (addr >= 1< AP -`else - col = {addr[BC-1:AP+1], addr[AP-1:0]}; // assume BC > AP -`endif - if (col >= 1< AP -`else - col = {addr[BC-1:AP+1], addr[AP-1:0]}; // assume BC > AP -`endif - if (col >= 1< TPD_MAX) - $display ("%m: at time %t ERROR: tPD maximum violation during Power Down Exit", $time); - if (DEBUG) $display ("%m: at time %t INFO: Power Down Exit", $time); - in_power_down = 0; - if ((active_bank == 0) && low_power) begin // precharge power down with dll off - if (ck_cntr - ck_odt < write_latency - 1) - $display ("%m: at time %t WARNING: tANPD violation during Power Down Exit. Synchronous or asynchronous change in termination resistance is possible.", $time); - tm_slow_exit_pd <= $time; - ck_slow_exit_pd <= ck_cntr; - end - tm_power_down <= $time; - ck_power_down <= ck_cntr; - end - if (in_self_refresh) begin - if (($time - tm_freq_change < TCKSRX) || (ck_cntr - ck_freq_change < TCKSRX_TCK)) - $display ("%m: at time %t ERROR: tCKSRX violation during Self Refresh Exit", $time); - if (ck_cntr - ck_cke_cmd < TCKESR_TCK) - $display ("%m: at time %t ERROR: tCKESR violation during Self Refresh Exit", $time); - if ($time - tm_cke < TISXR) - $display ("%m: at time %t ERROR: tISXR violation during Self Refresh Exit", $time); - if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Exit", $time); - in_self_refresh = 0; - ck_dll_reset <= ck_cntr; - ck_self_refresh <= ck_cntr; - tm_self_refresh <= $time; - tm_refresh <= $time; - end - end - endcase - if ((prev_cke !== 1) && (cmd !== NOP)) begin - $display ("%m: at time %t ERROR: NOP or Deselect is required when CKE goes active.", $time); - end - - if (!init_done) begin - case (init_step) - 0 : begin - if ($time - tm_rst_n < 500000000 && check_strict_timing) - $display ("%m at time %t WARNING: 500 us is required after RST_N goes inactive before CKE goes active.", $time); - tm_txpr <= $time; - ck_txpr <= ck_cntr; - init_step = init_step + 1; - end - 1 : begin - if (dll_en) init_step = init_step + 1; - end - 2 : begin - if (&init_mode_reg && init_dll_reset && zq_set) begin - if (DEBUG) $display ("%m: at time %t INFO: Initialization Sequence is complete", $time); - init_done = 1; - end - end - endcase - end - end else if (prev_cke) begin - if ((!init_done) && (init_step > 1)) begin - $display ("%m: at time %t ERROR: CKE must remain active until the initialization sequence is complete.", $time); - if (STOP_ON_ERROR) $stop(0); - end - case (cmd) - REFRESH : begin - if ($time - tm_txpr < TXPR) - $display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[SELF_REF]); - for (j=0; j<=SELF_REF; j=j+1) begin - chk_err(DIFF_BANK, bank, j, SELF_REF); - end - - if (mpr_en) begin - $display ("%m: at time %t ERROR: Self Refresh Failure. Multipurpose Register must be disabled.", $time); - if (STOP_ON_ERROR) $stop(0); - end else if (|active_bank) begin - $display ("%m: at time %t ERROR: Self Refresh Failure. All banks must be Precharged.", $time); - if (STOP_ON_ERROR) $stop(0); - end else if (odt_state) begin - $display ("%m: at time %t ERROR: Self Refresh Failure. ODT must be off prior to entering Self Refresh", $time); - if (STOP_ON_ERROR) $stop(0); - end else if (!init_done) begin - $display ("%m: at time %t ERROR: Self Refresh Failure. Initialization sequence is not complete.", $time); - if (STOP_ON_ERROR) $stop(0); - end else begin - if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Enter", $time); - if (feature_pasr) - // Partial Array Self Refresh - case (pasr) - 3'b000 : ;//keep Bank 0-7 - 3'b001 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 4-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hF0); end - 3'b010 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 2-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hFC); end - 3'b011 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 1-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hFE); end - 3'b100 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-1 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h03); end - 3'b101 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-3 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h0F); end - 3'b110 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-5 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h3F); end - 3'b111 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-6 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h7F); end - endcase - in_self_refresh = 1; - dll_locked = 0; - end - end - NOP : begin - // entering precharge power down with dll off and tANPD has not been satisfied - if (low_power && (active_bank == 0) && |odt_pipeline) - $display ("%m: at time %t WARNING: tANPD violation during %s. Synchronous or asynchronous change in termination resistance is possible.", $time, cmd_string[PWR_DOWN]); - if ($time - tm_txpr < TXPR) - $display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[PWR_DOWN]); - for (j=0; j<=SELF_REF; j=j+1) begin - chk_err(DIFF_BANK, bank, j, PWR_DOWN); - end - - if (mpr_en) begin - $display ("%m: at time %t ERROR: Power Down Failure. Multipurpose Register must be disabled.", $time); - if (STOP_ON_ERROR) $stop(0); - end else if (!init_done) begin - $display ("%m: at time %t ERROR: Power Down Failure. Initialization sequence is not complete.", $time); - if (STOP_ON_ERROR) $stop(0); - end else begin - if (DEBUG) begin - if (|active_bank) begin - $display ("%m: at time %t INFO: Active Power Down Enter", $time); - end else begin - $display ("%m: at time %t INFO: Precharge Power Down Enter", $time); - end - end - in_power_down = 1; - end - end - default : begin - $display ("%m: at time %t ERROR: NOP, Deselect, or Refresh is required when CKE goes inactive.", $time); - end - endcase - end else if (in_self_refresh || in_power_down) begin - if ((ck_cntr - ck_cke_cmd <= TCPDED) && (cmd !== NOP)) - $display ("%m: at time %t ERROR: tCPDED violation during Power Down or Self Refresh Entry. NOP or Deselect is required.", $time); - end - prev_cke = cke; - - end - endtask - - task data_task; - reg [BA_BITS-1:0] bank; - reg [ROW_BITS-1:0] row; - reg [COL_BITS-1:0] col; - integer i; - integer j; - begin - - if (diff_ck) begin - for (i=0; i<64; i=i+1) begin - if (dq_in_valid && dll_locked && ($time - tm_dqs_neg[i] < $rtoi(TDSS*tck_avg))) - $display ("%m: at time %t ERROR: tDSS violation on %s bit %d", $time, dqs_string[i/32], i%32); - if (check_write_dqs_high[i]) - $display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period.", $time, dqs_string[i/32], i%32); - end - check_write_dqs_high <= 0; - end else begin - for (i=0; i<64; i=i+1) begin - if (dll_locked && dq_in_valid) begin - tm_tdqss = abs_value(1.0*tm_ck_pos - tm_dqss_pos[i]); - if ((tm_tdqss < tck_avg/2.0) && (tm_tdqss > TDQSS*tck_avg)) - $display ("%m: at time %t ERROR: tDQSS violation on %s bit %d", $time, dqs_string[i/32], i%32); - end - if (check_write_dqs_low[i]) - $display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period", $time, dqs_string[i/32], i%32); - end - check_write_preamble <= 0; - check_write_postamble <= 0; - check_write_dqs_low <= 0; - end - - if (wr_pipeline[0] || rd_pipeline[0]) begin - bank = ba_pipeline[0]; - row = row_pipeline[0]; - col = col_pipeline[0]; - burst_cntr = 0; - memory_read(bank, row, col, memory_data); - end - - // burst counter - if (burst_cntr < burst_length) begin - burst_position = col ^ burst_cntr; - if (!burst_order) begin - burst_position[BO_BITS-1:0] = col + burst_cntr; - end - burst_cntr = burst_cntr + 1; - end - - // write dqs counter - if (wr_pipeline[WDQS_PRE + 1]) begin - wdqs_cntr = WDQS_PRE + bl_pipeline[WDQS_PRE + 1] + WDQS_PST - 1; - end - // write dqs - if ((wr_pipeline[2]) && (wdq_cntr == 0)) begin //write preamble - check_write_preamble <= ({DQS_BITS{1'b1}}<<32) | {DQS_BITS{1'b1}}; - end - if (wdqs_cntr > 1) begin // write data - if ((wdqs_cntr - WDQS_PST)%2) begin - check_write_dqs_high <= ({DQS_BITS{1'b1}}<<32) | {DQS_BITS{1'b1}}; - end else begin - check_write_dqs_low <= ({DQS_BITS{1'b1}}<<32) | {DQS_BITS{1'b1}}; - end - end - if (wdqs_cntr == WDQS_PST) begin // write postamble - check_write_postamble <= ({DQS_BITS{1'b1}}<<32) | {DQS_BITS{1'b1}}; - end - if (wdqs_cntr > 0) begin - wdqs_cntr = wdqs_cntr - 1; - end - - // write dq - if (dq_in_valid) begin // write data - bit_mask = 0; - if (diff_ck) begin - for (i=0; i>(burst_position*DQ_BITS); - if (DEBUG) $display ("%m: at time %t INFO: WRITE @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp); - if (burst_cntr%BL_MIN == 0) begin - memory_write(bank, row, col, memory_data); - end - end - if (wr_pipeline[1]) begin - wdq_cntr = bl_pipeline[1]; - end - if (wdq_cntr > 0) begin - wdq_cntr = wdq_cntr - 1; - dq_in_valid = 1'b1; - end else begin - dq_in_valid = 1'b0; - dqs_in_valid <= 1'b0; - for (i=0; i<63; i=i+1) begin - wdqs_pos_cntr[i] <= 0; - end - end - if (wr_pipeline[0]) begin - b2b_write <= 1'b0; - end - if (wr_pipeline[2]) begin - if (dqs_in_valid) begin - b2b_write <= 1'b1; - end - dqs_in_valid <= 1'b1; - wr_burst_length = bl_pipeline[2]; - end - - // read dqs enable counter - if (rd_pipeline[RDQSEN_PRE]) begin - rdqsen_cntr = RDQSEN_PRE + bl_pipeline[RDQSEN_PRE] + RDQSEN_PST - 1; - end - if (rdqsen_cntr > 0) begin - rdqsen_cntr = rdqsen_cntr - 1; - dqs_out_en = 1'b1; - end else begin - dqs_out_en = 1'b0; - end - - // read dqs counter - if (rd_pipeline[RDQS_PRE]) begin - rdqs_cntr = RDQS_PRE + bl_pipeline[RDQS_PRE] + RDQS_PST - 1; - end - // read dqs - if (((rd_pipeline>>1 & {RDQS_PRE{1'b1}}) > 0) && (rdq_cntr == 0)) begin //read preamble - dqs_out = 1'b0; - end else if (rdqs_cntr > RDQS_PST) begin // read data - dqs_out = rdqs_cntr - RDQS_PST; - end else if (rdqs_cntr > 0) begin // read postamble - dqs_out = 1'b0; - end else begin - dqs_out = 1'b1; - end - if (rdqs_cntr > 0) begin - rdqs_cntr = rdqs_cntr - 1; - end - - // read dq enable counter - if (rd_pipeline[RDQEN_PRE]) begin - rdqen_cntr = RDQEN_PRE + bl_pipeline[RDQEN_PRE] + RDQEN_PST; - end - if (rdqen_cntr > 0) begin - rdqen_cntr = rdqen_cntr - 1; - dq_out_en = 1'b1; - end else begin - dq_out_en = 1'b0; - end - // read dq - if (rd_pipeline[0]) begin - rdq_cntr = bl_pipeline[0]; - end - if (rdq_cntr > 0) begin // read data - if (mpr_en) begin -`ifdef MPR_DQ0 // DQ0 output MPR data, other DQ low - if (mpr_select == 2'b00) begin // Calibration Pattern - dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, calibration_pattern[burst_position]}}; - end else if (odts_readout && (mpr_select == 2'b11)) begin // Temp Sensor (ODTS) - dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, temp_sensor[burst_position]}}; - end else begin // Reserved - dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, 1'bx}}; - end -`else // all DQ output MPR data - if (mpr_select == 2'b00) begin // Calibration Pattern - dq_temp = {DQS_BITS{{`DQ_PER_DQS{calibration_pattern[burst_position]}}}}; - end else if (odts_readout && (mpr_select == 2'b11)) begin // Temp Sensor (ODTS) - dq_temp = {DQS_BITS{{`DQ_PER_DQS{temp_sensor[burst_position]}}}}; - end else begin // Reserved - dq_temp = {DQS_BITS{{`DQ_PER_DQS{1'bx}}}}; - end -`endif - if (DEBUG) $display ("%m: at time %t READ @ DQS MultiPurpose Register %d, col = %d, data = %b", $time, mpr_select, burst_position, dq_temp[0]); - end else begin - dq_temp = memory_data>>(burst_position*DQ_BITS); - if (DEBUG) $display ("%m: at time %t INFO: READ @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp); - end - dq_out = dq_temp; - rdq_cntr = rdq_cntr - 1; - end else begin - dq_out = {DQ_BITS{1'b1}}; - end - - // delay signals prior to output - if (RANDOM_OUT_DELAY && (dqs_out_en || (|dqs_out_en_dly) || dq_out_en || (|dq_out_en_dly))) begin - for (i=0; i dqsck[i] + TQH*tck_avg + TDQSQ) begin - dqsck_max = dqsck[i] + TQH*tck_avg + TDQSQ; - end - dqsck_min = -1*TDQSCK; - if (dqsck_min < dqsck[i] - TQH*tck_avg - TDQSQ) begin - dqsck_min = dqsck[i] - TQH*tck_avg - TDQSQ; - end - - // DQSQ requirements - // 1.) less than tDQSQ - // 2.) greater than 0 - // 3.) greater than tQH from the previous DQS edge - dqsq_min = 0; - if (dqsq_min < dqsck[i] - TQH*tck_avg) begin - dqsq_min = dqsck[i] - TQH*tck_avg; - end - if (dqsck_min == dqsck_max) begin - dqsck[i] = dqsck_min; - end else begin - dqsck[i] = $dist_uniform(seed, dqsck_min, dqsck_max); - end - dqsq_max = TDQSQ + dqsck[i]; - - dqs_out_en_dly[i] <= #(tck_avg/2) dqs_out_en; - dqs_out_dly[i] <= #(tck_avg/2 + dqsck[i]) dqs_out; - if (!write_levelization) begin - for (j=0; j<`DQ_PER_DQS; j=j+1) begin - dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2) dq_out_en; - if (dqsq_min == dqsq_max) begin - dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2 + dqsq_min) dq_out[i*`DQ_PER_DQS + j]; - end else begin - dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2 + $dist_uniform(seed, dqsq_min, dqsq_max)) dq_out[i*`DQ_PER_DQS + j]; - end - end - end - end - end else begin - if (dll_en) - if(diff_ck) - out_delay = ($rtoi(tch_avg) > 50000) ? 0 : $rtoi(tch_avg); - else - out_delay = ($rtoi(tcl_avg) > 50000) ? 0 : $rtoi(tcl_avg); - else - if(diff_ck) - out_delay = ($rtoi(tch_avg) > 50000) ? 0 : $rtoi(tch_avg) + TDQSCK_DLLDIS; - else - out_delay = ($rtoi(tcl_avg) > 50000) ? 0 : $rtoi(tcl_avg) + TDQSCK_DLLDIS; - dqs_out_en_dly <= #(out_delay) {DQS_BITS{dqs_out_en}}; - dqs_out_dly <= #(out_delay) {DQS_BITS{dqs_out }}; - if (write_levelization !== 1'b1) begin - dq_out_en_dly <= #(out_delay) {DQ_BITS {dq_out_en }}; - dq_out_dly <= #(out_delay) {DQ_BITS {dq_out }}; - end - end - end - endtask - - always @ (posedge rst_n_in) begin : reset - integer i; - if (rst_n_in) begin - if ($time < 200000000 && check_strict_timing) - $display ("%m at time %t WARNING: 200 us is required before RST_N goes inactive.", $time); - if (cke_in !== 1'b0) - $display ("%m: at time %t ERROR: CKE must be inactive when RST_N goes inactive.", $time); - if ($time - tm_cke < 10000) - $display ("%m: at time %t ERROR: CKE must be maintained inactive for 10 ns before RST_N goes inactive.", $time); - - // clear memory -`ifdef MAX_MEM - // verification group does not erase memory - // for (banki = 0; banki < `BANKS; banki = banki + 1) begin - // $fclose(memfd[banki]); - // memfd[banki] = open_bank_file(banki); - // end -`else - memory_used <= 0; //erase memory -`endif - - end - end - - always @(negedge rst_n_in or posedge diff_ck or negedge diff_ck) begin : main - integer i; - if (!rst_n_in) begin - reset_task; - end else begin - if (!in_self_refresh && (diff_ck !== 1'b0) && (diff_ck !== 1'b1)) - $display ("%m: at time %t ERROR: CK and CK_N are not allowed to go to an unknown state.", $time); - data_task; - - // Clock Frequency Change is legal: - // 1.) During Self Refresh - // 2.) During Precharge Power Down (DLL on or off) - if (in_self_refresh || (in_power_down && (active_bank == 0))) begin - if (diff_ck) begin - tjit_per_rtime = $time - tm_ck_pos - tck_avg; - end else begin - tjit_per_rtime = $time - tm_ck_neg - tck_avg; - end - if (dll_locked && (abs_value(tjit_per_rtime) > TJIT_PER)) begin - if ((tm_ck_pos - tm_cke_cmd < TCKSRE) || (ck_cntr - ck_cke_cmd < TCKSRE_TCK)) - $display ("%m: at time %t ERROR: tCKSRE violation during Self Refresh or Precharge Power Down Entry", $time); - if (odt_state) begin - $display ("%m: at time %t ERROR: Clock Frequency Change Failure. ODT must be off prior to Clock Frequency Change.", $time); - if (STOP_ON_ERROR) $stop(0); - end else begin - if (DEBUG) $display ("%m: at time %t INFO: Clock Frequency Change detected. DLL Reset is Required.", $time); - tm_freq_change <= $time; - ck_freq_change <= ck_cntr; - dll_locked = 0; - end - end - end - - if (diff_ck) begin - // check setup of command signals - if ($time > TIS) begin - if ($time - tm_cke < TIS) - $display ("%m: at time %t ERROR: tIS violation on CKE by %t", $time, tm_cke + TIS - $time); - if (cke_in) begin - for (i=0; i<23; i=i+1) begin - if ($time - tm_cmd_addr[i] < TIS) - $display ("%m: at time %t ERROR: tIS violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIS - $time); - end - end - end - - // update current state - if (dll_locked) begin - if (mr_chk == 0) begin - mr_chk = 1; - end else if (init_mode_reg[0] && (mr_chk == 1)) begin - // check CL value against the clock frequency - // check WR value against the clock frequency - if (ceil(write_recovery*tck_avg) < TWR) - $display ("%m: at time %t ERROR: Write Recovery = %d is illegal @tCK(avg) = %f", $time, write_recovery, tck_avg); - // check the CWL value against the clock frequency - if (check_strict_timing) begin - case (cas_write_latency) - 5 : if (tck_avg < 2500.0) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); - 6 : if ((tck_avg < 1875.0) || (tck_avg >= 2500.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); - 7 : if ((tck_avg < 1500.0) || (tck_avg >= 1875.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); - 8 : if ((tck_avg < 1250.0) || (tck_avg >= 1500.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); - 9 : if ((tck_avg < 15e3/14) || (tck_avg >= 1250.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); - 10: if ((tck_avg < 937.5) || (tck_avg >= 15e3/14)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); - default : $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); - endcase - // check the CL value against the clock frequency - if (!valid_cl(cas_latency, cas_write_latency)) - $display ("%m: at time %t ERROR: CAS Latency = %d is not valid when CAS Write Latency = %d", $time, cas_latency, cas_write_latency); - end - mr_chk = 2; - end - end else if (!in_self_refresh) begin - mr_chk = 0; - if (ck_cntr - ck_dll_reset == TDLLK) begin - dll_locked = 1; - end - end - - if (|auto_precharge_bank) begin - for (i=0; i<`BANKS; i=i+1) begin - // Write with Auto Precharge Calculation - // 1. Meet minimum tRAS requirement - // 2. Write Latency PLUS BL/2 cycles PLUS WR after Write command - if (write_precharge_bank[i]) begin - if ($time - tm_bank_activate[i] >= TRAS_MIN) begin - if (ck_cntr - ck_bank_write[i] >= write_latency + burst_length/2 + write_recovery) begin - if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i); - write_precharge_bank[i] = 0; - active_bank[i] = 0; - auto_precharge_bank[i] = 0; - tm_bank_precharge[i] = $time; - tm_precharge = $time; - ck_precharge = ck_cntr; - end - end - end - // Read with Auto Precharge Calculation - // 1. Meet minimum tRAS requirement - // 2. Additive Latency plus 4 cycles after Read command - // 3. tRTP after the last 8-bit prefetch - if (read_precharge_bank[i]) begin - if (($time - tm_bank_activate[i] >= TRAS_MIN) && (ck_cntr - ck_bank_read[i] >= additive_latency + TRTP_TCK)) begin - read_precharge_bank[i] = 0; - // In case the internal precharge is pushed out by tRTP, tRP starts at the point where - // the internal precharge happens (not at the next rising clock edge after this event). - if ($time - tm_bank_read_end[i] < TRTP) begin - if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", tm_bank_read_end[i] + TRTP, i); - active_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0; - auto_precharge_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0; - tm_bank_precharge[i] <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP; - tm_precharge <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP; - ck_precharge = ck_cntr; - end else begin - if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i); - active_bank[i] = 0; - auto_precharge_bank[i] = 0; - tm_bank_precharge[i] = $time; - tm_precharge = $time; - ck_precharge = ck_cntr; - end - end - end - end - end - - - // respond to incoming command - if (cke_in ^ prev_cke) begin - tm_cke_cmd <= $time; - ck_cke_cmd <= ck_cntr; - end - - - cmd_task(prev_cke, cke_in, cmd_n_in, ba_in, addr_in); - if ((cmd_n_in == WRITE) || (cmd_n_in == READ)) begin - al_pipeline[2*additive_latency] = 1'b1; - end - if (al_pipeline[0]) begin - // check tRCD after additive latency - if ((rd_pipeline[2*cas_latency - 1]) && ($time - tm_bank_activate[ba_pipeline[2*cas_latency - 1]] < TRCD)) - $display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[READ]); - if ((wr_pipeline[2*cas_write_latency + 1]) && ($time - tm_bank_activate[ba_pipeline[2*cas_write_latency + 1]] < TRCD)) - $display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[WRITE]); - // check tWTR after additive latency - if (rd_pipeline[2*cas_latency - 1]) begin //{ - if (truebl4) begin //{ - i = ba_pipeline[2*cas_latency - 1]; - if ($time - tm_group_write_end[i[1]] < TWTR) - $display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]); - if ($time - tm_write_end < TWTR_DG) - $display ("%m: at time %t ERROR: tWTR_DG violation during %s", $time, cmd_string[READ]); - end else begin - if ($time - tm_write_end < TWTR) - $display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]); - end - end - end - if (rd_pipeline) begin - if (rd_pipeline[2*cas_latency - 1]) begin - tm_bank_read_end[ba_pipeline[2*cas_latency - 1]] <= $time; - end - end - for (i=0; i<`BANKS; i=i+1) begin - if ((ck_cntr - ck_bank_write[i] > write_latency) && (ck_cntr - ck_bank_write[i] <= write_latency + burst_length/2)) begin - tm_bank_write_end[i] <= $time; - tm_group_write_end[i[1]] <= $time; - tm_write_end <= $time; - end - end - - // clk pin is disabled during self refresh - if (!in_self_refresh && tm_ck_pos ) begin - tjit_cc_time = $time - tm_ck_pos - tck_i; - tck_i = $time - tm_ck_pos; - tck_avg = tck_avg - tck_sample[ck_cntr%PERTCKAVG]/$itor(PERTCKAVG); - tck_avg = tck_avg + tck_i/$itor(PERTCKAVG); - tck_sample[ck_cntr%PERTCKAVG] = tck_i; - tjit_per_rtime = tck_i - tck_avg; - - if (dll_locked && check_strict_timing) begin - // check accumulated error - terr_nper_rtime = 0; - for (i=0; i<12; i=i+1) begin - terr_nper_rtime = terr_nper_rtime + tck_sample[i] - tck_avg; - terr_nper_rtime = abs_value(terr_nper_rtime); - case (i) - 0 :; - 1 : if (terr_nper_rtime - TERR_2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(2per) violation by %f ps.", $time, terr_nper_rtime - TERR_2PER); - 2 : if (terr_nper_rtime - TERR_3PER >= 1.0) $display ("%m: at time %t ERROR: tERR(3per) violation by %f ps.", $time, terr_nper_rtime - TERR_3PER); - 3 : if (terr_nper_rtime - TERR_4PER >= 1.0) $display ("%m: at time %t ERROR: tERR(4per) violation by %f ps.", $time, terr_nper_rtime - TERR_4PER); - 4 : if (terr_nper_rtime - TERR_5PER >= 1.0) $display ("%m: at time %t ERROR: tERR(5per) violation by %f ps.", $time, terr_nper_rtime - TERR_5PER); - 5 : if (terr_nper_rtime - TERR_6PER >= 1.0) $display ("%m: at time %t ERROR: tERR(6per) violation by %f ps.", $time, terr_nper_rtime - TERR_6PER); - 6 : if (terr_nper_rtime - TERR_7PER >= 1.0) $display ("%m: at time %t ERROR: tERR(7per) violation by %f ps.", $time, terr_nper_rtime - TERR_7PER); - 7 : if (terr_nper_rtime - TERR_8PER >= 1.0) $display ("%m: at time %t ERROR: tERR(8per) violation by %f ps.", $time, terr_nper_rtime - TERR_8PER); - 8 : if (terr_nper_rtime - TERR_9PER >= 1.0) $display ("%m: at time %t ERROR: tERR(9per) violation by %f ps.", $time, terr_nper_rtime - TERR_9PER); - 9 : if (terr_nper_rtime - TERR_10PER >= 1.0) $display ("%m: at time %t ERROR: tERR(10per) violation by %f ps.", $time, terr_nper_rtime - TERR_10PER); - 10 : if (terr_nper_rtime - TERR_11PER >= 1.0) $display ("%m: at time %t ERROR: tERR(11per) violation by %f ps.", $time, terr_nper_rtime - TERR_11PER); - 11 : if (terr_nper_rtime - TERR_12PER >= 1.0) $display ("%m: at time %t ERROR: tERR(12per) violation by %f ps.", $time, terr_nper_rtime - TERR_12PER); - endcase - end - - // check tCK min/max/jitter - if (abs_value(tjit_per_rtime) - TJIT_PER >= 1.0) - $display ("%m: at time %t ERROR: tJIT(per) violation by %f ps.", $time, abs_value(tjit_per_rtime) - TJIT_PER); - if (abs_value(tjit_cc_time) - TJIT_CC >= 1.0) - $display ("%m: at time %t ERROR: tJIT(cc) violation by %f ps.", $time, abs_value(tjit_cc_time) - TJIT_CC); - if (TCK_MIN - tck_avg >= 1.0) - $display ("%m: at time %t ERROR: tCK(avg) minimum violation by %f ps.", $time, TCK_MIN - tck_avg); - if (tck_avg - TCK_MAX >= 1.0) - $display ("%m: at time %t ERROR: tCK(avg) maximum violation by %f ps.", $time, tck_avg - TCK_MAX); - - // check tCL - if (tm_ck_neg - $time < TCL_ABS_MIN*tck_avg) - $display ("%m: at time %t ERROR: tCL(abs) minimum violation on CLK by %t", $time, TCL_ABS_MIN*tck_avg - tm_ck_neg + $time); - if (tcl_avg < TCL_AVG_MIN*tck_avg) - $display ("%m: at time %t ERROR: tCL(avg) minimum violation on CLK by %t", $time, TCL_AVG_MIN*tck_avg - tcl_avg); - if (tcl_avg > TCL_AVG_MAX*tck_avg) - $display ("%m: at time %t ERROR: tCL(avg) maximum violation on CLK by %t", $time, tcl_avg - TCL_AVG_MAX*tck_avg); - end - - // calculate the tch avg jitter - tch_avg = tch_avg - tch_sample[ck_cntr%PERTCKAVG]/$itor(PERTCKAVG); - tch_avg = tch_avg + tch_i/$itor(PERTCKAVG); - tch_sample[ck_cntr%PERTCKAVG] = tch_i; - tjit_ch_rtime = tch_i - tch_avg; - duty_cycle = $rtoi(tch_avg*100/tck_avg); - - // update timers/counters - tcl_i <= $time - tm_ck_neg; - end - - prev_odt <= odt_in; - // update timers/counters - ck_cntr <= ck_cntr + 1; - tm_ck_pos = $time; - end else begin - // clk pin is disabled during self refresh - if (!in_self_refresh) begin - if (dll_locked && check_strict_timing) begin - if ($time - tm_ck_pos < TCH_ABS_MIN*tck_avg) - $display ("%m: at time %t ERROR: tCH(abs) minimum violation on CLK by %t", $time, TCH_ABS_MIN*tck_avg - $time + tm_ck_pos); - if (tch_avg < TCH_AVG_MIN*tck_avg) - $display ("%m: at time %t ERROR: tCH(avg) minimum violation on CLK by %t", $time, TCH_AVG_MIN*tck_avg - tch_avg); - if (tch_avg > TCH_AVG_MAX*tck_avg) - $display ("%m: at time %t ERROR: tCH(avg) maximum violation on CLK by %t", $time, tch_avg - TCH_AVG_MAX*tck_avg); - end - - // calculate the tcl avg jitter - tcl_avg = tcl_avg - tcl_sample[ck_cntr%PERTCKAVG]/$itor(PERTCKAVG); - tcl_avg = tcl_avg + tcl_i/$itor(PERTCKAVG); - tcl_sample[ck_cntr%PERTCKAVG] = tcl_i; - - // update timers/counters - tch_i <= $time - tm_ck_pos; - end - tm_ck_neg = $time; - end - - // on die termination - if (odt_en || dyn_odt_en) begin - // odt pin is disabled during self refresh - if (!in_self_refresh && diff_ck) begin - if ($time - tm_odt < TIS) - $display ("%m: at time %t ERROR: tIS violation on ODT by %t", $time, tm_odt + TIS - $time); - if (prev_odt ^ odt_in) begin - if (!dll_locked) - $display ("%m: at time %t WARNING: tDLLK violation during ODT transition.", $time); - if (($time - tm_load_mode < TMOD) || (ck_cntr - ck_load_mode < TMOD_TCK)) - $display ("%m: at time %t ERROR: tMOD violation during ODT transition", $time); - if (ck_cntr - ck_zqinit < TZQINIT) - $display ("%m: at time %t ERROR: TZQinit violation during ODT transition", $time); - if (ck_cntr - ck_zqoper < TZQOPER) - $display ("%m: at time %t ERROR: TZQoper violation during ODT transition", $time); - if (ck_cntr - ck_zqcs < TZQCS) - $display ("%m: at time %t ERROR: tZQcs violation during ODT transition", $time); - // if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) - // $display ("%m: at time %t ERROR: tXPDLL violation during ODT transition", $time); - if (ck_cntr - ck_self_refresh < TXSDLL) - $display ("%m: at time %t ERROR: tXSDLL violation during ODT transition", $time); - if (in_self_refresh) - $display ("%m: at time %t ERROR: Illegal ODT transition during Self Refresh.", $time); - if (!odt_in && (ck_cntr - ck_odt < ODTH4)) - $display ("%m: at time %t ERROR: ODTH4 violation during ODT transition", $time); - if (!odt_in && (ck_cntr - ck_odth8 < ODTH8)) - $display ("%m: at time %t ERROR: ODTH8 violation during ODT transition", $time); - if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) - $display ("%m: at time %t WARNING: tXPDLL during ODT transition. Synchronous or asynchronous change in termination resistance is possible.", $time); - - // async ODT mode applies: - // 1.) during precharge power down with DLL off - // 2.) if tANPD has not been satisfied - // 3.) until tXPDLL has been satisfied - if ((in_power_down && low_power && (active_bank == 0)) || ($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) begin - odt_state = odt_in; - if (DEBUG && odt_en) $display ("%m: at time %t INFO: Async On Die Termination Rtt_NOM = %d Ohm", $time, {32{odt_state}} & get_rtt_nom(odt_rtt_nom)); - if (odt_state) begin - odt_state_dly <= #(TAONPD) odt_state; - end else begin - odt_state_dly <= #(TAOFPD) odt_state; - end - // sync ODT mode applies: - // 1.) during normal operation - // 2.) during active power down - // 3.) during precharge power down with DLL on - end else begin - odt_pipeline[2*(write_latency - 2)] = 1'b1; // ODTLon, ODTLoff - end - ck_odt <= ck_cntr; - end - end - if (odt_pipeline[0]) begin - odt_state = ~odt_state; - if (DEBUG && odt_en) $display ("%m: at time %t INFO: Sync On Die Termination Rtt_NOM = %d Ohm", $time, {32{odt_state}} & get_rtt_nom(odt_rtt_nom)); - if (odt_state) begin - odt_state_dly <= #(TAON) odt_state; - end else begin - odt_state_dly <= #(TAOF*tck_avg) odt_state; - end - end - if (rd_pipeline[RDQSEN_PRE]) begin - odt_cntr = 1 + RDQSEN_PRE + bl_pipeline[RDQSEN_PRE] + RDQSEN_PST - 1; - end - if (odt_cntr > 0) begin - if ((get_rtt_nom(odt_rtt_nom) > 0) && odt_state) begin - $display ("%m: at time %t ERROR: On Die Termination must be OFF during Read data transfer.", $time); - end - odt_cntr = odt_cntr - 1; - end - if (dyn_odt_en && ( odt_state || feature_odt_hi) ) begin - if (DEBUG && (dyn_odt_state ^ dyn_odt_pipeline[0])) - $display ("%m: at time %t INFO: Sync On Die Termination Rtt_WR = %d Ohm", $time, {32{dyn_odt_pipeline[0]}} & get_rtt_wr(odt_rtt_wr)); - dyn_odt_state = dyn_odt_pipeline[0]; - end - dyn_odt_state_dly <= #(TADC*tck_avg) dyn_odt_state; - end - - if (cke_in && write_levelization) begin - for (i=0; i>1; - wr_pipeline = wr_pipeline>>1; - rd_pipeline = rd_pipeline>>1; - for (i=0; i<`MAX_PIPE; i=i+1) begin - bl_pipeline[i] = bl_pipeline[i+1]; - ba_pipeline[i] = ba_pipeline[i+1]; - row_pipeline[i] = row_pipeline[i+1]; - col_pipeline[i] = col_pipeline[i+1]; - end - end - if (|odt_pipeline || |dyn_odt_pipeline) begin - odt_pipeline = odt_pipeline>>1; - dyn_odt_pipeline = dyn_odt_pipeline>>1; - end - end - end - - // receiver(s) - task dqs_even_receiver; - input [4:0] i; - reg [127:0] bit_mask; - begin - bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS); - if (dqs_even[i]) begin - if (tdqs_en) begin // tdqs disables dm - dm_in_pos[i] = 1'b0; - end else begin - dm_in_pos[i] = dm_in[i]; - end - dq_in_pos = (dq_in & bit_mask) | (dq_in_pos & ~bit_mask); - end - end - endtask - - always @(posedge dqs_even[ 0]) dqs_even_receiver( 0); - always @(posedge dqs_even[ 1]) dqs_even_receiver( 1); - always @(posedge dqs_even[ 2]) dqs_even_receiver( 2); - always @(posedge dqs_even[ 3]) dqs_even_receiver( 3); - always @(posedge dqs_even[ 4]) dqs_even_receiver( 4); - always @(posedge dqs_even[ 5]) dqs_even_receiver( 5); - always @(posedge dqs_even[ 6]) dqs_even_receiver( 6); - always @(posedge dqs_even[ 7]) dqs_even_receiver( 7); - always @(posedge dqs_even[ 8]) dqs_even_receiver( 8); - always @(posedge dqs_even[ 9]) dqs_even_receiver( 9); - always @(posedge dqs_even[10]) dqs_even_receiver(10); - always @(posedge dqs_even[11]) dqs_even_receiver(11); - always @(posedge dqs_even[12]) dqs_even_receiver(12); - always @(posedge dqs_even[13]) dqs_even_receiver(13); - always @(posedge dqs_even[14]) dqs_even_receiver(14); - always @(posedge dqs_even[15]) dqs_even_receiver(15); - - task dqs_odd_receiver; - input [4:0] i; - reg [127:0] bit_mask; - begin - bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS); - if (dqs_odd[i]) begin - if (tdqs_en) begin // tdqs disables dm - dm_in_neg[i] = 1'b0; - end else begin - dm_in_neg[i] = dm_in[i]; - end - dq_in_neg = (dq_in & bit_mask) | (dq_in_neg & ~bit_mask); - end - end - endtask - - always @(posedge dqs_odd[ 0]) dqs_odd_receiver( 0); - always @(posedge dqs_odd[ 1]) dqs_odd_receiver( 1); - always @(posedge dqs_odd[ 2]) dqs_odd_receiver( 2); - always @(posedge dqs_odd[ 3]) dqs_odd_receiver( 3); - always @(posedge dqs_odd[ 4]) dqs_odd_receiver( 4); - always @(posedge dqs_odd[ 5]) dqs_odd_receiver( 5); - always @(posedge dqs_odd[ 6]) dqs_odd_receiver( 6); - always @(posedge dqs_odd[ 7]) dqs_odd_receiver( 7); - always @(posedge dqs_odd[ 8]) dqs_odd_receiver( 8); - always @(posedge dqs_odd[ 9]) dqs_odd_receiver( 9); - always @(posedge dqs_odd[10]) dqs_odd_receiver(10); - always @(posedge dqs_odd[11]) dqs_odd_receiver(11); - always @(posedge dqs_odd[12]) dqs_odd_receiver(12); - always @(posedge dqs_odd[13]) dqs_odd_receiver(13); - always @(posedge dqs_odd[14]) dqs_odd_receiver(14); - always @(posedge dqs_odd[15]) dqs_odd_receiver(15); - - // Processes to check hold and pulse width of control signals - always @(posedge rst_n_in) begin - if ($time > 100000) begin - if (tm_rst_n + 100000 > $time) - $display ("%m: at time %t ERROR: RST_N pulse width violation by %t", $time, tm_rst_n + 100000 - $time); - end - tm_rst_n = $time; - end - always @(cke_in) begin - if (rst_n_in) begin - if ($time > TIH) begin - if ($time - tm_ck_pos < TIH) - $display ("%m: at time %t ERROR: tIH violation on CKE by %t", $time, tm_ck_pos + TIH - $time); - end - if ($time - tm_cke < TIPW) - $display ("%m: at time %t ERROR: tIPW violation on CKE by %t", $time, tm_cke + TIPW - $time); - end - tm_cke = $time; - end - always @(odt_in) begin - if (rst_n_in && odt_en && !in_self_refresh) begin - if ($time - tm_ck_pos < TIH) - $display ("%m: at time %t ERROR: tIH violation on ODT by %t", $time, tm_ck_pos + TIH - $time); - if ($time - tm_odt < TIPW) - $display ("%m: at time %t ERROR: tIPW violation on ODT by %t", $time, tm_odt + TIPW - $time); - end - tm_odt = $time; - end - - task cmd_addr_timing_check; - input i; - reg [4:0] i; - begin - if (rst_n_in && prev_cke) begin - if ((i == 0) && ($time - tm_ck_pos < TIH)) // always check tIH for CS# - $display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time); - if ((i > 0) && (cs_n_in == 0) &&($time - tm_ck_pos < TIH)) // Only check tIH for cmd_addr if CS# is low - $display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time); - if ((i == 0) && ($time - tm_cmd_addr[i] < TIPW)) // always check tIPW for CS# - $display ("%m: at time %t ERROR: tIPW violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIPW - $time); - if ((i > 0) && (cs_n_in == 0) && ($time - tm_cmd_addr[i] < TIPW)) - $display ("%m: at time %t ERROR: tIPW violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIPW - $time); - end - tm_cmd_addr[i] = $time; - end - endtask - - always @(cs_n_in ) cmd_addr_timing_check( 0); - always @(ras_n_in ) cmd_addr_timing_check( 1); - always @(cas_n_in ) cmd_addr_timing_check( 2); - always @(we_n_in ) cmd_addr_timing_check( 3); - always @(ba_in [ 0]) cmd_addr_timing_check( 4); - always @(ba_in [ 1]) cmd_addr_timing_check( 5); - always @(ba_in [ 2]) cmd_addr_timing_check( 6); - always @(addr_in[ 0]) cmd_addr_timing_check( 7); - always @(addr_in[ 1]) cmd_addr_timing_check( 8); - always @(addr_in[ 2]) cmd_addr_timing_check( 9); - always @(addr_in[ 3]) cmd_addr_timing_check(10); - always @(addr_in[ 4]) cmd_addr_timing_check(11); - always @(addr_in[ 5]) cmd_addr_timing_check(12); - always @(addr_in[ 6]) cmd_addr_timing_check(13); - always @(addr_in[ 7]) cmd_addr_timing_check(14); - always @(addr_in[ 8]) cmd_addr_timing_check(15); - always @(addr_in[ 9]) cmd_addr_timing_check(16); - always @(addr_in[10]) cmd_addr_timing_check(17); - always @(addr_in[11]) cmd_addr_timing_check(18); - always @(addr_in[12]) cmd_addr_timing_check(19); - always @(addr_in[13]) cmd_addr_timing_check(20); - always @(addr_in[14]) cmd_addr_timing_check(21); - always @(addr_in[15]) cmd_addr_timing_check(22); - always @(addr_in[16]) cmd_addr_timing_check(23); - - // Processes to check setup and hold of data signals - task dm_timing_check; - input i; - reg [4:0] i; - begin - if (dqs_in_valid) begin - if ($time - tm_dqs[i] < TDH) - $display ("%m: at time %t ERROR: tDH violation on DM bit %d by %t", $time, i, tm_dqs[i] + TDH - $time); - if (check_dm_tdipw[i]) begin - if ($time - tm_dm[i] < TDIPW) - $display ("%m: at time %t ERROR: tDIPW violation on DM bit %d by %t", $time, i, tm_dm[i] + TDIPW - $time); - end - end - check_dm_tdipw[i] <= 1'b0; - tm_dm[i] = $time; - end - endtask - - always @(dm_in[ 0]) dm_timing_check( 0); - always @(dm_in[ 1]) dm_timing_check( 1); - always @(dm_in[ 2]) dm_timing_check( 2); - always @(dm_in[ 3]) dm_timing_check( 3); - always @(dm_in[ 4]) dm_timing_check( 4); - always @(dm_in[ 5]) dm_timing_check( 5); - always @(dm_in[ 6]) dm_timing_check( 6); - always @(dm_in[ 7]) dm_timing_check( 7); - always @(dm_in[ 8]) dm_timing_check( 8); - always @(dm_in[ 9]) dm_timing_check( 9); - always @(dm_in[10]) dm_timing_check(10); - always @(dm_in[11]) dm_timing_check(11); - always @(dm_in[12]) dm_timing_check(12); - always @(dm_in[13]) dm_timing_check(13); - always @(dm_in[14]) dm_timing_check(14); - always @(dm_in[15]) dm_timing_check(15); - - always @(dm_in[16]) dm_timing_check(16); - always @(dm_in[17]) dm_timing_check(17); - always @(dm_in[18]) dm_timing_check(18); - always @(dm_in[19]) dm_timing_check(19); - always @(dm_in[20]) dm_timing_check(20); - always @(dm_in[21]) dm_timing_check(21); - always @(dm_in[22]) dm_timing_check(22); - always @(dm_in[23]) dm_timing_check(23); - always @(dm_in[24]) dm_timing_check(24); - always @(dm_in[25]) dm_timing_check(25); - always @(dm_in[26]) dm_timing_check(26); - always @(dm_in[27]) dm_timing_check(27); - always @(dm_in[28]) dm_timing_check(28); - always @(dm_in[29]) dm_timing_check(29); - always @(dm_in[30]) dm_timing_check(30); - always @(dm_in[31]) dm_timing_check(31); - - task dq_timing_check; - input i; - reg [6:0] i; - begin - if (dqs_in_valid) begin - if ($time - tm_dqs[i/(`DQ_PER_DQS)] < TDH) - $display ("%m: at time %t ERROR: tDH violation on DQ bit %d by %t", $time, i, tm_dqs[i/`DQ_PER_DQS] + TDH - $time); - if (check_dq_tdipw[i]) begin - if ($time - tm_dq[i] < TDIPW) - $display ("%m: at time %t ERROR: tDIPW violation on DQ bit %d by %t", $time, i, tm_dq[i] + TDIPW - $time); - end - end - check_dq_tdipw[i] <= 1'b0; - tm_dq[i] = $time; - end - endtask - - always @(dq_in[ 0]) dq_timing_check( 0); - always @(dq_in[ 1]) dq_timing_check( 1); - always @(dq_in[ 2]) dq_timing_check( 2); - always @(dq_in[ 3]) dq_timing_check( 3); - always @(dq_in[ 4]) dq_timing_check( 4); - always @(dq_in[ 5]) dq_timing_check( 5); - always @(dq_in[ 6]) dq_timing_check( 6); - always @(dq_in[ 7]) dq_timing_check( 7); - always @(dq_in[ 8]) dq_timing_check( 8); - always @(dq_in[ 9]) dq_timing_check( 9); - always @(dq_in[10]) dq_timing_check(10); - always @(dq_in[11]) dq_timing_check(11); - always @(dq_in[12]) dq_timing_check(12); - always @(dq_in[13]) dq_timing_check(13); - always @(dq_in[14]) dq_timing_check(14); - always @(dq_in[15]) dq_timing_check(15); - always @(dq_in[16]) dq_timing_check(16); - always @(dq_in[17]) dq_timing_check(17); - always @(dq_in[18]) dq_timing_check(18); - always @(dq_in[19]) dq_timing_check(19); - always @(dq_in[20]) dq_timing_check(20); - always @(dq_in[21]) dq_timing_check(21); - always @(dq_in[22]) dq_timing_check(22); - always @(dq_in[23]) dq_timing_check(23); - always @(dq_in[24]) dq_timing_check(24); - always @(dq_in[25]) dq_timing_check(25); - always @(dq_in[26]) dq_timing_check(26); - always @(dq_in[27]) dq_timing_check(27); - always @(dq_in[28]) dq_timing_check(28); - always @(dq_in[29]) dq_timing_check(29); - always @(dq_in[30]) dq_timing_check(30); - always @(dq_in[31]) dq_timing_check(31); - always @(dq_in[32]) dq_timing_check(32); - always @(dq_in[33]) dq_timing_check(33); - always @(dq_in[34]) dq_timing_check(34); - always @(dq_in[35]) dq_timing_check(35); - always @(dq_in[36]) dq_timing_check(36); - always @(dq_in[37]) dq_timing_check(37); - always @(dq_in[38]) dq_timing_check(38); - always @(dq_in[39]) dq_timing_check(39); - always @(dq_in[40]) dq_timing_check(40); - always @(dq_in[41]) dq_timing_check(41); - always @(dq_in[42]) dq_timing_check(42); - always @(dq_in[43]) dq_timing_check(43); - always @(dq_in[44]) dq_timing_check(44); - always @(dq_in[45]) dq_timing_check(45); - always @(dq_in[46]) dq_timing_check(46); - always @(dq_in[47]) dq_timing_check(47); - always @(dq_in[48]) dq_timing_check(48); - always @(dq_in[49]) dq_timing_check(49); - always @(dq_in[50]) dq_timing_check(50); - always @(dq_in[51]) dq_timing_check(51); - always @(dq_in[52]) dq_timing_check(52); - always @(dq_in[53]) dq_timing_check(53); - always @(dq_in[54]) dq_timing_check(54); - always @(dq_in[55]) dq_timing_check(55); - always @(dq_in[56]) dq_timing_check(56); - always @(dq_in[57]) dq_timing_check(57); - always @(dq_in[58]) dq_timing_check(58); - always @(dq_in[59]) dq_timing_check(59); - always @(dq_in[60]) dq_timing_check(60); - always @(dq_in[61]) dq_timing_check(61); - always @(dq_in[62]) dq_timing_check(62); - always @(dq_in[63]) dq_timing_check(63); - - always @(dq_in[64]) dq_timing_check(64); - always @(dq_in[65]) dq_timing_check(65); - always @(dq_in[66]) dq_timing_check(66); - always @(dq_in[67]) dq_timing_check(67); - always @(dq_in[68]) dq_timing_check(68); - always @(dq_in[69]) dq_timing_check(69); - always @(dq_in[70]) dq_timing_check(70); - always @(dq_in[71]) dq_timing_check(71); - always @(dq_in[72]) dq_timing_check(72); - always @(dq_in[73]) dq_timing_check(73); - always @(dq_in[74]) dq_timing_check(74); - always @(dq_in[75]) dq_timing_check(75); - always @(dq_in[76]) dq_timing_check(76); - always @(dq_in[77]) dq_timing_check(77); - always @(dq_in[78]) dq_timing_check(78); - always @(dq_in[79]) dq_timing_check(79); - always @(dq_in[80]) dq_timing_check(80); - always @(dq_in[81]) dq_timing_check(81); - always @(dq_in[82]) dq_timing_check(82); - always @(dq_in[83]) dq_timing_check(83); - always @(dq_in[84]) dq_timing_check(84); - always @(dq_in[85]) dq_timing_check(85); - always @(dq_in[86]) dq_timing_check(86); - always @(dq_in[87]) dq_timing_check(87); - always @(dq_in[88]) dq_timing_check(88); - always @(dq_in[89]) dq_timing_check(89); - always @(dq_in[90]) dq_timing_check(90); - always @(dq_in[91]) dq_timing_check(91); - always @(dq_in[92]) dq_timing_check(92); - always @(dq_in[93]) dq_timing_check(93); - always @(dq_in[94]) dq_timing_check(94); - always @(dq_in[95]) dq_timing_check(95); - always @(dq_in[96]) dq_timing_check(96); - always @(dq_in[97]) dq_timing_check(97); - always @(dq_in[98]) dq_timing_check(98); - always @(dq_in[99]) dq_timing_check(99); - always @(dq_in[100]) dq_timing_check(100); - always @(dq_in[101]) dq_timing_check(101); - always @(dq_in[102]) dq_timing_check(102); - always @(dq_in[103]) dq_timing_check(103); - always @(dq_in[104]) dq_timing_check(104); - always @(dq_in[105]) dq_timing_check(105); - always @(dq_in[106]) dq_timing_check(106); - always @(dq_in[107]) dq_timing_check(107); - always @(dq_in[108]) dq_timing_check(108); - always @(dq_in[109]) dq_timing_check(109); - always @(dq_in[110]) dq_timing_check(110); - always @(dq_in[111]) dq_timing_check(111); - always @(dq_in[112]) dq_timing_check(112); - always @(dq_in[113]) dq_timing_check(113); - always @(dq_in[114]) dq_timing_check(114); - always @(dq_in[115]) dq_timing_check(115); - always @(dq_in[116]) dq_timing_check(116); - always @(dq_in[117]) dq_timing_check(117); - always @(dq_in[118]) dq_timing_check(118); - always @(dq_in[119]) dq_timing_check(119); - always @(dq_in[120]) dq_timing_check(120); - always @(dq_in[121]) dq_timing_check(121); - always @(dq_in[122]) dq_timing_check(122); - always @(dq_in[123]) dq_timing_check(123); - always @(dq_in[124]) dq_timing_check(124); - always @(dq_in[125]) dq_timing_check(125); - always @(dq_in[126]) dq_timing_check(126); - always @(dq_in[127]) dq_timing_check(127); - - task dqs_pos_timing_check; - input i; - reg [5:0] i; - reg [4:0] j; - begin - if (write_levelization && i<32) begin - if (ck_cntr - ck_load_mode < TWLMRD) - $display ("%m: at time %t ERROR: tWLMRD violation on DQS bit %d positive edge.", $time, i); - if (($time - tm_ck_pos < TWLS) || ($time - tm_ck_neg < TWLS)) - $display ("%m: at time %t WARNING: tWLS violation on DQS bit %d positive edge. Indeterminate CK capture is possible.", $time, i); - if (DEBUG) - $display ("%m: at time %t Write Leveling @ DQS ck = %b", $time, diff_ck); - dq_out_en_dly[i*`DQ_PER_DQS] <= #(TWLO) 1'b1; - dq_out_dly[i*`DQ_PER_DQS] <= #(TWLO) diff_ck; -`ifdef WL_ALLDQ - for (j=1; j<`DQ_PER_DQS; j=j+1) begin - dq_out_en_dly[i*`DQ_PER_DQS+j] <= #(TWLO) 1'b1; - dq_out_dly[i*`DQ_PER_DQS+j] <= #(TWLO) diff_ck; - end -`else - for (j=1; j<`DQ_PER_DQS; j=j+1) begin - dq_out_en_dly[i*`DQ_PER_DQS+j] <= #(TWLO + TWLOE) 1'b1; - dq_out_dly[i*`DQ_PER_DQS+j] <= #(TWLO + TWLOE) 1'b0; - end -`endif - end - if (dqs_in_valid && ((wdqs_pos_cntr[i] < wr_burst_length/2) || b2b_write)) begin - if (dqs_in[i] ^ prev_dqs_in[i]) begin - if (dll_locked) begin - if (check_write_preamble[i]) begin - if ($time - tm_dqs_pos[i] < $rtoi(TWPRE*tck_avg)) - $display ("%m: at time %t ERROR: tWPRE violation on %s bit %d", $time, dqs_string[i/32], i%32); - end else if (check_write_postamble[i]) begin - if ($time - tm_dqs_neg[i] < $rtoi(TWPST*tck_avg)) - $display ("%m: at time %t ERROR: tWPST violation on %s bit %d", $time, dqs_string[i/32], i%32); - end else begin - if ($time - tm_dqs_neg[i] < $rtoi(TDQSL*tck_avg)) - $display ("%m: at time %t ERROR: tDQSL violation on %s bit %d", $time, dqs_string[i/32], i%32); - end - end - if ($time - tm_dm[i%32] < TDS) - $display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%32] + TDS - $time); - if (!dq_out_en) begin - for (j=0; j<`DQ_PER_DQS; j=j+1) begin - if ($time - tm_dq[(i%32)*`DQ_PER_DQS+j] < TDS) - $display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[(i%32)*`DQ_PER_DQS+j] + TDS - $time); - check_dq_tdipw[(i%32)*`DQ_PER_DQS+j] <= 1'b1; - end - end - if ((wdqs_pos_cntr[i] < wr_burst_length/2) && !b2b_write) begin - wdqs_pos_cntr[i] <= wdqs_pos_cntr[i] + 1; - end else begin - wdqs_pos_cntr[i] <= 1; - end - check_dm_tdipw[i%32] <= 1'b1; - check_write_preamble[i] <= 1'b0; - check_write_postamble[i] <= 1'b0; - check_write_dqs_low[i] <= 1'b0; - tm_dqs[i%32] <= $time; - end else begin - $display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/32], i%32); - end - end - tm_dqss_pos[i] <= $time; - tm_dqs_pos[i] = $time; - prev_dqs_in[i] <= dqs_in[i]; - end - endtask - - always @(posedge dqs_in[ 0]) if ( dqs_in[ 0]) dqs_pos_timing_check( 0); - always @(posedge dqs_in[ 1]) if ( dqs_in[ 1]) dqs_pos_timing_check( 1); - always @(posedge dqs_in[ 2]) if ( dqs_in[ 2]) dqs_pos_timing_check( 2); - always @(posedge dqs_in[ 3]) if ( dqs_in[ 3]) dqs_pos_timing_check( 3); - always @(posedge dqs_in[ 4]) if ( dqs_in[ 4]) dqs_pos_timing_check( 4); - always @(posedge dqs_in[ 5]) if ( dqs_in[ 5]) dqs_pos_timing_check( 5); - always @(posedge dqs_in[ 6]) if ( dqs_in[ 6]) dqs_pos_timing_check( 6); - always @(posedge dqs_in[ 7]) if ( dqs_in[ 7]) dqs_pos_timing_check( 7); - always @(posedge dqs_in[ 8]) if ( dqs_in[ 8]) dqs_pos_timing_check( 8); - always @(posedge dqs_in[ 9]) if ( dqs_in[ 9]) dqs_pos_timing_check( 9); - always @(posedge dqs_in[10]) if ( dqs_in[10]) dqs_pos_timing_check(10); - always @(posedge dqs_in[11]) if ( dqs_in[11]) dqs_pos_timing_check(11); - always @(posedge dqs_in[12]) if ( dqs_in[12]) dqs_pos_timing_check(12); - always @(posedge dqs_in[13]) if ( dqs_in[13]) dqs_pos_timing_check(13); - always @(posedge dqs_in[14]) if ( dqs_in[14]) dqs_pos_timing_check(14); - always @(posedge dqs_in[15]) if ( dqs_in[15]) dqs_pos_timing_check(15); - always @(posedge dqs_in[16]) if ( dqs_in[16]) dqs_pos_timing_check(16); - always @(posedge dqs_in[17]) if ( dqs_in[17]) dqs_pos_timing_check(17); - always @(posedge dqs_in[18]) if ( dqs_in[18]) dqs_pos_timing_check(18); - always @(posedge dqs_in[19]) if ( dqs_in[19]) dqs_pos_timing_check(19); - always @(posedge dqs_in[20]) if ( dqs_in[20]) dqs_pos_timing_check(20); - always @(posedge dqs_in[21]) if ( dqs_in[21]) dqs_pos_timing_check(21); - always @(posedge dqs_in[22]) if ( dqs_in[22]) dqs_pos_timing_check(22); - always @(posedge dqs_in[23]) if ( dqs_in[23]) dqs_pos_timing_check(23); - always @(posedge dqs_in[24]) if ( dqs_in[24]) dqs_pos_timing_check(24); - always @(posedge dqs_in[25]) if ( dqs_in[25]) dqs_pos_timing_check(25); - always @(posedge dqs_in[26]) if ( dqs_in[26]) dqs_pos_timing_check(26); - always @(posedge dqs_in[27]) if ( dqs_in[27]) dqs_pos_timing_check(27); - always @(posedge dqs_in[28]) if ( dqs_in[28]) dqs_pos_timing_check(28); - always @(posedge dqs_in[29]) if ( dqs_in[29]) dqs_pos_timing_check(29); - always @(posedge dqs_in[30]) if ( dqs_in[30]) dqs_pos_timing_check(30); - always @(posedge dqs_in[31]) if ( dqs_in[31]) dqs_pos_timing_check(31); - - always @(negedge dqs_in[32]) if (!dqs_in[32]) dqs_pos_timing_check(32); - always @(negedge dqs_in[33]) if (!dqs_in[33]) dqs_pos_timing_check(33); - always @(negedge dqs_in[34]) if (!dqs_in[34]) dqs_pos_timing_check(34); - always @(negedge dqs_in[35]) if (!dqs_in[35]) dqs_pos_timing_check(35); - always @(negedge dqs_in[36]) if (!dqs_in[36]) dqs_pos_timing_check(36); - always @(negedge dqs_in[37]) if (!dqs_in[37]) dqs_pos_timing_check(37); - always @(negedge dqs_in[38]) if (!dqs_in[38]) dqs_pos_timing_check(38); - always @(negedge dqs_in[39]) if (!dqs_in[39]) dqs_pos_timing_check(39); - always @(negedge dqs_in[40]) if (!dqs_in[40]) dqs_pos_timing_check(40); - always @(negedge dqs_in[41]) if (!dqs_in[41]) dqs_pos_timing_check(41); - always @(negedge dqs_in[42]) if (!dqs_in[42]) dqs_pos_timing_check(42); - always @(negedge dqs_in[43]) if (!dqs_in[43]) dqs_pos_timing_check(43); - always @(negedge dqs_in[44]) if (!dqs_in[44]) dqs_pos_timing_check(44); - always @(negedge dqs_in[45]) if (!dqs_in[45]) dqs_pos_timing_check(45); - always @(negedge dqs_in[46]) if (!dqs_in[46]) dqs_pos_timing_check(46); - always @(negedge dqs_in[47]) if (!dqs_in[47]) dqs_pos_timing_check(47); - always @(negedge dqs_in[48]) if (!dqs_in[48]) dqs_pos_timing_check(48); - always @(negedge dqs_in[49]) if (!dqs_in[49]) dqs_pos_timing_check(49); - always @(negedge dqs_in[50]) if (!dqs_in[50]) dqs_pos_timing_check(50); - always @(negedge dqs_in[51]) if (!dqs_in[51]) dqs_pos_timing_check(51); - always @(negedge dqs_in[52]) if (!dqs_in[52]) dqs_pos_timing_check(52); - always @(negedge dqs_in[53]) if (!dqs_in[53]) dqs_pos_timing_check(53); - always @(negedge dqs_in[54]) if (!dqs_in[54]) dqs_pos_timing_check(54); - always @(negedge dqs_in[55]) if (!dqs_in[55]) dqs_pos_timing_check(55); - always @(negedge dqs_in[56]) if (!dqs_in[56]) dqs_pos_timing_check(56); - always @(negedge dqs_in[57]) if (!dqs_in[57]) dqs_pos_timing_check(57); - always @(negedge dqs_in[58]) if (!dqs_in[58]) dqs_pos_timing_check(58); - always @(negedge dqs_in[59]) if (!dqs_in[59]) dqs_pos_timing_check(59); - always @(negedge dqs_in[60]) if (!dqs_in[60]) dqs_pos_timing_check(60); - always @(negedge dqs_in[61]) if (!dqs_in[61]) dqs_pos_timing_check(61); - always @(negedge dqs_in[62]) if (!dqs_in[62]) dqs_pos_timing_check(62); - always @(negedge dqs_in[63]) if (!dqs_in[63]) dqs_pos_timing_check(63); - - task dqs_neg_timing_check; - input i; - reg [5:0] i; - reg [4:0] j; - begin - if (write_levelization && i<32) begin - if (ck_cntr - ck_load_mode < TWLDQSEN) - $display ("%m: at time %t ERROR: tWLDQSEN violation on DQS bit %d.", $time, i); - if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg)) - $display ("%m: at time %t ERROR: tDQSH violation on DQS bit %d by %t", $time, i, tm_dqs_pos[i] + TDQSH*tck_avg - $time); - end - if (dqs_in_valid && (wdqs_pos_cntr[i] > 0) && check_write_dqs_high[i]) begin - if (dqs_in[i] ^ prev_dqs_in[i]) begin - if (dll_locked) begin - if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg)) - $display ("%m: at time %t ERROR: tDQSH violation on %s bit %d", $time, dqs_string[i/32], i%32); - if ($time - tm_ck_pos < $rtoi(TDSH*tck_avg)) - $display ("%m: at time %t ERROR: tDSH violation on %s bit %d", $time, dqs_string[i/32], i%32); - end - if ($time - tm_dm[i%32] < TDS) - $display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%32] + TDS - $time); - if (!dq_out_en) begin - for (j=0; j<`DQ_PER_DQS; j=j+1) begin - if ($time - tm_dq[(i%32)*`DQ_PER_DQS+j] < TDS) - $display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[(i%32)*`DQ_PER_DQS+j] + TDS - $time); - check_dq_tdipw[(i%32)*`DQ_PER_DQS+j] <= 1'b1; - end - end - check_dm_tdipw[i%32] <= 1'b1; - tm_dqs[i%32] <= $time; - end else begin - $display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/32], i%32); - end - end - check_write_dqs_high[i] <= 1'b0; - tm_dqs_neg[i] = $time; - prev_dqs_in[i] <= dqs_in[i]; - end - endtask - - always @(negedge dqs_in[ 0]) if (!dqs_in[ 0]) dqs_neg_timing_check( 0); - always @(negedge dqs_in[ 1]) if (!dqs_in[ 1]) dqs_neg_timing_check( 1); - always @(negedge dqs_in[ 2]) if (!dqs_in[ 2]) dqs_neg_timing_check( 2); - always @(negedge dqs_in[ 3]) if (!dqs_in[ 3]) dqs_neg_timing_check( 3); - always @(negedge dqs_in[ 4]) if (!dqs_in[ 4]) dqs_neg_timing_check( 4); - always @(negedge dqs_in[ 5]) if (!dqs_in[ 5]) dqs_neg_timing_check( 5); - always @(negedge dqs_in[ 6]) if (!dqs_in[ 6]) dqs_neg_timing_check( 6); - always @(negedge dqs_in[ 7]) if (!dqs_in[ 7]) dqs_neg_timing_check( 7); - always @(negedge dqs_in[ 8]) if (!dqs_in[ 8]) dqs_neg_timing_check( 8); - always @(negedge dqs_in[ 9]) if (!dqs_in[ 9]) dqs_neg_timing_check( 9); - always @(negedge dqs_in[10]) if (!dqs_in[10]) dqs_neg_timing_check(10); - always @(negedge dqs_in[11]) if (!dqs_in[11]) dqs_neg_timing_check(11); - always @(negedge dqs_in[12]) if (!dqs_in[12]) dqs_neg_timing_check(12); - always @(negedge dqs_in[13]) if (!dqs_in[13]) dqs_neg_timing_check(13); - always @(negedge dqs_in[14]) if (!dqs_in[14]) dqs_neg_timing_check(14); - always @(negedge dqs_in[15]) if (!dqs_in[15]) dqs_neg_timing_check(15); - always @(negedge dqs_in[16]) if (!dqs_in[16]) dqs_neg_timing_check(16); - always @(negedge dqs_in[17]) if (!dqs_in[17]) dqs_neg_timing_check(17); - always @(negedge dqs_in[18]) if (!dqs_in[18]) dqs_neg_timing_check(18); - always @(negedge dqs_in[19]) if (!dqs_in[19]) dqs_neg_timing_check(19); - always @(negedge dqs_in[20]) if (!dqs_in[20]) dqs_neg_timing_check(20); - always @(negedge dqs_in[21]) if (!dqs_in[21]) dqs_neg_timing_check(21); - always @(negedge dqs_in[22]) if (!dqs_in[22]) dqs_neg_timing_check(22); - always @(negedge dqs_in[23]) if (!dqs_in[23]) dqs_neg_timing_check(23); - always @(negedge dqs_in[24]) if (!dqs_in[24]) dqs_neg_timing_check(24); - always @(negedge dqs_in[25]) if (!dqs_in[25]) dqs_neg_timing_check(25); - always @(negedge dqs_in[26]) if (!dqs_in[26]) dqs_neg_timing_check(26); - always @(negedge dqs_in[27]) if (!dqs_in[27]) dqs_neg_timing_check(27); - always @(negedge dqs_in[28]) if (!dqs_in[28]) dqs_neg_timing_check(28); - always @(negedge dqs_in[29]) if (!dqs_in[29]) dqs_neg_timing_check(29); - always @(negedge dqs_in[30]) if (!dqs_in[30]) dqs_neg_timing_check(30); - always @(negedge dqs_in[31]) if (!dqs_in[31]) dqs_neg_timing_check(31); - - always @(posedge dqs_in[32]) if ( dqs_in[32]) dqs_neg_timing_check(32); - always @(posedge dqs_in[33]) if ( dqs_in[33]) dqs_neg_timing_check(33); - always @(posedge dqs_in[34]) if ( dqs_in[34]) dqs_neg_timing_check(34); - always @(posedge dqs_in[35]) if ( dqs_in[35]) dqs_neg_timing_check(35); - always @(posedge dqs_in[36]) if ( dqs_in[36]) dqs_neg_timing_check(36); - always @(posedge dqs_in[37]) if ( dqs_in[37]) dqs_neg_timing_check(37); - always @(posedge dqs_in[38]) if ( dqs_in[38]) dqs_neg_timing_check(38); - always @(posedge dqs_in[39]) if ( dqs_in[39]) dqs_neg_timing_check(39); - always @(posedge dqs_in[40]) if ( dqs_in[40]) dqs_neg_timing_check(40); - always @(posedge dqs_in[41]) if ( dqs_in[41]) dqs_neg_timing_check(41); - always @(posedge dqs_in[42]) if ( dqs_in[42]) dqs_neg_timing_check(42); - always @(posedge dqs_in[43]) if ( dqs_in[43]) dqs_neg_timing_check(43); - always @(posedge dqs_in[44]) if ( dqs_in[44]) dqs_neg_timing_check(44); - always @(posedge dqs_in[45]) if ( dqs_in[45]) dqs_neg_timing_check(45); - always @(posedge dqs_in[46]) if ( dqs_in[46]) dqs_neg_timing_check(46); - always @(posedge dqs_in[47]) if ( dqs_in[47]) dqs_neg_timing_check(47); - always @(posedge dqs_in[48]) if ( dqs_in[48]) dqs_neg_timing_check(48); - always @(posedge dqs_in[49]) if ( dqs_in[49]) dqs_neg_timing_check(49); - always @(posedge dqs_in[50]) if ( dqs_in[50]) dqs_neg_timing_check(50); - always @(posedge dqs_in[51]) if ( dqs_in[51]) dqs_neg_timing_check(51); - always @(posedge dqs_in[52]) if ( dqs_in[52]) dqs_neg_timing_check(52); - always @(posedge dqs_in[53]) if ( dqs_in[53]) dqs_neg_timing_check(53); - always @(posedge dqs_in[54]) if ( dqs_in[54]) dqs_neg_timing_check(54); - always @(posedge dqs_in[55]) if ( dqs_in[55]) dqs_neg_timing_check(55); - always @(posedge dqs_in[56]) if ( dqs_in[56]) dqs_neg_timing_check(56); - always @(posedge dqs_in[57]) if ( dqs_in[57]) dqs_neg_timing_check(57); - always @(posedge dqs_in[58]) if ( dqs_in[58]) dqs_neg_timing_check(58); - always @(posedge dqs_in[59]) if ( dqs_in[59]) dqs_neg_timing_check(59); - always @(posedge dqs_in[60]) if ( dqs_in[60]) dqs_neg_timing_check(60); - always @(posedge dqs_in[61]) if ( dqs_in[61]) dqs_neg_timing_check(61); - always @(posedge dqs_in[62]) if ( dqs_in[62]) dqs_neg_timing_check(62); - always @(posedge dqs_in[63]) if ( dqs_in[63]) dqs_neg_timing_check(63); - -endmodule diff --git a/resources/soc/simu/testbench/ddr3_model_parameters.vh b/resources/soc/simu/testbench/ddr3_model_parameters.vh deleted file mode 100644 index 4c14495..0000000 --- a/resources/soc/simu/testbench/ddr3_model_parameters.vh +++ /dev/null @@ -1,3412 +0,0 @@ -/**************************************************************************************** -* -* Disclaimer This software code and all associated documentation, comments or other -* of Warranty: information (collectively "Software") is provided "AS IS" without -* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY -* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES -* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT -* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE -* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. -* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR -* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, -* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE -* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, -* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, -* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, -* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, -* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE -* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH -* DAMAGES. Because some jurisdictions prohibit the exclusion or -* limitation of liability for consequential or incidental damages, the -* above limitation may not apply to you. -* -* Copyright 2003 Micron Technology, Inc. All rights reserved. -* -****************************************************************************************/ - - // Parameters current with 1Gb, 2Gb, 4Gb and 8Gb datasheet - - // Timing parameters based on Speed Grade - -`ifdef x8Gb // 8Gb parameters - // SYMBOL UNITS DESCRIPTION - // ------ ----- ----------- - `ifdef sg093 // sg093 is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin - parameter TCK_MIN = 938; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 180; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 46090; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13090; // tRCD ps Active to Read/Write command time - parameter TRP = 13090; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13090; // TAA ps Internal READ command to first data - parameter CL_TIME = 13090; // CL ps Minimum CAS Latency - `elsif sg107 // sg107 is equivalent to the JEDEC DDR3-1866 (13-13-13) speed bin - parameter TCK_MIN = 1071; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47910; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13910; // tRCD ps Active to Read/Write command time - parameter TRP = 13910; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13910; // TAA ps Internal READ command to first data - parameter CL_TIME = 13910; // CL ps Minimum CAS Latency - `elsif sg125 // sg125 is equivalent to the JEDEC DDR3-1600 (11-11-11) speed bin - parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 70; // tJIT(per) ps Period JItter - parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width - parameter TIS = 170; // tIS ps Input Setup Time - parameter TIH = 120; // tIH ps Input Hold Time - parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 48750; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13750; // tRCD ps Active to Read/Write command time - parameter TRP = 13750; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 165; // tWLS ps Setup time for tDQS flop - parameter TWLH = 165; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13750; // TAA ps Internal READ command to first data - parameter CL_TIME = 13750; // CL ps Minimum CAS Latency - `elsif sg15E // sg15E is equivalent to the JEDEC DDR3-1333 (9-9-9) speed bin - parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 80; // tJIT(per) ps Period JItter - parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width - parameter TIS = 190; // tIS ps Input Setup Time - parameter TIH = 140; // tIH ps Input Hold Time - parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 49500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13500; // tRCD ps Active to Read/Write command time - parameter TRP = 13500; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 195; // tWLS ps Setup time for tDQS flop - parameter TWLH = 195; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13500; // TAA ps Internal READ command to first data - parameter CL_TIME = 13500; // CL ps Minimum CAS Latency - `else - `define sg187E // sg187E is equivalent to the JEDEC DDR3-1066 (7-7-7) speed bin - parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 90; // tJIT(per) ps Period JItter - parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width - parameter TIS = 275; // tIS ps Input Setup Time - parameter TIH = 200; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 50625; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13125; // tRCD ps Active to Read/Write command time - parameter TRP = 13125; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 245; // tWLS ps Setup time for tDQS flop - parameter TWLH = 245; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data - parameter CL_TIME = 13125; // CL ps Minimum CAS Latency - `endif - - parameter TDQSCK_DLLDIS = TDQSCK; // tDQSCK ps for DLLDIS mode, timing not guaranteed - - `ifdef x16 - `ifdef sg093 - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg107 - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg125 - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg15E - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg15 - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window - `else // sg187E, sg187, sg25, sg25E - parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window - `endif - `else // x4, x8 - `ifdef sg093 - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg107 - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg125 - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg15E - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg15 - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg187E - parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg187 - parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window - `else // sg25, sg25E - parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window - `endif - `endif - - // Timing Parameters - - // Mode Register - parameter CL_MIN = 5; // CL tCK Minimum CAS Latency - parameter CL_MAX = 14; // CL tCK Maximum CAS Latency - parameter AL_MIN = 0; // AL tCK Minimum Additive Latency - parameter AL_MAX = 2; // AL tCK Maximum Additive Latency - parameter WR_MIN = 5; // WR tCK Minimum Write Recovery - parameter WR_MAX = 16; // WR tCK Maximum Write Recovery - parameter BL_MIN = 4; // BL tCK Minimum Burst Length - parameter BL_MAX = 8; // BL tCK Minimum Burst Length - parameter CWL_MIN = 5; // CWL tCK Minimum CAS Write Latency - parameter CWL_MAX = 10; // CWL tCK Maximum CAS Write Latency - - // Clock - parameter TCK_MAX = 3300; // tCK ps Maximum Clock Cycle Time - parameter TCH_AVG_MIN = 0.47; // tCH tCK Minimum Clock High-Level Pulse Width - parameter TCL_AVG_MIN = 0.47; // tCL tCK Minimum Clock Low-Level Pulse Width - parameter TCH_AVG_MAX = 0.53; // tCH tCK Maximum Clock High-Level Pulse Width - parameter TCL_AVG_MAX = 0.53; // tCL tCK Maximum Clock Low-Level Pulse Width - parameter TCH_ABS_MIN = 0.43; // tCH tCK Minimum Clock High-Level Pulse Width - parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width - parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width - parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data - - // Data OUT - parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS# - // Data Strobe OUT - parameter TRPRE = 0.90; // tRPRE tCK DQS Read Preamble - parameter TRPST = 0.30; // tRPST tCK DQS Read Postamble - // Data Strobe IN - parameter TDQSH = 0.45; // tDQSH tCK DQS input High Pulse Width - parameter TDQSL = 0.45; // tDQSL tCK DQS input Low Pulse Width - parameter TWPRE = 0.90; // tWPRE tCK DQS Write Preamble - parameter TWPST = 0.30; // tWPST tCK DQS Write Postamble - // Command and Address - integer TZQCS; // tZQCS tCK ZQ Cal (Short) time - integer TZQINIT = max(512, ceil(640000/TCK_MIN)); // tZQinit tCK ZQ Cal (Long) time - integer TZQOPER = max(256, ceil(320000/TCK_MIN)); // tZQoper tCK ZQ Cal (Long) time - parameter TCCD = 4; // tCCD tCK Cas to Cas command delay - parameter TCCD_DG = 2; // tCCD_DG tCK Cas to Cas command delay to different group - parameter TRAS_MAX = 60e9; // tRAS ps Maximum Active to Precharge command time - parameter TWR = 15000; // tWR ps Write recovery time - parameter TMRD = 4; // tMRD tCK Load Mode Register command cycle time - parameter TMOD = 15000; // tMOD ps LOAD MODE to non-LOAD MODE command cycle time - parameter TMOD_TCK = 12; // tMOD tCK LOAD MODE to non-LOAD MODE command cycle time - parameter TRRD_TCK = 4; // tRRD tCK Active bank a to Active bank b command time - parameter TRRD_DG = 3000; // tRRD_DG ps Active bank a to Active bank b command time to different group - parameter TRRD_DG_TCK = 2; // tRRD_DG tCK Active bank a to Active bank b command time to different group - parameter TRTP = 7500; // tRTP ps Read to Precharge command delay - parameter TRTP_TCK = 4; // tRTP tCK Read to Precharge command delay - parameter TWTR = 7500; // tWTR ps Write to Read command delay - parameter TWTR_DG = 3750; // tWTR_DG ps Write to Read command delay to different group - parameter TWTR_TCK = 4; // tWTR tCK Write to Read command delay - parameter TWTR_DG_TCK = 2; // tWTR_DG tCK Write to Read command delay to different group - parameter TDLLK = 512; // tDLLK tCK DLL locking time - // Refresh - 4Gb - parameter TRFC_MIN = 260000; // tRFC ps Refresh to Refresh Command interval minimum value - parameter TRFC_MAX =70200000; // tRFC ps Refresh to Refresh Command Interval maximum value - // Power Down - parameter TXP_TCK = 3; // tXP tCK Exit power down to a valid command - parameter TXPDLL = 24000; // tXPDLL ps Exit precharge power down to READ or WRITE command (DLL-off mode) - parameter TXPDLL_TCK = 10; // tXPDLL tCK Exit precharge power down to READ or WRITE command (DLL-off mode) - parameter TACTPDEN = 1; // tACTPDEN tCK Timing of last ACT command to power down entry - parameter TPRPDEN = 1; // tPREPDEN tCK Timing of last PRE command to power down entry - parameter TREFPDEN = 1; // tARPDEN tCK Timing of last REFRESH command to power down entry - parameter TCPDED = 1; // tCPDED tCK Command pass disable/enable delay - parameter TPD_MAX =TRFC_MAX; // tPD ps Power-down entry-to-exit timing - parameter TXPR = 270000; // tXPR ps Exit Reset from CKE assertion to a valid command - parameter TXPR_TCK = 5; // tXPR tCK Exit Reset from CKE assertion to a valid command - // Self Refresh - parameter TXS = 270000; // tXS ps Exit self refesh to a non-read or write command - parameter TXS_TCK = 5; // tXS tCK Exit self refesh to a non-read or write command - parameter TXSDLL = TDLLK; // tXSRD tCK Exit self refresh to a read or write command - parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit. - parameter TCKSRE = 10000; // tCKSRE ps Valid Clock requirement after self refresh entry (SRE) - parameter TCKSRE_TCK = 5; // tCKSRE tCK Valid Clock requirement after self refresh entry (SRE) - parameter TCKSRX = 10000; // tCKSRX ps Valid Clock requirement prior to self refresh exit (SRX) - parameter TCKSRX_TCK = 5; // tCKSRX tCK Valid Clock requirement prior to self refresh exit (SRX) - parameter TCKESR_TCK = 4; // tCKESR tCK Minimum CKE low width for Self Refresh entry to exit timing - // ODT - parameter TAOF = 0.7; // tAOF tCK RTT turn-off from ODTLoff reference - parameter TAONPD = 8500; // tAONPD ps Asynchronous RTT turn-on delay (Power-Down with DLL frozen) - parameter TAOFPD = 8500; // tAONPD ps Asynchronous RTT turn-off delay (Power-Down with DLL frozen) - parameter ODTH4 = 4; // ODTH4 tCK ODT minimum HIGH time after ODT assertion or write (BL4) - parameter ODTH8 = 6; // ODTH8 tCK ODT minimum HIGH time after write (BL8) - parameter TADC = 0.7; // tADC tCK RTT dynamic change skew - // Write Levelization - parameter TWLMRD = 40; // tWLMRD tCK First DQS pulse rising edge after tDQSS margining mode is programmed - parameter TWLDQSEN = 25; // tWLDQSEN tCK DQS/DQS delay after tDQSS margining mode is programmed - parameter TWLOE = 2000; // tWLOE ps Write levelization output error - - // Size Parameters based on Part Width - - `ifdef x4 - parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 16; // MAX Address Bits - parameter ROW_BITS = 16; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 14; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used - `define CA14PLUS - `elsif x8 - parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 16; // MAX Address Bits - parameter ROW_BITS = 16; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used - `else - `define x16 - parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 16; // MAX Address Bits - parameter ROW_BITS = 16; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 2; // Set this parameter to control how many Dqs bits are used - `endif - - // Size Parameters - parameter BA_BITS = 3; // Set this parmaeter to control how many Bank Address bits are used - parameter MEM_BITS = 15; // Set this parameter to control how many write data bursts can be stored in memory. The default is 2^10=1024. - parameter AP = 10; // the address bit that controls auto-precharge and precharge-all - parameter BC = 12; // the address bit that controls burst chop - parameter BL_BITS = 3; // the number of bits required to count to BL_MAX - parameter BO_BITS = 2; // the number of Burst Order Bits - - `ifdef QUAD_RANK - parameter CS_BITS = 4; // Number of Chip Select Bits - parameter RANKS = 4; // Number of Chip Selects - `elsif DUAL_RANK - parameter CS_BITS = 2; // Number of Chip Select Bits - parameter RANKS = 2; // Number of Chip Selects - `else - parameter CS_BITS = 1; // Number of Chip Select Bits - parameter RANKS = 1; // Number of Chip Selects - `endif - - // Simulation parameters - parameter RZQ = 240; // termination resistance - parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout - parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors - parameter DEBUG = 1; // Turn on Debug messages - parameter BUS_DELAY = 0; // delay in nanoseconds - parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads - parameter RANDOM_SEED = 31913; //seed value for random generator. - - parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe - parameter RDQSEN_PST = 1; // DQS driving time after last read strobe - parameter RDQS_PRE = 2; // DQS low time prior to first read strobe - parameter RDQS_PST = 1; // DQS low time after last read strobe - parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data - parameter RDQEN_PST = 0; // DQ/DM driving time after last read data - parameter WDQS_PRE = 2; // DQS half clock periods prior to first write strobe - parameter WDQS_PST = 1; // DQS half clock periods after last write strobe - - // check for legal cas latency based on the cas write latency - function valid_cl; - input [3:0] cl; - input [3:0] cwl; - - case ({cwl, cl}) - `ifdef sg093 - {4'd5 , 4'd5 }, - {4'd5 , 4'd6 }, - {4'd6 , 4'd7 }, - {4'd6 , 4'd8 }, - {4'd7 , 4'd9 }, - {4'd7 , 4'd10}, - {4'd8 , 4'd11}, - {4'd9 , 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `elsif sg107 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd13}: valid_cl = 1; - `elsif sg125 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}: valid_cl = 1; - `elsif sg15E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}: valid_cl = 1; - `elsif sg15 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd8 }, - {4'd7, 4'd10}: valid_cl = 1; - `elsif sg187E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }: valid_cl = 1; - `elsif sg187 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd8 }: valid_cl = 1; - `endif - default : valid_cl = 0; - endcase - endfunction - - // find the minimum valid cas write latency - function [3:0] min_cwl; - input period; - real period; - min_cwl = (period >= 2500.0) ? 5: - (period >= 1875.0) ? 6: - (period >= 1500.0) ? 7: - (period >= 1250.0) ? 8: - (period >= 1071.0) ? 9: - 10; // (period >= 938) - endfunction - - // find the minimum valid cas latency - function [3:0] min_cl; - input period; - real period; - reg [3:0] cwl; - reg [3:0] cl; - begin - cwl = min_cwl(period); - for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin - if (valid_cl(cl, cwl)) begin - min_cl = cl; - end - end - end - endfunction - -`elsif x4Gb // 4Gb parameters - // SYMBOL UNITS DESCRIPTION - // ------ ----- ----------- - `ifdef sg093 // sg093 is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin - parameter TCK_MIN = 938; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 180; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 46130; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13090; // tRCD ps Active to Read/Write command time - parameter TRP = 13090; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13090; // TAA ps Internal READ command to first data - parameter CL_TIME = 13090; // CL ps Minimum CAS Latency - `elsif sg093E // sg093E is equivalent to the JEDEC DDR3-2133 (13-13-13) speed bin - parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47155; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12155; // tRCD ps Active to Read/Write command time - parameter TRP = 12155; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12155; // TAA ps Internal READ command to first data - parameter CL_TIME = 12155; // CL ps Minimum CAS Latency - `elsif sg093F // sg093F is equivalent to the JEDEC DDR3-2133 (12-12-12) speed bin - parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 46220; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 11220; // tRCD ps Active to Read/Write command time - parameter TRP = 11220; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 11220; // TAA ps Internal READ command to first data - parameter CL_TIME = 11220; // CL ps Minimum CAS Latency - `elsif sg107 // sg107 is equivalent to the JEDEC DDR3-1866 (13-13-13) speed bin - parameter TCK_MIN = 1071; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47910; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13910; // tRCD ps Active to Read/Write command time - parameter TRP = 13910; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13910; // TAA ps Internal READ command to first data - parameter CL_TIME = 13910; // CL ps Minimum CAS Latency - `elsif sg107E // sg107E is equivalent to the JEDEC DDR3-1866 (12-12-12) speed bin - parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47840; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12840; // tRCD ps Active to Read/Write command time - parameter TRP = 12840; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12840; // TAA ps Internal READ command to first data - parameter CL_TIME = 12840; // CL ps Minimum CAS Latency - `elsif sg107F // sg107F is equivalent to the JEDEC DDR3-1866 (11-11-11) speed bin - parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 46770; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 11770; // tRCD ps Active to Read/Write command time - parameter TRP = 11770; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 11770; // TAA ps Internal READ command to first data - parameter CL_TIME = 11770; // CL ps Minimum CAS Latency - `elsif sg125E // sg125E is equivalent to the JEDEC DDR3-1600 (10-10-10) speed bin - parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 70; // tJIT(per) ps Period JItter - parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width - parameter TIS = 170; // tIS ps Input Setup Time - parameter TIH = 120; // tIH ps Input Hold Time - parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12500; // tRCD ps Active to Read/Write command time - parameter TRP = 12500; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 165; // tWLS ps Setup time for tDQS flop - parameter TWLH = 165; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data - parameter CL_TIME = 12500; // CL ps Minimum CAS Latency - `elsif sg125 // sg125 is equivalent to the JEDEC DDR3-1600 (11-11-11) speed bin - parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 70; // tJIT(per) ps Period JItter - parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width - parameter TIS = 170; // tIS ps Input Setup Time - parameter TIH = 120; // tIH ps Input Hold Time - parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 48750; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13750; // tRCD ps Active to Read/Write command time - parameter TRP = 13750; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 165; // tWLS ps Setup time for tDQS flop - parameter TWLH = 165; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13750; // TAA ps Internal READ command to first data - parameter CL_TIME = 13750; // CL ps Minimum CAS Latency - `elsif sg15E // sg15E is equivalent to the JEDEC DDR3-1333H (9-9-9) speed bin - parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 80; // tJIT(per) ps Period JItter - parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width - parameter TIS = 190; // tIS ps Input Setup Time - parameter TIH = 140; // tIH ps Input Hold Time - parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 49500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13500; // tRCD ps Active to Read/Write command time - parameter TRP = 13500; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 195; // tWLS ps Setup time for tDQS flop - parameter TWLH = 195; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13500; // TAA ps Internal READ command to first data - parameter CL_TIME = 13500; // CL ps Minimum CAS Latency - `elsif sg15 // sg15 is equivalent to the JEDEC DDR3-1333J (10-10-10) speed bin - parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 80; // tJIT(per) ps Period JItter - parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width - parameter TIS = 190; // tIS ps Input Setup Time - parameter TIH = 140; // tIH ps Input Hold Time - parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 51000; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 195; // tWLS ps Setup time for tDQS flop - parameter TWLH = 195; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `elsif sg187E // sg187E is equivalent to the JEDEC DDR3-1066F (7-7-7) speed bin - parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 90; // tJIT(per) ps Period JItter - parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width - parameter TIS = 275; // tIS ps Input Setup Time - parameter TIH = 200; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 50625; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13125; // tRCD ps Active to Read/Write command time - parameter TRP = 13125; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 245; // tWLS ps Setup time for tDQS flop - parameter TWLH = 245; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data - parameter CL_TIME = 13125; // CL ps Minimum CAS Latency - `elsif sg187 // sg187 is equivalent to the JEDEC DDR3-1066G (8-8-8) speed bin - parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 90; // tJIT(per) ps Period JItter - parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width - parameter TIS = 275; // tIS ps Input Setup Time - parameter TIH = 200; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 245; // tWLS ps Setup time for tDQS flop - parameter TWLH = 245; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `elsif sg25E // sg25E is equivalent to the JEDEC DDR3-800D (5-5-5) speed bin - parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 100; // tJIT(per) ps Period JItter - parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width - parameter TIS = 350; // tIS ps Input Setup Time - parameter TIH = 275; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 50000; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12500; // tRCD ps Active to Read/Write command time - parameter TRP = 12500; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 325; // tWLS ps Setup time for tDQS flop - parameter TWLH = 325; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data - parameter CL_TIME = 12500; // CL ps Minimum CAS Latency - `else //`define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin - parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 100; // tJIT(per) ps Period JItter - parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width - parameter TIS = 350; // tIS ps Input Setup Time - parameter TIH = 275; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 325; // tWLS ps Setup time for tDQS flop - parameter TWLH = 325; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `endif - - parameter TDQSCK_DLLDIS = TDQSCK; // tDQSCK ps for DLLDIS mode, timing not guaranteed - - `ifdef x16 - `ifdef sg093 - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg093E - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg093F - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg107 - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg107E - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg107F - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg125E - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg125 - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg15E - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg15 - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window - `else // sg187E, sg187, sg25, sg25E - parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window - `endif - `else // x4, x8 - `ifdef sg093 - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg093E - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg093F - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg107 - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg107E - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg107F - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg125E - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg125 - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg15E - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg15 - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg187E - parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg187 - parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window - `else // sg25, sg25E - parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window - `endif - `endif - - // Timing Parameters - - // Mode Register - parameter CL_MIN = 5; // CL tCK Minimum CAS Latency - parameter CL_MAX = 14; // CL tCK Maximum CAS Latency - parameter AL_MIN = 0; // AL tCK Minimum Additive Latency - parameter AL_MAX = 2; // AL tCK Maximum Additive Latency - parameter WR_MIN = 5; // WR tCK Minimum Write Recovery - parameter WR_MAX = 16; // WR tCK Maximum Write Recovery - parameter BL_MIN = 4; // BL tCK Minimum Burst Length - parameter BL_MAX = 8; // BL tCK Minimum Burst Length - parameter CWL_MIN = 5; // CWL tCK Minimum CAS Write Latency - parameter CWL_MAX = 10; // CWL tCK Maximum CAS Write Latency - - // Clock - parameter TCK_MAX = 3300; // tCK ps Maximum Clock Cycle Time - parameter TCH_AVG_MIN = 0.47; // tCH tCK Minimum Clock High-Level Pulse Width - parameter TCL_AVG_MIN = 0.47; // tCL tCK Minimum Clock Low-Level Pulse Width - parameter TCH_AVG_MAX = 0.53; // tCH tCK Maximum Clock High-Level Pulse Width - parameter TCL_AVG_MAX = 0.53; // tCL tCK Maximum Clock Low-Level Pulse Width - parameter TCH_ABS_MIN = 0.43; // tCH tCK Minimum Clock High-Level Pulse Width - parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width - parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width - parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data - - // Data OUT - parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS# - // Data Strobe OUT - parameter TRPRE = 0.90; // tRPRE tCK DQS Read Preamble - parameter TRPST = 0.30; // tRPST tCK DQS Read Postamble - // Data Strobe IN - parameter TDQSH = 0.45; // tDQSH tCK DQS input High Pulse Width - parameter TDQSL = 0.45; // tDQSL tCK DQS input Low Pulse Width - parameter TWPRE = 0.90; // tWPRE tCK DQS Write Preamble - parameter TWPST = 0.30; // tWPST tCK DQS Write Postamble - // Command and Address - integer TZQCS; // tZQCS tCK ZQ Cal (Short) time - integer TZQINIT = max(512, ceil(640000/TCK_MIN)); // tZQinit tCK ZQ Cal (Long) time - integer TZQOPER = max(256, ceil(320000/TCK_MIN)); // tZQoper tCK ZQ Cal (Long) time - parameter TCCD = 4; // tCCD tCK Cas to Cas command delay - parameter TCCD_DG = 2; // tCCD_DG tCK Cas to Cas command delay to different group - parameter TRAS_MAX = 60e9; // tRAS ps Maximum Active to Precharge command time - parameter TWR = 15000; // tWR ps Write recovery time - parameter TMRD = 4; // tMRD tCK Load Mode Register command cycle time - parameter TMOD = 15000; // tMOD ps LOAD MODE to non-LOAD MODE command cycle time - parameter TMOD_TCK = 12; // tMOD tCK LOAD MODE to non-LOAD MODE command cycle time - parameter TRRD_TCK = 4; // tRRD tCK Active bank a to Active bank b command time - parameter TRRD_DG = 3000; // tRRD_DG ps Active bank a to Active bank b command time to different group - parameter TRRD_DG_TCK = 2; // tRRD_DG tCK Active bank a to Active bank b command time to different group - parameter TRTP = 7500; // tRTP ps Read to Precharge command delay - parameter TRTP_TCK = 4; // tRTP tCK Read to Precharge command delay - parameter TWTR = 7500; // tWTR ps Write to Read command delay - parameter TWTR_DG = 3750; // tWTR_DG ps Write to Read command delay to different group - parameter TWTR_TCK = 4; // tWTR tCK Write to Read command delay - parameter TWTR_DG_TCK = 2; // tWTR_DG tCK Write to Read command delay to different group - parameter TDLLK = 512; // tDLLK tCK DLL locking time - // Refresh - 4Gb - parameter TRFC_MIN = 260000; // tRFC ps Refresh to Refresh Command interval minimum value - parameter TRFC_MAX =70200000; // tRFC ps Refresh to Refresh Command Interval maximum value - // Power Down - parameter TXP_TCK = 3; // tXP tCK Exit power down to a valid command - parameter TXPDLL = 24000; // tXPDLL ps Exit precharge power down to READ or WRITE command (DLL-off mode) - parameter TXPDLL_TCK = 10; // tXPDLL tCK Exit precharge power down to READ or WRITE command (DLL-off mode) - parameter TACTPDEN = 1; // tACTPDEN tCK Timing of last ACT command to power down entry - parameter TPRPDEN = 1; // tPREPDEN tCK Timing of last PRE command to power down entry - parameter TREFPDEN = 1; // tARPDEN tCK Timing of last REFRESH command to power down entry - parameter TCPDED = 1; // tCPDED tCK Command pass disable/enable delay - parameter TPD_MAX =TRFC_MAX; // tPD ps Power-down entry-to-exit timing - parameter TXPR = 270000; // tXPR ps Exit Reset from CKE assertion to a valid command - parameter TXPR_TCK = 5; // tXPR tCK Exit Reset from CKE assertion to a valid command - // Self Refresh - parameter TXS = 270000; // tXS ps Exit self refesh to a non-read or write command - parameter TXS_TCK = 5; // tXS tCK Exit self refesh to a non-read or write command - parameter TXSDLL = TDLLK; // tXSRD tCK Exit self refresh to a read or write command - parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit. - parameter TCKSRE = 10000; // tCKSRE ps Valid Clock requirement after self refresh entry (SRE) - parameter TCKSRE_TCK = 5; // tCKSRE tCK Valid Clock requirement after self refresh entry (SRE) - parameter TCKSRX = 10000; // tCKSRX ps Valid Clock requirement prior to self refresh exit (SRX) - parameter TCKSRX_TCK = 5; // tCKSRX tCK Valid Clock requirement prior to self refresh exit (SRX) - parameter TCKESR_TCK = 4; // tCKESR tCK Minimum CKE low width for Self Refresh entry to exit timing - // ODT - parameter TAOF = 0.7; // tAOF tCK RTT turn-off from ODTLoff reference - parameter TAONPD = 8500; // tAONPD ps Asynchronous RTT turn-on delay (Power-Down with DLL frozen) - parameter TAOFPD = 8500; // tAONPD ps Asynchronous RTT turn-off delay (Power-Down with DLL frozen) - parameter ODTH4 = 4; // ODTH4 tCK ODT minimum HIGH time after ODT assertion or write (BL4) - parameter ODTH8 = 6; // ODTH8 tCK ODT minimum HIGH time after write (BL8) - parameter TADC = 0.7; // tADC tCK RTT dynamic change skew - // Write Levelization - parameter TWLMRD = 40; // tWLMRD tCK First DQS pulse rising edge after tDQSS margining mode is programmed - parameter TWLDQSEN = 25; // tWLDQSEN tCK DQS/DQS delay after tDQSS margining mode is programmed - parameter TWLOE = 2000; // tWLOE ps Write levelization output error - - // Size Parameters based on Part Width - - `ifdef x4 - parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 16; // MAX Address Bits - parameter ROW_BITS = 16; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used - `elsif x8 - parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 16; // MAX Address Bits - parameter ROW_BITS = 16; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used - `else //`define x16 - parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 15; // MAX Address Bits - parameter ROW_BITS = 15; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 2; // Set this parameter to control how many Dqs bits are used - `endif - - // Size Parameters - parameter BA_BITS = 3; // Set this parmaeter to control how many Bank Address bits are used - parameter MEM_BITS = 15; // Set this parameter to control how many write data bursts can be stored in memory. The default is 2^10=1024. - parameter AP = 10; // the address bit that controls auto-precharge and precharge-all - parameter BC = 12; // the address bit that controls burst chop - parameter BL_BITS = 3; // the number of bits required to count to BL_MAX - parameter BO_BITS = 2; // the number of Burst Order Bits - - `ifdef QUAD_RANK - parameter CS_BITS = 4; // Number of Chip Select Bits - parameter RANKS = 4; // Number of Chip Selects - `elsif DUAL_RANK - parameter CS_BITS = 2; // Number of Chip Select Bits - parameter RANKS = 2; // Number of Chip Selects - `else - parameter CS_BITS = 1; // Number of Chip Select Bits - parameter RANKS = 1; // Number of Chip Selects - `endif - - // Simulation parameters - parameter RZQ = 240; // termination resistance - parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout - parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors - parameter DEBUG = 1; // Turn on Debug messages - parameter BUS_DELAY = 0; // delay in nanoseconds - parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads - parameter RANDOM_SEED = 31913; //seed value for random generator. - - parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe - parameter RDQSEN_PST = 1; // DQS driving time after last read strobe - parameter RDQS_PRE = 2; // DQS low time prior to first read strobe - parameter RDQS_PST = 1; // DQS low time after last read strobe - parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data - parameter RDQEN_PST = 0; // DQ/DM driving time after last read data - parameter WDQS_PRE = 2; // DQS half clock periods prior to first write strobe - parameter WDQS_PST = 1; // DQS half clock periods after last write strobe - - // check for legal cas latency based on the cas write latency - function valid_cl; - input [3:0] cl; - input [3:0] cwl; - - case ({cwl, cl}) - `ifdef sg093 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `elsif sg093E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}, - {4'd10, 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `elsif sg093F - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd9 }, - {4'd8, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}, - {4'd10, 4'd12}, - {4'd10, 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `elsif sg107 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd13}: valid_cl = 1; - `elsif sg107E - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}: valid_cl = 1; - `elsif sg107F - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}: valid_cl = 1; - `elsif sg125E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}: valid_cl = 1; - `elsif sg125 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}: valid_cl = 1; - `elsif sg15E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}: valid_cl = 1; - `elsif sg15 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd8 }, - {4'd7, 4'd10}: valid_cl = 1; - `elsif sg187E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }: valid_cl = 1; - `elsif sg187 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd8 }: valid_cl = 1; - `elsif sg25E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }: valid_cl = 1; - `elsif sg25 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }: valid_cl = 1; - `endif - default : valid_cl = 0; - endcase - endfunction - - // find the minimum valid cas write latency - function [3:0] min_cwl; - input period; - real period; - min_cwl = (period >= 2500.0) ? 5: - (period >= 1875.0) ? 6: - (period >= 1500.0) ? 7: - (period >= 1250.0) ? 8: - (period >= 1071.0) ? 9: - 10; // (period >= 938) - endfunction - - // find the minimum valid cas latency - function [3:0] min_cl; - input period; - real period; - reg [3:0] cwl; - reg [3:0] cl; - begin - cwl = min_cwl(period); - for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin - if (valid_cl(cl, cwl)) begin - min_cl = cl; - end - end - end - endfunction - -`elsif x2Gb // 2Gb parameters - - // SYMBOL UNITS DESCRIPTION - // ------ ----- ----------- - `ifdef sg093 // sg093 is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin - parameter TCK_MIN = 938; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 180; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 46130; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13090; // tRCD ps Active to Read/Write command time - parameter TRP = 13090; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13090; // TAA ps Internal READ command to first data - parameter CL_TIME = 13090; // CL ps Minimum CAS Latency - `elsif sg093E // sg093E is equivalent to the JEDEC DDR3-2133 (13-13-13) speed bin - parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47155; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12155; // tRCD ps Active to Read/Write command time - parameter TRP = 12155; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12155; // TAA ps Internal READ command to first data - parameter CL_TIME = 12155; // CL ps Minimum CAS Latency - `elsif sg093F // sg093F is equivalent to the JEDEC DDR3-2133 (12-12-12) speed bin - parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 46220; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 11220; // tRCD ps Active to Read/Write command time - parameter TRP = 11220; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 11220; // TAA ps Internal READ command to first data - parameter CL_TIME = 11220; // CL ps Minimum CAS Latency - `elsif sg107 // sg107 is equivalent to the JEDEC DDR3-1866 (13-13-13) speed bin - parameter TCK_MIN = 1071; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 48910; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13910; // tRCD ps Active to Read/Write command time - parameter TRP = 13910; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13910; // TAA ps Internal READ command to first data - parameter CL_TIME = 13910; // CL ps Minimum CAS Latency - `elsif sg107E // sg107E is equivalent to the JEDEC DDR3-1866 (12-12-12) speed bin - parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47840; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12840; // tRCD ps Active to Read/Write command time - parameter TRP = 12840; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12840; // TAA ps Internal READ command to first data - parameter CL_TIME = 12840; // CL ps Minimum CAS Latency - `elsif sg107F // sg107F is equivalent to the JEDEC DDR3-1866 (11-11-11) speed bin - parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 46770; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 11770; // tRCD ps Active to Read/Write command time - parameter TRP = 11770; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 11770; // TAA ps Internal READ command to first data - parameter CL_TIME = 11770; // CL ps Minimum CAS Latency - `elsif sg125E // sg125E is equivalent to the JEDEC DDR3-1600 (10-10-10) speed bin - parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 70; // tJIT(per) ps Period JItter - parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width - parameter TIS = 170; // tIS ps Input Setup Time - parameter TIH = 120; // tIH ps Input Hold Time - parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12500; // tRCD ps Active to Read/Write command time - parameter TRP = 12500; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 165; // tWLS ps Setup time for tDQS flop - parameter TWLH = 165; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data - parameter CL_TIME = 12500; // CL ps Minimum CAS Latency - `elsif sg125 // sg125 is equivalent to the JEDEC DDR3-1600 (11-11-11) speed bin - parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 70; // tJIT(per) ps Period JItter - parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width - parameter TIS = 170; // tIS ps Input Setup Time - parameter TIH = 120; // tIH ps Input Hold Time - parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 48750; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13750; // tRCD ps Active to Read/Write command time - parameter TRP = 13750; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 165; // tWLS ps Setup time for tDQS flop - parameter TWLH = 165; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13750; // TAA ps Internal READ command to first data - parameter CL_TIME = 13750; // CL ps Minimum CAS Latency - `elsif sg15E // sg15E is equivalent to the JEDEC DDR3-1333H (9-9-9) speed bin - parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 80; // tJIT(per) ps Period JItter - parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width - parameter TIS = 190; // tIS ps Input Setup Time - parameter TIH = 140; // tIH ps Input Hold Time - parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 49500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13500; // tRCD ps Active to Read/Write command time - parameter TRP = 13500; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 195; // tWLS ps Setup time for tDQS flop - parameter TWLH = 195; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13500; // TAA ps Internal READ command to first data - parameter CL_TIME = 13500; // CL ps Minimum CAS Latency - `elsif sg15 // sg15 is equivalent to the JEDEC DDR3-1333J (10-10-10) speed bin - parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 80; // tJIT(per) ps Period JItter - parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width - parameter TIS = 190; // tIS ps Input Setup Time - parameter TIH = 140; // tIH ps Input Hold Time - parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 51000; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 195; // tWLS ps Setup time for tDQS flop - parameter TWLH = 195; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `elsif sg187E // sg187E is equivalent to the JEDEC DDR3-1066F (7-7-7) speed bin - parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 90; // tJIT(per) ps Period JItter - parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width - parameter TIS = 275; // tIS ps Input Setup Time - parameter TIH = 200; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 50625; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13125; // tRCD ps Active to Read/Write command time - parameter TRP = 13125; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 245; // tWLS ps Setup time for tDQS flop - parameter TWLH = 245; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data - parameter CL_TIME = 13125; // CL ps Minimum CAS Latency - `elsif sg187 // sg187 is equivalent to the JEDEC DDR3-1066G (8-8-8) speed bin - parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 90; // tJIT(per) ps Period JItter - parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width - parameter TIS = 275; // tIS ps Input Setup Time - parameter TIH = 200; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 245; // tWLS ps Setup time for tDQS flop - parameter TWLH = 245; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `elsif sg25E // sg25E is equivalent to the JEDEC DDR3-800D (5-5-5) speed bin - parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 100; // tJIT(per) ps Period JItter - parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width - parameter TIS = 350; // tIS ps Input Setup Time - parameter TIH = 275; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 50000; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12500; // tRCD ps Active to Read/Write command time - parameter TRP = 12500; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 325; // tWLS ps Setup time for tDQS flop - parameter TWLH = 325; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data - parameter CL_TIME = 12500; // CL ps Minimum CAS Latency - `else //`define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin - parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 100; // tJIT(per) ps Period JItter - parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width - parameter TIS = 350; // tIS ps Input Setup Time - parameter TIH = 275; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 325; // tWLS ps Setup time for tDQS flop - parameter TWLH = 325; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `endif - - parameter TDQSCK_DLLDIS = TDQSCK; // tDQSCK ps for DLLDIS mode, timing not guaranteed - - `ifdef x16 - `ifdef sg093 - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg093E - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg093F - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg107 - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg107E - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg107F - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg125E - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg125 - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg15E - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg15 - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window - `else // sg187E, sg187, sg25, sg25E - parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window - `endif - `else // x4, x8 - `ifdef sg093 - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg093E - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg093F - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg107 - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg107E - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg107F - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg125E - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg125 - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg15E - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg15 - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg187E - parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg187 - parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window - `else // sg25, sg25E - parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window - `endif - `endif - - // Timing Parameters - - // Mode Register - parameter CL_MIN = 5; // CL tCK Minimum CAS Latency - parameter CL_MAX = 14; // CL tCK Maximum CAS Latency - parameter AL_MIN = 0; // AL tCK Minimum Additive Latency - parameter AL_MAX = 2; // AL tCK Maximum Additive Latency - parameter WR_MIN = 5; // WR tCK Minimum Write Recovery - parameter WR_MAX = 16; // WR tCK Maximum Write Recovery - parameter BL_MIN = 4; // BL tCK Minimum Burst Length - parameter BL_MAX = 8; // BL tCK Minimum Burst Length - parameter CWL_MIN = 5; // CWL tCK Minimum CAS Write Latency - parameter CWL_MAX = 10; // CWL tCK Maximum CAS Write Latency - - // Clock - parameter TCK_MAX = 3300; // tCK ps Maximum Clock Cycle Time - parameter TCH_AVG_MIN = 0.47; // tCH tCK Minimum Clock High-Level Pulse Width - parameter TCL_AVG_MIN = 0.47; // tCL tCK Minimum Clock Low-Level Pulse Width - parameter TCH_AVG_MAX = 0.53; // tCH tCK Maximum Clock High-Level Pulse Width - parameter TCL_AVG_MAX = 0.53; // tCL tCK Maximum Clock Low-Level Pulse Width - parameter TCH_ABS_MIN = 0.43; // tCH tCK Minimum Clock High-Level Pulse Width - parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width - parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width - parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data - - // Data OUT - parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS# - // Data Strobe OUT - parameter TRPRE = 0.90; // tRPRE tCK DQS Read Preamble - parameter TRPST = 0.30; // tRPST tCK DQS Read Postamble - // Data Strobe IN - parameter TDQSH = 0.45; // tDQSH tCK DQS input High Pulse Width - parameter TDQSL = 0.45; // tDQSL tCK DQS input Low Pulse Width - parameter TWPRE = 0.90; // tWPRE tCK DQS Write Preamble - parameter TWPST = 0.30; // tWPST tCK DQS Write Postamble - // Command and Address - integer TZQCS; // tZQCS tCK ZQ Cal (Short) time - integer TZQINIT = max(512, ceil(640000/TCK_MIN)); // tZQinit tCK ZQ Cal (Long) time - integer TZQOPER = max(256, ceil(320000/TCK_MIN)); // tZQoper tCK ZQ Cal (Long) time - parameter TCCD = 4; // tCCD tCK Cas to Cas command delay - parameter TCCD_DG = 2; // tCCD_DG tCK Cas to Cas command delay to different group - parameter TRAS_MAX = 60e9; // tRAS ps Maximum Active to Precharge command time - parameter TWR = 15000; // tWR ps Write recovery time - parameter TMRD = 4; // tMRD tCK Load Mode Register command cycle time - parameter TMOD = 15000; // tMOD ps LOAD MODE to non-LOAD MODE command cycle time - parameter TMOD_TCK = 12; // tMOD tCK LOAD MODE to non-LOAD MODE command cycle time - parameter TRRD_TCK = 4; // tRRD tCK Active bank a to Active bank b command time - parameter TRRD_DG = 3000; // tRRD_DG ps Active bank a to Active bank b command time to different group - parameter TRRD_DG_TCK = 2; // tRRD_DG tCK Active bank a to Active bank b command time to different group - parameter TRTP = 7500; // tRTP ps Read to Precharge command delay - parameter TRTP_TCK = 4; // tRTP tCK Read to Precharge command delay - parameter TWTR = 7500; // tWTR ps Write to Read command delay - parameter TWTR_DG = 3750; // tWTR_DG ps Write to Read command delay to different group - parameter TWTR_TCK = 4; // tWTR tCK Write to Read command delay - parameter TWTR_DG_TCK = 2; // tWTR_DG tCK Write to Read command delay to different group - parameter TDLLK = 512; // tDLLK tCK DLL locking time - // Refresh - 2Gb - parameter TRFC_MIN = 160000; // tRFC ps Refresh to Refresh Command interval minimum value - parameter TRFC_MAX =70200000; // tRFC ps Refresh to Refresh Command Interval maximum value - // Power Down - parameter TXP_TCK = 3; // tXP tCK Exit power down to a valid command - parameter TXPDLL = 24000; // tXPDLL ps Exit precharge power down to READ or WRITE command (DLL-off mode) - parameter TXPDLL_TCK = 10; // tXPDLL tCK Exit precharge power down to READ or WRITE command (DLL-off mode) - parameter TACTPDEN = 1; // tACTPDEN tCK Timing of last ACT command to power down entry - parameter TPRPDEN = 1; // tPREPDEN tCK Timing of last PRE command to power down entry - parameter TREFPDEN = 1; // tARPDEN tCK Timing of last REFRESH command to power down entry - parameter TCPDED = 1; // tCPDED tCK Command pass disable/enable delay - parameter TPD_MAX =TRFC_MAX; // tPD ps Power-down entry-to-exit timing - parameter TXPR = 170000; // tXPR ps Exit Reset from CKE assertion to a valid command - parameter TXPR_TCK = 5; // tXPR tCK Exit Reset from CKE assertion to a valid command - // Self Refresh - parameter TXS = 170000; // tXS ps Exit self refesh to a non-read or write command - parameter TXS_TCK = 5; // tXS tCK Exit self refesh to a non-read or write command - parameter TXSDLL = TDLLK; // tXSRD tCK Exit self refresh to a read or write command - parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit. - parameter TCKSRE = 10000; // tCKSRE ps Valid Clock requirement after self refresh entry (SRE) - parameter TCKSRE_TCK = 5; // tCKSRE tCK Valid Clock requirement after self refresh entry (SRE) - parameter TCKSRX = 10000; // tCKSRX ps Valid Clock requirement prior to self refresh exit (SRX) - parameter TCKSRX_TCK = 5; // tCKSRX tCK Valid Clock requirement prior to self refresh exit (SRX) - parameter TCKESR_TCK = 4; // tCKESR tCK Minimum CKE low width for Self Refresh entry to exit timing - // ODT - parameter TAOF = 0.7; // tAOF tCK RTT turn-off from ODTLoff reference - parameter TAONPD = 8500; // tAONPD ps Asynchronous RTT turn-on delay (Power-Down with DLL frozen) - parameter TAOFPD = 8500; // tAONPD ps Asynchronous RTT turn-off delay (Power-Down with DLL frozen) - parameter ODTH4 = 4; // ODTH4 tCK ODT minimum HIGH time after ODT assertion or write (BL4) - parameter ODTH8 = 6; // ODTH8 tCK ODT minimum HIGH time after write (BL8) - parameter TADC = 0.7; // tADC tCK RTT dynamic change skew - // Write Levelization - parameter TWLMRD = 40; // tWLMRD tCK First DQS pulse rising edge after tDQSS margining mode is programmed - parameter TWLDQSEN = 25; // tWLDQSEN tCK DQS/DQS delay after tDQSS margining mode is programmed - parameter TWLOE = 2000; // tWLOE ps Write levelization output error - - // Size Parameters based on Part Width - - `ifdef x4 - parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 15; // MAX Address Bits - parameter ROW_BITS = 15; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used - `elsif x8 - parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 15; // MAX Address Bits - parameter ROW_BITS = 15; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used - `else //`define x16 - parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 14; // MAX Address Bits - parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 2; // Set this parameter to control how many Dqs bits are used - `endif - - // Size Parameters - parameter BA_BITS = 3; // Set this parmaeter to control how many Bank Address bits are used - parameter MEM_BITS = 15; // Set this parameter to control how many write data bursts can be stored in memory. The default is 2^10=1024. - parameter AP = 10; // the address bit that controls auto-precharge and precharge-all - parameter BC = 12; // the address bit that controls burst chop - parameter BL_BITS = 3; // the number of bits required to count to BL_MAX - parameter BO_BITS = 2; // the number of Burst Order Bits - - `ifdef QUAD_RANK - `define DUAL_RANK // also define DUAL_RANK - parameter CS_BITS = 4; // Number of Chip Select Bits - parameter RANKS = 4; // Number of Chip Selects - `elsif DUAL_RANK - parameter CS_BITS = 2; // Number of Chip Select Bits - parameter RANKS = 2; // Number of Chip Selects - `else - parameter CS_BITS = 1; // Number of Chip Select Bits - parameter RANKS = 1; // Number of Chip Selects - `endif - - // Simulation parameters - parameter RZQ = 240; // termination resistance - parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout - parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors - parameter DEBUG = 1; // Turn on Debug messages - parameter BUS_DELAY = 0; // delay in nanoseconds - parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads - parameter RANDOM_SEED = 31913; //seed value for random generator. - - parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe - parameter RDQSEN_PST = 1; // DQS driving time after last read strobe - parameter RDQS_PRE = 2; // DQS low time prior to first read strobe - parameter RDQS_PST = 1; // DQS low time after last read strobe - parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data - parameter RDQEN_PST = 0; // DQ/DM driving time after last read data - parameter WDQS_PRE = 2; // DQS half clock periods prior to first write strobe - parameter WDQS_PST = 1; // DQS half clock periods after last write strobe - - // check for legal cas latency based on the cas write latency - function valid_cl; - input [3:0] cl; - input [3:0] cwl; - - case ({cwl, cl}) - `ifdef sg093 - {4'd5 , 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `elsif sg093E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}, - {4'd10, 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `elsif sg093F - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd9 }, - {4'd8, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}, - {4'd10, 4'd12}, - {4'd10, 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `elsif sg107 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd13}: valid_cl = 1; - `elsif sg107E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}: valid_cl = 1; - `elsif sg107F - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}: valid_cl = 1; - `elsif sg125E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}: valid_cl = 1; - `elsif sg125 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}: valid_cl = 1; - `elsif sg15E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}: valid_cl = 1; - `elsif sg15 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd8 }, - {4'd7, 4'd10}: valid_cl = 1; - `elsif sg187E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }: valid_cl = 1; - `elsif sg187 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd8 }: valid_cl = 1; - `elsif sg25E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }: valid_cl = 1; - `elsif sg25 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }: valid_cl = 1; - `endif - default : valid_cl = 0; - endcase - endfunction - - // find the minimum valid cas write latency - function [3:0] min_cwl; - input period; - real period; - min_cwl = (period >= 2500.0) ? 5: - (period >= 1875.0) ? 6: - (period >= 1500.0) ? 7: - (period >= 1250.0) ? 8: - (period >= 1071.0) ? 9: - 10; // (period >= 938) - endfunction - - // find the minimum valid cas latency - function [3:0] min_cl; - input period; - real period; - reg [3:0] cwl; - reg [3:0] cl; - begin - cwl = min_cwl(period); - for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin - if (valid_cl(cl, cwl)) begin - min_cl = cl; - end - end - end - endfunction - - -`else //`define x1Gb // 1Gb parts - - // SYMBOL UNITS DESCRIPTION - // ------ ----- ----------- - `ifdef sg093 // sg093 is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin - parameter TCK_MIN = 938; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 180; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 46130; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13090; // tRCD ps Active to Read/Write command time - parameter TRP = 13090; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13090; // TAA ps Internal READ command to first data - parameter CL_TIME = 13090; // CL ps Minimum CAS Latency - `elsif sg093E // sg093E is equivalent to the JEDEC DDR3-2133 (13-13-13) speed bin - parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47155; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12155; // tRCD ps Active to Read/Write command time - parameter TRP = 12155; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12155; // TAA ps Internal READ command to first data - parameter CL_TIME = 12155; // CL ps Minimum CAS Latency - `elsif sg093F // sg093F is equivalent to the JEDEC DDR3-2133 (12-12-12) speed bin - parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 46220; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 11220; // tRCD ps Active to Read/Write command time - parameter TRP = 11220; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 11220; // TAA ps Internal READ command to first data - parameter CL_TIME = 11220; // CL ps Minimum CAS Latency - `elsif sg107 // sg107 is equivalent to the JEDEC DDR3-1866 (13-13-13) speed bin - parameter TCK_MIN = 1071; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 48910; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13910; // tRCD ps Active to Read/Write command time - parameter TRP = 13910; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13910; // TAA ps Internal READ command to first data - parameter CL_TIME = 13910; // CL ps Minimum CAS Latency - `elsif sg107E // sg107E is equivalent to the JEDEC DDR3-1866 (12-12-12) speed bin - parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47840; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12840; // tRCD ps Active to Read/Write command time - parameter TRP = 12840; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12840; // TAA ps Internal READ command to first data - parameter CL_TIME = 12840; // CL ps Minimum CAS Latency - `elsif sg107F // sg107F is equivalent to the JEDEC DDR3-1866 (11-11-11) speed bin - parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 46770; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 11770; // tRCD ps Active to Read/Write command time - parameter TRP = 11770; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 11770; // TAA ps Internal READ command to first data - parameter CL_TIME = 11770; // CL ps Minimum CAS Latency - `elsif sg125E // sg125E is equivalent to the JEDEC DDR3-1600 (10-10-10) speed bin - parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 70; // tJIT(per) ps Period JItter - parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width - parameter TIS = 170; // tIS ps Input Setup Time - parameter TIH = 120; // tIH ps Input Hold Time - parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12500; // tRCD ps Active to Read/Write command time - parameter TRP = 12500; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 165; // tWLS ps Setup time for tDQS flop - parameter TWLH = 165; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data - parameter CL_TIME = 12500; // CL ps Minimum CAS Latency - `elsif sg125 // sg125 is equivalent to the JEDEC DDR3-1600 (11-11-11) speed bin - parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 70; // tJIT(per) ps Period JItter - parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width - parameter TIS = 170; // tIS ps Input Setup Time - parameter TIH = 120; // tIH ps Input Hold Time - parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 48750; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13750; // tRCD ps Active to Read/Write command time - parameter TRP = 13750; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 165; // tWLS ps Setup time for tDQS flop - parameter TWLH = 165; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13750; // TAA ps Internal READ command to first data - parameter CL_TIME = 13750; // CL ps Minimum CAS Latency - `elsif sg15E // sg15E is equivalent to the JEDEC DDR3-1333H (9-9-9) speed bin - parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 80; // tJIT(per) ps Period JItter - parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width - parameter TIS = 190; // tIS ps Input Setup Time - parameter TIH = 140; // tIH ps Input Hold Time - parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 49500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13500; // tRCD ps Active to Read/Write command time - parameter TRP = 13500; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 195; // tWLS ps Setup time for tDQS flop - parameter TWLH = 195; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13500; // TAA ps Internal READ command to first data - parameter CL_TIME = 13500; // CL ps Minimum CAS Latency - `elsif sg15 // sg15 is equivalent to the JEDEC DDR3-1333J (10-10-10) speed bin - parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 80; // tJIT(per) ps Period JItter - parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width - parameter TIS = 190; // tIS ps Input Setup Time - parameter TIH = 140; // tIH ps Input Hold Time - parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 51000; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 195; // tWLS ps Setup time for tDQS flop - parameter TWLH = 195; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `elsif sg187E // sg187E is equivalent to the JEDEC DDR3-1066F (7-7-7) speed bin - parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 90; // tJIT(per) ps Period JItter - parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width - parameter TIS = 275; // tIS ps Input Setup Time - parameter TIH = 200; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 50625; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13125; // tRCD ps Active to Read/Write command time - parameter TRP = 13125; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 245; // tWLS ps Setup time for tDQS flop - parameter TWLH = 245; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data - parameter CL_TIME = 13125; // CL ps Minimum CAS Latency - `elsif sg187 // sg187 is equivalent to the JEDEC DDR3-1066G (8-8-8) speed bin - parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 90; // tJIT(per) ps Period JItter - parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width - parameter TIS = 275; // tIS ps Input Setup Time - parameter TIH = 200; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 245; // tWLS ps Setup time for tDQS flop - parameter TWLH = 245; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `elsif sg25E // sg25E is equivalent to the JEDEC DDR3-800E (5-5-5) speed bin - parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 100; // tJIT(per) ps Period JItter - parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width - parameter TIS = 350; // tIS ps Input Setup Time - parameter TIH = 275; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 50000; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12500; // tRCD ps Active to Read/Write command time - parameter TRP = 12500; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 325; // tWLS ps Setup time for tDQS flop - parameter TWLH = 325; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data - parameter CL_TIME = 12500; // CL ps Minimum CAS Latency - `else //`define sg25 // sg25 is equivalent to the JEDEC DDR3-800 (6-6-6) speed bin - parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 100; // tJIT(per) ps Period JItter - parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width - parameter TIS = 350; // tIS ps Input Setup Time - parameter TIH = 275; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 325; // tWLS ps Setup time for tDQS flop - parameter TWLH = 325; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `endif - - parameter TDQSCK_DLLDIS = TDQSCK; // tDQSCK ps for DLLDIS mode, timing not guaranteed - - `ifdef x16 - `ifdef sg093 - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg093E - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg093F - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg107 - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg107E - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg107F - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg125E - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg125 - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg15E - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg15 - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg187E - parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg187 - parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg25E - parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window - `else // sg25 - parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window - `endif - `else // x4, x8 - `ifdef sg093 - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg093E - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg093F - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg107 - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg107E - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg107F - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg125E - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg125 - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg15E - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg15 - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg187E - parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg187 - parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg25E - parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window - `else // sg25 - parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window - `endif - `endif - - // Timing Parameters - - // Mode Register - parameter CL_MIN = 5; // CL tCK Minimum CAS Latency - parameter CL_MAX = 14; // CL tCK Maximum CAS Latency - parameter AL_MIN = 0; // AL tCK Minimum Additive Latency - parameter AL_MAX = 2; // AL tCK Maximum Additive Latency - parameter WR_MIN = 5; // WR tCK Minimum Write Recovery - parameter WR_MAX = 16; // WR tCK Maximum Write Recovery - parameter BL_MIN = 4; // BL tCK Minimum Burst Length - parameter BL_MAX = 8; // BL tCK Minimum Burst Length - parameter CWL_MIN = 5; // CWL tCK Minimum CAS Write Latency - parameter CWL_MAX = 10; // CWL tCK Maximum CAS Write Latency - - // Clock - parameter TCK_MAX = 3300; // tCK ps Maximum Clock Cycle Time - parameter TCH_AVG_MIN = 0.47; // tCH tCK Minimum Clock High-Level Pulse Width - parameter TCL_AVG_MIN = 0.47; // tCL tCK Minimum Clock Low-Level Pulse Width - parameter TCH_AVG_MAX = 0.53; // tCH tCK Maximum Clock High-Level Pulse Width - parameter TCL_AVG_MAX = 0.53; // tCL tCK Maximum Clock Low-Level Pulse Width - parameter TCH_ABS_MIN = 0.43; // tCH tCK Minimum Clock High-Level Pulse Width - parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width - parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width - parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data - - // Data OUT - parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS# - // Data Strobe OUT - parameter TRPRE = 0.90; // tRPRE tCK DQS Read Preamble - parameter TRPST = 0.30; // tRPST tCK DQS Read Postamble - // Data Strobe IN - parameter TDQSH = 0.45; // tDQSH tCK DQS input High Pulse Width - parameter TDQSL = 0.45; // tDQSL tCK DQS input Low Pulse Width - parameter TWPRE = 0.90; // tWPRE tCK DQS Write Preamble - parameter TWPST = 0.30; // tWPST tCK DQS Write Postamble - // Command and Address - integer TZQCS; // tZQCS tCK ZQ Cal (Short) time - integer TZQINIT = max(512, ceil(640000/TCK_MIN)); // tZQinit tCK ZQ Cal (Long) time - integer TZQOPER = max(256, ceil(320000/TCK_MIN)); // tZQoper tCK ZQ Cal (Long) time - parameter TCCD = 4; // tCCD tCK Cas to Cas command delay - parameter TCCD_DG = 2; // tCCD_DG tCK Cas to Cas command delay to different group - parameter TRAS_MAX = 60e9; // tRAS ps Maximum Active to Precharge command time - parameter TWR = 15000; // tWR ps Write recovery time - parameter TMRD = 4; // tMRD tCK Load Mode Register command cycle time - parameter TMOD = 15000; // tMOD ps LOAD MODE to non-LOAD MODE command cycle time - parameter TMOD_TCK = 12; // tMOD tCK LOAD MODE to non-LOAD MODE command cycle time - parameter TRRD_TCK = 4; // tRRD tCK Active bank a to Active bank b command time - parameter TRRD_DG = 3000; // tRRD_DG ps Active bank a to Active bank b command time to different group - parameter TRRD_DG_TCK = 2; // tRRD_DG tCK Active bank a to Active bank b command time to different group - parameter TRTP = 7500; // tRTP ps Read to Precharge command delay - parameter TRTP_TCK = 4; // tRTP tCK Read to Precharge command delay - parameter TWTR = 7500; // tWTR ps Write to Read command delay - parameter TWTR_DG = 3750; // tWTR_DG ps Write to Read command delay to different group - parameter TWTR_TCK = 4; // tWTR tCK Write to Read command delay - parameter TWTR_DG_TCK = 2; // tWTR_DG tCK Write to Read command delay to different group - parameter TDLLK = 512; // tDLLK tCK DLL locking time - // Refresh - 1Gb - parameter TRFC_MIN = 110000; // tRFC ps Refresh to Refresh Command interval minimum value - parameter TRFC_MAX =70200000; // tRFC ps Refresh to Refresh Command Interval maximum value - // Power Down - parameter TXP_TCK = 3; // tXP tCK Exit power down to a valid command - parameter TXPDLL = 24000; // tXPDLL ps Exit precharge power down to READ or WRITE command (DLL-off mode) - parameter TXPDLL_TCK = 10; // tXPDLL tCK Exit precharge power down to READ or WRITE command (DLL-off mode) - parameter TACTPDEN = 1; // tACTPDEN tCK Timing of last ACT command to power down entry - parameter TPRPDEN = 1; // tPREPDEN tCK Timing of last PRE command to power down entry - parameter TREFPDEN = 1; // tARPDEN tCK Timing of last REFRESH command to power down entry - parameter TCPDED = 1; // tCPDED tCK Command pass disable/enable delay - parameter TPD_MAX =TRFC_MAX; // tPD ps Power-down entry-to-exit timing - parameter TXPR = 120000; // tXPR ps Exit Reset from CKE assertion to a valid command - parameter TXPR_TCK = 5; // tXPR tCK Exit Reset from CKE assertion to a valid command - // Self Refresh - parameter TXS = 120000; // tXS ps Exit self refesh to a non-read or write command - parameter TXS_TCK = 5; // tXS tCK Exit self refesh to a non-read or write command - parameter TXSDLL = TDLLK; // tXSRD tCK Exit self refresh to a read or write command - parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit. - parameter TCKSRE = 10000; // tCKSRE ps Valid Clock requirement after self refresh entry (SRE) - parameter TCKSRE_TCK = 5; // tCKSRE tCK Valid Clock requirement after self refresh entry (SRE) - parameter TCKSRX = 10000; // tCKSRX ps Valid Clock requirement prior to self refresh exit (SRX) - parameter TCKSRX_TCK = 5; // tCKSRX tCK Valid Clock requirement prior to self refresh exit (SRX) - parameter TCKESR_TCK = 4; // tCKESR tCK Minimum CKE low width for Self Refresh entry to exit timing - // ODT - parameter TAOF = 0.7; // tAOF tCK RTT turn-off from ODTLoff reference - parameter TAONPD = 8500; // tAONPD ps Asynchronous RTT turn-on delay (Power-Down with DLL frozen) - parameter TAOFPD = 8500; // tAONPD ps Asynchronous RTT turn-off delay (Power-Down with DLL frozen) - parameter ODTH4 = 4; // ODTH4 tCK ODT minimum HIGH time after ODT assertion or write (BL4) - parameter ODTH8 = 6; // ODTH8 tCK ODT minimum HIGH time after write (BL8) - parameter TADC = 0.7; // tADC tCK RTT dynamic change skew - // Write Levelization - parameter TWLMRD = 40; // tWLMRD tCK First DQS pulse rising edge after tDQSS margining mode is programmed - parameter TWLDQSEN = 25; // tWLDQSEN tCK DQS/DQS delay after tDQSS margining mode is programmed - parameter TWLOE = 2000; // tWLOE ps Write levelization output error - - // Size Parameters based on Part Width - - `ifdef x4 - parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 14; // MAX Address Bits - parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used - `elsif x8 - parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 14; // MAX Address Bits - parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used - `else //`define x16 - parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 13; // MAX Address Bits - parameter ROW_BITS = 13; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 2; // Set this parameter to control how many Dqs bits are used - `endif - - // Size Parameters - parameter BA_BITS = 3; // Set this parmaeter to control how many Bank Address bits are used - parameter MEM_BITS = 15; // Set this parameter to control how many write data bursts can be stored in memory. The default is 2^10=1024. - parameter AP = 10; // the address bit that controls auto-precharge and precharge-all - parameter BC = 12; // the address bit that controls burst chop - parameter BL_BITS = 3; // the number of bits required to count to BL_MAX - parameter BO_BITS = 2; // the number of Burst Order Bits - - `ifdef QUAD_RANK - `define DUAL_RANK // also define DUAL_RANK - parameter CS_BITS = 4; // Number of Chip Select Bits - parameter RANKS = 4; // Number of Chip Selects - `elsif DUAL_RANK - parameter CS_BITS = 2; // Number of Chip Select Bits - parameter RANKS = 2; // Number of Chip Selects - `else - parameter CS_BITS = 1; // Number of Chip Select Bits - parameter RANKS = 1; // Number of Chip Selects - `endif - - // Simulation parameters - parameter RZQ = 240; // termination resistance - parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout - parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors - parameter DEBUG = 1; // Turn on Debug messages - parameter BUS_DELAY = 0; // delay in nanoseconds - parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads - parameter RANDOM_SEED = 31913; //seed value for random generator. - - parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe - parameter RDQSEN_PST = 1; // DQS driving time after last read strobe - parameter RDQS_PRE = 2; // DQS low time prior to first read strobe - parameter RDQS_PST = 1; // DQS low time after last read strobe - parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data - parameter RDQEN_PST = 0; // DQ/DM driving time after last read data - parameter WDQS_PRE = 2; // DQS half clock periods prior to first write strobe - parameter WDQS_PST = 1; // DQS half clock periods after last write strobe - - // check for legal cas latency based on the cas write latency - function valid_cl; - input [3:0] cl; - input [3:0] cwl; - - case ({cwl, cl}) - `ifdef sg093 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `elsif sg093E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}, - {4'd10, 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `elsif sg093F - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd9 }, - {4'd8, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}, - {4'd10, 4'd12}, - {4'd10, 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `elsif sg107 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd13}: valid_cl = 1; - `elsif sg107E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}: valid_cl = 1; - `elsif sg107F - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}: valid_cl = 1; - `elsif sg125E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}: valid_cl = 1; - `elsif sg125 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}: valid_cl = 1; - `elsif sg15E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}: valid_cl = 1; - `elsif sg15 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd8 }, - {4'd7, 4'd10}: valid_cl = 1; - `elsif sg187E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }: valid_cl = 1; - `elsif sg187 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd8 }: valid_cl = 1; - `elsif sg25E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }: valid_cl = 1; - `elsif sg25 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }: valid_cl = 1; - `endif - default : valid_cl = 0; - endcase - endfunction - - // find the minimum valid cas write latency - function [3:0] min_cwl; - input period; - real period; - min_cwl = (period >= 2500.0) ? 5: - (period >= 1875.0) ? 6: - (period >= 1500.0) ? 7: - (period >= 1250.0) ? 8: - (period >= 1071.0) ? 9: - 10; // (period >= 938) - endfunction - - // find the minimum valid cas latency - function [3:0] min_cl; - input period; - real period; - reg [3:0] cwl; - reg [3:0] cl; - begin - cwl = min_cwl(period); - for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin - if (valid_cl(cl, cwl)) begin - min_cl = cl; - end - end - end - endfunction - -`endif diff --git a/resources/soc/simu/testbench/ejtag_virtual_host.v b/resources/soc/simu/testbench/ejtag_virtual_host.v deleted file mode 100644 index 9210479..0000000 --- a/resources/soc/simu/testbench/ejtag_virtual_host.v +++ /dev/null @@ -1,235 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -module ejtag_virtual_host ( - TCK, - TMS, - TDO, - TDI, - TRST -); - -input TDO; -output TCK, TDI, TMS, TRST; -reg [31:0] control; -reg [31:0] impcode; -reg [31:0] idcode; -reg [31:0] data; -reg [31:0] addr; -reg [31:0] pc; -reg TDI, TCK, TMS, TRST; - -reg pracc; -reg prnw; -reg [1:0] psz; -reg rocc; -reg proben; -reg probtrap; - -reg dmseg_service; //serve dmseg access, or do other test -reg service_busy; //is the host in service - -reg [31:0] memory [{19{1'b1}}:0]; -integer j; - -always #25 TCK = ~TCK; - -initial -begin - TMS = 0; - for(j=0; j<128; j=j+1) - memory[j]=32'h0; - - - dmseg_service = 1'b0; - service_busy = 1'b0; - #50 TRST = 1'b0; - TRST = 1'b0; - TCK = 1'b0; - pracc = 1'b0; - rocc = 1'b0; - #20000 TRST = 1'b1; -//rocc = 1'b1; - $display("ejtag reboot done!"); - #1000 - query_reg32(5'ha, control); - start_dmseg_service; - -// stop_dmseg_service; -// test_ejtagbrk; -// #1000 -// start_dmseg_service; -end - -initial -begin - #10000 - begin - #20000 - if(dmseg_service) - begin - service_busy = 1'b1; - query_reg32(5'h01, idcode ); - $display("Idcode:%x Version:%x PartNumber:%x ManufID:%x\n", - idcode,idcode[31:28],idcode[27:12],idcode[11:1]); - - query_reg32(5'h03, impcode); - $display("Impcode:%x EJTAGver:%x DINTsup:%x NoDMA:%x MIPS32/64:%x\n", - impcode,impcode[31:29],impcode[24],impcode[14],impcode[0]); - service_busy = 1'b0; - end - if((!service_busy)&&dmseg_service) - end_dmseg_service; - end -end - - -task start_dmseg_service; -begin - dmseg_service = 1'b1; - $display("dmseg service start!"); -end -endtask - -task end_dmseg_service; -begin - dmseg_service = 1'b0; - query_reg32(5'ha, control); - control[31] = 1'b0; - control[15] = 1'b0; - control[14] = 1'b0; - control[12] = 1'b0; - write_reg32(5'ha, control); - $display("dmseg service end!"); -end -endtask - -task query_reg32; -input [4:0] reg_inst; -output [31:0] reg_data; -reg [31:0] reg_rd_data; -integer i; -begin - TMS = 0; - repeat(2) @(negedge TCK); - TMS = 1; - repeat(2) @(negedge TCK); - TMS = 0; - repeat(2) @(negedge TCK); - // Shift the IR command to select CONTROL - TDI = reg_inst[0]; - repeat(1) @(negedge TCK); - TDI = reg_inst[1]; - repeat(1) @(negedge TCK); - TDI = reg_inst[2]; - repeat(1) @(negedge TCK); - TDI = reg_inst[3]; - repeat(1) @(negedge TCK); - TDI = reg_inst[4]; - TMS = 1; - repeat(3) @(negedge TCK); - TMS = 0; - repeat(2) @(negedge TCK); - - for(i = 0; i < 32; i = i+1) - begin - repeat(1) @(negedge TCK); - reg_data[i] = TDO; - end - - if (reg_data[18]==1'b0) - reg_rd_data[31:0] = {reg_data[31:19], 1'b1, reg_data[17:0]}; - else - reg_rd_data[31:0] = reg_data[31:0]; - - for(i = 0; i < 32; i = i+1) - begin - TDI = reg_rd_data[i]; - repeat(1) @(posedge TCK); - if(i == 30) - begin - TMS = 1; - end - end - - repeat(1) @(posedge TCK); - TMS = 0; - repeat(3) @(negedge TCK); -end -endtask - - -task write_reg32; -input [4:0] reg_inst; -input [31:0] reg_data; -integer i; -begin - TMS = 0; - repeat(2) @(negedge TCK); - TMS = 1; - repeat(2) @(negedge TCK); - TMS = 0; - repeat(2) @(negedge TCK); - // Shift the IR command to select CONTROL - TDI = reg_inst[0]; - repeat(1) @(negedge TCK); - TDI = reg_inst[1]; - repeat(1) @(negedge TCK); - TDI = reg_inst[2]; - repeat(1) @(negedge TCK); - TDI = reg_inst[3]; - repeat(1) @(negedge TCK); - TDI = reg_inst[4]; - TMS = 1; - repeat(3) @(negedge TCK); - TMS = 0; - repeat(2) @(negedge TCK); - - repeat(1) @(posedge TCK); - for(i = 0; i < 32; i = i+1) - begin - TDI = reg_data[i]; - repeat(1) @(posedge TCK); - if(i==30) - begin - TMS = 1; - end - end - - repeat(1) @(posedge TCK); - TMS = 0; - repeat(3) @(negedge TCK); -end -endtask - -endmodule diff --git a/resources/soc/simu/testbench/godson_system.v b/resources/soc/simu/testbench/godson_system.v deleted file mode 100644 index fbb249d..0000000 --- a/resources/soc/simu/testbench/godson_system.v +++ /dev/null @@ -1,310 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -`timescale 1ns/1ps - -`define APP_FLASH "../../../../../../simu/soft/func/flash.vlog" - -`define UART_CLK soc_up_top.APB_DEV.uart0.regs.enable - -module godson_system; -// ========================================================================== // -// Signal Declarations // -// ========================================================================== // -// Clocks -reg clk,resetn; -reg mac_clk; -initial begin - clk = 1'b0; - mac_clk = 1'b0; - resetn = 1'b0; - #1000; - resetn = 1'b1; -end - -always #15.15 clk = ~clk; -always #20 mac_clk = ~mac_clk; - -//------DDR3 interface------ -wire [15:0] ddr3_dq; -wire [12:0] ddr3_addr; -wire [2 :0] ddr3_ba; -wire ddr3_ras_n; -wire ddr3_cas_n; -wire ddr3_we_n; -wire ddr3_odt; -wire ddr3_reset_n; -wire ddr3_cke; -wire [1:0] ddr3_dm; -wire [1:0] ddr3_dqs_p; -wire [1:0] ddr3_dqs_n; -wire ddr3_ck_p; -wire ddr3_ck_n; - -//----mac controller------ -//I/O pad interface signals -// Tx -wire mtxclk_0; // Transmit clock (from PHY) -wire [3:0] mtxd_0; // Transmit nibble (to PHY) -wire mtxen_0; // Transmit enable (to PHY) -wire mtxerr_0; // Transmit error (to PHY) -assign mtxclk_0 = mac_clk; -// Rx -wire mrxclk_0; // Receive clock (from PHY) -wire [3:0] mrxd_0; // Receive nibble (from PHY) -wire mrxdv_0; // Receive data valid (from PHY) -wire mrxerr_0; // Receive data error (from PHY) -assign mrxclk_0 = mac_clk; -// MII Management interface -wire mdc_0; // MII Management data clock (to PHY) -wire mdio_0; // MII data inout -wire phy_rstn; - -wire [7:0] LED; -wire UART_RX, UART_TX; -wire UART_CTS, UART_RTS; -wire UART_DTR, UART_DSR; -wire UART_RI, UART_DCD; - -//nand -wire NAND_CLE ; -wire NAND_ALE ; -wire NAND_RDY ; -wire [7:0] NAND_DATA; -wire NAND_RD ; -wire NAND_CE ; //low active -wire NAND_WR ; - -wire SPI_CLK, SPI_CS, SPI_MISO, SPI_MOSI; - -wire TDI; -wire TDO; -wire TCK; -wire TRST; -wire TMS; - -soc_up_top soc_up_top ( - .clk (clk ), - .resetn (resetn ), - - .ddr3_dq (ddr3_dq ), - .ddr3_addr (ddr3_addr ), - .ddr3_ba (ddr3_ba ), - .ddr3_ras_n (ddr3_ras_n ), - .ddr3_cas_n (ddr3_cas_n ), - .ddr3_we_n (ddr3_we_n ), - .ddr3_odt (ddr3_odt ), - .ddr3_reset_n (ddr3_reset_n), - .ddr3_cke (ddr3_cke ), - .ddr3_dm (ddr3_dm ), - .ddr3_dqs_p (ddr3_dqs_p ), - .ddr3_dqs_n (ddr3_dqs_n ), - .ddr3_ck_p (ddr3_ck_p ), - .ddr3_ck_n (ddr3_ck_n ), - - //------gpio---------------- - .led (), - .led_rg0 (), - .led_rg1 (), - .num_csn (), - .num_a_g (), - .switch (8'd0), - .btn_key_col (), - .btn_key_row (4'd0), - .btn_step (2'd0), - - //------mac controller------- - // I/O pad interface signals - //TX - .mtxclk_0 (mtxclk_0 ), - .mtxen_0 (mtxen_0 ), - .mtxd_0 (mtxd_0 ), - .mtxerr_0 (mtxerr_0 ), - //RX - .mrxclk_0 (mrxclk_0 ), - .mrxdv_0 (mrxdv_0 ), - .mrxd_0 (mrxd_0 ), - .mrxerr_0 (mrxerr_0 ), - .mcoll_0 (1'b0 ), - .mcrs_0 (1'b0 ), - // MIIM - .mdc_0 (mdc_0 ), - .mdio_0 (mdio_0 ), - - .phy_rstn (phy_rstn ), - - .UART_RX(UART_RX), - .UART_TX(UART_TX), - - //NAND - .NAND_CLE (NAND_CLE ), - .NAND_ALE (NAND_ALE ), - .NAND_RDY (NAND_RDY ), - .NAND_DATA(NAND_DATA), - .NAND_RD (NAND_RD ), - .NAND_CE (NAND_CE ), //low active - .NAND_WR (NAND_WR ), - - .EJTAG_TRST(TRST), - .EJTAG_TCK(TCK), - .EJTAG_TMS(TMS), - .EJTAG_TDI(TDI), - .EJTAG_TDO(TDO), - - .SPI_CLK(SPI_CLK), - .SPI_CS(SPI_CS), - .SPI_MISO(SPI_MISO), - .SPI_MOSI(SPI_MOSI) - ); - -pullup (NAND_RDY); -//nand module -s30ml08gp00 nand_model0 -( - .IO7 (NAND_DATA[7]) , - .IO6 (NAND_DATA[6]) , - .IO5 (NAND_DATA[5]), - .IO4 (NAND_DATA[4]), - .IO3 (NAND_DATA[3]), - .IO2 (NAND_DATA[2]), - .IO1 (NAND_DATA[1]), - .IO0 (NAND_DATA[0]), - .CLE (NAND_CLE ), - .ALE (NAND_ALE ), - .CE1Neg(NAND_CE ), - .RENeg (NAND_RD ), - .WENeg (NAND_WR ), - .RY1 (NAND_RDY ), - .CE2Neg(1'b1 ), - .WPNeg (1'b1 ), - .RY2 ( ), - .FP (1'b1 ) -); - -ejtag_virtual_host ejtag - ( - .TCK (TCK ), - .TMS (TMS ), - .TDO (TDO ), - .TDI (TDI ), - .TRST(TRST) - ); - - -MX25L6405D # - ( - .Init_File(`APP_FLASH) - ) - spi_flash - ( - .SCLK (SPI_CLK ), - .CS (SPI_CS ), - .SI (SPI_MOSI), - .SO (SPI_MISO), - .WP (1'b1 ), - .HOLD (1'b1 ) - ); - -uart_dev # - ( - .uart_number (0), - .STRLEN (80) - ) - uart_dev0 - ( - .clk (`UART_CLK), - .rst_n (resetn), - .rx (UART_TX), - .tx (UART_RX) - ); - -ddr3_model u_comp_ddr3 - ( - .rst_n (ddr3_reset_n), - .ck (ddr3_ck_p), - .ck_n (ddr3_ck_n), - .cke (ddr3_cke ), - .cs_n (1'b0 ), - .ras_n (ddr3_ras_n), - .cas_n (ddr3_cas_n), - .we_n (ddr3_we_n), - .dm_tdqs (ddr3_dm), - .ba (ddr3_ba), - .addr (ddr3_addr), - .dq (ddr3_dq), - .dqs (ddr3_dqs_p), - .dqs_n (ddr3_dqs_n), - .tdqs_n (), - .odt (ddr3_odt) - ); - -virtual_mac VIRTUAL_MAC( - .hclk (clk), - .hrst_n (resetn), - .mtxclk (mrxclk_0 ), - .mtxen (mrxdv_0 ), - .mtxd (mrxd_0 ), - .mtxerr (mrxerr_0 ), - - .mrxclk (mtxclk_0 ), - .mrxdv (mtxen_0 ), - .mrxd (mtxd_0 ), - .mrxerr (mtxerr_0 ), - .mcoll (1'b0 ), - .mcrs (1'b0 ), - .mdc (), - .md_io (), - .gpio (LED[4]) -); - -`ifdef DUMPDUMP -initial -begin - $fsdbDumpfile("wave.fsdb"); - $fsdbDumpvars(0, godson_system); - #57888881 - $fsdbDumpon; - #100000000 - $fsdbDumpoff; -end -`endif - -initial begin - forever begin - #500000; - $display("\t\t@%0t: CPU commit PC is %x", $time, godson_system.soc_up_top.cpu_mid.cpu_core.commitbus0[41:10]); - end -end - - -endmodule diff --git a/resources/soc/simu/testbench/nand_sim.v b/resources/soc/simu/testbench/nand_sim.v deleted file mode 100644 index 89c9b0f..0000000 --- a/resources/soc/simu/testbench/nand_sim.v +++ /dev/null @@ -1,3680 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// File name : s30ml08gp00.v -////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2005-2006 Free Model Foundry; http://www.FreeModelFoundry.com -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License version 2 as -// published by the Free Software Foundation. -// -// MODIFICATION HISTORY: -// -// version: | author: | mod date: | changes made: -// V1.0 D.Lukovic 05 Nov 02 Initial Version -// V1.1 D.Lukovic 06 Jan 24 SPEEDSIM support implemented -// Preload performance improvment -// RY pin is open drain, now. -// -////////////////////////////////////////////////////////////////////////////// -// PART DESCRIPTION: -// -// Library: FLASH -// Technology: FLASH MEMORY -// Part: s30ml08gp00 -// -// Description: NAND interface family based on Xtreme MirrorBit technology -// Flash Memory -// -////////////////////////////////////////////////////////////////////////////// -// Known Bugs: -// -////////////////////////////////////////////////////////////////////////////// - -////////////////////////////////////////////////////////////////////////////// -// TOP MODULE DECLARATION // -////////////////////////////////////////////////////////////////////////////// - - -`timescale 1 ns/1 ns -module s30ml08gp00 - ( - IO7 , - IO6 , - IO5 , - IO4 , - IO3 , - IO2 , - IO1 , - IO0 , - - CLE , - ALE , - CE1Neg , - CE2Neg , - RENeg , - WENeg , - WPNeg , - RY1 , - RY2 , - //PRE , - FP - ); - -//////////////////////////////////////////////////////////////////////// -// Port / Part Pin Declarations -//////////////////////////////////////////////////////////////////////// - - inout IO7 ; - inout IO6 ; - inout IO5 ; - inout IO4 ; - inout IO3 ; - inout IO2 ; - inout IO1 ; - inout IO0 ; - - input CLE ; - input ALE ; - input CE1Neg ; - input CE2Neg ; - input RENeg ; - input WENeg ; - input WPNeg ; - output RY1 ; - output RY2 ; - //input PRE ; - input FP ; - -s30ml04gp00 U_FLASH1 -( - .IO7(IO7) , - .IO6(IO6) , - .IO5(IO5) , - .IO4(IO4) , - .IO3(IO3) , - .IO2(IO2) , - .IO1(IO1) , - .IO0(IO0) , - .CLE(CLE) , - .ALE(ALE) , - .CENeg(CE1Neg), - .RENeg(RENeg), - .WENeg(WENeg), - .WPNeg(WPNeg), - .RY(RY1) , - .PRE(1'b1) , - .FP(FP) - ); - -endmodule - -module s30ml04gp00 - ( - IO7 , - IO6 , - IO5 , - IO4 , - IO3 , - IO2 , - IO1 , - IO0 , - - CLE , - ALE , - CENeg , - RENeg , - WENeg , - WPNeg , - RY , - FP , - PRE - ); - -//////////////////////////////////////////////////////////////////////// -// Port / Part Pin Declarations -//////////////////////////////////////////////////////////////////////// - - inout IO7 ; - inout IO6 ; - inout IO5 ; - inout IO4 ; - inout IO3 ; - inout IO2 ; - inout IO1 ; - inout IO0 ; - - input CLE ; - input ALE ; - input CENeg ; - input RENeg ; - input WENeg ; - input WPNeg ; - input PRE ; - input FP ; - output RY ; - - parameter mem_file_name = "none"; - parameter UserPreload = 1'b0; - parameter TimingModel = "DefaultTimingModel"; - -// interconnect path delay signals - - wire IO7_ipd ; - wire IO6_ipd ; - wire IO5_ipd ; - wire IO4_ipd ; - wire IO3_ipd ; - wire IO2_ipd ; - wire IO1_ipd ; - wire IO0_ipd ; - - wire [7 : 0] A; - assign A = {IO7_ipd, - IO6_ipd, - IO5_ipd, - IO4_ipd, - IO3_ipd, - IO2_ipd, - IO1_ipd, - IO0_ipd }; - - wire [7 : 0 ] DIn; - assign DIn = { - IO7_ipd, - IO6_ipd, - IO5_ipd, - IO4_ipd, - IO3_ipd, - IO2_ipd, - IO1_ipd, - IO0_ipd }; - - wire [7 : 0 ] DOut; - assign DOut = { - IO7, - IO6, - IO5, - IO4, - IO3, - IO2, - IO1, - IO0 }; - - wire CLE_ipd ; - wire ALE_ipd ; - wire CENeg_ipd ; - wire RENeg_ipd ; - wire WENeg_ipd ; - wire WPNeg_ipd ; - wire PRE_ipd ; - wire FP_ipd ; - -// internal delays - - reg PROG_in ; - reg PROG_out ; - reg XPROG_in ; - reg XPROG_out ; - reg PRE_PROG_in ; - reg PRE_PROG_out ; - reg BERS_in ; - reg BERS_out ; - reg XBERS_in ; - reg XBERS_out ; - reg DBSY_in ; - reg DBSY_out ; - reg TR_in ; - reg TR_out ; - reg FPSTART_in ; - reg FPSTART_out ; - reg BSTATINQ_in ; - reg BSTATINQ_out ; - - reg PROG1_in ; - reg PROG1_out ; - reg PROG2_in ; - reg PROG2_out ; - reg XPROG1_in ; - reg XPROG1_out ; - reg XPROG2_in ; - reg XPROG2_out ; - reg DBSY1_in ; - reg DBSY1_out ; - - reg [7 : 0] DOut_zd; - - wire IO7_zd ; - wire IO6_zd ; - wire IO5_zd ; - wire IO4_zd ; - wire IO3_zd ; - wire IO2_zd ; - wire IO1_zd ; - wire IO0_zd ; - - assign {IO7_zd , - IO6_zd , - IO5_zd , - IO4_zd , - IO3_zd , - IO2_zd , - IO1_zd , - IO0_zd } = DOut_zd; - - reg [7 : 0] DOut_pass; - - wire IO7_pass ; - wire IO6_pass ; - wire IO5_pass ; - wire IO4_pass ; - wire IO3_pass ; - wire IO2_pass ; - wire IO1_pass ; - wire IO0_pass ; - - - assign {IO7_pass , - IO6_pass , - IO5_pass , - IO4_pass , - IO3_pass , - IO2_pass , - IO1_pass , - IO0_pass } = DOut_pass; - - reg R_zd = 1'b0; - - parameter PartID = "s30ml04gp00"; - parameter MaxData = 8'hFF; - parameter BlockNum = 1023; - parameter BlockSize = 64; // 64 page - parameter PageSize = 2111;// by mhb - parameter SegmentNum = 7; // 8 segment within page - - // If Long_Timming is set to 0 uncomment line below - - `define SPEEDSIM; - - `ifdef SM_NAND_PGNUM - parameter PageNum = `SM_NAND_PGNUM; - `else // not SM_NAND_PGNUM - parameter PageNum = 16'hFFFF; - `endif // SM_NAND_PGNUM - - // control signals - reg STAT_ACT =1'b0; - reg STAT_M_ACT =1'b0; - reg ERS_ACT =1'b0; - reg PRG_ACT =1'b0; - reg RD_ACT =1'b0; - reg FP_ACT =1'b0; - reg XTREM_ACT =1'b0; - reg XTR_MPRG =1'b0; - reg RSTSTART =1'b0; - reg RSTDONE =1'b0; - reg back_to_xtrem =1'b0; - reg PMOVE =1'b0; - // Control signals for read operation - reg PGR_ACT =1'b0; // Page read in progress - reg PGD_ACT =1'b0; // Page Duplicate - - reg statread =1'b0; - reg nostatread =1'b1; - - // powerup - reg PoweredUp =1'b0; - reg reseted =1'b0; - - reg write =1'b0; - reg read =1'b0; - - integer WER_01; - - // 8 bit Address - integer AddrCom ; - // Address within page - integer Address ; // 0 - Pagesize - // Page Number - integer PageAddr = -1; //-1 - PageNum - // Partial page number - integer PartAddr = 0; - // Block Number - integer BlockAddr = -1; //-1 - BlockNum - integer BlckDup = 0; - - //Data - integer Data ; //-1 - MaxData - - //ID control signals - integer IDAddr ; // 0 - 4 - - integer BlockPage ; // RANGE 0 TO BlockSize; - integer Pom_Address ; // RANGE 0 TO PageSize; - reg firstFlag ; - // program control signals - integer CashBuffData [0:PageSize]; //Page chache register - integer CashBuffData1 [0:PageSize]; //Page chache register - integer CWrAddr ; // Cash -1 - Pagesize +1 - integer CWrPage ; // Cash 0 - PageNum - reg [0:SegmentNum] CSegForProg; //array [0:SegmentNum] of 0/1 - reg [0:SegmentNum] CSegForProg1; //array [0:SegmentNum] of 0/1 - - integer WrBuffData[0:PageSize]; - integer WrBuffData1[0:PageSize]; - integer WrAddr ; // -1 - Pagesize +1 - integer WrPage ; // 0 - PageNum - reg [0:SegmentNum] SegForProg; //array [0:SegmentNum] of 0/1 - reg [0:SegmentNum] SegForProg1; //array [0:SegmentNum] of 0/1 - - integer PDBuffer [0:PageSize]; - integer PDBuffer1 [0:PageSize]; - - integer Page_pom; - integer cnt_addr; - - integer pom_seg ; // RANGE -1 TO SegmentNum; - integer pom_seg1 ; // RANGE -1 TO SegmentNum; - integer segment ; // RANGE -1 TO SegmentNum; - integer segment1 ; // RANGE -1 TO SegmentNum; - reg [0:(PageNum+1)*(SegmentNum+1)-1] ProgramedFlag = 0; - reg [0:BlockNum] InvBlock = 0; - reg [0:BlockNum] InvBlockPgms = 0; - reg [0:BlockNum] PreProgFlag = 0; - reg [0:BlockNum] ProgBlock = 0; - reg [0:BlockNum] BlockMod = 0; // 0 for NORMAL, 1 for XTREME - integer ssa[0:SegmentNum]; // has to be initialized - integer sea[0:SegmentNum]; // has to be initialized - - // Mem(Page)(Address) - integer Mem[0:(PageSize+1)*(PageNum+1)-1]; - - // ID Array - integer IDArray[0:4]; - - // timing check violation - reg Viol = 1'b0; - - // initial - integer i,j; - - //Bus Cycle Decode - reg[7:0] A_tmp ; - reg[7:0] D_tmp ; - - //RstTime - time duration; - - //Functional - reg[7:0] Status = 8'hC0; - reg oe = 1'b0; - integer Page ; // 0 - PageNum - integer Blck ; // 0 - BlockNum - - event oe_event; - - integer prog_time; - integer erase_time; - - reg [14*8-1:0] tmp_timing;//stores copy of TimingModel - reg [14*8-1:0] tmp1_timing;//stores copy of TimingModel - reg [7:0] tmp_char;//stores "0" or "2" character - integer found = 1'b0; - - // states - reg [5:0] current_state; - reg [5:0] next_state; - - // FSM states - parameter IDLE =6'h00; // - parameter XTREM_PREL =6'h01; // - parameter XTREM_IDLE =6'h02; // - parameter UNKNOWN =6'h03; // wrong command sequneces - parameter PREL_RD =6'h04; // - parameter RESET =6'h05; // - parameter A0_RD =6'h06; // - parameter A1_RD =6'h07; // - parameter A2_RD =6'h08; // - parameter A3_RD =6'h09; // - parameter RD_WCMD =6'h0A; // waiting for the confirm read command - parameter BUFF_TR =6'h0B; // - parameter RD =6'h0C; // - parameter CAC_PREL =6'h0D; // Coloumn address change - parameter A0_CAC =6'h0E; // - parameter A1_CAC =6'h0F; // Wait for confirm EO command - parameter ID_PREL =6'h10; // - parameter ID =6'h11; // - parameter PREL_PRG =6'h12; // - parameter PGD_PREL =6'h13; // - parameter A0_PRG =6'h14; // - parameter A1_PRG =6'h15; // - parameter A2_PRG =6'h16; // - parameter A3_PRG =6'h17; // - parameter DATA_PRG =6'h18; // - parameter PRE_PRG =6'h19; - parameter WFPD =6'h1A; // wait for program done - parameter WFPPD =6'h1B; // - parameter PGMS_CAC =6'h1C; - parameter A0_PRG_CAC =6'h1D; - parameter PGMS =6'h1E; - parameter CBSY =6'h1F; - parameter RDY_PRG =6'h20; - parameter PREL_ERS =6'h21; - parameter A1_ERS =6'h22; - parameter A2_ERS =6'h23; - parameter A3_ERS =6'h24; - parameter BERS_EXEC =6'h25; - parameter A0_PGD =6'h26; - parameter A1_PGD =6'h27; - parameter A2_PGD =6'h28; - parameter A3_PGD =6'h29; - parameter CONF_PGD =6'h30; - parameter BSTAT_INQ =6'h31; - -/////////////////////////////////////////////////////////////////////////////// -//Interconnect Path Delay Section -/////////////////////////////////////////////////////////////////////////////// - - buf (IO7_ipd , IO7 ); - buf (IO6_ipd , IO6 ); - buf (IO5_ipd , IO5 ); - buf (IO4_ipd , IO4 ); - buf (IO3_ipd , IO3 ); - buf (IO2_ipd , IO2 ); - buf (IO1_ipd , IO1 ); - buf (IO0_ipd , IO0 ); - - buf (CLE_ipd , CLE ); - buf (ALE_ipd , ALE ); - buf (CENeg_ipd , CENeg ); - buf (RENeg_ipd , RENeg ); - buf (WENeg_ipd , WENeg ); - buf (WPNeg_ipd , WPNeg ); - buf (PRE_ipd , PRE ); - buf (FP_ipd , FP ); - -/////////////////////////////////////////////////////////////////////////////// -// Propagation delay Section -/////////////////////////////////////////////////////////////////////////////// - - - nmos (IO7 , IO7_pass , 1'b1); - nmos (IO6 , IO6_pass , 1'b1); - nmos (IO5 , IO5_pass , 1'b1); - nmos (IO4 , IO4_pass , 1'b1); - nmos (IO3 , IO3_pass , 1'b1); - nmos (IO2 , IO2_pass , 1'b1); - nmos (IO1 , IO1_pass , 1'b1); - nmos (IO0 , IO0_pass , 1'b1); - - nmos (RY , 1'b0, ~R_zd); - - wire deg; - - // Needed for TimingChecks - // VHDL CheckEnable Equivalent - - wire Check_IO0_WENeg; - assign Check_IO0_WENeg = ~CENeg; - - wire Check_WENeg; - assign Check_WENeg = PoweredUp; - reg tdp_AL, tdp_CL, tdp_CE, tdp_RE; - - wire statread_cond; - wire nostatread_cond; - - assign statread_cond = statread && tdp_CE; - assign nostatread_cond = nostatread_cond && tdp_CE; - -specify - - // tipd delays: interconnect path delays , mapped to input port delays. - // In Verilog is not necessary to declare any tipd_ delay variables, - // they can be taken from SDF file - // With all the other delays real delays would be taken from SDF file - - specparam tpd_CENeg_IO0 = 1;//tcea, tchz - specparam tpd_RENeg_IO0 = 1;//trea, trhZ - specparam tpd_WENeg_RY = 1;//twb - - //tsetup values - specparam tsetup_IO0_WENeg = 1;//tds edge / - specparam tsetup_CLE_WENeg = 1;//tcls edge \ - specparam tsetup_CENeg_WENeg = 1;//tcs edge \ - specparam tsetup_ALE_WENeg = 1;//tals edge \ - specparam tsetup_WENeg_RENeg = 1;//twhr edge \ - specparam tsetup_RENeg_WENeg = 1;//twhw edge \ - specparam tsetup_WENeg_CENeg = 1;//twhc edge \ - specparam tsetup_WPNeg_WENeg = 1;//tww edge / - specparam tsetup_RY_WENeg = 1;//twr edge \ - specparam tsetup_RY_RENeg = 1;//trr edge \ - specparam tsetup_CLE_RENeg = 1; - specparam tsetup_ALE_RENeg = 1; - specparam tsetup_CENeg_RENeg = 1; - specparam tsetup_RENeg_CENeg = 1; - - //thold values - specparam thold_CLE_WENeg = 1;//tclh edge / - specparam thold_CENeg_WENeg = 1;//tch edge / - specparam thold_ALE_WENeg = 1;//talh edge / - specparam thold_IO0_WENeg = 1;//tdh edge / - - //tpw values - specparam tpw_WENeg_negedge = 1;//twp - specparam tpw_WENeg_posedge = 1;//twh - specparam tpw_RENeg_negedge = 1;//trp - specparam tpw_RENeg_posedge = 1;//treh - specparam tperiod_WENeg = 1;//twc - specparam tperiod_RENeg = 1;//trc - - //tdevice values: values for internal delays - `ifdef SPEEDSIM - // Program Operation - specparam tdevice_PROG = 698; - // Fast programming operation - specparam tdevice_FPROG = 314; - // Program Operation - specparam tdevice_XPROG = 200; - // Program Operation - specparam tdevice_PRE_PROG = 9000; - //Block Erase Operation - specparam tdevice_BERS = 17400; - //Fast block erase operation - specparam tdevice_FBERS = 10200; - //Block Erase Operation - specparam tdevice_XBERS = 17400; - //Dummy busy time - specparam tdevice_DBSY = 400; - //Block status inquiry time - specparam tdevice_BSTATINQ = 100; - //Page transfer time - specparam tdevice_TR = 300; - //Fast programming start time - specparam tdevice_FPSTART = 100; - - `else // not SPEEDSIM - // Program Operation - specparam tdevice_PROG = 698000; - // Fast programming operation - specparam tdevice_FPROG = 314000; - // Program Operation - specparam tdevice_XPROG = 120000; - // Program Operation - specparam tdevice_PRE_PROG = 90000000; - //Block Erase Operation - specparam tdevice_BERS = 174000000; - //Fast block erase operation - specparam tdevice_FBERS = 102000000; - //Block Erase Operation - specparam tdevice_XBERS = 174000000; - //Dummy busy time - specparam tdevice_DBSY = 400; - //Block status inquiry time - specparam tdevice_BSTATINQ = 1000; - //Page transfer time - specparam tdevice_TR = 15000; - //Fast programming start time - specparam tdevice_FPSTART = 100; - `endif // SPEEDSIM - -/////////////////////////////////////////////////////////////////////////////// -// Input Port Delays don't require Verilog description -/////////////////////////////////////////////////////////////////////////////// -// Path delays // -/////////////////////////////////////////////////////////////////////////////// - -// specify transport delay for Data output paths - -// Data ouptut paths - - if(statread_cond) - ( CENeg *> IO7 ) = tpd_CENeg_IO0; - if(statread_cond) - ( CENeg *> IO6 ) = tpd_CENeg_IO0; - if(statread_cond) - ( CENeg *> IO5 ) = tpd_CENeg_IO0; - if(statread_cond) - ( CENeg *> IO4 ) = tpd_CENeg_IO0; - if(statread_cond) - ( CENeg *> IO3 ) = tpd_CENeg_IO0; - if(statread_cond) - ( CENeg *> IO2 ) = tpd_CENeg_IO0; - if(statread_cond) - ( CENeg *> IO1 ) = tpd_CENeg_IO0; - if(statread_cond) - ( CENeg *> IO0 ) = tpd_CENeg_IO0; - - if(nostatread_cond) - ( CENeg *> IO7 ) = tpd_CENeg_IO0; - if(nostatread_cond) - ( CENeg *> IO6 ) = tpd_CENeg_IO0; - if(nostatread_cond) - ( CENeg *> IO5 ) = tpd_CENeg_IO0; - if(nostatread_cond) - ( CENeg *> IO4 ) = tpd_CENeg_IO0; - if(nostatread_cond) - ( CENeg *> IO3 ) = tpd_CENeg_IO0; - if(nostatread_cond) - ( CENeg *> IO2 ) = tpd_CENeg_IO0; - if(nostatread_cond) - ( CENeg *> IO1 ) = tpd_CENeg_IO0; - if(nostatread_cond) - ( CENeg *> IO0 ) = tpd_CENeg_IO0; - - if(tdp_RE) - ( RENeg => IO7 ) = tpd_RENeg_IO0; - if(tdp_RE) - ( RENeg => IO6 ) = tpd_RENeg_IO0; - if(tdp_RE) - ( RENeg => IO5 ) = tpd_RENeg_IO0; - if(tdp_RE) - ( RENeg => IO4 ) = tpd_RENeg_IO0; - if(tdp_RE) - ( RENeg => IO3 ) = tpd_RENeg_IO0; - if(tdp_RE) - ( RENeg => IO2 ) = tpd_RENeg_IO0; - if(tdp_RE) - ( RENeg => IO1 ) = tpd_RENeg_IO0; - if(tdp_RE) - ( RENeg => IO0 ) = tpd_RENeg_IO0; - -// R output path - (WENeg => RY) = tpd_WENeg_RY; - -/////////////////////////////////////////////////////////////////////////////// -// Timing Violation / -/////////////////////////////////////////////////////////////////////////////// - - $setup ( IO7 ,posedge WENeg &&& Check_IO0_WENeg ,tsetup_IO0_WENeg,Viol); - $setup ( IO6 ,posedge WENeg &&& Check_IO0_WENeg ,tsetup_IO0_WENeg,Viol); - $setup ( IO5 ,posedge WENeg &&& Check_IO0_WENeg ,tsetup_IO0_WENeg,Viol); - $setup ( IO4 ,posedge WENeg &&& Check_IO0_WENeg ,tsetup_IO0_WENeg,Viol); - $setup ( IO3 ,posedge WENeg &&& Check_IO0_WENeg ,tsetup_IO0_WENeg,Viol); - $setup ( IO2 ,posedge WENeg &&& Check_IO0_WENeg ,tsetup_IO0_WENeg,Viol); - $setup ( IO1 ,posedge WENeg &&& Check_IO0_WENeg ,tsetup_IO0_WENeg,Viol); - $setup ( IO0 ,posedge WENeg &&& Check_IO0_WENeg ,tsetup_IO0_WENeg,Viol); - - $hold ( posedge WENeg &&& Check_IO0_WENeg , IO7 ,thold_IO0_WENeg, Viol); - $hold ( posedge WENeg &&& Check_IO0_WENeg , IO6 ,thold_IO0_WENeg, Viol); - $hold ( posedge WENeg &&& Check_IO0_WENeg , IO5 ,thold_IO0_WENeg, Viol); - $hold ( posedge WENeg &&& Check_IO0_WENeg , IO4 ,thold_IO0_WENeg, Viol); - $hold ( posedge WENeg &&& Check_IO0_WENeg , IO3 ,thold_IO0_WENeg, Viol); - $hold ( posedge WENeg &&& Check_IO0_WENeg , IO2 ,thold_IO0_WENeg, Viol); - $hold ( posedge WENeg &&& Check_IO0_WENeg , IO1 ,thold_IO0_WENeg, Viol); - $hold ( posedge WENeg &&& Check_IO0_WENeg , IO0 ,thold_IO0_WENeg, Viol); - - $setup ( CLE ,negedge WENeg ,tsetup_CLE_WENeg , Viol); - $setup ( ALE ,negedge WENeg ,tsetup_ALE_WENeg , Viol); - $setup ( CENeg ,negedge WENeg ,tsetup_CENeg_WENeg , Viol); - $setup ( WENeg ,negedge CENeg &&& WENeg ,tsetup_WENeg_CENeg , Viol); - $setup ( WENeg ,negedge RENeg ,tsetup_WENeg_RENeg , Viol); - $setup ( RY ,negedge WENeg &&& RY ,tsetup_RY_WENeg , Viol); - $setup ( RY ,negedge RENeg &&& RY ,tsetup_RY_RENeg , Viol); - $setup ( RENeg ,negedge WENeg ,tsetup_RENeg_WENeg , Viol); - $setup ( WPNeg ,negedge WENeg ,tsetup_WENeg_RENeg , Viol); - $setup ( CLE ,negedge RENeg ,tsetup_CLE_RENeg , Viol); - $setup ( ALE ,negedge RENeg ,tsetup_ALE_RENeg , Viol); - $setup ( CENeg ,negedge RENeg ,tsetup_CENeg_RENeg , Viol); - $setup ( RENeg ,negedge CENeg ,tsetup_RENeg_CENeg , Viol); - - $hold ( posedge WENeg &&& Check_WENeg,CLE,thold_CLE_WENeg, Viol); - $hold ( posedge WENeg &&& Check_WENeg,ALE,thold_ALE_WENeg, Viol); - $hold ( posedge WENeg &&& Check_WENeg,CENeg,thold_CENeg_WENeg,Viol); - - $width (posedge WENeg , tpw_WENeg_posedge); - $width (negedge WENeg , tpw_WENeg_negedge); - $period(negedge WENeg , tperiod_WENeg); - $period(posedge WENeg , tperiod_WENeg); - $width (posedge RENeg , tpw_RENeg_posedge); - $width (negedge RENeg , tpw_RENeg_negedge); - $period(negedge RENeg , tperiod_RENeg); - $period(posedge RENeg , tperiod_RENeg); - - endspecify - - //Used as wait periods - `ifdef SPEEDSIM - time poweredupT = 1000; // 10 us - time RstErsT = 500;// 5 us - time RstProgT = 1000; // 10 us - time RstReadT = 500; // 5 us - `else // not SPEEDSIM - time poweredupT = 10000; // 10 us - time RstErsT = 500000;// 500 us - time RstProgT = 10000; // 10 us - time RstReadT = 5000; // 5 us - `endif // SPEEDSIM - -/////////////////////////////////////////////////////////////////////////////// -// Main Behavior Block / -/////////////////////////////////////////////////////////////////////////////// - - reg deq; - ////////////////////////////////////////////////////////// - // Output Data Gen - ////////////////////////////////////////////////////////// - - always @(DIn, DOut) - begin - if (DIn==DOut) - deq=1'b1; - else - deq=1'b0; - end - // check when data is generated from model to avoid setuphold check in - // those occasion - assign deg=deq; - - initial - begin - ////////////////////////////////////////////////////////////////// - //ID array data / S30ML01GP00 DEVICE SPECIFIC - ////////////////////////////////////////////////////////////////// - IDArray[4'd0] = 8'h01; - IDArray[4'd1] = 8'hDC; - - tmp_timing = TimingModel;//copy of TimingModel - i = 14; - while ((i >= 0) && (found != 1'b1))//search for first non null character - begin //i keeps position of first non null character - j = 7; - while ((j >= 0) && (found != 1'b1)) - begin - if (tmp_timing[i*8+j] != 1'd0) - found = 1'b1; - else - j = j-1; - end - i = i - 1; - end - i = i +1; - if (found)//if non null character is found - begin - for (j=0;j<=7;j=j+1) - begin - tmp_char[j] = TimingModel[(i-13)*8+j]; - end - end - - if ((tmp_char == "0") || (tmp_char == "1")) - IDArray[4'd2] = 8'h00; - else - IDArray[4'd2] = 8'h01; - - IDArray[4'd3] = 8'h01; - IDArray[4'd4] = 8'h22; - end - - // initialize memory and load preoload files if any - initial - begin: InitMemory - integer i,j,k; - //for (i=0;i<= PageNum;i=i+1) - //begin - // for (j=0;j<= PageSize;j=j+1) - // begin - // Mem[i*(PageSize+1)+j]=MaxData; - // end - //end - - //page segment start address offset - ssa[0] =12'h000; - ssa[1] =12'h200; - ssa[2] =12'h400; - ssa[3] =12'h600; - ssa[4] =12'h800; - ssa[5] =12'h810; - ssa[6] =12'h820; - ssa[7] =12'h830; - //page segment end address offset - sea[0] =12'h1FF; - sea[1] =12'h3FF; - sea[2] =12'h5FF; - sea[3] =12'h7FF; - sea[4] =12'h80F; - sea[5] =12'h81F; - sea[6] =12'h82F; - sea[7] =12'h83F; - - if (UserPreload && !(mem_file_name == "none")) - begin - //----------------------------------------------------------------- - // Memory preload file format for s30ml04gp00 - //----------------------------------------------------------------- - // / - comment - // @aaaaaaaa - stands for page address and address within - // first 2112 bytes of the page - // dd -
is byte to be written at Mem(Page)(offset++) - // page is div 2112 - // offset is mod 2112 - // offset is incremented on every write - //----------------------------------------------------------------- - $readmemh(mem_file_name, Mem); - //mark page segments that have been programed - for (i=0;i<(PageNum+1)*(SegmentNum+1);i=i+1) - ProgramedFlag[i] = 1'b0; - for (i=0;i<= PageNum;i=i+1) - begin - j = 0; - while (j<= PageSize) - begin - if (Mem[i*(PageSize+1)+j]!==-1) - begin - k = i*(PageSize+1)+j; - getSegment(k,segment); - ProgramedFlag[i*(SegmentNum+1)+segment] = 1'b1; - j = sea [segment]; - j = j + 1; - end - else - j = j + 1; - end - end - end - end - - initial - begin - STAT_ACT =1'b0; - STAT_M_ACT =1'b0; - ERS_ACT =1'b0; - PRG_ACT =1'b0; - FP_ACT =1'b0; - RD_ACT =1'b0; - XTREM_ACT =1'b0; - XTR_MPRG =1'b0; - RSTSTART =1'b0; - RSTDONE =1'b0; - - write =1'b0; - read =1'b0; - for(j=0;j<=PageSize;j=j+1) - begin - WrBuffData[j] = -1; - WrBuffData1[j] = -1; - end - for(j=0;j<=SegmentNum;j=j+1) - begin - SegForProg[i]=1'b0; - CSegForProg[i]=1'b0; - SegForProg1[i]=1'b0; - CSegForProg1[i]=1'b0; - end - WrAddr = -1; - WrPage = -1; - CWrAddr = -1; - CWrPage = -1; - - current_state = IDLE; - next_state = IDLE; - - Status = 8'b01100100; - - PROG_in = 1'b0; - PROG_out = 1'b0; - XPROG_in = 1'b0; - XPROG_out = 1'b0; - PRE_PROG_in = 1'b0; - PRE_PROG_out = 1'b0; - BERS_in = 1'b0; - BERS_out = 1'b0; - XBERS_in = 1'b0; - XBERS_out = 1'b0; - DBSY_in = 1'b0; - DBSY_out = 1'b0; - TR_in = 1'b0; - TR_out = 1'b0; - FPSTART_in = 1'b0; - FPSTART_out= 1'b0; - BSTATINQ_in= 1'b0; - BSTATINQ_out=1'b0; - - PROG1_in = 1'b0; - PROG1_out = 1'b0; - PROG2_in = 1'b0; - PROG2_out = 1'b0; - XPROG1_in = 1'b0; - XPROG1_out = 1'b0; - XPROG2_in = 1'b0; - XPROG2_out = 1'b0; - DBSY1_in = 1'b0; - DBSY1_out = 1'b0; - R_zd = 1'b1; - - firstFlag = 1'b0; - prog_time = tdevice_PROG; - erase_time = tdevice_BERS; - statread = 1'b0; - nostatread = 1'b1; - end - - //Power Up time 10 us; - initial - begin - PoweredUp = 1'b0; - #poweredupT PoweredUp = 1'b1; - end - - always @(negedge FP) - begin - if (PRG_ACT) - begin - $display("Embeded programm in progress, simulation may be "); - $display("inacurate due to timinig violation on FP"); - end - if (ERS_ACT) - begin - $display("Embeded erase in progress, simulation may be "); - $display("inacurate due to timinig violation on FP"); - end - FP_ACT = 1'b1; - FPSTART_in = 1'b1; - prog_time = tdevice_FPROG; - erase_time= tdevice_FBERS; - end - - always @(posedge FP) - begin - if (PRG_ACT) - begin - $display("Embeded programm in progress, simulation may be "); - $display("inacurate due to timinig violation on FP"); - end - if (ERS_ACT) - begin - $display("Embeded erase in progress, simulation may be "); - $display("inacurate due to timinig violation on FP"); - end - FP_ACT = 1'b0; - FPSTART_in = 1'b0; - prog_time = tdevice_PROG; - erase_time = tdevice_BERS; - end - - always @(posedge FPSTART_in) - begin : FP_Time - #(tdevice_FPSTART) FPSTART_out = 1'b1; - end - - always @(negedge FPSTART_in) - begin - disable FP_Time; - #1 FPSTART_out = 1'b0; - end - - //Program Operation - always @(posedge PROG_in) - begin:ProgTime - #(prog_time + WER_01) PROG_out = 1'b1; - if (FP_ACT & (~FPSTART_out)) - begin - $display("Simulation results may been inacurate"); - $display("since timing violation occures on FP"); - end - end - - always @(negedge PROG_in) - begin - disable ProgTime; - #1 PROG_out = 1'b0; - end - //PreProgram Operation - always @(posedge PRE_PROG_in) - begin:PreProgTime - #(tdevice_PRE_PROG + WER_01) PRE_PROG_out = 1'b1; - end - always @(negedge PRE_PROG_in) - begin - disable PreProgTime; - #1 PRE_PROG_out = 1'b0; - end - //XProgram Operation - always @(posedge XPROG_in) - begin:XProgTime - #(tdevice_XPROG + WER_01) XPROG_out = 1'b1; - end - always @(negedge XPROG_in) - begin - disable XProgTime; - #1 XPROG_out = 1'b0; - end - //Program Operation 1 - always @(posedge PROG1_in) - begin:ProgTime1 - #(tdevice_PROG) PROG1_out = 1'b1; - end - always @(negedge PROG1_in) - begin - disable ProgTime1; - #1 PROG1_out = 1'b0; - end - //XProgram Operation 1 - always @(posedge XPROG1_in) - begin:XProgTime1 - #(tdevice_XPROG) XPROG1_out = 1'b1; - end - always @(negedge XPROG1_in) - begin - disable XProgTime1; - #1 XPROG1_out = 1'b0; - end - //Program Operation 2 - always @(posedge PROG2_in) - begin:ProgTime2 - #(tdevice_PROG) PROG2_out = 1'b1; - end - always @(negedge PROG2_in) - begin - disable ProgTime2; - #1 PROG2_out = 1'b0; - end - //XProgram Operation 2 - always @(posedge XPROG2_in) - begin:XProgTime2 - #(tdevice_XPROG) XPROG2_out = 1'b1; - end - always @(negedge XPROG2_in) - begin - disable XProgTime2; - #1 XPROG2_out = 1'b0; - end - // Dummy busy time1 - always @(posedge DBSY1_in) - begin : DummyBusyTime1 - #(tdevice_DBSY + WER_01) DBSY1_out = 1'b1; - end - always @(negedge DBSY1_in) - begin - disable DummyBusyTime1; - #1 DBSY1_out = 1'b0; - end - //Block Erase Operation - always @(posedge BERS_in) - begin : ErsTime - #(erase_time + WER_01) BERS_out = 1'b1; - if (FP_ACT & (~FPSTART_out)) - begin - $display("Simulation results may been inacurate"); - $display("since timing violation occures on FP"); - end - end - - always @(negedge BERS_in) - begin - disable ErsTime; - #1 BERS_out = 1'b0; - end - //Block Erase Operation - always @(posedge XBERS_in) - begin : XErsTime - #(tdevice_XBERS + WER_01) XBERS_out = 1'b1; - end - always @(negedge XBERS_in) - begin - disable XErsTime; - #1 XBERS_out = 1'b0; - end - // Dummy busy time - always @(posedge DBSY_in) - begin : DummyBusyTime - #(tdevice_DBSY+ WER_01) DBSY_out = 1'b1; - end - always @(negedge DBSY_in) - begin - disable DummyBusyTime; - #1 DBSY_out = 1'b0; - end - //Page transfer time - always @(posedge TR_in) - begin : PageTransferTime - #(tdevice_TR) TR_out = 1'b1; - end - always @(negedge TR_in) - begin - disable PageTransferTime; - #1 TR_out = 1'b0; - end - - always @(posedge BSTATINQ_in) - begin : BSTATINQ_Time - #(tdevice_BSTATINQ + WER_01) BSTATINQ_out = 1'b1; - end - - always @(negedge BSTATINQ_in) - begin - disable BSTATINQ_Time; - #1 BSTATINQ_out = 1'b0; - end - - /////////////////////////////////////////////////////////////////////////// - // process for reset control and FSM state transition - /////////////////////////////////////////////////////////////////////////// - always @(PoweredUp) - begin - if (PoweredUp) - begin - reseted = 1'b1; - if (PRE) - current_state = RD; - else //currently undefined functionality for PRE=0 - current_state = IDLE; - end - else - begin - current_state = IDLE; - reseted = 1'b0; - end - end - always @(next_state) - begin - if (PoweredUp) - current_state = next_state; - else - begin - current_state = IDLE; - reseted = 1'b0; - end - end - - ////////////////////////////////////////////////////////////////////////// - //process for generating the write and read signals - ////////////////////////////////////////////////////////////////////////// - always @ (WENeg, CENeg, RENeg) - begin - if (~WENeg && ~CENeg && RENeg && WPNeg) - write = 1'b1; - else if (WENeg && ~CENeg && RENeg && WPNeg) - write = 1'b0; - else - write = 1'b0; - if (WENeg && ~CENeg && ~RENeg ) - read = 1'b1; - else if (WENeg && ~CENeg && RENeg ) - read = 1'b0; - else - read = 1'b0; - end - - ////////////////////////////////////////////////////////////////////////// - //Latches 8 bit address on rising edge of WE# - //Latches data on rising edge of WE# - ////////////////////////////////////////////////////////////////////////// - always @ (posedge WENeg) - begin - // latch 8 bit read address - if (WENeg && ALE && ~CENeg && ~CLE && WPNeg) - AddrCom = A[7:0]; - // latch data - if (WENeg && ~ALE && RENeg && WPNeg) - Data = DIn[7:0]; - end - - /////////////////////////////////////////////////////////////////////////// - // Timing control for the Reset Operation - /////////////////////////////////////////////////////////////////////////// - event rstdone_event; - always @ (posedge reseted) - begin - disable rstdone_process; - RSTDONE = 1'b1; // reset done - end - - always @ (posedge RSTSTART) - begin - if (reseted && RSTDONE) - begin - if (ERS_ACT) - duration = RstErsT; - else if (PRG_ACT) - duration = RstProgT; - else - duration = RstReadT; - RSTDONE = 1'b0; - ->rstdone_event; - end - end - - always @(rstdone_event) - begin:rstdone_process - #duration RSTDONE = 1'b1; - end - - /////////////////////////////////////////////////////////////////////////// - // Main Behavior Process - // combinational process for next state generation - /////////////////////////////////////////////////////////////////////////// - - //WRITE CYCLE TRANSITIONS - always @(negedge write or negedge reseted) - begin - if (reseted != 1'b1 ) - next_state = current_state; - else - case (current_state) - IDLE : - begin - if (CLE && ~ALE && Data==8'h00 && ~FP_ACT) - next_state = PREL_RD; - else if ( CLE && ~ALE && Data==8'h90 && ~FP_ACT) - next_state = ID_PREL; - else if ( CLE && ~ALE && Data==8'h80) - next_state = PREL_PRG; - else if ( CLE && ~ALE && Data==8'h60) - next_state = PREL_ERS; - else if ( CLE && ~ALE && Data==8'hFF && ~FP_ACT) - next_state = RESET; // reset - else if ( CLE && ~ALE && Data==8'h70 ) - next_state = IDLE; // reset - else if (CLE && ~ALE && Data==8'h85 && PGD_ACT) - next_state = PGD_PREL; - else if ( CLE && ~ALE && Data==8'hA0 && ~FP_ACT ) - next_state = XTREM_PREL; - else if ( CLE) - next_state = UNKNOWN; - end - - XTREM_PREL : - begin - if (CLE && ~ALE && Data==8'hA0 && ~FP_ACT) - next_state = XTREM_IDLE; - else if (CLE && ~ALE && Data==8'hFF && ~FP_ACT) - next_state = RESET; - else if (CLE) - next_state = UNKNOWN; - end - - XTREM_IDLE : - begin - if (CLE && ~ALE && Data==8'h00 && ~FP_ACT ) - next_state = PREL_RD; - else if ( CLE && ~ALE && Data==8'h90 && ~FP_ACT) - next_state = ID_PREL; - else if ( CLE && ~ALE && Data==8'h80 && ~FP_ACT) - next_state = PREL_PRG; - else if ( CLE && ~ALE && Data==8'h60 && ~FP_ACT) - next_state = PREL_ERS; - else if ( CLE && ~ALE && Data==8'hFF && ~FP_ACT ) - next_state = RESET; // reset - else if ( CLE && ~ALE && Data==8'h70 && ~FP_ACT ) - next_state = XTREM_IDLE; // reset - else if (CLE && ~ALE && Data==8'h85 && PMOVE && ~FP_ACT) - next_state = PGD_PREL; - else if ( CLE && ~ALE && Data==8'hA0 && ~FP_ACT ) - next_state = XTREM_IDLE; - else if ( CLE) - next_state = UNKNOWN; - end - - PRE_PRG : - begin - if (CLE && ~ALE && Data==8'hFF && ~FP_ACT) - next_state = RESET; // reset - end - - UNKNOWN: - begin - if (CLE && ~ALE && Data==8'hFF && ~FP_ACT ) - next_state = RESET; - end - - PREL_RD: - begin - if (ALE && ~FP_ACT) - next_state = A0_RD; - else if ( CLE && ~ALE && Data==8'hFF && ~FP_ACT ) - next_state = RESET; // reset - end - - A0_RD : - begin - if ( ALE && ~FP_ACT) - next_state = A1_RD; - else if ( CLE && ~ALE && Data==8'hFF && ~FP_ACT ) - next_state = RESET; // reset - else if ( CLE) - next_state = UNKNOWN; - end - - A1_RD : - begin - if ( ALE && ~FP_ACT) - next_state = A2_RD; - else if ( CLE && ~ALE && Data==8'hFF && ~FP_ACT ) - next_state = RESET; // reset - else if ( CLE) - next_state = UNKNOWN; - end - - A2_RD : - begin - if ( ALE && ~FP_ACT) - next_state = A3_RD; - else if ( CLE && ~ALE && Data==8'hFF && ~FP_ACT ) - next_state = RESET; // reset - else if ( CLE) - next_state = UNKNOWN; - end - - A3_RD : - begin - if ( ALE && ~FP_ACT) - next_state = RD_WCMD; - else if ( CLE && ~ALE && Data==8'hFF && ~FP_ACT ) - next_state = RESET; // reset - else if ( CLE) - next_state = UNKNOWN; - end - - RD_WCMD: - begin - if ((ALE && cnt_addr >= 5) || (CLE && ~ALE && cnt_addr > 5)) - next_state = UNKNOWN; - else if (CLE && ~ALE && ~FP_ACT &&(Data==8'h30|| Data==8'h35)) - next_state = BUFF_TR; - else if (CLE && ~ALE && Data==8'hFF && ~FP_ACT) - next_state = RESET; - else if (CLE) - next_state = UNKNOWN; - end - - BUFF_TR : - begin - if ( CLE && ~ALE && Data==8'hFF && ~FP_ACT) - next_state = RESET; // reset - end - - RD : - begin - if ( CLE && ~ALE && Data==8'h00 && PGR_ACT && STAT_ACT - && ~FP_ACT) - next_state= RD; - else if (CLE && ~FP_ACT && ~ALE && Data==8'h00 && - (PGR_ACT || STAT_M_ACT)) - next_state= PREL_RD; - else if (CLE && ~ALE && Data==8'h80 && ~PGD_ACT) - next_state = PREL_PRG; - else if (CLE && ~ALE && Data==8'h90 && ~PGD_ACT && ~FP_ACT) - next_state = ID_PREL; - else if (CLE && ~ALE && Data==8'h70 && ~XTREM_ACT) - next_state = IDLE; - else if (CLE && ~ALE && Data==8'h70 && XTREM_ACT && ~FP_ACT) - next_state = XTREM_IDLE; - else if (CLE && ~ALE && Data==8'hFF && ~FP_ACT ) - next_state = RESET; // reset - else if (CLE && ~ALE && Data==8'h60 && ~PGD_ACT) - next_state = PREL_ERS; - else if (CLE && ~ALE && Data==8'h85 && PGD_ACT) - next_state = PGD_PREL; // Read next colomn address - else if (CLE && ~ALE && Data==8'h05 && ~PGD_ACT && ~FP_ACT) - next_state = CAC_PREL; - else if (CLE && ~ALE && Data==8'hA0 && ~PGD_ACT && ~XTREM_ACT - && ~FP_ACT) - next_state = XTREM_PREL; - else if (CLE) - next_state = UNKNOWN; - else - next_state = RD; - end - - CAC_PREL: - begin - if (ALE && ~FP_ACT) - next_state = A0_CAC; - else if (CLE && ~ALE && Data==8'hFF && ~FP_ACT) - next_state = RESET; - else if (CLE) - next_state = UNKNOWN; - end - - A0_CAC: - begin - if (ALE && ~FP_ACT) - next_state = A1_CAC; - else if (CLE && ~ALE && Data==8'hFF && ~FP_ACT) - next_state = RESET; - else if (CLE) - next_state = UNKNOWN; - end - - A1_CAC: - begin - if (CLE && ~ALE && Data==8'hE0 && ~FP_ACT) - next_state = RD; - else if (CLE && ~ALE && Data==8'hFF && ~FP_ACT) - next_state = RESET; - else if (CLE || ALE) - next_state = UNKNOWN; - end - - ID_PREL : - begin - if ( ALE && AddrCom==8'h00 && ~FP_ACT ) - next_state = ID; - else if ( CLE && ~ALE && Data==8'hFF && ~FP_ACT) - next_state = RESET; // reset - else if (CLE || ALE) - next_state = UNKNOWN; - end - - ID : - begin - if ( CLE && ~ALE && Data==8'h00 && ~FP_ACT ) - next_state = PREL_RD; - else if ( CLE && ~ALE && Data==8'h90 && ~FP_ACT ) - next_state = ID_PREL; - else if ( CLE && ~ALE && Data==8'h80 ) - next_state = PREL_PRG; - else if ( CLE && ~ALE && Data==8'h60 ) - next_state = PREL_ERS; - else if ( CLE && ~ALE && Data==8'h70 && ~XTREM_ACT ) - next_state = IDLE; - else if ( CLE && ~ALE && Data==8'h70 && XTREM_ACT && ~FP_ACT ) - next_state = XTREM_IDLE; - else if ( CLE && ~ALE && Data==8'hA0 && ~XTREM_ACT && ~FP_ACT) - next_state = XTREM_PREL; - else if ( CLE && ~ALE && Data==8'hFF && ~FP_ACT ) - next_state = RESET; // reset - else if (CLE || ALE) - next_state = UNKNOWN; - end - - PREL_PRG : - begin - if ( ALE ) - next_state = A0_PRG; - else if ( CLE && ~ALE && Data==8'hFF && ~FP_ACT) - next_state = RESET; // reset - else if (CLE) - next_state = UNKNOWN; - end - - A0_PRG : - begin - if ( ALE ) - next_state = A1_PRG; - else if ( CLE && ~ALE && Data==8'hFF && ~FP_ACT) - next_state = RESET; // reset - else if (CLE) - next_state = UNKNOWN; - end - - A1_PRG : - begin - if ( ALE ) - next_state = A2_PRG; - else if ( CLE && ~ALE && Data==8'hFF && ~FP_ACT) - next_state = RESET; // reset - else if (CLE) - next_state = UNKNOWN; - end - - A2_PRG : - begin - if ( ALE ) - next_state = A3_PRG; - else if ( CLE && ~ALE && Data==8'hFF && ~FP_ACT) - next_state = RESET; // reset - else if (CLE) - next_state = UNKNOWN; - end - - A3_PRG : - begin - if ( ALE ) - next_state = DATA_PRG; - else if ( CLE && ~ALE && Data==8'hFF && ~FP_ACT) - next_state = RESET; // reset - else if (CLE) - next_state = UNKNOWN; - end - - DATA_PRG : - begin - if ((ALE && (cnt_addr <2 || cnt_addr >= 5)) || - (CLE && ~ALE && cnt_addr > 5)) - next_state = UNKNOWN; - else if (CLE && ~ALE && Data==8'h10) - if (PRG_ACT) - next_state = WFPPD; // Waiting for programing done - else - next_state = PGMS; - else if (CLE && ~ALE && ~PGD_ACT && Data==8'h15) - if (PRG_ACT) - next_state = WFPD; // Waiting for programing done - else - next_state = CBSY; - else if (CLE && ~ALE && Data==8'h85) - next_state = PGMS_CAC; - else if (CLE && ~ALE && Data == 8'h12 && PGD_ACT && XTREM_ACT - && ~FP_ACT) - next_state = PGMS; - else if (CLE && ~ALE && Data==8'hFF) - next_state = RESET; // reset - else if (CLE) - next_state = UNKNOWN; - else if (~ALE && ~CLE && CWrAddr < PageSize+1) - next_state = DATA_PRG; // write next word to buffer - end - - WFPD: - begin - if (CLE && ~ALE && Data==8'hFF && ~FP_ACT) - next_state = RESET; // reset - end - - WFPPD: - begin - if (CLE && ~ALE && Data==8'hFF && ~FP_ACT) - next_state = RESET; // reset - end - - PGMS_CAC: - begin - if (CLE && ~ALE && Data==8'hFF && ~FP_ACT) - next_state = RESET; - else if (ALE) - next_state = A0_PRG_CAC; - else if (CLE) - next_state = UNKNOWN; - end - - PGMS : - begin - if ( CLE && ~ALE && Data==8'hFF && ~FP_ACT) - next_state = RESET; // reset - end - - CBSY: - begin - if ( CLE && ~ALE && Data==8'hFF && ~FP_ACT ) - next_state = RESET; // reset - end - - RDY_PRG : - begin - if ( CLE && ~ALE && Data==8'h80 ) - next_state = PREL_PRG; - else if ( CLE && ~ALE && Data==8'hFF && ~FP_ACT) - next_state = RESET; // reset - else if ( CLE && ~ALE && Data==8'h70 ) - next_state = RDY_PRG; // - else if ( CLE ) - next_state = UNKNOWN; // reset - end - - A0_PRG_CAC: - begin - if (ALE ) - next_state = DATA_PRG; - else if (CLE && ~ALE && Data==8'hFF && ~FP_ACT) - next_state = RESET; - else if ( CLE ) - next_state = UNKNOWN; // reset - end - - PREL_ERS : - begin - if ( ALE ) - next_state = A1_ERS; - else if ( CLE && ~ALE && Data==8'hFF && ~FP_ACT ) - next_state = RESET; // reset - else if ( CLE ) - next_state = UNKNOWN; // reset - end - - A1_ERS : - begin - if ( ALE ) - next_state = A2_ERS; - else if ( CLE && ~ALE && Data==8'hFF ) - next_state = RESET; // reset - else if ( CLE ) - next_state = UNKNOWN; // reset - end - - A2_ERS : - begin - if ( ALE ) - next_state = A3_ERS; - else if ( CLE && ~ALE && Data==8'hFF ) - next_state = RESET; // reset - else if ( CLE ) - next_state = UNKNOWN; // reset - end - - A3_ERS : - begin - if ( CLE && ~ALE && Data==8'hD0 ) - next_state = BERS_EXEC; - else if (CLE && ~ALE && XTREM_ACT && Data == 8'h11 - && ~FP_ACT) - next_state = PRE_PRG; - else if (CLE && ~ALE && Data == 8'h71 && ~FP_ACT) - next_state = BSTAT_INQ; //BUFF_TR; - else if ( CLE && ~ALE && Data==8'hFF && ~FP_ACT ) - next_state = RESET; // reset - else if ( CLE || ALE) - next_state = UNKNOWN; // reset - end - - BERS_EXEC : - begin - if ( CLE && ~ALE && Data==8'hFF && ~FP_ACT ) - next_state = RESET; // reset - end - - PGD_PREL : - begin - if ( ALE ) - next_state = A0_PGD; - else if ( CLE && ~ALE && Data==8'hFF && ~FP_ACT ) - next_state = RESET; // reset - else if ( CLE ) - next_state = UNKNOWN; // reset - end - - A0_PGD : - begin - if ( ALE ) - next_state = A1_PGD; - else if ( CLE && ~ALE && Data==8'hFF && ~FP_ACT ) - next_state = RESET; // reset - else if ( CLE ) - next_state = UNKNOWN; // reset - end - - A1_PGD : - begin - if ( ALE ) - next_state = A2_PGD; - else if ( CLE && ~ALE && Data==8'hFF && ~FP_ACT ) - next_state = RESET; // reset - else if ( CLE ) - next_state = UNKNOWN; // reset - end - - A2_PGD : - begin - if ( ALE ) - next_state = A3_PGD; - else if ( CLE && ~ALE && Data==8'hFF && ~FP_ACT ) - next_state = RESET; // reset - else if ( CLE ) - next_state = UNKNOWN; // reset - end - - A3_PGD : - begin - if ( ALE ) - next_state = CONF_PGD; - else if ( CLE && ~ALE && Data==8'hFF && ~FP_ACT ) - next_state = RESET; // reset - else if ( CLE ) - next_state = UNKNOWN; // reset - end - - CONF_PGD : - begin - if ((ALE && cnt_addr >= 5) || (CLE && ~ALE && cnt_addr > 5)) - next_state = UNKNOWN; - else if ( CLE && ~ALE && Data==8'h10) - next_state = PGMS; - else if ( CLE && ~ALE && XTREM_ACT && Data==8'h12 && ~FP_ACT) - next_state = PGMS; - else if ( CLE && ~ALE && Data==8'h85) - next_state = PGMS_CAC; - else if ( CLE && ~ALE && Data==8'hFF && ~FP_ACT) - next_state = RESET; // reset - else if ( CLE ) - next_state = UNKNOWN; // reset - end - BSTAT_INQ : - if ( CLE && ~ALE && Data==8'hFF && ~FP_ACT) - next_state = RESET; // reset - - endcase - end - - // RESET state, RSTDONE - always @(current_state, RSTDONE) - begin: StateGen1 - if (current_state == RESET && RSTDONE) - if (PRE) - next_state = RD; - else if (~XTREM_ACT) - next_state = IDLE; - else - next_state = XTREM_IDLE; - end - - always @(posedge reseted) - begin: StateGen1_1 - if (PRE) - next_state = RD; - else - next_state = IDLE; - end - - // BUFF_TR, TR_out - always @(current_state,read,BERS_out,XBERS_out,PROG_out,XPROG_out,TR_out, - DBSY_out, DBSY1_out, PROG1_out, XPROG1_out, - PROG2_out, XPROG2_out, BSTATINQ_out) - begin: StateGen2 - if (current_state == BUFF_TR) - if( TR_out) - next_state = RD; - if (current_state == BSTAT_INQ) - if( BSTATINQ_out) - next_state = RD; - end - - // CBSY - DBSY_out - always @(current_state,read,BERS_out,XBERS_out,PROG_out,XPROG_out,TR_out, - DBSY_out,DBSY1_out, PROG1_out, XPROG1_out, - PROG2_out, XPROG2_out) - begin: StateGen3 - if (current_state == CBSY && (DBSY_out || DBSY1_out)) - next_state = RDY_PRG; - end - - // WFPD,WFPPD,RDY_PRG - PROG_out - always @(current_state, BERS_out,XBERS_out,PROG_out,XPROG_out,TR_out, - DBSY_out, DBSY1_out, PROG1_out, XPROG1_out, - PROG2_out, XPROG2_out) - begin: StateGen5 - if (current_state == WFPD && (PROG1_out || XPROG1_out)) - next_state = CBSY; // programming done - else if (current_state == WFPPD && (PROG1_out || XPROG1_out)) - next_state = PGMS; // next start programing - else if (current_state == RDY_PRG && PROG1_out) - next_state = IDLE; - else if (current_state == RDY_PRG && XPROG1_out) - next_state = XTREM_IDLE; - end - - // PGMS - PROG_out - always @(posedge PROG_out ) - begin: StateGen5_1 - if (current_state == PGMS) - next_state = IDLE; // programming done - end - - // PRE_PRG - PRE_PROG_out - always @(posedge PRE_PROG_out ) - begin: StateGen5_2 - if (current_state == PRE_PRG) - next_state = XTREM_IDLE; // programming done - end - - // PGMS - XPROG_out - always @(posedge XPROG_out ) - begin: StateGen5_3 - if (current_state == PGMS) - next_state = XTREM_IDLE; // programming done - end - - // PGMS - PROG1_out - always @(posedge PROG2_out ) - begin: StateGen5_4 - if (current_state == PGMS) - next_state = IDLE; // programming done - end - - // PGMS - XPROG1_out - always @(posedge XPROG2_out ) - begin: StateGen5_5 - if (current_state == PGMS) - next_state = XTREM_IDLE; // programming done - end - - // BERS_EXEC, BERS_out - always @(current_state, BERS_out, - PROG_out, TR_out, DBSY_out) - begin: StateGen6_1 - if (current_state == BERS_EXEC && BERS_out) - next_state = IDLE; - end - - // BERS_EXEC, XBERS_out - always @(current_state, XBERS_out, - PROG_out, XPROG_out, TR_out, DBSY_out) - begin: StateGen6_2 - if (current_state == BERS_EXEC && XBERS_out) - next_state = XTREM_IDLE; - end - - always @(posedge STAT_ACT) - begin - statread = 1'b1; - nostatread = 1'b0; - end - - always @(negedge STAT_ACT) - begin - statread = 1'b0; - nostatread = 1'b1; - end - - /////////////////////////////////////////////////////////////////////////// - //FSM Output generation and general funcionality - /////////////////////////////////////////////////////////////////////////// - always @(posedge read) - begin - ->oe_event; - end - - always @(oe_event) - begin - oe = 1'b1; - #1 oe = 1'b0; - end - - always @( posedge oe) - begin: Output - case (current_state) - - RD : - begin - if (~PGD_ACT && ~STAT_ACT && ~STAT_M_ACT) - Read_Data(Address,PageAddr,BlockAddr); - else if (~PGD_ACT && ~STAT_ACT && STAT_M_ACT) - Read_StatMode(Blck); - else if (STAT_ACT) - Read_Status(Blck); - end - - ID : - begin - if ( IDAddr < 5 ) - begin - DOut_zd = IDArray[IDAddr]; - IDAddr = IDAddr+1; - end - else - DOut_zd = 'bz; - end - - IDLE , - XTREM_IDLE , - WFPD , - WFPPD , - PGMS , - CBSY , - PRE_PRG , - BUFF_TR , - RDY_PRG , - BERS_EXEC : - begin - if (STAT_ACT) - Read_Status(Blck); - end - endcase - end - - always @(WPNeg_ipd) - begin - Status[7] = WPNeg_ipd; - end - - always @(negedge write) - begin: Func0 - if (~reseted) - R_zd = 1'b1; - else if (reseted) - case (current_state) - IDLE, XTREM_IDLE : - begin - if ( CLE && ~ALE && (Data==8'h00 || Data==8'h60)) - begin - STAT_ACT = 1'b0; - Status[6:3] = 4'b1100; - Status[1:0] = 2'b00; - end - else if ( CLE && ~ALE && Data==8'h70 ) - begin - STAT_ACT = 1'b1; - end - else if (CLE && ~ALE && (Data==8'h80 || Data==8'h90)) - begin - STAT_ACT = 1'b0; - end - else if (CLE && ~ALE && Data==8'h85 && PGD_ACT) - begin - STAT_ACT = 1'b0; - Status[6:3] = 4'b1100; - Status[1:0] = 2'b00; - end - else if ( CLE && ~ALE && Data==8'hFF ) - set_reset; - end - - XTREM_PREL : - begin - if ( CLE && ~ALE && Data == 8'hA0) - XTREM_ACT = 1'b1; - else if ( CLE && ~ALE && Data==8'hFF ) - set_reset; - end - - UNKNOWN: - begin - if (CLE && ~ALE && Data==8'hFF) - begin - ERS_ACT = 1'b0; - PGD_ACT = 1'b0; - RD_ACT = 1'b0; - PGR_ACT = 1'b0; - Status[6:3] = 4'b1100; - Status[1:0] = 2'b00; - set_reset; - end - end - - PREL_RD: - begin - if (ALE) - begin - Pom_Address = AddrCom; - cnt_addr = 0; - end - else if (CLE && ~ALE && Data==8'hFF) - set_reset; - end - - A0_RD : - begin - if ( ALE ) - begin - Pom_Address = (AddrCom* 12'h100) + Pom_Address; - cnt_addr = cnt_addr + 1; - end - else if ( CLE && ~ALE && Data==8'hFF ) - set_reset; - end - - A1_RD : - begin - if ( ALE ) - begin - if ( XTREM_ACT ) - Page = AddrCom * 2; - else - Page = AddrCom; - cnt_addr = cnt_addr + 1; - end - else if ( CLE && ~ALE && Data==8'hFF ) - set_reset; - end - - A2_RD : - begin - if ( ALE ) - begin - Blck = AddrCom; - cnt_addr = cnt_addr + 1; - end - else if ( CLE && ~ALE && Data==8'hFF ) - set_reset; - end - - A3_RD : - begin - if ( ALE ) - begin - Blck = Blck + (AddrCom*12'h100); - cnt_addr = cnt_addr + 1; - end - else if ( CLE && ~ALE && Data==8'hFF ) - set_reset; - end - - RD_WCMD: - begin - if (CLE && ~ALE && Data==8'h30) - begin - PGR_ACT = 1'b1; - Address = Pom_Address; - PageAddr = Blck*(BlockSize + 1) + Page; - BlockAddr = Blck; - TR_in = 1'b1; - R_zd = 1'b0; - Status[6:5] = 2'b00; - end - else if( CLE && ~ALE && Data==8'h35) - begin - PGD_ACT = 1'b1; - PMOVE = 1'b1; - TR_in = 1'b1; - R_zd = 1'b0; - Status[6:5] = 2'b00; - Address = Pom_Address; - PageAddr = Blck*(BlockSize + 1) + Page; - for (i=0; i<=PageSize; i=i+1) - begin - PDBuffer[i] = -1; - PDBuffer1[i] = -1; - end - end - else if(CLE && ~ALE && Data==8'hFF) - set_reset; - else if (ALE) - cnt_addr = cnt_addr + 1; - end - - BUFF_TR : - begin - if ( CLE && ~ALE && Data==8'hFF ) - begin - TR_in = 1'b0; - DBSY_in = 1'b0; - if (XTREM_ACT) - back_to_xtrem = 1'b1; - else - back_to_xtrem = 1'b0; - set_reset; - end - else if ( CLE && ~ALE && Data==8'h70 ) - STAT_ACT = 1'b1; - end - - RD : - begin - if ( CLE && ~ALE && Data==8'h00 && ~PGD_ACT) - begin - Status[6:3] = 4'b1100; - Status[1:0] = 2'b00; - PGR_ACT = 1'b0; - STAT_ACT = 1'b0; - STAT_M_ACT = 1'b0; - end - else if ( CLE && ~ALE && Data==8'h70) - begin - STAT_ACT = 1'b1; - STAT_M_ACT = 1'b0; - PGR_ACT = 1'b0; - end - else if ( CLE && ~ALE && Data==8'h90 && ~PGD_ACT) - begin - STAT_ACT = 1'b0; - STAT_M_ACT = 1'b0; - PGR_ACT = 1'b0; - end - else if ( CLE && ~ALE && Data==8'h80 && ~PGD_ACT) - begin - STAT_ACT = 1'b0; - STAT_M_ACT = 1'b0; - PGR_ACT = 1'b0; - Status[6:3] = 4'b1100; - Status[1:0] = 2'b00; - end - else if ( CLE && ~ALE && Data==8'hA0 && ~PGD_ACT) - begin - STAT_ACT = 1'b0; - STAT_M_ACT = 1'b0; - Status[6:3] = 4'b1100; - Status[1:0] = 2'b00; - end - else if ( CLE && ~ALE && Data==8'h60 && ~PGD_ACT) - begin - STAT_ACT = 1'b0; - STAT_M_ACT = 1'b0; - PGR_ACT = 1'b0; - Status[6:3] = 4'b1100; - Status[1:0] = 2'b00; - end - else if ( CLE && ~ALE && Data==8'hFF ) - begin - set_reset; - STAT_M_ACT = 1'b0; - end - else if ( CLE && ~ALE && Data==8'h85 && PGD_ACT) - begin - STAT_ACT = 1'b0; - STAT_M_ACT = 1'b0; - Status[6:3] = 4'b1100; - Status[1:0] = 2'b00; - end - else if ( CLE && ~ALE && Data==8'h05 && ~PGD_ACT) - begin - STAT_ACT = 1'b0; - STAT_M_ACT = 1'b0; - Status[6:3] = 4'b1100; - Status[1:0] = 2'b00; - end - end - - CAC_PREL: - begin - if( ALE ) - begin - Pom_Address = AddrCom; - cnt_addr = 0; - end - else if( CLE && ~ALE && Data==8'hFF) - set_reset; - end - - A0_CAC: - begin - if (ALE) - begin - Pom_Address = Pom_Address + AddrCom * 12'h100; - cnt_addr = cnt_addr + 1; - end - else if (CLE && ~ALE && Data==8'hFF) - set_reset; - end - - A1_CAC: - begin - if (CLE && ~ALE && Data==8'hE0) - Address = Pom_Address; - else if (CLE && ~ALE && Data==8'hFF) - set_reset; - else if (ALE) - cnt_addr = cnt_addr + 1; - end - - ID_PREL : - begin - if ( ALE && AddrCom==8'h00 ) - IDAddr = 0; - else if ( CLE && ~ALE && Data==8'hFF ) - set_reset; - end - - ID : - begin - if ( CLE && ~ALE && Data==8'hFF ) - set_reset; - else if ( CLE && ~ALE && Data==8'h70 ) - STAT_ACT = 1'b1; - else if ( CLE && ~ALE && Data==8'h00 ) - STAT_ACT = 1'b0; - end - - PREL_PRG : - begin - if ( ALE ) - begin - CWrAddr = AddrCom; - cnt_addr = 0; - end - else if ( CLE && ~ALE && Data==8'hFF ) - set_reset; - end - - A0_PRG : - begin - if ( ALE ) - begin - CWrAddr = (AddrCom * 12'h100)+CWrAddr; - cnt_addr = cnt_addr + 1; - for(i=0; i<=PageSize; i=i+1) - CashBuffData[i]=-1; - end - else if ( CLE && ~ALE && Data==8'hFF ) - set_reset; - end - - A1_PRG : - begin - if ( ALE ) - begin - if ( XTREM_ACT ) - Page = AddrCom * 2; - else - Page = AddrCom; - - cnt_addr = cnt_addr + 1; - end - else if ( CLE && ~ALE && Data==8'hFF ) - set_reset; - end - - A2_PRG : - begin - if ( ALE ) - begin - Blck = AddrCom; - cnt_addr = cnt_addr + 1; - end - else if ( CLE && ~ALE && Data==8'hFF ) - set_reset; - end - - A3_PRG : - begin - if ( ALE ) - begin - Blck = (AddrCom*12'h100) + Blck; - Page_pom = Page + Blck*(BlockSize+1); - CWrPage = Page + Blck*(BlockSize+1); - getSegment(CWrAddr,segment); - cnt_addr = cnt_addr + 1; - for(i=0; i<= SegmentNum; i=i+1) - begin - CSegForProg[i] = ProgramedFlag[ - (SegmentNum+1)*Page_pom + i]; - CSegForProg1[i] = ProgramedFlag[ - (SegmentNum+1)*(Page_pom+1) + i]; - end - end - else if ( CLE && ~ALE && Data==8'hFF ) - set_reset; - end - - DATA_PRG : - begin - if (CLE && ~ALE && Data==8'hFF) - set_reset; - else if (~ALE && ~CLE && CWrAddr < PageSize+1) - begin - if (~XTREM_ACT) - begin - getSegment(CWrAddr,segment); - if (~ProgramedFlag[(SegmentNum+1)*CWrPage + segment]) - CashBuffData[CWrAddr] = Data; - CSegForProg[segment] = 1'b1; - end - else - begin - Page_pom = Page + Blck*(BlockSize+1); - XgetSegment(CWrAddr,segment,segment1); - if (~ProgramedFlag[(SegmentNum+1)*(Page_pom)+segment] - && ~ProgramedFlag[(SegmentNum+1)*(Page_pom)+segment1] - && ~PGD_ACT) - CashBuffData[CWrAddr] = Data; - else if (~ProgramedFlag[(SegmentNum+1)* - (Page_pom)+segment] && PGD_ACT && - ~ProgramedFlag[(SegmentNum+1)*(Page_pom)+segment1]) - XTR_Buffdata(CWrAddr,Data); - if (Page_pom > CWrPage) - begin - CSegForProg1[segment] = 1; - CSegForProg1[segment1] = 1; - end - else if (Page_pom == CWrPage) - begin - CSegForProg[segment] = 1; - CSegForProg[segment1] = 1; - end - end - Page_pom = Page + Blck*(BlockSize+1); - CWrAddr = CWrAddr+1; - end - else if (CLE && ~ALE && Data==8'h10) - begin - R_zd = 1'b0; - Status[5] = 1'b0; - //part of the FlagGeneration process - if (~PRG_ACT) - begin - CWrPage = Page + Blck*(BlockSize+1); - PRG_ACT = 1'b1; - if (~XTREM_ACT) - PROG_in = 1'b1; - else - XPROG_in = 1'b1; - end - firstFlag = 1'b1; - ProgBlock[Blck] = 1; - end - else if (CLE && ~ALE && Data==8'h12) - begin - if (PGD_ACT) - CWrPage = Page/2 + Blck*(BlockSize+1); - if (~PRG_ACT) - begin - PRG_ACT = 1'b1; - if (XTREM_ACT) - XPROG_in = 1'b1; - end - R_zd = 1'b0; - Status[5] = 1'b0; - XTR_MPRG = 1'b1; - firstFlag = 1'b1; - ProgBlock[Blck] = 1; - end - else if( CLE && ~ALE && ~PGD_ACT && Data==8'h15) - begin - if (~PRG_ACT) - begin - DBSY_in = 1'b1; - CWrPage = Page + Blck*(BlockSize+1); - end - R_zd = 1'b0; - Status[6] = 1'b0; - firstFlag = 1'b1; - ProgBlock[Blck] = 1; - end - else if (ALE) - cnt_addr = cnt_addr + 1; - end - - PGMS_CAC: - begin - if (ALE) - begin - CWrAddr = AddrCom; - cnt_addr = 0; - end - else if (CLE && ~ALE && Data==8'hFF) - set_reset; - end - - A0_PRG_CAC: - begin - if (ALE) - begin - CWrAddr = (AddrCom * 12'h100)+CWrAddr; - cnt_addr = cnt_addr + 1; - end - else if (CLE && ~ALE && Data==8'hFF) - set_reset; - end - - WFPD: - begin - if (CLE && ~ALE && Data==8'hFF) - begin - set_reset; - if (XTREM_ACT) - back_to_xtrem = 1'b1; - else - back_to_xtrem = 1'b0; - if (XTREM_ACT && ~PGD_ACT) - XTR_Pgms_init(WrPage); - end - else if (CLE && ~ALE && Data==8'h70) - STAT_ACT = 1'b1; - end - - WFPPD: - begin - if (CLE && ~ALE && Data==8'hFF) - begin - set_reset; - if (XTREM_ACT) - back_to_xtrem = 1'b1; - else - back_to_xtrem = 1'b0; - if (XTREM_ACT && ~PGD_ACT) - XTR_Pgms_init(WrPage); - // part of the FlagGeneration process - if(~PROG1_out) - begin - PROG1_in = 1'b0; - end - if(~XPROG1_out) - begin - XPROG1_in = 1'b0; - end - end - else if (CLE && ~ALE && Data==8'h70) - STAT_ACT = 1'b1; - end - - PRE_PRG : - begin - if (CLE && ~ALE && Data==8'hFF) - begin - if (~(WPNeg==1'b0)) - begin - for(i = Blck *(BlockSize+1) *(PageSize+1); - i < (Blck+1)*(BlockSize+1) *(PageSize+1); - i=i+1) - Mem[i] = -1; - InvBlock[Blck] = 1; - end - PRE_PROG_in = 1'b0; - set_reset; - end - else if (CLE && ~ALE && Data==8'h70) - STAT_ACT = 1; // read status - end - - PGMS : - begin - if ( CLE && ~ALE && Data==8'hFF ) - begin - set_reset; - InvBlockPgms[Blck] = 1; - if (XTREM_ACT) - back_to_xtrem = 1'b1; - else - back_to_xtrem = 1'b0; - if (XTREM_ACT && ~PGD_ACT) - XTR_Pgms_init(WrPage); - end - else if ( CLE && ~ALE && Data==8'h70 ) - STAT_ACT = 1'b1; - end - - CBSY : - begin - if ( CLE && ~ALE && Data==8'h70 ) - STAT_ACT = 1'b1; - else if ( CLE && ~ALE && Data==8'hFF ) - begin - set_reset; - if (XTREM_ACT) - back_to_xtrem = 1'b1; - else - back_to_xtrem = 1'b0; - DBSY_in = 1'b0; - DBSY1_in = 1'b0; - end - end - - RDY_PRG : - begin - if ( CLE && ~ALE && Data==8'h70 ) - STAT_ACT = 1'b1; - else if (CLE && ~ALE && Data==8'hFF) - begin - set_reset; - if (XTREM_ACT) - back_to_xtrem = 1'b1; - else - back_to_xtrem = 1'b0; - if (XTREM_ACT && ~PGD_ACT) - XTR_Pgms_init(WrPage); - end - end - - PREL_ERS : - begin - if ( ALE ) - begin - Page = AddrCom; - cnt_addr = 0; - end - else if ( CLE && ~ALE && Data==8'hFF ) - set_reset; - end - - A1_ERS : - begin - if ( ALE ) - begin - Blck = AddrCom; - cnt_addr = cnt_addr + 1; - end - else if ( CLE && ~ALE && Data==8'hFF ) - set_reset; - end - - A2_ERS : - begin - if ( ALE ) - begin - Blck = Blck + (AddrCom*12'h100); - WrPage = Page + Blck*(BlockSize+1); - cnt_addr = cnt_addr + 1; - end - else if ( CLE && ~ALE && Data==8'hFF ) - set_reset; - end - - A3_ERS : - begin - if ( CLE && ~ALE && Data==8'hFF ) - set_reset; - else if ( CLE && ~ALE && Data==8'hD0 ) - begin - if (~(WPNeg==1'b0)) - begin - for(i = Blck *(BlockSize+1) *(PageSize+1); - i < (Blck+1)*(BlockSize+1) *(PageSize+1); - i=i+1) - Mem[i] = -1; - end - if (~XTREM_ACT) - BERS_in = 1'b1; - else - XBERS_in = 1'b1; - ERS_ACT = 1'b1; - R_zd = 1'b0; - Status[6:5] = 2'b00; - end - else if ( CLE && ~ALE && XTREM_ACT && Data==8'h11 ) - begin - PRE_PROG_in = 1'b1; - PRG_ACT = 1'b1; - R_zd = 1'b0; - Status[6:5] = 2'b00; - end - else if ( CLE && ~ALE && Data==8'h71 ) - begin - STAT_M_ACT = 1'b1; - BSTATINQ_in = 1'b1; - R_zd = 1'b0; - Status[6:5] = 2'b00; - end - else if (ALE) - cnt_addr = cnt_addr + 1; - end - - BERS_EXEC : - begin - if ( CLE && ~ALE && Data==8'hFF ) - begin - BERS_in = 1'b0; - XBERS_in = 1'b0; - set_reset; - if (XTREM_ACT) - back_to_xtrem = 1'b1; - else - back_to_xtrem = 1'b0; - InvBlock[Blck] = 1; - end - else if ( CLE && ~ALE && Data==8'h70 ) - STAT_ACT = 1'b1; - end - - PGD_PREL : - begin - if (ALE) - begin - Pom_Address = AddrCom; - cnt_addr = 0; - PGD_ACT = 1'b1; - PMOVE = 1'b0; - end - else if( CLE && ~ALE && Data==8'hFF) - set_reset; - end - - A0_PGD: - begin - if (ALE) - begin - Pom_Address = (AddrCom* 12'h100) + Pom_Address; - CWrAddr = Pom_Address; - cnt_addr = cnt_addr + 1; - end - else if (CLE && ~ALE && Data==8'hFF) - set_reset; - end - - A1_PGD : - begin - if ( ALE ) - begin - Page = AddrCom; - cnt_addr = cnt_addr + 1; - end - else if (CLE && ~ALE && Data==8'hFF ) - set_reset; - end - - A2_PGD : - begin - if ( ALE ) - begin - Blck = AddrCom; - cnt_addr = cnt_addr + 1; - end - else if (CLE && ~ALE && Data==8'hFF ) - set_reset; - end - - A3_PGD : - begin - if ( ALE ) - begin - Blck = Blck + (AddrCom*12'h100); - cnt_addr = cnt_addr + 1; - BlckDup = Blck; - end - else if (CLE && ~ALE && Data==8'hFF ) - set_reset; - end - - CONF_PGD : - begin - if (CLE && ~ALE && (Data==8'h10 || Data==8'h12 || Data==8'h85)) - begin - if (~XTREM_ACT) - for (i=0; i<=PageSize; i=i+1) - CashBuffData[i] = PDBuffer[i]; - else - begin - for (i=0; i<=PageSize; i=i+1) - begin - CashBuffData[i] = PDBuffer[i]; - CashBuffData1[i] = PDBuffer1[i]; - end - end - for(i=0; i<= SegmentNum; i=i+1) - CSegForProg[i]=1'b1; - if (Data == 8'h12 && XTREM_ACT) - begin - XTR_MPRG = 1'b1; - Page =Page/2; - end - else - XTR_MPRG = 1'b0; - CWrPage = Page + Blck*(BlockSize+1); - end - if (CLE && ~ALE && (Data==8'h10 || Data==8'h12) && ~PRG_ACT) - begin - PRG_ACT = 1'b1; - if (~XTREM_ACT) - PROG_in = 1'b1; - else - begin - if (BlockMod[BlckDup]==0) - PROG_in = 1'b1; - else - XPROG_in = 1'b1; - end - ProgBlock[Blck] = 1; - firstFlag = 1'b1; - R_zd = 1'b0; - Status[5] = 1'b0; - end - else if ( CLE && ~ALE && Data==8'hFF) - set_reset; - else if (ALE) - cnt_addr = cnt_addr + 1; - end - - endcase - end - - always @(TR_out, DBSY_out,PROG_out,XPROG_out ) - begin : Func0_2 - if ((TR_out || DBSY_out || PROG_out || XPROG_out) && read && STAT_ACT) - Read_Status(Blck); - end - - //after reset, state is don't care - always @(posedge reseted) - begin: Func0_1 - if (reseted) - if (PRE) - begin - Address = 1'b0; - PageAddr= 1'b0; - PGR_ACT = 1'b1; - end - else - PGR_ACT = 1'b0; - end - - //RESET state, RSTDONE - always @(current_state, read, write, BERS_out, XBERS_out, - PROG_out, XPROG_out,TR_out,DBSY_out,RSTDONE,PROG1_out,XPROG1_out, - PROG2_out,XPROG2_out,DBSY1_out) - begin: Func1 - if (current_state == RESET) - begin - if (~back_to_xtrem) - XTREM_ACT = 1'b0; - else - XTREM_ACT = 1'b1; - if (RSTDONE) - begin - STAT_ACT = 1'b0; - ERS_ACT = 1'b0; - RD_ACT = 1'b0; - PGD_ACT = 1'b0; - PGR_ACT = 1'b1; - PRG_ACT = 1'b0; - STAT_M_ACT = 1'b0; - PMOVE = 1'b0; - XTR_MPRG = 1'b0; - R_zd = 1'b1; - Status[6:3] = 4'b1100; - Status[1:0] = 2'b00; - if (PRE) - begin - Address = 1'b0; - PageAddr= 1'b0; - PGR_ACT = 1'b1; - end - else - PGR_ACT = 1'b0; - end - end - end - - always @(current_state, read, write, BERS_out, XBERS_out, - PROG_out, XPROG_out,TR_out,DBSY_out,RSTDONE,PROG1_out,XPROG1_out, - PROG2_out,XPROG2_out,DBSY1_out) - begin: Func2_1 - if (current_state == XTREM_IDLE && ~XPROG_in) - begin - PGD_ACT = 1'b0; - XTR_MPRG = 1'b0; - end - end - - //BUFF_TR state, TR_out - always @(read, Data, AddrCom, current_state,PROG1_out,XPROG1_out,PROG2_out, - XPROG2_out, RENeg, CENeg, ALE, CLE, BERS_out,XBERS_out, PROG_out, - XPROG_out, TR_out, DBSY_out, WPNeg, PGD_ACT,DBSY1_out) - begin: Func2_2 - if (current_state == BUFF_TR && TR_out) - begin - if (PGD_ACT && ~XTREM_ACT) - for (i=0; i<=PageSize; i=i+1) - PDBuffer[i] = Mem[PageAddr*(PageSize+1)+i]; - else if (PGD_ACT && XTREM_ACT) - for (i=0; i<=PageSize; i=i+1) - begin - PDBuffer[i] = Mem[PageAddr*(PageSize+1)+i]; - PDBuffer1[i] = Mem[(PageAddr+1)*(PageSize+1)+i]; - end - R_zd = 1'b1; - Status[6:5]= 2'b11; - TR_in = 1'b0; - end - end - - always @(read, Data, AddrCom, reseted, current_state, - RENeg, CENeg, ALE, CLE, BERS_out,XBERS_out, PROG_out,XPROG_out, - DBSY_out, WPNeg, PGD_ACT,PROG1_out,XPROG1_out) - begin : Func3_1 - if(current_state==WFPD && PROG1_out) - begin - DBSY1_in = 1'b1; - CWrPage = Page + Blck*(BlockSize+1); - Status[5] = 1'b1; - end - else if(current_state==WFPPD && PROG1_out) - begin - PROG2_in = 1'b1; - PROG1_in = 1'b0; - if (WPNeg) - begin - for (j=0;j<=PageSize; j=j+1) - begin - getSegment(j,pom_seg); - if (WrBuffData[j] != -1 && - ~ProgramedFlag[WrPage*(SegmentNum+1)+pom_seg]) - begin - Mem[WrPage*(PageSize+1)+j] = WrBuffData[j]; - WrBuffData[j]=-1; - end - end - for (j=0;j<=SegmentNum; j=j+1) - ProgramedFlag[WrPage*(SegmentNum+1)+j]= SegForProg[j]; - CWrPage = Page + Blck*(BlockSize+1); - Status[5] = 1'b0; - end - end - end - - always @(read, Data, AddrCom, reseted, current_state, - RENeg, CENeg, ALE, CLE, BERS_out,XBERS_out, PROG_out,XPROG_out, - DBSY_out, WPNeg, PGD_ACT,PROG1_out,XPROG1_out) - begin : Func3_2 - if(current_state==WFPD && XPROG1_out) - begin - DBSY1_in = 1'b1; - CWrPage = Page + Blck*(BlockSize+1); - Status[5] = 1'b1; - end - else if(current_state==WFPPD && XPROG1_out) - begin - XPROG2_in = 1'b1; - XPROG1_in = 1'b0; - if (WPNeg) - begin - for (j=0;j<=PageSize; j=j+1) - begin - Page_pom = WrPage; - XgetSegment(j,pom_seg,pom_seg1); - if (WrBuffData[j] != -1 && - ~ProgramedFlag[Page_pom*(SegmentNum+1)+pom_seg] && - ~ProgramedFlag[Page_pom*(SegmentNum+1)+pom_seg1]) - begin - XTR_Pgms_data(j,WrPage); - end - end - for (j=0; j<=SegmentNum; j=j+1) - begin - ProgramedFlag[WrPage*(SegmentNum+1)+j]= SegForProg[j]; - ProgramedFlag[(WrPage+1)*(SegmentNum+1)+j]= SegForProg1[j]; - end - CWrPage = Page + Blck*(BlockSize+1); - Status[5] = 1'b0; - end - end - end - - //PGMS state,WPNeg - always @(current_state) - begin: Func4 - integer i,j,k; - if (current_state==PGMS ) - begin - if ( WPNeg && firstFlag) - begin - firstFlag = 1'b0; - for (i=0; i<=PageSize; i=i+1) - begin - WrBuffData[i] = CashBuffData[i]; - WrBuffData1[i] = CashBuffData1[i]; - end - WrPage = CWrPage; - WrAddr = CWrAddr; - for(i=0;i<=SegmentNum;i=i+1) - begin - SegForProg[i]=CSegForProg[i]; - SegForProg1[i]=CSegForProg1[i]; - end - if (~XTREM_ACT) - begin - for(i=0;i<=PageSize;i=i+1) - begin - getSegment(i,segment); - if ( CashBuffData[i] != -1 && - ProgramedFlag[CWrPage*(SegmentNum+1) + segment]== 0) - Mem[CWrPage*(PageSize+1)+i]= -1; - end - end - else if (XTR_MPRG) - begin - for (i=0;i<=PageSize;i=i+1) - begin - getSegment(i,segment); - if ( CashBuffData[i] != -1 && - ProgramedFlag[CWrPage*(SegmentNum+1) + segment]== 0) - Mem[CWrPage*(PageSize+1)+i]= -1; - end - end - else if (PGD_ACT) - begin - for (i=0;i<=PageSize;i=i+1) - begin - Page_pom = CWrPage; - XgetSegment(i,pom_seg,pom_seg1); - if (ProgramedFlag[CWrPage*(SegmentNum+1)+pom_seg] ==0 - && ProgramedFlag[CWrPage*(SegmentNum+1)+pom_seg1] ==0 - && CashBuffData[i] != -1) - Mem[CWrPage*(PageSize+1)+i]= -1; - if (ProgramedFlag[(CWrPage+1)*(SegmentNum+1)+ - pom_seg]==0 && CashBuffData1[i] != -1 && - ProgramedFlag[(CWrPage+1)*(SegmentNum+1)+ - pom_seg1]==0) - Mem[(CWrPage+1)*(PageSize+1)+i]= -1; - end - end - end - end - end - - always @(BSTATINQ_out) - begin - if (current_state == BSTAT_INQ) - begin - if (BSTATINQ_out) - begin - R_zd = 1'b1; - Status [6:5] = "11"; - BSTATINQ_in = 1'b0; - end - end - end - - //PGMS state,PROG_out - always @(posedge PROG_out) - begin: Func5_1 - if (current_state==PGMS ) - begin - PGD_ACT <= #1 1'b0; - R_zd = 1'b1; - end - end - - //PGMS state,XPROG_out - always @(posedge XPROG_out) - begin: Func5_2 - if (current_state==PGMS ) - begin - R_zd = 1'b1; - end - end - - //PGMS state,PROG2_out - always @(posedge PROG2_out) - begin: Func5_3 - if (current_state==PGMS ) - R_zd = 1'b1; - end - - //PGMS state,XPROG2_out - always @(posedge XPROG2_out) - begin: Func5_4 - if (current_state==PGMS ) - R_zd = 1'b1; - end - - //RDY_PRG state,PROG1_out - always @(posedge PROG1_out) - begin: Func5_5 - if (current_state==RDY_PRG ) - R_zd = 1'b1; - end - - //RDY_PRG state,XPROG1_out - always @(posedge XPROG1_out) - begin: Func5_6 - if (current_state==RDY_PRG ) - R_zd = 1'b1; - end - - //CBSY state, firstFlag - always @(current_state,PROG1_out,XPROG1_out,PROG2_out,XPROG2_out, - PROG_out, XPROG_out, DBSY_out, firstFlag,DBSY1_out) - begin: Func6 - if (current_state == CBSY ) - if (firstFlag) - begin - firstFlag=1'b0; - Status[6] = 1'b0; - end - end - //CBSY state, WPNeg - always @(current_state,PROG1_out,XPROG1_out,PROG2_out,XPROG2_out, - PROG_out, XPROG_out,DBSY_out, WPNeg,firstFlag,DBSY1_out) - begin: Func6_0 - if (current_state == CBSY ) - if (WPNeg && (DBSY1_out||DBSY_out)) - for( i=0; i<= PageSize; i=i+1) - if( CashBuffData[i] != -1) - Mem[CWrPage*(PageSize+1)+i]= -1; - end - - //CBSY state, DBSY_out - always @(posedge DBSY_out) - begin: Func6_1 - if (current_state == CBSY ) - begin - Status[6] = 1'b1; - R_zd = 1'b1; - DBSY_in = 1'b0; - for( i=0; i<= PageSize; i=i+1) - WrBuffData[i] = CashBuffData[i]; - WrPage = CWrPage; - WrAddr = CWrAddr; - for(i=0;i<=SegmentNum;i=i+1) - SegForProg[i]=CSegForProg[i]; - end - end - - //CBSY state, DBSY1_out - always @(posedge DBSY1_out) - begin: Func6_2 - if (current_state == CBSY ) - begin - Status[6] = 1'b1; - R_zd = 1'b1; - DBSY1_in = 1'b0; - for( i=0; i<= PageSize; i=i+1) - WrBuffData[i] = CashBuffData[i]; - WrPage = CWrPage; - WrAddr = CWrAddr; - for(i=0;i<=SegmentNum;i=i+1) - SegForProg[i]=CSegForProg[i]; - end - end - - //BERS_EXEC state BERS_out - always @(Data, AddrCom, current_state, - RENeg, CENeg, ALE, CLE, BERS_out, PROG_out, - TR_out, DBSY_out, WPNeg) - begin: Func7_0 - integer i,j,k; - if (current_state==BERS_EXEC && BERS_out) - begin - for(i = Blck *(BlockSize+1) *(PageSize+1); - i < (Blck+1)*(BlockSize+1) *(PageSize+1); - i=i+1) - Mem[i] = MaxData; - for(i = Blck *(BlockSize+1) *(SegmentNum+1); - i < (Blck+1)*(BlockSize+1) *(SegmentNum+1); - i=i+1) - ProgramedFlag[i] = 1'b0; - InvBlock[Blck] = 0; - BlockMod[Blck] = 0; - PreProgFlag[Blck] = 0; - ProgBlock[Blck] = 0; - InvBlockPgms[Blck] = 0; - BERS_in = 1'b0; - ERS_ACT = 1'b0; - R_zd = 1'b1; - Status[6:5] = 2'b11; - end - end - - //BERS_EXEC state XBERS_out - always @(Data, AddrCom, current_state, - RENeg, CENeg, ALE, CLE, XBERS_out, XPROG_out, - TR_out, DBSY_out, WPNeg) - begin: Func7_1 - integer i,j,k; - if (current_state==BERS_EXEC && XBERS_out) - begin - for(i = Blck *(BlockSize+1) *(PageSize+1); - i < (Blck+1)*(BlockSize+1) *(PageSize+1); - i=i+1) - Mem[i] = MaxData; - for(i = Blck *(BlockSize+1) *(SegmentNum+1); - i < (Blck+1)*(BlockSize+1) *(SegmentNum+1); - i=i+1) - ProgramedFlag[i] = 1'b0; - InvBlock[Blck] = 0; - BlockMod[Blck] = 1; - ProgBlock[Blck] = 0; - InvBlockPgms[Blck] = 0; - XBERS_in = 1'b0; - ERS_ACT = 1'b0; - R_zd = 1'b1; - Status[6:5] = 2'b11; - end - end - - always @(current_state) - begin: Func8_1 - if (current_state == IDLE | current_state == XTREM_IDLE | - current_state == RD) - begin - back_to_xtrem = 1'b0; - end - else if (current_state == PRE_PRG ) - begin - back_to_xtrem = 1'b1; - end - end - - /////////////////////////////////////////////////////////////////////////// - //FlagGeneration - /////////////////////////////////////////////////////////////////////////// - always @(posedge DBSY_out) - begin - PRG_ACT = 1'b1; - PROG1_in = ~XTREM_ACT; - XPROG1_in = XTREM_ACT; - Status[6:5] = 2'b10; - end - always @(posedge DBSY1_out) - begin - PRG_ACT = 1'b1; - PROG1_in = ~XTREM_ACT; - XPROG1_in = XTREM_ACT; - Status[6:5] = 2'b10; - end - - always @(posedge PROG_out or posedge XPROG_out or posedge PROG1_out or - posedge XPROG1_out or posedge PROG2_out or posedge XPROG2_out) - begin - if( current_state==PGMS || current_state==PREL_PRG - || current_state==A0_PRG || current_state==A1_PRG - || current_state==A2_PRG || current_state==DATA_PRG - || current_state==PGMS_CAC || current_state==A0_PRG_CAC - || current_state==WFPD || current_state==RDY_PRG - || current_state==CBSY || current_state==UNKNOWN) - begin - PRG_ACT = 1'b0; - Status[5] = 1'b1; - PROG_in = 1'b0; - XPROG_in = 1'b0; - PROG1_in = 1'b0; - XPROG1_in = 1'b0; - PROG2_in = 1'b0; - XPROG2_in = 1'b0; - if( WPNeg && ~XTREM_ACT && InvBlock[WrPage/(BlockSize+1)] == 0) - begin - for( j=0; j<=PageSize; j=j+1) - begin - getSegment(j,pom_seg); - if( WrBuffData[j] != -1 && - ProgramedFlag[WrPage*(SegmentNum+1) + pom_seg]== 0 ) - begin - Mem[WrPage*(PageSize+1)+j]= WrBuffData[j]; - WrBuffData[j]=-1; - end - end - for( j=0; j<=SegmentNum; j=j+1) - ProgramedFlag[WrPage*(SegmentNum+1) + j] = SegForProg[j]; - end - else if (WPNeg && XTREM_ACT && InvBlock[WrPage/(BlockSize+1)] == 0) - begin - for (j=0; j<=PageSize; j=j+1) - begin - Page_pom = WrPage; - XgetSegment(j,pom_seg,pom_seg1); - if (~PGD_ACT) - begin - if (ProgramedFlag[Page_pom*(SegmentNum+1)+pom_seg] ==0 && - ProgramedFlag[Page_pom*(SegmentNum+1)+pom_seg1] ==0 && - WrBuffData[j] != -1) - XTR_Pgms_data(j,WrPage); - end - else if (~XTR_MPRG) - begin - Page_pom = WrPage; - if (ProgramedFlag[Page_pom*(SegmentNum+1)+pom_seg] ==0 && - ProgramedFlag[Page_pom*(SegmentNum+1)+pom_seg1] ==0 && - WrBuffData[j] != -1) - Mem[WrPage*(PageSize+1)+j]= WrBuffData[j]; - if (ProgramedFlag[(Page_pom+1)*(SegmentNum+1)+pom_seg]==0 - &&ProgramedFlag[(Page_pom+1)*(SegmentNum+1)+pom_seg1]==0 - && WrBuffData[j] != -1) - Mem[(WrPage+1)*(PageSize+1)+j]= WrBuffData1[j]; - end - else - begin - if (ProgramedFlag[Page_pom*(SegmentNum+1)+pom_seg] == 0) - XTR_MPrg_proc; - end - end - for( j=0; j<=SegmentNum; j=j+1) - ProgramedFlag[WrPage*(SegmentNum+1) + j] = SegForProg[j]; - if (~XTR_MPRG) - for( j=0; j<=SegmentNum; j=j+1) - ProgramedFlag[(WrPage+1)*(SegmentNum+1) + j] = - SegForProg1[j]; - end - end - end - - always @(posedge PRE_PROG_out) - begin - if (WPNeg && XTREM_ACT) - begin - if (InvBlock[WrPage/(BlockSize+1)] == 0 && - InvBlockPgms[WrPage/(BlockSize+1)] == 0) - begin - XTR_PrePrg_proc(WrPage/(BlockSize+1)); - PreProgFlag[WrPage/(BlockSize+1)] = 1; - end - end - Status[5] = 1'b1; - R_zd = 1'b1; - Status[6:5] = 2'b11; - BlockMod[Blck] = 1'b1; - PRE_PROG_in = 1'b0; - PRG_ACT = 1'b0; - end - - always @(negedge write) - begin - if( current_state==PGMS || current_state==PREL_PRG - || current_state==A0_PRG || current_state==A1_PRG - || current_state==A2_PRG || current_state==DATA_PRG - || current_state==PGMS_CAC || current_state==A0_PRG_CAC - || current_state==WFPD || current_state==CBSY - || current_state==RDY_PRG || current_state==PRE_PRG - || current_state==UNKNOWN) - begin - if(CLE && ~ALE && PRG_ACT && Data==8'hFF) - begin - PROG_in = 1'b0; - XPROG_in = 1'b0; - PROG1_in = 1'b0; - XPROG1_in = 1'b0; - PROG2_in = 1'b0; - XPROG2_in = 1'b0; - end - else if (CLE && ~ALE && Data==8'hFF) - PRE_PROG_in = 1'b0; - end - end - - //Output Disable Control - always @(read, write, Data, AddrCom, reseted, current_state, - RENeg, CENeg, ALE, CLE, BERS_out, PROG_out, TR_out, - DBSY_out, RSTDONE, WPNeg ) - begin - if (RENeg || CENeg) - DOut_zd = 8'bZ; - end - - task Read_Data; - inout [31:0] Addr; - inout [31:0] Page; - inout [31:0] Blck; - reg [7:0] data_tmp; - reg [7:0] data_tmp1; - integer i; - integer j; - begin - if (~XTREM_ACT) - begin - if (Mem[Page*(PageSize+1)+Addr] != -1) - DOut_zd = Mem[Page*(PageSize+1)+Addr]; - else - DOut_zd = 8'bx; - if (Addr != PageSize) - Addr = Addr+1; - end - else - begin - if (Addr*2 < PageSize) - begin - if (Mem[Page*(PageSize+1)+(Addr*2)] != -1 && - Mem[Page*(PageSize+1)+(Addr*2+1)] != -1) - begin - data_tmp = Mem[Page*(PageSize+1)+(Addr*2+1)]; - data_tmp1= Mem[Page*(PageSize+1)+(Addr*2)]; - i = 0; - j = 0; - while (i <= 7) - begin - if ((i % 2) !=0) - begin - DOut_zd[j] = data_tmp1[i]; - DOut_zd[j+4] = data_tmp[i]; - j = j + 1; - end - i = i + 1; - end - end - else - DOut_zd = 8'bx; - end - else - begin - if (Mem[(Page+1)*(PageSize+1)+(Addr*2- PageSize)] != -1 && - Mem[(Page+1)*(PageSize+1)+(Addr*2-(PageSize+1))] != -1) - begin - data_tmp = Mem[(Page+1)*(PageSize+1)+(Addr*2- PageSize)]; - data_tmp1= Mem[(Page+1)*(PageSize+1)+(Addr*2-(PageSize+1))]; - i = 0; - j = 0; - while (i <= 7) - begin - if ((i % 2) !=0) - begin - DOut_zd[j] = data_tmp1[i]; - DOut_zd[j+4] =data_tmp[i]; - j = j + 1; - end - i = i + 1; - end - end - else - DOut_zd = 8'bx; - end - if (Addr != PageSize) - Addr = Addr+1; - end - end - endtask - - task Read_Status; - input [31:0] Blck; - begin - if ((PreProgFlag[Blck] == 1 && ProgBlock[Blck] == 0) || - BlockMod[Blck] == 1) - Status[2] = 1'b1; - else - Status[2] = 1'b0; - DOut_zd = Status; - end - endtask - - task Read_StatMode; - input [31:0] Blck; - begin - DOut_zd[7:1] = 0; - if ((PreProgFlag[Blck] == 1 && ProgBlock[Blck] == 0) || - BlockMod[Blck] == 1) - begin - DOut_zd[7:1] = 0; - DOut_zd[0] = 1'b1; - end - else - DOut_zd[0] = 1'b0; - end - endtask - - task getSegment; - input [31:0] paddress; - output [31:0] seg; - integer i; - begin - paddress = paddress % (PageSize + 1); - for (i=0; i<=SegmentNum; i=i+1) - if(paddress >= ssa[i] && paddress <= sea[i]) - seg = i; - end - endtask - - task XgetSegment; - input [31:0] paddress; - output [31:0] j; - output [31:0] k; - integer addr; - integer i; - begin - if (~PGD_ACT) - if (paddress*2 < PageSize) - addr = paddress*2; - else - begin - addr = paddress*2 - PageSize; - Page_pom = Page_pom + 1; - end - else - addr = paddress; - for (i=0; i<= SegmentNum; i=i+1) - if (addr >= ssa[i] && addr <= sea[i]) - j = i; - if ((j % 2) ==0) - k = j + 1; - else - k = j - 1; - end - endtask - - task XTR_Pgms_init; - input [31:0] Page; - integer i; - begin - if (WPNeg) - for(i=0; i<=PageSize; i=i+1) - begin - if (CashBuffData[i] != -1 && (i*2 < PageSize)) - begin - Mem[(Page)*(PageSize+1)+(i*2)] = - 1; - Mem[(Page)*(PageSize+1)+(i*2+1)] = - 1; - end - else if (CashBuffData[i] != -1 && (i*2 > PageSize)) - begin - Mem[(Page+1)*(PageSize+1)+(i*2- PageSize)] = - 1; - Mem[(Page+1)*(PageSize+1)+(i*2-(PageSize+1))] = - 1; - end - end - end - endtask - - task XTR_Pgms_data; - input [31:0] i; - input [31:0] Page; - reg [7:0] data_tmp; - reg [7:0] data_tmp1; - reg [7:0] data_reg; - integer k; - integer j; - begin - k = 0; - if (WrBuffData[i] != -1 && (i*2 < PageSize)) - begin - data_tmp = Mem[(Page)*(PageSize+1)+(i*2)]; - data_tmp1 = Mem[(Page)*(PageSize+1)+(i*2+1)]; - data_reg = WrBuffData[i]; - for (j=0; j<=7; j=j+1) - begin - if ((j % 2) !=0) - begin - data_tmp[j] = data_reg[k]; - data_tmp1[j] = data_reg[k+4]; - k = k + 1; - end - else - begin - data_tmp[j] = data_tmp[j]; - data_tmp1[j] = data_tmp1[j]; - end - end - Mem[(Page)*(PageSize+1)+(i*2)] = data_tmp; - Mem[(Page)*(PageSize+1)+(i*2+1)] = data_tmp1; - end - else if (WrBuffData[i] != -1 && (i*2 > PageSize)) - begin - data_tmp = Mem[(Page+1)*(PageSize+1)+(i*2- (PageSize+1))]; - data_tmp1 = Mem[(Page+1)*(PageSize+1)+(i*2 - PageSize)]; - data_reg = WrBuffData[i]; - for (j=0; j<=7; j=j+1) - begin - if ((j % 2) !=0) - begin - data_tmp[j] = data_reg[k]; - data_tmp1[j] = data_reg[k+4]; - k = k + 1; - end - else - begin - data_tmp[j] = data_tmp[j]; - data_tmp1[j] = data_tmp1[j]; - end - end - Mem[(Page+1)*(PageSize+1)+(i*2- PageSize)] = data_tmp1; - Mem[(Page+1)*(PageSize+1)+(i*2-(PageSize+1))] = data_tmp; - end - end - endtask - - task XTR_Buffdata; - input [31:0] address; - input [31:0] Data; - reg [7:0] data_tmp; - reg [7:0] data_tmp1; - reg [7:0] data_input; - integer k; - integer j; - integer inv; - begin - inv = 0; - if (address*2 < PageSize && CashBuffData[address*2] != -1 && - CashBuffData[address*2+1] != -1) - begin - data_tmp = CashBuffData[address*2]; - data_tmp1 = CashBuffData[address*2+1]; - inv = 1; - end - else if (address*2 > PageSize && - CashBuffData1[address*2- (PageSize+1)] != -1 && - CashBuffData1[address*2- PageSize] != -1) - begin - data_tmp = CashBuffData1[address*2- (PageSize+1)]; - data_tmp1 = CashBuffData1[address*2- PageSize]; - inv = 1; - end - - if (inv == 1) - begin - k = 0; - j = 0; - data_input = Data; - while (j <= 7) - begin - if ((j % 2) !=0) - begin - data_tmp[j]= data_input[k]; - data_tmp1[j]= data_input[k+4]; - k = k + 1; - end - j = j + 1; - end - if (address*2 < PageSize) - begin - CashBuffData[address*2] = data_tmp; - CashBuffData[address*2+1] = data_tmp1; - end - else - begin - CashBuffData1[address*2- PageSize] = data_tmp1; - CashBuffData1[address*2- (PageSize+1)] = data_tmp; - end - end - end - endtask - - task XTR_PrePrg_proc; - input [31:0] Blck; - reg [7:0] data_prog; - integer i; - integer k; - begin - for (i=Blck * (BlockSize+1)*(PageSize+1); - i<=(Blck+1)*(BlockSize+1)*(PageSize+1); - i=i+1) - begin - data_prog = Mem[i]; - for (k=0; k<=7; k=k+1) - if ((k % 2) == 0) - data_prog[k] = 1'b1; - Mem[i] = data_prog; - end - end - endtask - - task XTR_MPrg_proc; - reg [7:0] data_tmp; - reg [7:0] data_tmp1; - reg [7:0] data_tmp2; - integer k; - integer i; - integer inv; - begin - inv = 0; - k = 0; - i = 0; - if (j*2 < PageSize && WrBuffData[j*2+1] != -1 && - WrBuffData[j*2] != -1) - begin - data_tmp = WrBuffData[j*2+1]; - data_tmp1 = WrBuffData[j*2]; - inv = 1; - end - else if (j*2 > PageSize && WrBuffData1[j*2 - PageSize] != -1 && - WrBuffData1[j*2 - (PageSize+1)] != -1) - begin - data_tmp = WrBuffData1[j*2 - PageSize]; - data_tmp1 = WrBuffData1[j*2- (PageSize+1)]; - inv = 1; - end - if (inv == 1) - begin - while (i <= 7) - begin - if ((i % 2) !=0) - begin - data_tmp2[k] = data_tmp1[i]; - data_tmp2[k+4] = data_tmp[i]; - k = k + 1; - end - i = i + 1; - end - Mem[WrPage*(PageSize+1)+j] = data_tmp2; - end - end - endtask - - task set_reset; - begin - STAT_ACT = 1'b0; - RSTSTART = 1'b1; - RSTSTART <= #1 1'b0; - R_zd = 1'b0; - end - endtask - - reg BuffInR; - wire BuffOutR; - - BUFFER BUFR (BuffOutR , BuffInR); - - initial - begin - BuffInR = 1'b1; - end - - always @(posedge BuffOutR) - begin - WER_01 = $time; - end - reg BuffInRE, BuffInCE, BuffInALE, BuffInCLE; - wire BuffOutRE, BuffOutCE, BuffOutALE, BuffOutCLE; - - BUFFER BUFRENeg (BuffOutRE, BuffInRE); - BUFFER BUFCENeg (BuffOutCE, BuffInCE); - BUFFER BUFALE (BuffOutALE, BuffInALE); - BUFFER BUFCLE (BuffOutCLE, BuffInCLE); - - initial - begin - BuffInRE = 1'b1; - BuffInCE = 1'b1; - BuffInALE = 1'b1; - BuffInCLE = 1'b1; - end - - time CEDQ_t, REDQ_t, ALEDQ_t, CLEDQ_t; - time REDQ_01, CEDQ_01, ALEDQ_01, CLEDQ_01; - time CENeg_event, RENeg_event, ALE_event, CLE_event; - always @(posedge BuffOutRE) - begin - REDQ_01 = $time; - end - always @(posedge BuffOutCE) - begin - CEDQ_01 = $time; - end - always @(BuffOutALE) - begin - ALEDQ_01 = $time; - end - always @(BuffOutCLE) - begin - CLEDQ_01 = $time; - end - - always @(negedge CENeg) - begin - CENeg_event = $time; - end - - always @(negedge RENeg) - begin - RENeg_event = $time; - end - - always @(negedge ALE) - begin - ALE_event = $time; - end - always @(negedge CLE) - begin - CLE_event = $time; - end - - always @(DOut_zd) - begin : OutputGen - time time_t; - if (DOut_zd[0] !== 1'bz) - begin - CEDQ_t = CENeg_event + CEDQ_01; - REDQ_t = RENeg_event + REDQ_01; - tdp_CE = ((CEDQ_t >= REDQ_t) && ( CEDQ_t > $time)); - tdp_RE = ((REDQ_t > CEDQ_t) && ( REDQ_t > $time)); - DOut_pass = #5 DOut_zd; - end - end - - always @(DOut_zd) - begin - if (DOut_zd[0] === 1'bz) - begin - disable OutputGen; - tdp_CE = 1'b1; - tdp_RE= 1'b1; - DOut_pass = #5 DOut_zd; - end - end - -endmodule - -module BUFFER (OUT,IN); - input IN; - output OUT; - buf ( OUT, IN); -endmodule diff --git a/resources/soc/simu/testbench/uart_dev.v b/resources/soc/simu/testbench/uart_dev.v deleted file mode 100644 index 883b47b..0000000 --- a/resources/soc/simu/testbench/uart_dev.v +++ /dev/null @@ -1,527 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -`timescale 1ns/10ps - -`define V_UART_FIFO_COUNTER_W 5 -`define V_UART_FIFO_WIDTH 8 -`define V_UART_LC_PE 3 -`define V_UART_LC_EP 4 -`define V_UART_LC_SP 5 -`define V_UART_LC_SB 2 -`define V_UART_LC_BITS 1:0 -`define V_UART_LC_BC 6 -`define V_UART_FIFO_DEPTH 16 -`define V_UART_FIFO_POINTER_W 4 - -module uart_dev -( - input wire clk, - input wire rst_n, - input wire rx, - output wire tx -); -parameter uart_number=0; -parameter STRLEN = 80; - - wire [7:0] data; - wire hwrite; - wire hready; - wire [1:0] htrans; - wire [31:0] haddr; - wire hclk; - wire apb_clk; - wire gpio; - - assign data = 8'h0; - assign hwrite = 1'b0; - assign hready = 1'b0; - assign htrans = 2'b0; - assign haddr = 32'h0; - assign hclk = clk; - assign apb_clk = clk; - assign gpio = 1'b1; - - wire uart_beh_reset; - - reg [7:0] buffer[STRLEN:0]; - wire [8*STRLEN-1:0] outbuf; - - reg [7:0] byte_in; - reg [7:0] ptr; - integer i; - wire tx_mid; - assign #1 tx= tx_mid; - assign uart_beh_reset = !rst_n; - initial - begin - while(rx !== 1'b1) @(rx); - forever begin - byte_in = 8'h20; - while(rx != 1'b0) @(rx); - repeat(8) @(posedge clk); - for ( i=0; i<8; i=i+1 ) begin - repeat(16) @(posedge clk); - byte_in[i] = rx; - end - repeat(16) @(posedge clk); - push(byte_in); - end - end - - reg [31:0] haddr_d1; - reg hwrite_d1; - always @(posedge hclk) begin - haddr_d1 <= haddr; - hwrite_d1<= hwrite && hready && htrans[1]; - if (haddr_d1 == 32'h1f00_03f8 && hwrite_d1) begin - push(data); - end - end - - initial #100 - begin:init_buffer - for (ptr = 8'h00; ptr < STRLEN; ptr = ptr + 1) - begin - buffer[ptr] = 8'h20; - end - ptr = 8'h00; - end - - assign outbuf[639:0] = { buffer[0], buffer[1], buffer[2], buffer[3], buffer[4], buffer[5], buffer[6], buffer[7], - buffer[8], buffer[9], buffer[10],buffer[11],buffer[12],buffer[13],buffer[14],buffer[15], - buffer[16],buffer[17],buffer[18],buffer[19],buffer[20],buffer[21],buffer[22],buffer[23], - buffer[24],buffer[25],buffer[26],buffer[27],buffer[28],buffer[29],buffer[30],buffer[31], - buffer[32],buffer[33],buffer[34],buffer[35],buffer[36],buffer[37],buffer[38],buffer[39], - buffer[40],buffer[41],buffer[42],buffer[43],buffer[44],buffer[45],buffer[46],buffer[47], - buffer[48],buffer[49],buffer[50],buffer[51],buffer[52],buffer[53],buffer[54],buffer[55], - buffer[56],buffer[57],buffer[58],buffer[59],buffer[60],buffer[61],buffer[62],buffer[63], - buffer[64],buffer[65],buffer[66],buffer[67],buffer[68],buffer[69],buffer[70],buffer[71], - buffer[72],buffer[73],buffer[74],buffer[75],buffer[76],buffer[77],buffer[78],buffer[79]}; - - - task push; - input [7:0] data; - begin - buffer[ptr] = (data[7:0]==8'h0D)? 8'h0A : data[7:0]; - ptr = ptr + 1; - if (data[7:0] == 8'h0A || data[7:0] == 8'h0D) - begin - print; - ptr = 8'h00; - end - else if (ptr == STRLEN) - begin - print; - ptr = 8'h00; - end - end - endtask - - task print; - begin - $display("[%t]:[uart%1x]: %s", $time, uart_number,outbuf); - if (outbuf[639:576] == "GouSheng") $finish; - for (ptr = 8'h00; ptr < STRLEN; ptr = ptr + 1) - begin - buffer[ptr] = 8'h20; - end - end - endtask - - reg uart_push; - reg [7:0] uart_tx_data; - wire [2:0] uart_tx_state; - - initial - begin - begin - #1000000; - // #250000; - wait(gpio); - if (uart_number == 1) #200000; - //$display("[%t]:[uart%1x_output]: SEND STRING \"d4a000000010 \"", $time,uart_number); - uart_send_multiple("d4a000000010 ", 32'd13); - // uart_send_multiple("gb", 32'd2); - end - end - - uart_transmitter_v ut( .clk (apb_clk ), - .wb_rst_i (uart_beh_reset), - .lcr (8'h3 ), - .tf_push (uart_push ), - .wb_dat_i (uart_tx_data ), - .enable (1'b1 ), - .stx_pad_o (tx_mid ), - .tstate (uart_tx_state ), - .tf_count ( ), - .tx_reset (uart_beh_reset), - .lsr_mask (1'b0 ) - ); - - task uart_send_multiple; - input [8*80-1: 0] uart_string; - input [31:0] len; - integer send_multi_i; - begin - for (send_multi_i=len-1; send_multi_i >=0; send_multi_i = send_multi_i-1) begin - uart_send({uart_string[send_multi_i*8 + 7], - uart_string[send_multi_i*8 + 6], - uart_string[send_multi_i*8 + 5], - uart_string[send_multi_i*8 + 4], - uart_string[send_multi_i*8 + 3], - uart_string[send_multi_i*8 + 2], - uart_string[send_multi_i*8 + 1], - uart_string[send_multi_i*8 + 0]}); - end - end - endtask - task uart_send; - input [7:0] data; - begin - uart_tx_data = data; - @(posedge clk); - uart_push = 1'b1; - @(posedge clk); - uart_push = 1'b0; - repeat (3) @(posedge clk); - while(uart_tx_state != 3'b001) - @uart_tx_state; - end - endtask - - -endmodule - -module uart_transmitter_v (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask); - -input clk; -input wb_rst_i; -input [7:0] lcr; -input tf_push; -input [7:0] wb_dat_i; -input enable; -input tx_reset; -input lsr_mask; -output stx_pad_o; -output [2:0] tstate; -output [`V_UART_FIFO_COUNTER_W-1:0] tf_count; - -reg [2:0] tstate; -reg [4:0] counter; -reg [2:0] bit_counter; -reg [6:0] shift_out; -reg stx_o_tmp; -reg parity_xor; -reg tf_pop; -reg bit_out; - -wire [`V_UART_FIFO_WIDTH-1:0] tf_data_in; -wire [`V_UART_FIFO_WIDTH-1:0] tf_data_out; -wire tf_push; -wire tf_overrun; -wire [`V_UART_FIFO_COUNTER_W-1:0]tf_count; - -assign tf_data_in = wb_dat_i; - -uart_tfifo_v fifo_tx( - .clk (clk ), - .wb_rst_i (wb_rst_i ), - .data_in (tf_data_in ), - .data_out (tf_data_out), - .push (tf_push ), - .pop (tf_pop ), - .overrun (tf_overrun ), - .count (tf_count ), - .fifo_reset (tx_reset ), - .reset_status(lsr_mask ) -); - -parameter s_idle = 3'd0; -parameter s_send_start = 3'd1; -parameter s_send_byte = 3'd2; -parameter s_send_parity = 3'd3; -parameter s_send_stop = 3'd4; -parameter s_pop_byte = 3'd5; - -always @(posedge clk ) -begin - if (wb_rst_i) - begin - tstate <= s_idle; - stx_o_tmp <= 1'b1; - counter <= 5'b0; - shift_out <= 7'b0; - bit_out <= 1'b0; - parity_xor <= 1'b0; - tf_pop <= 1'b0; - bit_counter <= 3'b0; - end - else - if (enable) - begin - case (tstate) - s_idle :if (~|tf_count) - begin - tstate <= s_idle; - stx_o_tmp <= 1'b1; - end - else begin - tf_pop <= 1'b0; - stx_o_tmp <= 1'b1; - tstate <= s_pop_byte; - end - s_pop_byte : begin - tf_pop <= 1'b1; - case (lcr[1:0]) - 2'b00 : begin - bit_counter <= 3'b100; - parity_xor <= ^tf_data_out[4:0]; - end - 2'b01 : begin - bit_counter <= 3'b101; - parity_xor <= ^tf_data_out[5:0]; - end - 2'b10 : begin - bit_counter <= 3'b110; - parity_xor <= ^tf_data_out[6:0]; - end - 2'b11 : begin - bit_counter <= 3'b111; - parity_xor <= ^tf_data_out[7:0]; - end - endcase - {shift_out[6:0], bit_out} <= tf_data_out; - tstate <= s_send_start; - end - s_send_start : begin - tf_pop <= 1'b0; - if (~|counter) - counter <= 5'b01111; - else if (counter == 5'b00001) - begin - counter <= 0; - tstate <= s_send_byte; - end - else - counter <= counter - 1'b1; - stx_o_tmp <= 1'b0; - end - s_send_byte : begin - if (~|counter) - counter <= 5'b01111; - else if (counter == 5'b00001) - begin - if (bit_counter > 3'b0) begin - bit_counter <= bit_counter - 1'b1; - {shift_out[5:0],bit_out } <= {shift_out[6:1], shift_out[0]}; - tstate <= s_send_byte; - end - else - if (~lcr[`V_UART_LC_PE]) begin - tstate <= s_send_stop; - end - else begin - case ({lcr[`V_UART_LC_EP],lcr[`V_UART_LC_SP]}) - 2'b00: bit_out <= ~parity_xor; - 2'b01: bit_out <= 1'b1; - 2'b10: bit_out <= parity_xor; - 2'b11: bit_out <= 1'b0; - endcase - tstate <= s_send_parity; - end - counter <= 0; - end - else counter <= counter - 1'b1; - stx_o_tmp <= bit_out; - end - s_send_parity : begin - if (~|counter) counter <= 5'b01111; - else if (counter == 5'b00001) begin - counter <= 4'b0; - tstate <= s_send_stop; - end - else counter <= counter - 1'b1; - stx_o_tmp <= bit_out; - end - s_send_stop : begin - if (~|counter) begin - casex ({lcr[`V_UART_LC_SB],lcr[`V_UART_LC_BITS]}) - 3'b0xx: counter <= 5'b01101; - 3'b100: counter <= 5'b10101; - default: counter <= 5'b11101; - endcase - end - else if (counter == 5'b00001) begin - counter <= 0; - tstate <= s_idle; - end - else counter <= counter - 1'b1; - stx_o_tmp <= 1'b1; - end - default : - tstate <= s_idle; - endcase - end - else tf_pop <= 1'b0; -end - -assign stx_pad_o = lcr[`V_UART_LC_BC] ? 1'b0 : stx_o_tmp; - -endmodule - -module uart_tfifo_v (clk, - wb_rst_i, data_in, data_out, - push, - pop, - - overrun, - count, - fifo_reset, - reset_status -); - - -parameter fifo_width = `V_UART_FIFO_WIDTH; -parameter fifo_depth = `V_UART_FIFO_DEPTH; -parameter fifo_pointer_w = `V_UART_FIFO_POINTER_W; -parameter fifo_counter_w = `V_UART_FIFO_COUNTER_W; - -input clk; -input wb_rst_i; -input push; -input pop; -input [fifo_width-1:0] data_in; -input fifo_reset; -input reset_status; - -output [fifo_width-1:0] data_out; -output overrun; -output [fifo_counter_w-1:0] count; - -wire [fifo_width-1:0] data_out; - -reg [fifo_pointer_w-1:0] top; -reg [fifo_pointer_w-1:0] bottom; - -reg [fifo_counter_w-1:0] count; -reg overrun; -wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1; - -raminfr_v #(fifo_pointer_w,fifo_width,fifo_depth) tfifo (.clk(clk), - .we(push), - .a(top), - .dpra(bottom), - .di(data_in), - .dpo(data_out) -); - - -always @(posedge clk) -begin - if (wb_rst_i) - begin - top <= 0; - bottom <= 1'b0; - count <= 0; - end - else - if (fifo_reset) begin - top <= 0; - bottom <= 1'b0; - count <= 0; - end - else - begin - case ({push, pop}) - 2'b10 : if (count0) - begin - bottom <= bottom + 1'b1; - count <= count - 1'b1; - end - 2'b11 : begin - bottom <= bottom + 1'b1; - top <= top_plus_1; - end - default: ; - endcase - end -end - -always @(posedge clk) -begin - if (wb_rst_i) - overrun <= 1'b0; - else - if(fifo_reset | reset_status) - overrun <= 1'b0; - else - if(push & (count==fifo_depth)) - overrun <= 1'b1; -end - -endmodule - -module raminfr_v(clk, we, a, dpra, di, dpo); - -parameter addr_width = 4; -parameter data_width = 8; -parameter depth = 16; - -input clk; -input we; -input [addr_width-1:0] a; -input [addr_width-1:0] dpra; -input [data_width-1:0] di; -output [data_width-1:0] dpo; -reg [data_width-1:0] ram [depth-1:0]; - -wire [data_width-1:0] di; -wire [addr_width-1:0] a; -wire [addr_width-1:0] dpra; - -always @(posedge clk) begin - if (we) - ram[a] <= di; -end -reg [data_width-1:0] dpo; - -always @(posedge clk) - dpo <= ram[dpra]; - -endmodule diff --git a/resources/soc/simu/testbench/vmac/mac2ahb_package.v b/resources/soc/simu/testbench/vmac/mac2ahb_package.v deleted file mode 100644 index e108e52..0000000 --- a/resources/soc/simu/testbench/vmac/mac2ahb_package.v +++ /dev/null @@ -1,98 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - - // HTRANS states - parameter [1:0] IDLE = 0; - parameter [1:0] NONSEQ = 1; - parameter [1:0] SEQ = 2; - parameter [1:0] HTRANS_IDLE = 2'b00; - parameter [1:0] HTRANS_BUSY = 2'b01; - parameter [1:0] HTRANS_NONSEQ = 2'b10; - parameter [1:0] HTRANS_SEQ = 2'b11; - - // HBURST states - parameter SINGLE = 1'b0; - parameter INCR = 1'b1; - parameter [2:0] HBURST_SINGLE = 3'b000; - parameter [2:0] HBURST_INCR = 3'b001; - - // HSIZE states - parameter [2:0] HSIZE8BIT = 0; - parameter [2:0] HSIZE16BIT = 1; - parameter [2:0] HSIZE32BIT = 2; - parameter [2:0] HSIZE64BIT = 3; - parameter [2:0] HSIZE256BIT = 4; - parameter [2:0] HSIZE512BIT = 5; - parameter [2:0] HSIZE1024BIT = 6; - parameter [2:0] UNSUPPORTED = 7; - - parameter [2:0] HSIZE_8BIT = 3'b000; - parameter [2:0] HSIZE_16BIT = 3'b001; - parameter [2:0] HSIZE_32BIT = 3'b010; - parameter [2:0] HSIZE_64BIT = 3'b011; - parameter [2:0] HSIZE_128BIT = 3'b100; - parameter [2:0] HSIZE_256BIT = 3'b101; - parameter [2:0] HSIZE_512BIT = 3'b110; - parameter [2:0] HSIZE_1024BIT = 3'b111; - - // HRESP states - parameter [1:0] OKAY = 0; - parameter [1:0] ERROR = 1; - parameter [1:0] RETRY = 2; - parameter [1:0] SPLIT = 3; - parameter [1:0] HRESP_OKAY = 2'b00; - parameter [1:0] HRESP_ERROR = 2'b01; - parameter [1:0] HRESP_RETRY = 2'b10; - parameter [1:0] HRESP_SPLIT = 2'b11; - - // HPROT subvalue - parameter HPROT_0_OPCODEFETCH = 1'b0; - parameter HPROT_0_DATAACCESS = 1'b1; - parameter HPROT_1_USERACCESS = 1'b0; - parameter HPROT_1_PRIVILAGEDACCESS = 1'b1; - parameter HPROT_2_NOTBUFFERABLE = 1'b0; - parameter HPROT_2_BUFFERABLE = 1'b1; - parameter HPROT_3_NOTCACHEABLE = 1'b0; - parameter HPROT_3_CACHEABLE = 1'b1; - - // HPROT default value - parameter [3:0] HPROT_MACPROTECTIONCONTROL = {HPROT_3_NOTCACHEABLE, - HPROT_2_NOTBUFFERABLE, - HPROT_1_USERACCESS, - HPROT_0_DATAACCESS}; - - // MACDATA2AHB FSM states - parameter [1:0] AHBM_ADDR = 0; - parameter [1:0] AHBM_ADDRDATA = 1; - parameter [1:0] AHBM_IDLE = 2; - parameter [1:0] AHBM_DATA = 3; diff --git a/resources/soc/simu/testbench/vmac/mac_ram.v b/resources/soc/simu/testbench/vmac/mac_ram.v deleted file mode 100644 index c388776..0000000 --- a/resources/soc/simu/testbench/vmac/mac_ram.v +++ /dev/null @@ -1,989 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -module RF2_64x16 ( - QA, - AA, - CLKA, - CENA, - AB, - DB, - CLKB, - CENB -); - parameter BITS = 16; - parameter word_depth = 64; - parameter addr_width = 6; - output [15:0] QA; - input [5:0] AA; - input CLKA; - input CENA; - input [5:0] AB; - input [15:0] DB; - input CLKB; - input CENB; - reg [15:0] QA; - - reg [BITS-1:0] mem [word_depth-1:0]; - - not (NOT_CENA, CENA); - always @ ( posedge CLKA ) if ( NOT_CENA ) QA<=mem[AA]; - - not (NOT_CENB, CENB); - always @ ( posedge CLKB ) if ( NOT_CENB ) mem[AB]<=DB; - -endmodule - -module RF2_512x32 ( - QA, - AA, - CLKA, - CENA, - AB, - DB, - CLKB, - CENB -); - parameter BITS = 32; - parameter word_depth = 512; - parameter addr_width = 9; - parameter wordx = {BITS{1'bx}}; - parameter addrx = {addr_width{1'bx}}; - - output [31:0] QA; - input [8:0] AA; - input CLKA; - input CENA; - input [8:0] AB; - input [31:0] DB; - input CLKB; - input CENB; - - reg [BITS-1:0] mem [word_depth-1:0]; - reg NOT_CONTA; - reg NOT_CONTB; - - reg NOT_CENA; - reg NOT_CENB; - - reg NOT_AA0; - reg NOT_AA1; - reg NOT_AA2; - reg NOT_AA3; - reg NOT_AA4; - reg NOT_AA5; - reg NOT_AA6; - reg NOT_AA7; - reg NOT_AA8; - reg [addr_width-1:0] NOT_AA; - reg NOT_AB0; - reg NOT_AB1; - reg NOT_AB2; - reg NOT_AB3; - reg NOT_AB4; - reg NOT_AB5; - reg NOT_AB6; - reg NOT_AB7; - reg NOT_AB8; - reg [addr_width-1:0] NOT_AB; - reg NOT_DB0; - reg NOT_DB1; - reg NOT_DB2; - reg NOT_DB3; - reg NOT_DB4; - reg NOT_DB5; - reg NOT_DB6; - reg NOT_DB7; - reg NOT_DB8; - reg NOT_DB9; - reg NOT_DB10; - reg NOT_DB11; - reg NOT_DB12; - reg NOT_DB13; - reg NOT_DB14; - reg NOT_DB15; - reg NOT_DB16; - reg NOT_DB17; - reg NOT_DB18; - reg NOT_DB19; - reg NOT_DB20; - reg NOT_DB21; - reg NOT_DB22; - reg NOT_DB23; - reg NOT_DB24; - reg NOT_DB25; - reg NOT_DB26; - reg NOT_DB27; - reg NOT_DB28; - reg NOT_DB29; - reg NOT_DB30; - reg NOT_DB31; - reg [BITS-1:0] NOT_DB; - reg NOT_CLKA_PER; - reg NOT_CLKA_MINH; - reg NOT_CLKA_MINL; - reg NOT_CLKB_PER; - reg NOT_CLKB_MINH; - reg NOT_CLKB_MINL; - - reg LAST_NOT_CENA; - reg LAST_NOT_CENB; - - - reg LAST_NOT_AA0; - reg LAST_NOT_AA1; - reg LAST_NOT_AA2; - reg LAST_NOT_AA3; - reg LAST_NOT_AA4; - reg LAST_NOT_AA5; - reg LAST_NOT_AA6; - reg LAST_NOT_AA7; - reg LAST_NOT_AA8; - reg [addr_width-1:0] LAST_NOT_AA; - reg LAST_NOT_AB0; - reg LAST_NOT_AB1; - reg LAST_NOT_AB2; - reg LAST_NOT_AB3; - reg LAST_NOT_AB4; - reg LAST_NOT_AB5; - reg LAST_NOT_AB6; - reg LAST_NOT_AB7; - reg LAST_NOT_AB8; - reg [addr_width-1:0] LAST_NOT_AB; - reg LAST_NOT_DB0; - reg LAST_NOT_DB1; - reg LAST_NOT_DB2; - reg LAST_NOT_DB3; - reg LAST_NOT_DB4; - reg LAST_NOT_DB5; - reg LAST_NOT_DB6; - reg LAST_NOT_DB7; - reg LAST_NOT_DB8; - reg LAST_NOT_DB9; - reg LAST_NOT_DB10; - reg LAST_NOT_DB11; - reg LAST_NOT_DB12; - reg LAST_NOT_DB13; - reg LAST_NOT_DB14; - reg LAST_NOT_DB15; - reg LAST_NOT_DB16; - reg LAST_NOT_DB17; - reg LAST_NOT_DB18; - reg LAST_NOT_DB19; - reg LAST_NOT_DB20; - reg LAST_NOT_DB21; - reg LAST_NOT_DB22; - reg LAST_NOT_DB23; - reg LAST_NOT_DB24; - reg LAST_NOT_DB25; - reg LAST_NOT_DB26; - reg LAST_NOT_DB27; - reg LAST_NOT_DB28; - reg LAST_NOT_DB29; - reg LAST_NOT_DB30; - reg LAST_NOT_DB31; - reg [BITS-1:0] LAST_NOT_DB; - reg LAST_NOT_CLKA_PER; - reg LAST_NOT_CLKA_MINH; - reg LAST_NOT_CLKA_MINL; - reg LAST_NOT_CLKB_PER; - reg LAST_NOT_CLKB_MINH; - reg LAST_NOT_CLKB_MINL; - - reg LAST_NOT_CONTA; - reg LAST_NOT_CONTB; - wire contA_flag; - wire contB_flag; - wire cont_flag; - - wire [BITS-1:0] _QA; - wire [addr_width-1:0] _AA; - wire [addr_width-1:0] _AB; - wire _CLKA; - wire _CLKB; - wire _CENA; - - - wire _CENB; - wire [BITS-1:0] _DB; - wire re_flagA; - - - wire re_flagB; - - reg LATCHED_CENA; - - - reg LATCHED_CENB; - reg [addr_width-1:0] LATCHED_AA; - reg [addr_width-1:0] LATCHED_AB; - reg [BITS-1:0] LATCHED_DB; - - reg CENAi; - reg CENBi; - - - reg [addr_width-1:0] AAi; - reg [addr_width-1:0] ABi; - reg [BITS-1:0] DBi; - reg [BITS-1:0] QAi; - reg [BITS-1:0] LAST_QAi; - - - - reg LAST_CLKA; - reg LAST_CLKB; - - reg valid_cycleA; - reg valid_cycleB; - - - task update_Anotifier_buses; - begin - NOT_AA = { - NOT_AA8, - NOT_AA7, - NOT_AA6, - NOT_AA5, - NOT_AA4, - NOT_AA3, - NOT_AA2, - NOT_AA1, - NOT_AA0}; - end - endtask - - task update_Bnotifier_buses; - begin - NOT_AB = { - NOT_AB8, - NOT_AB7, - NOT_AB6, - NOT_AB5, - NOT_AB4, - NOT_AB3, - NOT_AB2, - NOT_AB1, - NOT_AB0}; - NOT_DB = { - NOT_DB31, - NOT_DB30, - NOT_DB29, - NOT_DB28, - NOT_DB27, - NOT_DB26, - NOT_DB25, - NOT_DB24, - NOT_DB23, - NOT_DB22, - NOT_DB21, - NOT_DB20, - NOT_DB19, - NOT_DB18, - NOT_DB17, - NOT_DB16, - NOT_DB15, - NOT_DB14, - NOT_DB13, - NOT_DB12, - NOT_DB11, - NOT_DB10, - NOT_DB9, - NOT_DB8, - NOT_DB7, - NOT_DB6, - NOT_DB5, - NOT_DB4, - NOT_DB3, - NOT_DB2, - NOT_DB1, - NOT_DB0}; - - - end - endtask - - task mem_cycleA; - begin - valid_cycleA = 1'bx; - casez({CENAi}) - 1'b0: begin - valid_cycleA = 1; - read_memA(1,0); - end - 1'b1: ; - 1'bx: begin - valid_cycleA = 1; - read_memA(0,1); - end - endcase - end - endtask - - task mem_cycleB; - begin - valid_cycleB = 1'bx; - casez(CENBi) - 1'b0: begin - valid_cycleB = 0; - write_mem(ABi,DBi); - end - 1'b1: ; - 1'bx: begin - valid_cycleB = 0; - write_mem_x(ABi); - end - endcase - end - endtask - - task contentionA; - begin - casez(valid_cycleB) - 1'bx: ; - 1'b0:begin - read_memA(0,1); - end - 1'b1: ; - endcase - end - endtask - - task contentionB; - begin - casez(valid_cycleA) - 1'bx: ; - 1'b1:begin - read_memA(0,1); - end - 1'b0: ; - endcase - end - endtask - - task update_Alast_notifiers; - begin - LAST_NOT_AA = NOT_AA; - LAST_NOT_CENA = NOT_CENA; - LAST_NOT_CLKA_PER = NOT_CLKA_PER; - LAST_NOT_CLKA_MINH = NOT_CLKA_MINH; - LAST_NOT_CLKA_MINL = NOT_CLKA_MINL; - LAST_NOT_CONTA = NOT_CONTA; - end - endtask - - task update_Blast_notifiers; - begin - LAST_NOT_AB = NOT_AB; - LAST_NOT_DB = NOT_DB; - LAST_NOT_CENB = NOT_CENB; - LAST_NOT_CLKB_PER = NOT_CLKB_PER; - LAST_NOT_CLKB_MINH = NOT_CLKB_MINH; - LAST_NOT_CLKB_MINL = NOT_CLKB_MINL; - LAST_NOT_CONTB = NOT_CONTB; - end - endtask - - task latch_Ainputs; - begin - LATCHED_AA = _AA ; - LATCHED_CENA = _CENA ; - LAST_QAi = QAi; - end - endtask - - task latch_Binputs; - begin - LATCHED_AB = _AB ; - LATCHED_DB = _DB ; - LATCHED_CENB = _CENB ; - end - endtask - - task update_Alogic; - integer n; - begin - CENAi = LATCHED_CENA; - AAi = LATCHED_AA; - end - endtask - - task update_Blogic; - integer n; - begin - CENBi = LATCHED_CENB; - ABi = LATCHED_AB; - DBi = LATCHED_DB; - end - endtask - - - - - task x_Ainputs; - integer n; - begin - for (n=0; n QA[0]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[1]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[2]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[3]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[4]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[5]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[6]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[7]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[8]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[9]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[10]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[11]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[12]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[13]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[14]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[15]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[16]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[17]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[18]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[19]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[20]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[21]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[22]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[23]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[24]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[25]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[26]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[27]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[28]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[29]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[30]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - (CLKA => QA[31]) = (1.000, 1.000, 0.500, 1.000, 0.500, 1.000); - -endspecify - -endmodule diff --git a/resources/soc/simu/testbench/vmac/mac_top.v b/resources/soc/simu/testbench/vmac/mac_top.v deleted file mode 100644 index 2b624f4..0000000 --- a/resources/soc/simu/testbench/vmac/mac_top.v +++ /dev/null @@ -1,13548 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -module vMAC_TOP -( - hclk, hrst_, SYS_RST_, - - hmst, hmstlock, - htrans, hburst, haddr, - hwrite, hsize, - hrdata, hwdata, hrdy, hresp, - eth_hreq, eth_hlock, eth_hgnt, - eth_htrans, eth_hburst, eth_haddr, - eth_hwrite, eth_hsize, eth_hprot, - eth_hwdata, - eth_hsel, eth_hrdy, eth_hresp, eth_hsplit, - eth_hrdata, - - interrupt, - - mtxclk, mtxen, mtxd, mtxerr, - mrxclk, mrxdv, mrxd, mrxerr, - mcoll, mcrs, - mdc, md_i, md_o, md_oe, - - bist_mode - - ); - -input hclk; -input hrst_; -input [3:0] hmst; -input hmstlock; -input [1:0] htrans; -input [2:0] hburst; -input [31:0] haddr; -input hwrite; -input [2:0] hsize; -input [31:0] hrdata; -input [31:0] hwdata; -input hrdy; -input [1:0] hresp; - -output eth_hreq; -output eth_hlock; -input eth_hgnt; -output [1:0] eth_htrans; -output [2:0] eth_hburst; -output [31:0] eth_haddr; -output eth_hwrite; -output [2:0] eth_hsize; -output [3:0] eth_hprot; -output [31:0] eth_hwdata; - -input eth_hsel; -output eth_hrdy; -output [1:0] eth_hresp; -output [15:0] eth_hsplit; -output [31:0] eth_hrdata; - -input mtxclk; -output [3:0] mtxd; -output mtxen; -output mtxerr; - -input mrxclk; -input [3:0] mrxd; -input mrxdv; -input mrxerr; - -input mcoll; -input mcrs; - -input md_i; -output mdc; -output md_o; -output md_oe; - -output interrupt; - -input bist_mode; -input SYS_RST_; - -wire tps,rps,rsttco,rstrco,sclk,scs,sdo; - `define MAHBDATAWIDTH 32 - `define TFIFODEPTH 9 - `define RFIFODEPTH 9 - `define ADDRDEPTH 6 - wire [`MAHBDATAWIDTH - 1:0] trdata; - wire twe; - wire [`TFIFODEPTH - 1:0] twaddr; - wire [`TFIFODEPTH - 1:0] traddr; - wire [`MAHBDATAWIDTH - 1:0] twdata; - wire [`MAHBDATAWIDTH - 1:0] rrdata; - wire rwe; - wire [`RFIFODEPTH - 1:0] rwaddr; - wire [`RFIFODEPTH - 1:0] rraddr; - wire [`MAHBDATAWIDTH - 1:0] rwdata; - wire [15:0] frdata; - wire fwe; - wire [`ADDRDEPTH - 1:0] fwaddr; - wire [`ADDRDEPTH - 1:0] fraddr; - wire [15:0] fwdata; - wire match; - wire matchval; - wire matchen; - wire [47:0] matchdata; - - -RF2_512x32 TX_RAM(.CLKA(mtxclk),.CENA(1'b0),.AA(traddr),.QA(trdata), - .CLKB(hclk ),.CENB(!twe),.AB(twaddr),.DB(twdata)); - - -RF2_512x32 RX_RAM(.CLKA(hclk ),.CENA(1'b0),.AA(rraddr),.QA(rrdata), - .CLKB(mrxclk),.CENB(!rwe),.AB(rwaddr),.DB(rwdata)); - -RF2_64x16 ADDR_RAM(.CLKA(mrxclk),.CENA(1'b0),.AA(fraddr),.QA(frdata), - .CLKB(hclk ),.CENB(!fwe),.AB(fwaddr),.DB(fwdata)); - - -CAM_V FIL_CAM(.clk(mrxclk), .matchen(matchen), .matchdata(matchdata), .match(match), .matchval(matchval)); -MAC_AHB_V MAC_TEST( - .clkt(mtxclk), - .clkr(mrxclk), - .rsttco(rsttco), - .rstrco(rstrco), - .interrupt(interrupt), - .tps(tps), - .rps(rps), - .mhclk(hclk), - .mhresetn(hrst_), - .mhrdata(hrdata), - .mhready(hrdy), - .mhresp(hresp), - .mhaddr(eth_haddr), - .mhtrans(eth_htrans), - .mhwrite(eth_hwrite), - .mhsize(eth_hsize), - .mhburst(eth_hburst), - .mhprot(eth_hprot), - .mhwdata(eth_hwdata), - .mhgrantmac(eth_hgnt), - .mhbusreqmac(eth_hreq), - .mhlockmac(eth_hlock), - .shclk(hclk), - .shresetn(hrst_), - .shselmac(eth_hsel), - .shaddr(haddr[7:0]), - .shwrite(hwrite), - .shreadyi(hrdy), - .shtrans(htrans), - .shsize(hsize), - .shburst(hburst), - .shwdata(hwdata), - .shreadyo(eth_hrdy), - .shresp(eth_hresp), - .shrdata(eth_hrdata), - .trdata(trdata), - .twe(twe), - .twaddr(twaddr), - .traddr(traddr), - .twdata(twdata), - .rrdata(rrdata), - .rwe(rwe), - .rwaddr(rwaddr), - .rraddr(rraddr), - .rwdata(rwdata), - .frdata(frdata), - .fwe(fwe), - .fwaddr(fwaddr), - .fraddr(fraddr), - .fwdata(fwdata), - .match(match), - .matchval(matchval), - .matchen(matchen), - .matchdata(matchdata), - .sdi(1'b0), - .sclk(sclk), - .scs(scs), - .sdo(sdo), - .rxer(mrxerr), - .rxdv(mrxdv), - .col(mcoll), - .crs(mcrs), - .rxd(mrxd), - .txen(mtxen), - .txer(mtxerr), - .txd(mtxd), - .mdc(mdc), - .mdi(md_i), - .mdo(md_o), - .mden(md_oe) - ); - -endmodule - -module BD_V ( - clk, - rst, - col, - crs, - fdp, - tprog, - preamble, - tpend, - winp, - tiack, - coll, - carrier, - bkoff, - lc, - lo, - nc, - ec, - cc - ); - - `include "utility.v" - - input clk; - input rst; - - input col; - input crs; - - input fdp; - - input tprog; - input preamble; - input tpend; - output winp; - wire winp; - input tiack; - output coll; - wire coll; - output carrier; - wire carrier; - output bkoff; - wire bkoff; - output lc; - wire lc; - output lo; - reg lo; - output nc; - wire nc; - output ec; - reg ec; - output [3:0] cc; - wire [3:0] cc; - - - reg crs_r; - reg inc; - - reg ibkoff; - reg ibkoff_r; - reg icoll; - reg ilc; - reg [3:0] ccnt; - reg [9:0] bkcnt; - reg [8:0] slcnt; - reg [9:0] bkrel_c; - wire [9:0] p_rand; - reg [31:0] lfsr; - reg [31:0] lfsr_c; - reg iwinp; - - always @(posedge clk) - begin : crs_reg_proc - if (rst) - begin - crs_r <= 1'b0 ; - lo <= 1'b0 ; - inc <= 1'b0 ; - end - else - begin - if (fdp) - begin - crs_r <= 1'b0 ; - end - else - begin - crs_r <= crs ; - end - - if (tprog & !inc & !crs_r) - begin - lo <= 1'b1 ; - end - else if(!tpend & !tprog) - begin - lo <= 1'b0 ; - end - - if (tprog & crs_r) - begin - inc <= 1'b0 ; - end - else if (!tpend & !tprog) - begin - inc <= 1'b1 ; - end - end - end - - assign nc = inc ; - - always @(ccnt or p_rand) - begin : bkrel_proc - case (ccnt) - 4'b0000 : - begin - bkrel_c <= {9'b000000000, p_rand[0]} ; - end - 4'b0001 : - begin - bkrel_c <= {8'b00000000, p_rand[1:0]} ; - end - 4'b0010 : - begin - bkrel_c <= {7'b0000000, p_rand[2:0]} ; - end - 4'b0011 : - begin - bkrel_c <= {6'b000000, p_rand[3:0]} ; - end - 4'b0100 : - begin - bkrel_c <= {5'b00000, p_rand[4:0]} ; - end - 4'b0101 : - begin - bkrel_c <= {4'b0000, p_rand[5:0]} ; - end - 4'b0110 : - begin - bkrel_c <= {3'b000, p_rand[6:0]} ; - end - 4'b0111 : - begin - bkrel_c <= {2'b00, p_rand[7:0]} ; - end - 4'b1000 : - begin - bkrel_c <= {1'b0, p_rand[8:0]} ; - end - default : - begin - bkrel_c <= p_rand[9:0] ; - end - endcase - end - - always @(posedge clk) - begin : slcnt_reg_proc - if (rst) - begin - slcnt <= {9{1'b1}} ; - end - else - begin - if (tprog & !preamble & !icoll) - begin - if (slcnt != 9'b000000000) - begin - slcnt <= slcnt - 1 ; - end - end - else if (ibkoff) - begin - if (slcnt == 9'b000000000 | icoll) - begin - slcnt <= SLOT_TIME ; - end - else - begin - slcnt <= slcnt - 1 ; - end - end - else - begin - slcnt <= SLOT_TIME ; - end - end - end - - always @(posedge clk) - begin : bkcnt_reg_proc - if (rst) - begin - bkcnt <= {10{1'b1}} ; - end - else - begin - if (icoll & !ibkoff) - begin - bkcnt <= bkrel_c ; - end - else if (slcnt == 9'b000000000) - begin - bkcnt <= bkcnt - 1 ; - end - end - end - - always @(posedge clk) - begin : rand_reg_proc - if (rst) - begin - lfsr <= {31{1'b1}}; - end - else - begin - lfsr <= lfsr_c; - end - end - - always @(lfsr) - begin : lfsr_drv - - reg [31:0] lfsr_n; - - integer i; - for(i=0; i<=30; i=i+1) - begin - lfsr_n[i] = lfsr[i+1]; - end - - lfsr_n[31] = 1'b0; - if(lfsr[0]==1'b1) - begin - lfsr_n = lfsr_n ^ 32'b10000000000000000000111010100110; - end - - lfsr_c <= lfsr_n; - - end - - assign p_rand = lfsr[9:0] ; - - - always @(posedge clk) - begin : ibkoff_reg_proc - if (rst) - begin - ibkoff <= 1'b0 ; - ibkoff_r <= 1'b0 ; - end - else - begin - ibkoff_r <= ibkoff ; - if(icoll & ccnt!=4'b1111 & !iwinp & !ilc) - begin - ibkoff <= 1'b1 ; - end - else if (bkcnt == 10'b0000000000) - begin - ibkoff <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : coll_reg_proc - if (rst) - begin - icoll <= 1'b0 ; - ilc <= 1'b0 ; - ec <= 1'b0 ; - iwinp <= 1'b1 ; - ccnt <= 4'b0000 ; - end - else - begin - if ((preamble | tprog) & col & !fdp) - begin - icoll <= 1'b1 ; - end - else if (!tprog & !preamble) - begin - icoll <= 1'b0 ; - end - - if (tiack) - begin - ilc <= 1'b0 ; - end - else if (tprog & icoll & iwinp) - begin - ilc <= 1'b1 ; - end - - if (tiack) - begin - ec <= 1'b0 ; - end - else if (icoll & ccnt == 4'b1111 & tprog) - begin - ec <= 1'b1 ; - end - - if (slcnt == 9'b000000000 | !tprog) - begin - iwinp <= 1'b1 ; - end - else - begin - iwinp <= 1'b0 ; - end - - if (!tpend & !tprog) - begin - ccnt <= 4'b0000 ; - end - else if (ibkoff & !ibkoff_r) - begin - ccnt <= ccnt + 4'b0001 ; - end - end - end - - assign winp = iwinp ; - - assign lc = ilc; - - assign carrier = crs_r ; - - assign coll = icoll ; - - assign bkoff = ibkoff ; - - assign cc = ccnt ; - -endmodule - - - -module CAM_V (clk, matchen, matchdata, match, matchval); - - input clk; - input matchen; - input [47:0] matchdata; - output match; - wire match; - output matchval; - wire matchval; - - parameter [47:0] adr0 = {8'b10111010, 8'b10011000, 8'b01110110, - 8'b01010100, 8'b00110010, 8'b00010001}; - parameter [47:0] adr1 = {8'b00000000, 8'b00000000, 8'b00000000, - 8'b00000000, 8'b00000000, 8'b00000000}; - parameter [47:0] adr2 = {8'b00000000, 8'b00000000, 8'b00000000, - 8'b00000000, 8'b00000000, 8'b00000000}; - parameter [47:0] adr3 = {8'b00000000, 8'b00000000, 8'b00000000, - 8'b00000000, 8'b00000000, 8'b00000000}; - reg imatchval; - - always @(posedge clk) - begin : imatchval_proc - imatchval <= matchen ; - end - - assign match = (imatchval & (adr0 == matchdata | - adr1 == matchdata | - adr2 == matchdata | - adr3 == matchdata)) ? 1'b1 : 1'b0 ; - - assign matchval = imatchval ; - -endmodule - - - -module CSR_V ( - clk, - rst, - interrupt, - csrreq, - csrrw, - csrbe, - csraddr, - csrdatai, - csrack, - csrdatao, - rstsofto, - tprog, - tireq, - unf, - tcsreq, - tiack, - tcsack, - fd, - ic, - etireq, - etiack, - tm, - sf, - tset, - tdes, - tbuf, - tstat, - tu, - tpollack, - ft, - tpoll, - tdbadc, - tdbad, - rcsreq, - rprog, - rcsack, - ren, - ra, - pm, - pr, - pb, - rif, - ho, - hp, - foclack, - mfclack, - oco, - mfo, - focg, - mfcg, - focl, - mfcl, - rireq, - erireq, - ru, - rpollack, - rdes, - rbuf, - rstat, - riack, - eriack, - rpoll, - rdbadc, - rdbad, - ble, - dbo, - dma_priority, - pbl, - dsl, - stoptc, - stoptlsm, - stoptfifo, - stopt, - tps, - stoprc, - stoprlsm, - stopr, - rps, - sdi, - sclk, - scs, - sdo, - mdi, - mdc, - mdo, - mden - ); - - parameter CSRWIDTH = 32; - parameter DATAWIDTH = 32; - parameter DATADEPTH = 32; - parameter RFIFODEPTH = 9; - parameter RCDEPTH = 2; - - `include "utility.v" - - input clk; - input rst; - output interrupt; - wire interrupt; - - input csrreq; - input csrrw; - input [CSRWIDTH / 8 - 1:0] csrbe; - input [CSRDEPTH - 1:0] csraddr; - input [CSRWIDTH - 1:0] csrdatai; - output csrack; - wire csrack; - output [CSRWIDTH - 1:0] csrdatao; - reg [CSRWIDTH - 1:0] csrdatao; - - output rstsofto; - reg rstsofto; - - input tprog; - input tireq; - input unf; - input tcsreq; - output tiack; - wire tiack; - output tcsack; - wire tcsack; - output fd; - wire fd; - - input ic; - input etireq; - output etiack; - wire etiack; - output [2:0] tm; - wire [2:0] tm; - output sf; - wire sf; - - input tset; - input tdes; - input tbuf; - input tstat; - input tu; - input tpollack; - input [1:0] ft; - output tpoll; - wire tpoll; - output tdbadc; - reg tdbadc; - output [DATADEPTH - 1:0] tdbad; - wire [DATADEPTH - 1:0] tdbad; - - input rcsreq; - input rprog; - output rcsack; - wire rcsack; - output ren; - wire ren; - output ra; - wire ra; - output pm; - wire pm; - output pr; - wire pr; - output pb; - wire pb; - output rif; - wire rif; - output ho; - wire ho; - output hp; - wire hp; - - input foclack; - input mfclack; - input oco; - input mfo; - input [10:0] focg; - input [15:0] mfcg; - output focl; - reg focl; - output mfcl; - reg mfcl; - - input rireq; - input erireq; - input ru; - input rpollack; - input rdes; - input rbuf; - input rstat; - output riack; - wire riack; - output eriack; - wire eriack; - output rpoll; - reg rpoll; - output rdbadc; - reg rdbadc; - output [DATADEPTH - 1:0] rdbad; - wire [DATADEPTH - 1:0] rdbad; - - output ble; - wire ble; - output dbo; - wire dbo; - output [1:0] dma_priority; - wire [1:0] dma_priority; - output [5:0] pbl; - wire [5:0] pbl; - output [4:0] dsl; - wire [4:0] dsl; - - input stoptc; - input stoptlsm; - input stoptfifo; - output stopt; - wire stopt; - output tps; - reg tps; - - input stoprc; - input stoprlsm; - output stopr; - wire stopr; - output rps; - reg rps; - - input sdi; - output sclk; - wire sclk; - output scs; - wire scs; - output sdo; - wire sdo; - - input mdi; - output mdc; - wire mdc; - output mdo; - wire mdo; - output mden; - wire mden; - - - reg [31:0] csrdata_c; - reg [3:0] csrdbe_c; - wire [1:0] csraddr10; - wire [5:0] csraddr72; - wire [1:0] csrbe10; - wire [31:0] csr0; - wire [31:0] csr5; - wire [31:0] csr6; - wire [31:0] csr7; - wire [31:0] csr8; - wire [31:0] csr9; - wire [31:0] csr11; - - reg csr0_dbo; - reg [2:0] csr0_tap; - reg [5:0] csr0_pbl; - reg csr0_ble; - reg [4:0] csr0_dsl; - reg csr0_bar; - reg csr0_swr; - - reg [31:0] csr3; - - reg [31:0] csr4; - - reg [2:0] csr5_ts; - reg [2:0] csr5_rs; - reg csr5_nis; - reg csr5_ais; - reg csr5_eri; - reg csr5_gte; - reg csr5_eti; - reg csr5_rps; - reg csr5_ru; - reg csr5_ri; - reg csr5_unf; - reg csr5_tu; - reg csr5_tps; - reg csr5_ti; - - reg csr6_ra; - reg csr6_ttm; - reg csr6_sf; - reg [1:0] csr6_tr; - reg csr6_st; - reg csr6_fd; - reg csr6_pm; - reg csr6_pr; - reg csr6_if; - reg csr6_pb; - reg csr6_ho; - reg csr6_sr; - reg csr6_hp; - - reg csr7_nie; - reg csr7_aie; - reg csr7_ere; - reg csr7_gte; - reg csr7_ete; - reg csr7_rse; - reg csr7_rue; - reg csr7_rie; - reg csr7_une; - reg csr7_tue; - reg csr7_tse; - reg csr7_tie; - - reg [10:0] csr8_foc; - reg csr8_oco; - reg [15:0] csr8_mfc; - reg csr8_mfo; - reg csr8read; - - reg csr9_mdi; - reg csr9_mii; - reg csr9_mdo; - reg csr9_mdc; - reg csr9_sdi; - reg csr9_sclk; - reg csr9_scs; - reg csr9_sdo; - - reg csr11_cs; - reg [3:0] csr11_tt; - reg [2:0] csr11_ntp; - reg [3:0] csr11_rt; - reg [2:0] csr11_nrp; - reg csr11_con; - reg [15:0] csr11_tim; - reg csr11wr; - - reg tapwr; - reg tpollcmd; - reg itpoll; - reg [2:0] tapcnt; - - reg [1:0] tpsm_c; - reg [1:0] tpsm; - reg tstopcmd; - reg tstartcmd; - reg stoptc_r; - reg stoptlsm_r; - reg stoptfifo_r; - wire [2:0] ts_c; - - reg [1:0] rpsm_c; - reg [1:0] rpsm; - reg rstopcmd; - reg rstartcmd; - reg stoprc_r; - reg stoprlsm_r; - wire [2:0] rs_c; - - reg rpollcmd; - - wire csr5wr_c; - reg csr5wr; - reg gte; - reg iint; - reg rireq_r; - reg rireq_r2; - reg eri; - reg erireq_r; - reg erireq_r2; - reg tireq_r; - reg tireq_r2; - reg eti; - reg etireq_r; - reg etireq_r2; - reg unfi; - reg unf_r; - reg unf_r2; - reg tui; - reg tu_r; - reg tu_r2; - reg rui; - reg ru_r; - reg ru_r2; - reg iic; - - reg rcsreq_r; - reg rcsreq_r1; - reg rimprog; - reg [3:0] rcscnt; - reg rcs2048; - reg rcs128; - reg [3:0] rtcnt; - reg [2:0] rcnt; - reg rimex; - - reg timprog; - reg [7:0] ttcnt; - reg [2:0] tcnt; - reg timex; - reg tcsreq_r1; - reg tcsreq_r2; - reg [3:0] tcscnt; - reg tcs2048; - reg tcs128; - - reg [10:0] foc_c; - reg [15:0] mfc_c; - reg [10:0] focg_r; - reg [15:0] mfcg_r; - - reg gstart; - reg gstart_r; - reg [15:0] gcnt; - wire [CSRWIDTH_MAX + 1:0] csrdatai_max; - wire [CSRWIDTH_MAX + 1:0] czero_max; - wire [CSRWIDTH_MAX/8 + 1:0] csrbe_max; - - assign csraddr10 = csraddr[1:0] ; - - assign csraddr72 = csraddr[7:2] ; - - assign csrbe10 = (CSRWIDTH == 16) ? csrbe_max[1:0] : {2{1'b1}} ; - - always @(csrdatai_max or csrbe_max or csraddr or csraddr10 or csrbe10) - begin : csrdata_proc - csrdata_c <= {32{1'b1}} ; - csrdbe_c <= {4{1'b1}} ; - case (CSRWIDTH) - 8 : - begin - if (csrbe_max[0]) - begin - case (csraddr10) - 2'b00 : - begin - csrdata_c[7:0] <= csrdatai_max[CSRWIDTH-1:0] ; - csrdbe_c <= 4'b0001 ; - end - 2'b01 : - begin - csrdata_c[15:8] <= csrdatai_max[CSRWIDTH-1:0] ; - csrdbe_c <= 4'b0010 ; - end - 2'b10 : - begin - csrdata_c[23:16] <= csrdatai_max[CSRWIDTH-1:0] ; - csrdbe_c <= 4'b0100 ; - end - default : - begin - csrdata_c[31:24] <= csrdatai_max[CSRWIDTH-1:0] ; - csrdbe_c <= 4'b1000 ; - end - endcase - end - else - begin - csrdbe_c <= 4'b0000 ; - end - end - 16 : - begin - case (csrbe10) - 2'b11 : - begin - if (csraddr[1]) - begin - csrdata_c[31:16] <= csrdatai_max[CSRWIDTH-1:0] ; - csrdbe_c <= 4'b1100 ; - end - else - begin - csrdata_c[15:0] <= csrdatai_max[CSRWIDTH-1:0] ; - csrdbe_c <= 4'b0011 ; - end - end - 2'b10 : - begin - if (csraddr[1]) - begin - csrdata_c[31:24] <= - csrdatai_max[CSRWIDTH - 1:CSRWIDTH / 2] ; - csrdbe_c <= 4'b1000 ; - end - else - begin - csrdata_c[15: 8] <= - csrdatai_max[CSRWIDTH - 1:CSRWIDTH / 2] ; - csrdbe_c <= 4'b0010 ; - end - end - 2'b01 : - begin - if (csraddr[1]) - begin - csrdata_c[23:16] <= csrdatai_max[7:0] ; - csrdbe_c <= 4'b0100 ; - end - else - begin - csrdata_c[7:0] <= csrdatai_max[7:0] ; - csrdbe_c <= 4'b0001 ; - end - end - default : - begin - csrdbe_c <= 4'b0000 ; - end - endcase - end - default : - begin - csrdata_c <= csrdatai_max[31:0] ; - csrdbe_c <= csrbe_max[3:0] ; - end - endcase - end - - always @(posedge clk) - begin : csr0_reg_proc - if (rst) - begin - csr0_dbo <= CSR0_RV[20] ; - csr0_tap <= CSR0_RV[19:17] ; - csr0_pbl <= CSR0_RV[13:8] ; - csr0_ble <= CSR0_RV[7] ; - csr0_dsl <= CSR0_RV[6:2] ; - csr0_bar <= CSR0_RV[1] ; - csr0_swr <= CSR0_RV[0] ; - tapwr <= 1'b0 ; - end - else - begin - if (!csrrw & csrreq & csraddr72 == CSR0_ID) - begin - if (csrdbe_c[2]) - begin - csr0_dbo <= csrdata_c[20] ; - csr0_tap <= csrdata_c[19:17] ; - tapwr <= 1'b1 ; - end - else - begin - tapwr <= 1'b0 ; - end - if (csrdbe_c[1]) - begin - csr0_pbl <= csrdata_c[13:8] ; - end - if (csrdbe_c[0]) - begin - csr0_ble <= csrdata_c[7] ; - csr0_dsl <= csrdata_c[6:2] ; - csr0_bar <= csrdata_c[1] ; - csr0_swr <= csrdata_c[0] ; - end - end - else - begin - tapwr <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : tpoolcmd_reg_proc - if (rst) - begin - tpollcmd <= 1'b0 ; - end - else - begin - if (!csrrw & csrreq & csraddr72 == CSR1_ID) - begin - tpollcmd <= 1'b1 ; - end - else - begin - tpollcmd <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : rpoolcmd_reg_proc - if (rst) - begin - rpollcmd <= 1'b0 ; - end - else - begin - if (!csrrw & csrreq & csraddr72 == CSR2_ID) - begin - rpollcmd <= 1'b1 ; - end - else - begin - rpollcmd <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : csr3_reg_proc - if (rst) - begin - csr3 <= CSR3_RV ; - end - else - begin - if (!csrrw & csrreq & csraddr72 == CSR3_ID) - begin - if (csrdbe_c[0]) - begin - csr3[7:0] <= csrdata_c[7:0] ; - end - if (csrdbe_c[1]) - begin - csr3[15:8] <= csrdata_c[15:8] ; - end - if (csrdbe_c[2]) - begin - csr3[23:16] <= csrdata_c[23:16] ; - end - if (csrdbe_c[3]) - begin - csr3[31:24] <= csrdata_c[31:24] ; - end - end - end - end - - assign rdbad = csr3[DATADEPTH - 1:0] ; - - always @(posedge clk) - begin : rdbadc_reg_proc - if (rst) - begin - rdbadc <= 1'b1 ; - end - else - begin - if (!csrrw & csrreq & csraddr72 == CSR3_ID & rpsm == PSM_STOP) - begin - rdbadc <= 1'b1 ; - end - else if (rpsm == PSM_RUN) - begin - rdbadc <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : csr4_reg_proc - if (rst) - begin - csr4 <= CSR4_RV ; - end - else - begin - if (!csrrw & csrreq & csraddr72 == CSR4_ID) - begin - if (csrdbe_c[0]) - begin - csr4[7:0] <= csrdata_c[7:0] ; - end - if (csrdbe_c[1]) - begin - csr4[15:8] <= csrdata_c[15:8] ; - end - if (csrdbe_c[2]) - begin - csr4[23:16] <= csrdata_c[23:16] ; - end - if (csrdbe_c[3]) - begin - csr4[31:24] <= csrdata_c[31:24] ; - end - end - end - end - - always @(posedge clk) - begin : tdbadc_reg_proc - if (rst) - begin - tdbadc <= 1'b1 ; - end - else - begin - if (!csrrw & csrreq & csraddr72 == CSR4_ID) - begin - tdbadc <= 1'b1 ; - end - else if (tpsm == PSM_RUN) - begin - tdbadc <= 1'b0 ; - end - end - end - - assign csr5wr_c = (!csrrw & csrreq & csraddr72 == CSR5_ID) ? 1'b1 : - 1'b0 ; - - always @(posedge clk) - begin : csr5wr_reg_proc - if (rst) - begin - csr5wr <= 1'b0 ; - end - else - begin - csr5wr <= csr5wr_c ; - end - end - - always @(posedge clk) - begin : csr5_reg_proc - if (rst) - begin - csr5_ts <= CSR5_RV[22:20] ; - csr5_rs <= CSR5_RV[19:17] ; - csr5_nis <= CSR5_RV[16] ; - csr5_ais <= CSR5_RV[15] ; - csr5_eri <= CSR5_RV[14] ; - csr5_gte <= CSR5_RV[11] ; - csr5_eti <= CSR5_RV[10] ; - csr5_rps <= CSR5_RV[8] ; - csr5_ru <= CSR5_RV[7] ; - csr5_ri <= CSR5_RV[6] ; - csr5_unf <= CSR5_RV[5] ; - csr5_tu <= CSR5_RV[2] ; - csr5_tps <= CSR5_RV[1] ; - csr5_ti <= CSR5_RV[0] ; - end - else - begin - if (csr5wr_c) - begin - if (csrdbe_c[2]) - begin - csr5_nis <= ~csrdata_c[16] & csr5_nis ; - end - if (csrdbe_c[1]) - begin - csr5_ais <= ~csrdata_c[15] & csr5_ais ; - csr5_eri <= ~csrdata_c[14] & csr5_eri ; - csr5_gte <= ~csrdata_c[11] & csr5_gte ; - csr5_eti <= ~csrdata_c[10] & csr5_eti ; - csr5_rps <= ~csrdata_c[8] & csr5_rps ; - end - if (csrdbe_c[0]) - begin - csr5_ru <= ~csrdata_c[7] & csr5_ru ; - csr5_ri <= ~csrdata_c[6] & csr5_ri ; - csr5_unf <= ~csrdata_c[5] & csr5_unf ; - csr5_tu <= ~csrdata_c[2] & csr5_tu ; - csr5_tps <= ~csrdata_c[1] & csr5_tps ; - csr5_ti <= ~csrdata_c[0] & csr5_ti ; - end - end - else - begin - if (timex) - begin - csr5_ti <= 1'b1 ; - end - if (rimex) - begin - csr5_ri <= 1'b1 ; - end - if (eti) - begin - csr5_eti <= 1'b1 ; - end - if (eri) - begin - csr5_eri <= 1'b1 ; - end - if (gte) - begin - csr5_gte <= 1'b1 ; - end - if (tpsm_c == PSM_STOP & - (tpsm == PSM_RUN | tpsm == PSM_SUSPEND)) - begin - csr5_tps <= 1'b1 ; - end - if (rpsm_c == PSM_STOP & - (rpsm == PSM_RUN | rpsm == PSM_SUSPEND)) - begin - csr5_rps <= 1'b1 ; - end - if (rui) - begin - csr5_ru <= 1'b1 ; - end - if (tui) - begin - csr5_tu <= 1'b1 ; - end - if (unfi) - begin - csr5_unf <= 1'b1 ; - end - if ((csr5_ri & csr7_rie) | - (csr5_ti & csr7_tie) | - (csr5_eri & csr7_ere) | - (csr5_tu & csr7_tue) | - (csr5_gte & csr7_gte)) - begin - csr5_nis <= 1'b1 ; - end - else - begin - csr5_nis <= 1'b0 ; - end - if ((csr5_eti & csr7_ete) | - (csr5_rps & csr7_rse) | - (csr5_ru & csr7_rue) | - (csr5_unf & csr7_une) | - (csr5_tps & csr7_tse)) - begin - csr5_ais <= 1'b1 ; - end - else - begin - csr5_ais <= 1'b0 ; - end - csr5_ts <= ts_c ; - csr5_rs <= rs_c ; - end - end - end - - always @(posedge clk) - begin : csr6_reg_proc - if (rst) - begin - csr6_ra <= CSR6_RV[30] ; - csr6_ttm <= CSR6_RV[22] ; - csr6_sf <= CSR6_RV[21] ; - csr6_tr <= CSR6_RV[15:14] ; - csr6_st <= CSR6_RV[13] ; - csr6_fd <= CSR6_RV[9] ; - csr6_pm <= CSR6_RV[7] ; - csr6_pr <= CSR6_RV[6] ; - csr6_if <= CSR6_RV[4] ; - csr6_pb <= CSR6_RV[3] ; - csr6_ho <= CSR6_RV[2] ; - csr6_sr <= CSR6_RV[1] ; - csr6_hp <= CSR6_RV[0] ; - end - else - begin - if (!csrrw & csrreq & csraddr72 == CSR6_ID) - begin - if (csrdbe_c[3]) - begin - csr6_ra <= csrdata_c[30] ; - end - if (csrdbe_c[2]) - begin - csr6_ttm <= csrdata_c[22] ; - if (tpsm == PSM_STOP) - begin - csr6_sf <= csrdata_c[21] ; - end - end - if (csrdbe_c[1]) - begin - csr6_tr <= csrdata_c[15:14] ; - csr6_st <= csrdata_c[13] ; - csr6_fd <= csrdata_c[9] ; - end - if (csrdbe_c[0]) - begin - csr6_pm <= csrdata_c[7] ; - csr6_pr <= csrdata_c[6] ; - csr6_pb <= csrdata_c[3] ; - csr6_sr <= csrdata_c[1] ; - end - end - case (ft) - FT_PERFECT : - begin - csr6_ho <= 1'b0 ; - csr6_if <= 1'b0 ; - csr6_hp <= 1'b0 ; - end - FT_HASH : - begin - csr6_ho <= 1'b0 ; - csr6_if <= 1'b0 ; - csr6_hp <= 1'b1 ; - end - FT_INVERSE : - begin - csr6_ho <= 1'b0 ; - csr6_if <= 1'b1 ; - csr6_hp <= 1'b0 ; - end - default : - begin - csr6_ho <= 1'b1 ; - csr6_if <= 1'b0 ; - csr6_hp <= 1'b1 ; - end - endcase - end - end - - always @(posedge clk) - begin : csr7_reg_proc - if (rst) - begin - csr7_nie <= CSR7_RV[16] ; - csr7_aie <= CSR7_RV[15] ; - csr7_ere <= CSR7_RV[14] ; - csr7_gte <= CSR7_RV[11] ; - csr7_ete <= CSR7_RV[10] ; - csr7_rse <= CSR7_RV[8] ; - csr7_rue <= CSR7_RV[7] ; - csr7_rie <= CSR7_RV[6] ; - csr7_une <= CSR7_RV[5] ; - csr7_tue <= CSR7_RV[2] ; - csr7_tse <= CSR7_RV[1] ; - csr7_tie <= CSR7_RV[0] ; - end - else - begin - if (!csrrw & csrreq & csraddr72 == CSR7_ID) - begin - if (csrdbe_c[2]) - begin - csr7_nie <= csrdata_c[16] ; - end - if (csrdbe_c[1]) - begin - csr7_aie <= csrdata_c[15] ; - csr7_ere <= csrdata_c[14] ; - csr7_gte <= csrdata_c[11] ; - csr7_ete <= csrdata_c[10] ; - csr7_rse <= csrdata_c[8] ; - end - if (csrdbe_c[0]) - begin - csr7_rue <= csrdata_c[7] ; - csr7_rie <= csrdata_c[6] ; - csr7_une <= csrdata_c[5] ; - csr7_tue <= csrdata_c[2] ; - csr7_tse <= csrdata_c[1] ; - csr7_tie <= csrdata_c[0] ; - end - end - end - end - - always @(posedge clk) - begin : csr8_reg_proc - if (rst) - begin - csr8_oco <= 1'b0 ; - csr8_mfo <= 1'b0 ; - csr8_foc <= {11{1'b0}} ; - csr8_mfc <= {16{1'b0}} ; - end - else - begin - if (!(csrrw & csrreq & csraddr72 == CSR8_ID)) - begin - if (!csr8read) - begin - csr8_foc <= foc_c ; - csr8_mfc <= mfc_c ; - csr8_oco <= oco ; - csr8_mfo <= mfo ; - end - end - end - end - - always @(posedge clk) - begin : csr8read_reg_proc - if (rst) - begin - csr8read <= 1'b0 ; - end - else - begin - if (csrrw & csrreq & csraddr72 == CSR8_ID) - begin - csr8read <= csrdbe_c[3] ; - end - else - begin - csr8read <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : csr9_reg_proc - if (rst) - begin - csr9_mdi <= CSR9_RV[19] ; - csr9_mii <= CSR9_RV[18] ; - csr9_mdo <= CSR9_RV[17] ; - csr9_mdc <= CSR9_RV[16] ; - csr9_sdi <= CSR9_RV[2] ; - csr9_sclk <= CSR9_RV[1] ; - csr9_scs <= CSR9_RV[0] ; - csr9_sdo <= CSR9_RV[3] ; - end - else - begin - if (!csrrw & csrreq & csraddr72 == CSR9_ID) - begin - if (csrdbe_c[0]) - begin - csr9_sclk <= csrdata_c[1] ; - csr9_scs <= csrdata_c[0] ; - csr9_sdo <= csrdata_c[3] ; - end - if (csrdbe_c[2]) - begin - csr9_mii <= csrdata_c[18] ; - csr9_mdo <= csrdata_c[17] ; - csr9_mdc <= csrdata_c[16] ; - end - end - csr9_mdi <= mdi ; - csr9_sdi <= sdi ; - end - end - - always @(posedge clk) - begin : csr11_reg_proc - if (rst) - begin - csr11_cs <= CSR11_RV[31] ; - csr11_tt <= CSR11_RV[30:27] ; - csr11_ntp <= CSR11_RV[26:24] ; - csr11_rt <= CSR11_RV[23:20] ; - csr11_nrp <= CSR11_RV[19:17] ; - csr11_con <= CSR11_RV[16] ; - csr11_tim <= CSR11_RV[15:0] ; - end - else - begin - if (!csrrw & csrreq & csraddr72 == CSR11_ID) - begin - if (csrdbe_c[3]) - begin - csr11_cs <= csrdata_c[31] ; - csr11_tt <= csrdata_c[30:27] ; - csr11_ntp <= csrdata_c[26:24] ; - end - if (csrdbe_c[2]) - begin - csr11_rt <= csrdata_c[23:20] ; - csr11_nrp <= csrdata_c[19:17] ; - csr11_con <= csrdata_c[16] ; - end - if (csrdbe_c[1]) - begin - csr11_tim[15:8] <= csrdata_c[15:8] ; - end - if (csrdbe_c[0]) - begin - csr11_tim[7:0] <= csrdata_c[7:0] ; - end - end - end - end - - always @(posedge clk) - begin : csr11wr_reg_proc - if (rst) - begin - csr11wr <= 1'b0 ; - end - else - begin - if (!csrrw & csrreq & csraddr72 == CSR11_ID) - begin - csr11wr <= 1'b1 ; - end - else - begin - csr11wr <= 1'b0 ; - end - end - end - - assign csr0 = {CSR0_RV[31:26], CSR0_RV[25:21], csr0_dbo, csr0_tap, - CSR0_RV[16:14], csr0_pbl, csr0_ble, - csr0_dsl, csr0_bar, (rst | csr0_swr)} ; - - assign csr5 = {CSR5_RV[31:23], csr5_ts, csr5_rs, csr5_nis, - csr5_ais, csr5_eri, CSR5_RV[13:12], csr5_gte, csr5_eti, - CSR5_RV[9], csr5_rps, csr5_ru, csr5_ri, csr5_unf, - CSR5_RV[4:3], csr5_tu, csr5_tps, csr5_ti} ; - - assign csr6 = {CSR6_RV[31], csr6_ra, CSR6_RV[29:26], - CSR6_RV[25:23], csr6_ttm, csr6_sf, CSR6_RV[20], - CSR6_RV[19], CSR6_RV[18], CSR6_RV[17], CSR6_RV[16], - csr6_tr, csr6_st, CSR6_RV[13], CSR6_RV[12:11], - csr6_fd, CSR6_RV[8], csr6_pm, csr6_pr, CSR6_RV[5], - csr6_if, csr6_pb, csr6_ho, csr6_sr, csr6_hp} ; - - assign csr7 = {CSR7_RV[31:17], csr7_nie, csr7_aie, csr7_ere, - CSR7_RV[13:12], csr7_gte, csr7_ete, CSR6_RV[9], - csr7_rse, csr7_rue, csr7_rie, csr7_une, - CSR7_RV[4:3], csr7_tue, csr7_tse, csr7_tie} ; - - assign csr8 = {CSR8_RV[31:29], csr8_oco, csr8_foc, - csr8_mfo, csr8_mfc} ; - - assign csr9 = {CSR9_RV[31:20], csr9_mdi, csr9_mii, csr9_mdo, - csr9_mdc, CSR9_RV[15:4], csr9_sdo, csr9_sdi, - csr9_sclk, csr9_scs} ; - - assign csr11 = {csr11_cs, ttcnt[7:4], tcnt[2:0], rtcnt[3:0], - rcnt[2:0], csr11_con, gcnt} ; - - always @(csr0 or - csr3 or - csr4 or - csr5 or - csr6 or - csr7 or - csr8 or - csr9 or - csr11 or - csraddr or - csraddr72 or - csraddr10) - begin : csrmux_proc - case (CSRWIDTH) - 8 : - begin - case (csraddr10) - 2'b00 : - begin - case (csraddr72) - CSR0_ID : - begin - csrdatao <= csr0[7:0] ; - end - CSR3_ID : - begin - csrdatao <= csr3[7:0] ; - end - CSR4_ID : - begin - csrdatao <= csr4[7:0] ; - end - CSR5_ID : - begin - csrdatao <= csr5[7:0] ; - end - CSR6_ID : - begin - csrdatao <= csr6[7:0] ; - end - CSR7_ID : - begin - csrdatao <= csr7[7:0] ; - end - CSR8_ID : - begin - csrdatao <= csr8[7:0] ; - end - CSR9_ID : - begin - csrdatao <= csr9[7:0] ; - end - CSR11_ID : - begin - csrdatao <= csr11[7:0] ; - end - default : - begin - csrdatao <= {CSRWIDTH{1'b0}} ; - end - endcase - end - 2'b01 : - begin - case (csraddr72) - CSR0_ID : - begin - csrdatao <= csr0[15:8] ; - end - CSR3_ID : - begin - csrdatao <= csr3[15:8] ; - end - CSR4_ID : - begin - csrdatao <= csr4[15:8] ; - end - CSR5_ID : - begin - csrdatao <= csr5[15:8] ; - end - CSR6_ID : - begin - csrdatao <= csr6[15:8] ; - end - CSR7_ID : - begin - csrdatao <= csr7[15:8] ; - end - CSR8_ID : - begin - csrdatao <= csr8[15:8] ; - end - CSR9_ID : - begin - csrdatao <= csr9[15:8] ; - end - CSR11_ID : - begin - csrdatao <= csr11[15:8] ; - end - default : - begin - csrdatao <= {CSRWIDTH{1'b0}} ; - end - endcase - end - 2'b10 : - begin - case (csraddr72) - CSR0_ID : - begin - csrdatao <= csr0[23:16] ; - end - CSR3_ID : - begin - csrdatao <= csr3[23:16] ; - end - CSR4_ID : - begin - csrdatao <= csr4[23:16] ; - end - CSR5_ID : - begin - csrdatao <= csr5[23:16] ; - end - CSR6_ID : - begin - csrdatao <= csr6[23:16] ; - end - CSR7_ID : - begin - csrdatao <= csr7[23:16] ; - end - CSR8_ID : - begin - csrdatao <= csr8[23:16] ; - end - CSR9_ID : - begin - csrdatao <= csr9[23:16] ; - end - CSR11_ID : - begin - csrdatao <= csr11[23:16] ; - end - default : - begin - csrdatao <= {CSRWIDTH{1'b0}} ; - end - endcase - end - 2'b11 : - begin - case (csraddr72) - CSR0_ID : - begin - csrdatao <= csr0[31:24] ; - end - CSR3_ID : - begin - csrdatao <= csr3[31:24] ; - end - CSR4_ID : - begin - csrdatao <= csr4[31:24] ; - end - CSR5_ID : - begin - csrdatao <= csr5[31:24] ; - end - CSR6_ID : - begin - csrdatao <= csr6[31:24] ; - end - CSR7_ID : - begin - csrdatao <= csr7[31:24] ; - end - CSR8_ID : - begin - csrdatao <= csr8[31:24] ; - end - CSR9_ID : - begin - csrdatao <= csr9[31:24] ; - end - CSR11_ID : - begin - csrdatao <= csr11[31:24] ; - end - default : - begin - csrdatao <= {CSRWIDTH{1'b0}} ; - end - endcase - end - default : - begin - csrdatao <= {CSRWIDTH{1'b0}} ; - end - endcase - end - 16 : - begin - case (csraddr[1]) - 1'b0 : - begin - case (csraddr72) - CSR0_ID : - begin - csrdatao <= csr0[15:0] ; - end - CSR3_ID : - begin - csrdatao <= csr3[15:0] ; - end - CSR4_ID : - begin - csrdatao <= csr4[15:0] ; - end - CSR5_ID : - begin - csrdatao <= csr5[15:0] ; - end - CSR6_ID : - begin - csrdatao <= csr6[15:0] ; - end - CSR7_ID : - begin - csrdatao <= csr7[15:0] ; - end - CSR8_ID : - begin - csrdatao <= csr8[15:0] ; - end - CSR9_ID : - begin - csrdatao <= csr9[15:0] ; - end - CSR11_ID : - begin - csrdatao <= csr11[15:0] ; - end - default : - begin - csrdatao <= {CSRWIDTH{1'b0}} ; - end - endcase - end - 1'b1 : - begin - case (csraddr72) - CSR0_ID : - begin - csrdatao <= csr0[31:16] ; - end - CSR3_ID : - begin - csrdatao <= csr3[31:16] ; - end - CSR4_ID : - begin - csrdatao <= csr4[31:16] ; - end - CSR5_ID : - begin - csrdatao <= csr5[31:16] ; - end - CSR6_ID : - begin - csrdatao <= csr6[31:16] ; - end - CSR7_ID : - begin - csrdatao <= csr7[31:16] ; - end - CSR8_ID : - begin - csrdatao <= csr8[31:16] ; - end - CSR9_ID : - begin - csrdatao <= csr9[31:16] ; - end - CSR11_ID : - begin - csrdatao <= csr11[31:16] ; - end - default : - begin - csrdatao <= {CSRWIDTH{1'b0}} ; - end - endcase - end - default : - begin - csrdatao <= {CSRWIDTH{1'b0}} ; - end - endcase - end - default : - begin - case (csraddr72) - CSR0_ID : - begin - csrdatao <= csr0 ; - end - CSR3_ID : - begin - csrdatao <= csr3 ; - end - CSR4_ID : - begin - csrdatao <= csr4 ; - end - CSR5_ID : - begin - csrdatao <= csr5 ; - end - CSR6_ID : - begin - csrdatao <= csr6 ; - end - CSR7_ID : - begin - csrdatao <= csr7 ; - end - CSR8_ID : - begin - csrdatao <= csr8 ; - end - CSR9_ID : - begin - csrdatao <= csr9 ; - end - CSR11_ID : - begin - csrdatao <= csr11 ; - end - default : - begin - csrdatao <= {CSRWIDTH{1'b0}} ; - end - endcase - end - endcase - end - - assign csrack = 1'b1 ; - - assign dma_priority = (csr0_bar & !tprog) ? 2'b01 : - (csr0_bar & tprog) ? 2'b10 : - 2'b00 ; - - assign dbo = csr0_dbo ; - - assign pbl = csr0_pbl ; - - assign dsl = csr0_dsl ; - - assign ble = csr0_ble ; - - assign tdbad = csr4[DATADEPTH - 1:0] ; - - always @(posedge clk) - begin : itpoll_reg_proc - if (rst) - begin - itpoll <= 1'b0 ; - end - else - begin - if (((((csr0_tap == 3'b001 | - csr0_tap == 3'b010 | - csr0_tap == 3'b011) & tcs2048) | - ((csr0_tap == 3'b100 | - csr0_tap == 3'b101 | - csr0_tap == 3'b110 | - csr0_tap == 3'b111) & tcs128)) & - tapcnt == 3'b000 & tpsm == PSM_SUSPEND) | - tpollcmd | tstartcmd) - begin - itpoll <= 1'b1 ; - end - else if (tpollack) - begin - itpoll <= 1'b0 ; - end - end - end - - assign tpoll = itpoll ; - - always @(posedge clk) - begin : tap_reg_proc - if (rst) - begin - tapcnt <= {3{1'b1}} ; - end - else - begin - if (((csr0_tap == 3'b001 | - csr0_tap == 3'b010 | - csr0_tap == 3'b011) & (tcs2048 | tapwr)) | - ((csr0_tap == 3'b100 | - csr0_tap == 3'b101 | - csr0_tap == 3'b110 | - csr0_tap == 3'b111) & (tcs128 | tapwr))) - begin - if (tapcnt == 3'b000 | tapwr) - begin - case (csr0_tap) - 3'b001 : - begin - tapcnt <= 3'b000 ; - end - 3'b010 : - begin - tapcnt <= 3'b010 ; - end - 3'b011 : - begin - tapcnt <= 3'b110 ; - end - 3'b100 : - begin - tapcnt <= 3'b000 ; - end - 3'b101 : - begin - tapcnt <= 3'b001 ; - end - 3'b110 : - begin - tapcnt <= 3'b010 ; - end - default : - begin - tapcnt <= 3'b111 ; - end - endcase - end - else - begin - tapcnt <= tapcnt - 1 ; - end - end - end - end - - assign tm = {csr6_ttm, csr6_tr} ; - - assign sf = csr6_sf ; - - always @(posedge clk) - begin : tim_reg_proc - if (rst) - begin - timprog <= 1'b0 ; - timex <= 1'b0 ; - ttcnt <= {8{1'b1}} ; - tcnt <= {3{1'b1}} ; - end - else - begin - if (csr5_ti) - begin - timprog <= 1'b0 ; - end - else if (tireq_r & !tireq_r2) - begin - timprog <= 1'b1 ; - end - - if (csr5_ti) - begin - timex <= 1'b0 ; - end - else if (timprog & - ((ttcnt == 8'b00000000 & csr11_tt != 4'b0000) | - (tcnt == 3'b000 & csr11_ntp != 3'b000) | - (iic) | - (csr11_tt == 4'b0000 & csr11_ntp == 3'b000))) - begin - timex <= 1'b1 ; - end - - if ((tireq_r & !tireq_r2) | csr5_ti | csr11wr) - begin - ttcnt <= {csr11_tt, 4'b0000} ; - end - else if (((tcs128 & csr11_cs) | - (tcs2048 & !csr11_cs)) & - ttcnt != 8'b00000000 & timprog) - begin - ttcnt <= ttcnt - 1 ; - end - - if (csr5_ti | csr11wr) - begin - tcnt <= csr11_ntp ; - end - else if (tireq_r & !tireq_r2 & - tcnt != 3'b000 & csr11_ntp != 3'b000) - begin - tcnt <= tcnt - 1 ; - end - end - end - - always @(posedge clk) - begin : tcscnt_reg_proc - if (rst) - begin - tcsreq_r1 <= 1'b0 ; - tcsreq_r2 <= 1'b0 ; - tcs2048 <= 1'b0 ; - tcs128 <= 1'b0 ; - tcscnt <= {4{1'b1}} ; - end - else - begin - tcsreq_r1 <= tcsreq ; - tcsreq_r2 <= tcsreq_r1 ; - - if (tcs128) - begin - if (tcscnt == 4'b0000) - begin - tcscnt <= 4'b1111 ; - end - else - begin - tcscnt <= tcscnt - 1 ; - end - end - - if (tcsreq_r1 & !tcsreq_r2) - begin - tcs128 <= 1'b1 ; - end - else - begin - tcs128 <= 1'b0 ; - end - - if (tcscnt == 4'b0000 & tcs128) - begin - tcs2048 <= 1'b1 ; - end - else - begin - tcs2048 <= 1'b0 ; - end - - end - end - - assign tcsack = tcsreq_r2 ; - - always @(posedge clk) - begin : st_reg_proc - if (rst) - begin - tstopcmd <= 1'b1 ; - tstartcmd <= 1'b0 ; - end - else - begin - if (tstartcmd) - begin - tstopcmd <= 1'b0 ; - end - else if (!csrrw & csrreq & !(csrdata_c[13]) & - csraddr72 == CSR6_ID & (csrdbe_c[1])) - begin - tstopcmd <= 1'b1 ; - end - - if (tpsm == PSM_RUN | tpsm == PSM_SUSPEND) - begin - tstartcmd <= 1'b0 ; - end - else if (!csrrw & csrreq & (csrdata_c[13]) & - csraddr72 == CSR6_ID & (csrdbe_c[1])) - begin - tstartcmd <= 1'b1 ; - end - - end - end - - assign ts_c = (tpsm == PSM_STOP) ? 3'b000 : - (tpsm == PSM_SUSPEND) ? 3'b110 : - (tstat) ? 3'b111 : - (tdes) ? 3'b001 : - (tset) ? 3'b101 : - (tbuf) ? 3'b011 : - (tprog) ? 3'b010 : - csr5_ts ; - - always @(posedge clk) - begin : tpsack_reg_proc - if (rst) - begin - stoptc_r <= 1'b0 ; - stoptlsm_r <= 1'b0 ; - stoptfifo_r <= 1'b0 ; - end - else - begin - stoptc_r <= stoptc ; - stoptlsm_r <= stoptlsm ; - stoptfifo_r <= stoptfifo ; - end - end - - always @(tpsm or - tstartcmd or - tstopcmd or - tu_r or - stoptc_r or - stoptlsm_r or - stoptfifo_r) - begin : tpsm_proc - case (tpsm) - PSM_STOP : - begin - if (tstartcmd & !stoptc_r & !stoptlsm_r & !stoptfifo_r) - begin - tpsm_c <= PSM_RUN ; - end - else - begin - tpsm_c <= PSM_STOP ; - end - end - PSM_SUSPEND : - begin - if (tstopcmd & stoptc_r & stoptlsm_r & stoptfifo_r) - begin - tpsm_c <= PSM_STOP ; - end - else if (!tu_r) - begin - tpsm_c <= PSM_RUN ; - end - else - begin - tpsm_c <= PSM_SUSPEND ; - end - end - default : - begin - if (tstopcmd & stoptc_r & stoptlsm_r & stoptfifo_r) - begin - tpsm_c <= PSM_STOP ; - end - else if (tu_r) - begin - tpsm_c <= PSM_SUSPEND ; - end - else - begin - tpsm_c <= PSM_RUN ; - end - end - endcase - end - - always @(posedge clk) - begin : tpsm_reg_proc - if (rst) - begin - tpsm <= PSM_STOP ; - end - else - begin - tpsm <= tpsm_c ; - end - end - - always @(posedge clk) - begin : tps_reg_proc - if (rst) - begin - tps <= 1'b0 ; - end - else - begin - if (tstartcmd) - begin - tps <= 1'b0 ; - end - else if (tpsm == PSM_STOP) - begin - tps <= 1'b1 ; - end - end - end - - assign stopt = tstopcmd ; - - assign ren = csr6_sr ; - - assign fd = csr6_fd ; - - assign ra = csr6_ra ; - - assign pm = csr6_pm ; - - assign pr = csr6_pr ; - - assign rif = csr6_if ; - - assign pb = csr6_pb ; - - assign ho = csr6_ho ; - - assign hp = csr6_hp ; - - always @(posedge clk) - begin : rpoll_reg_proc - if (rst) - begin - rpoll <= 1'b0 ; - end - else - begin - if (rpollcmd | rstartcmd) - begin - rpoll <= 1'b1 ; - end - else if (rpollack) - begin - rpoll <= 1'b0 ; - end - end - end - - assign rs_c = (rpsm == PSM_STOP) ? 3'b000 : - (rpsm == PSM_SUSPEND) ? 3'b100 : - (rstat) ? 3'b101 : - (rdes) ? 3'b001 : - (rbuf) ? 3'b111 : - (rprog) ? 3'b010 : - 3'b011 ; - - always @(posedge clk) - begin : rpsack_reg_proc - if (rst) - begin - stoprc_r <= 1'b0 ; - stoprlsm_r <= 1'b0 ; - end - else - begin - stoprc_r <= stoprc ; - stoprlsm_r <= stoprlsm ; - end - end - - always @(rpsm or - rstartcmd or - rstopcmd or - rui or - ru_r or - stoprc_r or - stoprlsm_r) - begin : rpsm_proc - case (rpsm) - PSM_STOP : - begin - if (rstartcmd & !stoprc_r & !stoprlsm_r) - begin - rpsm_c <= PSM_RUN ; - end - else - begin - rpsm_c <= PSM_STOP ; - end - end - PSM_SUSPEND : - begin - if (rstopcmd & stoprc_r & stoprlsm_r) - begin - rpsm_c <= PSM_STOP ; - end - else if (!ru_r) - begin - rpsm_c <= PSM_RUN ; - end - else - begin - rpsm_c <= PSM_SUSPEND ; - end - end - default : - begin - if (rstopcmd & stoprc_r & stoprlsm_r) - begin - rpsm_c <= PSM_STOP ; - end - else if (rui) - begin - rpsm_c <= PSM_SUSPEND ; - end - else - begin - rpsm_c <= PSM_RUN ; - end - end - endcase - end - - always @(posedge clk) - begin : rpsm_reg_proc - if (rst) - begin - rpsm <= PSM_STOP ; - end - else - begin - rpsm <= rpsm_c ; - end - end - - always @(posedge clk) - begin : rps_reg_proc - if (rst) - begin - rps <= 1'b0 ; - end - else - begin - if (rstartcmd) - begin - rps <= 1'b0 ; - end - else if (rpsm == PSM_STOP) - begin - rps <= 1'b1 ; - end - end - end - - always @(posedge clk) - begin : rstartcmd_reg_proc - if (rst) - begin - rstartcmd <= 1'b0 ; - rstopcmd <= 1'b0 ; - end - else - begin - if (rpsm == PSM_RUN) - begin - rstartcmd <= 1'b0 ; - end - else if (!csrrw & csrreq & (csrdata_c[1]) & - csraddr72 == CSR6_ID & (csrdbe_c[0])) - begin - rstartcmd <= 1'b1 ; - end - - if (rpsm == PSM_STOP) - begin - rstopcmd <= 1'b0 ; - end - else if (!csrrw & csrreq & !(csrdata_c[1]) & - csraddr72 == CSR6_ID & (csrdbe_c[0])) - begin - rstopcmd <= 1'b1 ; - end - end - end - - assign stopr = rstopcmd ; - - always @(posedge clk) - begin : rim_reg_proc - if (rst) - begin - rimex <= 1'b0 ; - rimprog <= 1'b0 ; - rtcnt <= {4{1'b1}} ; - rcnt <= {3{1'b1}} ; - end - else - begin - if (csr5_ri) - begin - rimex <= 1'b0 ; - end - else if (rimprog & - ((rtcnt == 4'b0000 & csr11_rt != 4'b0000) | - (rcnt == 3'b000 & csr11_nrp != 3'b000) | - (csr11_rt == 4'b0000 & csr11_nrp == 3'b000))) - begin - rimex <= 1'b1 ; - end - - if (csr5_ri) - begin - rimprog <= 1'b0 ; - end - else if (rireq_r & !rireq_r2) - begin - rimprog <= 1'b1 ; - end - - if ((rireq_r & !rireq_r2) | csr5_ri) - begin - rtcnt <= csr11_rt ; - end - else if (((rcs128 & csr11_cs) | - (rcs2048 & !csr11_cs)) & - rtcnt != 4'b0000 & rimprog) - begin - rtcnt <= rtcnt - 1 ; - end - - if (csr5_ri | csr11wr) - begin - rcnt <= csr11_nrp ; - end - else if (rireq_r & !rireq_r2 & - rcnt != 3'b000 & csr11_nrp != 3'b000) - begin - rcnt <= rcnt - 1 ; - end - - end - end - - always @(posedge clk) - begin : rcscnt_reg_proc - if (rst) - begin - rcsreq_r <= 1'b0 ; - rcsreq_r1 <= 1'b0 ; - rcscnt <= {4{1'b1}} ; - rcs128 <= 1'b0 ; - rcs2048 <= 1'b0 ; - end - else - begin - - rcsreq_r <= rcsreq ; - rcsreq_r1 <= rcsreq_r ; - - if (rcs128) - begin - if (rcscnt == 4'b0000) - begin - rcscnt <= 4'b1111 ; - end - else - begin - rcscnt <= rcscnt - 1 ; - end - end - - if (rcsreq_r & !rcsreq_r1) - begin - rcs128 <= 1'b1 ; - end - else - begin - rcs128 <= 1'b0 ; - end - - if (rcscnt == 4'b0000 & rcs128) - begin - rcs2048 <= 1'b1 ; - end - else - begin - rcs2048 <= 1'b0 ; - end - end - end - - assign rcsack = rcsreq_r ; - - always @(posedge clk) - begin : ireq_reg_proc - if (rst) - begin - rireq_r <= 1'b0 ; - rireq_r2 <= 1'b0 ; - erireq_r <= 1'b0 ; - erireq_r2 <= 1'b0 ; - tireq_r <= 1'b0 ; - tireq_r2 <= 1'b0 ; - etireq_r <= 1'b0 ; - etireq_r2 <= 1'b0 ; - unf_r <= 1'b0 ; - unf_r2 <= 1'b0 ; - tu_r <= 1'b0 ; - tu_r2 <= 1'b0 ; - ru_r <= 1'b0 ; - ru_r2 <= 1'b0 ; - end - else - begin - rireq_r <= rireq ; - rireq_r2 <= rireq_r ; - erireq_r <= erireq ; - erireq_r2 <= erireq_r ; - tireq_r <= tireq ; - tireq_r2 <= tireq_r ; - etireq_r <= etireq ; - etireq_r2 <= etireq_r ; - unf_r <= unf ; - unf_r2 <= unf_r ; - tu_r <= tu ; - tu_r2 <= tu_r ; - ru_r <= ru ; - ru_r2 <= ru_r ; - end - end - - always @(posedge clk) - begin : iic_reg_proc - if (rst) - begin - iic <= 1'b0 ; - end - else - begin - if (tireq_r & !tireq_r2) - begin - if (!ic & !iint) - begin - iic <= 1'b0 ; - end - else - begin - iic <= 1'b1 ; - end - end - end - end - - always @(posedge clk) - begin : eti_reg_proc - if (rst) - begin - eti <= 1'b0 ; - end - else - begin - if (etireq_r & !etireq_r2) - begin - eti <= 1'b1 ; - end - else if (!csr5wr_c) - begin - eti <= 1'b0 ; - end - end - end - - assign etiack = etireq_r2 ; - - always @(posedge clk) - begin : eri_reg_proc - if (rst) - begin - eri <= 1'b0 ; - end - else - begin - if (erireq_r & !erireq_r2) - begin - eri <= 1'b1 ; - end - else if (!csr5wr_c) - begin - eri <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : unfi_reg_proc - if (rst) - begin - unfi <= 1'b0 ; - end - else - begin - if (unf_r & !unf_r2) - begin - unfi <= 1'b1 ; - end - else if (!csr5wr_c) - begin - unfi <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : tui_reg_proc - if (rst) - begin - tui <= 1'b0 ; - end - else - begin - if (tu_r & !tu_r2) - begin - tui <= 1'b1 ; - end - else if (!csr5wr_c) - begin - tui <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : rui_reg_proc - if (rst) - begin - rui <= 1'b0 ; - end - else - begin - if (ru_r & !ru_r2) - begin - rui <= 1'b1 ; - end - else if (!csr5wr_c) - begin - rui <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : iint_reg_proc - if (rst) - begin - iint <= 1'b0 ; - end - else - begin - iint <= ((csr5_nis && csr7_nie) || - (csr5_ais && csr7_aie)) && ~csr5wr; - end - end - - assign interrupt = iint ; - - assign riack = rireq_r2 ; - - assign eriack = erireq_r2 ; - - assign tiack = tireq_r2 ; - - always @(focg_r) - begin : foc_proc - reg [10:0] foc_v; - - foc_v[10] = focg_r[10] ; - begin : foc_loop - integer i; - for(i = 9; i >= 0; i = i - 1) - begin - foc_v[i] = foc_v[i + 1] ^ focg_r[i] ; - end - end - foc_c = foc_v; - end - - always @(mfcg_r) - begin : mfc_proc - reg [15:0] mfc_v; - - mfc_v[15] = mfcg_r[10] ; - begin : mfc_loop - integer i; - for(i = 14; i >= 0; i = i - 1) - begin - mfc_v[i] = mfc_v[i + 1] ^ mfcg_r[i] ; - end - end - mfc_c = mfc_v; - end - - always @(posedge clk) - begin : sc_reg_proc - if (rst) - begin - focl <= 1'b0 ; - mfcl <= 1'b0 ; - focg_r <= {11{1'b0}} ; - mfcg_r <= {16{1'b0}} ; - end - else - begin - if (csr8read) - begin - focl <= 1'b1 ; - end - else if (foclack) - begin - focl <= 1'b0 ; - end - - if (csr8read) - begin - mfcl <= 1'b1 ; - end - else if (mfclack) - begin - mfcl <= 1'b0 ; - end - - mfcg_r <= mfcg ; - - focg_r <= focg ; - - end - end - - assign mdo = csr9_mdo ; - - assign mden = csr9_mii ; - - assign mdc = csr9_mdc ; - - assign sclk = csr9_sclk ; - - assign scs = csr9_scs ; - - assign sdo = csr9_sdo ; - - always @(posedge clk) - begin : gpt_reg_proc - if (rst) - begin - gstart <= 1'b0 ; - gstart_r <= 1'b0 ; - gcnt <= {16{1'b0}} ; - gte <= 1'b0 ; - end - else - begin - if (!csrrw & csrreq & (csrdbe_c[3]) & csraddr72 == CSR11_ID) - begin - gstart <= 1'b1 ; - end - else if ((!csr11_con & gte) | - csr11_tim == 16'b0000000000000000) - begin - gstart <= 1'b0 ; - end - - if(csr11_tim != 16'b0000000000000000) - begin - gstart_r <= gstart ; - end - else - begin - gstart_r <= 1'b0 ; - end - - if (gstart & !gstart_r) - begin - gcnt <= csr11_tim ; - end - else if (gcnt == 16'b0000000000000000) - begin - if (csr11_con) - begin - gcnt <= csr11_tim ; - end - end - else if (tcs2048) - begin - gcnt <= gcnt - 1 ; - end - - if (csr5wr_c) - begin - gte <= 1'b0 ; - end - else if (gstart_r & gcnt == 16'b0000000000000000 & - csr11_tim != 16'b0000000000000000) - begin - gte <= 1'b1 ; - end - - end - end - - always @(posedge clk) - begin : rstsofto_reg_proc - rstsofto <= csr0_swr; - end - - assign czero_max = {CSRWIDTH_MAX{1'b0}} ; - - assign csrdatai_max = {czero_max[CSRWIDTH_MAX+1:CSRWIDTH], - csrdatai}; - - assign csrbe_max = {czero_max[CSRWIDTH_MAX/8+1:CSRWIDTH/8], - csrbe}; - -endmodule - - - -module DMA_V ( - clk, - rst, - dma_priority, - ble, - dbo, - rdes, - rbuf, - rstat, - tdes, - tbuf, - tstat, - dataack, - datai, - datareq, - datareqc, - datarw, - dataeob, - dataeobc, - datao, - dataaddr, - idataaddr, - req1, - write1, - tcnt1, - addr1, - datai1, - ack1, - eob1, - datao1, - req2, - write2, - tcnt2, - addr2, - datai2, - ack2, - eob2, - datao2); - - parameter DATAWIDTH = 32; - parameter DATADEPTH = 32; - - `include "utility.v" - - input clk; - input rst; - - input [1:0] dma_priority; - input ble; - input dbo; - input rdes; - input rbuf; - input rstat; - input tdes; - input tbuf; - input tstat; - - - input dataack; - input [DATAWIDTH - 1:0] datai; - output datareq; - wire datareq; - output datareqc; - wire datareqc; - output datarw; - reg datarw; - output dataeob; - wire dataeob; - output dataeobc; - wire dataeobc; - output [DATAWIDTH - 1:0] datao; - wire [DATAWIDTH - 1:0] datao; - output [DATADEPTH - 1:0] dataaddr; - wire [DATADEPTH - 1:0] dataaddr; - output [DATADEPTH - 1:0] idataaddr; - wire [DATADEPTH - 1:0] idataaddr; - - input req1; - input write1; - input [FIFODEPTH_MAX - 1:0] tcnt1; - input [DATADEPTH - 1:0] addr1; - input [DATAWIDTH - 1:0] datai1; - output ack1; - wire ack1; - output eob1; - wire eob1; - output [DATAWIDTH - 1:0] datao1; - wire [DATAWIDTH - 1:0] datao1; - - input req2; - input write2; - input [FIFODEPTH_MAX - 1:0] tcnt2; - input [DATADEPTH - 1:0] addr2; - input [DATAWIDTH - 1:0] datai2; - output ack2; - wire ack2; - output eob2; - wire eob2; - output [DATAWIDTH - 1:0] datao2; - wire [DATAWIDTH - 1:0] datao2; - - - reg [1:0] dsm_c; - reg [1:0] dsm; - reg hist1; - reg hist2; - wire [1:0] dmareq; - reg [FIFODEPTH_MAX - 1:0] msmbcnt; - reg idatareq; - reg idatareqc; - reg eob; - reg eobc; - reg [DATADEPTH - 1:0] addr_c; - reg [DATADEPTH - 1:0] addr; - reg blesel_c; - reg [DATAWIDTH - 1:0] dataible_c; - reg [DATAWIDTH - 1:0] dataoble_c; - wire [DATAWIDTH_MAX + 1:0] datai_max; - reg req_c; - reg write_c; - reg [FIFODEPTH_MAX - 1:0] tcnt_c; - reg [DATADEPTH - 1:0] saddr_c; - reg [DATAWIDTH_MAX - 1:0] datai_c; - wire [DATAWIDTH_MAX + 1:0] datai_max_c; - wire [FIFODEPTH_MAX - 1:0] fzero; - wire [DATAWIDTH_MAX + 1:0] dzero; - - assign dmareq = {req2, req1} ; - - always @(dsm or - dmareq or - hist1 or - hist2 or - dma_priority or - eob or - dataack) - begin : dsm_proc - case (dsm) - DSM_IDLE : - begin - case (dmareq) - 2'b11 : - begin - case (dma_priority) - 2'b01 : - begin - if (!hist1 & !hist2) - begin - dsm_c <= DSM_CH2 ; - end - else - begin - dsm_c <= DSM_CH1 ; - end - end - 2'b10 : - begin - if (hist1 & hist2) - begin - dsm_c <= DSM_CH1 ; - end - else - begin - dsm_c <= DSM_CH2 ; - end - end - default : - begin - if (hist1) - begin - dsm_c <= DSM_CH1 ; - end - else - begin - dsm_c <= DSM_CH2 ; - end - end - endcase - end - 2'b01 : - begin - dsm_c <= DSM_CH1 ; - end - 2'b10 : - begin - dsm_c <= DSM_CH2 ; - end - default : - begin - dsm_c <= DSM_IDLE ; - end - endcase - end - DSM_CH1 : - begin - if (eob & dataack) - begin - dsm_c <= DSM_IDLE ; - end - else - begin - dsm_c <= DSM_CH1 ; - end - end - default : - begin - if (eob & dataack) - begin - dsm_c <= DSM_IDLE ; - end - else - begin - dsm_c <= DSM_CH2 ; - end - end - endcase - end - - always @(posedge clk) - begin : dsm_reg_proc - if (rst) - begin - dsm <= DSM_IDLE ; - end - else - begin - dsm <= dsm_c ; - end - end - - always @(posedge clk) - begin : hist_reg_proc - if (rst) - begin - hist1 <= 1'b1 ; - hist2 <= 1'b1 ; - end - else - begin - if (eob) - begin - case (dsm) - DSM_CH1 : - begin - hist1 <= 1'b1 ; - end - DSM_CH2 : - begin - hist1 <= 1'b0 ; - end - default : - begin - hist1 <= hist1 ; - end - endcase - end - hist2 <= hist1 ; - end - end - - always @(dbo or - ble or - dsm_c or - dsm or - tdes or - tbuf or - tstat or - rdes or - rbuf or - rstat) - begin : blesel_proc - if (dsm_c == DSM_CH1 | dsm == DSM_CH1) - begin - if ((tbuf & ble) | - ((tdes | tstat) & dbo)) - begin - blesel_c <= 1'b1 ; - end - else - begin - blesel_c <= 1'b0 ; - end - end - else - begin - if ((rbuf & ble) | - ((rdes | rstat) & dbo)) - begin - blesel_c <= 1'b1 ; - end - else - begin - blesel_c <= 1'b0 ; - end - end - end - - always @(dsm_c or - dsm or - req1 or - write1 or - tcnt1 or - addr1 or - datai1 or - req2 or - write2 or - tcnt2 or - addr2 or - datai2) - begin : chmux_proc - if (dsm_c == DSM_CH1 | dsm == DSM_CH1) - begin - req_c <= req1 ; - write_c <= write1 ; - tcnt_c <= tcnt1 ; - saddr_c <= addr1 ; - datai_c <= {{((DATAWIDTH_MAX+1)-DATAWIDTH){1'b0}},datai1} ; - end - else - begin - req_c <= req2 ; - write_c <= write2 ; - tcnt_c <= tcnt2 ; - saddr_c <= addr2 ; - datai_c <= {{((DATAWIDTH_MAX+1)-DATAWIDTH){1'b0}},datai2} ; - end - end - - assign datai_max_c = {dzero[DATAWIDTH_MAX+1:DATAWIDTH],datai_c}; - - always @(datai_max_c or blesel_c) - begin : dataoble_proc - case (DATAWIDTH) - 32 : - begin - if (blesel_c) - begin - dataoble_c <= {datai_max_c[ 7: 0], - datai_max_c[15: 8], - datai_max_c[23:16], - datai_max_c[31:24]}; - end - else - begin - dataoble_c <= datai_max_c[31:0]; - end - end - 16 : - begin - if (blesel_c) - begin - dataoble_c <= {datai_max_c[7 :0], - datai_max_c[15:8]}; - end - else - begin - dataoble_c <= datai_max_c[15:0]; - end - end - default : - begin - dataoble_c <= datai_max_c[7:0]; - end - endcase - end - - assign datai_max = {dzero[DATAWIDTH_MAX+1:DATAWIDTH],datai}; - - always @(datai_max or blesel_c) - begin : dataible_proc - case (DATAWIDTH) - 32 : - begin - if (blesel_c) - begin - dataible_c <= {datai_max[ 7: 0], - datai_max[15: 8], - datai_max[23:16], - datai_max[31:24]}; - end - else - begin - dataible_c <= datai_max[31:0]; - end - end - 16 : - begin - if (blesel_c) - begin - dataible_c <= {datai_max[7 :0], - datai_max[15:8]}; - end - else - begin - dataible_c <= datai_max[15:0]; - end - end - default : - begin - dataible_c <= datai_max[7:0]; - end - endcase - end - - always @(posedge clk) - begin : msmbcnt_reg_proc - if (rst) - begin - msmbcnt <= {FIFODEPTH_MAX{1'b0}} ; - end - else - begin - if (!idatareq) - begin - msmbcnt <= tcnt_c ; - end - else if (dataack & idatareq) - begin - msmbcnt <= msmbcnt - 1 ; - end - end - end - - always @(posedge clk) - begin : datarw_reg_proc - if (rst) - begin - datarw <= 1'b1 ; - end - else - begin - if (req_c) - begin - datarw <= ~write_c ; - end - end - end - - always @(posedge clk) - begin : idatareq_reg_proc - if (rst) - begin - idatareq <= 1'b0 ; - end - else - begin - if (eob & dataack & idatareq) - begin - idatareq <= 1'b0 ; - end - else if (req1 | req2) - begin - idatareq <= 1'b1 ; - end - end - end - - assign datareq = idatareq ; - - always @(idatareq or - dataack or - req1 or - req2 or - eob - ) - begin : idatareqc_comb_proc - if (eob & dataack & idatareq) - begin - idatareqc <= 1'b0 ; - end - else if (req1 | req2) - begin - idatareqc <= 1'b1 ; - end - else - begin - idatareqc <= idatareq ; - end - end - - assign datareqc = idatareqc ; - - assign dataeob = eob ; - - assign dataeobc = eobc ; - - assign datao1 = dataible_c ; - - assign datao2 = dataible_c ; - - assign datao = dataoble_c ; - - always @(dataack or - idatareq or - addr or - saddr_c or - req_c or - dsm) - begin : addr_proc - if (dataack & idatareq) - begin - case (DATAWIDTH) - 8 : - begin - addr_c <= addr + 1 ; - end - 16 : - begin - addr_c <= {addr[DATADEPTH - 1:1] + 1, 1'b0} ; - end - default : - begin - addr_c <= {addr[DATADEPTH - 1:2] + 1, 2'b00} ; - end - endcase - end - else if (req_c & dsm == DSM_IDLE) - begin - addr_c <= saddr_c ; - end - else - begin - addr_c <= addr ; - end - end - - always @(posedge clk) - begin : addr_reg_proc - if (rst) - begin - addr <= {DATADEPTH{1'b1}} ; - end - else - begin - addr <= addr_c ; - end - end - - assign dataaddr = addr ; - - assign idataaddr = addr ; - - assign ack1 = (dataack & dsm == DSM_CH1) ? 1'b1 : 1'b0 ; - - assign ack2 = (dataack & dsm == DSM_CH2) ? 1'b1 : 1'b0 ; - - always @(posedge clk) - begin : eob_reg_proc - if (rst) - begin - eob <= 1'b0 ; - end - else if (req_c | idatareq) - begin - if ((idatareq & - (msmbcnt == fzero | - msmbcnt == {fzero[FIFODEPTH_MAX-1:1], 1'b1} | - (msmbcnt == {fzero[FIFODEPTH_MAX-1:2], 2'b10} & dataack))) - | - (!idatareq & - (tcnt_c == fzero | - tcnt_c == {fzero[FIFODEPTH_MAX-1:1], 1'b1}))) - begin - eob <= 1'b1 ; - end - else - begin - eob <= 1'b0 ; - end - end - end - - always @(req_c or - idatareq or - msmbcnt or - dataack or - tcnt_c or - fzero or - eob) - begin : eob_comb_proc - if (req_c | idatareq) - begin - if ((idatareq & - (msmbcnt == fzero | - msmbcnt == {fzero[FIFODEPTH_MAX-1:1], 1'b1} | - (msmbcnt == {fzero[FIFODEPTH_MAX-1:2], 2'b10} & dataack))) - | - (!idatareq & - (tcnt_c == fzero | - tcnt_c == {fzero[FIFODEPTH_MAX-1:1], 1'b1}))) - begin - eobc <= 1'b1 ; - end - else - begin - eobc <= 1'b0 ; - end - end - else - begin - eobc <= eob; - end - end - - assign eob1 = eob ; - - assign eob2 = eob ; - - assign fzero = {FIFODEPTH_MAX{1'b0}} ; - - assign dzero = {(DATAWIDTH_MAX+1){1'b0}} ; - -endmodule - - -module MAC_V ( - clkdma, - clkcsr, - rstcsr, - clkt, - clkr, - rsttco, - rstrco, - interrupt, - tps, - rps, - csrreq, - csrrw, - csrbe, - csrdatai, - csraddr, - csrack, - csrdatao, - dataack, - datareq, - datareqc, - datarw, - dataeob, - dataeobc, - datai, - dataaddr, - datao, - trdata, - twe, - twaddr, - traddr, - twdata, - rrdata, - rwe, - rwaddr, - rraddr, - rwdata, - frdata, - fwe, - fwaddr, - fraddr, - fwdata, - match, - matchval, - matchen, - matchdata, - sdi, - sclk, - scs, - sdo, - rxer, - rxdv, - col, - crs, - rxd, - txen, - txer, - txd, - mdc, - mdi, - mdo, - mden - ); - - parameter CSRWIDTH = 32; - parameter DATAWIDTH = 32; - parameter DATADEPTH = 32; - parameter TFIFODEPTH = 9; - parameter RFIFODEPTH = 9; - parameter TCDEPTH = 1; - parameter RCDEPTH = 2; - - `include "utility.v" - - input clkdma; - input clkcsr; - input rstcsr; - input clkt; - input clkr; - output rsttco; - wire rsttco; - output rstrco; - wire rstrco; - - output interrupt; - wire interrupt; - - output tps; - wire tps; - output rps; - wire rps; - - input csrreq; - input csrrw; - input [CSRWIDTH / 8 - 1:0] csrbe; - input [CSRWIDTH - 1:0] csrdatai; - input [CSRDEPTH - 1:0] csraddr; - output csrack; - wire csrack; - output [CSRWIDTH - 1:0] csrdatao; - wire [CSRWIDTH - 1:0] csrdatao; - - input dataack; - output datareq; - wire datareq; - output datareqc; - wire datareqc; - output datarw; - wire datarw; - output dataeob; - wire dataeob; - output dataeobc; - wire dataeobc; - input [DATAWIDTH - 1:0] datai; - output [DATADEPTH - 1:0] dataaddr; - wire [DATADEPTH - 1:0] dataaddr; - output [DATAWIDTH - 1:0] datao; - wire [DATAWIDTH - 1:0] datao; - - input [DATAWIDTH - 1:0] trdata; - output twe; - wire twe; - output [TFIFODEPTH - 1:0] twaddr; - wire [TFIFODEPTH - 1:0] twaddr; - output [TFIFODEPTH - 1:0] traddr; - wire [TFIFODEPTH - 1:0] traddr; - output [DATAWIDTH - 1:0] twdata; - wire [DATAWIDTH - 1:0] twdata; - - input [DATAWIDTH - 1:0] rrdata; - output rwe; - wire rwe; - output [RFIFODEPTH - 1:0] rwaddr; - wire [RFIFODEPTH - 1:0] rwaddr; - output [RFIFODEPTH - 1:0] rraddr; - wire [RFIFODEPTH - 1:0] rraddr; - output [DATAWIDTH - 1:0] rwdata; - wire [DATAWIDTH - 1:0] rwdata; - - input [15:0] frdata; - output fwe; - wire fwe; - output [ADDRDEPTH - 1:0] fwaddr; - wire [ADDRDEPTH - 1:0] fwaddr; - output [ADDRDEPTH - 1:0] fraddr; - wire [ADDRDEPTH - 1:0] fraddr; - output [15:0] fwdata; - wire [15:0] fwdata; - - input match; - input matchval; - output matchen; - wire matchen; - output [47:0] matchdata; - wire [47:0] matchdata; - - input sdi; - output sclk; - wire sclk; - output scs; - wire scs; - output sdo; - wire sdo; - - input rxer; - input rxdv; - input col; - input crs; - input [MIIWIDTH - 1:0] rxd; - output txen; - wire txen; - output txer; - wire txer; - output [MIIWIDTH - 1:0] txd; - wire [MIIWIDTH - 1:0] txd; - output mdc; - wire mdc; - input mdi; - output mdo; - wire mdo; - output mden; - wire mden; - - - wire rstsoft; - wire rsttc; - wire rstrc; - wire rstdmao; - wire rstcsro; - - wire [5:0] pbl; - wire ac; - wire dpd; - wire [4:0] dsl; - wire tpoll; - wire [DATADEPTH - 1:0] tdbad; - wire sf; - wire [2:0] tm; - wire fd; - wire ble; - wire dbo; - wire ra; - wire pm; - wire pr; - wire pb; - wire rif; - wire ho; - wire hp; - wire rpoll; - wire rpollack; - wire [DATADEPTH - 1:0] rdbad; - - wire tdes; - wire tbuf; - wire tset; - wire tstat; - wire tu; - wire [1:0] ft; - wire rdes; - wire rstat; - wire ru; - wire rcomp; - wire rcompack; - wire tcomp; - wire tcompack; - - wire [1:0] dma_priority; - wire treq; - wire twrite; - wire [FIFODEPTH_MAX - 1:0] tcnt; - wire [DATADEPTH - 1:0] taddr; - wire [DATAWIDTH - 1:0] tdatai; - wire tack; - wire teob; - wire [DATAWIDTH - 1:0] tdatao; - wire rreq; - wire rwrite; - wire [FIFODEPTH_MAX - 1:0] rcnt; - wire [DATADEPTH - 1:0] raddr; - wire [DATAWIDTH - 1:0] rdatai; - wire rack; - wire reob; - wire [DATAWIDTH - 1:0] rdatao; - wire [DATADEPTH - 1:0] idataaddr; - - wire tfifonf; - wire tfifocnf; - wire tfifoval; - wire tfifowe; - wire tfifoeof; - wire [DATAWIDTH / 8 - 1:0] tfifobe; - wire [DATAWIDTH - 1:0] tfifodata; - wire [TFIFODEPTH - 1:0] tfifolev; - wire [TFIFODEPTH - 1:0] tradg; - - wire etiack; - wire etireq; - wire tcsne; - wire tcachere; - wire ic; - wire ici; - wire aci; - wire dpdi; - wire lo_o; - wire nc_o; - wire lc_o; - wire ec_o; - wire de_o; - wire ur_o; - wire [3:0] cc_o; - wire lo_i; - wire nc_i; - wire lc_i; - wire ec_i; - wire de_i; - wire ur_i; - wire [3:0] cc_i; - - wire tpollack; - wire tdbadc; - wire [DATADEPTH - 1:0] statado; - wire [DATADEPTH - 1:0] statadi; - - wire sofreq; - wire eofreq; - wire [DATAWIDTH / 8 - 1:0] be; - wire [TFIFODEPTH - 1:0] eofad; - wire [TFIFODEPTH - 1:0] twadg; - wire tireq; - wire tiack; - wire winp; - - wire coll; - wire carrier; - wire bkoff; - wire tpend; - wire tprog; - wire preamble; - - wire tcsreq; - wire tcsack; - - wire stopt; - wire stoptc; - wire stoptfifo; - wire stoptlsm; - - wire [RFIFODEPTH - 1:0] rradg; - wire [RFIFODEPTH - 1:0] rwadg; - wire rfifore; - wire [DATAWIDTH - 1:0] rfifodata; - wire rcachere; - wire rcachene; - wire rcachenf; - wire [DATAWIDTH - 1:0] irwdata; - wire irwe; - - wire riack; - wire ren; - wire rireq; - wire ff; - wire rf; - wire mf; - wire db; - wire re; - wire ce; - wire tl; - wire ftp; - wire ov; - wire cs; - wire [13:0] length; - wire rprog; - wire rcpoll; - - - wire ff_o; - wire rf_o; - wire mf_o; - wire tl_o; - wire re_o; - wire db_o; - wire ce_o; - wire ov_o; - wire cs_o; - wire [13:0] fl_o; - - wire rdbadc; - wire erireq; - wire eriack; - wire rbuf; - - wire foclack; - wire mfclack; - wire oco; - wire mfo; - wire [10:0] focg; - wire [15:0] mfcg; - wire focl; - wire mfcl; - - wire stopr; - wire stoprc; - wire stoprfifo; - wire stoprlsm; - - wire rcsack; - wire rcsreq; - - DMA_V #(DATAWIDTH, DATADEPTH) U_DMA( - .clk (clkdma), - .rst (rstdmao), - .dma_priority (dma_priority), - .ble (ble), - .dbo (dbo), - .rdes (rdes), - .rbuf (rbuf), - .rstat (rstat), - .tdes (tdes), - .tbuf (tbuf), - .tstat (tstat), - .dataack (dataack), - .datai (datai), - .datareq (datareq), - .datareqc (datareqc), - .datarw (datarw), - .dataeob (dataeob), - .dataeobc (dataeobc), - .datao (datao), - .dataaddr (dataaddr), - .idataaddr (idataaddr), - .req1 (treq), - .write1 (twrite), - .tcnt1 (tcnt), - .addr1 (taddr), - .datai1 (tdatao), - .ack1 (tack), - .eob1 (teob), - .datao1 (tdatai), - .req2 (rreq), - .write2 (rwrite), - .tcnt2 (rcnt), - .addr2 (raddr), - .datai2 (rdatao), - .ack2 (rack), - .eob2 (reob), - .datao2 (rdatai) - ); - - TLSM_V #(DATAWIDTH, DATADEPTH, TFIFODEPTH) U_TLSM( - .clk (clkdma), - .rst (rstdmao), - .fifonf (tfifonf), - .fifocnf (tfifocnf), - .fifoval (tfifoval), - .fifowe (tfifowe), - .fifoeof (tfifoeof), - .fifobe (tfifobe), - .fifodata (tfifodata), - .fifolev (tfifolev), - .ic (ici), - .ac (aci), - .dpd (dpdi), - .statado (statadi), - .csne (tcsne), - .lo (lo_i), - .nc (nc_i), - .lc (lc_i), - .ec (ec_i), - .de (de_i), - .ur (ur_i), - .cc (cc_i), - .cachere (tcachere), - .statadi (statado), - .dmaack (tack), - .dmaeob (teob), - .dmadatai (tdatai), - .dmaaddr (idataaddr), - .dmareq (treq), - .dmawr (twrite), - .dmacnt (tcnt), - .dmaaddro (taddr), - .dmadatao (tdatao), - .fwe (fwe), - .fdata (fwdata), - .faddr (fwaddr), - .dsl (dsl), - .pbl (pbl), - .poll (tpoll), - .dbadc (tdbadc), - .dbad (tdbad), - .pollack (tpollack), - .tcompack (tcompack), - .tcomp (tcomp), - .des (tdes), - .fbuf (tbuf), - .stat (tstat), - .setp (tset), - .tu (tu), - .ft (ft), - .stopi (stopt), - .stopo (stoptlsm) - ); - - TFIFO_V #(DATAWIDTH, DATADEPTH, TFIFODEPTH, TCDEPTH) U_TFIFO( - .clk (clkdma), - .rst (rstdmao), - .ramwe (twe), - .ramaddr (twaddr), - .ramdata (twdata), - .fifowe (tfifowe), - .fifoeof (tfifoeof), - .fifobe (tfifobe), - .fifodata (tfifodata), - .fifonf (tfifonf), - .fifocnf (tfifocnf), - .fifoval (tfifoval), - .flev (tfifolev), - .ici (ici), - .dpdi (dpdi), - .aci (aci), - .statadi (statadi), - .cachere (tcachere), - .deo (de_i), - .lco (lc_i), - .loo (lo_i), - .nco (nc_i), - .eco (ec_i), - .ico (ic), - .uro (ur_i), - .csne (tcsne), - .cco (cc_i), - .statado (statado), - .sofreq (sofreq), - .eofreq (eofreq), - .dpdo (dpd), - .aco (ac), - .beo (be), - .eofad (eofad), - .wadg (twadg), - .tireq (tireq), - .winp (winp), - .dei (de_o), - .lci (lc_o), - .loi (lo_o), - .nci (nc_o), - .eci (ec_o), - .uri (ur_o), - .cci (cc_o), - .radg (tradg), - .tiack (tiack), - .sf (sf), - .fdp (fd), - .tm (tm), - .pbl (pbl), - .etiack (etiack), - .etireq (etireq), - .stopi (stopt), - .stopo (stoptfifo) - ); - - TC_V #(TFIFODEPTH, DATAWIDTH) U_TC( - .clk (clkt), - .rst (rsttc), - .txen (txen), - .txer (txer), - .txd (txd), - .ramdata (trdata), - .ramaddr (traddr), - .wadg (twadg), - .radg (tradg), - .dpd (dpd), - .ac (ac), - .sofreq (sofreq), - .eofreq (eofreq), - .tiack (tiack), - .lastbe (be), - .eofadg (eofad), - .tireq (tireq), - .ur (ur_o), - .de (de_o), - .coll (coll), - .carrier (carrier), - .bkoff (bkoff), - .tpend (tpend), - .tprog (tprog), - .preamble (preamble), - .stopi (stopt), - .stopo (stoptc), - .tcsack (tcsack), - .tcsreq (tcsreq) - ); - - BD_V U_BD( - .clk (clkt), - .rst (rsttc), - .col (col), - .crs (crs), - .fdp (fd), - .tprog (tprog), - .preamble (preamble), - .tpend (tpend), - .winp (winp), - .tiack (tiack), - .coll (coll), - .carrier (carrier), - .bkoff (bkoff), - .lc (lc_o), - .lo (lo_o), - .nc (nc_o), - .ec (ec_o), - .cc (cc_o) - ); - - - - RC_V #(RFIFODEPTH, DATAWIDTH) U_RC( - .clk (clkr), - .rst (rstrc), - .col (col), - .rxdv (rxdv), - .rxer (rxer), - .rxd (rxd), - .ramwe (irwe), - .ramaddr (rwaddr), - .ramdata (irwdata), - .fdata (frdata), - .faddr (fraddr), - .cachenf (rcachenf), - .radg (rradg), - .wadg (rwadg), - .rprog (rprog), - .rcpoll (rcpoll), - .riack (riack), - .ren (ren), - .ra (ra), - .pm (pm), - .pr (pr), - .pb (pb), - .rif (rif), - .ho (ho), - .hp (hp), - .rireq (rireq), - .ff (ff), - .rf (rf), - .mf (mf), - .db (db), - .re (re), - .ce (ce), - .tl (tl), - .ftp (ftp), - .ov (ov), - .cs (cs), - .length (length), - .match (match), - .matchval (matchval), - .matchen (matchen), - .matchdata (matchdata), - .focl (focl), - .foclack (foclack), - .oco (oco), - .focg (focg), - .mfcl (mfcl), - .mfclack (mfclack), - .mfo (mfo), - .mfcg (mfcg), - .stopi (stopr), - .stopo (stoprc), - .rcsack (rcsack), - .rcsreq (rcsreq) - ); - - RFIFO_V #(DATAWIDTH, DATADEPTH, RFIFODEPTH, RCDEPTH) U_RFIFO( - .clk (clkdma), - .rst (rstdmao), - .ramdata (rrdata), - .ramaddr (rraddr), - .fifore (rfifore), - .ffo (ff_o), - .rfo (rf_o), - .mfo (mf_o), - .tlo (tl_o), - .reo (re_o), - .dbo (db_o), - .ceo (ce_o), - .ovo (ov_o), - .cso (cs_o), - .flo (fl_o), - .fifodata (rfifodata), - .cachere (rcachere), - .cachene (rcachene), - .cachenf (rcachenf), - .radg (rradg), - .rireq (rireq), - .ffi (ff), - .rfi (rf), - .mfi (mf), - .tli (tl), - .rei (re), - .dbi (db), - .cei (ce), - .ovi (ov), - .csi (cs), - .fli (length), - .wadg (rwadg), - .riack (riack) - ); - - RLSM_V #(DATAWIDTH, DATADEPTH, RFIFODEPTH) U_RLSM( - .clk (clkdma), - .rst (rstdmao), - .fifodata (rfifodata), - .fifore (rfifore), - .cachere (rcachere), - .dmaack (rack), - .dmaeob (reob), - .dmadatai (rdatai), - .dmaaddr (idataaddr), - .dmareq (rreq), - .dmawr (rwrite), - .dmacnt (rcnt), - .dmaaddro (raddr), - .dmadatao (rdatao), - .rprog (rprog), - .rcpoll (rcpoll), - .fifocne (rcachene), - .ff (ff_o), - .rf (rf_o), - .mf (mf_o), - .db (db_o), - .re (re_o), - .ce (ce_o), - .tl (tl_o), - .ftp (ftp), - .ov (ov_o), - .cs (cs_o), - .length (fl_o), - .pbl (pbl), - .dsl (dsl), - .rpoll (rpoll), - .rdbadc (rdbadc), - .rdbad (rdbad), - .rpollack (rpollack), - .bufack (eriack), - .rcompack (rcompack), - .des (rdes), - .fbuf (rbuf), - .stat (rstat), - .ru (ru), - .rcomp (rcomp), - .bufcomp (erireq), - .stopi (stopr), - .stopo (stoprlsm) - ); - - CSR_V #(CSRWIDTH, DATAWIDTH, DATADEPTH, RFIFODEPTH, RCDEPTH) U_CSR( - .clk (clkcsr), - .rst (rstcsro), - .interrupt (interrupt), - .rstsofto (rstsoft), - .csrreq (csrreq), - .csrrw (csrrw), - .csrbe (csrbe), - .csraddr (csraddr), - .csrdatai (csrdatai), - .csrack (csrack), - .csrdatao (csrdatao), - .tprog (tprog), - .tireq (tcomp), - .unf (ur_i), - .tiack (tcompack), - .tcsreq (tcsreq), - .tcsack (tcsack), - .fd (fd), - .ic (ic), - .etireq (etireq), - .etiack (etiack), - .tm (tm), - .sf (sf), - .tset (tset), - .tdes (tdes), - .tbuf (tbuf), - .tstat (tstat), - .tu (tu), - .tpollack (tpollack), - .ft (ft), - .tpoll (tpoll), - .tdbadc (tdbadc), - .tdbad (tdbad), - .rireq (rcomp), - .rcsreq (rcsreq), - .rprog (rprog), - .riack (rcompack), - .rcsack (rcsack), - .ren (ren), - .ra (ra), - .pm (pm), - .pr (pr), - .pb (pb), - .rif (rif), - .ho (ho), - .hp (hp), - .foclack (foclack), - .mfclack (mfclack), - .oco (oco), - .mfo (mfo), - .focg (focg), - .mfcg (mfcg), - .focl (focl), - .mfcl (mfcl), - .erireq (erireq), - .ru (ru), - .rpollack (rpollack), - .rdes (rdes), - .rbuf (rbuf), - .rstat (rstat), - .eriack (eriack), - .rpoll (rpoll), - .rdbadc (rdbadc), - .rdbad (rdbad), - .ble (ble), - .dbo (dbo), - .dma_priority (dma_priority), - .pbl (pbl), - .dsl (dsl), - .stoptc (stoptc), - .stoptlsm (stoptlsm), - .stoptfifo (stoptfifo), - .stopt (stopt), - .tps (tps), - .stoprc (stoprc), - .stoprlsm (stoprlsm), - .stopr (stopr), - .rps (rps), - .sdi (sdi), - .sclk (sclk), - .scs (scs), - .sdo (sdo), - .mdi (mdi), - .mdc (mdc), - .mdo (mdo), - .mden (mden) - ); - - RSTC_V U_RSTC ( - .clkdma(clkdma), - .clkcsr(clkcsr), - .clkt(clkt), - .clkr(clkr), - .rstcsr(rstcsr), - .rstsoft(rstsoft), - .rsttc(rsttc), - .rstrc(rstrc), - .rstdmao(rstdmao), - .rstcsro(rstcsro) - ); - - assign rwe = irwe ; - - assign rwdata = irwdata ; - - assign rsttco = rsttc ; - - assign rstrco = rstrc ; - -endmodule - - - - - -module MAC2AHB_V ( - mhclk, - mhresetn, - mhrdata, - mhready, - mhresp, - mhaddr, - mhtrans, - mhwrite, - mhsize, - mhburst, - mhprot, - mhwdata, - mhgrantmac, - mhbusreqmac, - mhlockmac, - shclk, - shresetn, - shselmac, - shaddr, - shwrite, - shreadyi, - shtrans, - shsize, - shburst, - shwdata, - shreadyo, - shresp, - shrdata, - datareq, - datareqc, - datarw, - dataeob, - dataeobc, - dataaddr, - datao, - dataack, - datai, - rstcsr, - csrack, - csrdatao, - csrreq, - csrrw, - csrbe, - csrdatai, - csraddr - ); - - parameter MAHBDATAWIDTH = 32; - parameter MAHBADDRESSWIDTH = 32; - - parameter SAHBDATAWIDTH = 32; - parameter SAHBADDRESSWIDTH = 32; - - parameter MACDATAWIDTH = 32; - parameter MACADDRESSWIDTH = 32; - - parameter CSRDATAWIDTH = 32; - parameter CSRADDRESSWIDTH = 32; - - `include "mac2ahb_package.v" - - input mhclk; - input mhresetn; - input [MAHBDATAWIDTH - 1:0] mhrdata; - input mhready; - input [1:0] mhresp; - output [MAHBADDRESSWIDTH - 1:0] mhaddr; - wire [MAHBADDRESSWIDTH - 1:0] mhaddr; - output [1:0] mhtrans; - wire [1:0] mhtrans; - output mhwrite; - wire mhwrite; - output [2:0] mhsize; - wire [2:0] mhsize; - output [2:0] mhburst; - wire [2:0] mhburst; - output [3:0] mhprot; - wire [3:0] mhprot; - output [MAHBDATAWIDTH - 1:0] mhwdata; - wire [MAHBDATAWIDTH - 1:0] mhwdata; - - input mhgrantmac; - output mhbusreqmac; - wire mhbusreqmac; - output mhlockmac; - wire mhlockmac; - - input shclk; - input shresetn; - input shselmac; - input [SAHBADDRESSWIDTH - 1:0] shaddr; - input shwrite; - input shreadyi; - input [1:0] shtrans; - input [2:0] shsize; - input [2:0] shburst; - input [SAHBDATAWIDTH - 1:0] shwdata; - output shreadyo; - wire shreadyo; - output [1:0] shresp; - wire [1:0] shresp; - output [SAHBDATAWIDTH - 1:0] shrdata; - wire [SAHBDATAWIDTH - 1:0] shrdata; - - - input datareq; - input datareqc; - input datarw; - input dataeob; - input dataeobc; - input [MACADDRESSWIDTH - 1:0] dataaddr; - input [MACDATAWIDTH - 1:0] datao; - output dataack; - wire dataack; - output [MACDATAWIDTH - 1:0] datai; - wire [MACDATAWIDTH - 1:0] datai; - - - output rstcsr; - wire rstcsr; - input csrack; - input [CSRDATAWIDTH - 1:0] csrdatao; - output csrreq; - wire csrreq; - output csrrw; - wire csrrw; - output [CSRDATAWIDTH / 8 - 1:0] csrbe; - wire [CSRDATAWIDTH / 8 - 1:0] csrbe; - output [CSRDATAWIDTH - 1:0] csrdatai; - wire [CSRDATAWIDTH - 1:0] csrdatai; - output [CSRADDRESSWIDTH - 1:0] csraddr; - wire [CSRADDRESSWIDTH - 1:0] csraddr; - - - MACDATA2AHB_V - #(MAHBDATAWIDTH, MAHBADDRESSWIDTH, MACDATAWIDTH, MACADDRESSWIDTH) - U_MACDATA2AHB ( - .mhclk (mhclk), - .mhresetn (mhresetn), - .mhrdata (mhrdata), - .mhready (mhready), - .mhresp (mhresp), - .mhaddr (mhaddr), - .mhtrans (mhtrans), - .mhwrite (mhwrite), - .mhsize (mhsize), - .mhburst (mhburst), - .mhprot (mhprot), - .mhwdata (mhwdata), - .mhgrantmac (mhgrantmac), - .mhbusreqmac (mhbusreqmac), - .mhlockmac (mhlockmac), - .datareq (datareq), - .datareqc (datareqc), - .datarw (datarw), - .dataeob (dataeob), - .dataeobc (dataeobc), - .dataaddr (dataaddr), - .datao (datao), - .dataack (dataack), - .datai (datai) - ); - - MACCSR2AHB_V - #(SAHBDATAWIDTH, SAHBADDRESSWIDTH, CSRDATAWIDTH, CSRADDRESSWIDTH) - U_MACCSR2AHB( - .shclk (shclk), - .shresetn (shresetn), - .shselmac (shselmac), - .shaddr (shaddr), - .shwrite (shwrite), - .shreadyi (shreadyi), - .shtrans (shtrans), - .shsize (shsize), - .shburst (shburst), - .shwdata (shwdata), - .shreadyo (shreadyo), - .shresp (shresp), - .shrdata (shrdata), - .rstcsr (rstcsr), - .csrack (csrack), - .csrdatao (csrdatao), - .csrreq (csrreq), - .csrrw (csrrw), - .csrbe (csrbe), - .csrdatai (csrdatai), - .csraddr (csraddr) - ); - -endmodule - - - - -module MAC_AHB_V ( - clkt, - clkr, - rsttco, - rstrco, - interrupt, - tps, - rps, - mhclk, - mhresetn, - mhrdata, - mhready, - mhresp, - mhaddr, - mhtrans, - mhwrite, - mhsize, - mhburst, - mhprot, - mhwdata, - mhgrantmac, - mhbusreqmac, - mhlockmac, - shclk, - shresetn, - shselmac, - shaddr, - shwrite, - shreadyi, - shtrans, - shsize, - shburst, - shwdata, - shreadyo, - shresp, - shrdata, - trdata, - twe, - twaddr, - traddr, - twdata, - rrdata, - rwe, - rwaddr, - rraddr, - rwdata, - frdata, - fwe, - fwaddr, - fraddr, - fwdata, - match, - matchval, - matchen, - matchdata, - sdi, - sclk, - scs, - sdo, - rxer, - rxdv, - col, - crs, - rxd, - txen, - txer, - txd, - mdc, - mdi, - mdo, - mden - ); - - parameter MAHBDATAWIDTH = 32; - parameter MAHBADDRESSWIDTH = 32; - parameter TFIFODEPTH = 9; - parameter RFIFODEPTH = 9; - parameter TCDEPTH = 1; - parameter RCDEPTH = 2; - - `include "utility.v" - - parameter SAHBDATAWIDTH = 32; - parameter SAHBADDRESSWIDTH = CSRDEPTH; - - input clkt; - input clkr; - output rsttco; - wire rsttco; - output rstrco; - wire rstrco; - - - output interrupt; - wire interrupt; - - output tps; - wire tps; - output rps; - wire rps; - - input mhclk; - input mhresetn; - input [MAHBDATAWIDTH - 1:0] mhrdata; - input mhready; - input [1:0] mhresp; - output [MAHBADDRESSWIDTH - 1:0] mhaddr; - wire [MAHBADDRESSWIDTH - 1:0] mhaddr; - output [1:0] mhtrans; - wire [1:0] mhtrans; - output mhwrite; - wire mhwrite; - output [2:0] mhsize; - wire [2:0] mhsize; - output [2:0] mhburst; - wire [2:0] mhburst; - output [3:0] mhprot; - wire [3:0] mhprot; - output [MAHBDATAWIDTH - 1:0] mhwdata; - wire [MAHBDATAWIDTH - 1:0] mhwdata; - input mhgrantmac; - output mhbusreqmac; - wire mhbusreqmac; - output mhlockmac; - wire mhlockmac; - - input shclk; - input shresetn; - input shselmac; - input [SAHBADDRESSWIDTH - 1:0] shaddr; - input shwrite; - input [1:0] shtrans; - input [2:0] shsize; - input shreadyi; - input [2:0] shburst; - input [SAHBDATAWIDTH - 1:0] shwdata; - output shreadyo; - wire shreadyo; - output [1:0] shresp; - wire [1:0] shresp; - output [SAHBDATAWIDTH - 1:0] shrdata; - wire [SAHBDATAWIDTH - 1:0] shrdata; - - input [MAHBDATAWIDTH - 1:0] trdata; - output twe; - wire twe; - output [TFIFODEPTH - 1:0] twaddr; - wire [TFIFODEPTH - 1:0] twaddr; - output [TFIFODEPTH - 1:0] traddr; - wire [TFIFODEPTH - 1:0] traddr; - output [MAHBDATAWIDTH - 1:0] twdata; - wire [MAHBDATAWIDTH - 1:0] twdata; - - - input [MAHBDATAWIDTH - 1:0] rrdata; - output rwe; - wire rwe; - output [RFIFODEPTH - 1:0] rwaddr; - wire [RFIFODEPTH - 1:0] rwaddr; - output [RFIFODEPTH - 1:0] rraddr; - wire [RFIFODEPTH - 1:0] rraddr; - output [MAHBDATAWIDTH - 1:0] rwdata; - wire [MAHBDATAWIDTH - 1:0] rwdata; - - input [15:0] frdata; - output fwe; - wire fwe; - output [ADDRDEPTH - 1:0] fwaddr; - wire [ADDRDEPTH - 1:0] fwaddr; - output [ADDRDEPTH - 1:0] fraddr; - wire [ADDRDEPTH - 1:0] fraddr; - output [15:0] fwdata; - wire [15:0] fwdata; - - input match; - input matchval; - output matchen; - wire matchen; - output [47:0] matchdata; - wire [47:0] matchdata; - - input sdi; - output sclk; - wire sclk; - output scs; - wire scs; - output sdo; - wire sdo; - - input rxer; - input rxdv; - input col; - input crs; - input [MIIWIDTH - 1:0] rxd; - output txen; - wire txen; - output txer; - wire txer; - output [MIIWIDTH - 1:0] txd; - wire [MIIWIDTH - 1:0] txd; - output mdc; - wire mdc; - input mdi; - output mdo; - wire mdo; - output mden; - wire mden; - - - wire datareq; - wire datareqc; - wire datarw; - wire dataeob; - wire dataeobc; - wire [(MAHBADDRESSWIDTH - 1):0] dataaddr; - wire [(MAHBDATAWIDTH - 1):0] datao; - wire dataack; - wire [(MAHBDATAWIDTH - 1):0] datai; - - wire rstcsr; - wire csrack; - wire [SAHBDATAWIDTH - 1:0] csrdatao; - wire csrreq; - wire csrrw; - wire [SAHBDATAWIDTH / 8 - 1:0] csrbe; - wire [SAHBDATAWIDTH - 1:0] csrdatai; - wire [SAHBADDRESSWIDTH - 1:0] csraddr; - - MAC_V - #(SAHBDATAWIDTH, - MAHBDATAWIDTH, - MAHBADDRESSWIDTH, - TFIFODEPTH, - RFIFODEPTH, - TCDEPTH, - RCDEPTH) - U_MAC ( - .clkdma (mhclk), - .clkcsr (shclk), - .clkt (clkt), - .clkr (clkr), - .rstcsr (rstcsr), - .rsttco (rsttco), - .rstrco (rstrco), - .interrupt (interrupt), - .rps (rps), - .tps (tps), - .csrreq (csrreq), - .csrrw (csrrw), - .csrbe (csrbe), - .csrdatai (csrdatai), - .csrack (csrack), - .csraddr (csraddr), - .csrdatao (csrdatao), - .dataack (dataack), - .datareq (datareq), - .datareqc (datareqc), - .datarw (datarw), - .dataeob (dataeob), - .dataeobc (dataeobc), - .datai (datai), - .dataaddr (dataaddr), - .datao (datao), - .trdata (trdata), - .twe (twe), - .twaddr (twaddr), - .traddr (traddr), - .twdata (twdata), - .rrdata (rrdata), - .rwe (rwe), - .rwaddr (rwaddr), - .rraddr (rraddr), - .rwdata (rwdata), - .frdata (frdata), - .fwe (fwe), - .fraddr (fraddr), - .fwaddr (fwaddr), - .fwdata (fwdata), - .match (match), - .matchval (matchval), - .matchen (matchen), - .matchdata (matchdata), - .sdi (sdi), - .sclk (sclk), - .scs (scs), - .sdo (sdo), - .rxer (rxer), - .rxdv (rxdv), - .col (col), - .crs (crs), - .rxd (rxd), - .txen (txen), - .txer (txer), - .txd (txd), - .mdi (mdi), - .mdo (mdo), - .mden (mden), - .mdc (mdc) - ); - - MAC2AHB_V - #(MAHBDATAWIDTH, - MAHBADDRESSWIDTH, - SAHBDATAWIDTH, - SAHBADDRESSWIDTH, - MAHBDATAWIDTH, - MAHBADDRESSWIDTH, - SAHBDATAWIDTH, - SAHBADDRESSWIDTH) - U_MAC2AHB ( - .mhclk (mhclk), - .mhresetn (mhresetn), - .mhrdata (mhrdata), - .mhready (mhready), - .mhresp (mhresp), - .mhaddr (mhaddr), - .mhtrans (mhtrans), - .mhwrite (mhwrite), - .mhsize (mhsize), - .mhburst (mhburst), - .mhprot (mhprot), - .mhwdata (mhwdata), - .mhgrantmac (mhgrantmac), - .mhbusreqmac (mhbusreqmac), - .mhlockmac (mhlockmac), - .shclk (shclk), - .shresetn (shresetn), - .shselmac (shselmac), - .shaddr (shaddr), - .shwrite (shwrite), - .shreadyi (shreadyi), - .shtrans (shtrans), - .shsize (shsize), - .shburst (shburst), - .shwdata (shwdata), - .shreadyo (shreadyo), - .shresp (shresp), - .shrdata (shrdata), - .datareq (datareq), - .datareqc (datareqc), - .datarw (datarw), - .dataeob (dataeob), - .dataeobc (dataeobc), - .dataaddr (dataaddr), - .datao (datao), - .dataack (dataack), - .datai (datai), - .rstcsr (rstcsr), - .csrack (csrack), - .csrdatao (csrdatao), - .csrreq (csrreq), - .csrrw (csrrw), - .csrbe (csrbe), - .csrdatai (csrdatai), - .csraddr (csraddr) - ); - - -endmodule - - - - -module MACCSR2AHB_V ( - shclk, - shresetn, - shselmac, - shaddr, - shwrite, - shreadyi, - shtrans, - shsize, - shburst, - shwdata, - shreadyo, - shresp, - shrdata, - rstcsr, - csrack, - csrdatao, - csrreq, - csrrw, - csrbe, - csrdatai, - csraddr - ); - - parameter SAHBDATAWIDTH = 32; - parameter SAHBADDRESSWIDTH = 8; - parameter CSRDATAWIDTH = 32; - parameter CSRADDRESSWIDTH = 8; - - `include "mac2ahb_package.v" - - - input shclk; - input shresetn; - input shselmac; - input [SAHBADDRESSWIDTH - 1:0] shaddr; - input shwrite; - input shreadyi; - input [1:0] shtrans; - input [2:0] shsize; - input [2:0] shburst; - input [SAHBDATAWIDTH - 1:0] shwdata; - output shreadyo; - wire shreadyo; - output [1:0] shresp; - wire [1:0] shresp; - output [SAHBDATAWIDTH - 1:0] shrdata; - wire [SAHBDATAWIDTH - 1:0] shrdata; - - - output rstcsr; - wire rstcsr; - input csrack; - input [CSRDATAWIDTH - 1:0] csrdatao; - output csrreq; - wire csrreq; - output csrrw; - wire csrrw; - output [CSRDATAWIDTH / 8 - 1:0] csrbe; - wire [CSRDATAWIDTH / 8 - 1:0] csrbe; - output [CSRDATAWIDTH - 1:0] csrdatai; - wire [CSRDATAWIDTH - 1:0] csrdatai; - output [CSRADDRESSWIDTH - 1:0] csraddr; - wire [CSRADDRESSWIDTH - 1:0] csraddr; - - - reg [CSRADDRESSWIDTH - 1:0] i_addrreg_r; - - reg i_transfind_r; - - reg i_transfdir_r; - - reg [CSRDATAWIDTH / 8 - 1:0] i_calcbe; - - reg [CSRDATAWIDTH / 8 - 1:0] i_calcbe_r; - - always @(posedge shclk) - begin : i_transfind_proc - if (!shresetn) - begin - i_transfind_r <= 1'b0 ; - end - else - begin - i_transfind_r <= 1'b0 ; - if (shtrans == HTRANS_NONSEQ & shreadyi & - shburst == HBURST_SINGLE & shselmac) - begin - i_transfind_r <= 1'b1 ; - end - end - end - - always @(posedge shclk) - begin : i_transfdir_proc - if (!shresetn) - begin - i_transfdir_r <= 1'b1 ; - end - else - begin - if (shtrans == HTRANS_NONSEQ & shselmac & shreadyi) - begin - if (shwrite) - begin - i_transfdir_r <= 1'b0 ; - end - else - begin - i_transfdir_r <= 1'b1 ; - end - end - end - end - - always @(posedge shclk) - begin : i_addrreg_proc - if (!shresetn) - begin - i_addrreg_r <= {CSRADDRESSWIDTH{1'b0}} ; - end - else - begin - i_addrreg_r <= i_addrreg_r ; - if (shtrans == HTRANS_NONSEQ & shselmac & shreadyi) - begin - i_addrreg_r <= shaddr[CSRADDRESSWIDTH - 1:0] ; - end - end - end - - always @(posedge shclk) - begin : i_calcbe_reg_proc - if (!shresetn) - begin - i_calcbe_r <= {CSRDATAWIDTH / 8{1'b0}} ; - end - else - begin - i_calcbe_r <= i_calcbe ; - end - end - - always @(shaddr or shsize) - begin : i_calcbe_proc - case (SAHBDATAWIDTH) - 8 : - begin - i_calcbe = 1'b1 ; - end - 16 : - begin - i_calcbe = {CSRDATAWIDTH / 8{1'b1}} ; - case (shsize) - HSIZE_8BIT : - begin - if (shaddr[0]) - begin - i_calcbe = 2'b10 ; - end - else - begin - i_calcbe = 2'b01 ; - end - end - HSIZE_16BIT : - begin - if (!(shaddr[0])) - begin - i_calcbe = 2'b11 ; - end - else - begin - i_calcbe = 2'b00 ; - end - end - default : - begin - end - endcase - end - 32 : - begin - i_calcbe = {CSRDATAWIDTH / 8{1'b1}} ; - case (shsize) - HSIZE_8BIT : - begin - if (shaddr[1:0] == 2'b00) - begin - i_calcbe = 4'b0001 ; - end - else if (shaddr[1:0] == 2'b01) - begin - i_calcbe = 4'b0010 ; - end - else if (shaddr[1:0] == 2'b10) - begin - i_calcbe = 4'b0100 ; - end - else - begin - i_calcbe = 4'b1000 ; - end - end - HSIZE_16BIT : - begin - if (shaddr[1:0] == 2'b00) - begin - i_calcbe = 4'b0011 ; - end - else if (shaddr[1:0] == 2'b10) - begin - i_calcbe = 4'b1100 ; - end - else - begin - i_calcbe = 4'b0000 ; - end - end - HSIZE_32BIT : - begin - if (shaddr[1:0] == 2'b00) - begin - i_calcbe = 4'b1111 ; - end - else - begin - i_calcbe = 4'b0000 ; - end - end - default : - begin - end - endcase - end - default : - begin - end - endcase - end - - assign shresp = HRESP_OKAY ; - - assign csrdatai = shwdata ; - - assign csrbe = i_calcbe_r ; - - assign csraddr = i_addrreg_r ; - - assign csrreq = i_transfind_r ; - - assign csrrw = i_transfdir_r ; - - assign rstcsr = ~shresetn ; - - assign shreadyo = csrack ; - - assign shrdata = csrdatao ; - -endmodule - - -module MACDATA2AHB_V ( - mhclk, - mhresetn, - mhrdata, - mhready, - mhresp, - mhaddr, - mhtrans, - mhwrite, - mhsize, - mhburst, - mhprot, - mhwdata, - mhgrantmac, - mhbusreqmac, - mhlockmac, - datareq, - datareqc, - datarw, - dataeob, - dataeobc, - dataaddr, - datao, - dataack, - datai - ); - - parameter MAHBDATAWIDTH = 32; - parameter MAHBADDRESSWIDTH = 32; - parameter MACDATAWIDTH = 32; - parameter MACADDRESSWIDTH = 32; - - `include "mac2ahb_package.v" - - - input mhclk; - input mhresetn; - input [MAHBDATAWIDTH - 1:0] mhrdata; - input mhready; - input [1:0] mhresp; - output [MAHBADDRESSWIDTH - 1:0] mhaddr; - wire [MAHBADDRESSWIDTH - 1:0] mhaddr; - output [1:0] mhtrans; - reg [1:0] mhtrans; - output mhwrite; - wire mhwrite; - output [2:0] mhsize; - reg [2:0] mhsize; - output [2:0] mhburst; - reg [2:0] mhburst; - output [3:0] mhprot; - wire [3:0] mhprot; - output [MAHBDATAWIDTH - 1:0] mhwdata; - wire [MAHBDATAWIDTH - 1:0] mhwdata; - - input mhgrantmac; - output mhbusreqmac; - wire mhbusreqmac; - output mhlockmac; - wire mhlockmac; - - input datareq; - input datareqc; - input datarw; - input dataeob; - input dataeobc; - input [MACADDRESSWIDTH - 1:0] dataaddr; - input [MACDATAWIDTH - 1:0] datao; - output dataack; - wire dataack; - output [MACDATAWIDTH - 1:0] datai; - wire [MACDATAWIDTH - 1:0] datai; - - - - wire [MAHBDATAWIDTH - 1:0] ahb_hrdata; - wire ahb_hready; - reg[1:0] ahb_hresp; - wire [MAHBADDRESSWIDTH - 1:0] ahb_haddr; - wire [1:0] ahb_htrans; - wire ahb_hwrite; - wire [2:0] ahb_hsize; - wire [0:0] ahb_hburst; - wire [3:0] ahb_hprot; - wire [MAHBDATAWIDTH - 1:0] ahb_hwdata; - wire ahb_hgrantmac; - reg ahb_hbusreqmac; - wire ahb_hlockmac; - wire mac_datareqc; - wire mac_datareq; - wire mac_datarw; - wire mac_dataeobc; - wire mac_dataeobcc; - wire [MACADDRESSWIDTH - 1:0] mac_dataaddr; - wire [MACDATAWIDTH - 1:0] mac_datao; - wire mac_dataack; - wire [MACDATAWIDTH - 1:0] mac_datai; - reg [1:0] fsm_macdata2ahb_nxt; - reg [1:0] fsm_macdata2ahb_r; - reg [MACADDRESSWIDTH - 1:0] i_ahb_haddr; - reg [MACADDRESSWIDTH - 1:0] i_ahb_haddr_c; - reg i_ahb_hgrant_r; - wire i_hbusreq_c; - reg i_mac_dataeobc_r; - reg i_datareqc_r; - wire i_hwritem_c; - reg i_hwritem; - wire [1:0] i_htransm_c; - reg [1:0] i_htransm; - wire i_dataack_c; - wire i_1kc; - - assign ahb_hwdata = mac_datao ; - - assign mac_datai = ahb_hrdata ; - - always @(i_ahb_haddr or - fsm_macdata2ahb_r or - ahb_hready or - mac_dataaddr or - i_ahb_hgrant_r or - i_mac_dataeobc_r or - i_datareqc_r or - dataaddr) - begin : i_ahb_haddr_proc - case (fsm_macdata2ahb_r) - AHBM_ADDR : - begin - if (ahb_hready == 1'b1 & i_mac_dataeobc_r == 1'b0) - begin - i_ahb_haddr_c = i_ahb_haddr + 3'b100 ; - end - else - begin - i_ahb_haddr_c = i_ahb_haddr ; - end - end - AHBM_ADDRDATA : - begin - if (ahb_hready == 1'b1 & i_mac_dataeobc_r == 1'b0) - begin - i_ahb_haddr_c = i_ahb_haddr + 3'b100 ; - end - else - begin - i_ahb_haddr_c = i_ahb_haddr ; - end - end - AHBM_IDLE : - begin - if (i_datareqc_r == 1'b1) - begin - i_ahb_haddr_c = dataaddr ; - end - else - begin - i_ahb_haddr_c = i_ahb_haddr ; - end - end - default : - begin - i_ahb_haddr_c = i_ahb_haddr ; - end - endcase - end - - always @(posedge mhclk) - begin : iahbaddrm_reg_proc - if (mhresetn == 1'b0) - begin - i_ahb_haddr <= {MACADDRESSWIDTH - 1+1{1'b1}} ; - end - else - begin - i_ahb_haddr <= i_ahb_haddr_c ; - end - end - - assign ahb_haddr = i_ahb_haddr ; - - assign i_1kc = (ahb_htrans == SEQ | ahb_htrans == NONSEQ) ? - (i_ahb_haddr[10] ^ i_ahb_haddr_c[10]) : 1'b0 ; - - assign i_hbusreq_c = (mac_datareqc == 1'b1 & - ( - mac_dataeobc == 1'b0 | - fsm_macdata2ahb_nxt == AHBM_IDLE - ) - ) ? 1'b1 : 1'b0 ; - - assign ahb_hwrite = i_hwritem ; - - assign ahb_htrans = (!ahb_hgrantmac & fsm_macdata2ahb_r == AHBM_ADDR) ? - IDLE : i_htransm ; - - assign ahb_hlockmac = 1'b0 ; - - - assign i_hwritem_c = (fsm_macdata2ahb_nxt == AHBM_ADDR) ? - ~mac_datarw : i_hwritem ; - - - assign ahb_hburst = INCR ; - - assign i_htransm_c = (fsm_macdata2ahb_nxt == AHBM_ADDR) ? NONSEQ : - (fsm_macdata2ahb_nxt == AHBM_ADDRDATA) ? SEQ : - IDLE ; - - assign i_dataack_c = (ahb_hready == 1'b1 & - ( - ahb_hresp == OKAY | ahb_hresp == ERROR - ) & - ( - fsm_macdata2ahb_r == AHBM_DATA | - fsm_macdata2ahb_r == AHBM_ADDRDATA - ) - ) ? 1'b1 : 1'b0 ; - - assign mac_dataack = i_dataack_c ; - - always @(fsm_macdata2ahb_r or - ahb_hgrantmac or - ahb_hresp or - ahb_hready or - i_datareqc_r or - i_mac_dataeobc_r or - mac_dataeobc or - mac_datareqc or - mac_datareq or - i_1kc) - begin : fsm_macdata2ahb_r_proc - case (fsm_macdata2ahb_r) - AHBM_IDLE : - begin - if (ahb_hgrantmac == 1'b1 & - ahb_hready == 1'b1 & - mac_datareq == 1'b1) - begin - fsm_macdata2ahb_nxt = AHBM_ADDR ; - end - else - begin - fsm_macdata2ahb_nxt = AHBM_IDLE ; - end - end - AHBM_ADDR : - begin - if(!ahb_hgrantmac) - begin - fsm_macdata2ahb_nxt = AHBM_IDLE; - end - else if (ahb_hready == 1'b1) - begin - if (i_mac_dataeobc_r == 1'b1 | - ahb_hgrantmac == 1'b0 | - i_1kc == 1'b1) - begin - fsm_macdata2ahb_nxt = AHBM_DATA ; - end - else - begin - fsm_macdata2ahb_nxt = AHBM_ADDRDATA ; - end - end - else - begin - fsm_macdata2ahb_nxt = AHBM_ADDR ; - end - end - AHBM_DATA : - begin - if (ahb_hready == 1'b1) - begin - if (ahb_hgrantmac == 1'b1 & - mac_datareqc == 1'b1 & - i_1kc == 1'b0) - begin - fsm_macdata2ahb_nxt = AHBM_ADDR ; - end - else - begin - fsm_macdata2ahb_nxt = AHBM_IDLE ; - end - end - else - begin - if (ahb_hresp == OKAY | ahb_hresp == ERROR) - begin - fsm_macdata2ahb_nxt = AHBM_DATA ; - end - else - begin - fsm_macdata2ahb_nxt = AHBM_IDLE ; - end - end - end - default: - begin - if (ahb_hready == 1'b1) - begin - if (ahb_hgrantmac == 1'b0 | - mac_dataeobc == 1'b1 | - i_1kc == 1'b1) - begin - fsm_macdata2ahb_nxt = AHBM_DATA ; - end - else - begin - fsm_macdata2ahb_nxt = AHBM_ADDRDATA ; - end - end - else - begin - if (ahb_hresp == OKAY | ahb_hresp == ERROR) - begin - fsm_macdata2ahb_nxt = AHBM_ADDRDATA ; - end - else - begin - fsm_macdata2ahb_nxt = AHBM_IDLE ; - end - end - end - endcase - end - - always @(posedge mhclk) - begin : fsm_macdata2ahb_r_reg_proc - if (mhresetn == 1'b0) - begin - fsm_macdata2ahb_r <= AHBM_IDLE ; - end - else - begin - fsm_macdata2ahb_r <= fsm_macdata2ahb_nxt ; - end - end - - always @(posedge mhclk) - begin : datactrl_reg_proc - if (mhresetn == 1'b0) - begin - i_datareqc_r <= 1'b0 ; - i_mac_dataeobc_r <= 1'b0 ; - i_ahb_hgrant_r <= 1'b0 ; - end - else - begin - i_datareqc_r <= mac_datareqc ; - i_mac_dataeobc_r <= mac_dataeobc ; - i_ahb_hgrant_r <= ahb_hgrantmac ; - end - end - - always @(posedge mhclk) - begin : ahbm_ctrl_reg_proc - if (mhresetn == 1'b0) - begin - ahb_hbusreqmac <= 1'b0 ; - i_hwritem <= 1'b0 ; - i_htransm <= IDLE ; - end - else - begin - ahb_hbusreqmac <= i_hbusreq_c ; - i_hwritem <= i_hwritem_c ; - i_htransm <= i_htransm_c ; - end - end - assign ahb_hsize = (MAHBDATAWIDTH == 8) ? HSIZE8BIT : - (MAHBDATAWIDTH == 16) ? HSIZE16BIT : - (MAHBDATAWIDTH == 32) ? HSIZE32BIT : - (MAHBDATAWIDTH == 64) ? HSIZE64BIT : - UNSUPPORTED ; - - assign ahb_hprot = HPROT_MACPROTECTIONCONTROL ; - - assign ahb_hrdata = mhrdata ; - - assign ahb_hready = mhready ; - - always @(mhresp) - begin : ahb_hresp_map_proc - case (mhresp) - HRESP_ERROR : - begin - ahb_hresp = ERROR ; - end - HRESP_RETRY : - begin - ahb_hresp = RETRY ; - end - HRESP_SPLIT : - begin - ahb_hresp = SPLIT ; - end - default : - begin - ahb_hresp = OKAY ; - end - endcase - end - - assign mhaddr = ahb_haddr ; - - always @(ahb_htrans) - begin : ahb_htrans_map_proc - case (ahb_htrans) - NONSEQ : - begin - mhtrans = HTRANS_NONSEQ ; - end - SEQ : - begin - mhtrans = HTRANS_SEQ ; - end - default : - begin - mhtrans = HTRANS_IDLE ; - end - endcase - end - - assign mhwrite = ahb_hwrite ; - - always @(ahb_hsize) - begin : ahb_hsize_map_proc - case (ahb_hsize) - HSIZE8BIT : - begin - mhsize = HSIZE_8BIT ; - end - HSIZE16BIT : - begin - mhsize = HSIZE_16BIT ; - end - default : - begin - mhsize = HSIZE_32BIT ; - end - endcase - end - - always @(ahb_hburst) - begin : ahb_hburst_map_proc - case (ahb_hburst) - INCR : - begin - mhburst = HBURST_INCR ; - end - default : - begin - mhburst = HBURST_SINGLE ; - end - endcase - end - - assign mhprot = ahb_hprot ; - - assign mhwdata = ahb_hwdata ; - - assign ahb_hgrantmac = mhgrantmac ; - - assign mhbusreqmac = ahb_hbusreqmac ; - - assign mhlockmac = ahb_hlockmac ; - - - assign mac_datareqc = datareqc ; - - assign mac_datareq = datareq ; - - assign mac_datarw = datarw ; - - assign mac_dataeobc = dataeobc ; - - assign mac_dataaddr = dataaddr ; - - assign mac_datao = datao ; - - assign dataack = mac_dataack ; - - assign datai = mac_datai ; - -endmodule - - -module RC_V ( - clk, - rst, - rxdv, - rxer, - rxd, - col, - ramwe, - ramaddr, - ramdata, - fdata, - faddr, - cachenf, - radg, - wadg, - rprog, - rcpoll, - riack, - ren, - ra, - pm, - pr, - pb, - rif, - ho, - hp, - rireq, - ff, - rf, - mf, - db, - re, - ce, - tl, - ftp, - ov, - cs, - length, - match, - matchval, - matchen, - matchdata, - focl, - foclack, - oco, - focg, - mfcl, - mfclack, - mfo, - mfcg, - stopi, - stopo, - rcsack, - rcsreq); - - parameter FIFODEPTH = 9; - parameter DATAWIDTH = 32; - - `include "utility.v" - - input clk; - input rst; - - input col; - input rxdv; - input rxer; - input [MIIWIDTH - 1:0] rxd; - - output ramwe; - wire ramwe; - output [FIFODEPTH - 1:0] ramaddr; - wire [FIFODEPTH - 1:0] ramaddr; - output [DATAWIDTH - 1:0] ramdata; - wire [DATAWIDTH - 1:0] ramdata; - - input [ADDRWIDTH - 1:0] fdata; - output [ADDRDEPTH - 1:0] faddr; - wire [ADDRDEPTH - 1:0] faddr; - - input cachenf; - input [FIFODEPTH - 1:0] radg; - output [FIFODEPTH - 1:0] wadg; - wire [FIFODEPTH - 1:0] wadg; - output rprog; - reg rprog; - output rcpoll; - wire rcpoll; - - input riack; - input ren; - input ra; - input pm; - input pr; - input pb; - input rif; - input ho; - input hp; - output rireq; - reg rireq; - output ff; - reg ff; - output rf; - reg rf; - output mf; - reg mf; - output db; - reg db; - output re; - reg re; - output ce; - reg ce; - output tl; - reg tl; - output ftp; - reg ftp; - output cs; - reg cs; - output ov; - reg ov; - output [13:0] length; - reg [13:0] length; - - input match; - input matchval; - output matchen; - reg matchen; - output [47:0] matchdata; - wire [47:0] matchdata; - - input focl; - output foclack; - wire foclack; - output oco; - reg oco; - output [10:0] focg; - reg [10:0] focg; - input mfcl; - output mfclack; - output mfo; - reg mfo; - output [15:0] mfcg; - reg [15:0] mfcg; - - input stopi; - output stopo; - reg stopo; - - input rcsack; - output rcsreq; - reg rcsreq; - - - - reg we; - reg full; - reg [FIFODEPTH - 1:0] wad; - reg [FIFODEPTH - 1:0] wadi; - reg [FIFODEPTH - 1:0] iwadg; - reg [FIFODEPTH - 1:0] wadig; - reg [FIFODEPTH - 1:0] radg_0_r; - reg [FIFODEPTH - 1:0] radg_r; - reg [FIFODEPTH - 1:0] isofad; - reg cachenf_r; - reg cachenf_2r; - reg fcfbci; - reg fcfbci_r; - reg eorfff; - - - reg col_r; - reg rxdv_r; - reg rxer_r; - reg [MIIWIDTH - 1:0] rxd_r; - wire [3:0] rxd_r4; - - reg [3:0] rsm_c; - reg [3:0] rsm; - reg [3:0] ncnt; - wire [1:0] ncnt10; - wire [2:0] ncnt20; - reg [DATAWIDTH - 1:0] data_c; - reg [DATAWIDTH - 1:0] data; - reg [31:0] crc_c; - reg [31:0] crc; - reg [6:0] bcnt; - wire [2:0] bcnt20; - reg bz; - reg winp; - wire iri_c; - reg iri; - reg riack_r; - reg [13:0] lcnt; - reg [15:0] lfield; - reg ren_r; - reg irprog; - - reg [2:0] fsm_c; - reg [2:0] fsm; - reg perfm_c; - reg perfm; - reg invm; - reg [8:0] crchash; - reg hash; - reg [47:0] dest; - reg [2:0] flcnt; - reg [ADDRDEPTH - 1:0] fa; - reg [15:0] fdata_r; - - reg rcs; - reg rcsack_r; - reg [7:0] rcscnt; - - reg [10:0] focnt; - reg focl_r; - reg [15:0] mfcnt; - reg mfcl_r; - - reg stop_r; - - wire [FIFODEPTH - 1:0] fzero; - wire [MIIWIDTH_MAX + 1:0] mzero_max; - wire [MIIWIDTH_MAX + 1:0] rxd_r_max; - - always @(posedge clk) - begin : mii_reg_proc - if (rst) - begin - col_r <= 1'b0; - rxdv_r <= 1'b0 ; - rxer_r <= 1'b0 ; - rxd_r <= {MIIWIDTH{1'b0}} ; - data <= {DATAWIDTH{1'b1}} ; - end - else - begin - col_r <= col ; - rxdv_r <= rxdv ; - rxer_r <= rxer ; - rxd_r <= rxd ; - data <= data_c ; - end - end - - assign rxd_r4 = rxd_r_max[MIIWIDTH-1:0]; - - assign ncnt10 = ncnt[1:0] ; - - assign ncnt20 = ncnt[2:0] ; - - always @(ncnt or ncnt10 or ncnt20 or rxd_r_max or data) - begin : data_proc - reg[15:0] data16; - reg[31:0] data32; - case (DATAWIDTH) - 8 : - begin - data_c <= data ; - if (!(ncnt[0])) - begin - data_c[3:0] <= rxd_r_max[MIIWIDTH-1:0] ; - end - else - begin - data_c[7:4] <= rxd_r_max[MIIWIDTH-1:0] ; - end - end - 16 : - begin - data16 = data; - case (ncnt10) - 2'b00 : - begin - data16[3:0] = rxd_r_max[MIIWIDTH-1:0]; - end - 2'b01 : - begin - data16[7:4] = rxd_r_max[MIIWIDTH-1:0]; - end - 2'b10 : - begin - data16[11:8] = rxd_r_max[MIIWIDTH-1:0]; - end - default : - begin - data16[15:12] = rxd_r_max[MIIWIDTH-1:0]; - end - endcase - data_c <= data16 ; - end - default : - begin - data32 = data; - case (ncnt20) - 3'b000 : - begin - data32[3:0] = rxd_r_max[MIIWIDTH-1:0]; - end - 3'b001 : - begin - data32[7:4] = rxd_r_max[MIIWIDTH-1:0]; - end - 3'b010 : - begin - data32[11:8] = rxd_r_max[MIIWIDTH-1:0]; - end - 3'b011 : - begin - data32[15:12] = rxd_r_max[MIIWIDTH-1:0]; - end - 3'b100 : - begin - data32[19:16] = rxd_r_max[MIIWIDTH-1:0]; - end - 3'b101 : - begin - data32[23:20] = rxd_r_max[MIIWIDTH-1:0]; - end - 3'b110 : - begin - data32[27:24] = rxd_r_max[MIIWIDTH-1:0]; - end - default : - begin - data32[31:28] = rxd_r_max[MIIWIDTH-1:0]; - end - endcase - data_c <= data32 ; - end - endcase - end - - always @(posedge clk) - begin : fifofull_reg_proc - if (rst) - begin - cachenf_r <= 1'b1 ; - cachenf_2r <= 1'b1 ; - full <= 1'b0 ; - end - else - begin - cachenf_r <= cachenf ; - - if(cachenf_2r | - ( - (!rxdv_r & cachenf_r) | - ( rxdv_r & cachenf_r & - (rsm==RSM_IDLE_RCSMT | rsm==RSM_SFD) - ) - ) - ) - begin - cachenf_2r <= cachenf ; - end - - if ((wadig == radg_r) | (iwadg == radg_r & full)) - begin - full <= 1'b1 ; - end - else - begin - full <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : addr_reg_proc - if (rst) - begin - wad <= {FIFODEPTH{1'b0}} ; - wadi <= {fzero[FIFODEPTH - 1:1], 1'b1} ; - iwadg <= {FIFODEPTH{1'b0}} ; - isofad <= {FIFODEPTH{1'b0}} ; - wadig <= {fzero[FIFODEPTH - 1:1],1'b1} ; - radg_0_r <= {FIFODEPTH{1'b0}} ; - radg_r <= {FIFODEPTH{1'b0}} ; - end - else - begin - if (rsm == RSM_BAD) - begin - wad <= isofad ; - end - else if (we) - begin - wad <= wad + 1 ; - end - - if (rsm == RSM_BAD) - begin - wadi <= isofad + 1 ; - end - else if (we) - begin - wadi <= wadi + 1 ; - end - - iwadg[FIFODEPTH - 1] <= wad[FIFODEPTH - 1] ; - begin : iwaddrg_loop - integer i; - for(i = FIFODEPTH - 2; i >= 0; i = i - 1) - begin - iwadg[i] <= wad[i + 1] ^ wad[i] ; - end - end - - wadig[FIFODEPTH - 1] <= wadi[FIFODEPTH - 1] ; - begin : waddrig_loop - integer i; - for(i = FIFODEPTH - 2; i >= 0; i = i - 1) - begin - wadig[i] <= wadi[i + 1] ^ wadi[i] ; - end - end - - if (rsm == RSM_IDLE_RCSMT) - begin - isofad <= wad ; - end - - radg_0_r <= radg ; - radg_r <= radg_0_r ; - - end - end - - always @(posedge clk) - begin : we_reg_proc - if (rst) - begin - we <= 1'b0 ; - end - else - begin - if ((rsm == RSM_INFO | - rsm == RSM_DEST | - rsm == RSM_LENGTH | - rsm == RSM_SOURCE) & - ((rxdv_r & ((DATAWIDTH == 8 & (ncnt[0])) | - (DATAWIDTH == 16 & ncnt[1:0] == 2'b11) | - (DATAWIDTH == 32 & ncnt[2:0] == 3'b111))) | - (!rxdv_r & !we & - ( - (DATAWIDTH==32 & ncnt[2:1]!=2'b00) | - (DATAWIDTH==16 & ncnt[1] !=1'b0) - ) - ) | - (full & !we))) - begin - we <= 1'b1 ; - end - else - begin - we <= 1'b0 ; - end - end - end - - assign ramdata = data ; - - assign ramwe = we ; - - assign ramaddr = wad ; - - assign wadg = iwadg ; - - always @(rsm or - rxdv_r or - rxd_r_max or - rxd_r4 or - stop_r or - bz or - fsm or - ra or - pm or - pb or - dest or - riack_r or - full or - ren_r or - winp or - irprog or - cachenf_r) - begin : rsm_proc - case (rsm) - RSM_IDLE_RCSMT : - begin - if (rxdv_r & !stop_r & ren_r) - begin - if (rxd_r_max[MIIWIDTH-1:0] == 4'b0101) - begin - rsm_c <= RSM_SFD ; - end - else - begin - rsm_c <= RSM_IDLE_RCSMT ; - end - end - else - begin - rsm_c <= RSM_IDLE_RCSMT ; - end - end - RSM_SFD : - begin - if (rxdv_r & !full & cachenf_r) - begin - case (rxd_r4) - 4'b1101 : - begin - rsm_c <= RSM_DEST ; - end - 4'b0101 : - begin - rsm_c <= RSM_SFD ; - end - default : - begin - rsm_c <= RSM_IDLE_RCSMT ; - end - endcase - end - else if (full | !cachenf_r) - begin - rsm_c <= RSM_BAD ; - end - else - begin - rsm_c <= RSM_IDLE_RCSMT ; - end - end - RSM_DEST : - begin - if (!rxdv_r | full | !cachenf_r) - begin - rsm_c <= RSM_BAD ; - end - else if (bz) - begin - rsm_c <= RSM_SOURCE ; - end - else - begin - rsm_c <= RSM_DEST ; - end - end - RSM_SOURCE : - begin - if (!rxdv_r) - begin - if ((pb) & (fsm == FSM_MATCH | ra | (pm & (dest[0])))) - begin - rsm_c <= RSM_SUCC ; - end - else - begin - rsm_c <= RSM_BAD ; - end - end - else if (full | !cachenf_r) - begin - rsm_c <= RSM_BAD ; - end - else if (bz) - begin - rsm_c <= RSM_LENGTH ; - end - else - begin - rsm_c <= RSM_SOURCE ; - end - end - RSM_LENGTH : - begin - if (!rxdv_r) - begin - if ((pb) & (fsm == FSM_MATCH | ra | (pm & (dest[0])))) - begin - rsm_c <= RSM_SUCC ; - end - else - begin - rsm_c <= RSM_BAD ; - end - end - else if (full | !cachenf_r) - begin - rsm_c <= RSM_BAD ; - end - else if (bz) - begin - rsm_c <= RSM_INFO ; - end - else - begin - rsm_c <= RSM_LENGTH ; - end - end - RSM_INFO : - begin - if (!rxdv_r) - begin - if ((winp | pb) & - (fsm == FSM_MATCH | ra | (pm & (dest[0])))) - begin - rsm_c <= RSM_SUCC ; - end - else - begin - rsm_c <= RSM_BAD ; - end - end - else if (full | !cachenf_r) - begin - if (winp) - begin - rsm_c <= RSM_SUCC ; - end - else - begin - rsm_c <= RSM_BAD ; - end - end - else if (fsm == FSM_FAIL & !ra & ~(pm & (dest[0]))) - begin - rsm_c <= RSM_BAD ; - end - else - begin - rsm_c <= RSM_INFO ; - end - end - RSM_SUCC : - begin - rsm_c <= RSM_INT ; - end - RSM_INT : - begin - if (riack_r) - begin - rsm_c <= RSM_INT1 ; - end - else - begin - rsm_c <= RSM_INT ; - end - end - RSM_INT1 : - begin - if (!rxdv_r & !riack_r) - begin - rsm_c <= RSM_IDLE_RCSMT ; - end - else - begin - rsm_c <= RSM_INT1 ; - end - end - default : - begin - if (!rxdv_r & !riack_r & !irprog) - begin - rsm_c <= RSM_IDLE_RCSMT ; - end - else - begin - rsm_c <= RSM_BAD ; - end - end - endcase - end - - always @(posedge clk) - begin : rsm_reg_proc - if (rst) - begin - rsm <= RSM_IDLE_RCSMT ; - end - else - begin - rsm <= rsm_c ; - end - end - - always @(posedge clk) - begin : rprog_reg_proc - if (rst) - begin - irprog <= 1'b0 ; - rprog <= 1'b0 ; - end - else - begin - if (rsm == RSM_IDLE_RCSMT | - rsm == RSM_BAD | - rsm == RSM_INT | - rsm == RSM_INT1) - begin - irprog <= 1'b0 ; - end - else - begin - irprog <= 1'b1 ; - end - - if (winp & irprog) - begin - rprog <= 1'b1 ; - end - else - begin - rprog <= 1'b0 ; - end - end - end - - assign rcpoll = irprog ; - - always @(posedge clk) - begin : bncnt_reg_proc - if (rst) - begin - bcnt <= {7{1'b0}} ; - bz <= 1'b0 ; - ncnt <= 4'b0000 ; - end - else - begin - if(cachenf_r) - begin - if (bz | rsm == RSM_IDLE_RCSMT) - begin - case (rsm) - RSM_IDLE_RCSMT : - begin - bcnt <= 7'b0000101 ; - end - RSM_DEST : - begin - bcnt <= 7'b0000101 ; - end - RSM_SOURCE : - begin - bcnt <= 7'b0000001 ; - end - default : - begin - bcnt <= 7'b0110001 ; - end - endcase - end - else - begin - if (ncnt[0]) - begin - bcnt <= bcnt - 1 ; - end - end - end - else - begin - if(!fcfbci_r) - begin - bcnt <= 7'b0111110 ; - end - else - begin - if (!ncnt[0]) - begin - bcnt <= bcnt - 1 ; - end - end - end - - if (bcnt == 7'b0000000 & !ncnt[0]) - begin - bz <= 1'b1 ; - end - else - begin - bz <= 1'b0 ; - end - - if (rsm == RSM_SFD | rsm == RSM_IDLE_RCSMT) - begin - ncnt <= 4'b0000 ; - end - else - begin - ncnt <= ncnt + 1 ; - end - end - end - - always @(posedge clk) - begin : winp_reg_proc - if (rst) - begin - winp <= 1'b0 ; - end - else - begin - if (rsm == RSM_IDLE_RCSMT) - begin - winp <= 1'b0 ; - end - else if ((rsm == RSM_INFO & bz & cachenf_2r) | - (rsm == RSM_BAD & bz & !cachenf_2r)) - begin - winp <= 1'b1 ; - end - end - end - - always @(crc or rsm or rxd_r_max) - begin : crc_proc - case (rsm) - RSM_IDLE_RCSMT : - begin - crc_c <= {32{1'b1}} ; - end - RSM_DEST, RSM_SOURCE, RSM_LENGTH, RSM_INFO : - begin - crc_c[0] <= crc[28] ^ - rxd_r_max[3] ; - crc_c[1] <= crc[28] ^ crc[29] ^ - rxd_r_max[2] ^ rxd_r_max[3] ; - crc_c[2] <= crc[28] ^ crc[29] ^ crc[30] ^ - rxd_r_max[1] ^ rxd_r_max[2] ^ rxd_r_max[3] ; - crc_c[3] <= crc[29] ^ crc[30] ^ crc[31] ^ - rxd_r_max[0] ^ rxd_r_max[1] ^ rxd_r_max[2] ; - crc_c[4] <= crc[0] ^ crc[28] ^ crc[30] ^ crc[31] ^ - rxd_r_max[0] ^ rxd_r_max[1] ^ rxd_r_max[3] ; - crc_c[5] <= crc[1] ^ crc[28] ^ crc[29] ^ crc[31] ^ - rxd_r_max[0] ^ rxd_r_max[2] ^ rxd_r_max[3] ; - crc_c[6] <= crc[2] ^ crc[29] ^ crc[30] ^ - rxd_r_max[1] ^ rxd_r_max[2] ; - crc_c[7] <= crc[3] ^ crc[28] ^ crc[30] ^ crc[31] ^ - rxd_r_max[0] ^ rxd_r_max[1] ^ rxd_r_max[3] ; - crc_c[8] <= crc[4] ^ crc[28] ^ crc[29] ^ crc[31] ^ - rxd_r_max[0] ^ rxd_r_max[2] ^ rxd_r_max[3] ; - crc_c[9] <= crc[5] ^ crc[29] ^ crc[30] ^ - rxd_r_max[1] ^ rxd_r_max[2] ; - crc_c[10] <= crc[6] ^ crc[28] ^ crc[30] ^ crc[31] ^ - rxd_r_max[0] ^ rxd_r_max[1] ^ rxd_r_max[3] ; - crc_c[11] <= crc[7] ^ crc[28] ^ crc[29] ^ crc[31] ^ - rxd_r_max[0] ^ rxd_r_max[2] ^ rxd_r_max[3] ; - crc_c[12] <= crc[8] ^ crc[28] ^ crc[29] ^ crc[30] ^ - rxd_r_max[1] ^ rxd_r_max[2] ^ rxd_r_max[3] ; - crc_c[13] <= crc[9] ^ crc[29] ^ crc[30] ^ crc[31] ^ - rxd_r_max[0] ^ rxd_r_max[1] ^ rxd_r_max[2] ; - crc_c[14] <= crc[10] ^ crc[30] ^ crc[31] ^ - rxd_r_max[0] ^ rxd_r_max[1] ; - crc_c[15] <= crc[11] ^ crc[31] ^ - rxd_r_max[0] ; - crc_c[16] <= crc[12] ^ crc[28] ^ - rxd_r_max[3] ; - crc_c[17] <= crc[13] ^ crc[29] ^ - rxd_r_max[2] ; - crc_c[18] <= crc[14] ^ crc[30] ^ - rxd_r_max[1] ; - crc_c[19] <= crc[15] ^ crc[31] ^ - rxd_r_max[0] ; - crc_c[20] <= crc[16] ; - crc_c[21] <= crc[17] ; - crc_c[22] <= crc[18] ^ crc[28] ^ - rxd_r_max[3] ; - crc_c[23] <= crc[19] ^ crc[28] ^ crc[29] ^ - rxd_r_max[2] ^ rxd_r_max[3] ; - crc_c[24] <= crc[20] ^ crc[29] ^ crc[30] ^ - rxd_r_max[1] ^ rxd_r_max[2] ; - crc_c[25] <= crc[21] ^ crc[30] ^ crc[31] ^ - rxd_r_max[0] ^ rxd_r_max[1] ; - crc_c[26] <= crc[22] ^ crc[28] ^ crc[31] ^ - rxd_r_max[0] ^ rxd_r_max[3] ; - crc_c[27] <= crc[23] ^ crc[29] ^ - rxd_r_max[2] ; - crc_c[28] <= crc[24] ^ crc[30] ^ - rxd_r_max[1] ; - crc_c[29] <= crc[25] ^ crc[31] ^ - rxd_r_max[0] ; - crc_c[30] <= crc[26] ; - crc_c[31] <= crc[27] ; - end - default : - begin - crc_c <= crc ; - end - endcase - end - - always @(posedge clk) - begin : crc_reg_proc - if (rst) - begin - crc <= {32{1'b1}} ; - end - else - begin - crc <= crc_c ; - end - end - - assign iri_c = (rsm == RSM_INT) ? 1'b1 : 1'b0 ; - - always @(posedge clk) - begin : rint_reg_proc - if (rst) - begin - iri <= 1'b0 ; - riack_r <= 1'b0 ; - rireq <= 1'b0 ; - end - else - begin - iri <= iri_c ; - riack_r <= riack ; - rireq <= iri ; - end - end - - always @(posedge clk) - begin : length_reg_proc - if (rst) - begin - lcnt <= {14{1'b0}} ; - length <= {14{1'b0}} ; - end - else - begin - if ((rsm == RSM_IDLE_RCSMT && cachenf_2r) | - (!fcfbci && !cachenf_2r) | - rsm == RSM_INT1) - begin - lcnt <= {14{1'b0}} ; - end - else if (((rsm == RSM_INFO | - rsm == RSM_LENGTH | - rsm == RSM_DEST | - rsm == RSM_SOURCE) & rxdv_r) | - (fcfbci && !cachenf_2r)) - begin - if (ncnt[0]) - begin - lcnt <= lcnt + 1 ; - end - end - - length[13] <= lcnt[13] ; - begin : length_loop - integer i; - for(i = 12; i >= 0; i = i - 1) - begin - length[i] <= lcnt[i + 1] ^ lcnt[i] ; - end - end - end - end - - always @(posedge clk) - begin : fcfbci_reg_proc - if (rst) - begin - fcfbci <= 1'b0 ; - fcfbci_r <= 1'b0 ; - end - else - begin - - fcfbci_r <= fcfbci ; - - if(!cachenf_2r) - begin - if(rxdv_r && rxd_r4==4'b1101) - begin - fcfbci <= 1'b1 ; - end - else if(!rxdv_r) - begin - fcfbci <= 1'b0 ; - end - end - else - begin - fcfbci <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : eorfff_reg_proc - if (rst) - begin - eorfff <= 1'b0 ; - end - else - begin - if(rsm_c==RSM_IDLE_RCSMT && rsm==RSM_BAD && !cachenf_2r) - begin - eorfff <= 1'b1 ; - end - else - begin - eorfff <= 1'b0 ; - end - end - end - - - always @(posedge clk) - begin : stat_reg_proc - if (rst) - begin - lfield <= {16{1'b0}} ; - ftp <= 1'b0 ; - tl <= 1'b0 ; - ff <= 1'b0 ; - mf <= 1'b0 ; - re <= 1'b0 ; - ce <= 1'b0 ; - db <= 1'b0 ; - rf <= 1'b0 ; - ov <= 1'b0 ; - cs <= 1'b0 ; - end - else - begin - if (rsm == RSM_LENGTH) - begin - if (bcnt[1:0] == 2'b00) - begin - if (!(ncnt[0])) - begin - lfield[3:0] <= rxd_r_max[MIIWIDTH-1:0] ; - end - else - begin - lfield[7:4] <= rxd_r_max[MIIWIDTH-1:0] ; - end - end - else - begin - if (!(ncnt[0])) - begin - lfield[11:8] <= rxd_r_max[MIIWIDTH-1:0] ; - end - else - begin - lfield[15:12] <= rxd_r_max[MIIWIDTH-1:0] ; - end - end - end - - if (lfield > MAX_SIZE) - begin - ftp <= 1'b1 ; - end - else - begin - ftp <= 1'b0 ; - end - - if (lcnt == MAX_FRAME & !iri_c) - begin - tl <= 1'b1 ; - end - else if (rsm == RSM_IDLE_RCSMT) - begin - tl <= 1'b0 ; - end - - if (!iri_c) - begin - if (fsm == FSM_MATCH) - begin - ff <= 1'b0 ; - end - else - begin - ff <= 1'b1 ; - end - end - - if (!iri_c) - begin - mf <= dest[0] ; - end - - if (rxer_r & !iri_c) - begin - re <= 1'b1 ; - end - else if (rsm == RSM_IDLE_RCSMT) - begin - re <= 1'b0 ; - end - - if (rsm == RSM_INFO & !(ncnt[0])) - begin - if (crc == CRCVAL) - begin - ce <= 1'b0 ; - end - else - begin - ce <= 1'b1 ; - end - end - - if (rsm == RSM_INFO) - begin - if (!rxdv_r & (ncnt[0])) - begin - db <= 1'b1 ; - end - else - begin - db <= 1'b0 ; - end - end - - if (!winp & iri_c) - begin - rf <= 1'b1 ; - end - else if (rsm == RSM_IDLE_RCSMT) - begin - rf <= 1'b0 ; - end - - if (rsm == RSM_IDLE_RCSMT) - begin - ov <= 1'b0 ; - end - else if (full | !cachenf_r) - begin - ov <= 1'b1 ; - end - - if (col_r & !iri_c) - begin - cs <= 1'b1 ; - end - else if (rsm == RSM_IDLE_RCSMT) - begin - cs <= 1'b0 ; - end - - - end - end - - always @(posedge clk) - begin : ren_reg_proc - if (rst) - begin - ren_r <= 1'b0 ; - end - else - begin - if (rsm == RSM_IDLE_RCSMT) - begin - ren_r <= ren ; - end - end - end - - always @(fsm or - rsm or - ho or - hp or - dest or - lcnt or - ncnt or - flcnt or - perfm or - hash or - pr or - fa or - invm or - rif or - matchval or - match) - begin : fsm_proc - case (fsm) - FSM_IDLE : - begin - if (lcnt[2:0] == 3'b101 & (ncnt[0])) - begin - if (pr) - begin - fsm_c <= FSM_MATCH ; - end - else if (ho | (hp & (dest[0]))) - begin - fsm_c <= FSM_HASH ; - end - else if (!hp) - begin - fsm_c <= FSM_PERF16 ; - end - else - begin - fsm_c <= FSM_PERF1 ; - end - end - else - begin - fsm_c <= FSM_IDLE ; - end - end - FSM_PERF1 : - begin - if (fa == 6'b101100) - begin - if(perfm | - (matchval & match)) - begin - fsm_c <= FSM_MATCH ; - end - else - begin - fsm_c <= FSM_FAIL ; - end - end - else - begin - fsm_c <= FSM_PERF1 ; - end - end - FSM_PERF16 : - begin - if ((flcnt == 3'b010 & perfm & !rif) | - (fa == 6'b110010 & rif & invm) | - (matchval & match)) - begin - fsm_c <= FSM_MATCH ; - end - else if (fa == 6'b110010) - begin - fsm_c <= FSM_FAIL ; - end - else - begin - fsm_c <= FSM_PERF16 ; - end - end - FSM_HASH : - begin - if (matchval & match) - begin - fsm_c <= FSM_MATCH ; - end - else if (flcnt == 3'b101) - begin - if (hash) - begin - fsm_c <= FSM_MATCH ; - end - else - begin - fsm_c <= FSM_FAIL ; - end - end - else - begin - fsm_c <= FSM_HASH ; - end - end - FSM_MATCH : - begin - if (rsm == RSM_IDLE_RCSMT) - begin - fsm_c <= FSM_IDLE ; - end - else - begin - fsm_c <= FSM_MATCH ; - end - end - default : - begin - if (rsm == RSM_IDLE_RCSMT) - begin - fsm_c <= FSM_IDLE ; - end - else - begin - fsm_c <= FSM_FAIL ; - end - end - endcase - end - - always @(posedge clk) - begin : fsm_reg_proc - if (rst) - begin - fsm <= FSM_IDLE ; - end - else - begin - fsm <= fsm_c ; - end - end - - assign bcnt20 = bcnt[2:0] ; - - always @(posedge clk) - begin : dest_reg_proc - if (rst) - begin - dest <= {48{1'b0}} ; - end - else - begin - if (rsm == RSM_DEST) - begin - if (!(ncnt[0])) - begin - case (bcnt20) - 3'b101 : - begin - dest[3:0] <= rxd_r_max[MIIWIDTH-1:0] ; - end - 3'b100 : - begin - dest[11:8] <= rxd_r_max[MIIWIDTH-1:0] ; - end - 3'b011 : - begin - dest[19:16] <= rxd_r_max[MIIWIDTH-1:0] ; - end - 3'b010 : - begin - dest[27:24] <= rxd_r_max[MIIWIDTH-1:0] ; - end - 3'b001 : - begin - dest[35:32] <= rxd_r_max[MIIWIDTH-1:0] ; - end - default : - begin - dest[43:40] <= rxd_r_max[MIIWIDTH-1:0] ; - end - endcase - end - else - begin - case (bcnt20) - 3'b101 : - begin - dest[7:4] <= rxd_r_max[MIIWIDTH-1:0] ; - end - 3'b100 : - begin - dest[15:12] <= rxd_r_max[MIIWIDTH-1:0] ; - end - 3'b011 : - begin - dest[23:20] <= rxd_r_max[MIIWIDTH-1:0] ; - end - 3'b010 : - begin - dest[31:28] <= rxd_r_max[MIIWIDTH-1:0] ; - end - 3'b001 : - begin - dest[39:36] <= rxd_r_max[MIIWIDTH-1:0] ; - end - default : - begin - dest[47:44] <= rxd_r_max[MIIWIDTH-1:0] ; - end - endcase - end - end - end - end - - always @(posedge clk) - begin : hash_reg_proc - if (rst) - begin - crchash <= {9{1'b0}} ; - hash <= 1'b0 ; - fdata_r <= {16{1'b0}} ; - end - else - begin - if (fsm == FSM_HASH & flcnt == 3'b000) - begin - crchash <= {crc[23], crc[24], crc[25], crc[26], - crc[27], crc[28], crc[29], crc[30], crc[31]} ; - end - - hash <= fdata_r[crchash[3:0]] ; - - fdata_r <= fdata ; - end - end - - always @(perfm or flcnt or fsm or fdata_r or dest) - begin : perfm_proc - if ((flcnt == 3'b001 & fdata_r != dest[47:32]) | - (flcnt == 3'b000 & fdata_r != dest[31:16]) | - (flcnt == 3'b010 & fdata_r != dest[15:0]) | fsm == FSM_IDLE) - begin - perfm_c <= 1'b0 ; - end - else if (flcnt == 3'b010 & fdata_r == dest[15:0]) - begin - perfm_c <= 1'b1 ; - end - else - begin - perfm_c <= perfm ; - end - end - - always @(posedge clk) - begin : perfm_reg_proc - if (rst) - begin - invm <= 1'b0 ; - perfm <= 1'b0 ; - end - else - begin - perfm <= perfm_c ; - - if (fsm == FSM_IDLE) - begin - invm <= 1'b1 ; - end - else if (flcnt == 3'b001 & perfm_c) - begin - invm <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : fa_reg_proc - if (rst) - begin - flcnt <= {3{1'b0}} ; - fa <= {ADDRDEPTH{1'b0}} ; - end - else - begin - case (fsm) - FSM_PERF1, FSM_PERF16 : - begin - fa <= fa + 1 ; - end - FSM_HASH : - begin - fa[5:0] <= {1'b0, crchash[8:4]} ; - end - default : - begin - if (hp & !(dest[0])) - begin - fa <= PERF1_ADDR ; - end - else - begin - fa <= {ADDRDEPTH{1'b0}} ; - end - end - endcase - - if (fsm_c == FSM_IDLE | - (flcnt == 3'b010 & fsm_c == FSM_PERF16) | - (flcnt == 3'b010 & fsm_c == FSM_PERF1)) - begin - flcnt <= {3{1'b0}} ; - end - else if (fsm == FSM_PERF1 | - fsm == FSM_PERF16 | - fsm == FSM_HASH) - begin - flcnt <= flcnt + 1 ; - end - end - end - - assign faddr = fa ; - - assign matchdata = dest ; - - always @(posedge clk) - begin : matchen_reg_proc - if (rst) - begin - matchen <= 1'b0 ; - end - else - begin - if (fsm == FSM_PERF1 | fsm == FSM_HASH | fsm == FSM_PERF16) - begin - matchen <= 1'b1 ; - end - else - begin - matchen <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : stop_reg_proc - if (rst) - begin - stop_r <= 1'b0 ; - stopo <= 1'b0 ; - end - else - begin - stop_r <= stopi ; - - if (stop_r & rsm == RSM_IDLE_RCSMT) - begin - stopo <= 1'b1 ; - end - else - begin - stopo <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : rcscnt_reg_proc - if (rst) - begin - rcscnt <= {8{1'b0}} ; - rcs <= 1'b0 ; - rcsreq <= 1'b0 ; - rcsack_r <= 1'b0 ; - end - else - begin - if (rcscnt == 8'b00000000) - begin - rcscnt <= 8'b10000000 ; - end - else - begin - rcscnt <= rcscnt - 1 ; - end - - if (rcscnt == 8'b00000000) - begin - rcs <= 1'b1 ; - end - else if (rcsack_r) - begin - rcs <= 1'b0 ; - end - - if (rcs & !rcsack_r) - begin - rcsreq <= 1'b1 ; - end - else if (rcsack_r) - begin - rcsreq <= 1'b0 ; - end - - rcsack_r <= rcsack ; - end - end - - always @(posedge clk) - begin : focnt_reg_proc - if (rst) - begin - focnt <= {11{1'b0}} ; - oco <= 1'b0 ; - focl_r <= 1'b0 ; - focg <= {11{1'b0}} ; - end - else - begin - if (focl_r) - begin - focnt <= {11{1'b0}} ; - end - else if ((rsm == RSM_DEST | - rsm == RSM_SOURCE | - rsm == RSM_LENGTH | - rsm == RSM_INFO | - rsm == RSM_SFD) & - full) - begin - focnt <= focnt + 1 ; - end - - if (focl_r) - begin - oco <= 1'b0 ; - end - else if ((rsm == RSM_DEST | - rsm == RSM_SOURCE | - rsm == RSM_LENGTH | - rsm == RSM_INFO) & - focnt == 11'b11111111111 & - (full | !cachenf_r)) - begin - oco <= 1'b1 ; - end - - focl_r <= focl ; - - focg[10] <= focnt[10] ; - begin : focg_loop - integer i; - for(i = 9; i >= 0; i = i - 1) - begin - focg[i] <= focnt[i] ^ focnt[i + 1] ; - end - end - end - end - - assign foclack = focl_r ; - - always @(posedge clk) - begin : mfcnt_reg_proc - if (rst) - begin - mfcnt <= {16{1'b0}} ; - mfo <= 1'b0 ; - mfcl_r <= 1'b0 ; - mfcg <= {16{1'b0}} ; - end - else - begin - if (mfcl_r) - begin - mfcnt <= {16{1'b0}} ; - end - else if ( - eorfff && - (pb | winp) && - ( - fsm==FSM_MATCH | ra | - ( - pm && dest[0] - ) - ) - ) - begin - mfcnt <= mfcnt + 1'b1 ; - end - - if (mfcl_r) - begin - mfo <= 1'b0 ; - end - else if ( - mfcnt=={16{1'b1}} && pb && - ( - fsm==FSM_MATCH | ra | - ( - pm && dest[0] - ) - ) - ) - begin - mfo <= 1'b1 ; - end - - mfcl_r <= mfcl; - - begin : mfcg_reg_write - integer i; - mfcg[15] <= mfcnt[15]; - for(i = 14; i >= 0; i = i - 1) - begin - mfcg[i] <= mfcnt[i] ^ mfcnt[i + 1]; - end - end - end - end - - assign mfclack = mfcl_r ; - - assign fzero = {FIFODEPTH{1'b0}} ; - - assign mzero_max = {(MIIWIDTH_MAX + 1){1'b0}} ; - - assign rxd_r_max = {mzero_max[MIIWIDTH_MAX + 1:MIIWIDTH], - rxd_r}; - -endmodule - - - -module RFIFO_V ( - clk, - rst, - ramdata, - ramaddr, - fifore, - ffo, - rfo, - mfo, - tlo, - reo, - dbo, - ceo, - ovo, - cso, - flo, - fifodata, - cachere, - cachene, - cachenf, - radg, - rireq, - ffi, - rfi, - mfi, - tli, - rei, - dbi, - cei, - ovi, - csi, - fli, - wadg, - riack - ); - - parameter DATAWIDTH = 32; - parameter DATADEPTH = 32; - parameter FIFODEPTH = 9; - parameter CACHEDEPTH = 2; - - input clk; - input rst; - - input [DATAWIDTH - 1:0] ramdata; - output [FIFODEPTH - 1:0] ramaddr; - wire [FIFODEPTH - 1:0] ramaddr; - - input fifore; - output ffo; - wire ffo; - output rfo; - wire rfo; - output mfo; - wire mfo; - output tlo; - wire tlo; - output reo; - wire reo; - output dbo; - wire dbo; - output ceo; - wire ceo; - output ovo; - wire ovo; - output cso; - wire cso; - output [13:0] flo; - wire [13:0] flo; - output [DATAWIDTH - 1:0] fifodata; - wire [DATAWIDTH - 1:0] fifodata; - - input cachere; - output cachene; - wire cachene; - - output cachenf; - wire cachenf; - output [FIFODEPTH - 1:0] radg; - reg [FIFODEPTH - 1:0] radg; - - input rireq; - input ffi; - input rfi; - input mfi; - input tli; - input rei; - input dbi; - input cei; - input ovi; - input csi; - input [13:0] fli; - input [FIFODEPTH - 1:0] wadg; - output riack; - wire riack; - - - parameter CSWIDTH = 23; - reg [CSWIDTH - 1:0] csmem[(1'b1 << CACHEDEPTH) - 1:0]; - wire cswe; - wire csre; - reg csnf; - reg csne; - reg [CACHEDEPTH - 1:0] cswad; - reg [CACHEDEPTH - 1:0] cswadi; - reg [CACHEDEPTH - 1:0] csrad; - reg [CACHEDEPTH - 1:0] csrad_r; - wire [CSWIDTH - 1:0] csdi; - wire [CSWIDTH - 1:0] csdo; - - reg [FIFODEPTH - 1:0] stat; - reg [FIFODEPTH - 1:0] rad_c; - reg [FIFODEPTH - 1:0] rad; - reg [FIFODEPTH - 1:0] wad_c; - reg [FIFODEPTH - 1:0] wad; - reg [FIFODEPTH - 1:0] wadg_0_r; - reg [FIFODEPTH - 1:0] wadg_r; - reg [13:0] flibin_c; - reg [13:0] flibin; - reg [13:0] fli_r; - - reg rireq_r; - reg iriack; - - wire [FIFODEPTH - 1:0] fzero; - - always @(posedge clk) - begin : csmem_reg_proc - if (rst) - begin : csmem_reset - integer i; - for(i = ((1'b1 << CACHEDEPTH) - 1); i >= 0; i = i - 1) - begin - csmem[i] <= {CSWIDTH{1'b0}}; - end - csrad_r <= csrad ; - end - else - begin - csmem[cswad] <= csdi ; - csrad_r <= csrad ; - end - end - - always @(posedge clk) - begin : cswad_reg_proc - if (rst) - begin - cswad <= {CACHEDEPTH{1'b1}} ; - end - else - begin - if (cswe) - begin - cswad <= cswad + 1 ; - end - end - end - - always @(posedge clk) - begin : csrad_reg_proc - if (rst) - begin - csrad <= {CACHEDEPTH{1'b1}} ; - end - else - begin - if (csre) - begin - csrad <= csrad + 1 ; - end - end - end - - always @(posedge clk) - begin : csne_reg_proc - if (rst) - begin - csne <= 1'b0 ; - end - else - begin - if (cswad == csrad) - begin - csne <= 1'b0 ; - end - else - begin - csne <= 1'b1 ; - end - end - end - - always @(cswad) - begin : cswadi_drv - cswadi <= cswad + 1; - end - - always @(posedge clk) - begin : csnf_reg_proc - if (rst) - begin - csnf <= 1'b0 ; - end - else - begin - if (cswadi == csrad) - begin - csnf <= 1'b0 ; - end - else - begin - csnf <= 1'b1 ; - end - end - end - - always @(fli_r) - begin : flibin_proc - reg[13:0] flibin_v; - flibin_v[13] = fli_r[13]; - begin : flibin_loop - integer i; - for(i = 12; i >= 0; i = i - 1) - begin - flibin_v[i] = flibin_v[i + 1] ^ fli_r[i]; - end - end - flibin_c = flibin_v ; - end - - always @(posedge clk) - begin : flibin_reg_proc - if (rst) - begin - flibin <= {14{1'b0}} ; - fli_r <= {14{1'b0}} ; - end - else - begin - flibin <= flibin_c ; - fli_r <= fli ; - end - end - - assign cachene = csne ; - - assign cachenf = csnf ; - - assign cswe = rireq_r & ~iriack ; - - assign csdo = csmem[csrad_r] ; - - assign csdi = {ffi, rfi, mfi, tli, rei, dbi, cei, ovi, csi, flibin} ; - - assign ffo = csdo[CSWIDTH - 1] ; - - assign rfo = csdo[CSWIDTH - 2] ; - - assign mfo = csdo[CSWIDTH - 3] ; - - assign tlo = csdo[CSWIDTH - 4] ; - - assign reo = csdo[CSWIDTH - 5] ; - - assign dbo = csdo[CSWIDTH - 6] ; - - assign ceo = csdo[CSWIDTH - 7] ; - - assign ovo = csdo[CSWIDTH - 8] ; - - assign cso = csdo[CSWIDTH - 9]; - - assign flo = csdo[13:0] ; - - assign csre = cachere ; - - always @(posedge clk) - begin : rireq_reg_proc - if (rst) - begin - rireq_r <= 1'b0 ; - end - else - begin - rireq_r <= rireq ; - end - end - - always @(posedge clk) - begin : irecack_reg_proc - if (rst) - begin - iriack <= 1'b0 ; - end - else - begin - iriack <= rireq_r ; - end - end - - assign riack = iriack ; - - always @(rad or fifore) - begin : rad_proc - if (fifore) - begin - rad_c <= rad + 1 ; - end - else - begin - rad_c <= rad ; - end - end - - always @(posedge clk) - begin : rad_reg_proc - if (rst) - begin - rad <= {FIFODEPTH{1'b0}} ; - end - else - begin - rad <= rad_c ; - end - end - - always @(posedge clk) - begin : radg_reg_proc - if (rst) - begin - radg <= {FIFODEPTH{1'b0}} ; - end - else - begin - radg[FIFODEPTH - 1] <= rad[FIFODEPTH - 1] ; - begin : radg_loop - integer i; - for(i = FIFODEPTH - 2; i >= 0; i = i - 1) - begin - radg[i] <= rad[i] ^ rad[i + 1] ; - end - end - end - end - - always @(posedge clk) - begin : wadg_reg_proc - if (rst) - begin - wadg_0_r <= {FIFODEPTH{1'b0}} ; - wadg_r <= {FIFODEPTH{1'b0}} ; - end - else - begin - wadg_0_r <= wadg; - wadg_r <= wadg_0_r; - end - end - - always @(wadg_r) - begin : wad_proc - reg[FIFODEPTH - 1:0] wad_v; - wad_v[FIFODEPTH - 1] = wadg_r[FIFODEPTH - 1]; - begin : wad_loop - integer i; - for(i = FIFODEPTH - 2; i >= 0; i = i - 1) - begin - wad_v[i] = wad_v[i + 1] ^ wadg_r[i]; - end - end - wad_c = wad_v ; - end - - always @(posedge clk) - begin : ad_reg_proc - if (rst) - begin - wad <= {FIFODEPTH{1'b0}} ; - end - else - begin - wad <= wad_c ; - end - end - - always @(posedge clk) - begin : stat_reg_proc - if (rst) - begin - stat <= {FIFODEPTH{1'b0}} ; - end - else - begin - stat <= wad - rad ; - end - end - - assign ramaddr = rad_c ; - - assign fifodata = ramdata ; - - - assign fzero = {FIFODEPTH{1'b0}}; - -endmodule - - - -module RLSM_V ( - clk, - rst, - fifodata, - fifore, - cachere, - dmaack, - dmaeob, - dmadatai, - dmaaddr, - dmareq, - dmawr, - dmacnt, - dmaaddro, - dmadatao, - rprog, - rcpoll, - fifocne, - ff, - rf, - mf, - db, - re, - ce, - tl, - ftp, - ov, - cs, - length, - pbl, - dsl, - rpoll, - rdbadc, - rdbad, - rpollack, - rcompack, - bufack, - des, - fbuf, - stat, - ru, - rcomp, - bufcomp, - stopi, - stopo - ); - - parameter DATAWIDTH = 32; - parameter DATADEPTH = 32; - parameter FIFODEPTH = 9; - - `include "utility.v" - - input clk; - input rst; - - input [DATAWIDTH - 1:0] fifodata; - output fifore; - wire fifore; - output cachere; - wire cachere; - - input dmaack; - input dmaeob; - input [DATAWIDTH - 1:0] dmadatai; - input [DATADEPTH - 1:0] dmaaddr; - output dmareq; - wire dmareq; - output dmawr; - wire dmawr; - output [FIFODEPTH_MAX - 1:0] dmacnt; - reg [FIFODEPTH_MAX - 1:0] dmacnt; - output [DATADEPTH - 1:0] dmaaddro; - reg [DATADEPTH - 1:0] dmaaddro; - output [DATAWIDTH - 1:0] dmadatao; - reg [DATAWIDTH - 1:0] dmadatao; - - input rprog; - input rcpoll; - input fifocne; - input ff; - input rf; - input mf; - input db; - input re; - input ce; - input tl; - input ftp; - input ov; - input cs; - input [13:0] length; - - input [5:0] pbl; - input [4:0] dsl; - input rpoll; - input rdbadc; - input [DATADEPTH - 1:0] rdbad; - output rpollack; - reg rpollack; - - input rcompack; - input bufack; - output des; - reg des; - output fbuf; - reg fbuf; - output stat; - reg stat; - output ru; - reg ru; - output rcomp; - reg rcomp; - output bufcomp; - reg bufcomp; - - input stopi; - output stopo; - reg stopo; - - - - reg [3:0] lsm_c; - reg [3:0] lsm; - reg [3:0] lsm_r; - reg own_c; - reg own; - reg rch; - reg rer; - reg rls; - reg rfs; - reg rde; - wire res_c; - reg [10:0] bs1; - reg [10:0] bs2; - - reg adwrite; - reg [DATADEPTH - 1:0] bad; - reg [DATADEPTH - 1:0] dad; - reg [10:0] bcnt; - reg [DATADEPTH - 1:0] statad; - reg [DATADEPTH - 1:0] tstatad; - reg dbadc_r; - - reg req_c; - reg req; - wire [2:0] dmaaddr20; - wire [1:0] addr10; - reg [DATADEPTH_MAX - 1:0] dataimax_r; - wire [31:0] fstat; - - reg rprog_r; - reg rcpoll_r; - reg rcpoll_r2; - reg whole; - - reg [13:0] fifolev_r; - reg [13:0] fbcnt; - reg [13:0] fbcnt_c; - reg [13:0] length_r; - wire ififore; - reg ififore_r; - reg icachere; - wire [FIFODEPTH_MAX - 1:0] bsmax; - wire [FIFODEPTH_MAX - 1:0] flmax; - wire [FIFODEPTH_MAX - 1:0] blmax; - reg fl_g_16; - reg fl_g_bs; - reg fl_g_bl; - reg bl_g_bs; - reg pblz; - - reg stop_r; - - wire [FIFODEPTH_MAX - 1:0] fzero_max; - wire [DATAWIDTH_MAX + 1:0] dmadatai_max; - wire [DATAWIDTH_MAX + 1:0] dzero_max; - - always @(posedge clk) - begin : dataimax_reg_proc - if (rst) - begin - dataimax_r <= {DATADEPTH_MAX{1'b1}} ; - end - else - begin - case (DATAWIDTH) - 8 : - begin - case (dmaaddr20) - 3'b000, 3'b100 : - begin - dataimax_r[7:0] <= dmadatai_max[DATAWIDTH-1:0] ; - end - 3'b001, 3'b101 : - begin - dataimax_r[15:8] <= dmadatai_max[DATAWIDTH-1:0] ; - end - 3'b010, 3'b110 : - begin - dataimax_r[23:16] <= dmadatai_max[DATAWIDTH-1:0] ; - end - default : - begin - dataimax_r[31:24] <= dmadatai_max[DATAWIDTH-1:0] ; - end - endcase - end - 16 : - begin - if (!(dmaaddr[1])) - begin - dataimax_r[15:0] <= dmadatai_max[DATAWIDTH-1:0] ; - end - else - begin - dataimax_r[31:16] <= dmadatai_max[DATAWIDTH-1:0] ; - end - end - default : - begin - dataimax_r <= dmadatai_max[31:0] ; - end - endcase - end - end - - always @(posedge clk) - begin : fifolev_reg_proc - if (rst) - begin - length_r <= {14{1'b0}} ; - fifolev_r <= {14{1'b0}} ; - fl_g_bs <= 1'b0 ; - fl_g_16 <= 1'b0 ; - fl_g_bl <= 1'b0 ; - bl_g_bs <= 1'b0 ; - pblz <= 1'b0 ; - end - else - begin - length_r <= length; - - fifolev_r <= length_r - fbcnt_c ; - - if (flmax >= bsmax) - begin - fl_g_bs <= 1'b1 ; - end - else - begin - fl_g_bs <= 1'b0 ; - end - - case (DATAWIDTH) - 8 : - begin - if (flmax > ({fzero_max[FIFODEPTH_MAX - 1:6], - 6'b111111})) - begin - fl_g_16 <= 1'b1 ; - end - else - begin - fl_g_16 <= 1'b0 ; - end - end - 16 : - begin - if (flmax > ({fzero_max[FIFODEPTH_MAX - 1:5], - 5'b11111})) - begin - fl_g_16 <= 1'b1 ; - end - else - begin - fl_g_16 <= 1'b0 ; - end - end - default : - begin - if (flmax > ({fzero_max[FIFODEPTH_MAX - 1:4], - 4'b1111})) - begin - fl_g_16 <= 1'b1 ; - end - else - begin - fl_g_16 <= 1'b0 ; - end - end - endcase - - if (flmax >= (blmax + 1'b1)) - begin - fl_g_bl <= 1'b1 ; - end - else - begin - fl_g_bl <= 1'b0 ; - end - - if (blmax >= bsmax) - begin - bl_g_bs <= 1'b1 ; - end - else - begin - bl_g_bs <= 1'b0 ; - end - - if (pbl == 6'b000000) - begin - pblz <= 1'b1 ; - end - else - begin - pblz <= 1'b0 ; - end - end - end - - assign flmax = (DATAWIDTH == 8) ? {fzero_max[FIFODEPTH_MAX - 1:14], - fifolev_r} : - (DATAWIDTH == 16) ? {fzero_max[FIFODEPTH_MAX - 1:13], - fifolev_r[13:1]} : - {fzero_max[FIFODEPTH_MAX - 1:12], - fifolev_r[13:2]} ; - - assign blmax = {fzero_max[FIFODEPTH_MAX - 1:6], pbl} ; - - assign bsmax = (DATAWIDTH == 8) ? {fzero_max[FIFODEPTH_MAX - 1:11], - bcnt} : - (DATAWIDTH == 16) ? {fzero_max[FIFODEPTH_MAX - 1:10], - bcnt[10:1]} : - {fzero_max[FIFODEPTH_MAX - 1:9], - bcnt[10:2]} ; - - always @(lsm or - fl_g_bs or - fl_g_bl or - bl_g_bs or - pblz or - blmax or - bsmax or - flmax or - fzero_max) - begin : dmacnt_proc - if (lsm == LSM_DES0 | - lsm == LSM_DES1 | - lsm == LSM_DES2 | - lsm == LSM_DES3 | - lsm == LSM_STAT | - lsm == LSM_FSTAT | - lsm == LSM_DES0P) - begin - case (DATAWIDTH) - 8 : - begin - dmacnt <= {fzero_max[FIFODEPTH_MAX - 1:3], 3'b100} ; - end - 16 : - begin - dmacnt <= {fzero_max[FIFODEPTH_MAX - 1:3], 3'b010} ; - end - default : - begin - dmacnt <= {fzero_max[FIFODEPTH_MAX - 1:3], 3'b001} ; - end - endcase - end - else - begin - if (pblz) - begin - if (fl_g_bs) - begin - dmacnt <= bsmax ; - end - else - begin - dmacnt <= flmax ; - end - end - else - begin - if (fl_g_bl) - begin - if (bl_g_bs) - begin - dmacnt <= bsmax ; - end - else - begin - dmacnt <= blmax ; - end - end - else - begin - if (fl_g_bs) - begin - dmacnt <= bsmax ; - end - else - begin - dmacnt <= flmax ; - end - end - end - end - end - - always @(req or - lsm or - lsm_c or - fifocne or - fl_g_bl or - fl_g_16 or - pblz or - whole or - rprog_r or - dmaack or - dmaeob or - flmax or - fzero_max) - begin : req_proc - case (lsm) - LSM_BUF1, LSM_BUF2 : - begin - if ((dmaack & dmaeob) | lsm_c==LSM_NXT) - begin - req_c <= 1'b0 ; - end - else if (fifocne | (rprog_r & ((fl_g_bl & !pblz) | - (fl_g_16 & pblz)))) - begin - req_c <= 1'b1 ; - end - else - begin - req_c <= req ; - end - end - LSM_DES0, LSM_DES1, LSM_DES2, - LSM_DES3, LSM_STAT, LSM_DES0P : - begin - if (dmaack) - begin - req_c <= 1'b0 ; - end - else - begin - req_c <= 1'b1 ; - end - end - LSM_FSTAT : - begin - if (dmaack | !whole | - (DATAWIDTH == 8 & flmax[1:0] != fzero_max[1:0]) - | - (DATAWIDTH == 16 & flmax[ 1] != fzero_max[1])) - begin - req_c <= 1'b0 ; - end - else - begin - req_c <= 1'b1 ; - end - end - default : - begin - req_c <= 1'b0 ; - end - endcase - end - - always @(posedge clk) - begin : req_reg_proc - if (rst) - begin - req <= 1'b0 ; - end - else - begin - req <= req_c ; - end - end - - always @(lsm or bad or dad or statad) - begin : dmaaddro_proc - case (lsm) - LSM_BUF1, LSM_BUF2 : - begin - dmaaddro <= bad ; - end - LSM_STAT, LSM_FSTAT : - begin - dmaaddro <= statad ; - end - default : - begin - dmaaddro <= dad ; - end - endcase - end - - assign fstat = {1'b0, ff, length, res_c, rde, - RDES0_RV[13:12], rf, mf, rfs, rls, tl, - cs, ftp, RDES0_RV[4], re, db, ce, ov} ; - - assign dmawr = (lsm == LSM_STAT | - lsm == LSM_FSTAT | - lsm == LSM_BUF1 | - lsm == LSM_BUF2) ? 1'b1 : 1'b0 ; - - always @(fifodata or lsm or addr10 or fstat) - begin : dmadatao_proc - if (lsm == LSM_BUF1 | lsm == LSM_BUF2) - begin - dmadatao <= fifodata ; - end - else - begin - case (DATAWIDTH) - 8 : - begin - case (addr10) - 2'b00 : - begin - dmadatao <= fstat[7:0] ; - end - 2'b01 : - begin - dmadatao <= fstat[15:8] ; - end - 2'b10 : - begin - dmadatao <= fstat[23:16] ; - end - default : - begin - dmadatao <= fstat[31:24] ; - end - endcase - end - 16 : - begin - if (addr10 == 2'b00) - begin - dmadatao <= fstat[15:0] ; - end - else - begin - dmadatao <= fstat[31:16] ; - end - end - default : - begin - dmadatao <= fstat ; - end - endcase - end - end - - assign dmareq = req ; - - always @(lsm or - rcpoll_r or - rcpoll_r2 or - rpoll or - dmaack or - dmaeob or - own_c or - bs1 or - bs2 or - whole or - rch or - stop_r or - own or - bcnt or - dbadc_r) - begin : lsm_proc - case (lsm) - LSM_IDLE : - begin - if (!dbadc_r & !stop_r & ((rcpoll_r & !rcpoll_r2) | rpoll)) - begin - lsm_c <= LSM_DES0 ; - end - else - begin - lsm_c <= LSM_IDLE ; - end - end - LSM_DES0 : - begin - if (dmaack & dmaeob) - begin - if (own_c) - begin - lsm_c <= LSM_DES1 ; - end - else - begin - lsm_c <= LSM_IDLE ; - end - end - else - begin - lsm_c <= LSM_DES0 ; - end - end - LSM_DES0P : - begin - if (dmaack & dmaeob) - begin - if (!own_c | whole) - begin - lsm_c <= LSM_FSTAT ; - end - else - begin - lsm_c <= LSM_STAT ; - end - end - else - begin - lsm_c <= LSM_DES0P ; - end - end - LSM_DES1 : - begin - if (dmaack & dmaeob) - begin - lsm_c <= LSM_DES2 ; - end - else - begin - lsm_c <= LSM_DES1 ; - end - end - LSM_DES2 : - begin - if (dmaack & dmaeob) - begin - if (bs1 == 11'b00000000000) - begin - lsm_c <= LSM_DES3 ; - end - else - begin - lsm_c <= LSM_BUF1 ; - end - end - else - begin - lsm_c <= LSM_DES2 ; - end - end - LSM_DES3 : - begin - if (dmaack & dmaeob) - begin - if (bs2 != 11'b00000000000 & !rch) - begin - lsm_c <= LSM_BUF2 ; - end - else - begin - lsm_c <= LSM_NXT ; - end - end - else - begin - lsm_c <= LSM_DES3 ; - end - end - LSM_BUF1 : - begin - if (whole | bcnt == 11'b00000000000) - begin - lsm_c <= LSM_DES3 ; - end - else if(dbadc_r) - begin - lsm_c <= LSM_IDLE ; - end - else - begin - lsm_c <= LSM_BUF1 ; - end - end - LSM_BUF2 : - begin - if (whole | bcnt == 11'b00000000000) - begin - lsm_c <= LSM_NXT ; - end - else if(dbadc_r) - begin - lsm_c <= LSM_IDLE ; - end - else - begin - lsm_c <= LSM_BUF2 ; - end - end - LSM_NXT : - begin - if (whole) - begin - if (stop_r) - begin - lsm_c <= LSM_FSTAT ; - end - else - begin - lsm_c <= LSM_DES0P ; - end - end - else - begin - lsm_c <= LSM_DES0P ; - end - end - LSM_STAT : - begin - if (dmaack & dmaeob) - begin - lsm_c <= LSM_DES1 ; - end - else - begin - lsm_c <= LSM_STAT ; - end - end - default : - begin - if (dmaack & dmaeob) - begin - if (own & !stop_r) - begin - lsm_c <= LSM_DES1 ; - end - else - begin - lsm_c <= LSM_IDLE ; - end - end - else - begin - lsm_c <= LSM_FSTAT ; - end - end - endcase - end - - always @(posedge clk) - begin : rlsm_reg_proc - if (rst) - begin - lsm <= LSM_IDLE ; - lsm_r <= LSM_IDLE ; - end - else - begin - lsm <= lsm_c ; - lsm_r <= lsm ; - end - end - - always @(posedge clk) - begin : rpollack_reg_proc - if (rst) - begin - rpollack <= 1'b0 ; - end - else - begin - if (rpoll & !dbadc_r) - begin - rpollack <= 1'b1 ; - end - else if (!rpoll) - begin - rpollack <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : bcnt_reg_proc - if (rst) - begin - bcnt <= {11{1'b1}} ; - end - else - begin - if (lsm == LSM_DES2) - begin - bcnt <= bs1 ; - end - else if (lsm == LSM_DES3) - begin - bcnt <= bs2 ; - end - else - begin - if (dmaack) - begin - case (DATAWIDTH) - 8 : - begin - bcnt <= bcnt - 1 ; - end - 16 : - begin - bcnt <= {(bcnt[10:1] - 1), 1'b0} ; - end - default : - begin - bcnt <= {(bcnt[10:2] - 1), 2'b00} ; - end - endcase - end - end - end - end - - always @(own or - dmaack or - dmaeob or - lsm or - dmadatai_max) - begin : own_proc - if (dmaack & dmaeob & (lsm == LSM_DES0 | lsm == LSM_DES0P)) - begin - own_c <= dmadatai_max[DATAWIDTH - 1] ; - end - else - begin - own_c <= own ; - end - end - - always @(posedge clk) - begin : des1_reg_proc - reg ft22; - if (rst) - begin - rer <= 1'b0 ; - rch <= 1'b0 ; - bs2 <= {11{1'b0}} ; - bs1 <= {11{1'b0}} ; - end - else - begin - if (lsm == LSM_DES1 & dmaack) - begin - case (DATAWIDTH) - 8 : - begin - case (dmaaddr20) - 3'b000, 3'b100 : - begin - bs1[7:0] <= dmadatai_max[7:0] ; - end - 3'b001, 3'b101 : - begin - bs1[10:8] <= dmadatai_max[2:0] ; - bs2[4:0] <= dmadatai_max[7:3] ; - end - 3'b010, 3'b110 : - begin - bs2[10:5] <= dmadatai_max[5:0] ; - end - default : - begin - rer <= dmadatai_max[1] ; - rch <= dmadatai_max[0] ; - end - endcase - end - 16 : - begin - case (dmaaddr20) - 3'b000, 3'b100 : - begin - bs1[10:0] <= dmadatai_max[10:0] ; - bs2[4:0] <= dmadatai_max[15:11] ; - end - default : - begin - bs2[10:5] <= dmadatai_max[5:0] ; - rer <= dmadatai_max[9] ; - rch <= dmadatai_max[8] ; - end - endcase - end - default : - begin - rer <= dmadatai_max[25] ; - rch <= dmadatai_max[24] ; - bs2 <= dmadatai_max[21:11] ; - bs1 <= dmadatai_max[10:0] ; - end - endcase - end - end - end - - always @(posedge clk) - begin : rdes_reg_proc - if (rst) - begin - own <= 1'b0 ; - rfs <= 1'b1 ; - rls <= 1'b0 ; - rde <= 1'b0 ; - end - else - begin - if (lsm == LSM_FSTAT & dmaack & dmaeob) - begin - rfs <= 1'b1 ; - end - else if (lsm == LSM_STAT & dmaack & dmaeob) - begin - rfs <= 1'b0 ; - end - - if (lsm == LSM_FSTAT) - begin - rls <= 1'b1 ; - end - else - begin - rls <= 1'b0 ; - end - - if (lsm == LSM_FSTAT & !whole) - begin - rde <= 1'b1 ; - end - else if (lsm == LSM_IDLE) - begin - rde <= 1'b0 ; - end - - own <= own_c ; - end - end - - assign res_c = rf | ce | rde | cs | tl ; - - always @(posedge clk) - begin : adwrite_reg_proc - if (rst) - begin - adwrite <= 1'b0 ; - dbadc_r <= 1'b0 ; - end - else - begin - if (dmaack & dmaeob) - begin - adwrite <= 1'b1 ; - end - else - begin - adwrite <= 1'b0 ; - end - - dbadc_r <= rdbadc ; - end - end - - always @(posedge clk) - begin : dad_reg_proc - if (rst) - begin - dad <= {DATADEPTH{1'b1}} ; - end - else - begin - if (dbadc_r) - begin - dad <= rdbad ; - end - else if (adwrite & lsm == LSM_NXT & rch) - begin - dad <= dataimax_r[DATADEPTH - 1:0] ; - end - else if (adwrite) - begin - case (lsm_r) - LSM_DES3 : - begin - if (rer) - begin - dad <= rdbad ; - end - else - begin - dad <= dmaaddr + ({dsl, 2'b00}) ; - end - end - LSM_DES0, LSM_DES0P : - begin - if (own) - begin - dad <= dmaaddr ; - end - end - LSM_DES2 : - begin - dad <= dmaaddr ; - end - LSM_DES1 : - begin - dad <= dmaaddr ; - end - LSM_FSTAT : - begin - dad <= (lsm == LSM_IDLE) ? rdbad : dad; - end - default : - begin - dad <= dad ; - end - endcase - end - end - end - - always @(posedge clk) - begin : bad_reg_proc - if (rst) - begin - bad <= {DATADEPTH{1'b1}} ; - end - else - begin - if (adwrite) - begin - if (lsm_r == LSM_BUF1 | lsm_r == LSM_BUF2) - begin - bad <= dmaaddr ; - end - else - begin - bad <= dataimax_r[DATADEPTH - 1:0] ; - end - end - end - end - - always @(posedge clk) - begin : stataddr_reg_proc - if (rst) - begin - tstatad <= {DATADEPTH{1'b1}} ; - statad <= {DATADEPTH{1'b1}} ; - end - else - begin - if (lsm == LSM_DES1 & adwrite) - begin - statad <= tstatad ; - end - - if ((lsm == LSM_DES0 | lsm == LSM_DES0P) & dmaack & dmaeob) - begin - tstatad <= dad ; - end - end - end - - always @(fbcnt or icachere or ififore) - begin : fbcnt_proc - if (icachere) - begin - fbcnt_c <= {14{1'b0}} ; - end - else - begin - if (ififore) - begin - case (DATAWIDTH) - 8 : - begin - fbcnt_c <= fbcnt + 1 ; - end - 16 : - begin - fbcnt_c <= fbcnt + 2'b10 ; - end - default : - begin - fbcnt_c <= fbcnt + 3'b100 ; - end - endcase - end - else - begin - fbcnt_c <= fbcnt; - end - end - end - - always @(posedge clk) - begin : fbcnt_reg_proc - if(rst) - begin - fbcnt <= {14{1'b0}}; - end - else - begin - fbcnt <= fbcnt_c; - end - end - - always @(fbcnt or length or fifocne) - begin : whole_proc - if (fbcnt >= length & fifocne) - begin - whole <= 1'b1 ; - end - else - begin - whole <= 1'b0 ; - end - end - - assign ififore = (((lsm == LSM_BUF1 | lsm == LSM_BUF2) & dmaack) | - (lsm == LSM_FSTAT & !whole & - flmax != fzero_max[14:0] & !ififore_r) | - (lsm == LSM_FSTAT & !whole & - fifocne & !ififore_r)) ? 1'b1 : 1'b0 ; - - always @(posedge clk) - begin : ififore_reg_proc - if (rst) - begin - ififore_r <= 1'b0 ; - icachere <= 1'b0 ; - end - else - begin - ififore_r <= ififore ; - - if (lsm == LSM_FSTAT & dmaack & dmaeob) - begin - icachere <= 1'b1 ; - end - else - begin - icachere <= 1'b0 ; - end - end - end - - assign fifore = ififore ; - - assign cachere = icachere ; - - always @(posedge clk) - begin : rprog_reg_proc - if (rst) - begin - rprog_r <= 1'b0 ; - rcpoll_r <= 1'b0 ; - rcpoll_r2 <= 1'b0 ; - end - else - begin - rprog_r <= rprog ; - rcpoll_r <= rcpoll ; - if (lsm == LSM_IDLE) - begin - rcpoll_r2 <= rcpoll_r ; - end - end - end - - always @(posedge clk) - begin : stat_reg_drv - if (rst) - begin - des <= 1'b0 ; - fbuf <= 1'b0 ; - stat <= 1'b0 ; - rcomp <= 1'b0 ; - bufcomp <= 1'b0 ; - ru <= 1'b0 ; - end - else - begin - if (lsm == LSM_DES0 | - lsm == LSM_DES1 | - lsm == LSM_DES2 | - lsm == LSM_DES3 | - lsm == LSM_DES0P) - begin - des <= 1'b1 ; - end - else - begin - des <= 1'b0 ; - end - - if ((lsm == LSM_BUF1 | lsm == LSM_BUF2) & req) - begin - fbuf <= 1'b1 ; - end - else - begin - fbuf <= 1'b0 ; - end - - if (lsm == LSM_STAT | lsm == LSM_FSTAT) - begin - stat <= 1'b1 ; - end - else - begin - stat <= 1'b0 ; - end - - if (lsm == LSM_FSTAT & dmaack & dmaeob) - begin - rcomp <= 1'b1 ; - end - else if (rcompack) - begin - rcomp <= 1'b0 ; - end - - if (lsm == LSM_STAT & dmaack & dmaeob) - begin - bufcomp <= 1'b1 ; - end - else if (bufack) - begin - bufcomp <= 1'b0 ; - end - - if (own & !own_c) - begin - ru <= 1'b1 ; - end - else if (own) - begin - ru <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : stop_reg_proc - if (rst) - begin - stop_r <= 1'b1 ; - stopo <= 1'b1 ; - end - else - begin - stop_r <= stopi ; - - if (stop_r & (lsm == LSM_IDLE | - ((lsm == LSM_BUF1 | lsm == LSM_BUF2) & - !fifocne & !rprog_r))) - begin - stopo <= 1'b1 ; - end - else - begin - stopo <= 1'b0 ; - end - end - end - - assign dzero_max = {DATAWIDTH_MAX{1'b0}} ; - - assign fzero_max = {FIFODEPTH_MAX{1'b0}} ; - - assign dmadatai_max = {dzero_max[DATAWIDTH_MAX+1:DATAWIDTH], - dmadatai}; - - assign dmaaddr20 = dmaaddr[2:0] ; - - assign addr10 = dmaaddr[1:0] ; - -endmodule - - - -module RSTC_V ( - clkdma, - clkcsr, - clkt, - clkr, - rstcsr, - rstsoft, - rsttc, - rstrc, - rstdmao, - rstcsro - ); - - input clkdma; - input clkcsr; - input clkt; - input clkr; - - input rstcsr; - input rstsoft; - output rsttc; - reg rsttc; - output rstrc; - reg rstrc; - output rstdmao; - reg rstdmao; - output rstcsro; - reg rstcsro; - - - reg rstsoft_rc1; - reg rstsoft_rc2; - reg rstsoft_rc3; - reg rstsoft_tc1; - reg rstsoft_tc2; - reg rstsoft_tc3; - reg rstsoft_dma1; - reg rstsoft_dma2; - reg rstsoft_dma3; - reg rstsoft_csr; - reg rstsoft_dma_csr1; - reg rstsoft_dma_csr2; - reg rstsoft_rc_csr1; - reg rstsoft_rc_csr2; - reg rstsoft_tc_csr1; - reg rstsoft_tc_csr2; - reg rstcsr_r1; - reg rstcsr_r2; - reg rstcsr_tc1; - reg rstcsr_tc2; - reg rstcsr_rc1; - reg rstcsr_rc2; - reg rstcsr_dma1; - reg rstcsr_dma2; - - - always @(posedge clkcsr) - begin : rstsoft_csr_reg_proc - if (rstcsr_r2) - begin - rstsoft_csr <= 1'b0 ; - rstsoft_dma_csr1 <= 1'b0 ; - rstsoft_dma_csr2 <= 1'b0 ; - rstsoft_tc_csr1 <= 1'b0 ; - rstsoft_tc_csr2 <= 1'b0 ; - rstsoft_rc_csr1 <= 1'b0 ; - rstsoft_rc_csr2 <= 1'b0 ; - end - else - begin - if (rstsoft) - begin - rstsoft_csr <= 1'b1 ; - end - else if (rstsoft_rc_csr2 & rstsoft_tc_csr2 & rstsoft_dma_csr2) - begin - rstsoft_csr <= 1'b0 ; - end - rstsoft_dma_csr1 <= rstsoft_dma3; - rstsoft_dma_csr2 <= rstsoft_dma_csr1; - rstsoft_tc_csr1 <= rstsoft_tc3; - rstsoft_tc_csr2 <= rstsoft_tc_csr1; - rstsoft_rc_csr1 <= rstsoft_rc3; - rstsoft_rc_csr2 <= rstsoft_rc_csr1; - end - end - - always @(posedge clkcsr) - begin : rstcsro_reg_proc - rstcsr_r1 <= rstcsr; - rstcsr_r2 <= rstcsr_r1; - rstcsro <= rstcsr_r2 | rstsoft_csr; - end - - always @(posedge clkr) - begin : rstrc_reg_proc - rstcsr_rc1 <= rstcsr; - rstcsr_rc2 <= rstcsr_rc1; - rstsoft_rc1 <= rstsoft_csr; - rstsoft_rc2 <= rstsoft_rc1; - rstsoft_rc3 <= rstsoft_rc2; - rstrc <= rstcsr_rc2 | rstsoft_rc2; - end - - always @(posedge clkt) - begin : rsttc_proc - rstcsr_tc1 <= rstcsr; - rstcsr_tc2 <= rstcsr_tc1; - rstsoft_tc1 <= rstsoft_csr; - rstsoft_tc2 <= rstsoft_tc1; - rstsoft_tc3 <= rstsoft_tc2; - rsttc <= rstcsr_tc2 | rstsoft_tc2; - end - - always @(posedge clkdma) - begin : rstdma_reg_proc - rstcsr_dma1 <= rstcsr; - rstcsr_dma2 <= rstcsr_dma1; - rstsoft_dma1 <= rstsoft_csr; - rstsoft_dma2 <= rstsoft_dma1; - rstsoft_dma3 <= rstsoft_dma2; - rstdmao <= rstcsr_dma2 | rstsoft_dma2; - end - -endmodule - -module TC_V ( - clk, - rst, - txen, - txer, - txd, - ramdata, - ramaddr, - wadg, - radg, - dpd, - ac, - sofreq, - eofreq, - tiack, - lastbe, - eofadg, - tireq, - ur, - de, - coll, - carrier, - bkoff, - tpend, - tprog, - preamble, - stopi, - stopo, - tcsack, - tcsreq - ); - - parameter FIFODEPTH = 9; - parameter DATAWIDTH = 32; - - `include "utility.v" - - input clk; - input rst; - - output txen; - reg txen; - output txer; - wire txer; - output [MIIWIDTH - 1:0] txd; - reg [MIIWIDTH - 1:0] txd; - - input [DATAWIDTH - 1:0] ramdata; - output [FIFODEPTH - 1:0] ramaddr; - wire [FIFODEPTH - 1:0] ramaddr; - - input [FIFODEPTH - 1:0] wadg; - output [FIFODEPTH - 1:0] radg; - wire [FIFODEPTH - 1:0] radg; - - input dpd; - input ac; - input sofreq; - input eofreq; - input tiack; - input [DATAWIDTH / 8 - 1:0] lastbe; - input [FIFODEPTH - 1:0] eofadg; - output tireq; - reg tireq; - output ur; - wire ur; - output de; - reg de; - - input coll; - input carrier; - input bkoff; - output tpend; - wire tpend; - output tprog; - reg tprog; - output preamble; - reg preamble; - - input stopi; - output stopo; - reg stopo; - - input tcsack; - output tcsreq; - reg tcsreq; - - - reg re_c; - reg re; - reg empty_c; - reg empty; - reg [FIFODEPTH - 1:0] rad_r; - reg [FIFODEPTH - 1:0] rad; - reg [FIFODEPTH - 1:0] iradg; - reg [FIFODEPTH - 1:0] wadg_0_r; - reg [FIFODEPTH - 1:0] iwadg; - reg [FIFODEPTH - 1:0] iwad_c; - reg [FIFODEPTH - 1:0] iwad; - reg [FIFODEPTH - 1:0] sofad; - reg [FIFODEPTH - 1:0] eofadg_r; - reg sofreq_r; - reg eofreq_r; - reg whole; - reg eof; - reg [DATAWIDTH - 1:0] ramdata_r; - - reg [MIIWIDTH - 1:0] itxd0; - reg [DATAWIDTH - 1:0] pmux; - reg [DATAWIDTH - 1:0] datamux_c; - wire [DATAWIDTH_MAX + 1:0] datamux_c_max; - reg txen1; - reg txen_rise; - reg [MIIWIDTH - 1:0] txd_rise; - - reg [3:0] tsm_c; - reg [3:0] tsm; - reg nset; - reg [3:0] ncnt; - wire [1:0] ncnt10; - wire [2:0] ncnt20; - reg [6:0] brel; - reg bset; - reg [6:0] bcnt; - reg bz; - reg nopad; - reg crcgen; - reg crcsend; - reg [31:0] crc_c; - reg [31:0] crc; - reg [31:0] crcneg_c; - reg itprog; - reg itpend; - reg iur; - reg iti; - reg tiack_r; - reg [3:0] ifscnt; - - reg tcsack_r; - reg [7:0] tcscnt; - reg tcs; - - reg ifs1p; - reg ifs2p; - wire defer; - - reg bkoff_r; - - reg stop_r; - wire [3:0] hnibble; - wire [MIIWIDTH_MAX + 1:0] itxd0_max; - wire [MIIWIDTH_MAX + 1:0] itxd0zero_max; - wire [DATAWIDTH_MAX + 1:0] dzero_max; - - always @(posedge clk) - begin : faddr_reg_proc - if (rst) - begin - rad <= {FIFODEPTH{1'b0}} ; - rad_r <= {FIFODEPTH{1'b0}} ; - iradg <= {FIFODEPTH{1'b0}} ; - sofad <= {FIFODEPTH{1'b0}} ; - eofadg_r <= {FIFODEPTH{1'b0}} ; - iwad <= {FIFODEPTH{1'b0}} ; - wadg_0_r <= {FIFODEPTH{1'b0}} ; - iwadg <= {FIFODEPTH{1'b0}} ; - end - else - begin - if (bkoff_r) - begin - rad <= sofad ; - end - else if (re_c) - begin - rad <= rad + 1 ; - end - else if (eof & tsm == TSM_FLUSH) - begin - rad <= iwad ; - end - - rad_r <= rad ; - - iradg <= rad ^ {1'b0, rad[FIFODEPTH - 1:1]} ; - - if (tsm == TSM_IDLE_TCSMT) - begin - sofad <= rad_r ; - end - - eofadg_r <= eofadg ; - - iwad <= iwad_c ; - - wadg_0_r <= wadg; - if (eofreq_r) - begin - iwadg <= eofadg_r ; - end - else - begin - iwadg <= wadg_0_r ; - end - end - end - - always @(iwadg) - begin : iwad_proc - reg[FIFODEPTH - 1:0] wad_v; - wad_v[FIFODEPTH - 1] = iwadg[FIFODEPTH - 1]; - begin : iwad_loop - integer i; - for(i = FIFODEPTH - 2; i >= 0; i = i - 1) - begin - wad_v[i] = wad_v[i + 1] ^ iwadg[i]; - end - end - iwad_c = wad_v ; - end - - always @(rad or iwad) - begin : empty_proc - if (rad == iwad) - begin - empty_c <= 1'b1 ; - end - else - begin - empty_c <= 1'b0 ; - end - end - - always @(posedge clk) - begin : empty_reg_proc - if (rst) - begin - empty <= 1'b1 ; - end - else - begin - empty <= empty_c ; - end - end - - always @(tsm or empty_c or ncnt) - begin : re_proc - if ((tsm == TSM_INFO | - tsm == TSM_SFD | - tsm == TSM_FLUSH) & !empty_c & - ((DATAWIDTH == 8 & !(ncnt[0])) | - (DATAWIDTH == 16 & ncnt[1:0] == 2'b10) | - (DATAWIDTH == 32 & ncnt[2:0] == 3'b110))) - begin - re_c <= 1'b1 ; - end - else - begin - re_c <= 1'b0 ; - end - end - - always @(posedge clk) - begin : re_reg_proc - if (rst) - begin - re <= 1'b0 ; - end - else - begin - re <= re_c ; - end - end - - assign ramaddr = rad ; - - assign radg = iradg ; - - always @(posedge clk) - begin : whole_reg_proc - if (rst) - begin - whole <= 1'b0 ; - end - else - begin - if (iti) - begin - whole <= 1'b0 ; - end - else if (eofreq_r) - begin - whole <= 1'b1 ; - end - end - end - - always @(posedge clk) - begin : se_reg_proc - if (rst) - begin - sofreq_r <= 1'b0 ; - eofreq_r <= 1'b0 ; - end - else - begin - sofreq_r <= sofreq ; - eofreq_r <= eofreq ; - end - end - - always @(tsm or - itpend or - bkoff_r or - defer or bz or - ncnt or dpd or - iur or - hnibble or - ac or - empty or - whole or - tiack_r or - nopad or - coll or - eof) - begin : tsm_proc - case (tsm) - TSM_IDLE_TCSMT : - begin - if (itpend & !bkoff_r & !defer) - begin - tsm_c <= TSM_PREA ; - end - else - begin - tsm_c <= TSM_IDLE_TCSMT ; - end - end - TSM_PREA : - begin - if (bz & (ncnt[0])) - begin - tsm_c <= TSM_SFD ; - end - else - begin - tsm_c <= TSM_PREA ; - end - end - TSM_SFD : - begin - if (bz & (ncnt[0])) - begin - tsm_c <= TSM_INFO ; - end - else - begin - tsm_c <= TSM_SFD ; - end - end - TSM_INFO : - begin - if (coll) - begin - tsm_c <= TSM_JAM ; - end - else if (empty) - begin - if (!whole & ncnt == hnibble) - begin - tsm_c <= TSM_JAM ; - end - else if (eof & (nopad | dpd)) - begin - if (ac) - begin - tsm_c <= TSM_INT ; - end - else - begin - tsm_c <= TSM_CRC ; - end - end - else if (eof) - begin - tsm_c <= TSM_PAD ; - end - else - begin - tsm_c <= TSM_INFO ; - end - end - else - begin - tsm_c <= TSM_INFO ; - end - end - TSM_PAD : - begin - if (coll) - begin - tsm_c <= TSM_JAM ; - end - else if (nopad & (ncnt[0])) - begin - tsm_c <= TSM_CRC ; - end - else - begin - tsm_c <= TSM_PAD ; - end - end - TSM_CRC : - begin - if (coll) - begin - tsm_c <= TSM_JAM ; - end - else if (bz & (ncnt[0])) - begin - tsm_c <= TSM_INT ; - end - else - begin - tsm_c <= TSM_CRC ; - end - end - TSM_JAM : - begin - if (bz & (ncnt[0])) - begin - if (!bkoff_r | iur) - begin - tsm_c <= TSM_FLUSH ; - end - else - begin - tsm_c <= TSM_IDLE_TCSMT ; - end - end - else - begin - tsm_c <= TSM_JAM ; - end - end - TSM_FLUSH : - begin - if (whole & empty) - begin - tsm_c <= TSM_INT ; - end - else - begin - tsm_c <= TSM_FLUSH ; - end - end - default : - begin - if (tiack_r) - begin - tsm_c <= TSM_IDLE_TCSMT ; - end - else - begin - tsm_c <= TSM_INT ; - end - end - endcase - end - - always @(posedge clk) - begin : tsm_reg_proc - if (rst) - begin - tsm <= TSM_IDLE_TCSMT ; - end - else - begin - tsm <= tsm_c ; - end - end - - assign defer = ifs1p | ifs2p ; - - always @(posedge clk) - begin : ifs_reg_proc - if (rst) - begin - ifs1p <= 1'b0 ; - ifs2p <= 1'b0 ; - ifscnt <= IFS1_TIME ; - end - else - begin - if (!itprog & !ifs1p & !ifs2p & ifscnt != 4'b0000) - begin - ifs1p <= 1'b1 ; - end - else if (ifscnt == 4'b0000 | ifs2p) - begin - ifs1p <= 1'b0 ; - end - - if (ifs1p & ifscnt == 4'b0000) - begin - ifs2p <= 1'b1 ; - end - else if (ifs2p & ifscnt == 4'b0000) - begin - ifs2p <= 1'b0 ; - end - - if (itprog | - (carrier & ifs1p) | - (carrier & ifscnt == 4'b0000 & !itpend) | - (carrier & ifscnt == 4'b0000 & bkoff_r)) - begin - ifscnt <= IFS1_TIME ; - end - else if (ifs1p & ifscnt == 4'b0000) - begin - ifscnt <= IFS2_TIME ; - end - else if (ifscnt != 4'b0000) - begin - ifscnt <= ifscnt - 1 ; - end - end - end - - always @(posedge clk) - begin : de_reg_proc - if (rst) - begin - de <= 1'b0 ; - end - else - begin - if (ifs1p & itpend & carrier & tsm == TSM_IDLE_TCSMT) - begin - de <= 1'b1 ; - end - else if (tiack_r) - begin - de <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : eof_reg_proc - if (rst) - begin - eof <= 1'b0 ; - end - else - begin - case (DATAWIDTH) - 8 : - begin - if (whole & !(ncnt[0])) - begin - eof <= 1'b1 ; - end - else - begin - eof <= 1'b0 ; - end - end - 16 : - begin - if (whole & ((lastbe == 2'b11 & ncnt[1:0] == 2'b10) | - (lastbe == 2'b01 & ncnt[1:0] == 2'b00))) - begin - eof <= 1'b1 ; - end - else - begin - eof <= 1'b0 ; - end - end - default : - begin - if (whole & ((lastbe == 4'b1111 & ncnt[2:0] == 3'b110) | - (lastbe == 4'b0111 & ncnt[2:0] == 3'b100) | - (lastbe == 4'b0011 & ncnt[2:0] == 3'b010) | - (lastbe == 4'b0001 & ncnt[2:0] == 3'b000))) - begin - eof <= 1'b1 ; - end - else - begin - eof <= 1'b0 ; - end - end - endcase - end - end - - always @(coll or tsm or ncnt or bz or empty or eof or nopad) - begin : bset_reg_proc - if ((coll & (tsm == TSM_INFO | - tsm == TSM_PAD | - tsm == TSM_CRC)) | - (tsm == TSM_PAD & nopad & !(ncnt[0])) | - (tsm == TSM_PREA & bz & !(ncnt[0])) | - (tsm == TSM_SFD & (ncnt[0])) | - (tsm == TSM_INFO & empty & eof & nopad) | - (tsm == TSM_IDLE_TCSMT)) - begin - bset <= 1'b1 ; - end - else - begin - bset <= 1'b0 ; - end - end - - always @(posedge clk) - begin : bcnt_reg_proc - if (rst) - begin - bcnt <= {7{1'b1}} ; - brel <= 7'b0000110 ; - bz <= 1'b0 ; - end - else - begin - if (bset) - begin - if(coll & tsm==TSM_INFO) - begin - bcnt <= 7'b0000011; - end - else - begin - bcnt <= brel ; - end - end - else if ((ncnt[0]) & !bz) - begin - bcnt <= bcnt - 1 ; - end - - case (tsm) - TSM_IDLE_TCSMT : - begin - brel <= 7'b0000110 ; - end - TSM_PREA : - begin - brel <= 7'b0000000 ; - end - TSM_SFD : - begin - if (coll) - begin - brel <= 7'b0000011 ; - end - else - begin - brel <= MIN_FRAME - 1 ; - end - end - default : - begin - brel <= 7'b0000011 ; - end - endcase - - if (bset & brel != 7'b0000000) - begin - bz <= 1'b0 ; - end - else if (bcnt == 7'b0000001 & (ncnt[0]) & !bz) - begin - bz <= 1'b1 ; - end - end - end - - always @(posedge clk) - begin : nopad_reg_proc - if (rst) - begin - nopad <= 1'b0 ; - end - else - begin - if ((tsm == TSM_INFO & bcnt == 7'b0000100 & !ac) | - (tsm == TSM_INFO & bcnt == 7'b0000001 & ac) | - (tsm == TSM_PAD & bcnt == 7'b0000100) | (dpd & !ac)) - begin - nopad <= 1'b1 ; - end - else if (tsm == TSM_IDLE_TCSMT) - begin - nopad <= 1'b0 ; - end - end - end - - always @(tsm or - itpend or - bkoff_r or - defer or - ncnt or - eof or - empty or - nopad) - begin : nset_proc - if ((tsm == TSM_IDLE_TCSMT & ~(itpend & !bkoff_r & !defer)) | - (tsm == TSM_INFO & empty & eof) | - (tsm == TSM_PAD & nopad & (ncnt[0]))) - begin - nset <= 1'b1 ; - end - else - begin - nset <= 1'b0 ; - end - end - - always @(posedge clk) - begin : ncnt_reg_proc - if (rst) - begin - ncnt <= {4{1'b0}} ; - end - else - begin - if (nset) - begin - ncnt <= {4{1'b0}} ; - end - else if (tsm != TSM_IDLE_TCSMT) - begin - ncnt <= ncnt + 1 ; - end - end - end - - always @(tsm or crc or itxd0_max or crcgen) - begin : crc_proc - if (tsm == TSM_PREA) - begin - crc_c <= {32{1'b1}} ; - end - else if (crcgen) - begin - crc_c[0] <= crc[28] ^ - itxd0_max[3] ; - crc_c[1] <= crc[28] ^ crc[29] ^ - itxd0_max[2] ^ itxd0_max[3] ; - crc_c[2] <= crc[28] ^ crc[29] ^ crc[30] ^ - itxd0_max[1] ^ itxd0_max[2] ^ itxd0_max[3] ; - crc_c[3] <= crc[29] ^ crc[30] ^ crc[31] ^ - itxd0_max[0] ^ itxd0_max[1] ^ itxd0_max[2] ; - crc_c[4] <= crc[0] ^ crc[28] ^ crc[30] ^ crc[31] ^ - itxd0_max[0] ^ itxd0_max[1] ^ itxd0_max[3] ; - crc_c[5] <= crc[1] ^ crc[28] ^ crc[29] ^ crc[31] ^ - itxd0_max[0] ^ itxd0_max[2] ^ itxd0_max[3] ; - crc_c[6] <= crc[2] ^ crc[29] ^ crc[30] ^ - itxd0_max[1] ^ itxd0_max[2] ; - crc_c[7] <= crc[3] ^ crc[28] ^ crc[30] ^ crc[31] ^ - itxd0_max[0] ^ itxd0_max[1] ^ itxd0_max[3] ; - crc_c[8] <= crc[4] ^ crc[28] ^ crc[29] ^ crc[31] ^ - itxd0_max[0] ^ itxd0_max[2] ^ itxd0_max[3] ; - crc_c[9] <= crc[5] ^ crc[29] ^ crc[30] ^ - itxd0_max[1] ^ itxd0_max[2] ; - crc_c[10] <= crc[6] ^ crc[28] ^ crc[30] ^ crc[31] ^ - itxd0_max[0] ^ itxd0_max[1] ^ itxd0_max[3] ; - crc_c[11] <= crc[7] ^ crc[28] ^ crc[29] ^ crc[31] ^ - itxd0_max[0] ^ itxd0_max[2] ^ itxd0_max[3] ; - crc_c[12] <= crc[8] ^ crc[28] ^ crc[29] ^ crc[30] ^ - itxd0_max[1] ^ itxd0_max[2] ^ itxd0_max[3] ; - crc_c[13] <= crc[9] ^ crc[29] ^ crc[30] ^ crc[31] ^ - itxd0_max[0] ^ itxd0_max[1] ^ itxd0_max[2] ; - crc_c[14] <= crc[10] ^ crc[30] ^ crc[31] ^ - itxd0_max[0] ^ itxd0_max[1] ; - crc_c[15] <= crc[11] ^ crc[31] ^ - itxd0_max[0] ; - crc_c[16] <= crc[12] ^ crc[28] ^ - itxd0_max[3] ; - crc_c[17] <= crc[13] ^ crc[29] ^ - itxd0_max[2] ; - crc_c[18] <= crc[14] ^ crc[30] ^ - itxd0_max[1] ; - crc_c[19] <= crc[15] ^ crc[31] ^ - itxd0_max[0] ; - crc_c[20] <= crc[16] ; - crc_c[21] <= crc[17] ; - crc_c[22] <= crc[18] ^ crc[28] ^ - itxd0_max[3] ; - crc_c[23] <= crc[19] ^ crc[28] ^ crc[29] ^ - itxd0_max[2] ^ itxd0_max[3] ; - crc_c[24] <= crc[20] ^ crc[29] ^ crc[30] ^ - itxd0_max[1] ^ itxd0_max[2] ; - crc_c[25] <= crc[21] ^ crc[30] ^ crc[31] ^ - itxd0_max[0] ^ itxd0_max[1] ; - crc_c[26] <= crc[22] ^ crc[28] ^ crc[31] ^ - itxd0_max[0] ^ itxd0_max[3] ; - crc_c[27] <= crc[23] ^ crc[29] ^ - itxd0_max[2] ; - crc_c[28] <= crc[24] ^ crc[30] ^ - itxd0_max[1] ; - crc_c[29] <= crc[25] ^ crc[31] ^ - itxd0_max[0] ; - crc_c[30] <= crc[26] ; - crc_c[31] <= crc[27] ; - end - else - begin - crc_c <= crc ; - end - end - - always @(posedge clk) - begin : crc_reg_proc - if (rst) - begin - crcgen <= 1'b0 ; - crcsend <= 1'b0 ; - crc <= {32{1'b1}} ; - end - else - begin - crc <= crc_c ; - - if (tsm == TSM_INFO | tsm == TSM_PAD) - begin - crcgen <= 1'b1 ; - end - else - begin - crcgen <= 1'b0 ; - end - - if (tsm == TSM_CRC) - begin - crcsend <= 1'b1 ; - end - else - begin - crcsend <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : tstate_reg_proc - if (rst) - begin - itprog <= 1'b0 ; - itpend <= 1'b0 ; - tprog <= 1'b0 ; - preamble <= 1'b0 ; - end - else - begin - if (tsm == TSM_INFO | tsm == TSM_PAD | tsm == TSM_CRC | - tsm == TSM_JAM) - begin - itprog <= 1'b1 ; - end - else - begin - itprog <= 1'b0 ; - end - - if (sofreq_r) - begin - itpend <= 1'b1 ; - end - else - begin - itpend <= 1'b0 ; - end - - if (tsm == TSM_PREA | - tsm == TSM_SFD | - tsm == TSM_INFO | - tsm == TSM_PAD | - tsm == TSM_CRC | - tsm == TSM_JAM) - begin - tprog <= 1'b1 ; - end - else - begin - tprog <= 1'b0 ; - end - - if (tsm == TSM_PREA | tsm == TSM_SFD) - begin - preamble <= 1'b1 ; - end - else - begin - preamble <= 1'b0 ; - end - end - end - - assign tpend = itpend ; - - always @(posedge clk) - begin : iti_reg_proc - if (rst) - begin - iti <= 1'b0 ; - tireq <= 1'b0 ; - tiack_r <= 1'b0 ; - end - else - begin - if (tsm == TSM_INT) - begin - iti <= 1'b1 ; - end - else if (tiack) - begin - iti <= 1'b0 ; - end - - tireq <= iti ; - tiack_r <= tiack ; - end - end - - always @(posedge clk) - begin : iur_reg_proc - if (rst) - begin - iur <= 1'b0 ; - end - else - begin - if (itprog & empty & !whole) - begin - iur <= 1'b1 ; - end - else if (tiack_r) - begin - iur <= 1'b0 ; - end - end - end - - assign ur = iur ; - - always @(tsm or ramdata_r or pmux) - begin : datamux_proc - if (tsm == TSM_INFO) - begin - datamux_c <= ramdata_r ; - end - else - begin - datamux_c <= pmux ; - end - end - - assign ncnt10 = ncnt[1:0] ; - - assign ncnt20 = ncnt[2:0] ; - - assign datamux_c_max = {dzero_max[DATAWIDTH_MAX + 1:DATAWIDTH], - datamux_c}; - - always @(crc) - begin : crcneg_proc - begin : crcneg_loop - integer i; - for(i = 31; i >= 0; i = i - 1) - begin - crcneg_c[i] <= ~crc[31 - i] ; - end - end - end - - always @(posedge clk) - begin : txd_proc - if (rst) - begin - txd_rise <= {MIIWIDTH{1'b1}} ; - pmux <= {DATAWIDTH{1'b1}} ; - itxd0 <= {MIIWIDTH{1'b1}} ; - ramdata_r <= {DATAWIDTH{1'b0}} ; - end - else - begin - case (tsm_c) - TSM_PAD : - begin - pmux <= PAD_PATTERN[63:64 - DATAWIDTH] ; - end - TSM_JAM : - begin - pmux <= JAM_PATTERN[63:64 - DATAWIDTH] ; - end - TSM_PREA : - begin - pmux <= PRE_PATTERN[63:64 - DATAWIDTH] ; - end - TSM_SFD : - begin - pmux <= SFD_PATTERN[63:64 - DATAWIDTH] ; - end - default : - begin - pmux <= {DATAWIDTH{1'b1}} ; - end - endcase - - case (DATAWIDTH) - 32 : - begin - case (ncnt20) - 3'b000 : - begin - itxd0 <= datamux_c_max[3:0] ; - end - 3'b001 : - begin - itxd0 <= datamux_c_max[7:4] ; - end - 3'b010 : - begin - itxd0 <= datamux_c_max[11:8] ; - end - 3'b011 : - begin - itxd0 <= datamux_c_max[15:12] ; - end - 3'b100 : - begin - itxd0 <= datamux_c_max[19:16] ; - end - 3'b101 : - begin - itxd0 <= datamux_c_max[23:20] ; - end - 3'b110 : - begin - itxd0 <= datamux_c_max[27:24] ; - end - default : - begin - itxd0 <= datamux_c_max[31:28] ; - end - endcase - end - 16 : - begin - case (ncnt10) - 2'b00 : - begin - itxd0 <= datamux_c_max[3:0] ; - end - 2'b01 : - begin - itxd0 <= datamux_c_max[7:4] ; - end - 2'b10 : - begin - itxd0 <= datamux_c_max[11:8] ; - end - default : - begin - itxd0 <= datamux_c_max[15:12] ; - end - endcase - end - default : - begin - if (!(ncnt[0])) - begin - itxd0 <= datamux_c_max[3:0] ; - end - else - begin - itxd0 <= datamux_c_max[7:4] ; - end - end - endcase - - if (re) - begin - ramdata_r <= ramdata ; - end - - if (crcsend) - begin - case (ncnt) - 4'b0001 : - begin - txd_rise <= crcneg_c[3:0] ; - end - 4'b0010 : - begin - txd_rise <= crcneg_c[7:4] ; - end - 4'b0011 : - begin - txd_rise <= crcneg_c[11:8] ; - end - 4'b0100 : - begin - txd_rise <= crcneg_c[15:12] ; - end - 4'b0101 : - begin - txd_rise <= crcneg_c[19:16] ; - end - 4'b0110 : - begin - txd_rise <= crcneg_c[23:20] ; - end - 4'b0111 : - begin - txd_rise <= crcneg_c[27:24] ; - end - default : - begin - txd_rise <= crcneg_c[31:28] ; - end - endcase - end - else - begin - txd_rise <= itxd0 ; - end - end - end - - always @(posedge clk) - begin : txen_reg_proc - if (rst) - begin - txen1 <= 1'b0 ; - txen_rise <= 1'b0 ; - end - else - begin - txen_rise <= txen1 ; - if (tsm == TSM_IDLE_TCSMT | - tsm == TSM_INT | - tsm == TSM_FLUSH) - begin - txen1 <= 1'b0 ; - end - else - begin - txen1 <= 1'b1 ; - end - end - end - - always @(posedge clk) - begin : mii_fall_reg_proc - txen <= txen_rise ; - txd <= txd_rise; - end - - assign txer = 1'b0 ; - - always @(posedge clk) - begin : bkoff_reg_proc - if (rst) - begin - bkoff_r <= 1'b0 ; - end - else - begin - if (bkoff) - begin - bkoff_r <= 1'b1 ; - end - else if (tsm != TSM_JAM) - begin - bkoff_r <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : stopo_reg_proc - if (rst) - begin - stop_r <= 1'b0 ; - stopo <= 1'b0 ; - end - else - begin - stop_r <= stopi; - - if (stop_r & tsm == TSM_IDLE_TCSMT & !itpend) - begin - stopo <= 1'b1 ; - end - else - begin - stopo <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : cscnt_reg_proc - if (rst) - begin - tcscnt <= {8{1'b0}} ; - tcs <= 1'b0 ; - tcsreq <= 1'b0 ; - tcsack_r <= 1'b0 ; - end - else - begin - if (tcscnt == 8'b00000000) - begin - tcscnt <= 8'b10000000 ; - end - else - begin - tcscnt <= tcscnt - 1 ; - end - - if (tcscnt == 8'b00000000) - begin - tcs <= 1'b1 ; - end - else if (tcsack_r) - begin - tcs <= 1'b0 ; - end - - if (tcs & !tcsack_r) - begin - tcsreq <= 1'b1 ; - end - else if (tcsack_r) - begin - tcsreq <= 1'b0 ; - end - - tcsack_r <= tcsack ; - - end - end - - assign hnibble = (DATAWIDTH == 32) ? 4'b0111 : - (DATAWIDTH == 16) ? 4'b0011 : - 4'b0001 ; - - assign itxd0zero_max = {(MIIWIDTH_MAX + 1){1'b0}} ; - - assign itxd0_max = {itxd0zero_max[MIIWIDTH_MAX + 1:MIIWIDTH], - itxd0}; - - assign dzero_max = {(DATAWIDTH_MAX + 1){1'b0}} ; - -endmodule - - - -module TFIFO_V ( - clk, - rst, - ramwe, - ramaddr, - ramdata, - fifowe, - fifoeof, - fifobe, - fifodata, - fifonf, - fifocnf, - fifoval, - flev, - ici, - dpdi, - aci, - statadi, - cachere, - deo, - lco, - loo, - nco, - eco, - csne, - ico, - uro, - cco, - statado, - sofreq, - eofreq, - dpdo, - aco, - beo, - eofad, - wadg, - tireq, - winp, - dei, - lci, - loi, - nci, - eci, - uri, - cci, - radg, - tiack, - sf, - fdp, - tm, - pbl, - etiack, - etireq, - stopi, - stopo - ); - - parameter DATAWIDTH = 32; - parameter DATADEPTH = 32; - parameter FIFODEPTH = 9; - parameter CACHEDEPTH = 1; - - `include "utility.v" - - input clk; - input rst; - - output ramwe; - wire ramwe; - output [FIFODEPTH - 1:0] ramaddr; - wire [FIFODEPTH - 1:0] ramaddr; - output [DATAWIDTH - 1:0] ramdata; - wire [DATAWIDTH - 1:0] ramdata; - - input fifowe; - input fifoeof; - input [DATAWIDTH / 8 - 1:0] fifobe; - input [DATAWIDTH - 1:0] fifodata; - output fifonf; - reg fifonf; - output fifocnf; - wire fifocnf; - output fifoval; - reg fifoval; - output [FIFODEPTH - 1:0] flev; - wire [FIFODEPTH - 1:0] flev; - - input ici; - input dpdi; - input aci; - input [DATADEPTH - 1:0] statadi; - - input cachere; - output deo; - wire deo; - output lco; - wire lco; - output loo; - wire loo; - output nco; - wire nco; - output eco; - wire eco; - output csne; - wire csne; - output ico; - wire ico; - output uro; - wire uro; - output [3:0] cco; - wire [3:0] cco; - output [DATADEPTH - 1:0] statado; - wire [DATADEPTH - 1:0] statado; - - output sofreq; - wire sofreq; - output eofreq; - reg eofreq; - output dpdo; - wire dpdo; - output aco; - wire aco; - output [DATAWIDTH / 8 - 1:0] beo; - wire [DATAWIDTH / 8 - 1:0] beo; - output [FIFODEPTH - 1:0] eofad; - reg [FIFODEPTH - 1:0] eofad; - output [FIFODEPTH - 1:0] wadg; - reg [FIFODEPTH - 1:0] wadg; - - input tireq; - input winp; - input dei; - input lci; - input loi; - input nci; - input eci; - input uri; - input [3:0] cci; - input [FIFODEPTH - 1:0] radg; - output tiack; - wire tiack; - - input sf; - input fdp; - input [2:0] tm; - input [5:0] pbl; - - input etiack; - output etireq; - reg etireq; - - input stopi; - output stopo; - reg stopo; - - - parameter CCWIDTH = (3 + DATADEPTH + DATAWIDTH / 8 + FIFODEPTH); - reg [CCWIDTH - 1:0] ccmem[(1'b1 << CACHEDEPTH) - 1:0]; - wire ccwe; - wire ccre; - reg ccne; - reg iccnf; - wire [CACHEDEPTH - 1:0] ccwad_c; - reg [CACHEDEPTH - 1:0] ccwad; - reg [CACHEDEPTH - 1:0] ccrad; - reg [CACHEDEPTH - 1:0] ccrad_r; - wire [CCWIDTH - 1:0] ccdi; - wire [CCWIDTH - 1:0] ccdo; - - parameter CSWIDTH = (DATADEPTH + 11); - reg [CSWIDTH - 1:0] csmem[(1'b1 << CACHEDEPTH) - 1:0]; - wire cswe; - reg csre; - reg [CACHEDEPTH - 1:0] cswad; - wire [CACHEDEPTH - 1:0] csrad_c; - reg [CACHEDEPTH - 1:0] csrad; - reg [CACHEDEPTH - 1:0] csrad_r; - wire [CSWIDTH - 1:0] csdi; - wire [CSWIDTH - 1:0] csdo; - wire [DATADEPTH - 1:0] statad; - wire ic; - reg icsne; - - reg tprog; - reg tprog_r; - - reg winp_r; - reg [FIFODEPTH_MAX - 1:0] tlev_c; - reg tresh; - reg [FIFODEPTH - 1:0] stat; - reg [FIFODEPTH - 1:0] wad; - reg [FIFODEPTH - 1:0] rad_c; - reg [FIFODEPTH - 1:0] rad; - reg [FIFODEPTH - 1:0] radg_0_r; - reg [FIFODEPTH - 1:0] radg_r; - reg [FIFODEPTH - 1:0] sad; - wire [FIFODEPTH - 1:0] eofad_bin; - reg pblz; - reg [FIFODEPTH_MAX - 1:0] sflev_c; - - reg tireq_r; - reg tireq_r2; - - reg stop_r; - - wire [FIFODEPTH - 1:0] fone; - wire [FIFODEPTH - 1:0] fzero; - - always @(posedge clk) - begin : ccmem_reg_proc - if (rst) - begin : ccmem_reset - integer i; - for(i = ((1'b1 << CACHEDEPTH) - 1); i >= 0; i = i - 1) - begin - ccmem[i] <= {CCWIDTH{1'b0}}; - end - ccrad_r <= {CACHEDEPTH{1'b0}} ; - end - else - begin - if (fifowe | fifoeof) - begin - ccmem[ccwad] <= ccdi ; - end - ccrad_r <= ccrad ; - end - end - - assign ccwad_c = (fifoeof) ? ccwad + 1 : ccwad ; - - always @(posedge clk) - begin : ccaddr_reg_proc - if (rst) - begin - ccwad <= {CACHEDEPTH{1'b0}} ; - ccrad <= {CACHEDEPTH{1'b0}} ; - end - else - begin - ccwad <= ccwad_c ; - - if (ccre) - begin - ccrad <= ccrad + 1 ; - end - end - end - - always @(posedge clk) - begin : ccfe_reg_proc - if (rst) - begin - iccnf <= 1'b1 ; - ccne <= 1'b0 ; - end - else - begin - if ((ccwad_c == ccrad) & ccwe) - begin - iccnf <= 1'b0 ; - end - else if (ccre) - begin - iccnf <= 1'b1 ; - end - - if (ccwad == ccrad & iccnf) - begin - ccne <= 1'b0 ; - end - else - begin - ccne <= 1'b1 ; - end - end - end - - assign fifocnf = iccnf ; - - assign ccdo = ccmem[ccrad_r] ; - - assign ccdi = {ici, aci, dpdi, wad, fifobe, statadi} ; - - assign ccwe = fifoeof ; - - assign ccre = tireq_r & ~tireq_r2 ; - - assign ic = ccdo[CCWIDTH - 1] ; - - assign aco = ccdo[CCWIDTH - 2] ; - - assign dpdo = ccdo[CCWIDTH - 3] ; - - assign eofad_bin = ccdo[CCWIDTH - 4:CCWIDTH - 3 - FIFODEPTH] ; - - always @(posedge clk) - begin : eofad_reg_proc - if (rst) - begin - eofad <= {FIFODEPTH{1'b0}} ; - end - else - begin - eofad[FIFODEPTH - 1] <= eofad_bin[FIFODEPTH - 1] ; - begin : eofad_loop - integer i; - for(i = FIFODEPTH - 2; i >= 0; i = i - 1) - begin - eofad[i] <= eofad_bin[i] ^ eofad_bin[i + 1] ; - end - end - end - end - - assign beo = ccdo[DATADEPTH + DATAWIDTH / 8 - 1:DATADEPTH] ; - - assign statad = ccdo[DATADEPTH - 1:0] ; - - always @(posedge clk) - begin : csmem_reg_proc - if (rst) - begin : csmem_reset - integer i; - for(i = ((1'b1 << CACHEDEPTH) - 1); i >= 0; i = i - 1) - begin - csmem[i] <= {CSWIDTH{1'b0}}; - end - csrad_r <= {CACHEDEPTH{1'b0}}; - end - else - begin - csmem[cswad] <= csdi ; - csrad_r <= csrad ; - end - end - - always @(posedge clk) - begin : csaddr_reg_proc - if (rst) - begin - cswad <= {CACHEDEPTH{1'b0}} ; - csrad <= {CACHEDEPTH{1'b0}} ; - end - else - begin - if (cswe) - begin - cswad <= cswad + 1 ; - end - - csrad <= csrad_c ; - end - end - - assign csrad_c = (csre) ? csrad + 1 : csrad ; - - always @(posedge clk) - begin : icsne_reg_proc - if (rst) - begin - icsne <= 1'b0 ; - end - else - begin - if (cswad == csrad | (csre & cswad == csrad_c)) - begin - icsne <= 1'b0 ; - end - else - begin - icsne <= 1'b1 ; - end - end - end - - assign csne = icsne; - - assign csdo = csmem[csrad_r] ; - - assign csdi = {dei, lci, loi, nci, eci, ic, cci, uri, statad} ; - - assign deo = csdo[CSWIDTH - 1] ; - - assign lco = csdo[CSWIDTH - 2] ; - - assign loo = csdo[CSWIDTH - 3] ; - - assign nco = csdo[CSWIDTH - 4] ; - - assign eco = csdo[CSWIDTH - 5] ; - - assign ico = csdo[CSWIDTH - 6] ; - - assign cco = csdo[CSWIDTH - 7:CSWIDTH - 10] ; - - assign uro = csdo[CSWIDTH - 11] ; - - assign statado = csdo[DATADEPTH - 1:0] ; - - assign cswe = tireq_r & tprog ; - - always @(posedge clk) - begin : csre_reg_proc - if (rst) - begin - csre <= 1'b0 ; - end - else - begin - csre <= cachere ; - end - end - - always @(posedge clk) - begin : tprog_reg_proc - if (rst) - begin - tprog <= 1'b0 ; - tprog_r <= 1'b0 ; - end - else - begin - tprog_r <= tprog ; - if (tireq_r) - begin - tprog <= 1'b0 ; - end - else if ((!sf & !tprog & !tireq_r & tresh) | ccne) - begin - tprog <= 1'b1 ; - end - end - end - - always @(posedge clk) - begin : eofreq_reg_proc - if (rst) - begin - eofreq <= 1'b0 ; - end - else - begin - if (tprog & ccne) - begin - eofreq <= 1'b1 ; - end - else if (tireq_r) - begin - eofreq <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : tireq_reg_proc - if (rst) - begin - tireq_r <= 1'b0 ; - tireq_r2 <= 1'b0 ; - end - else - begin - tireq_r <= tireq ; - tireq_r2 <= tireq_r ; - end - end - - always @(posedge clk) - begin : etireq_reg_proc - if (rst) - begin - etireq <= 1'b0 ; - end - else - begin - if (fifoeof) - begin - etireq <= 1'b1 ; - end - else if (etiack) - begin - etireq <= 1'b0 ; - end - end - end - - assign tiack = tireq_r2 ; - - assign sofreq = tprog ; - - always @(posedge clk) - begin : addr_reg_proc - if (rst) - begin - wad <= {FIFODEPTH{1'b0}} ; - wadg <= {FIFODEPTH{1'b0}} ; - radg_0_r <= {FIFODEPTH{1'b0}} ; - radg_r <= {FIFODEPTH{1'b0}} ; - rad <= {FIFODEPTH{1'b0}} ; - sad <= {FIFODEPTH{1'b0}} ; - end - else - begin - if (fifowe) - begin - wad <= wad + 1 ; - end - - wadg[FIFODEPTH - 1] <= wad[FIFODEPTH - 1] ; - begin : wadg_loop - integer i; - for(i = FIFODEPTH - 2; i >= 0; i = i - 1) - begin - wadg[i] <= wad[i] ^ wad[i + 1] ; - end - end - - radg_0_r <= radg ; - radg_r <= radg_0_r ; - - rad <= rad_c ; - - if (!tprog & tprog_r) - begin - sad <= eofad_bin ; - end - end - end - - always @(radg_r) - begin : rad_proc - reg[FIFODEPTH - 1:0] rad_v; - rad_v[FIFODEPTH - 1] = radg_r[FIFODEPTH - 1]; - begin : rad_loop - integer i; - for(i = FIFODEPTH - 2; i >= 0; i = i - 1) - begin - rad_v[i] = rad_v[i + 1] ^ radg_r[i]; - end - end - rad_c = rad_v ; - end - - always @(posedge clk) - begin : stat_reg_proc - if (rst) - begin - stat <= {FIFODEPTH{1'b0}} ; - end - else - begin - if ((!winp_r & !fdp & tprog & !tireq_r) | !tprog_r) - begin - stat <= wad - sad ; - end - else - begin - stat <= wad - rad ; - end - end - end - - always @(posedge clk) - begin : winp_reg_proc - if (rst) - begin - winp_r <= 1'b0 ; - end - else - begin - winp_r <= winp ; - end - end - - always @(tm) - begin : tresh_proc - tlev_c <= {FIFODEPTH_MAX{1'b0}} ; - case (DATAWIDTH) - 8 : - begin - case (tm) - 3'b000, 3'b101, 3'b110 : - begin - tlev_c[10:0] <= 11'b00010000000 ; - end - 3'b001, 3'b111 : - begin - tlev_c[10:0] <= 11'b00100000000 ; - end - 3'b010 : - begin - tlev_c[10:0] <= 11'b01000000000 ; - end - 3'b011 : - begin - tlev_c[10:0] <= 11'b10000000000 ; - end - default : - begin - tlev_c[10:0] <= 11'b00001000000 ; - end - endcase - end - 16 : - begin - case (tm) - 3'b000, 3'b101, 3'b110 : - begin - tlev_c[10:0] <= 11'b00001000000 ; - end - 3'b001, 3'b111 : - begin - tlev_c[10:0] <= 11'b00010000000 ; - end - 3'b010 : - begin - tlev_c[10:0] <= 11'b00100000000 ; - end - 3'b011 : - begin - tlev_c[10:0] <= 11'b01000000000 ; - end - default : - begin - tlev_c[10:0] <= 11'b00000100000 ; - end - endcase - end - default : - begin - case (tm) - 3'b000, 3'b101, 3'b110 : - begin - tlev_c[10:0] <= 11'b00000100000 ; - end - 3'b001, 3'b111 : - begin - tlev_c[10:0] <= 11'b00001000000 ; - end - 3'b010 : - begin - tlev_c[10:0] <= 11'b00010000000 ; - end - 3'b011 : - begin - tlev_c[10:0] <= 11'b00100000000 ; - end - default : - begin - tlev_c[10:0] <= 11'b00000010000 ; - end - endcase - end - endcase - end - - always @(posedge clk) - begin : tresh_reg_proc - if (rst) - begin - tresh <= 1'b0 ; - end - else - begin - if (stat >= tlev_c[FIFODEPTH - 1:0]) - begin - tresh <= 1'b1 ; - end - else - begin - tresh <= 1'b0 ; - end - end - end - - always @(pbl or pblz) - begin : sflev_proc - sflev_c[FIFODEPTH_MAX - 1:6] <= {(FIFODEPTH_MAX-6){1'b1}} ; - if (pblz) - begin - sflev_c[5:0] <= 6'b000000 ; - end - else - begin - sflev_c[5:0] <= ~pbl ; - end - end - - always @(posedge clk) - begin : fifoval_reg_proc - if (rst) - begin - fifoval <= 1'b0 ; - end - else - begin - if (stat <= sflev_c[FIFODEPTH - 1:0]) - begin - fifoval <= 1'b1 ; - end - else - begin - fifoval <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : pblz_reg_proc - if (rst) - begin - pblz <= 1'b0 ; - end - else - begin - if (pbl == 6'b000000) - begin - pblz <= 1'b1 ; - end - else - begin - pblz <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : fifonf_reg_proc - if (rst) - begin - fifonf <= 1'b1 ; - end - else - begin - if ((stat == {fone[FIFODEPTH - 1:1], 1'b0} & fifowe) | - (stat == fone)) - begin - fifonf <= 1'b0 ; - end - else - begin - fifonf <= 1'b1 ; - end - end - end - - assign flev = stat ; - - assign ramaddr = wad ; - - assign ramdata = fifodata ; - - assign ramwe = fifowe ; - - always @(posedge clk) - begin : tstop_reg_proc - if (rst) - begin - stop_r <= 1'b1 ; - stopo <= 1'b0 ; - end - else - begin - stop_r <= stopi ; - - if (stop_r & !ccne & !icsne & stat == fzero & !tprog) - begin - stopo <= 1'b1 ; - end - else - begin - stopo <= 1'b0 ; - end - end - end - - assign fone = {FIFODEPTH{1'b1}} ; - - assign fzero = {FIFODEPTH{1'b0}} ; - -endmodule - - - -module TLSM_V ( - clk, - rst, - fifonf, - fifocnf, - fifoval, - fifolev, - fifowe, - fifoeof, - fifobe, - fifodata, - ic, - ac, - dpd, - statado, - csne, - lo, - nc, - lc, - ec, - de, - ur, - cc, - statadi, - cachere, - dmaack, - dmaeob, - dmadatai, - dmaaddr, - dmareq, - dmawr, - dmacnt, - dmaaddro, - dmadatao, - fwe, - fdata, - faddr, - dsl, - pbl, - poll, - dbadc, - dbad, - pollack, - tcompack, - tcomp, - des, - fbuf, - stat, - setp, - tu, - ft, - stopi, - stopo - ); - - parameter DATAWIDTH = 32; - parameter DATADEPTH = 32; - parameter FIFODEPTH = 9; - - `include "utility.v" - - input clk; - input rst; - - input fifonf; - input fifocnf; - input fifoval; - input [FIFODEPTH - 1:0] fifolev; - output fifowe; - wire fifowe; - output fifoeof; - wire fifoeof; - output [DATAWIDTH / 8 - 1:0] fifobe; - reg [DATAWIDTH / 8 - 1:0] fifobe; - output [DATAWIDTH - 1:0] fifodata; - wire [DATAWIDTH - 1:0] fifodata; - - output ic; - reg ic; - output ac; - reg ac; - output dpd; - reg dpd; - output [DATADEPTH - 1:0] statado; - wire [DATADEPTH - 1:0] statado; - - input csne; - input lo; - input nc; - input lc; - input ec; - input de; - input ur; - input [3:0] cc; - input [DATADEPTH - 1:0] statadi; - output cachere; - wire cachere; - - input dmaack; - input dmaeob; - input [DATAWIDTH - 1:0] dmadatai; - input [DATADEPTH - 1:0] dmaaddr; - output dmareq; - wire dmareq; - output dmawr; - wire dmawr; - output [FIFODEPTH_MAX - 1:0] dmacnt; - wire [FIFODEPTH_MAX - 1:0] dmacnt; - output [DATADEPTH - 1:0] dmaaddro; - reg [DATADEPTH - 1:0] dmaaddro; - output [DATAWIDTH - 1:0] dmadatao; - reg [DATAWIDTH - 1:0] dmadatao; - - output fwe; - wire fwe; - output [ADDRWIDTH - 1:0] fdata; - wire [ADDRWIDTH - 1:0] fdata; - output [ADDRDEPTH - 1:0] faddr; - wire [ADDRDEPTH - 1:0] faddr; - - input [4:0] dsl; - input [5:0] pbl; - input poll; - input dbadc; - input [DATADEPTH - 1:0] dbad; - output pollack; - wire pollack; - - input tcompack; - output tcomp; - wire tcomp; - output des; - reg des; - output fbuf; - reg fbuf; - output stat; - reg stat; - output setp; - reg setp; - output tu; - reg tu; - output [1:0] ft; - reg [1:0] ft; - - input stopi; - output stopo; - reg stopo; - - - wire [DATAWIDTH_MAX + 1:0] dmadatai_max; - reg [DATAWIDTH_MAX - 1:0] dataimax_r; - wire [1:0] dataimax_r10; - wire [2:0] dmaaddr20; - reg req_c; - reg req; - reg [2:0] req_r; - - reg idmareq; - wire [31:0] datao32; - wire [FIFODEPTH_MAX - 1:0] bsmax; - wire [FIFODEPTH_MAX - 1:0] flmax; - wire [FIFODEPTH - 1:0] flmax_sub; - wire [FIFODEPTH_MAX - 1:0] blmax; - reg fl_g_bs; - reg fl_g_bl; - reg bl_g_bs; - reg pblz; - reg buffetch; - reg dmaack_r; - - reg [3:0] lsm_c; - reg [3:0] lsm; - reg [3:0] lsm_r; - reg [2:0] csm_c; - reg [2:0] csm; - reg [2:0] lsmcnt; - reg tsprog; - reg [DATADEPTH - 1:0] statad; - wire es_c; - reg own_c; - reg own; - reg tch; - reg ter; - reg set; - reg tls; - reg tfs; - wire [10:0] bs_c; - wire [1:0] bs_c10; - reg [10:0] bs1; - reg [10:0] bs2; - reg adwrite; - reg [DATADEPTH - 1:0] bad; - reg [DATADEPTH - 1:0] dad; - reg dbadc_r; - wire [31:0] tstat; - reg lastdma; - reg icachere; - reg poll_r; - reg [FIFODEPTH_MAX - 1:0] dmacnt_c; - reg [FIFODEPTH_MAX - 1:0] dmacnt_r; - - wire [1:0] addsel16; - wire [3:0] addsel32; - reg [3:0] addv_c; - reg [1:0] badd_c; - reg [11:0] bcnt; - reg ififowe; - wire bufwe; - wire firstb_c; - reg firstb; - reg [DATAWIDTH - 1:0] buf0_c; - reg [DATAWIDTH * 2 - 9:0] buf_c; - reg [DATAWIDTH * 2 - 9:0] buf_r; - reg [3:0] buflev_c; - reg [3:0] buflev; - reg [DATAWIDTH / 8 - 1:0] firstbe; - reg [DATAWIDTH / 8 - 1:0] lastbe; - reg [DATAWIDTH / 8 - 1:0] be; - wire [1:0] be10; - wire [3:0] be30; - - reg itcomp; - reg tcompack_r; - - reg ifwe; - reg [ADDRDEPTH - 1:0] ifaddr; - - reg stop_r; - - wire [FIFODEPTH_MAX - 1:0] fzero_max; - wire [DATAWIDTH_MAX + 1:0] dzero_max; - wire [DATAWIDTH_MAX * 2 - 7:0] buf_r_max; - wire [DATAWIDTH_MAX * 2 - 7:0] bufzero_max; - - - always @(posedge clk) - begin : idmareq_reg_proc - if (rst) - begin - idmareq <= 1'b0 ; - end - else - begin - if (req_c) - begin - idmareq <= 1'b1 ; - end - else if (dmaack & dmaeob) - begin - idmareq <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : cachere_reg_proc - if (rst) - begin - icachere <= 1'b0 ; - end - else - begin - if (itcomp & tcompack_r) - begin - icachere <= 1'b1 ; - end - else - begin - icachere <= 1'b0 ; - end - end - end - - assign cachere = icachere ; - - always @(lsm or - csm or - poll_r or - dmaack or - dmaeob or - own_c or - tch or - bs1 or - bs2 or - stop_r or - lsmcnt or - fifocnf or - tsprog or - lastdma or - dbadc_r) - begin : lsm_proc - case (lsm) - LSM_IDLE : - begin - if (!dbadc_r & !stop_r & fifocnf & (poll_r | (tsprog & dmaack & dmaeob))) - begin - lsm_c <= LSM_DES0 ; - end - else - begin - lsm_c <= LSM_IDLE ; - end - end - LSM_DES0 : - begin - if (dmaack & dmaeob & !tsprog) - begin - if (own_c) - begin - lsm_c <= LSM_DES1 ; - end - else - begin - lsm_c <= LSM_IDLE ; - end - end - else - begin - lsm_c <= LSM_DES0 ; - end - end - LSM_DES1 : - begin - if (dmaack & dmaeob & !tsprog) - begin - lsm_c <= LSM_DES2 ; - end - else - begin - lsm_c <= LSM_DES1 ; - end - end - LSM_DES2 : - begin - if (dmaack & dmaeob & !tsprog) - begin - if (bs1 == 11'b00000000000 | csm == CSM_IDLE) - begin - lsm_c <= LSM_DES3 ; - end - else - begin - lsm_c <= LSM_BUF1 ; - end - end - else - begin - lsm_c <= LSM_DES2 ; - end - end - LSM_DES3 : - begin - if (dmaack & dmaeob & !tsprog) - begin - if (bs2 == 11'b00000000000 | tch | csm == CSM_IDLE) - begin - lsm_c <= LSM_NXT ; - end - else - begin - lsm_c <= LSM_BUF2 ; - end - end - else - begin - lsm_c <= LSM_DES3 ; - end - end - LSM_BUF1 : - begin - if (!tsprog & dmaack & dmaeob & lastdma) - begin - lsm_c <= LSM_DES3 ; - end - else - begin - lsm_c <= LSM_BUF1 ; - end - end - LSM_BUF2 : - begin - if (!tsprog & dmaack & dmaeob & lastdma) - begin - lsm_c <= LSM_NXT ; - end - else - begin - lsm_c <= LSM_BUF2 ; - end - end - LSM_NXT : - begin - if (lsmcnt == 3'b000) - begin - if (csm == CSM_L | csm == CSM_FL) - begin - if (stop_r | !fifocnf) - begin - lsm_c <= LSM_IDLE ; - end - else - begin - lsm_c <= LSM_DES0 ; - end - end - else - begin - lsm_c <= LSM_STAT ; - end - end - else - begin - lsm_c <= LSM_NXT ; - end - end - default : - begin - if (dmaack & dmaeob & !tsprog) - begin - if (stop_r) - begin - lsm_c <= LSM_IDLE ; - end - else - begin - lsm_c <= LSM_DES0 ; - end - end - else - begin - lsm_c <= LSM_STAT ; - end - end - endcase - end - - always @(posedge clk) - begin : lsm_reg_proc - if (rst) - begin - lsm <= LSM_IDLE ; - lsm_r <= LSM_IDLE ; - end - else - begin - lsm <= lsm_c ; - lsm_r <= lsm ; - end - end - - always @(csm or lsm or tfs or tls or own or set or bs1 or bs2) - begin : csm_proc - case (csm) - CSM_IDLE : - begin - if (lsm == LSM_DES2) - begin - if (!set & tfs & tls) - begin - csm_c <= CSM_FL ; - end - else if (!set & tfs & !tls) - begin - csm_c <= CSM_F ; - end - else if (set & !tfs & !tls) - begin - csm_c <= CSM_SET ; - end - else - begin - csm_c <= CSM_IDLE ; - end - end - else - begin - csm_c <= CSM_IDLE ; - end - end - CSM_FL : - begin - if (lsm == LSM_DES0 | lsm == LSM_IDLE) - begin - csm_c <= CSM_IDLE ; - end - else if (lsm == LSM_DES2 & - bs1 == 11'b00000000000 & - bs2 == 11'b00000000000) - begin - csm_c <= CSM_BAD ; - end - else - begin - csm_c <= CSM_FL ; - end - end - CSM_F : - begin - if (tls) - begin - csm_c <= CSM_L ; - end - else if (lsm == LSM_DES1 & !tfs) - begin - csm_c <= CSM_I ; - end - else - begin - csm_c <= CSM_F ; - end - end - CSM_L : - begin - if (lsm == LSM_DES0 | lsm == LSM_IDLE) - begin - csm_c <= CSM_IDLE ; - end - else - begin - csm_c <= CSM_L ; - end - end - CSM_SET : - begin - if (lsm == LSM_DES0 | lsm == LSM_IDLE) - begin - csm_c <= CSM_IDLE ; - end - else - begin - csm_c <= CSM_SET ; - end - end - CSM_I : - begin - if (tls) - begin - csm_c <= CSM_L ; - end - else - begin - csm_c <= CSM_I ; - end - end - default : - begin - if (lsm == LSM_NXT) - begin - csm_c <= CSM_IDLE ; - end - else - begin - csm_c <= CSM_BAD ; - end - end - endcase - end - - always @(posedge clk) - begin : csm_reg_proc - if (rst) - begin - csm <= CSM_IDLE ; - end - else - begin - csm <= csm_c ; - end - end - - always @(posedge clk) - begin : lsmcnt_reg_proc - if (rst) - begin - lsmcnt <= {3{1'b1}} ; - end - else - begin - if (lsm == LSM_NXT) - begin - lsmcnt <= lsmcnt - 1 ; - end - else - begin - lsmcnt <= {3{1'b1}} ; - end - end - end - - always @(posedge clk) - begin : poll_reg_proc - if (rst) - begin - poll_r <= 1'b0 ; - end - else - begin - if (poll) - begin - poll_r <= 1'b1 ; - end - else if (!dbadc_r) - begin - poll_r <= 1'b0 ; - end - end - end - - assign pollack = poll_r ; - - always @(own or dmaack or dmaeob or lsm or dmadatai_max or tsprog) - begin : own_proc - if (dmaack & dmaeob & lsm == LSM_DES0 & !tsprog) - begin - own_c <= dmadatai_max[DATAWIDTH - 1] ; - end - else - begin - own_c <= own ; - end - end - - always @(posedge clk) - begin : own_reg_proc - if (rst) - begin - own <= 1'b1 ; - end - else - begin - own <= own_c ; - end - end - - always @(posedge clk) - begin : des1_reg_proc - reg ft22; - if (rst) - begin - ft22 = 1'b0; - tls <= 1'b0 ; - tfs <= 1'b0 ; - set <= 1'b0 ; - ac <= 1'b0 ; - ter <= 1'b0 ; - tch <= 1'b0 ; - dpd <= 1'b0 ; - ic <= 1'b0 ; - bs2 <= {11{1'b0}} ; - bs1 <= {11{1'b0}} ; - ft <= {2{1'b0}} ; - end - else - begin - if (lsm == LSM_DES1 & dmaack & !tsprog) - begin - case (DATAWIDTH) - 8 : - begin - case (dmaaddr20) - 3'b000, 3'b100 : - begin - bs1[7:0] <= dmadatai_max[7:0] ; - end - 3'b001, 3'b101 : - begin - bs1[10:8] <= dmadatai_max[2:0] ; - bs2[4:0] <= dmadatai_max[7:3] ; - end - 3'b010, 3'b110 : - begin - bs2[10:5] <= dmadatai_max[5:0] ; - dpd <= dmadatai_max[7] ; - ft22 = dmadatai_max[6]; - end - default : - begin - ic <= dmadatai_max[7] ; - tls <= dmadatai_max[6] ; - tfs <= dmadatai_max[5] ; - set <= dmadatai_max[3] ; - ac <= dmadatai_max[2] ; - ter <= dmadatai_max[1] ; - tch <= dmadatai_max[0] ; - if (dmadatai_max[3]) - begin - ft <= {dmadatai_max[4], ft22} ; - end - end - endcase - end - 16 : - begin - case (dmaaddr20) - 3'b000, 3'b100 : - begin - bs1[10:0] <= dmadatai_max[10:0] ; - bs2[4:0] <= dmadatai_max[15:11] ; - end - default : - begin - bs2[10:5] <= dmadatai_max[5:0] ; - ic <= dmadatai_max[15] ; - tls <= dmadatai_max[14] ; - tfs <= dmadatai_max[13] ; - set <= dmadatai_max[11] ; - ac <= dmadatai_max[10] ; - ter <= dmadatai_max[9] ; - tch <= dmadatai_max[8] ; - dpd <= dmadatai_max[7] ; - if (dmadatai_max[11]) - begin - ft <= {dmadatai_max[12], dmadatai_max[6]} ; - end - end - endcase - end - default : - begin - ic <= dmadatai_max[31] ; - tls <= dmadatai_max[30] ; - tfs <= dmadatai_max[29] ; - set <= dmadatai_max[27] ; - ac <= dmadatai_max[26] ; - ter <= dmadatai_max[25] ; - tch <= dmadatai_max[24] ; - dpd <= dmadatai_max[23] ; - bs2 <= dmadatai_max[21:11] ; - bs1 <= dmadatai_max[10:0] ; - if (dmadatai_max[27]) - begin - ft <= {dmadatai_max[28], dmadatai_max[22]} ; - end - end - endcase - end - end - end - - always @(posedge clk) - begin : adwrite_reg_proc - if (rst) - begin - adwrite <= 1'b0 ; - end - else - begin - if (dmaack & dmaeob & !tsprog) - begin - adwrite <= 1'b1 ; - end - else - begin - adwrite <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : dbadc_reg_proc - if (rst) - begin - dbadc_r <= 1'b0 ; - end - else - begin - dbadc_r <= dbadc ; - end - end - - always @(posedge clk) - begin : dad_reg_proc - if (rst) - begin - dad <= {DATADEPTH{1'b1}} ; - end - else - begin - if (dbadc_r) - begin - dad <= dbad ; - end - else if (adwrite) - begin - case (lsm_r) - LSM_DES3 : - begin - if (ter) - begin - dad <= dbad ; - end - else if (tch) - begin - dad <= dataimax_r[DATADEPTH - 1:0] ; - end - else - begin - dad <= dmaaddr + ({dsl, 2'b00}) ; - end - end - LSM_DES0 : - begin - if (own) - begin - dad <= dmaaddr ; - end - end - LSM_DES2 : - begin - dad <= dmaaddr ; - end - LSM_DES1 : - begin - dad <= dmaaddr ; - end - default : - begin - end - endcase - end - end - end - - always @(posedge clk) - begin : bad_reg_proc - if (rst) - begin - bad <= {DATADEPTH{1'b1}} ; - end - else - begin - if (adwrite) - begin - if (lsm_r == LSM_DES2 | lsm_r == LSM_DES3) - begin - case (DATAWIDTH) - 8 : - begin - bad <= dataimax_r[DATADEPTH - 1:0] ; - end - 16 : - begin - bad <= {dataimax_r[DATADEPTH - 1:1], 1'b0} ; - end - default : - begin - bad <= {dataimax_r[DATADEPTH - 1:2], 2'b00} ; - end - endcase - end - else - begin - bad <= dmaaddr ; - end - end - end - end - - always @(posedge clk) - begin : stataddr_reg_proc - if (rst) - begin - statad <= {DATADEPTH{1'b1}} ; - end - else - begin - if (lsm_r == LSM_DES0 & adwrite & own) - begin - statad <= dad ; - end - end - end - - assign statado = statad ; - - assign bs_c = (lsm_r == LSM_DES2) ? bs1 : bs2 ; - - assign addsel16 = {dataimax_r[0], bs_c[0]} ; - - assign addsel32 = {dataimax_r10, bs_c10} ; - - always @(addsel16 or addsel32) - begin : badd_proc - case (DATAWIDTH) - 8 : - begin - badd_c <= 2'b00 ; - end - 16 : - begin - if (addsel16 == 2'b01 | - addsel16 == 2'b10 | - addsel16 == 2'b11) - begin - badd_c <= 2'b01 ; - end - else - begin - badd_c <= 2'b00 ; - end - end - default : - begin - case (addsel32) - 4'b0000 : - begin - badd_c <= 2'b00 ; - end - 4'b1011, 4'b1110, 4'b1111 : - begin - badd_c <= 2'b10 ; - end - default : - begin - badd_c <= 2'b01 ; - end - endcase - end - endcase - end - - always @(posedge clk) - begin : bcnt_reg_proc - if (rst) - begin - bcnt <= {12{1'b1}} ; - end - else - begin - case (DATAWIDTH) - 8 : - begin - if (lsm_r == LSM_DES2 | lsm_r == LSM_DES3) - begin - bcnt <= {1'b0, bs_c} ; - end - else if (dmaack & !tsprog) - begin - bcnt <= bcnt - 1 ; - end - end - 16 : - begin - if (lsm_r == LSM_DES2 | lsm_r == LSM_DES3) - begin - bcnt <= {(({1'b0, bs_c[10:1]}) + badd_c), 1'b0} ; - end - else if (dmaack & !tsprog) - begin - bcnt <= {(bcnt[11:1] - 1), 1'b0} ; - end - end - default : - begin - if (lsm_r == LSM_DES2 | lsm_r == LSM_DES3) - begin - bcnt <= {(({1'b0, bs_c[10:2]}) + badd_c), 2'b00} ; - end - else if (dmaack & !tsprog) - begin - bcnt <= {(bcnt[11:2] - 1), 2'b00} ; - end - end - endcase - end - end - - - assign bs_c10 = bs_c[1:0] ; - - assign dataimax_r10 = dataimax_r[1:0] ; - - always @(posedge clk) - begin : firstbe_reg_proc - if (rst) - begin - firstbe <= {(DATAWIDTH/8){1'b1}} ; - end - else - begin - if (lsm_r == LSM_DES2 | lsm_r == LSM_DES3) - begin - case (DATAWIDTH) - 8 : - begin - firstbe <= 1'b1 ; - end - 16 : - begin - if (dataimax_r[0]) - begin - firstbe <= 2'b10 ; - end - else - begin - firstbe <= 2'b11 ; - end - end - default : - begin - case (dataimax_r10) - 2'b00 : - begin - firstbe <= 4'b1111 ; - end - 2'b01 : - begin - firstbe <= 4'b1110 ; - end - 2'b10 : - begin - firstbe <= 4'b1100 ; - end - default : - begin - firstbe <= 4'b1000 ; - end - endcase - end - endcase - end - end - end - - always @(posedge clk) - begin : lastbe_reg_proc - if (rst) - begin - lastbe <= {(DATAWIDTH/8){1'b1}} ; - end - else - begin - if (lsm_r == LSM_DES2 | lsm_r == LSM_DES3) - begin - case (DATAWIDTH) - 8 : - begin - lastbe <= 1'b1 ; - end - 16 : - begin - if ((!(dataimax_r[0]) & !(bs_c[0])) | - ((dataimax_r[0]) & (bs_c[0]))) - begin - lastbe <= 2'b11 ; - end - else - begin - lastbe <= 2'b01 ; - end - end - default : - begin - case (dataimax_r10) - 2'b00 : - begin - case (bs_c10) - 2'b00 : - begin - lastbe <= 4'b1111 ; - end - 2'b01 : - begin - lastbe <= 4'b0001 ; - end - 2'b10 : - begin - lastbe <= 4'b0011 ; - end - default : - begin - lastbe <= 4'b0111 ; - end - endcase - end - 2'b01 : - begin - case (bs_c10) - 2'b00 : - begin - lastbe <= 4'b0001 ; - end - 2'b01 : - begin - lastbe <= 4'b0011 ; - end - 2'b10 : - begin - lastbe <= 4'b0111 ; - end - default : - begin - lastbe <= 4'b1111 ; - end - endcase - end - 2'b10 : - begin - case (bs_c10) - 2'b00 : - begin - lastbe <= 4'b0011 ; - end - 2'b01 : - begin - lastbe <= 4'b0111 ; - end - 2'b10 : - begin - lastbe <= 4'b1111 ; - end - default : - begin - lastbe <= 4'b0001 ; - end - endcase - end - default : - begin - case (bs_c10) - 2'b00 : - begin - lastbe <= 4'b0111 ; - end - 2'b01 : - begin - lastbe <= 4'b1111 ; - end - 2'b10 : - begin - lastbe <= 4'b0001 ; - end - default : - begin - lastbe <= 4'b0011 ; - end - endcase - end - endcase - end - endcase - end - end - end - - always @(posedge clk) - begin : tfwe_reg_proc - if (rst) - begin - ififowe <= 1'b0 ; - end - else - begin - if (((DATAWIDTH == 8 & buflev_c >= 4'b0001 & bufwe) | - (DATAWIDTH ==16 & buflev_c >= 4'b0010 & bufwe) | - (DATAWIDTH ==32 & buflev_c >= 4'b0100 & bufwe) | - (buflev_c != 4'b0000 & lsm == LSM_NXT & - (csm == CSM_L | csm == CSM_FL))) & fifonf) - begin - ififowe <= 1'b1 ; - end - else - begin - ififowe <= 1'b0 ; - end - end - end - - assign fifoeof = ((csm == CSM_L | csm == CSM_FL) & - lsm == LSM_NXT & lsmcnt == 3'b001) ? 1'b1 : 1'b0 ; - - assign fifowe = ififowe ; - - assign firstb_c = (bufwe) ? 1'b0 : - (lsm == LSM_DES2 | lsm == LSM_DES3) ? 1'b1 : - firstb ; - - always @(firstb or firstbe or lastbe or dmaeob or lastdma) - begin : be_proc - if (dmaeob & lastdma) - begin - be <= lastbe ; - end - else if (firstb) - begin - be <= firstbe ; - end - else - begin - be <= {(DATAWIDTH/8){1'b1}} ; - end - end - - always @(be or be30 or dmadatai_max) - begin : tbuf0_proc - reg[15:0] buf0_16; - reg[31:0] buf0_32; - buf0_c <= {DATAWIDTH{1'b0}} ; - case (DATAWIDTH) - 8 : - begin - buf0_c <= dmadatai_max[7:0]; - end - 16 : - begin - buf0_16 = {16{1'b0}}; - if (be == 2'b10) - begin - buf0_16[7:0] = dmadatai_max[15:8]; - end - else - begin - buf0_16 = dmadatai_max[15:0]; - end - buf0_c <= buf0_16 ; - end - default : - begin - buf0_32 = {32{1'b0}}; - case (be30) - 4'b1110 : - begin - buf0_32[23:0] = dmadatai_max[31:8]; - end - 4'b1100 : - begin - buf0_32[15:0] = dmadatai_max[31:16]; - end - 4'b1000 : - begin - buf0_32[7:0] = dmadatai_max[31:24]; - end - default : - begin - buf0_32 = dmadatai_max[31:0]; - end - endcase - buf0_c <= buf0_32 ; - end - endcase - end - - always @(buflev or buf_r_max or buf0_c or bufwe or ififowe) - begin : tbuf_proc - reg[23:0] buf_16; - reg[55:0] buf_32; - case (DATAWIDTH) - 8 : - begin - buf_c <= buf0_c ; - end - 16 : - begin - buf_16 = buf_r_max[DATAWIDTH * 2 - 9:0]; - if (bufwe) - begin - case (buflev) - 4'b0000 : - begin - buf_16[15:0] = buf0_c; - end - 4'b0001 : - begin - buf_16[23:8] = buf0_c; - end - 4'b0010 : - begin - buf_16[15:0] = buf0_c; - end - default : - begin - buf_16[23:8] = buf0_c; - buf_16[7:0] = buf_r_max[23:16]; - end - endcase - end - else if (ififowe) - begin - buf_16 = {buf_r_max[23:8], buf_r_max[23:16]}; - end - buf_c <= buf_16 ; - end - default : - begin - buf_32 = buf_r_max[DATAWIDTH * 2 - 9:0]; - if (bufwe) - begin - case (buflev) - 4'b0000 : - begin - buf_32[31:0] = buf0_c; - end - 4'b0001 : - begin - buf_32[39:8] = buf0_c; - end - 4'b0010 : - begin - buf_32[47:16] = buf0_c; - end - 4'b0011 : - begin - buf_32[55:24] = buf0_c; - end - 4'b0100 : - begin - buf_32[31:0] = buf0_c; - end - 4'b0101 : - begin - buf_32[39:8] = buf0_c; - buf_32[7:0] = buf_r_max[39:32]; - end - 4'b0110 : - begin - buf_32[47:16] = buf0_c; - buf_32[15:0] = buf_r_max[47:32]; - end - default : - begin - buf_32[55:24] = buf0_c; - buf_32[23:0] = buf_r_max[55:32]; - end - endcase - end - else if (ififowe) - begin - buf_32 = {buf_r_max[55:24], buf_r_max[55:32]}; - end - buf_c <= buf_32 ; - end - endcase - end - - assign bufwe = (dmaack & !set & fifonf & !tsprog & - (lsm == LSM_BUF1 | lsm == LSM_BUF2)) ? 1'b1 : 1'b0 ; - - assign fifodata = buf_r_max[DATAWIDTH - 1:0] ; - - assign be10 = (DATAWIDTH == 16) ? be : {2{1'b1}} ; - - assign be30 = (DATAWIDTH == 32) ? be : {4{1'b1}} ; - - always @(be10 or be30) - begin : addv_proc - case (DATAWIDTH) - 8 : - begin - addv_c <= 4'b0000 ; - end - 16 : - begin - case (be10) - 2'b01, 2'b10 : - begin - addv_c <= 4'b0001 ; - end - default : - begin - addv_c <= 4'b0010 ; - end - endcase - end - default : - begin - case (be30) - 4'b0001, 4'b1000 : - begin - addv_c <= 4'b0001 ; - end - 4'b0011, 4'b1100 : - begin - addv_c <= 4'b0010 ; - end - 4'b0111, 4'b1110 : - begin - addv_c <= 4'b0011 ; - end - default : - begin - addv_c <= 4'b0100 ; - end - endcase - end - endcase - end - - always @(buflev or bufwe or ififowe or addv_c) - begin : buflev_proc - case (DATAWIDTH) - 8 : - begin - if (bufwe) - begin - buflev_c <= 4'b0001 ; - end - else if (ififowe) - begin - buflev_c <= 4'b0000 ; - end - else - begin - buflev_c <= buflev ; - end - end - 16 : - begin - if (bufwe) - begin - buflev_c <= ({buflev[3:2], 1'b0, buflev[0]}) + addv_c ; - end - else if (ififowe & (buflev[1])) - begin - buflev_c <= {buflev[3:2], 1'b0, buflev[0]} ; - end - else if (ififowe & !(buflev[1])) - begin - buflev_c <= {buflev[3:1], 1'b0} ; - end - else - begin - buflev_c <= buflev ; - end - end - default : - begin - if (bufwe) - begin - buflev_c <= ({buflev[3:3], 1'b0, buflev[1:0]}) + addv_c ; - end - else if (ififowe & (buflev[2])) - begin - buflev_c <= {buflev[3:3], 1'b0, buflev[1:0]} ; - end - else if (ififowe & !(buflev[2])) - begin - buflev_c <= {buflev[3:2], 2'b00} ; - end - else - begin - buflev_c <= buflev ; - end - end - endcase - end - - always @(posedge clk) - begin : buf_reg_proc - if (rst) - begin - buflev <= {4{1'b0}} ; - firstb <= 1'b1 ; - buf_r <= {(DATAWIDTH*2){1'b0}} ; - end - else - begin - buflev <= buflev_c ; - firstb <= firstb_c ; - buf_r <= buf_c ; - end - end - - always @(posedge clk) - begin : lbe_reg_proc - if (rst) - begin - fifobe <= {(DATAWIDTH/8){1'b1}} ; - end - else - begin - if (ififowe) - begin - case (DATAWIDTH) - 8 : - begin - fifobe <= 1'b1 ; - end - 16 : - begin - case (buflev) - 4'b0001 : - begin - fifobe <= 2'b01 ; - end - default : - begin - fifobe <= 2'b11 ; - end - endcase - end - default : - begin - case (buflev) - 4'b0001 : - begin - fifobe <= 4'b0001 ; - end - 4'b0010 : - begin - fifobe <= 4'b0011 ; - end - 4'b0011 : - begin - fifobe <= 4'b0111 ; - end - default : - begin - fifobe <= 4'b1111 ; - end - endcase - end - endcase - end - end - end - - assign es_c = ur | lc | lo | nc | ec ; - - assign tstat = {1'b0, TDES0_RV[30:16], - es_c, TDES0_RV[14:12], lo, nc, lc, - ec, TDES0_RV[7], - cc, TDES0_RV[2], ur, de}; - - assign datao32 = (tsprog) ? tstat : (set) ? SET0_RV : TDES0_RV ; - - always @(posedge clk) - begin : dataimax_reg_proc - if (rst) - begin - dataimax_r <= {DATADEPTH_MAX{1'b1}} ; - end - else - begin - case (DATAWIDTH) - 8 : - begin - case (dmaaddr20) - 3'b000, 3'b100 : - begin - dataimax_r[7:0] <= dmadatai_max[DATAWIDTH-1:0] ; - end - 3'b001, 3'b101 : - begin - dataimax_r[15:8] <= dmadatai_max[DATAWIDTH-1:0] ; - end - 3'b010, 3'b110 : - begin - dataimax_r[23:16] <= dmadatai_max[DATAWIDTH-1:0] ; - end - default : - begin - dataimax_r[31:24] <= dmadatai_max[DATAWIDTH-1:0] ; - end - endcase - end - 16 : - begin - if (!(dmaaddr[1])) - begin - dataimax_r[15:0] <= dmadatai_max[DATAWIDTH-1:0] ; - end - else - begin - dataimax_r[31:16] <= dmadatai_max[DATAWIDTH-1:0] ; - end - end - default : - begin - dataimax_r <= dmadatai_max[31:0] ; - end - endcase - end - end - - always @(datao32 or dmaaddr) - begin : datao_proc - reg[1:0] addr10; - addr10 = dmaaddr[1:0]; - case (DATAWIDTH) - 8 : - begin - case (addr10) - 2'b00 : - begin - dmadatao <= datao32[7:0] ; - end - 2'b01 : - begin - dmadatao <= datao32[15:8] ; - end - 2'b10 : - begin - dmadatao <= datao32[23:16] ; - end - default : - begin - dmadatao <= datao32[31:24] ; - end - endcase - end - 16 : - begin - if (!(addr10[1])) - begin - dmadatao <= datao32[15:0] ; - end - else - begin - dmadatao <= datao32[31:16] ; - end - end - default : - begin - dmadatao <= datao32 ; - end - endcase - end - - assign flmax_sub = fzero_max[FIFODEPTH - 1:0] - 1 - fifolev ; - - assign flmax = {fzero_max[FIFODEPTH_MAX - 1:FIFODEPTH], - flmax_sub} ; - - assign blmax = {fzero_max[FIFODEPTH_MAX - 1:6], pbl} ; - - assign bsmax = (DATAWIDTH == 8) ? {fzero_max[FIFODEPTH_MAX - 1:12], - bcnt} : - (DATAWIDTH ==16) ? {fzero_max[FIFODEPTH_MAX - 1:11], - bcnt[11:1]} : - {fzero_max[FIFODEPTH_MAX - 1:10], - bcnt[11:2]} ; - - always @(posedge clk) - begin : fifolev_reg_proc - if (rst) - begin - fl_g_bs <= 1'b0 ; - fl_g_bl <= 1'b0 ; - bl_g_bs <= 1'b0 ; - pblz <= 1'b0 ; - end - else - begin - if (flmax >= bsmax) - begin - fl_g_bs <= 1'b1 ; - end - else - begin - fl_g_bs <= 1'b0 ; - end - - if (flmax >= blmax) - begin - fl_g_bl <= 1'b1 ; - end - else - begin - fl_g_bl <= 1'b0 ; - end - - if (blmax >= bsmax) - begin - bl_g_bs <= 1'b1 ; - end - else - begin - bl_g_bs <= 1'b0 ; - end - - if (pbl == 6'b000000) - begin - pblz <= 1'b1 ; - end - else - begin - pblz <= 1'b0 ; - end - end - end - - always @(csm or - lsm or - pblz or - tsprog or - fl_g_bs or - fl_g_bl or - bl_g_bs or - blmax or - bsmax or - flmax or - fzero_max or - buffetch or - dmacnt_r) - begin : dmacnt_proc - if (lsm == LSM_DES0 | - lsm == LSM_DES1 | - lsm == LSM_DES2 | - lsm == LSM_DES3 | - lsm == LSM_STAT | tsprog) - begin - case (DATAWIDTH) - 8 : - begin - dmacnt_c <= {fzero_max[FIFODEPTH_MAX - 1:3], 3'b100} ; - end - 16 : - begin - dmacnt_c <= {fzero_max[FIFODEPTH_MAX - 1:3], 3'b010} ; - end - default : - begin - dmacnt_c <= {fzero_max[FIFODEPTH_MAX - 1:3], 3'b001} ; - end - endcase - end - else if(!buffetch) - begin - if (pblz) - begin - if (fl_g_bs | csm == CSM_SET) - begin - dmacnt_c <= bsmax ; - end - else - begin - dmacnt_c <= flmax ; - end - end - else - begin - if (fl_g_bl | csm == CSM_SET) - begin - if (bl_g_bs) - begin - dmacnt_c <= bsmax ; - end - else - begin - dmacnt_c <= blmax ; - end - end - else - begin - if (fl_g_bs) - begin - dmacnt_c <= bsmax ; - end - else - begin - dmacnt_c <= flmax ; - end - end - end - end - else - begin - dmacnt_c <= dmacnt_r; - end - end - - always @(posedge clk) - begin : dmacnt_reg_proc - if (rst) - begin - dmacnt_r <= {FIFODEPTH_MAX{1'b0}}; - end - else - begin - dmacnt_r <= dmacnt_c; - end - end - - assign dmacnt = dmacnt_c; - - always @(posedge clk) - begin : lastdma_reg_proc - if (rst) - begin - lastdma <= 1'b1 ; - end - else - begin - if (lsm == LSM_DES0 | - lsm == LSM_DES1 | - lsm == LSM_DES2 | - lsm == LSM_DES3 | - lsm == LSM_STAT | tsprog) - begin - lastdma <= 1'b1 ; - end - else if (!buffetch) - begin - if (pblz) - begin - if (fl_g_bs | csm == CSM_SET) - begin - lastdma <= 1'b1 ; - end - else - begin - lastdma <= 1'b0 ; - end - end - else - begin - if (fl_g_bl | csm == CSM_SET) - begin - if (bl_g_bs) - begin - lastdma <= 1'b1 ; - end - else - begin - lastdma <= 1'b0 ; - end - end - else - begin - if (fl_g_bs) - begin - lastdma <= 1'b1 ; - end - else - begin - lastdma <= 1'b0 ; - end - end - end - end - end - end - - always @(tsprog or lsm or statadi or bad or dad or statad) - begin : dmaaddro_proc - if (tsprog) - begin - dmaaddro <= statadi ; - end - else - begin - case (lsm) - LSM_BUF1, LSM_BUF2 : - begin - dmaaddro <= bad ; - end - LSM_STAT : - begin - dmaaddro <= statad ; - end - default : - begin - dmaaddro <= dad ; - end - endcase - end - end - - always @(req or - dmaack or - dmaeob or - lsm or - tsprog or - fifoval or - req_r) - begin : req_proc - case (lsm) - LSM_BUF1, LSM_BUF2 : - begin - if (dmaack & dmaeob) - begin - req_c <= 1'b0 ; - end - else if ((fifoval & req_r == 3'b000) | tsprog) - begin - req_c <= 1'b1 ; - end - else - begin - req_c <= req ; - end - end - LSM_DES0, LSM_DES1, LSM_DES2, LSM_DES3, LSM_STAT : - begin - if (dmaack) - begin - req_c <= 1'b0 ; - end - else - begin - req_c <= 1'b1 ; - end - end - default : - begin - if (dmaack) - begin - req_c <= 1'b0 ; - end - else if (tsprog) - begin - req_c <= 1'b1 ; - end - else - begin - req_c <= 1'b0 ; - end - end - endcase - end - - always @(posedge clk) - begin : req_reg_proc - if (rst) - begin - req <= 1'b0 ; - req_r <= {3{1'b0 }}; - dmaack_r <= 1'b0 ; - end - else - begin - req <= req_c ; - req_r[0] <= req; - req_r[1] <= req_r[0]; - req_r[2] <= req_r[1]; - dmaack_r <= dmaack & dmaeob ; - end - end - - assign dmawr = (tsprog | lsm == LSM_STAT) ? 1'b1 : 1'b0 ; - - assign dmareq = req ; - - always @(posedge clk) - begin : stat_reg_proc - if (rst) - begin - des <= 1'b0 ; - fbuf <= 1'b0 ; - stat <= 1'b0 ; - tsprog <= 1'b0 ; - buffetch <= 1'b0 ; - tu <= 1'b0 ; - end - else - begin - if (lsm == LSM_DES0 | - lsm == LSM_DES1 | - lsm == LSM_DES2 | - lsm == LSM_DES3) - begin - des <= 1'b1 ; - end - else - begin - des <= 1'b0 ; - end - - if (lsm == LSM_BUF1 | lsm == LSM_BUF2) - begin - fbuf <= 1'b1 ; - end - else - begin - fbuf <= 1'b0 ; - end - - if (tsprog) - begin - stat <= 1'b1 ; - end - else - begin - stat <= 1'b0 ; - end - - if ((dmaeob & dmaack) | itcomp | tcompack_r) - begin - tsprog <= 1'b0 ; - end - else if (csne & !idmareq & !icachere) - begin - tsprog <= 1'b1 ; - end - - if (dmaack_r) - begin - buffetch <= 1'b0 ; - end - else if (req_r[0] & (lsm == LSM_BUF1 | lsm == LSM_BUF2)) - begin - buffetch <= 1'b1 ; - end - - if (lsm == LSM_IDLE & !own) - begin - tu <= 1'b1 ; - end - else if (own_c) - begin - tu <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : tcompack_reg_proc - if (rst) - begin - tcompack_r <= 1'b0 ; - itcomp <= 1'b0 ; - end - else - begin - tcompack_r <= tcompack ; - - if (tsprog & dmaeob & dmaack) - begin - itcomp <= 1'b1 ; - end - else if (tcompack_r) - begin - itcomp <= 1'b0 ; - end - end - end - - assign tcomp = itcomp ; - - always @(posedge clk) - begin : setp_reg_proc - if (rst) - begin - setp <= 1'b0 ; - end - else - begin - if (csm == CSM_SET) - begin - setp <= 1'b1 ; - end - else - begin - setp <= 1'b0 ; - end - end - end - - always @(posedge clk) - begin : ifaddr_reg_proc - if (rst) - begin - ifaddr <= {ADDRDEPTH{1'b0}} ; - end - else - begin - if (csm == CSM_IDLE) - begin - ifaddr <= {ADDRDEPTH{1'b0}} ; - end - else if (ifwe) - begin - ifaddr <= ifaddr + 1 ; - end - end - end - - always @(posedge clk) - begin : ifwe_reg_proc - if (rst) - begin - ifwe <= 1'b0 ; - end - else - begin - case (DATAWIDTH) - 8 : - begin - if (csm == CSM_SET & - dmaack & - dmaaddr[1:0] == 2'b11 & - lsm == LSM_BUF1) - begin - ifwe <= 1'b1 ; - end - else - begin - ifwe <= 1'b0 ; - end - end - 16 : - begin - if (csm == CSM_SET & - dmaack & - dmaaddr[1] & - lsm == LSM_BUF1) - begin - ifwe <= 1'b1 ; - end - else - begin - ifwe <= 1'b0 ; - end - end - default : - begin - if (csm == CSM_SET & dmaack & - lsm == LSM_BUF1) - begin - ifwe <= 1'b1 ; - end - else - begin - ifwe <= 1'b0 ; - end - end - endcase - end - end - - assign faddr = ifaddr ; - - assign fwe = ifwe ; - - assign fdata = dataimax_r[15:0] ; - - always @(posedge clk) - begin : stop_reg_proc - if (rst) - begin - stop_r <= 1'b1 ; - stopo <= 1'b1 ; - end - else - begin - stop_r <= stopi ; - - if (lsm == LSM_IDLE & stop_r) - begin - stopo <= 1'b1 ; - end - else - begin - stopo <= 1'b0 ; - end - end - end - - assign fzero_max = {FIFODEPTH_MAX{1'b0}} ; - - assign dzero_max = {DATAWIDTH_MAX{1'b0}} ; - - assign bufzero_max = {(DATAWIDTH_MAX * 2 - 9){1'b0}} ; - - assign dmaaddr20 = dmaaddr[2:0] ; - - assign dmadatai_max = {dzero_max[DATAWIDTH_MAX+1:DATAWIDTH], - dmadatai}; - - assign buf_r_max = {bufzero_max[DATAWIDTH_MAX * 2 - 7: - DATAWIDTH * 2 - 8], - buf_r}; - -endmodule - diff --git a/resources/soc/simu/testbench/vmac/ram.vlog b/resources/soc/simu/testbench/vmac/ram.vlog deleted file mode 100644 index 8722327..0000000 --- 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-01234567 -01234567 -89a0cdef -01234567 -89abcdef -01234567 -89abcdef -01234567 -89abcdef -01234567 -89abcdef -01234567 -89abcdef -01234567 -89abcdef -01234567 -89abcdef -01234567 -89abcdef -01234567 -89abcdef -01234567 diff --git a/resources/soc/simu/testbench/vmac/virtual_mac.v b/resources/soc/simu/testbench/vmac/virtual_mac.v deleted file mode 100644 index f913c52..0000000 --- a/resources/soc/simu/testbench/vmac/virtual_mac.v +++ /dev/null @@ -1,406 +0,0 @@ -/*------------------------------------------------------------------------------ --------------------------------------------------------------------------------- -Copyright (c) 2016, Loongson Technology Corporation Limited. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of Loongson Technology Corporation Limited nor the names of -its contributors may be used to endorse or promote products derived from this -software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE -TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --------------------------------------------------------------------------------- -------------------------------------------------------------------------------*/ - -`timescale 1ns/1ps -`define IO_DELAY 2.5 - -module virtual_mac( - hclk, hrst_n, - mtxclk, mtxen, mtxd, mtxerr, - mrxclk, mrxdv, mrxd, mrxerr, - mcoll, mcrs, - mdc, md_io, - gpio); - -input hclk, hrst_n; -input mtxclk; -output [3:0] mtxd; -output mtxen; -output mtxerr; - -input mrxclk; -input [3:0] mrxd; -input mrxdv; -input mrxerr; - -input mcoll; -input mcrs; - -inout md_io; -output mdc; - -input gpio; - -wire md_oe, md_o; -wire mdio = md_oe ? md_o : 1'bz; -wire md_i = mdio; - -wire [1:0] v_htrans; -wire [2:0] v_hburst; -wire [31:0] v_haddr; -wire v_hwrite; -wire [2:0] v_hsize; -wire [31:0] v_hrdata; -wire [31:0] v_hwdata; -wire v_hrdy; -wire [1:0] v_hresp = 2'b0; - -wire m_hreq, m_hlock, m_hgnt; -wire [1:0] m_htrans; -wire [2:0] m_hburst; -wire [31:0] m_haddr; -wire m_hwrite; -wire [2:0] m_hsize; -wire [3:0] m_hprot; -wire [31:0] m_hwdata; - -wire s_hsel, s_hrdy; -wire [1:0] s_hresp; -wire [15:0] s_hsplit; -wire [31:0] s_hrdata; - -wire read_complete; -assign m_hgnt = ~s_hsel; -reg grant_dly; -always @(posedge hclk) - grant_dly <= m_hgnt & m_hreq; - -wire [3:0] mtxd_mid; -wire mtxen_mid; -wire mtxerr_mid; -wire mdc_mid; -assign #`IO_DELAY mtxd = mtxd_mid; -assign #`IO_DELAY mtxen = mtxen_mid; -assign #`IO_DELAY mtxerr = mtxerr_mid; -assign #`IO_DELAY mdc = mdc_mid; -vMAC_TOP virtual_core -( - .hclk(hclk), .hrst_(hrst_n), .SYS_RST_(hrst_n), - - .hmst(4'b1), .hmstlock(1'b0), - .htrans(v_htrans), .hburst(v_hburst), .haddr(v_haddr), - .hwrite(v_hwrite), .hsize(v_hsize), - .hrdata(v_hrdata), .hwdata(v_hwdata), .hrdy(v_hrdy), .hresp(v_hresp), - .eth_hreq(m_hreq), .eth_hlock(m_hlock), .eth_hgnt(m_hgnt), - .eth_htrans(m_htrans), .eth_hburst(m_hburst), .eth_haddr(m_haddr), - .eth_hwrite(m_hwrite), .eth_hsize(m_hsize), .eth_hprot(m_hprot), - .eth_hwdata(m_hwdata), - .eth_hsel(s_hsel), .eth_hrdy(s_hrdy), .eth_hresp(s_hresp), .eth_hsplit(s_hsplit), - .eth_hrdata(s_hrdata), - - .interrupt(), - .mtxclk(mtxclk), .mtxen(mtxen_mid), .mtxd(mtxd_mid), .mtxerr(mtxerr_mid), - .mrxclk(mrxclk), .mrxdv(mrxdv), .mrxd(mrxd), .mrxerr(mrxerr), - .mcoll(mcoll), .mcrs(mcrs), - .mdc(mdc_mid), .md_i(md_i), .md_o(md_o), .md_oe(md_oe), - - .bist_mode(1'b0) - ); - -virtual_mac_slave virtual_mac_slave_0( - .hclk(hclk), .hrst_n(hrst_n), - .hreq(m_hreq), .hlock(m_hlock), .hgnt(m_hgnt), .hrdy(v_hrdy), - .htrans(m_htrans), .hburst(m_hburst), .haddr(m_haddr), .hrdata(v_hrdata), - .hwrite(m_hwrite), .hsize(m_hsize), .hprot(m_hprot), .hwdata(m_hwdata), .read_complete(read_complete)); - -virtual_mac_master virtual_mac_master_0( - .hclk(hclk), .hrst_n(hrst_n), .grant_dly(grant_dly), - .hsel(s_hsel), .htrans(v_htrans), .hburst(v_hburst), .hsize(v_hsize), .hrdy(s_hrdy), - .hwrite(v_hwrite), .hrdata(s_hrdata), .hwdata(v_hwdata), .haddr(v_haddr), .hprot(), .read_complete(read_complete), - .gpio(gpio)); -endmodule - -module virtual_mac_slave( - hclk, hrst_n, - hreq, hlock, hgnt, hrdy, - htrans, hburst, haddr, hrdata, - hwrite, hsize, hprot, hwdata, read_complete); -input hclk, hrst_n; -input hreq, hlock, hgnt; -input [1:0] htrans; -input [2:0] hburst; -input [31:0] haddr; -output[31:0] hrdata; -input hwrite; -input [2:0] hsize; -input [3:0] hprot; -input [31:0] hwdata; -output hrdy; -input read_complete; - -wire hrdy = 1'b1; -wire s_command = (htrans[1] == 1'b1) & hrdy; - - -reg [31:0] MEM_in[1048575:0]; -reg [31:0] MEM_out[1048575:0]; -reg reg_enable; -wire s_end = hrdy & reg_enable; -always @(posedge hclk) - if (~hrst_n) - reg_enable <= 1'b0; - else if (s_command) - reg_enable <= 1'b1; - else if (s_end) - reg_enable <= 1'b0; - -reg reg_we; -always @(posedge hclk) - if (~hrst_n) - reg_we <= 1'b0; - else if (s_command) - reg_we <= hwrite; - else if (s_end) - reg_we <= 1'b0; - -reg [31:0] reg_addr; -always @(posedge hclk) - if (~hrst_n) - reg_addr <= 31'b0; - else if (s_command) - reg_addr <= {2'b00,haddr[31:2]}; - -integer i; -`ifdef VIRTUAL_MAC -initial -begin - for (i = 0 ;i <1048576; i = i+1) MEM_out[i] = 32'b0; - #100; - $readmemh("../../testbench/vmac/ram.vlog", MEM_out); - $display("[%t]:)[virtual_mac]:reading ../../testbench/vmac/ram.vlog",$time); - $display("DEBUG: MEM_out[32'h1040]=%h, MEM_out[32'h840]=%h", MEM_out[32'h1040], MEM_out[32'h840]); -end -`endif - -initial -begin - @(posedge read_complete); - for (i= 0; i < 32'h40; i= i+1) - if (MEM_out[i+32'h800] != MEM_out[i+32'h1000]) - $display("[%t]:[virtual_mac]:error data, MEM_out[%h] = %h, correct is %h",$time, i, MEM_out[i+32'h1000], MEM_out[i+32'h800]); - else - $display("data, MEM_out[%h] = %h", i, MEM_out[i+32'h1000]); -`ifdef MAC_DEBUG - $display("[%t]:[virtual_mac]:valuation complete",$time); -`endif -end - -reg flag; -initial - begin - flag = 1'b0; - end - -always @(posedge hclk) - if (hrst_n & reg_we & s_end) - begin - MEM_out[reg_addr] <= hwdata; - if (reg_addr==32'h1040) flag = 1'b1; - end - -assign hrdata = (reg_addr == 32'h400 |reg_addr == 32'h420)? 32'h80000000: MEM_out[reg_addr]; - -endmodule - -module virtual_mac_master( - hclk, hrst_n, grant_dly, - hsel, htrans, hburst, hsize, hrdy, - hwrite, hrdata, hwdata, haddr, hprot, read_complete, - gpio); -input hclk, hrst_n; -input grant_dly; -output hsel; -output [1:0] htrans; -output [2:0] hburst; -output [2:0] hsize; -input hrdy; -output hwrite; -input [31:0] hrdata; -output [31:0] hwdata; -output [31:0] haddr; -output [3:0] hprot; -output read_complete; -input gpio; - -reg ready; -reg hsel; -reg [1:0] htrans; -reg [2:0] hburst; -reg [2:0] hsize; -reg hwrite; -reg [31:0] hwdata; -reg [31:0] haddr; -reg [3:0] hprot; - -reg read_complete; - -`ifdef MAC_DEBUG -wire debug = 1; -`else -wire debug = 0; -`endif - -initial begin - -htrans = 2'b00; -haddr = 2'b00; -hburst = 3'b00; -hwrite = 1'b0; -hsize = 3'b000; -hwdata = 32'b0; -hsel = 1'b0; -hprot = 4'b0; - -read_complete = 1'b0; - -ready = 1'b0; - -`ifdef VIRTUAL_MAC -@(posedge hrst_n); - -wait(gpio); - -@(posedge hclk) - -if (debug) $display("[%t]:[virtual_mac]:start transmit process ",$time); -while (grant_dly) @(posedge hclk); -one_write(32'h00,32'h0000, 2); - -while (grant_dly) @(posedge hclk); -one_write(32'h20,32'h1000, 2); - -while (grant_dly) @(posedge hclk); -one_write(32'h18,32'h1100, 2); - -while (grant_dly) @(posedge hclk); -one_write(32'h30,32'h40002002, 2); - -@(posedge hclk) - -while (grant_dly) @(posedge hclk); -one_read(32'h28,2); -while (hrdata[6]==0) -begin - while (grant_dly) @(posedge hclk); - one_read(32'h28,2); - repeat(10)@(posedge hclk); - #3; -end -read_complete = 1'b1; - -if (debug) $display("[%t]:[virtual_mac]:receive process complete",$time); - -`endif -end - - -task one_write; -input [11:0] addr; -input [31:0] wdata; -input [2:0] size; -begin -if (debug) $display("[%t]:[virtual_mac]: write address phase begin: haddr = %x",$time, addr); -htrans = 2'b10; -haddr = addr; -hburst = 3'b00; -hwrite = 1'b1; -hsize = size; -hsel = 1'b1; -ready = 1'b0; - -@(posedge hclk); - if( hrdy == 1'b1) ready = 1'b1; -while (ready != 1'b1) -begin - @(posedge hclk); - if( hrdy == 1'b1) ready = 1'b1; - #3; -end -ready = 1'b0; - -if (debug) $display("[%t]:[virtual_mac]: write data phase begin: haddr = %x", $time, addr); - -hwdata = wdata; -hsel = 1'b0; -htrans = 2'b00; -@(posedge hclk); - if( hrdy == 1'b1) ready = 1'b1; -while (ready != 1'b1) -begin - @(posedge hclk); - if( hrdy == 1'b1) ready = 1'b1; - #3; -end -ready = 1'b0; - -if (debug) $display("[%t]:[virtual_mac]: write complete!!!", $time); -end -endtask - -task one_read; -input [11:0] addr; -input [2:0] size; -begin -htrans = 2'b10; -haddr = addr; -hburst = 3'b00; -hwrite = 1'b0; -hsize = size; -hsel = 1'b1; - - -@(posedge hclk); - if( hrdy == 1'b1) ready = 1'b1; -while (ready != 1'b1) -begin - @(posedge hclk); - if( hrdy == 1'b1) ready = 1'b1; - #3; -end -ready = 1'b0; - -htrans = 2'b00; - -hsel = 1'b0; -@(posedge hclk); - if( hrdy == 1'b1) ready = 1'b1; -while (ready != 1'b1) -begin - @(posedge hclk); - if( hrdy == 1'b1) ready = 1'b1; -end -ready = 1'b0; -end -endtask - -endmodule diff --git a/resources/soc/vivado_xpr/project_1/project_1/project_1.xpr b/resources/soc/vivado_xpr/project_1/project_1/project_1.xpr deleted file mode 100644 index cea8981..0000000 --- a/resources/soc/vivado_xpr/project_1/project_1/project_1.xpr +++ /dev/null @@ -1,1154 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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false - false - false - false - false - false - false - false - Use_ENA_Pin - Always_Enabled - Single_Bit_Error_Injection - false - Native - false - no_mem_loaded - Single_Port_RAM - WRITE_FIRST - WRITE_FIRST - 0 - 0 - BRAM - 0 - 100 - 100 - 50 - 0 - 0 - 0 - 8kx2 - false - false - 1 - 1 - 32 - 32 - false - false - false - false - 0 - false - false - CE - CE - SYNC - false - false - false - false - false - false - false - 128 - 32 - 32 - No_ECC - false - false - false - Stand_Alone - artix7 - - - xc7a200t - fbg676 - VERILOG - - MIXED - -2 - - - TRUE - TRUE - IP_Flow - 4 - TRUE - . - - . - 2019.2 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/resources/soc/vivado_xpr/project_1/xilinx_ip/sram_128x64/sram_128x64.xci b/resources/soc/vivado_xpr/project_1/xilinx_ip/sram_128x64/sram_128x64.xci deleted file mode 100644 index 200b408..0000000 --- a/resources/soc/vivado_xpr/project_1/xilinx_ip/sram_128x64/sram_128x64.xci +++ /dev/null @@ -1,311 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - sram_128x64 - - - 4096 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - OTHER - NONE - 8192 - 32 - 1 - - OTHER - NONE - 8192 - 32 - 1 - - - 100000000 - 0 - 0.000 - 0 - 7 - 7 - 1 - 4 - 0 - 1 - 8 - 0 - 0 - 1 - NONE - 0 - 0 - 0 - ./ - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Estimated Power for IP : 6.700549 mW - artix7 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - sram_128x64.mem - no_coe_file_loaded - 0 - 0 - 0 - 0 - 1 - 128 - 128 - 1 - 1 - 64 - 64 - 0 - 0 - CE - CE - ALL - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 8 - 8 - 128 - 128 - WRITE_FIRST - WRITE_FIRST - 64 - 64 - artix7 - 4 - Memory_Slave - AXI4_Full - false - Minimum_Area - false - 8 - NONE - no_coe_file_loaded - ALL - sram_128x64 - false - false - false - false - false - false - false - false - false - Use_ENA_Pin - Always_Enabled - Single_Bit_Error_Injection - false - Native - false - no_mem_loaded - Single_Port_RAM - WRITE_FIRST - WRITE_FIRST - 0 - 0 - BRAM - 0 - 100 - 100 - 50 - 0 - 0 - 0 - 8kx2 - false - false - 1 - 1 - 64 - 64 - false - false - false - false - 0 - false - false - CE - CE - SYNC - false - true - false - false - false - false - false - 128 - 64 - 64 - No_ECC - false - false - false - Stand_Alone - artix7 - - - xc7a200t - fbg676 - VERILOG - - MIXED - -2 - - - TRUE - TRUE - IP_Flow - 4 - TRUE - . - - . - 2019.2 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/resources/soc/vivado_xpr/project_1/xilinx_ip/sram_32x52bit/sram_32x52bit.xci b/resources/soc/vivado_xpr/project_1/xilinx_ip/sram_32x52bit/sram_32x52bit.xci deleted file mode 100644 index 9bd5d2e..0000000 --- a/resources/soc/vivado_xpr/project_1/xilinx_ip/sram_32x52bit/sram_32x52bit.xci +++ /dev/null @@ -1,309 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - sram_32x52bit - - - 4096 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - OTHER - NONE - 8192 - 32 - 1 - - OTHER - NONE - 8192 - 32 - 1 - - - 100000000 - 0 - 0.000 - 0 - 5 - 5 - 1 - 4 - 0 - 1 - 9 - 0 - 0 - 1 - NONE - 0 - 0 - 0 - ./ - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Estimated Power for IP : 6.27815 mW - artix7 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - sram_32x52bit.mem - no_coe_file_loaded - 0 - 0 - 0 - 0 - 1 - 32 - 32 - 1 - 1 - 52 - 52 - 0 - 0 - CE - CE - ALL - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 32 - 32 - WRITE_FIRST - WRITE_FIRST - 52 - 52 - artix7 - 4 - Memory_Slave - AXI4_Full - false - Minimum_Area - false - 9 - NONE - no_coe_file_loaded - ALL - sram_32x52bit - false - false - false - false - false - false - false - false - false - Use_ENA_Pin - Always_Enabled - Single_Bit_Error_Injection - false - Native - false - no_mem_loaded - Single_Port_RAM - WRITE_FIRST - WRITE_FIRST - 0 - 0 - BRAM - 0 - 100 - 100 - 50 - 0 - 0 - 0 - 8kx2 - false - false - 1 - 1 - 52 - 52 - false - false - false - false - 0 - false - false - CE - CE - SYNC - false - false - false - false - false - false - false - 32 - 52 - 52 - No_ECC - false - false - false - Stand_Alone - artix7 - - - xc7a200t - fbg676 - VERILOG - - MIXED - -2 - - - TRUE - TRUE - IP_Flow - 4 - TRUE - . - - . - 2019.2 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/resources/soc/vivado_xpr/soc_up.xdc b/resources/soc/vivado_xpr/soc_up.xdc deleted file mode 100644 index d4e156e..0000000 --- a/resources/soc/vivado_xpr/soc_up.xdc +++ /dev/null @@ -1,200 +0,0 @@ -#set_property SEVERITY {Warning} [get_drc_checks RTSTAT-2] -#时钟信号连接 -#create_clock -period 10.000 [get_ports clk] -set_property PACKAGE_PIN AC19 [get_ports clk] -set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk] -create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk] - -#reset -set_property PACKAGE_PIN Y3 [get_ports resetn] - -#LED -set_property PACKAGE_PIN K23 [get_ports {led[0]}] -set_property PACKAGE_PIN J21 [get_ports {led[1]}] -set_property PACKAGE_PIN H23 [get_ports {led[2]}] -set_property PACKAGE_PIN J19 [get_ports {led[3]}] -set_property PACKAGE_PIN G9 [get_ports {led[4]}] -set_property PACKAGE_PIN J26 [get_ports {led[5]}] -set_property PACKAGE_PIN J23 [get_ports {led[6]}] -set_property PACKAGE_PIN J8 [get_ports {led[7]}] -set_property PACKAGE_PIN H8 [get_ports {led[8]}] -set_property PACKAGE_PIN G8 [get_ports {led[9]}] -set_property PACKAGE_PIN F7 [get_ports {led[10]}] -set_property PACKAGE_PIN A4 [get_ports {led[11]}] -set_property PACKAGE_PIN A5 [get_ports {led[12]}] -set_property PACKAGE_PIN A3 [get_ports {led[13]}] -set_property PACKAGE_PIN D5 [get_ports {led[14]}] -set_property PACKAGE_PIN H7 [get_ports {led[15]}] - -#led_rg 0/1 -set_property PACKAGE_PIN G7 [get_ports {led_rg0[0]}] -set_property PACKAGE_PIN F8 [get_ports {led_rg0[1]}] -set_property PACKAGE_PIN B5 [get_ports {led_rg1[0]}] -set_property PACKAGE_PIN D6 [get_ports {led_rg1[1]}] - -#NUM -set_property PACKAGE_PIN D3 [get_ports {num_csn[7]}] -set_property PACKAGE_PIN D25 [get_ports {num_csn[6]}] -set_property PACKAGE_PIN D26 [get_ports {num_csn[5]}] -set_property PACKAGE_PIN E25 [get_ports {num_csn[4]}] -set_property PACKAGE_PIN E26 [get_ports {num_csn[3]}] -set_property PACKAGE_PIN G25 [get_ports {num_csn[2]}] -set_property PACKAGE_PIN G26 [get_ports {num_csn[1]}] -set_property PACKAGE_PIN H26 [get_ports {num_csn[0]}] - -set_property PACKAGE_PIN C3 [get_ports {num_a_g[0]}] -set_property PACKAGE_PIN E6 [get_ports {num_a_g[1]}] -set_property PACKAGE_PIN B2 [get_ports {num_a_g[2]}] -set_property PACKAGE_PIN B4 [get_ports {num_a_g[3]}] -set_property PACKAGE_PIN E5 [get_ports {num_a_g[4]}] -set_property PACKAGE_PIN D4 [get_ports {num_a_g[5]}] -set_property PACKAGE_PIN A2 [get_ports {num_a_g[6]}] -#set_property PACKAGE_PIN C4 :DP - -#switch -set_property PACKAGE_PIN AC21 [get_ports {switch[7]}] -set_property PACKAGE_PIN AD24 [get_ports {switch[6]}] -set_property PACKAGE_PIN AC22 [get_ports {switch[5]}] -set_property PACKAGE_PIN AC23 [get_ports {switch[4]}] -set_property PACKAGE_PIN AB6 [get_ports {switch[3]}] -set_property PACKAGE_PIN W6 [get_ports {switch[2]}] -set_property PACKAGE_PIN AA7 [get_ports {switch[1]}] -set_property PACKAGE_PIN Y6 [get_ports {switch[0]}] - -#btn_key -set_property PACKAGE_PIN V8 [get_ports {btn_key_col[0]}] -set_property PACKAGE_PIN V9 [get_ports {btn_key_col[1]}] -set_property PACKAGE_PIN Y8 [get_ports {btn_key_col[2]}] -set_property PACKAGE_PIN V7 [get_ports {btn_key_col[3]}] -set_property PACKAGE_PIN U7 [get_ports {btn_key_row[0]}] -set_property PACKAGE_PIN W8 [get_ports {btn_key_row[1]}] -set_property PACKAGE_PIN Y7 [get_ports {btn_key_row[2]}] -set_property PACKAGE_PIN AA8 [get_ports {btn_key_row[3]}] - -#btn_step -set_property PACKAGE_PIN Y5 [get_ports btn_step[0]] -set_property PACKAGE_PIN V6 [get_ports btn_step[1]] - -#SPI flash -set_property PACKAGE_PIN P20 [get_ports SPI_CLK] -set_property PACKAGE_PIN R20 [get_ports SPI_CS] -set_property PACKAGE_PIN P19 [get_ports SPI_MISO] -set_property PACKAGE_PIN N18 [get_ports SPI_MOSI] - -#mac phy connect -set_property PACKAGE_PIN AB21 [get_ports mtxclk_0] -set_property PACKAGE_PIN AA19 [get_ports mrxclk_0] -set_property PACKAGE_PIN AA15 [get_ports mtxen_0] -set_property PACKAGE_PIN AF18 [get_ports {mtxd_0[0]}] -set_property PACKAGE_PIN AE18 [get_ports {mtxd_0[1]}] -set_property PACKAGE_PIN W15 [get_ports {mtxd_0[2]}] -set_property PACKAGE_PIN W14 [get_ports {mtxd_0[3]}] -set_property PACKAGE_PIN AB20 [get_ports mtxerr_0] -set_property PACKAGE_PIN AE22 [get_ports mrxdv_0] -set_property PACKAGE_PIN V1 [get_ports {mrxd_0[0]}] -set_property PACKAGE_PIN V4 [get_ports {mrxd_0[1]}] -set_property PACKAGE_PIN V2 [get_ports {mrxd_0[2]}] -set_property PACKAGE_PIN V3 [get_ports {mrxd_0[3]}] -set_property PACKAGE_PIN W16 [get_ports mrxerr_0] -set_property PACKAGE_PIN Y15 [get_ports mcoll_0] -set_property PACKAGE_PIN AF20 [get_ports mcrs_0] -set_property PACKAGE_PIN W3 [get_ports mdc_0] -set_property PACKAGE_PIN W1 [get_ports mdio_0] -set_property PACKAGE_PIN AE26 [get_ports phy_rstn] - -#uart -set_property PACKAGE_PIN F23 [get_ports UART_RX] -set_property IOSTANDARD LVCMOS33 [get_ports UART_RX] -set_property PACKAGE_PIN H19 [get_ports UART_TX] -set_property IOSTANDARD LVCMOS33 [get_ports UART_TX] - -#nand flash -set_property PACKAGE_PIN V19 [get_ports NAND_CLE] -set_property PACKAGE_PIN W20 [get_ports NAND_ALE] -set_property PACKAGE_PIN AA25 [get_ports NAND_RDY] -set_property PACKAGE_PIN AA24 [get_ports NAND_RD] -set_property PACKAGE_PIN AB24 [get_ports NAND_CE] -set_property PACKAGE_PIN AA22 [get_ports NAND_WR] -set_property PACKAGE_PIN W19 [get_ports {NAND_DATA[7]}] -set_property PACKAGE_PIN Y20 [get_ports {NAND_DATA[6]}] -set_property PACKAGE_PIN Y21 [get_ports {NAND_DATA[5]}] -set_property PACKAGE_PIN V18 [get_ports {NAND_DATA[4]}] -set_property PACKAGE_PIN U19 [get_ports {NAND_DATA[3]}] -set_property PACKAGE_PIN U20 [get_ports {NAND_DATA[2]}] -set_property PACKAGE_PIN W21 [get_ports {NAND_DATA[1]}] -set_property PACKAGE_PIN AC24 [get_ports {NAND_DATA[0]}] - -#ejtag -# set_property PACKAGE_PIN J18 [get_ports EJTAG_TRST] -# set_property PACKAGE_PIN K18 [get_ports EJTAG_TCK] -# set_property PACKAGE_PIN K20 [get_ports EJTAG_TDI] -# set_property PACKAGE_PIN K22 [get_ports EJTAG_TMS] -# set_property PACKAGE_PIN K21 [get_ports EJTAG_TDO] - - -set_property IOSTANDARD LVCMOS33 [get_ports clk] -set_property IOSTANDARD LVCMOS33 [get_ports resetn] -set_property IOSTANDARD LVCMOS33 [get_ports {led[*]}] -set_property IOSTANDARD LVCMOS33 [get_ports {led_rg0[*]}] -set_property IOSTANDARD LVCMOS33 [get_ports {led_rg1[*]}] -set_property IOSTANDARD LVCMOS33 [get_ports {num_a_g[*]}] -set_property IOSTANDARD LVCMOS33 [get_ports {num_csn[*]}] -set_property IOSTANDARD LVCMOS33 [get_ports {switch[*]}] -set_property IOSTANDARD LVCMOS33 [get_ports {btn_key_col[*]}] -set_property IOSTANDARD LVCMOS33 [get_ports {btn_key_row[*]}] -set_property IOSTANDARD LVCMOS33 [get_ports {btn_step[*]}] - -set_property IOSTANDARD LVCMOS33 [get_ports SPI_MOSI] -set_property IOSTANDARD LVCMOS33 [get_ports SPI_MISO] -set_property IOSTANDARD LVCMOS33 [get_ports SPI_CS] -set_property IOSTANDARD LVCMOS33 [get_ports SPI_CLK] - -set_property IOSTANDARD LVCMOS33 [get_ports {mrxd_0[*]}] -set_property IOSTANDARD LVCMOS33 [get_ports {mtxd_0[*]}] -set_property IOSTANDARD LVCMOS33 [get_ports phy_rstn] -set_property IOSTANDARD LVCMOS33 [get_ports mtxerr_0] -set_property IOSTANDARD LVCMOS33 [get_ports mtxen_0] -set_property IOSTANDARD LVCMOS33 [get_ports mtxclk_0] -set_property IOSTANDARD LVCMOS33 [get_ports mrxerr_0] -set_property IOSTANDARD LVCMOS33 [get_ports mcoll_0] -set_property IOSTANDARD LVCMOS33 [get_ports mcrs_0] -set_property IOSTANDARD LVCMOS33 [get_ports mdc_0] -set_property IOSTANDARD LVCMOS33 [get_ports mdio_0] -set_property IOSTANDARD LVCMOS33 [get_ports mrxclk_0] -set_property IOSTANDARD LVCMOS33 [get_ports mrxdv_0] - -set_property IOSTANDARD LVCMOS33 [get_ports NAND_CLE] -set_property IOSTANDARD LVCMOS33 [get_ports NAND_ALE] -set_property IOSTANDARD LVCMOS33 [get_ports NAND_RDY] -set_property IOSTANDARD LVCMOS33 [get_ports NAND_RD] -set_property IOSTANDARD LVCMOS33 [get_ports NAND_CE] -set_property IOSTANDARD LVCMOS33 [get_ports NAND_WR] -set_property IOSTANDARD LVCMOS33 [get_ports {NAND_DATA[7]}] -set_property IOSTANDARD LVCMOS33 [get_ports {NAND_DATA[6]}] -set_property IOSTANDARD LVCMOS33 [get_ports {NAND_DATA[5]}] -set_property IOSTANDARD LVCMOS33 [get_ports {NAND_DATA[4]}] -set_property IOSTANDARD LVCMOS33 [get_ports {NAND_DATA[3]}] -set_property IOSTANDARD LVCMOS33 [get_ports {NAND_DATA[2]}] -set_property IOSTANDARD LVCMOS33 [get_ports {NAND_DATA[1]}] -set_property IOSTANDARD LVCMOS33 [get_ports {NAND_DATA[0]}] - -# set_property IOSTANDARD LVCMOS33 [get_ports EJTAG_TRST] -# set_property IOSTANDARD LVCMOS33 [get_ports EJTAG_TCK] -# set_property IOSTANDARD LVCMOS33 [get_ports EJTAG_TDI] -# set_property IOSTANDARD LVCMOS33 [get_ports EJTAG_TMS] -# set_property IOSTANDARD LVCMOS33 [get_ports EJTAG_TDO] -# set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets EJTAG_TCK_IBUF] - -create_clock -period 40.000 -name mrxclk_0 -waveform {0.000 20.000} [get_ports mrxclk_0] -create_clock -period 40.000 -name mtxclk_0 -waveform {0.000 20.000} [get_ports mtxclk_0] - -set_false_path -from [get_clocks clk_pll_i] -to [get_clocks clk_out1_clk_pll_33] -set_false_path -from [get_clocks mrxclk_0] -to [get_clocks clk_out1_clk_pll_33] -set_false_path -from [get_clocks mtxclk_0] -to [get_clocks clk_out1_clk_pll_33] -set_false_path -from [get_clocks clk_out1_clk_pll_33] -to [get_clocks mrxclk_0] -set_false_path -from [get_clocks clk_out1_clk_pll_33] -to [get_clocks mrxclk_0] -set_false_path -from [get_clocks clk_out1_clk_pll_33] -to [get_clocks mtxclk_0] -set_false_path -from [get_clocks clk_out1_clk_pll_33] -to [get_clocks mtxclk_0] - -set_false_path -from [get_clocks -of_objects [get_pins mig_axi/u_mig_axi_32_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT]] -to [get_clocks -of_objects [get_pins clk_pll_33/inst/plle2_adv_inst/CLKOUT0]] -set_false_path -from [get_clocks -of_objects [get_pins clk_pll_33/inst/plle2_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins mig_axi/u_mig_axi_32_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT]] diff --git a/resources/tft-lcd/LCD.sv b/resources/tft-lcd/LCD.sv deleted file mode 100644 index 05ed4d6..0000000 --- a/resources/tft-lcd/LCD.sv +++ /dev/null @@ -1,28 +0,0 @@ -module LCD ( - input logic clk, - input logic rst, - - // TFT-LCD - output logic CS, // 片选 低有效 - output logic RS, // 0命令 1数据 - output logic WR, // 写使能 低有效 - output logic RD, // 读使能 低有效 - output logic RSTN, // 复位 低有效 - inout logic [15:0] DATA, // 双向数据总线 - output logic BL_CTR, // 背光控制引脚 高点亮, 低关闭 - inout logic SDA , // I2C SDA - input logic PEN, // 触摸中断 - output logic CT_RST, // 触摸屏复位 - output logic SCL, // I2C SCL - - // CPU - output logic intr // To CPU中断信号 -); - // 复位同步 - assign RSTN = ~rst; - assign CT_RST = ~rst; - // 点亮背光 - assign BL_CTR = 1'b1; - - -endmodule \ No newline at end of file diff --git a/sim/.gitignore b/sim/.gitignore deleted file mode 100644 index 9b2e351..0000000 --- a/sim/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -logs -obj_dir \ No newline at end of file diff --git a/sim/Makefile b/sim/Makefile deleted file mode 100644 index 3d3c773..0000000 --- a/sim/Makefile +++ /dev/null @@ -1,60 +0,0 @@ -GENHTML = genhtml - -VERILATOR = verilator -VERILATOR_COVERAGE = verilator_coverage - -VERILATOR_FLAGS = -# Generate C++ in executable form -VERILATOR_FLAGS += -cc --exe -# Generate makefile dependencies (not shown as complicates the Makefile) -VERILATOR_FLAGS += -MMD -# Optimize -VERILATOR_FLAGS += -Os -x-assign 0 -# Warn abount lint issues; may not want this on less solid designs -VERILATOR_FLAGS += -Wall -# Make waveforms -VERILATOR_FLAGS += --trace -# Check SystemVerilog assertions -VERILATOR_FLAGS += --assert -# Generate coverage analysis -VERILATOR_FLAGS += --coverage -# Run make to compile model, with as many CPUs as are free -VERILATOR_FLAGS += --build -j - -# Get rid of annoying warnings -VERILATOR_FLAGS += -Wno-UNOPT -Wno-UNOPTFLAT -Wno-BLKSEQ -VERILATOR_FLAGS += -DSIMULATION_PC - -# Create annotated source -VERILATOR_COV_FLAGS += --annotate logs/annotated -# A single coverage hit is considered good enough -VERILATOR_COV_FLAGS += --annotate-min 1 -# Create LCOV info -VERILATOR_COV_FLAGS += --write-info logs/coverage.info -# Input file from Verilator -VERILATOR_COV_FLAGS += logs/coverage.dat - -SOURCE = $(wildcard ../model/*.v ../model/*.sv ../src/*.v ../src/*.sv ../src/**/*.v ../src/**/*.sv) -INCLUDE = $(addprefix -I, $(dir $(wildcard ../src/*/. ../src/**/*/.))) -# Input files for Verilator -VERILATOR_INPUT = $(INCLUDE) $(SOURCE) -top mycpu_top sim_main.cpp - -default: run - -test: - echo $(INCLUDE) - -verilate: - $(VERILATOR) $(VERILATOR_FLAGS) $(VERILATOR_INPUT) - -run: verilate - @rm -rf logs - @mkdir -p logs - obj_dir/Vmycpu_top - -coverage: verilate - @rm -rf logs/annotated - $(VERILATOR_COVERAGE) $(VERILATOR_COV_FLAGS) - -clean: - -rm -rf obj_dir logs *.log *.dmp *.vpd core \ No newline at end of file diff --git a/sim/sim_main.cpp b/sim/sim_main.cpp deleted file mode 100644 index f02506a..0000000 --- a/sim/sim_main.cpp +++ /dev/null @@ -1,47 +0,0 @@ -#include - -#include "Vmycpu_top.h" - -vluint64_t main_time = 0; -double sc_time_stamp() { - return main_time; // Note does conversion to real, to match SystemC -} - -int main(int argc, char** argv, char** env) { - if (0 && argc && argv && env) {} - - Verilated::debug(0); - Verilated::randReset(2); - Verilated::traceEverOn(true); - Verilated::commandArgs(argc, argv); - Verilated::mkdir("logs"); - - Vmycpu_top* top = new Vmycpu_top; // Or use a const unique_ptr, or the VL_UNIQUE_PTR wrapper - - top->aclk = 0; - while (!Verilated::gotFinish()) { - ++main_time; - top->aclk = !top->aclk; - top->aresetn = (main_time < 10) ? 1 : 0; - if (main_time < 5) { - // Zero coverage if still early in reset, otherwise toggles there may - // falsely indicate a signal is covered - VerilatedCov::zero(); - } - top->eval(); - - // TODO: fake AXI - } - - top->final(); - - // Coverage analysis (since test passed) -#if VM_COVERAGE - Verilated::mkdir("logs"); - VerilatedCov::write("logs/coverage.dat"); -#endif - - delete top; - top = NULL; - exit(0); -} \ No newline at end of file