fix5
This commit is contained in:
parent
c487401438
commit
a0a6e4c2f2
@ -26,22 +26,6 @@ module CP0 (
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rf_cp0 = {504'b0, 8'b10000010, 105'b0, 1'b1, 406'b0};
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count_lo = 0;
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end else if (clk) begin
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if (exception.ERET) rf_cp0.Status.EXL = 1'b0;
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else begin
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if (exception.ExcValid && rf_cp0.Status.EXL == 1'b0) begin
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rf_cp0.Cause.ExcCode = exception.ExcCode;
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if (exception.ExcCode == 4 || exception.ExcCode == 5)
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rf_cp0.BadVAddr = exception.BadVAddr;
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rf_cp0.Status.EXL = 1'b1;
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if (~rf_cp0.Status.EXL) begin
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rf_cp0.EPC = exception.EPC;
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if (exception.delay) begin
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rf_cp0.Cause.BD = 1'b1;
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rf_cp0.EPC = rf_cp0.EPC - 4;
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end else rf_cp0.Cause.BD = 1'b0;
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end
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end
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end
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// count
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count_lo = count_lo + 1;
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if (count_lo == 1) rf_cp0.Count = rf_cp0.Count + 1;
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@ -86,6 +70,19 @@ module CP0 (
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default: begin
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end
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endcase
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if (exception.ERET) rf_cp0.Status.EXL = 1'b0;
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else begin
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if (exception.ExcValid && rf_cp0.Status.EXL == 1'b0) begin
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rf_cp0.Cause.ExcCode = exception.ExcCode;
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if (exception.ExcCode == 4 || exception.ExcCode == 5)
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rf_cp0.BadVAddr = exception.BadVAddr;
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rf_cp0.EPC = exception.EPC;
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if (exception.delay) rf_cp0.EPC = rf_cp0.EPC - 4;
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rf_cp0.Cause.BD = exception.delay;
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rf_cp0.Status.EXL = 1'b1;
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end
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end
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end
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always_comb
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case (addr)
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@ -12,7 +12,7 @@ module Controller (
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inst[15:11],
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5'b11111,
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ctrl.RT,
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{inst[31] | inst[29], inst[26]},
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{inst[31] | inst[30] & ~inst[26] | inst[29], inst[26]},
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ctrl.RD
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);
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@ -46,7 +46,6 @@ module Datapath (
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// Pre Fetch
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logic PF_go;
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logic PF_req;
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word_t PF_pcp8;
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word_t PF_pcb;
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@ -159,6 +158,8 @@ module Datapath (
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// Memory
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logic M_go;
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EXCEPTION_t M_exception;
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logic [ 7:0] M_I1_Byte;
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logic [15:0] M_I1_Half;
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word_t M_I1_ByteX;
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@ -178,6 +179,9 @@ module Datapath (
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logic M_I0_FT_W_I1;
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word_t M_I0_ForwardT;
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logic M_I1_RData_OK;
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word_t M_I1_RData;
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word_t HI;
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word_t LO;
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@ -203,22 +207,22 @@ module Datapath (
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`PCEXC,
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C0_EPC,
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`PCRST,
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{~F_valid, C0_exception.ExcValid, ~D_IA_valid},
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{~F_valid, M_exception.ERET, M_exception.ExcValid, ~D_IA_valid},
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PF.pc
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);
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assign rstD = D.IA.PFCtrl.PCS != PCP8 & D_IA_can_dispatch;
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assign rstM = C0_exception.ExcValid;
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assign PF_req = ~D.IA_ExcValid & ~D.IB_ExcValid & ~E.I0.ExcValid & ~E.I1.ExcValid;
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assign PF_go = PF.pc[1:0] == 2'b00 & PF_req;
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assign fetch_i.req = rst | C0_exception.ERET | C0_exception.ExcValid | ~D_IA_valid
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assign PF_go = ~D.IA_ExcValid & ~D.IB_ExcValid & ~E.I0.ExcValid & ~E.I1.ExcValid & PF.pc[1:0] == 2'b00;
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assign fetch_i.req = rst | M_exception.ExcValid | ~D_IA_valid
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| PF_go & (~D.IA.PFCtrl.BJRJ | D_IA_can_dispatch)
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& ( ~IQ_valids[3]
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| ~IQ_valids[2] & (PF.pc[2] | F.pc[2] | D_readygo | D_readygo1)
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| ~IQ_valids[1] & (PF.pc[2] & (F.pc[2] | D_readygo | D_readygo1) | F.pc[2] & (D_readygo | D_readygo1) | D_readygo & D_readygo1)
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| ~IQ_valids[0] & (PF.pc[2] & (F.pc[2] & (D_readygo | D_readygo1) | D_readygo & D_readygo1) | F.pc[2] & D_readygo & D_readygo1)
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| IQ_valids[0] & PF.pc[2] & F.pc[2] & D_readygo & D_readygo1);
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& (rstD
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| ( ~IQ_valids[3]
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| ~IQ_valids[2] & (PF.pc[2] | F.pc[2] | D_readygo | D_readygo1)
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| ~IQ_valids[1] & (PF.pc[2] & (F.pc[2] | D_readygo | D_readygo1) | F.pc[2] & (D_readygo | D_readygo1) | D_readygo & D_readygo1)
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| ~IQ_valids[0] & (PF.pc[2] & (F.pc[2] & (D_readygo | D_readygo1) | D_readygo & D_readygo1) | F.pc[2] & D_readygo & D_readygo1)
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| IQ_valids[0] & PF.pc[2] & F.pc[2] & D_readygo & D_readygo1));
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assign fetch_i.addr = {PF.pc[31:3], 3'b000};
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//---------------------------------------------------------------------------//
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@ -241,7 +245,7 @@ module Datapath (
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F.pc
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);
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assign F.en = fetch_i.req & fetch_i.addr_ok;
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assign F.en = PF.pc[1:0] != 2'b00 & D_IA_can_dispatch | fetch_i.req & fetch_i.addr_ok;
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//---------------------------------------------------------------------------//
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// Instr Queue //
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@ -299,8 +303,8 @@ module Datapath (
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.raddr2(D.IA.RT),
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.raddr3(D.IB.RS),
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.raddr4(D.IB.RT),
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.we1(W.I0.WCtrl.RW),
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.we2(W.I1.WCtrl.RW),
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.we1(W.I0.WCtrl.RW & (W.I0.RD != W.I1.RD | W.A)),
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.we2(W.I1.WCtrl.RW & (W.I0.RD != W.I1.RD | ~W.A)),
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.waddr1(W.I0.RD),
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.waddr2(W.I1.RD),
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.wdata1(W.I0.RDataW),
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@ -360,12 +364,12 @@ module Datapath (
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);
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assign D.IA_ExcValid = D_IA_valid & (D.IA_pc[1:0] != 2'b00 | ~D_IA_iv | D.IA.SYSCALL | D.IA.BREAK | D.IA.ERET);
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assign D.IA_ERET = D_IA_valid & D.IA.ERET;
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assign D.IA_ERET = D_IA_valid & D_IA_iv & D.IA.ERET;
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assign D.IA_ExcCode = D.IA_pc[1:0] != 2'b00 ? `EXCCODE_ADDRR : ~D_IA_iv ? `EXCCODE_RI : D.IA.SYSCALL ? `EXCCODE_SYSCALL : `EXCCODE_BREAK;
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assign D.IA_Delay = 1'b0;
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assign D.IB_ExcValid = D_IB_valid & (D.IB_pc[1:0] != 2'b00 | ~D_IB_iv | D.IB.SYSCALL | D.IB.BREAK | D.IB.ERET | D.IB_Delay & D.IB.PFCtrl.BJRJ);
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assign D.IB_ERET = D_IB_valid & D.IB.ERET & ~D.IB_Delay;
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assign D.IB_ERET = D_IB_valid & D_IB_iv & D.IB.ERET & ~D.IB_Delay;
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assign D.IB_ExcCode = D.IB_pc[1:0] != 2'b00 ? `EXCCODE_ADDRR : ~D_IB_iv ? `EXCCODE_RI : D.IB.SYSCALL ? `EXCCODE_SYSCALL : D.IB.BREAK ? `EXCCODE_BREAK : `EXCCODE_RI;
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assign D.IB_Delay = D.IA.PFCtrl.BJRJ;
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@ -416,7 +420,7 @@ module Datapath (
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assign D.en0 = ~D_IA_valid | ~D_IB_valid | D_go & E.en;
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assign D.en1 = ~D_IA_valid | (~D_IB_valid | D_IB_can_dispatch) & D_go & E.en;
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assign D_go = (~PF_req | D.IA.PFCtrl.PCS == PCP8 | fetch_i.req & fetch_i.addr_ok) & D_IA_can_dispatch | D.IA_ExcValid;
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assign D_go = (~PF_go | D.IA.PFCtrl.PCS == PCP8 | fetch_i.req & fetch_i.addr_ok) & D_IA_can_dispatch | D.IA_ExcValid;
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assign D_IA_go = D_IA_valid & ~D.IA_ExcValid;
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assign D_IB_go = D_IB_valid & ~D.IB_ExcValid & D_IB_can_dispatch & ~D.IA_ExcValid;
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@ -530,11 +534,17 @@ module Datapath (
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~D_go,
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{E_I0_PrevExcValid, E.I0.ERET, E_I0_PrevExcCode, E.I0.Delay, E.I0.OFA}
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);
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ffen #(5 + 5 + 32 + 32) E_I0_ST_ff (
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ffen #(5 + 5) E_I0_RST_ff (
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clk,
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{D.I0.RS, D.I0.RT, D.I0.S, D.I0.T},
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{D.I0.RS, D.I0.RT},
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E.en,
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{E.I0.RS, E.I0.RT, E.I0.S, E.I0.T}
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{E.I0.RS, E.I0.RT}
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);
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ffen #(32 + 32) E_I0_ST_ff (
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clk,
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E.en ? {D.I0.S, D.I0.T} : {E_I0_ForwardS, E_I0_ForwardT},
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1'b1,
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{E.I0.S, E.I0.T}
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);
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ffen #(32 + 5) E_I0_IS_ff (
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clk,
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@ -581,11 +591,17 @@ module Datapath (
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~D_go,
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{E_I1_PrevExcValid, E.I1.ERET, E_I1_PrevExcCode, E.I1.Delay, E.I1.OFA}
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);
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ffen #(5 + 5 + 32 + 32) E_I1_ST_ff (
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ffen #(5 + 5) E_I1_RST_ff (
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clk,
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{D.I1.RS, D.I1.RT, D.I1.S, D.I1.T},
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{D.I1.RS, D.I1.RT},
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E.en,
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{E.I1.RS, E.I1.RT, E.I1.S, E.I1.T}
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{E.I1.RS, E.I1.RT}
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);
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ffen #(32 + 32) E_I1_ST_ff (
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clk,
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E.en ? {D.I1.S, D.I1.T} : {E_I1_ForwardS, E_I1_ForwardT},
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1'b1,
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{E.I1.S, E.I1.T}
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);
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ffen #(32 + 5) E_I1_IS_ff (
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clk,
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@ -778,11 +794,17 @@ module Datapath (
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~E_go,
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{M.I0.ExcValid, M.I0.ERET, M.I0.ExcCode, M.I0.Delay}
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);
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ffen #(5 + 5 + 32 + 32) M_I0_ST_ff (
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ffen #(5 + 5) M_I0_RST_ff (
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clk,
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{E.I0.RS, E.I0.RT, E_I0_ForwardS, E_I0_ForwardT},
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{E.I0.RS, E.I0.RT},
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M.en,
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{M.I0.RS, M.I0.RT, M.I0.S, M.I0.T}
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{M.I0.RS, M.I0.RT}
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);
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ffen #(32 + 32) M_I0_ST_ff (
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clk,
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M.en ? {E_I0_ForwardS, E_I0_ForwardT} : {M_I0_ForwardS, M_I0_ForwardT},
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1'b1,
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{M.I0.S, M.I0.T}
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);
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ffen #(32 * 9) M_I0_ALUOut_ff (
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clk,
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@ -840,12 +862,6 @@ module Datapath (
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~E_go,
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{M.I1.ExcValid, M.I1.ERET, M.I1.ExcCode, M.I1.BadVAddr, M.I1.Delay}
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);
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ffen #(5 + 32) M_I1_T_ff (
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clk,
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{E.I1.RT, E_I1_ForwardT},
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M.en,
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{M.I1.RT, M.I1.T}
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);
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ffen #(32) M_I1_ALUOut_ff (
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clk,
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E.I1.ALUOut,
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@ -871,11 +887,19 @@ module Datapath (
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// M.Exc
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assign M.I0.BadVAddr = M.I0.pc;
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assign C0_exception = M.I1.ExcValid & M.A ? {
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assign M_exception = ~M.I0.ExcValid | M.I1.ExcValid & M.A ? {
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M.I1.ExcValid, M.I1.Delay, M.I1.ExcCode, M.I1.BadVAddr, M.I1.pc, M.I1.ERET
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} : {
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M.I0.ExcValid, M.I0.Delay, M.I0.ExcCode, M.I0.BadVAddr, M.I0.pc, M.I0.ERET
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};
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assign C0_exception = {
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M_exception.ExcValid & M.en,
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M_exception.delay,
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M_exception.ExcCode,
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M_exception.BadVAddr,
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M_exception.EPC,
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M_exception.ERET & M.en
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};
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// M.I0.HILOC0
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mux4 #(32) M_I0_RDataW_mux (
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@ -923,16 +947,16 @@ module Datapath (
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// M.I1.MEM
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mux4 #(8) M_I1_Byte_mux (
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mem_i.rdata[7:0],
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mem_i.rdata[15:8],
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mem_i.rdata[23:16],
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mem_i.rdata[31:24],
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M_I1_RData[7:0],
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M_I1_RData[15:8],
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M_I1_RData[23:16],
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M_I1_RData[31:24],
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M.I1.ALUOut[1:0],
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M_I1_Byte
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);
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mux2 #(16) M_I1_Half_mux (
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mem_i.rdata[15:0],
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mem_i.rdata[31:16],
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M_I1_RData[15:0],
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M_I1_RData[31:16],
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M.I1.ALUOut[1],
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M_I1_Half
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);
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@ -949,7 +973,7 @@ module Datapath (
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mux3 #(32) M_I1_MData_mux (
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M_I1_ByteX,
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M_I1_HalfX,
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mem_i.rdata,
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M_I1_RData,
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M.I1.MCtrl.SZ,
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M_I1_MData
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);
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@ -960,8 +984,17 @@ module Datapath (
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M.I1.RDataW
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);
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buffer #(32) M_I1_RData_buffer (
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clk, rst,
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mem_i.data_ok,
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mem_i.rdata,
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M.en,
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M_I1_RData_OK,
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M_I1_RData
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);
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assign M.en = M_go & W.en;
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assign M_go = ~M.I1.MCtrl.MR | mem_i.data_ok;
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assign M_go = (~M.I1.MCtrl.MR | M_I1_RData_OK) & (~M_exception.ExcValid | fetch_i.req & fetch_i.addr_ok);
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// M.Forwarding
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assign M_I0_FS_M_I1 = M.A & M.I1.WCtrl.RW & M.I0.RS == M.I1.RD;
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@ -168,3 +168,36 @@ module extender #(
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assign q = {{(OWIDTH - IWIDTH) {s & d[IWIDTH-1]}}, d};
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endmodule
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module buffer #(
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parameter WIDTH = 8
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) (
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input clk,
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input rst,
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input logic prev_valid,
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input logic [WIDTH-1:0] prev_data,
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input logic next_en,
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output logic next_valid,
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output logic [WIDTH-1:0] next_data
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);
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logic valid;
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logic [WIDTH-1:0] data;
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ffenr #(1) valid_ff (
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clk,
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rst,
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prev_valid,
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prev_valid ^ next_en,
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valid
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);
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ffen #(WIDTH) data_ff (
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clk,
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prev_data,
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next_en,
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data
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);
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assign next_valid = valid | prev_valid;
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assign next_data = valid ? data : prev_data;
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endmodule
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@ -319,9 +319,6 @@ typedef struct packed {
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word_t BadVAddr;
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logic Delay;
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logic [4:0] RT;
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word_t T;
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word_t ALUOut;
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MCtrl1_t MCtrl;
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@ -45,7 +45,7 @@
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32'b001101?????????????????????????? 0 0 0 ? 0 0 0 1 1 0 0 RS IMM OR 0 0 0 ? ? RT 1 ALUOut 0 0 0 ?
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32'b001110?????????????????????????? 0 0 0 ? 0 0 0 1 1 0 0 RS IMM XOR ? 0 0 ? ? RT 1 ALUOut 0 0 0 ?
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32'b00111100000????????????????????? 0 0 0 ? 0 0 0 1 1 1 ? 0 IMM ADD 0 0 0 ? ? RT 1 ALUOut 0 0 0 ?
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32'b01000000000??????????00000000??? 0 0 0 ? 0 0 0 1 0 ? ? 0 IMM ? ? 0 ? ? ? RD 1 C0 0 0 0 ?
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32'b01000000000??????????00000000??? 0 0 0 ? 0 0 0 1 0 ? ? 0 IMM ? ? 0 ? ? ? RT 1 C0 0 0 0 ?
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32'b01000000100??????????00000000??? 0 0 0 ? 0 0 0 1 0 ? ? 0 IMM ? ? 0 ? ? ? ? 0 ? 0 0 1 ?
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32'b01000010000000000000000000011000 1 0 0 ? 0 0 0 1 1 ? ? 0 IMM ? ? 0 0 ? ? ? 0 ? 0 0 0 ?
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32'b100000?????????????????????????? 0 0 0 ? 0 0 0 0 1 0 1 RS IMM ADD 0 0 1 0 1 RT 1 ? ? ? ? ?
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