diff --git a/resources/ping-pong-mips32/term/spv.py b/resources/ping-pong-mips32/term/spv.py index b27be4c..763fb0e 100644 --- a/resources/ping-pong-mips32/term/spv.py +++ b/resources/ping-pong-mips32/term/spv.py @@ -1,6 +1,7 @@ import argparse import struct import serial +from sys import stdout matrix = [[0] * 81 for _ in range(25)] pos = [0, 0, 0, 0] # p1y p2y bx by @@ -62,40 +63,42 @@ def update_map(): def main(): global hello - hello = tty.readline()[:-1].decode('utf-8') + hello = '' pause = False while True: line = tty.readline()[:-1] - if len(line) < 4: - continue - - if line[0] == ord('r'): - pause = False + if line[0] < 128: + if line == b'resume': + pause = False + print_map() + continue + if line == b'pause': + pause = True + print('>>>', end=' ') + stdout.flush() + continue + try: + hello = line.decode('utf-8') + except: + pass + else: + if pause: + continue + if len(line) != 4: + continue + clear_map() + pos[0] = 25 - (line[0] - 128) + pos[1] = 25 - (line[1] - 128) + pos[2] = line[2] - 129 + pos[3] = 25 - (line[3] - 128) + update_map() print_map() - continue - if pause: - continue - if line[0] == ord('p'): - pause = True - print('>>>') - continue - - if len(line) != 4: - continue - - clear_map() - pos[0] = 25 - (line[0] - 128) - pos[1] = 25 - (line[1] - 128) - pos[2] = line[2] - 129 - pos[3] = 25 - (line[3] - 128) - update_map() - print_map() if __name__ == '__main__': parser = argparse.ArgumentParser(description='Ping Pong MIPS UI') - parser.add_argument('-s', '--serial', default='com3', type=str, + parser.add_argument('-s', '--serial', default='/dev/tty.usbserial-FTAMV947', type=str, help='Serial port name (e.g. /dev/ttyACM0, COM3)') parser.add_argument('-b', '--baud', default=57600, type=int, help='Serial port baud rate') diff --git a/src/testbench/Controller/Makefile b/src/testbench/Controller/Makefile new file mode 100644 index 0000000..e6bc6a6 --- /dev/null +++ b/src/testbench/Controller/Makefile @@ -0,0 +1,22 @@ +HOME = ../.. +INC = ${HOME}/include/ + +sources += Testbench.cpp +sources += Testbench.sv +sources += ${HOME}/Core/Controller.sv +sources += ${HOME}/Gadgets.sv + +run: test.vcd + open test.vcd + +clean: + rm -rf obj_dir + rm -f test.vcd + +test.vcd: ./obj_dir/test.out + $^ +trace + +./obj_dir/test.out: ${sources} + verilator -Wall -Wno-fatal -I${INC} +1800-2017ext+s --cc --trace --exe --build -o test.out $^ + +.PHONY: run clean diff --git a/src/testbench/Controller/Testbench.cpp b/src/testbench/Controller/Testbench.cpp new file mode 100644 index 0000000..e6164c8 --- /dev/null +++ b/src/testbench/Controller/Testbench.cpp @@ -0,0 +1,32 @@ +#include +#include "VTestbench.h" +#include "verilated.h" + +double sc_time_stamp() { return 0; } + +std::unique_ptr contextp; +std::unique_ptr top; + +int main(int argc, char **argv, char **env) { + contextp = std::make_unique(); + + contextp->debug(0); + contextp->randReset(2); + contextp->traceEverOn(true); + contextp->commandArgs(argc, argv); + + top = std::make_unique(contextp.get()); + + top->eq = 0; + top->ltz = 0; + + top->inst = 0x26100001; + top->eval(); + contextp->timeInc(5); + top->inst = 0x82040000; + top->eval(); + contextp->timeInc(5); + top->eval(); + top->final(); + return 0; +} diff --git a/src/testbench/Controller/Testbench.sv b/src/testbench/Controller/Testbench.sv new file mode 100644 index 0000000..129de25 --- /dev/null +++ b/src/testbench/Controller/Testbench.sv @@ -0,0 +1,99 @@ +`include "defines.svh" + +module Testbench( + input word_t inst, + input logic eq, + input logic ltz +); + + Ctrl_t ctrl; + word_t imm; + logic [4:0] sa; + + Controller controller( + inst, + eq, + ltz, + ctrl, + imm, + sa + ); + + + logic SYSCALL; + logic BREAK; + logic ERET; + logic OFA; + + logic [4:0] RS; + logic [4:0] RT; + + logic BJRJ; + logic B; + logic JR; + logic J; + logic BGO; + logic DP0; + logic DP1; + logic DS; + logic DT; + logic ES; + logic ET; + + SA_t ECtrl_SA; + SB_t ECtrl_SB; + aluctrl_t ECtrl_OP; + + RS0_t MCtrl0_RS0; + logic MCtrl0_HW; + logic MCtrl0_LW; + logic [4:0] MCtrl0_C0D; + logic MCtrl0_C0W; + HLS_t MCtrl0_HLS; + logic MCtrl1_MR; + logic MCtrl1_MWR; + logic MCtrl1_MX; + logic [1:0] MCtrl1_SZ; + + logic [4:0] RD; + logic WCtrl_RW; + + assign SYSCALL = ctrl.SYSCALL; + assign BREAK = ctrl.BREAK; + assign ERET = ctrl.ERET; + assign OFA = ctrl.OFA; + assign RS = ctrl.RS; + assign RT = ctrl.RT; + assign BJRJ = ctrl.BJRJ; + assign B = ctrl.B; + assign JR = ctrl.JR; + assign J = ctrl.J; + assign BGO = ctrl.BGO; + assign DP0 = ctrl.DP0; + assign DP1 = ctrl.DP1; + assign DS = ctrl.DS; + assign DT = ctrl.DT; + assign ES = ctrl.ES; + assign ET = ctrl.ET; + assign ECtrl_SA = ctrl.ECtrl.SA; + assign ECtrl_SB = ctrl.ECtrl.SB; + assign ECtrl_OP = ctrl.ECtrl.OP; + assign MCtrl0_RS0 = ctrl.MCtrl0.RS0; + assign MCtrl0_HW = ctrl.MCtrl0.HW; + assign MCtrl0_LW = ctrl.MCtrl0.LW; + assign MCtrl0_C0D = ctrl.MCtrl0.C0D; + assign MCtrl0_C0W = ctrl.MCtrl0.C0W; + assign MCtrl0_HLS = ctrl.MCtrl0.HLS; + + assign MCtrl1_MR = ctrl.MCtrl1.MR; + assign MCtrl1_MWR = ctrl.MCtrl1.MWR; + assign MCtrl1_MX = ctrl.MCtrl1.MX; + assign MCtrl1_SZ = ctrl.MCtrl1.SZ; + assign RD = ctrl.RD; + assign WCtrl_RW = ctrl.WCtrl.RW; + + initial begin + $dumpfile("test.vcd"); + $dumpvars(0, Testbench); + end +endmodule