From 9e6b806ec7c66dffab75d9b63769ed07b703dc0f Mon Sep 17 00:00:00 2001 From: Paul Pan Date: Sat, 31 Jul 2021 19:29:31 +0800 Subject: [PATCH] fix7 - mmu --- src/Cache/DCache.sv | 28 ++++++++++++++-------------- src/Core/Datapath.sv | 4 ++-- src/MMU/MMU.sv | 11 ++--------- src/include/sram.svh | 2 +- 4 files changed, 19 insertions(+), 26 deletions(-) diff --git a/src/Cache/DCache.sv b/src/Cache/DCache.sv index b0724d9..9dae4bd 100644 --- a/src/Cache/DCache.sv +++ b/src/Cache/DCache.sv @@ -273,7 +273,7 @@ module DCache ( case (port.wstrb) 4'b1111: begin - case (port.addr[1:0]) + case (addr[3:2]) 2'b11: begin wdata1[0][127:96] = port.wdata; wdata1[1][127:96] = port.wdata; @@ -299,7 +299,7 @@ module DCache ( wdata1[3][31:0] = port.wdata; end endcase - case (addr[1:0]) + case (addr[3:2]) 2'b11: begin wdata2[0][127:96] = port.wdata; wdata2[1][127:96] = port.wdata; @@ -327,7 +327,7 @@ module DCache ( endcase end 4'b1100: begin - case (port.addr[1:0]) + case (addr[3:2]) 2'b11: begin wdata1[0][127:112] = port.wdata[31:16]; wdata1[1][127:112] = port.wdata[31:16]; @@ -353,7 +353,7 @@ module DCache ( wdata1[3][31:16] = port.wdata[31:16]; end endcase - case (addr[1:0]) + case (addr[3:2]) 2'b11: begin wdata2[0][127:112] = port.wdata[31:16]; wdata2[1][127:112] = port.wdata[31:16]; @@ -381,7 +381,7 @@ module DCache ( endcase end 4'b0011: begin - case (port.addr[1:0]) + case (addr[3:2]) 2'b11: begin wdata1[0][111:96] = port.wdata[15:0]; wdata1[1][111:96] = port.wdata[15:0]; @@ -407,7 +407,7 @@ module DCache ( wdata1[3][15:0] = port.wdata[15:0]; end endcase - case (addr[1:0]) + case (addr[3:2]) 2'b11: begin wdata2[0][111:96] = port.wdata[15:0]; wdata2[1][111:96] = port.wdata[15:0]; @@ -435,7 +435,7 @@ module DCache ( endcase end 4'b1000: begin - case (port.addr[1:0]) + case (addr[3:2]) 2'b11: begin wdata1[0][127:120] = port.wdata[31:24]; wdata1[1][127:120] = port.wdata[31:24]; @@ -461,7 +461,7 @@ module DCache ( wdata1[3][31:24] = port.wdata[31:24]; end endcase - case (addr[1:0]) + case (addr[3:2]) 2'b11: begin wdata2[0][127:120] = port.wdata[31:24]; wdata2[1][127:120] = port.wdata[31:24]; @@ -489,7 +489,7 @@ module DCache ( endcase end 4'b0100: begin - case (port.addr[1:0]) + case (addr[3:2]) 2'b11: begin wdata1[0][119:112] = port.wdata[23:16]; wdata1[1][119:112] = port.wdata[23:16]; @@ -515,7 +515,7 @@ module DCache ( wdata1[3][23:16] = port.wdata[23:16]; end endcase - case (addr[1:0]) + case (addr[3:2]) 2'b11: begin wdata2[0][119:112] = port.wdata[23:16]; wdata2[1][119:112] = port.wdata[23:16]; @@ -543,7 +543,7 @@ module DCache ( endcase end 4'b0010: begin - case (port.addr[1:0]) + case (addr[3:2]) 2'b11: begin wdata1[0][111:104] = port.wdata[15:8]; wdata1[1][111:104] = port.wdata[15:8]; @@ -569,7 +569,7 @@ module DCache ( wdata1[3][15:8] = port.wdata[15:8]; end endcase - case (addr[1:0]) + case (addr[3:2]) 2'b11: begin wdata2[0][111:104] = port.wdata[15:8]; wdata2[1][111:104] = port.wdata[15:8]; @@ -597,7 +597,7 @@ module DCache ( endcase end 4'b0001: begin - case (port.addr[1:0]) + case (addr[3:2]) 2'b11: begin wdata1[0][103:96] = port.wdata[7:0]; wdata1[1][103:96] = port.wdata[7:0]; @@ -623,7 +623,7 @@ module DCache ( wdata1[3][7:0] = port.wdata[7:0]; end endcase - case (addr[1:0]) + case (addr[3:2]) 2'b11: begin wdata2[0][103:96] = port.wdata[7:0]; wdata2[1][103:96] = port.wdata[7:0]; diff --git a/src/Core/Datapath.sv b/src/Core/Datapath.sv index 11a7e22..ed59260 100644 --- a/src/Core/Datapath.sv +++ b/src/Core/Datapath.sv @@ -210,7 +210,7 @@ module Datapath ( `PCEXC, C0_EPC, `PCRST, - {~F_valid, M_exception.ERET, M_exception.ExcValid, ~D_IA_valid}, + {~F_valid, M_exception.ERET, M_exception.ExcValid, ~D_IB_valid}, PF.pc ); @@ -218,7 +218,7 @@ module Datapath ( assign rstM = C0_exception.ExcValid; assign PF_go = ~D.IA_ExcValid & ~D.IB_ExcValid & ~E.I0.ExcValid & ~E.I1.ExcValid & PF.pc[1:0] == 2'b00; - assign fetch_i.req = rst | M_exception.ExcValid | ~D_IA_valid + assign fetch_i.req = rst | M_exception.ExcValid | ~D_IB_valid | PF_go & (~D.IA.PFCtrl.BJRJ | D_IA_can_dispatch) & (rstD | ( ~IQ_valids[3] diff --git a/src/MMU/MMU.sv b/src/MMU/MMU.sv index eaa43ae..b231a19 100644 --- a/src/MMU/MMU.sv +++ b/src/MMU/MMU.sv @@ -188,7 +188,6 @@ module MMU ( word_t ddAddr1; logic [127:0] ddData1; - logic ddValid1; // ============================ // ======== dFlip-Flop ======== @@ -400,7 +399,7 @@ module MMU ( case (dwState) DW_IDLE: begin if ((drState == DR_IDLE) & dValid1 & (~dCached1 & dwr1 | dCached1 & ~dc.hit & dc.dirt_valid)) begin - if (ddValid1) begin + if (dCached1) begin wdata_axi.wdata = ddData1[31:0]; wdata_axi.wstrb = 4'b1111; wdata_axi.wvalid = 1'b1; @@ -426,7 +425,7 @@ module MMU ( end end DW_WD1: begin - if (ddValid1) begin + if (dCached1) begin wdata_axi.wdata = ddData1[31:0]; wdata_axi.wstrb = 4'b1111; wdata_axi.wvalid = 1'b1; @@ -542,12 +541,6 @@ module MMU ( dc.dirt_valid, ddData1 ); - ffen #(1) ddvalid_ff ( - clk, - dc.dirt_valid, - dc.dirt_valid, - ddValid1 - ); // ================================ // ========== dwFunction ========== diff --git a/src/include/sram.svh b/src/include/sram.svh index 4150c03..985a339 100644 --- a/src/include/sram.svh +++ b/src/include/sram.svh @@ -32,7 +32,7 @@ interface sramro_i (); endinterface -// SRAM interface for ICache/MMU <-> AXI +// SRAM interface for IDCache/MMU <-> AXI interface SRAM_RO_AXI_i; logic req; word_t addr;