Upgrade IP and Retarget to Kintex7
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resources/k7/confreg.v
Executable file
755
resources/k7/confreg.v
Executable file
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// TODO: modify to K7 board
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`define CR0_ADDR 16'h8000 //32'hbfaf_8000
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`define CR1_ADDR 16'h8004 //32'hbfaf_8004
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`define CR2_ADDR 16'h8008 //32'hbfaf_8008
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`define CR3_ADDR 16'h800c //32'hbfaf_800c
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`define CR4_ADDR 16'h8010 //32'hbfaf_8010
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`define CR5_ADDR 16'h8014 //32'hbfaf_8014
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`define CR6_ADDR 16'h8018 //32'hbfaf_8018
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`define CR7_ADDR 16'h801c //32'hbfaf_801c
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`define LED_ADDR 16'hf000 //32'hbfaf_f000
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`define LED_RG0_ADDR 16'hf004 //32'hbfaf_f004
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`define LED_RG1_ADDR 16'hf008 //32'hbfaf_f008
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`define NUM_ADDR 16'hf010 //32'hbfaf_f010
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`define SWITCH_ADDR 16'hf020 //32'hbfaf_f020
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`define BTN_KEY_ADDR 16'hf024 //32'hbfaf_f024
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`define BTN_STEP_ADDR 16'hf028 //32'hbfaf_f028
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`define SW_INTER_ADDR 16'hf02c //32'hbfaf_f02c
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`define TIMER_ADDR 16'he000 //32'hbfaf_e000
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`define IO_SIMU_ADDR 16'hffec //32'hbfaf_ffec
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`define VIRTUAL_UART_ADDR 16'hfff0 //32'hbfaf_fff0
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`define SIMU_FLAG_ADDR 16'hfff4 //32'hbfaf_fff4
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`define OPEN_TRACE_ADDR 16'hfff8 //32'hbfaf_fff8
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`define NUM_MONITOR_ADDR 16'hfffc //32'hbfaf_fffc
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module confreg
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#(parameter SIMULATION=1'b0)
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(
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input aclk,
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input timer_clk,
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input aresetn,
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// read and write from cpu
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//ar
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input [3 :0] arid ,
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input [31:0] araddr ,
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input [7 :0] arlen ,
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input [2 :0] arsize ,
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input [1 :0] arburst,
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input [1 :0] arlock ,
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input [3 :0] arcache,
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input [2 :0] arprot ,
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input arvalid,
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output arready,
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//r
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output [3 :0] rid ,
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output [31:0] rdata ,
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output [1 :0] rresp ,
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output rlast ,
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output rvalid ,
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input rready ,
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//aw
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input [3 :0] awid ,
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input [31:0] awaddr ,
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input [7 :0] awlen ,
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input [2 :0] awsize ,
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input [1 :0] awburst,
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input [1 :0] awlock ,
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input [3 :0] awcache,
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input [2 :0] awprot ,
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input awvalid,
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output awready,
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//w
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input [3 :0] wid ,
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input [31:0] wdata ,
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input [3 :0] wstrb ,
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input wlast ,
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input wvalid ,
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output wready ,
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//b
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output [3 :0] bid ,
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output [1 :0] bresp ,
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output bvalid ,
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input bready ,
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// read and write to device on board
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output [15:0] led,
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output [1 :0] led_rg0,
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output [1 :0] led_rg1,
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output reg [7 :0] num_csn,
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output reg [6 :0] num_a_g,
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input [7 :0] switch,
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output [3 :0] btn_key_col,
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input [3 :0] btn_key_row,
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input [1 :0] btn_step
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);
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reg [31:0] cr0;
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reg [31:0] cr1;
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reg [31:0] cr2;
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reg [31:0] cr3;
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reg [31:0] cr4;
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reg [31:0] cr5;
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reg [31:0] cr6;
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reg [31:0] cr7;
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reg [31:0] led_data;
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reg [31:0] led_rg0_data;
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reg [31:0] led_rg1_data;
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reg [31:0] num_data;
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wire [31:0] switch_data;
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wire [31:0] sw_inter_data; //switch interleave
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wire [31:0] btn_key_data;
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wire [31:0] btn_step_data;
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reg [31:0] timer_r2;
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reg [31:0] simu_flag;
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reg [31:0] io_simu;
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reg [7 :0] virtual_uart_data;
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reg open_trace;
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reg num_monitor;
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//--------------------------{axi interface}begin-------------------------//
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reg busy,write,R_or_W;
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reg s_wready;
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wire ar_enter = arvalid & arready;
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wire r_retire = rvalid & rready & rlast;
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wire aw_enter = awvalid & awready;
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wire w_enter = wvalid & wready & wlast;
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wire b_retire = bvalid & bready;
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assign arready = ~busy & (!R_or_W| !awvalid);
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assign awready = ~busy & ( R_or_W| !arvalid);
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reg [3 :0] buf_id;
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reg [31:0] buf_addr;
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reg [7 :0] buf_len;
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reg [2 :0] buf_size;
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always @(posedge aclk)
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begin
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if(~aresetn) busy <= 1'b0;
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else if(ar_enter|aw_enter) busy <= 1'b1;
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else if(r_retire|b_retire) busy <= 1'b0;
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end
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always @(posedge aclk)
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begin
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if(~aresetn)
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begin
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R_or_W <= 1'b0;
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buf_id <= 4'b0;
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buf_addr <= 32'b0;
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buf_len <= 8'b0;
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buf_size <= 3'b0;
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end
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else
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if(ar_enter | aw_enter)
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begin
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R_or_W <= ar_enter;
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buf_id <= ar_enter ? arid : awid ;
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buf_addr <= ar_enter ? araddr : awaddr ;
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buf_len <= ar_enter ? arlen : awlen ;
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buf_size <= ar_enter ? arsize : awsize ;
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end
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end
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reg conf_wready_reg;
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assign wready = conf_wready_reg;
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always@(posedge aclk)
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begin
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if (~aresetn ) conf_wready_reg <= 1'b0;
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else if(aw_enter ) conf_wready_reg <= 1'b1;
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else if(w_enter & wlast) conf_wready_reg <= 1'b0;
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end
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// read data has one cycle delay
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reg [31:0] conf_rdata_reg;
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reg conf_rvalid_reg;
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reg conf_rlast_reg;
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assign rdata = conf_rdata_reg;
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assign rvalid = conf_rvalid_reg;
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assign rlast = conf_rlast_reg;
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always @(posedge aclk)
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begin
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if(~aresetn)
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begin
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conf_rdata_reg <= 32'd0;
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conf_rvalid_reg <= 1'd0;
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conf_rlast_reg <= 1'd0;
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end
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else if(busy & R_or_W & !r_retire)
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begin
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conf_rvalid_reg <= 1'd1;
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conf_rlast_reg <= 1'd1;
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case (buf_addr[15:0])
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`CR0_ADDR : conf_rdata_reg <= cr0 ;
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`CR1_ADDR : conf_rdata_reg <= cr1 ;
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`CR2_ADDR : conf_rdata_reg <= cr2 ;
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`CR3_ADDR : conf_rdata_reg <= cr3 ;
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`CR4_ADDR : conf_rdata_reg <= cr4 ;
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`CR5_ADDR : conf_rdata_reg <= cr5 ;
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`CR6_ADDR : conf_rdata_reg <= cr6 ;
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`CR7_ADDR : conf_rdata_reg <= cr7 ;
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`LED_ADDR : conf_rdata_reg <= led_data ;
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`LED_RG0_ADDR : conf_rdata_reg <= led_rg0_data ;
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`LED_RG1_ADDR : conf_rdata_reg <= led_rg1_data ;
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`NUM_ADDR : conf_rdata_reg <= num_data ;
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`SWITCH_ADDR : conf_rdata_reg <= switch_data ;
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`BTN_KEY_ADDR : conf_rdata_reg <= btn_key_data ;
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`BTN_STEP_ADDR : conf_rdata_reg <= btn_step_data;
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`SW_INTER_ADDR : conf_rdata_reg <= sw_inter_data;
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`TIMER_ADDR : conf_rdata_reg <= timer_r2 ;
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`SIMU_FLAG_ADDR: conf_rdata_reg <= simu_flag ;
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`IO_SIMU_ADDR : conf_rdata_reg <= io_simu ;
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`VIRTUAL_UART_ADDR : conf_rdata_reg <= {24'd0,virtual_uart_data} ;
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`OPEN_TRACE_ADDR : conf_rdata_reg <= {31'd0,open_trace} ;
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`NUM_MONITOR_ADDR: conf_rdata_reg <= {31'd0,num_monitor} ;
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default : conf_rdata_reg <= 32'd0;
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endcase
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end
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else if(r_retire)
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begin
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conf_rvalid_reg <= 1'b0;
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end
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end
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//conf write, only support a word write
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wire conf_we;
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wire [31:0] conf_addr;
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wire [31:0] conf_wdata;
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assign conf_we = w_enter;
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assign conf_addr = buf_addr;
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assign conf_wdata= wdata;
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reg conf_bvalid_reg;
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assign bvalid = conf_bvalid_reg;
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always @(posedge aclk)
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begin
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if (~aresetn) conf_bvalid_reg <= 1'b0;
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else if(w_enter ) conf_bvalid_reg <= 1'b1;
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else if(b_retire) conf_bvalid_reg <= 1'b0;
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end
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assign rid = buf_id;
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assign bid = buf_id;
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assign bresp = 2'b0;
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assign rresp = 2'b0;
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//---------------------------{axi interface}end--------------------------//
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//-------------------------{confreg register}begin-----------------------//
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wire write_cr0 = conf_we & (conf_addr[15:0]==`CR0_ADDR);
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wire write_cr1 = conf_we & (conf_addr[15:0]==`CR1_ADDR);
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wire write_cr2 = conf_we & (conf_addr[15:0]==`CR2_ADDR);
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wire write_cr3 = conf_we & (conf_addr[15:0]==`CR3_ADDR);
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wire write_cr4 = conf_we & (conf_addr[15:0]==`CR4_ADDR);
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wire write_cr5 = conf_we & (conf_addr[15:0]==`CR5_ADDR);
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wire write_cr6 = conf_we & (conf_addr[15:0]==`CR6_ADDR);
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wire write_cr7 = conf_we & (conf_addr[15:0]==`CR7_ADDR);
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always @(posedge aclk)
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begin
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cr0 <= !aresetn ? 32'd0 :
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write_cr0 ? conf_wdata : cr0;
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cr1 <= !aresetn ? 32'd0 :
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write_cr1 ? conf_wdata : cr1;
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cr2 <= !aresetn ? 32'd0 :
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write_cr2 ? conf_wdata : cr2;
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cr3 <= !aresetn ? 32'd0 :
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write_cr3 ? conf_wdata : cr3;
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cr4 <= !aresetn ? 32'd0 :
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write_cr4 ? conf_wdata : cr4;
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cr5 <= !aresetn ? 32'd0 :
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write_cr5 ? conf_wdata : cr5;
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cr6 <= !aresetn ? 32'd0 :
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write_cr6 ? conf_wdata : cr6;
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cr7 <= !aresetn ? 32'd0 :
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write_cr7 ? conf_wdata : cr7;
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end
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//--------------------------{confreg register}end------------------------//
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//-------------------------------{timer}begin----------------------------//
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reg write_timer_begin,write_timer_begin_r1, write_timer_begin_r2,write_timer_begin_r3;
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reg write_timer_end_r1, write_timer_end_r2;
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reg [31:0] conf_wdata_r, conf_wdata_r1,conf_wdata_r2;
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reg [31:0] timer_r1;
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reg [31:0] timer;
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wire write_timer = conf_we & (conf_addr[15:0]==`TIMER_ADDR);
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always @(posedge aclk)
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begin
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if (!aresetn)
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begin
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write_timer_begin <= 1'b0;
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end
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else if (write_timer)
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begin
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write_timer_begin <= 1'b1;
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conf_wdata_r <= conf_wdata;
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end
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else if (write_timer_end_r2)
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begin
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write_timer_begin <= 1'b0;
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end
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write_timer_end_r1 <= write_timer_begin_r2;
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write_timer_end_r2 <= write_timer_end_r1;
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end
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always @(posedge timer_clk)
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begin
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write_timer_begin_r1 <= write_timer_begin;
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write_timer_begin_r2 <= write_timer_begin_r1;
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write_timer_begin_r3 <= write_timer_begin_r2;
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conf_wdata_r1 <= conf_wdata_r;
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conf_wdata_r2 <= conf_wdata_r1;
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if(!aresetn)
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begin
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timer <= 32'd0;
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end
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else if (write_timer_begin_r2 && !write_timer_begin_r3)
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begin
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timer <= conf_wdata_r2[31:0];
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end
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else
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begin
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timer <= timer + 1'b1;
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end
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end
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always @(posedge aclk)
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begin
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timer_r1 <= timer;
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timer_r2 <= timer_r1;
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end
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//--------------------------------{timer}end-----------------------------//
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//--------------------------{simulation flag}begin-----------------------//
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always @(posedge aclk)
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begin
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if(!aresetn)
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begin
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simu_flag <= {32{SIMULATION}};
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end
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end
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//---------------------------{simulation flag}end------------------------//
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//---------------------------{io simulation}begin------------------------//
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wire write_io_simu = conf_we & (conf_addr[15:0]==`IO_SIMU_ADDR);
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always @(posedge aclk)
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begin
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if(!aresetn)
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begin
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io_simu <= 32'd0;
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end
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else if(write_io_simu)
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begin
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io_simu <= {conf_wdata[15:0],conf_wdata[31:16]};
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end
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end
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//----------------------------{io simulation}end-------------------------//
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//-----------------------------{open trace}begin-------------------------//
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wire write_open_trace = conf_we & (conf_addr[15:0]==`OPEN_TRACE_ADDR);
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always @(posedge aclk)
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begin
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if(!aresetn)
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begin
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open_trace <= 1'b1;
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end
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else if(write_open_trace)
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begin
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open_trace <= |conf_wdata;
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end
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end
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//-----------------------------{open trace}end---------------------------//
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//----------------------------{num monitor}begin-------------------------//
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wire write_num_monitor = conf_we & (conf_addr[15:0]==`NUM_MONITOR_ADDR);
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always @(posedge aclk)
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begin
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if(!aresetn)
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begin
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num_monitor <= 1'b1;
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end
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else if(write_num_monitor)
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begin
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num_monitor <= conf_wdata[0];
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end
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end
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//----------------------------{num monitor}end---------------------------//
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//---------------------------{virtual uart}begin-------------------------//
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wire [7:0] write_uart_data;
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wire write_uart_valid = conf_we & (conf_addr[15:0]==`VIRTUAL_UART_ADDR);
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assign write_uart_data = conf_wdata[7:0];
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always @(posedge aclk)
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begin
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if(!aresetn)
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begin
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virtual_uart_data <= 8'd0;
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end
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else if(write_uart_valid)
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begin
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virtual_uart_data <= write_uart_data;
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end
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end
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//----------------------------{virtual uart}end--------------------------//
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//--------------------------------{led}begin-----------------------------//
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//led display
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//led_data[31:0]
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wire write_led = conf_we & (conf_addr[15:0]==`LED_ADDR);
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assign led = led_data[15:0];
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assign switch_led = {{2{switch[7]}},{2{switch[6]}},{2{switch[5]}},{2{switch[4]}},
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{2{switch[3]}},{2{switch[2]}},{2{switch[1]}},{2{switch[0]}}};
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always @(posedge aclk)
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begin
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if(!aresetn)
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begin
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led_data <= {16'h0,switch_led};
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end
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else if(write_led)
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begin
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led_data <= conf_wdata[31:0];
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end
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end
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//---------------------------------{led}end------------------------------//
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//-------------------------------{switch}begin---------------------------//
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//switch data
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//switch_data[7:0]
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assign switch_data = {24'd0,switch};
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assign sw_inter_data = {16'd0,
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switch[7],1'b0,switch[6],1'b0,
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switch[5],1'b0,switch[4],1'b0,
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switch[3],1'b0,switch[2],1'b0,
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switch[1],1'b0,switch[0],1'b0};
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//--------------------------------{switch}end----------------------------//
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//------------------------------{btn key}begin---------------------------//
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//btn key data
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reg [15:0] btn_key_r;
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assign btn_key_data = {16'd0,btn_key_r};
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//state machine
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reg [2:0] state;
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wire [2:0] next_state;
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//eliminate jitter
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reg key_flag;
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reg [19:0] key_count;
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reg [ 3:0] state_count;
|
||||
wire key_start = (state==3'b000) && !(&btn_key_row);
|
||||
wire key_end = (state==3'b111) && (&btn_key_row);
|
||||
wire key_sample= key_count[19];
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
key_flag <= 1'd0;
|
||||
end
|
||||
else if (key_sample && state_count[3])
|
||||
begin
|
||||
key_flag <= 1'b0;
|
||||
end
|
||||
else if( key_start || key_end )
|
||||
begin
|
||||
key_flag <= 1'b1;
|
||||
end
|
||||
|
||||
if(!aresetn || !key_flag)
|
||||
begin
|
||||
key_count <= 20'd0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
key_count <= key_count + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn || state_count[3])
|
||||
begin
|
||||
state_count <= 4'd0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
state_count <= state_count + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
state <= 3'b000;
|
||||
end
|
||||
else if (state_count[3])
|
||||
begin
|
||||
state <= next_state;
|
||||
end
|
||||
end
|
||||
|
||||
assign next_state = (state == 3'b000) ? ( (key_sample && !(&btn_key_row)) ? 3'b001 : 3'b000 ) :
|
||||
(state == 3'b001) ? ( !(&btn_key_row) ? 3'b111 : 3'b010 ) :
|
||||
(state == 3'b010) ? ( !(&btn_key_row) ? 3'b111 : 3'b011 ) :
|
||||
(state == 3'b011) ? ( !(&btn_key_row) ? 3'b111 : 3'b100 ) :
|
||||
(state == 3'b100) ? ( !(&btn_key_row) ? 3'b111 : 3'b000 ) :
|
||||
(state == 3'b111) ? ( (key_sample && (&btn_key_row)) ? 3'b000 : 3'b111 ) :
|
||||
3'b000;
|
||||
assign btn_key_col = (state == 3'b000) ? 4'b0000:
|
||||
(state == 3'b001) ? 4'b1110:
|
||||
(state == 3'b010) ? 4'b1101:
|
||||
(state == 3'b011) ? 4'b1011:
|
||||
(state == 3'b100) ? 4'b0111:
|
||||
4'b0000;
|
||||
wire [15:0] btn_key_tmp;
|
||||
always @(posedge aclk) begin
|
||||
if(!aresetn) begin
|
||||
btn_key_r <= 16'd0;
|
||||
end
|
||||
else if(next_state==3'b000)
|
||||
begin
|
||||
btn_key_r <=16'd0;
|
||||
end
|
||||
else if(next_state == 3'b111 && state != 3'b111) begin
|
||||
btn_key_r <= btn_key_tmp;
|
||||
end
|
||||
end
|
||||
|
||||
assign btn_key_tmp = (state == 3'b001)&(btn_key_row == 4'b1110) ? 16'h0001:
|
||||
(state == 3'b001)&(btn_key_row == 4'b1101) ? 16'h0010:
|
||||
(state == 3'b001)&(btn_key_row == 4'b1011) ? 16'h0100:
|
||||
(state == 3'b001)&(btn_key_row == 4'b0111) ? 16'h1000:
|
||||
(state == 3'b010)&(btn_key_row == 4'b1110) ? 16'h0002:
|
||||
(state == 3'b010)&(btn_key_row == 4'b1101) ? 16'h0020:
|
||||
(state == 3'b010)&(btn_key_row == 4'b1011) ? 16'h0200:
|
||||
(state == 3'b010)&(btn_key_row == 4'b0111) ? 16'h2000:
|
||||
(state == 3'b011)&(btn_key_row == 4'b1110) ? 16'h0004:
|
||||
(state == 3'b011)&(btn_key_row == 4'b1101) ? 16'h0040:
|
||||
(state == 3'b011)&(btn_key_row == 4'b1011) ? 16'h0400:
|
||||
(state == 3'b011)&(btn_key_row == 4'b0111) ? 16'h4000:
|
||||
(state == 3'b100)&(btn_key_row == 4'b1110) ? 16'h0008:
|
||||
(state == 3'b100)&(btn_key_row == 4'b1101) ? 16'h0080:
|
||||
(state == 3'b100)&(btn_key_row == 4'b1011) ? 16'h0800:
|
||||
(state == 3'b100)&(btn_key_row == 4'b0111) ? 16'h8000:16'h0000;
|
||||
//-------------------------------{btn key}end----------------------------//
|
||||
|
||||
//-----------------------------{btn step}begin---------------------------//
|
||||
//btn step data
|
||||
reg btn_step0_r; //0:press
|
||||
reg btn_step1_r; //0:press
|
||||
assign btn_step_data = {30'd0,~btn_step0_r,~btn_step1_r}; //1:press
|
||||
|
||||
//-----step0
|
||||
//eliminate jitter
|
||||
reg step0_flag;
|
||||
reg [19:0] step0_count;
|
||||
wire step0_start = btn_step0_r && !btn_step[0];
|
||||
wire step0_end = !btn_step0_r && btn_step[0];
|
||||
wire step0_sample= step0_count[19];
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
step0_flag <= 1'd0;
|
||||
end
|
||||
else if (step0_sample)
|
||||
begin
|
||||
step0_flag <= 1'b0;
|
||||
end
|
||||
else if( step0_start || step0_end )
|
||||
begin
|
||||
step0_flag <= 1'b1;
|
||||
end
|
||||
|
||||
if(!aresetn || !step0_flag)
|
||||
begin
|
||||
step0_count <= 20'd0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
step0_count <= step0_count + 1'b1;
|
||||
end
|
||||
|
||||
if(!aresetn)
|
||||
begin
|
||||
btn_step0_r <= 1'b1;
|
||||
end
|
||||
else if(step0_sample)
|
||||
begin
|
||||
btn_step0_r <= btn_step[0];
|
||||
end
|
||||
end
|
||||
|
||||
//-----step1
|
||||
//eliminate jitter
|
||||
reg step1_flag;
|
||||
reg [19:0] step1_count;
|
||||
wire step1_start = btn_step1_r && !btn_step[1];
|
||||
wire step1_end = !btn_step1_r && btn_step[1];
|
||||
wire step1_sample= step1_count[19];
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
step1_flag <= 1'd0;
|
||||
end
|
||||
else if (step1_sample)
|
||||
begin
|
||||
step1_flag <= 1'b0;
|
||||
end
|
||||
else if( step1_start || step1_end )
|
||||
begin
|
||||
step1_flag <= 1'b1;
|
||||
end
|
||||
|
||||
if(!aresetn || !step1_flag)
|
||||
begin
|
||||
step1_count <= 20'd0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
step1_count <= step1_count + 1'b1;
|
||||
end
|
||||
|
||||
if(!aresetn)
|
||||
begin
|
||||
btn_step1_r <= 1'b1;
|
||||
end
|
||||
else if(step1_sample)
|
||||
begin
|
||||
btn_step1_r <= btn_step[1];
|
||||
end
|
||||
end
|
||||
//------------------------------{btn step}end----------------------------//
|
||||
|
||||
//-------------------------------{led rg}begin---------------------------//
|
||||
//led_rg0_data[31:0] led_rg0_data[31:0]
|
||||
//bfd0_f010 bfd0_f014
|
||||
wire write_led_rg0 = conf_we & (conf_addr[15:0]==`LED_RG0_ADDR);
|
||||
wire write_led_rg1 = conf_we & (conf_addr[15:0]==`LED_RG1_ADDR);
|
||||
assign led_rg0 = led_rg0_data[1:0];
|
||||
assign led_rg1 = led_rg1_data[1:0];
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
led_rg0_data <= 32'h0;
|
||||
end
|
||||
else if(write_led_rg0)
|
||||
begin
|
||||
led_rg0_data <= conf_wdata[31:0];
|
||||
end
|
||||
|
||||
if(!aresetn)
|
||||
begin
|
||||
led_rg1_data <= 32'h0;
|
||||
end
|
||||
else if(write_led_rg1)
|
||||
begin
|
||||
led_rg1_data <= conf_wdata[31:0];
|
||||
end
|
||||
end
|
||||
//--------------------------------{led rg}end----------------------------//
|
||||
|
||||
//---------------------------{digital number}begin-----------------------//
|
||||
//digital number display
|
||||
//num_data[31:0]
|
||||
wire write_num = conf_we & (conf_addr[15:0]==`NUM_ADDR);
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
num_data <= 32'h0;
|
||||
end
|
||||
else if(write_num)
|
||||
begin
|
||||
num_data <= conf_wdata[31:0];
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
reg [19:0] count;
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
count <= 20'd0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
count <= count + 1'b1;
|
||||
end
|
||||
end
|
||||
//scan data
|
||||
reg [3:0] scan_data;
|
||||
always @ ( posedge aclk )
|
||||
begin
|
||||
if ( !aresetn )
|
||||
begin
|
||||
scan_data <= 32'd0;
|
||||
num_csn <= 8'b1111_1111;
|
||||
end
|
||||
else
|
||||
begin
|
||||
case(count[19:17])
|
||||
3'b000 : scan_data <= num_data[31:28];
|
||||
3'b001 : scan_data <= num_data[27:24];
|
||||
3'b010 : scan_data <= num_data[23:20];
|
||||
3'b011 : scan_data <= num_data[19:16];
|
||||
3'b100 : scan_data <= num_data[15:12];
|
||||
3'b101 : scan_data <= num_data[11: 8];
|
||||
3'b110 : scan_data <= num_data[7 : 4];
|
||||
3'b111 : scan_data <= num_data[3 : 0];
|
||||
endcase
|
||||
|
||||
case(count[19:17])
|
||||
3'b000 : num_csn <= 8'b0111_1111;
|
||||
3'b001 : num_csn <= 8'b1011_1111;
|
||||
3'b010 : num_csn <= 8'b1101_1111;
|
||||
3'b011 : num_csn <= 8'b1110_1111;
|
||||
3'b100 : num_csn <= 8'b1111_0111;
|
||||
3'b101 : num_csn <= 8'b1111_1011;
|
||||
3'b110 : num_csn <= 8'b1111_1101;
|
||||
3'b111 : num_csn <= 8'b1111_1110;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if ( !aresetn )
|
||||
begin
|
||||
num_a_g <= 7'b0000000;
|
||||
end
|
||||
else
|
||||
begin
|
||||
case ( scan_data )
|
||||
4'd0 : num_a_g <= 7'b1111110; //0
|
||||
4'd1 : num_a_g <= 7'b0110000; //1
|
||||
4'd2 : num_a_g <= 7'b1101101; //2
|
||||
4'd3 : num_a_g <= 7'b1111001; //3
|
||||
4'd4 : num_a_g <= 7'b0110011; //4
|
||||
4'd5 : num_a_g <= 7'b1011011; //5
|
||||
4'd6 : num_a_g <= 7'b1011111; //6
|
||||
4'd7 : num_a_g <= 7'b1110000; //7
|
||||
4'd8 : num_a_g <= 7'b1111111; //8
|
||||
4'd9 : num_a_g <= 7'b1111011; //9
|
||||
4'd10: num_a_g <= 7'b1110111; //a
|
||||
4'd11: num_a_g <= 7'b0011111; //b
|
||||
4'd12: num_a_g <= 7'b1001110; //c
|
||||
4'd13: num_a_g <= 7'b0111101; //d
|
||||
4'd14: num_a_g <= 7'b1001111; //e
|
||||
4'd15: num_a_g <= 7'b1000111; //f
|
||||
endcase
|
||||
end
|
||||
end
|
||||
//----------------------------{digital number}end------------------------//
|
||||
endmodule
|
||||
184
resources/k7/kintex_basec_ddr3_pin.ucf
Normal file
184
resources/k7/kintex_basec_ddr3_pin.ucf
Normal file
@ -0,0 +1,184 @@
|
||||
NET "ddr3_dm[0]" LOC = "AF15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[0]" LOC = "AF14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[1]" LOC = "AF17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[2]" LOC = "AE15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[3]" LOC = "AE17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[4]" LOC = "AD16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[5]" LOC = "AF20" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[6]" LOC = "AD15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[7]" LOC = "AF19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[0]" LOC = "AF18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[0]" LOC = "AE18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dm[0]" LOC = "AF15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dm[1]" LOC = "AA15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[0]" LOC = "AF14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[10]" LOC = "AA18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[11]" LOC = "AA14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[12]" LOC = "AB16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[13]" LOC = "AB14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[14]" LOC = "AA17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[15]" LOC = "AD14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[1]" LOC = "AF17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[2]" LOC = "AE15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[3]" LOC = "AE17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[4]" LOC = "AD16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[5]" LOC = "AF20" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[6]" LOC = "AD15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[7]" LOC = "AF19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[8]" LOC = "AB15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[9]" LOC = "AC14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[0]" LOC = "AF18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[1]" LOC = "Y16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[0]" LOC = "AE18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[1]" LOC = "Y15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dm[0]" LOC = "AF15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dm[1]" LOC = "AA15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dm[2]" LOC = "AB19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dm[3]" LOC = "V14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[0]" LOC = "AF14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[10]" LOC = "AA18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[11]" LOC = "AA14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[12]" LOC = "AB16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[13]" LOC = "AB14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[14]" LOC = "AA17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[15]" LOC = "AD14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[16]" LOC = "AD19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[17]" LOC = "AC19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[18]" LOC = "AD18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[19]" LOC = "AA19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[1]" LOC = "AF17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[20]" LOC = "AC17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[21]" LOC = "AA20" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[22]" LOC = "AC18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[23]" LOC = "AB17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[2]" LOC = "AE15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[3]" LOC = "AE17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[4]" LOC = "AD16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[5]" LOC = "AF20" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[6]" LOC = "AD15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[7]" LOC = "AF19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[8]" LOC = "AB15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[9]" LOC = "AC14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[0]" LOC = "AF18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[1]" LOC = "Y16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[2]" LOC = "AE20" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[3]" LOC = "W19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[0]" LOC = "AE18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[1]" LOC = "Y15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[2]" LOC = "AD20" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[3]" LOC = "W18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dm[0]" LOC = "AF15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dm[1]" LOC = "AA15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dm[2]" LOC = "AB19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dm[3]" LOC = "V14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[0]" LOC = "AF14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[10]" LOC = "AA18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[11]" LOC = "AA14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[12]" LOC = "AB16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[13]" LOC = "AB14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[14]" LOC = "AA17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[15]" LOC = "AD14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[16]" LOC = "AD19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[17]" LOC = "AC19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[18]" LOC = "AD18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[19]" LOC = "AA19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[1]" LOC = "AF17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[20]" LOC = "AC17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[21]" LOC = "AA20" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[22]" LOC = "AC18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[23]" LOC = "AB17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[24]" LOC = "Y17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[25]" LOC = "V16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[26]" LOC = "V17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[27]" LOC = "W14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[28]" LOC = "V18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[29]" LOC = "W15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[2]" LOC = "AE15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[30]" LOC = "V19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[31]" LOC = "W16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[3]" LOC = "AE17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[4]" LOC = "AD16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[5]" LOC = "AF20" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[6]" LOC = "AD15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[7]" LOC = "AF19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[8]" LOC = "AB15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[9]" LOC = "AC14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[0]" LOC = "AF18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[1]" LOC = "Y16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[2]" LOC = "AE20" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[3]" LOC = "W19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[0]" LOC = "AE18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[1]" LOC = "Y15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[2]" LOC = "AD20" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[3]" LOC = "W18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[0]" LOC = "AF8" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[10]" LOC = "AD9" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[11]" LOC = "AA10" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[12]" LOC = "AF9" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[13]" LOC = "V7" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[14]" LOC = "Y8" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[1]" LOC = "AB10" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[2]" LOC = "V9" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[3]" LOC = "Y7" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[4]" LOC = "AC9" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[5]" LOC = "W8" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[6]" LOC = "Y11" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[7]" LOC = "V8" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[8]" LOC = "AA8" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[9]" LOC = "AC11" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_ba[0]" LOC = "AA7" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_ba[1]" LOC = "AB11" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_ba[2]" LOC = "AF7" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_cas_n" LOC = "W10" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_ck_n[0]" LOC = "AB9" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_ck_p[0]" LOC = "AA9" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_cke[0]" LOC = "AF10" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_cs_n[0]" LOC = "AB7" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dm[0]" LOC = "AF15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dm[1]" LOC = "AA15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dm[2]" LOC = "AB19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dm[3]" LOC = "V14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[0]" LOC = "AF14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[10]" LOC = "AA18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[11]" LOC = "AA14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[12]" LOC = "AB16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[13]" LOC = "AB14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[14]" LOC = "AA17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[15]" LOC = "AD14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[16]" LOC = "AD19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[17]" LOC = "AC19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[18]" LOC = "AD18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[19]" LOC = "AA19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[1]" LOC = "AF17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[20]" LOC = "AC17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[21]" LOC = "AA20" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[22]" LOC = "AC18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[23]" LOC = "AB17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[24]" LOC = "Y17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[25]" LOC = "V16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[26]" LOC = "V17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[27]" LOC = "W14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[28]" LOC = "V18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[29]" LOC = "W15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[2]" LOC = "AE15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[30]" LOC = "V19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[31]" LOC = "W16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[3]" LOC = "AE17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[4]" LOC = "AD16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[5]" LOC = "AF20" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[6]" LOC = "AD15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[7]" LOC = "AF19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[8]" LOC = "AB15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[9]" LOC = "AC14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[0]" LOC = "AF18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[1]" LOC = "Y16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[2]" LOC = "AE20" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[3]" LOC = "W19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[0]" LOC = "AE18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[1]" LOC = "Y15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[2]" LOC = "AD20" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[3]" LOC = "W18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_odt[0]" LOC = "AC8" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_ras_n" LOC = "AD8" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_reset_n" LOC = "Y10" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_we_n" LOC = "W9" | | VCCAUX_IO = HIGH ;
|
||||
91
resources/k7/mycpu_top_verilog.v
Normal file
91
resources/k7/mycpu_top_verilog.v
Normal file
@ -0,0 +1,91 @@
|
||||
module mycpu_top_verilog (
|
||||
input wire [5:0] ext_int, //high active
|
||||
|
||||
input wire aclk,
|
||||
input wire aresetn, //low active
|
||||
|
||||
output wire [ 3:0] arid,
|
||||
output wire [31:0] araddr,
|
||||
output wire [ 3:0] arlen,
|
||||
output wire [ 2:0] arsize,
|
||||
output wire [ 1:0] arburst,
|
||||
output wire [ 1:0] arlock,
|
||||
output wire [ 3:0] arcache,
|
||||
output wire [ 2:0] arprot,
|
||||
output wire arvalid,
|
||||
input wire arready,
|
||||
|
||||
input wire [ 3:0] rid,
|
||||
input wire [31:0] rdata,
|
||||
input wire [ 1:0] rresp,
|
||||
input wire rlast,
|
||||
input wire rvalid,
|
||||
output wire rready,
|
||||
|
||||
output wire [ 3:0] awid,
|
||||
output wire [31:0] awaddr,
|
||||
output wire [ 3:0] awlen,
|
||||
output wire [ 2:0] awsize,
|
||||
output wire [ 1:0] awburst,
|
||||
output wire [ 1:0] awlock,
|
||||
output wire [ 3:0] awcache,
|
||||
output wire [ 2:0] awprot,
|
||||
output wire awvalid,
|
||||
input wire awready,
|
||||
|
||||
output wire [ 3:0] wid,
|
||||
output wire [31:0] wdata,
|
||||
output wire [ 3:0] wstrb,
|
||||
output wire wlast,
|
||||
output wire wvalid,
|
||||
input wire wready,
|
||||
|
||||
input wire [3:0] bid,
|
||||
input wire [1:0] bresp,
|
||||
input wire bvalid,
|
||||
output wire bready
|
||||
);
|
||||
|
||||
mycpu_top cpu(
|
||||
.ext_int(ext_int),
|
||||
.aclk (aclk),
|
||||
.aresetn(aresetn),
|
||||
.arid (arid),
|
||||
.araddr (araddr),
|
||||
.arlen (arlen),
|
||||
.arsize (arsize),
|
||||
.arburst(arburst),
|
||||
.arlock (arlock),
|
||||
.arcache(arcache),
|
||||
.arprot (arprot),
|
||||
.arvalid(arvalid),
|
||||
.arready(arready),
|
||||
.rid (rid),
|
||||
.rdata (rdata),
|
||||
.rresp (rresp),
|
||||
.rlast (rlast),
|
||||
.rvalid (rvalid),
|
||||
.rready (rready),
|
||||
.awid (awid),
|
||||
.awaddr (awaddr),
|
||||
.awlen (awlen),
|
||||
.awsize (awsize),
|
||||
.awburst(awburst),
|
||||
.awlock (awlock),
|
||||
.awcache(awcache),
|
||||
.awprot (awprot),
|
||||
.awvalid(awvalid),
|
||||
.awready(awready),
|
||||
.wid (wid),
|
||||
.wdata (wdata),
|
||||
.wstrb (wstrb),
|
||||
.wlast (wlast),
|
||||
.wvalid (wvalid),
|
||||
.wready (wready),
|
||||
.bid (bid),
|
||||
.bresp (bresp),
|
||||
.bvalid (bvalid),
|
||||
.bready (bready)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@ -3,7 +3,7 @@
|
||||
"ip_inst": {
|
||||
"xci_name": "div_signed",
|
||||
"component_reference": "xilinx.com:ip:div_gen:5.1",
|
||||
"ip_revision": "19",
|
||||
"ip_revision": "20",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
@ -32,7 +32,7 @@
|
||||
"ARESETN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_XDEVICEFAMILY": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_XDEVICEFAMILY": [ { "value": "kintex7", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_ARESETN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_ACLKEN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_LATENCY": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
@ -58,11 +58,11 @@
|
||||
"C_M_AXIS_DOUT_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "artix7" } ],
|
||||
"ARCHITECTURE": [ { "value": "kintex7" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7a200t" } ],
|
||||
"PACKAGE": [ { "value": "fbg676" } ],
|
||||
"DEVICE": [ { "value": "xc7k325t" } ],
|
||||
"PACKAGE": [ { "value": "ffg676" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
@ -74,12 +74,12 @@
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "19" } ],
|
||||
"IPREVISION": [ { "value": "20" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2022.2" } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
"ip_inst": {
|
||||
"xci_name": "div_unsigned",
|
||||
"component_reference": "xilinx.com:ip:div_gen:5.1",
|
||||
"ip_revision": "19",
|
||||
"ip_revision": "20",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
@ -32,7 +32,7 @@
|
||||
"ARESETN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_XDEVICEFAMILY": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_XDEVICEFAMILY": [ { "value": "kintex7", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_ARESETN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_ACLKEN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_LATENCY": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
@ -58,11 +58,11 @@
|
||||
"C_M_AXIS_DOUT_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "artix7" } ],
|
||||
"ARCHITECTURE": [ { "value": "kintex7" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7a200t" } ],
|
||||
"PACKAGE": [ { "value": "fbg676" } ],
|
||||
"DEVICE": [ { "value": "xc7k325t" } ],
|
||||
"PACKAGE": [ { "value": "ffg676" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
@ -74,12 +74,12 @@
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "19" } ],
|
||||
"IPREVISION": [ { "value": "20" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2022.2" } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
"ip_inst": {
|
||||
"xci_name": "mul_signed",
|
||||
"component_reference": "xilinx.com:ip:mult_gen:12.0",
|
||||
"ip_revision": "18",
|
||||
"ip_revision": "19",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
@ -33,7 +33,7 @@
|
||||
"C_VERBOSITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MODEL_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OPTIMIZE_GOAL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_XDEVICEFAMILY": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_XDEVICEFAMILY": [ { "value": "kintex7", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_CE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SCLR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_LATENCY": [ { "value": "6", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
@ -52,11 +52,11 @@
|
||||
"C_ROUND_PT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "artix7" } ],
|
||||
"ARCHITECTURE": [ { "value": "kintex7" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7a200t" } ],
|
||||
"PACKAGE": [ { "value": "fbg676" } ],
|
||||
"DEVICE": [ { "value": "xc7k325t" } ],
|
||||
"PACKAGE": [ { "value": "ffg676" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
@ -68,12 +68,12 @@
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "18" } ],
|
||||
"IPREVISION": [ { "value": "19" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2022.2" } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
@ -90,7 +90,7 @@
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_static_object": false } ]
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "A" } ]
|
||||
@ -105,11 +105,11 @@
|
||||
"ASSOCIATED_RESET": [ { "value": "sclr", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "ce", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "CLK" } ]
|
||||
@ -121,7 +121,7 @@
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"ce_intf": {
|
||||
@ -137,7 +137,7 @@
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_static_object": false } ]
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "B" } ]
|
||||
@ -148,7 +148,7 @@
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_static_object": false } ]
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "P" } ]
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
"ip_inst": {
|
||||
"xci_name": "mul_unsigned",
|
||||
"component_reference": "xilinx.com:ip:mult_gen:12.0",
|
||||
"ip_revision": "18",
|
||||
"ip_revision": "19",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
@ -33,7 +33,7 @@
|
||||
"C_VERBOSITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MODEL_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OPTIMIZE_GOAL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_XDEVICEFAMILY": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_XDEVICEFAMILY": [ { "value": "kintex7", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_CE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SCLR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_LATENCY": [ { "value": "6", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
@ -52,11 +52,11 @@
|
||||
"C_ROUND_PT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "artix7" } ],
|
||||
"ARCHITECTURE": [ { "value": "kintex7" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7a200t" } ],
|
||||
"PACKAGE": [ { "value": "fbg676" } ],
|
||||
"DEVICE": [ { "value": "xc7k325t" } ],
|
||||
"PACKAGE": [ { "value": "ffg676" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
@ -68,12 +68,12 @@
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "18" } ],
|
||||
"IPREVISION": [ { "value": "19" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2022.2" } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
@ -90,7 +90,7 @@
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_static_object": false } ]
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "A" } ]
|
||||
@ -105,11 +105,11 @@
|
||||
"ASSOCIATED_RESET": [ { "value": "sclr", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "ce", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "CLK" } ]
|
||||
@ -121,7 +121,7 @@
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"ce_intf": {
|
||||
@ -137,7 +137,7 @@
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_static_object": false } ]
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "B" } ]
|
||||
@ -148,7 +148,7 @@
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_static_object": false } ]
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "P" } ]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user