fetch free test
fix bug
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b352e51af0
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@ -56,6 +56,7 @@ module Datapath (
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// F
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// F
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logic F_valid;
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logic F_valid;
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logic F_free;
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// Instr Queue
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// Instr Queue
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logic IQ_IA_valid;
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logic IQ_IA_valid;
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@ -111,7 +112,6 @@ module Datapath (
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logic D_IA_DataHazard;
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logic D_IA_DataHazard;
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logic D_IB_DataHazard;
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logic D_IB_DataHazard;
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// Execute
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// Execute
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logic E_valid;
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logic E_valid;
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logic E_go;
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logic E_go;
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@ -223,10 +223,10 @@ module Datapath (
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| PF_go & (~D_IB_valid & ~IQ_valids[3] | (~D.IA.BJRJ | D_readygo)
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| PF_go & (~D_IB_valid & ~IQ_valids[3] | (~D.IA.BJRJ | D_readygo)
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& (rstD
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& (rstD
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| ~IQ_valids[3]
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| ~IQ_valids[3]
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| ~IQ_valids[2] & (PF.pc[2] | F.pc[2] | D_readygo)
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| ~IQ_valids[2] & (F_free | PF.pc[2] | F.pc[2] | D_readygo)
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| ~IQ_valids[1] & (PF.pc[2] & (F.pc[2] | D_readygo) | F.pc[2] & D_readygo | D_readygo & D_readygo1)
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| ~IQ_valids[1] & (F_free | PF.pc[2] & (F.pc[2] | D_readygo) | F.pc[2] & D_readygo | D_readygo & D_readygo1)
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| ~IQ_valids[0] & (PF.pc[2] & (F.pc[2] & D_readygo | D_readygo & D_readygo1) | F.pc[2] & D_readygo & D_readygo1)
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| ~IQ_valids[0] & (F_free & (PF.pc[2] | F.pc[2] | D_readygo) | PF.pc[2] & (F.pc[2] & D_readygo | D_readygo & D_readygo1) | F.pc[2] & D_readygo & D_readygo1)
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| IQ_valids[0] & PF.pc[2] & F.pc[2] & D_readygo & D_readygo1));
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| IQ_valids[0] & (F_free & (PF.pc[2] & (F.pc[2] | D_readygo) | F.pc[2] & D_readygo | D_readygo & D_readygo1) | PF.pc[2] & F.pc[2] & D_readygo & D_readygo1)));
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assign fetch_i.addr = {PF.pc[31:3], 3'b000};
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assign fetch_i.addr = {PF.pc[31:3], 3'b000};
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//---------------------------------------------------------------------------//
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//---------------------------------------------------------------------------//
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@ -235,10 +235,17 @@ module Datapath (
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// F.FF
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// F.FF
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ffenr #(1) F_valid_ff (
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ffenr #(1) F_valid_ff (
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clk, rst,
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clk, rst,
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1'b1,
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1'b1,
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1'b1,
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1'b1,
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F_valid
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F_valid
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);
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ffenr #(1) F_free_ff (
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clk, rst,
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~F.en,
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F.en | fetch_i.data_ok,
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F_free
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);
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);
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ffenr #(32) F_pc_ff (
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ffenr #(32) F_pc_ff (
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