diff --git a/src/Core/ALU.sv b/src/Core/ALU.sv
index 4dc29dd..2856b3e 100644
--- a/src/Core/ALU.sv
+++ b/src/Core/ALU.sv
@@ -10,11 +10,6 @@ module alu(
 
     wire logic [ 4:0] sa = a[4:0];
     wire logic        ex = alt & b[31];
-    wire logic [46:0] sr4 = sa[4] ? {{31{ex}}, b[31:16]} : {{15{ex}}, b[31:0]};
-    wire logic [34:0] sr2 = sa[3] ? sa[2] ? sr4[46:12] : sr4[42:8]
-                                  : sa[2] ? sr4[38: 4] : sr4[34:0];
-    wire logic [31:0] sr  = sa[1] ? sa[0] ? sr2[34: 3] : sr2[33:2]
-                                  : sa[0] ? sr2[32: 1] : sr2[31:0];
 
     wire word_t b2 = alt ? ~b : b;
     wire word_t sum;
@@ -22,7 +17,7 @@ module alu(
 
     assign {lt, ltu, sum} = {a[31], 1'b0, a} + {b2[31], 1'b1, b2} + alt; // alt for cin(CARRY4) at synthesis
     assign aluout = (aluctrl.f_sl   ? b << sa                : 32'b0)
-                  | (aluctrl.f_sr   ? sr                     : 32'b0)
+                  | (aluctrl.f_sr   ? {{31{ex}}, b}[sa+:32]  : 32'b0)
                   | (aluctrl.f_add  ? sum                    : 32'b0)
                   | (aluctrl.f_and  ? a & b                  : 32'b0)
                   | (aluctrl.f_or   ? alt ? ~(a | b) : a | b : 32'b0)
diff --git a/src/Core/Gadgets.sv b/src/Core/Gadgets.sv
index c19605a..4be3820 100644
--- a/src/Core/Gadgets.sv
+++ b/src/Core/Gadgets.sv
@@ -19,7 +19,7 @@ module instr_valid(
         output logic  valid);
 
     always_comb
-        unique casex(instr)
+        casez(instr)
             32'b00000000000???????????????000000: valid = 1'b1; // SLL
             32'b00000000000???????????????000010: valid = 1'b1; // SRL
             32'b00000000000???????????????000011: valid = 1'b1; // SRA
diff --git a/tools/ctrl_maker.py b/tools/ctrl_maker.py
index 400fd1b..d1e61f2 100644
--- a/tools/ctrl_maker.py
+++ b/tools/ctrl_maker.py
@@ -3,6 +3,8 @@ with open('ctrl.sv') as f:
 	title = lines[0].split()
 	items = [x.split() for x in lines[1:]]
 
+bits = title[0].count('-')
+
 def gini(d):
 	s = set(v for k, v in d)
 	g = 1
@@ -32,7 +34,7 @@ def solve(d):
 		return {s.pop(): ''}
 	min_gini = -1
 	min_idx = -1
-	for i in range(0, 32):
+	for i in range(0, bits):
 		s0 = [(k, v) for k, v in d if k[i] == '0']
 		s1 = [(k, v) for k, v in d if k[i] == '1']
 		if(len(s0) + len(s1) != len(d)):