fix top
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c73a8278af
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@ -84,11 +84,11 @@ module soc_up_top(
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output phy_rstn,
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//------EJTAG-------
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input EJTAG_TRST,
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input EJTAG_TCK,
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input EJTAG_TDI,
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input EJTAG_TMS,
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output EJTAG_TDO,
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// input EJTAG_TRST,
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// input EJTAG_TCK,
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// input EJTAG_TDI,
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// input EJTAG_TMS,
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// output EJTAG_TDO,
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//------uart-------
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inout UART_RX,
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@ -555,12 +555,10 @@ assign int_out = {1'b0,dma_int,nand_int,spi_inta_o,uart0_int,mac_int};
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assign int_n_i = ~int_out;
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// cpu
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godson_cpu_mid cpu_mid(
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.coreclock (aclk),
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.interrupt_i (int_n_i[4:0]), //232 only 5bit
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.nmi (1'b1),
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.areset_n (aresetn ),
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mycpu_top mycpu(
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.aclk (aclk ),
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.ext_int (int_out ),
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.aresetn (aresetn ),
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.arid (m0_arid[3:0] ),
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.araddr (m0_araddr ),
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.arlen (m0_arlen ),
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@ -596,16 +594,7 @@ godson_cpu_mid cpu_mid(
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.bid (m0_bid[3:0] ),
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.bresp (m0_bresp ),
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.bvalid (m0_bvalid ),
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.bready (m0_bready ),
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.EJTAG_TCK (EJTAG_TCK ),
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.EJTAG_TDI (EJTAG_TDI ),
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.EJTAG_TMS (EJTAG_TMS ),
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.EJTAG_TRST (EJTAG_TRST ),
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.EJTAG_TDO (EJTAG_TDO ),
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.prrst_to_core ( ),
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.testmode (1'b0 )
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.bready (m0_bready )
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);
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// AXI_MUX
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@ -125,11 +125,11 @@ set_property PACKAGE_PIN W21 [get_ports {NAND_DATA[1]}]
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set_property PACKAGE_PIN AC24 [get_ports {NAND_DATA[0]}]
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#ejtag
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set_property PACKAGE_PIN J18 [get_ports EJTAG_TRST]
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set_property PACKAGE_PIN K18 [get_ports EJTAG_TCK]
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set_property PACKAGE_PIN K20 [get_ports EJTAG_TDI]
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set_property PACKAGE_PIN K22 [get_ports EJTAG_TMS]
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set_property PACKAGE_PIN K21 [get_ports EJTAG_TDO]
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# set_property PACKAGE_PIN J18 [get_ports EJTAG_TRST]
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# set_property PACKAGE_PIN K18 [get_ports EJTAG_TCK]
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# set_property PACKAGE_PIN K20 [get_ports EJTAG_TDI]
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# set_property PACKAGE_PIN K22 [get_ports EJTAG_TMS]
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# set_property PACKAGE_PIN K21 [get_ports EJTAG_TDO]
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set_property IOSTANDARD LVCMOS33 [get_ports clk]
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@ -178,12 +178,12 @@ set_property IOSTANDARD LVCMOS33 [get_ports {NAND_DATA[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {NAND_DATA[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {NAND_DATA[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports EJTAG_TRST]
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set_property IOSTANDARD LVCMOS33 [get_ports EJTAG_TCK]
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set_property IOSTANDARD LVCMOS33 [get_ports EJTAG_TDI]
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set_property IOSTANDARD LVCMOS33 [get_ports EJTAG_TMS]
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set_property IOSTANDARD LVCMOS33 [get_ports EJTAG_TDO]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets EJTAG_TCK_IBUF]
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# set_property IOSTANDARD LVCMOS33 [get_ports EJTAG_TRST]
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# set_property IOSTANDARD LVCMOS33 [get_ports EJTAG_TCK]
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# set_property IOSTANDARD LVCMOS33 [get_ports EJTAG_TDI]
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# set_property IOSTANDARD LVCMOS33 [get_ports EJTAG_TMS]
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# set_property IOSTANDARD LVCMOS33 [get_ports EJTAG_TDO]
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# set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets EJTAG_TCK_IBUF]
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create_clock -period 40.000 -name mrxclk_0 -waveform {0.000 20.000} [get_ports mrxclk_0]
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create_clock -period 40.000 -name mtxclk_0 -waveform {0.000 20.000} [get_ports mtxclk_0]
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@ -195,3 +195,9 @@ set_false_path -from [get_clocks clk_out1_clk_pll_33] -to [get_clocks mrxclk_0]
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set_false_path -from [get_clocks clk_out1_clk_pll_33] -to [get_clocks mrxclk_0]
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set_false_path -from [get_clocks clk_out1_clk_pll_33] -to [get_clocks mtxclk_0]
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set_false_path -from [get_clocks clk_out1_clk_pll_33] -to [get_clocks mtxclk_0]
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set_false_path -from [get_clocks -of_objects [get_pins mig_axi/u_mig_axi_32_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT]] -to [get_clocks -of_objects [get_pins clk_pll_33/inst/plle2_adv_inst/CLKOUT0]]
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set_false_path -from [get_clocks -of_objects [get_pins mig_axi/u_mig_axi_32_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT]] -to [get_clocks -of_objects [get_pins clk_pll_33/inst/plle2_adv_inst/CLKOUT1]]
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set_false_path -from [get_clocks -of_objects [get_pins clk_pll_33/inst/plle2_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins mig_axi/u_mig_axi_32_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT]]
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set_false_path -from [get_clocks -of_objects [get_pins clk_pll_33/inst/plle2_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins mig_axi/u_mig_axi_32_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT]]
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