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2alu without overflow

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This commit is contained in:
cxy004 2022-08-05 00:32:08 +08:00
parent f4ac7199c9
commit 9048a4749d
3 changed files with 24 additions and 18 deletions
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4
src/Core/Controller.sv
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@ -41,8 +41,8 @@ module Controller (
assign ctrl.ERET = ~inst[31] & inst[30] & inst[4]; assign ctrl.ERET = ~inst[31] & inst[30] & inst[4];
assign ctrl.OFA = ~inst[26] & ~inst[30] & (~inst[29] & ~inst[31] & ~inst[28] & ~inst[27] & inst[5] & ~inst[0] & ~inst[4] & ~inst[2] & ~inst[3] | inst[29] & ~inst[27] & ~inst[31] & ~inst[28]); assign ctrl.OFA = ~inst[26] & ~inst[30] & (~inst[29] & ~inst[31] & ~inst[28] & ~inst[27] & inst[5] & ~inst[0] & ~inst[4] & ~inst[2] & ~inst[3] | inst[29] & ~inst[27] & ~inst[31] & ~inst[28]);
assign ctrl.ES = ~inst[31] & ~inst[27] & (~inst[30] & ~inst[29] & (~inst[28] & ~inst[26] & (~inst[5] & ~inst[4] & inst[3] & ~inst[2] & inst[1] | inst[4] & (inst[5] | inst[3])) | ~inst[28] & inst[26] & inst[19]) | inst[30] & inst[29]) | inst[31] & ~inst[30]; assign ctrl.ES = ~inst[31] & ~inst[27] & (~inst[30] & ~inst[29] & ~inst[28] & (~inst[26] & (~inst[4] & ~inst[2] & (~inst[5] & inst[3] & inst[1] | inst[5] & ~inst[3] & ~inst[0]) | inst[4] & (inst[5] | inst[3])) | inst[26] & inst[19]) | inst[29] & (inst[30] | ~inst[28] & ~inst[26])) | inst[31] & ~inst[30];
assign ctrl.ET = ~inst[27] & ~inst[26] & (~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & (~inst[5] & ~inst[4] & inst[3] & ~inst[2] & inst[1] | inst[4] & (inst[5] | inst[3])) | inst[30] & inst[29]); assign ctrl.ET = ~inst[27] & ~inst[26] & (~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & (~inst[4] & ~inst[2] & (~inst[5] & inst[3] & inst[1] | inst[5] & ~inst[3] & ~inst[0]) | inst[4] & (inst[5] | inst[3])) | inst[30] & inst[29]);
assign ctrl.ES2 = ~inst[30] & ~inst[28] & ~inst[27] & ~inst[26] & (inst[5] | ~inst[3] & inst[2]) | inst[29]; assign ctrl.ES2 = ~inst[30] & ~inst[28] & ~inst[27] & ~inst[26] & (inst[5] | ~inst[3] & inst[2]) | inst[29];
assign ctrl.ET2 = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & (inst[5] | ~inst[4] & ~inst[3]); assign ctrl.ET2 = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & (inst[5] | ~inst[4] & ~inst[3]);
assign ctrl.DS = ~inst[26] & (~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[4] & inst[3] & ~inst[2] & ~inst[1] | ~inst[31] & ~inst[29] & inst[28]) | ~inst[31] & ~inst[29] & inst[26] & (inst[28] | ~inst[27] & ~inst[19]); assign ctrl.DS = ~inst[26] & (~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[4] & inst[3] & ~inst[2] & ~inst[1] | ~inst[31] & ~inst[29] & inst[28]) | ~inst[31] & ~inst[29] & inst[26] & (inst[28] | ~inst[27] & ~inst[19]);

32
src/Core/Datapath.sv
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@ -137,10 +137,12 @@ module Datapath (
logic E_I0_Overflow; logic E_I0_Overflow;
WCtrl_t E_I0_NowWCtrl; WCtrl_t E_I0_NowWCtrl;
logic E_I0_NowExcValid; logic E_I0_NowExcValid;
logic E_I0_NowExcValidWithoutOF;
logic E_I0_PrevExcValid; logic E_I0_PrevExcValid;
logic [4:0] E_I0_PrevExcCode; logic [4:0] E_I0_PrevExcCode;
logic E_I0_PrevERET; logic E_I0_PrevERET;
logic E_I0_PrevREFILL; logic E_I0_PrevREFILL;
logic E_I0_ExcValidWithoutOF;
word_t E_I1_A; word_t E_I1_A;
word_t E_I1_B; word_t E_I1_B;
@ -209,9 +211,6 @@ module Datapath (
word_t M_I0_B; word_t M_I0_B;
logic M_I0_ALUvalid; logic M_I0_ALUvalid;
logic M_I0_Overflow; logic M_I0_Overflow;
logic M_I0_NowExcValid;
logic M_I0_PrevExcValid;
logic [4:0] M_I0_PrevExcCode;
logic M_I0_DIV_valid; logic M_I0_DIV_valid;
word_t M_I0_DIVH; word_t M_I0_DIVH;
@ -308,7 +307,7 @@ module Datapath (
assign rstD = D_IA_valid & (D.IA.B & D.IA.BGO | D.IA.JR | D.IA.J) & D_IB_valid & D_readygo; assign rstD = D_IA_valid & (D.IA.B & D.IA.BGO | D.IA.JR | D.IA.J) & D_IB_valid & D_readygo;
assign rstM = C0.cpu_exception.ExcValid; assign rstM = C0.cpu_exception.ExcValid;
assign PF_go = ~D.IA_ExcValid & ~D.IB_ExcValid & ~E.I0.ExcValid & ~E_I1_ExcValidWithoutOF assign PF_go = ~D.IA_ExcValid & ~D.IB_ExcValid & ~E_I0_ExcValidWithoutOF & ~E_I1_ExcValidWithoutOF
& (~D_IB_valid | ~D.IA.JR | PF_pcjr[1:0] == 2'b00); & (~D_IB_valid | ~D.IA.JR | PF_pcjr[1:0] == 2'b00);
assign fetch.req = M_exception.ExcValid assign fetch.req = M_exception.ExcValid
| PF_go & (~D_IB_valid & ~fetch.data_ok | (~D.IA.BJRJ | D_readygo) | PF_go & (~D_IB_valid & ~fetch.data_ok | (~D.IA.BJRJ | D_readygo)
@ -621,6 +620,13 @@ module Datapath (
// $display("[%0t] D_go=%d D_IA_go=%d D_IA_pc=0x%0h D_IA_inst=0x%0h D_IB_go=%d D_IB_pc=0x%0h D_IB_inst=0x%0h", // $display("[%0t] D_go=%d D_IA_go=%d D_IA_pc=0x%0h D_IA_inst=0x%0h D_IB_go=%d D_IB_pc=0x%0h D_IB_inst=0x%0h",
// $time, D_go, D_IA_go, D.IA_pc, D.IA_inst, D_IB_go, D.IB_pc, D.IB_inst); // $time, D_go, D_IA_go, D.IA_pc, D.IA_inst, D_IB_go, D.IB_pc, D.IB_inst);
// end // end
// `endif
// `ifdef SIMULATION_VERILATOR
// always_ff @(posedge clk) begin
// $display("<perf> stall = %d, hazard = %d, fetch = %d, mem = %d </perf>",
// 2 - (D.en0 + D.en1), D_IA_Hazard+D_IB_Hazard, {(fetch.req & ~fetch.addr_ok), 1'b0}, {(mem.req & ~mem.addr_ok), 1'b0});
// end
// `endif // `endif
assign D_I0_go = D.A ? D_IB_go : D_IA_go; assign D_I0_go = D.A ? D_IB_go : D_IA_go;
@ -871,11 +877,14 @@ module Datapath (
); );
// E.Exc // E.Exc
assign E_I0_NowExcValid = C0_int & E_valid; assign E_I0_NowExcValidWithoutOF = C0_int & E_valid;
assign E_I0_NowExcValid = E_I0_NowExcValidWithoutOF | E_I0_Overflow & E.I0.OFA;
assign E_I0_ExcValidWithoutOF = E_I0_PrevExcValid | E_I0_NowExcValidWithoutOF;
assign E.I0.ExcValid = E_I0_PrevExcValid | E_I0_NowExcValid; assign E.I0.ExcValid = E_I0_PrevExcValid | E_I0_NowExcValid;
assign E.I0.ERET = E_I0_PrevERET & ~C0_int; assign E.I0.ERET = E_I0_PrevERET & ~C0_int;
assign E.I0.REFILL = E_I0_PrevREFILL & ~C0_int; assign E.I0.REFILL = E_I0_PrevREFILL & ~C0_int;
assign E.I0.ExcCode = C0_int ? 5'h0 : E_I0_PrevExcCode; assign E.I0.ExcCode = C0_int ? 5'h0
: E_I0_PrevExcValid ? E_I0_PrevExcCode : `EXCCODE_OV;
assign E_I1_NowExcValidWithoutOF = C0_int & E_valid | E.I1.MCtrl.MR & E_I1_STRBERROR; assign E_I1_NowExcValidWithoutOF = C0_int & E_valid | E.I1.MCtrl.MR & E_I1_STRBERROR;
assign E_I1_NowExcValid = E_I1_NowExcValidWithoutOF | E_I1_Overflow & E.I1.OFA; assign E_I1_NowExcValid = E_I1_NowExcValidWithoutOF | E_I1_Overflow & E.I1.OFA;
@ -890,7 +899,7 @@ module Datapath (
assign E.I1.BadVAddr = E_I1_PrevExcValid ? E.I1.pc : E.I1.ALUOut; assign E.I1.BadVAddr = E_I1_PrevExcValid ? E.I1.pc : E.I1.ALUOut;
assign E_I0_go = ~E_I0_NowExcValid & (~E.A | ~E_I1_NowExcValid); assign E_I0_go = ~E_I0_NowExcValid & (~E.A | ~E_I1_NowExcValid);
assign E_I1_goWithoutOF = ~E_I1_NowExcValidWithoutOF & (E.A | ~E_I0_NowExcValid); assign E_I1_goWithoutOF = ~E_I1_NowExcValidWithoutOF & (E.A | ~E_I0_NowExcValidWithoutOF);
assign E_I1_go = ~E_I1_NowExcValid & (E.A | ~E_I0_NowExcValid); assign E_I1_go = ~E_I1_NowExcValid & (E.A | ~E_I0_NowExcValid);
// E.I0.ALU // E.I0.ALU
@ -1081,7 +1090,7 @@ module Datapath (
{E.I0.ExcValid, E.I0.ERET, E.I0.REFILL, E.I0.ExcCode, E.I0.CE, E.I0.Delay}, {E.I0.ExcValid, E.I0.ERET, E.I0.REFILL, E.I0.ExcCode, E.I0.CE, E.I0.Delay},
M.en, M.en,
~E_go, ~E_go,
{M_I0_PrevExcValid, M.I0.ERET, M.I0.REFILL, M_I0_PrevExcCode, M.I0.CE, M.I0.Delay} {M.I0.ExcValid, M.I0.ERET, M.I0.REFILL, M.I0.ExcCode, M.I0.CE, M.I0.Delay}
); );
ffenrc #(1) M_I0_ExcCtrl_ff ( ffenrc #(1) M_I0_ExcCtrl_ff (
clk, clk,
@ -1220,9 +1229,6 @@ module Datapath (
{dTLBRefillB, dTLBInvalidB, dTLBModifiedB, dAddressErrorB} {dTLBRefillB, dTLBInvalidB, dTLBModifiedB, dAddressErrorB}
); );
assign M_I0_NowExcValid = M_I0_Overflow & M.I0.OFA;
assign M.I0.ExcValid = M_I0_PrevExcValid | M_I0_NowExcValid;
assign M.I0.ExcCode = M_I0_PrevExcValid ? M_I0_PrevExcCode : `EXCCODE_OV;
assign M_I1_NowExcValid = 0 assign M_I1_NowExcValid = 0
`ifdef ENABLE_TLB `ifdef ENABLE_TLB
| dTLBRefillB | dTLBInvalidB | dTLBModifiedB | dAddressErrorB | dTLBRefillB | dTLBInvalidB | dTLBModifiedB | dAddressErrorB
@ -1242,8 +1248,8 @@ module Datapath (
: dTLBInvalidB ? M.I1.MCtrl.MWR ? `EXCCODE_TLBS : `EXCCODE_TLBL : dTLBInvalidB ? M.I1.MCtrl.MWR ? `EXCCODE_TLBS : `EXCCODE_TLBL
: `EXCCODE_MOD; : `EXCCODE_MOD;
assign M_I0_go = ~M_I0_NowExcValid & (~M.A | ~M_I1_NowExcValid); assign M_I0_go = ~M.A | ~M_I1_NowExcValid;
assign M_I1_go = ~M_I1_NowExcValid & ( M.A | ~M_I0_NowExcValid); assign M_I1_go = ~M_I1_NowExcValid;
assign {M_exception, M_exception_REFILL} = { assign {M_exception, M_exception_REFILL} = {
M.I1.ExcValid | M.I0.ExcValid, M.I1.ExcValid | M.I0.ExcValid,

6
tools/global.txt
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@ -20,9 +20,9 @@
32'b000000??????????0000000000011001 0 0 0 0 1 1 ? ? 0 0 1 0 // MULTU 32'b000000??????????0000000000011001 0 0 0 0 1 1 ? ? 0 0 1 0 // MULTU
32'b000000??????????0000000000011010 0 0 0 0 1 1 ? ? 0 0 1 0 // DIV 32'b000000??????????0000000000011010 0 0 0 0 1 1 ? ? 0 0 1 0 // DIV
32'b000000??????????0000000000011011 0 0 0 0 1 1 ? ? 0 0 1 0 // DIVU 32'b000000??????????0000000000011011 0 0 0 0 1 1 ? ? 0 0 1 0 // DIVU
32'b000000???????????????00000100000 0 0 0 1 0 0 1 1 0 0 1 1 // ADD 32'b000000???????????????00000100000 0 0 0 1 1 1 ? ? 0 0 1 1 // ADD
32'b000000???????????????00000100001 0 0 0 0 0 0 1 1 0 0 1 1 // ADDU 32'b000000???????????????00000100001 0 0 0 0 0 0 1 1 0 0 1 1 // ADDU
32'b000000???????????????00000100010 0 0 0 1 0 0 1 1 0 0 1 1 // SUB 32'b000000???????????????00000100010 0 0 0 1 1 1 ? ? 0 0 1 1 // SUB
32'b000000???????????????00000100011 0 0 0 0 0 0 1 1 0 0 1 1 // SUBU 32'b000000???????????????00000100011 0 0 0 0 0 0 1 1 0 0 1 1 // SUBU
32'b000000???????????????00000100100 0 0 0 0 0 0 1 1 0 0 1 1 // AND 32'b000000???????????????00000100100 0 0 0 0 0 0 1 1 0 0 1 1 // AND
32'b000000???????????????00000100101 0 0 0 0 0 0 1 1 0 0 1 1 // OR 32'b000000???????????????00000100101 0 0 0 0 0 0 1 1 0 0 1 1 // OR
@ -52,7 +52,7 @@
32'b000101?????????????????????????? 0 0 0 0 0 0 0 0 1 1 1 1 // BNE 32'b000101?????????????????????????? 0 0 0 0 0 0 0 0 1 1 1 1 // BNE
32'b000110?????00000???????????????? 0 0 0 0 0 0 0 0 1 0 1 1 // BLEZ 32'b000110?????00000???????????????? 0 0 0 0 0 0 0 0 1 0 1 1 // BLEZ
32'b000111?????00000???????????????? 0 0 0 0 0 0 0 0 1 0 1 1 // BGTZ 32'b000111?????00000???????????????? 0 0 0 0 0 0 0 0 1 0 1 1 // BGTZ
32'b001000?????????????????????????? 0 0 0 1 0 0 1 0 0 0 1 1 // ADDI 32'b001000?????????????????????????? 0 0 0 1 1 0 ? 0 0 0 1 1 // ADDI
32'b001001?????????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // ADDIU 32'b001001?????????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // ADDIU
32'b001010?????????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // SLTI 32'b001010?????????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // SLTI
32'b001011?????????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // SLTIU 32'b001011?????????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // SLTIU