Merge branch 'master' of https://git.builds.ninja/NSCSCC/MIPS
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commit
8de814d26e
@ -56,7 +56,6 @@ module Datapath (
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// F
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logic F_valid;
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logic F_free;
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// Instr Queue
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logic IQ_IA_valid;
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@ -250,13 +249,13 @@ module Datapath (
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assign PF_go = ~D.IA_ExcValid & ~D.IB_ExcValid & ~E.I0.ExcValid & ~E.I1.ExcValid & PF.pc[1:0] == 2'b00;
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assign fetch_i.req = ~F_valid | M_exception.ExcValid
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| PF_go & (~D_IB_valid & ~IQ_valids[3] | (~D.IA.BJRJ | D_readygo)
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| PF_go & (~D_IB_valid & ~IQ_valids[0] | (~D.IA.BJRJ | D_readygo)
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& (rstD
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| ~IQ_valids[3]
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| ~IQ_valids[2] & (F_free | PF.pc[2] | F.pc[2] | D_readygo)
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| ~IQ_valids[1] & (F_free | PF.pc[2] & (F.pc[2] | D_readygo) | F.pc[2] & D_readygo | D_readygo & D_readygo1)
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| ~IQ_valids[0] & (F_free & (PF.pc[2] | F.pc[2] | D_readygo) | PF.pc[2] & (F.pc[2] & D_readygo | D_readygo & D_readygo1) | F.pc[2] & D_readygo & D_readygo1)
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| IQ_valids[0] & (F_free & (PF.pc[2] & (F.pc[2] | D_readygo) | F.pc[2] & D_readygo | D_readygo & D_readygo1) | PF.pc[2] & F.pc[2] & D_readygo & D_readygo1)));
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| ~IQ_valids[0]
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| ~IQ_valids[1] & (~fetch_i.data_ok | PF.pc[2] | F.pc[2] | D_readygo)
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| ~IQ_valids[2] & (~fetch_i.data_ok | PF.pc[2] & (F.pc[2] | D_readygo) | F.pc[2] & D_readygo | D_readygo & D_readygo1)
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| ~IQ_valids[3] & (~fetch_i.data_ok & (PF.pc[2] | D_readygo) | PF.pc[2] & (F.pc[2] & D_readygo | D_readygo & D_readygo1) | F.pc[2] & D_readygo & D_readygo1)
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| IQ_valids[3] & (~fetch_i.data_ok & (PF.pc[2] & D_readygo | D_readygo & D_readygo1) | PF.pc[2] & F.pc[2] & D_readygo & D_readygo1)));
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assign fetch_i.addr = {PF.pc[31:3], 3'b000};
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//---------------------------------------------------------------------------//
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@ -271,13 +270,6 @@ module Datapath (
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F_valid
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);
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ffenr #(1) F_free_ff (
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clk, rst,
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~F.en,
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F.en | fetch_i.data_ok,
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F_free
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);
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ffenr #(32) F_pc_ff (
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clk,
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rst,
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@ -292,27 +284,23 @@ module Datapath (
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// Instr Queue //
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//---------------------------------------------------------------------------//
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InstrQueue InstrQueue (
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Queue #(64) InstrQueue (
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.clk(clk),
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.rst(rst | rstD | rstM),
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.vinA(fetch_i.data_ok | F.pc[1:0] != 2'b00),
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.inA (F.pc[2] ? fetch_i.rdata1 : fetch_i.rdata0),
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.pinA(F.pc),
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.inA ({F.pc[2] ? fetch_i.rdata1 : fetch_i.rdata0, F.pc}),
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.vinB(fetch_i.data_ok & ~F.pc[2]),
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.inB (fetch_i.rdata1),
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.pinB({F.pc[31:3], 3'b100}),
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.inB ({fetch_i.rdata1, F.pc[31:3], 3'b100}),
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.enA (D.en0),
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.voutA(IQ_IA_valid),
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.outA (IQ_IA_inst),
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.poutA(IQ_IA_pc),
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.outA ({IQ_IA_inst, IQ_IA_pc}),
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.enB (D.en1),
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.voutB(IQ_IB_valid),
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.outB (IQ_IB_inst),
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.poutB(IQ_IB_pc),
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.outB ({IQ_IB_inst, IQ_IB_pc}),
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.valids(IQ_valids)
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);
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@ -325,14 +313,14 @@ module Datapath (
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ffenr #(1 + 32 + 32) D_IA_ff (
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clk,
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rst | rstM,
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D.en1 ? {IQ_IA_valid, IQ_IA_pc, IQ_IA_inst} : {D_IB_valid, D.IB_pc, D.IB_inst},
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D.en1 ? {IQ_IA_valid & ~rstD, IQ_IA_pc, IQ_IA_inst} : {D_IB_valid, D.IB_pc, D.IB_inst},
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~D_IA_valid | D_go & E.en,
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{D_IA_valid, D.IA_pc, D.IA_inst}
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);
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ffenr #(1 + 32 + 32) D_IB_ff (
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clk,
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rst | rstM,
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D.en1 ? {IQ_IB_valid, IQ_IB_pc, IQ_IB_inst} : {IQ_IA_valid, IQ_IA_pc, IQ_IA_inst},
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D.en1 ? {IQ_IB_valid & ~rstD, IQ_IB_pc, IQ_IB_inst} : {IQ_IA_valid & ~rstD, IQ_IA_pc, IQ_IA_inst},
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D.en0,
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{D_IB_valid, D.IB_pc, D.IB_inst}
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);
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81
src/Core/Queue.sv
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81
src/Core/Queue.sv
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@ -0,0 +1,81 @@
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`include "defines.svh"
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module Queue #(parameter WIDTH = 64) (
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input clk,
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input rst,
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input logic vinA,
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input logic [WIDTH-1:0] inA,
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input logic vinB,
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input logic [WIDTH-1:0] inB,
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input logic enA,
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output logic voutA,
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output logic [WIDTH-1:0] outA,
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input logic enB,
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output logic voutB,
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output logic [WIDTH-1:0] outB,
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output logic [3:0] valids
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);
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typedef struct packed {
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logic valid;
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logic [WIDTH-1:0] data;
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} item_t;
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logic en1, en2, en3, en4;
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item_t item1, item2, item3, item4;
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item_t next1, next2, next3, next4;
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assign {voutA, outA} = item1.valid ? item1 : {vinA, inA};
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assign {voutB, outB} = item2.valid ? item2 : item1.valid ? {vinA, inA} : {vinB, inB};
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assign en1 = ~enA & ~item1.valid | enA & (~enB | item1.valid);
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assign en2 = ~enA & ~item2.valid | enA & (~enB & item1.valid | item2.valid);
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assign en3 = ~enA & (item1.valid & ~item2.valid | item2.valid & ~item3.valid) | enA & item2.valid & (~enB | item3.valid);
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assign en4 = ~enA & (item2.valid & ~item3.valid | item3.valid & ~item4.valid) | enA & item3.valid & (~enB | item4.valid);
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assign valids = {item4.valid, item3.valid, item2.valid, item1.valid};
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mux4 #(1 + WIDTH) next1_mux (
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{vinB, inB},
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{vinA, inA},
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item3,
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item2,
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{item2.valid & (~enB | item3.valid), (~enB & (~enA | item1.valid) | enB & ~item3.valid & item2.valid)},
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next1
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);
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mux4 #(1 + WIDTH) next2_mux (
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{vinB, inB},
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{vinA, inA},
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item4,
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item3,
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{item3.valid & (~enB | item4.valid), item1.valid & (~enB & (~enA | item2.valid) | enB & item3.valid & ~item4.valid)},
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next2
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);
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mux3 #(1 + WIDTH) next3_mux (
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{vinB, inB},
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{vinA, inA},
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item4,
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{~enB & item4.valid, item2.valid & (~enB & (~enA | item3.valid) | item4.valid)},
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next3
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);
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mux2 #(1 + WIDTH) next4_mux (
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{vinB, inB},
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{vinA, inA},
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~enB & item3.valid & (~enA | item4.valid),
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next4
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);
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ffenr #(1) valid1_ff (clk, rst, next1.valid, en1, item1.valid);
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ffenr #(1) valid2_ff (clk, rst, next2.valid, en2, item2.valid);
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ffenr #(1) valid3_ff (clk, rst, next3.valid, en3, item3.valid);
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ffenr #(1) valid4_ff (clk, rst, next4.valid, en4, item4.valid);
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ffen #(WIDTH) data1_ff (clk, next1.data, en1, item1.data);
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ffen #(WIDTH) data2_ff (clk, next2.data, en2, item2.data);
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ffen #(WIDTH) data3_ff (clk, next3.data, en3, item3.data);
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ffen #(WIDTH) data4_ff (clk, next4.data, en4, item4.data);
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endmodule
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21
tools/iq.sv
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21
tools/iq.sv
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@ -0,0 +1,21 @@
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///------ en3 en4
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6'b000000 0 0
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6'b000001 0 0
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6'b000010 0 0
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6'b000011 0 0
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6'b000100 1 0
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6'b000101 0 0
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6'b000110 0 0
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6'b000111 0 0
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6'b001100 1 1
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6'b001101 0 0
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6'b001110 1 0
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6'b001111 0 0
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6'b011100 0 1
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6'b011101 0 0
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6'b011110 1 1
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6'b011111 1 0
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6'b111100 0 0
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6'b111101 0 0
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6'b111110 1 1
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6'b111111 1 1
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