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fix perf tb

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This commit is contained in:
Paul Pan 2021-08-03 15:28:11 +08:00
parent 2201513f50
commit 86b6dc7a3d
1 changed files with 1 additions and 13 deletions
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14
resources/2021/soc_axi_perf/testbench/tb2.sv
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@ -3,7 +3,7 @@
`define CONFREG_OPEN_TRACE 1'b0 `define CONFREG_OPEN_TRACE 1'b0
`define CONFREG_UART_DISPLAY soc_lite.u_confreg.write_uart_valid `define CONFREG_UART_DISPLAY soc_lite.u_confreg.write_uart_valid
`define CONFREG_UART_DATA soc_lite.u_confreg.write_uart_data `define CONFREG_UART_DATA soc_lite.u_confreg.write_uart_data
`define END_PC 32'hbfc00380 `define END_PC 32'hbfc00100
module tb2_top (); module tb2_top ();
logic resetn; logic resetn;
@ -103,18 +103,6 @@ module tb2_top ();
assign dbg_1_rf_wnum = debug_wb_pc_A ? debug_wb_rf_wnum : debug_wb1_rf_wnum; assign dbg_1_rf_wnum = debug_wb_pc_A ? debug_wb_rf_wnum : debug_wb1_rf_wnum;
assign dbg_1_rf_wdata = debug_wb_pc_A ? debug_wb_rf_wdata : debug_wb1_rf_wdata; assign dbg_1_rf_wdata = debug_wb_pc_A ? debug_wb_rf_wdata : debug_wb1_rf_wdata;
//always @(posedge clk) begin
// if (|dbg_0_rf_wen) begin
// $display("mycpu0 : PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h, wen= %d", dbg_0_pc,
// dbg_0_rf_wnum, dbg_0_rf_wdata, |dbg_0_rf_wen);
// end
// if (|dbg_1_rf_wen) begin
// $display("mycpu1 : PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h, wen= %d", dbg_1_pc,
// dbg_1_rf_wnum, dbg_1_rf_wdata, |dbg_1_rf_wen);
// end
//end
//妯℃嫙涓插彛鎵撳嵃
wire uart_display; wire uart_display;
wire [7:0] uart_data; wire [7:0] uart_data;
assign uart_display = `CONFREG_UART_DISPLAY; assign uart_display = `CONFREG_UART_DISPLAY;